From eb637e76047a3b1d9787b1c75de5da3db2fe8aea Mon Sep 17 00:00:00 2001 From: Delia Burduv Date: Fri, 6 Mar 2020 10:38:20 +0000 Subject: ACLE intrinsics: BFloat16 load intrinsics for AArch32 2020-03-06 Delia Burduv * config/arm/arm_neon.h (vld2_bf16): New. (vld2q_bf16): New. (vld3_bf16): New. (vld3q_bf16): New. (vld4_bf16): New. (vld4q_bf16): New. (vld2_dup_bf16): New. (vld2q_dup_bf16): New. (vld3_dup_bf16): New. (vld3q_dup_bf16): New. (vld4_dup_bf16): New. (vld4q_dup_bf16): New. * config/arm/arm_neon_builtins.def (vld2): Changed to VAR13 and added v4bf, v8bf (vld2_dup): Changed to VAR8 and added v4bf, v8bf (vld3): Changed to VAR13 and added v4bf, v8bf (vld3_dup): Changed to VAR8 and added v4bf, v8bf (vld4): Changed to VAR13 and added v4bf, v8bf (vld4_dup): Changed to VAR8 and added v4bf, v8bf * config/arm/iterators.md (VDXBF2): New iterator. *config/arm/neon.md (neon_vld2): Use new iterators. (neon_vld2_dup): Likewise. (neon_vld3qa): Likewise. (neon_vld3qb): Likewise. (neon_vld3_dup): Likewise. (neon_vld4): Likewise. (neon_vld4qa): Likewise. (neon_vld4qb): Likewise. (neon_vld4_dup): Likewise. (neon_vld2_dupv8bf): New. (neon_vld3_dupv8bf): Likewise. (neon_vld4_dupv8bf): Likewise. * gcc.target/arm/simd/bf16_vldn_1.c: New test. --- gcc/ChangeLog | 36 ++++++ gcc/config/arm/arm_neon.h | 108 +++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 18 +-- gcc/config/arm/iterators.md | 3 + gcc/config/arm/neon.md | 88 ++++++++++++-- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c | 152 ++++++++++++++++++++++++ 7 files changed, 387 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d2a35c..8253442 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,41 @@ 2020-03-06 Delia Burduv + * config/arm/arm_neon.h (vld2_bf16): New. + (vld2q_bf16): New. + (vld3_bf16): New. + (vld3q_bf16): New. + (vld4_bf16): New. + (vld4q_bf16): New. + (vld2_dup_bf16): New. + (vld2q_dup_bf16): New. + (vld3_dup_bf16): New. + (vld3q_dup_bf16): New. + (vld4_dup_bf16): New. + (vld4q_dup_bf16): New. + * config/arm/arm_neon_builtins.def + (vld2): Changed to VAR13 and added v4bf, v8bf + (vld2_dup): Changed to VAR8 and added v4bf, v8bf + (vld3): Changed to VAR13 and added v4bf, v8bf + (vld3_dup): Changed to VAR8 and added v4bf, v8bf + (vld4): Changed to VAR13 and added v4bf, v8bf + (vld4_dup): Changed to VAR8 and added v4bf, v8bf + * config/arm/iterators.md (VDXBF2): New iterator. + *config/arm/neon.md (neon_vld2): Use new iterators. + (neon_vld2_dup): Likewise. + (neon_vld3qa): Likewise. + (neon_vld3qb): Likewise. + (neon_vld3_dup): Likewise. + (neon_vld4): Likewise. + (neon_vld4qa): Likewise. + (neon_vld4qb): Likewise. + (neon_vld4_dup): Likewise. + (neon_vld2_dupv8bf): New. + (neon_vld3_dupv8bf): Likewise. + (neon_vld4_dupv8bf): Likewise. + +2020-03-06 Delia Burduv + * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef. (bfloat16x8x2_t): New typedef. (bfloat16x4x3_t): New typedef. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 4ab79d5..f5ccf18 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -19557,6 +19557,114 @@ vst4q_bf16 (bfloat16_t * __ptr, bfloat16x8x4_t __val) return __builtin_neon_vst4v8bf (__ptr, __bu.__o); } +__extension__ extern __inline bfloat16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld2_bf16 (bfloat16_t const * __ptr) +{ + union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2v4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld2q_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2v8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld3_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3v4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld3q_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3v8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld4_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4v4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld4q_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4v8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld2_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld2q_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld2_dupv8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld3_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld3q_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld3_dupv8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld4_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv4bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + +__extension__ extern __inline bfloat16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld4q_dup_bf16 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_neon_vld4_dupv8bf ((const __builtin_neon_hi *) __ptr); + return __rv.__i; +} + #pragma GCC pop_options #ifdef __cplusplus diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index b73b3e5..34c1945 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -320,29 +320,29 @@ VAR12 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di) VAR12 (STORE1LANE, vst1_lane, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di) -VAR11 (LOAD1, vld2, - v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf) +VAR13 (LOAD1, vld2, + v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf) VAR9 (LOAD1LANE, vld2_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf) -VAR6 (LOAD1, vld2_dup, v8qi, v4hi, v4hf, v2si, v2sf, di) +VAR8 (LOAD1, vld2_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf) VAR13 (STORE1, vst2, v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf) VAR9 (STORE1LANE, vst2_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf) -VAR11 (LOAD1, vld3, - v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf) +VAR13 (LOAD1, vld3, + v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf) VAR9 (LOAD1LANE, vld3_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf) -VAR6 (LOAD1, vld3_dup, v8qi, v4hi, v4hf, v2si, v2sf, di) +VAR8 (LOAD1, vld3_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf) VAR13 (STORE1, vst3, v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf) VAR9 (STORE1LANE, vst3_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf) -VAR11 (LOAD1, vld4, - v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf) +VAR13 (LOAD1, vld4, + v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf) VAR9 (LOAD1LANE, vld4_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf) -VAR6 (LOAD1, vld4_dup, v8qi, v4hi, v4hf, v2si, v2sf, di) +VAR8 (LOAD1, vld4_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf) VAR13 (STORE1, vst4, v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf) VAR9 (STORE1LANE, vst4_lane, diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 8ff3c15..2440852 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -87,6 +87,9 @@ ;; Double-width vector modes plus 64-bit elements, including V4BF. (define_mode_iterator VDXBF [V8QI V4HI V4HF (V4BF "TARGET_BF16_SIMD") V2SI V2SF DI]) +;; Double-width vector modes plus 64-bit elements, V4BF and V8BF. +(define_mode_iterator VDXBF2 [V8QI V4HI V4HF V2SI V2SF DI (V4BF "TARGET_BF16_SIMD") (V8BF ("TARGET_BF16_SIMD"))]) + ;; Double-width vector modes plus 64-bit elements, ;; with V4BFmode added, suitable for moves. (define_mode_iterator VDXMOV [V8QI V4HI V4HF V4BF V2SI V2SF DI]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 250d578..ead3e28 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5428,7 +5428,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld2" [(set (match_operand:TI 0 "s_register_operand" "=w") (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD2))] "TARGET_NEON" { @@ -5453,7 +5453,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld2" [(set (match_operand:OI 0 "s_register_operand" "=w") (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD2))] "TARGET_NEON" "vld2.\t%h0, %A1" @@ -5516,7 +5516,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld2_dup" [(set (match_operand:TI 0 "s_register_operand" "=w") (unspec:TI [(match_operand: 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD2_DUP))] "TARGET_NEON" { @@ -5531,6 +5531,27 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_load1_1reg")))] ) +(define_insn "neon_vld2_dupv8bf" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(match_operand:V2BF 1 "neon_struct_operand" "Um") + (unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_DUP))] + "TARGET_BF16_SIMD" + { + rtx ops[5]; + int tabbase = REGNO (operands[0]); + + ops[4] = operands[1]; + ops[0] = gen_rtx_REG (V4BFmode, tabbase); + ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2); + ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4); + ops[3] = gen_rtx_REG (V4BFmode, tabbase + 6); + output_asm_insn ("vld2.16\t{%P0, %P1, %P2, %P3}, %A4", ops); + return ""; + } + [(set_attr "type" "neon_load2_all_lanes_q")] +) + (define_expand "vec_store_lanesti" [(set (match_operand:TI 0 "neon_struct_operand") (unspec:TI [(match_operand:TI 1 "s_register_operand") @@ -5637,7 +5658,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld3" [(set (match_operand:EI 0 "s_register_operand" "=w") (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD3))] "TARGET_NEON" { @@ -5665,7 +5686,7 @@ if (BYTES_BIG_ENDIAN) (define_expand "neon_vld3" [(match_operand:CI 0 "s_register_operand") (match_operand:CI 1 "neon_struct_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_NEON" { rtx mem; @@ -5680,7 +5701,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld3qa" [(set (match_operand:CI 0 "s_register_operand" "=w") (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD3A))] "TARGET_NEON" { @@ -5700,7 +5721,7 @@ if (BYTES_BIG_ENDIAN) [(set (match_operand:CI 0 "s_register_operand" "=w") (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") (match_operand:CI 2 "s_register_operand" "0") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD3B))] "TARGET_NEON" { @@ -5777,7 +5798,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld3_dup" [(set (match_operand:EI 0 "s_register_operand" "=w") (unspec:EI [(match_operand: 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD3_DUP))] "TARGET_NEON" { @@ -5800,6 +5821,26 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_load3_all_lanes") (const_string "neon_load1_1reg")))]) +(define_insn "neon_vld3_dupv8bf" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(match_operand:V2BF 1 "neon_struct_operand" "Um") + (unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_DUP))] + "TARGET_BF16_SIMD" + { + rtx ops[4]; + int tabbase = REGNO (operands[0]); + + ops[3] = operands[1]; + ops[0] = gen_rtx_REG (V4BFmode, tabbase); + ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2); + ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4); + output_asm_insn ("vld3.16\t{%P0[], %P1[], %P2[]}, %A3", ops); + return ""; + } + [(set_attr "type" "neon_load3_all_lanes_q")] +) + (define_expand "vec_store_lanesei" [(set (match_operand:EI 0 "neon_struct_operand") (unspec:EI [(match_operand:EI 1 "s_register_operand") @@ -5955,7 +5996,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld4" [(set (match_operand:OI 0 "s_register_operand" "=w") (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD4))] "TARGET_NEON" { @@ -5983,7 +6024,7 @@ if (BYTES_BIG_ENDIAN) (define_expand "neon_vld4" [(match_operand:XI 0 "s_register_operand") (match_operand:XI 1 "neon_struct_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_NEON" { rtx mem; @@ -5998,7 +6039,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld4qa" [(set (match_operand:XI 0 "s_register_operand" "=w") (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD4A))] "TARGET_NEON" { @@ -6019,7 +6060,7 @@ if (BYTES_BIG_ENDIAN) [(set (match_operand:XI 0 "s_register_operand" "=w") (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") (match_operand:XI 2 "s_register_operand" "0") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD4B))] "TARGET_NEON" { @@ -6099,7 +6140,7 @@ if (BYTES_BIG_ENDIAN) (define_insn "neon_vld4_dup" [(set (match_operand:OI 0 "s_register_operand" "=w") (unspec:OI [(match_operand: 1 "neon_struct_operand" "Um") - (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + (unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VLD4_DUP))] "TARGET_NEON" { @@ -6125,6 +6166,27 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_load1_1reg")))] ) +(define_insn "neon_vld4_dupv8bf" + [(set (match_operand:XI 0 "s_register_operand" "=w") + (unspec:XI [(match_operand:V2BF 1 "neon_struct_operand" "Um") + (unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_DUP))] + "TARGET_BF16_SIMD" + { + rtx ops[5]; + int tabbase = REGNO (operands[0]); + + ops[4] = operands[1]; + ops[0] = gen_rtx_REG (V4BFmode, tabbase); + ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2); + ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4); + ops[3] = gen_rtx_REG (V4BFmode, tabbase + 6); + output_asm_insn ("vld4.16\t{%P0[], %P1[], %P2[], %P3[]}, %A4", ops); + return ""; + } + [(set_attr "type" "neon_load4_all_lanes_q")] +) + (define_expand "vec_store_lanesoi" [(set (match_operand:OI 0 "neon_struct_operand") (unspec:OI [(match_operand:OI 1 "s_register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b7bbb47..13da5a8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2020-03-06 Delia Burduv + * gcc.target/arm/simd/bf16_vldn_1.c: New test. + +2020-03-06 Delia Burduv + * gcc.target/arm/simd/bf16_vstn_1.c: New test. 2020-03-06 Kito Cheng diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c new file mode 100644 index 0000000..222e7af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c @@ -0,0 +1,152 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon.h" + + +/* +**test_vld2_bf16: +** ... +** vld2.16 {d0-d1}, \[r0\] +** bx lr +*/ +bfloat16x4x2_t +test_vld2_bf16 (bfloat16_t * ptr) +{ + return vld2_bf16 (ptr); +} + +/* +**test_vld2q_bf16: +** ... +** vld2.16 {d0-d3}, \[r0\] +** bx lr +*/ +bfloat16x8x2_t +test_vld2q_bf16 (bfloat16_t * ptr) +{ + return vld2q_bf16 (ptr); +} + +/* +**test_vld2_dup_bf16: +** ... +** vld2.16 {d0\[\], d1\[\]}, \[r0\] +** bx lr +*/ +bfloat16x4x2_t +test_vld2_dup_bf16 (bfloat16_t * ptr) +{ + return vld2_dup_bf16 (ptr); +} + +/* +**test_vld2q_dup_bf16: +** ... +** vld2.16 {d0, d1, d2, d3}, \[r0\] +** bx lr +*/ +bfloat16x8x2_t +test_vld2q_dup_bf16 (bfloat16_t * ptr) +{ + return vld2q_dup_bf16 (ptr); +} + +/* +**test_vld3_bf16: +** ... +** vld3.16 {d0-d2}, \[r0\] +** bx lr +*/ +bfloat16x4x3_t +test_vld3_bf16 (bfloat16_t * ptr) +{ + return vld3_bf16 (ptr); +} + +/* +**test_vld3q_bf16: +** ... +** vld3.16 {d1, d3, d5}, \[r0\] +** bx lr +*/ +bfloat16x8x3_t +test_vld3q_bf16 (bfloat16_t * ptr) +{ + return vld3q_bf16 (ptr); +} + +/* +**test_vld3_dup_bf16: +** ... +** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\] +** bx lr +*/ +bfloat16x4x3_t +test_vld3_dup_bf16 (bfloat16_t * ptr) +{ + return vld3_dup_bf16 (ptr); +} + +/* +**test_vld3q_dup_bf16: +** ... +** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\] +** bx lr +*/ +bfloat16x8x3_t +test_vld3q_dup_bf16 (bfloat16_t * ptr) +{ + return vld3q_dup_bf16 (ptr); +} + +/* +**test_vld4_bf16: +** ... +** vld4.16 {d0-d3}, \[r0\] +** bx lr +*/ +bfloat16x4x4_t +test_vld4_bf16 (bfloat16_t * ptr) +{ + return vld4_bf16 (ptr); +} + +/* +**test_vld4q_bf16: +** ... +** vld4.16 {d1, d3, d5, d7}, \[r0\] +** bx lr +*/ +bfloat16x8x4_t +test_vld4q_bf16 (bfloat16_t * ptr) +{ + return vld4q_bf16 (ptr); +} + +/* +**test_vld4_dup_bf16: +** ... +** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\] +** bx lr +*/ +bfloat16x4x4_t +test_vld4_dup_bf16 (bfloat16_t * ptr) +{ + return vld4_dup_bf16 (ptr); +} + +/* +**test_vld4q_dup_bf16: +** ... +** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\] +** bx lr +*/ +bfloat16x8x4_t +test_vld4q_dup_bf16 (bfloat16_t * ptr) +{ + return vld4q_dup_bf16 (ptr); +} -- cgit v1.1 From 068fe0a9e9910ea795229d65b094757633e84524 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Fri, 6 Mar 2020 12:44:27 +0100 Subject: Add missing ChangeLog entries --- gcc/ChangeLog | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8253442..8436483 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -93,6 +93,11 @@ (UNSPEC_BFCVT): New UNSPEC. * config/arm/types.md (bf_cvt): New type. +2020-03-06 Andreas Krebbel + + * config/s390/s390.md ("tabort"): Get rid of two consecutive + blanks in format string. + 2020-03-05 H.J. Lu PR target/89229 @@ -204,6 +209,39 @@ * rs6000.c (rs6000_disable_incompatible_switches): Add table entry for OPTION_MASK_ALTIVEC. +2020-03-04 Andreas Krebbel + + * config.gcc: Include the glibc-stdint.h header for zTPF. + +2020-03-04 Andreas Krebbel + + * config/s390/s390.c (s390_secondary_memory_needed): Disallow + direct FPR-GPR copies. + (s390_register_info_gprtofpr): Disallow GPR content to be saved in + FPRs. + +2020-03-04 Andreas Krebbel + + * config/s390/s390.c (s390_emit_prologue): Specify the 2 new + operands to the prologue_tpf expander. + (s390_emit_epilogue): Likewise. + (s390_option_override_internal): Do error checking and setup for + the new options. + * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK) + (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET) + (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET) + (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions. + * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new + operands for the check flag and the branch target. + * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check") + ("mtpf-trace-hook-prologue-target") + ("mtpf-trace-hook-epilogue-check") + ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New + options. + * doc/invoke.texi: Document -mtpf-trace-skip option. The other + options are for debugging purposes and will not be documented + here. + 2020-03-04 Jakub Jelinek PR debug/93888 -- cgit v1.1 From 4b62b3960ec405c6ed226a7763e0905c434cb2bb Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Fri, 6 Mar 2020 16:36:23 +0200 Subject: arc: Update tumaddsidi4 test. The test is using -O1 and, the macu instruction is generated by the combiner and not in the expand step. My previous "arc: Improve code gen for 64bit add/sub operations." is actually splitting the 64-bit add in the expand, leading to the impossibility to match the multiply and accumulate on 64 bit datum by the combiner, hence, the error. This patch is stepping up the optimization level which will generate the macu instruction at the expand time. xxxx-xx-xx Claudiu Zissulescu * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. Signed-off-by: Claudiu Zissulescu --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 13da5a8..ea9bc42 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-06 Claudiu Zissulescu + + * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. + 2020-03-06 Delia Burduv * gcc.target/arm/simd/bf16_vldn_1.c: New test. diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c index d5dc294..0298a24 100644 --- a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c +++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy -w" } */ +/* { dg-options "-mcpu=archs -O2 -mmpy-option=plus_dmpy -w" } */ /* Check how we generate umaddsidi4 patterns. */ long a; @@ -11,4 +11,4 @@ void fn1(void) b = d * (long long)c + a; } -/* { dg-final { scan-assembler "macu 0,r" } } */ +/* { dg-final { scan-assembler "macu" } } */ -- cgit v1.1 From e6ce69cae5059dfd715edd4e26653c23baf4cb0f Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Fri, 6 Mar 2020 08:34:01 -0700 Subject: Avoid putting a REG_NOTE on anything other than an INSN in haifa-sched.c PR rtl-optimization/93996 * haifa-sched.c (remove_notes): Be more careful when adding REG_SAVE_NOTE. --- gcc/ChangeLog | 7 +++++++ gcc/haifa-sched.c | 9 +++++++++ 2 files changed, 16 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8436483..e38af8e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-06 Andrew Pinski + Jeff Law + + PR rtl-optimization/93996 + * haifa-sched.c (remove_notes): Be more careful when adding + REG_SAVE_NOTE. + 2020-03-06 Delia Burduv * config/arm/arm_neon.h (vld2_bf16): New. diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index 1d3de7b..80687fb 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -4239,6 +4239,15 @@ remove_notes (rtx_insn *head, rtx_insn *tail) if (insn != tail) { remove_insn (insn); + /* If an insn was split just before the EPILOGUE_BEG note and + that split created new basic blocks, we could have a + BASIC_BLOCK note here. Safely advance over it in that case + and assert that we land on a real insn. */ + if (NOTE_P (next) + && NOTE_KIND (next) == NOTE_INSN_BASIC_BLOCK + && next != next_tail) + next = NEXT_INSN (next); + gcc_assert (INSN_P (next)); add_reg_note (next, REG_SAVE_NOTE, GEN_INT (NOTE_INSN_EPILOGUE_BEG)); break; -- cgit v1.1 From 3dcf51ad7b0a9cacba1a056755c16cc1cf7984ee Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Thu, 5 Mar 2020 20:41:08 -0500 Subject: rs6000: Correct logic to disable NO_SUM_IN_TOC and NO_FP_IN_TOC [PR94065] aix61.h, aix71.h and aix72.h intends to prevent SUM_IN_TOC and FP_IN_TOC when cmodel=large. This patch defines the variables associated with the target options to 1 to _enable_ NO_SUM_IN_TOC and enable NO_FP_IN_TOC. Bootstrapped on powerpc-ibm-aix7.2.0.0 2020-03-06 David Edelsohn PR target/94065 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for cmodel=large. (TARGET_NO_FP_IN_TOC): Same. * config/rs6000/aix71.h: Same. * config/rs6000/aix72.h: Same. --- gcc/ChangeLog | 9 +++++++++ gcc/config/rs6000/aix61.h | 4 ++-- gcc/config/rs6000/aix71.h | 4 ++-- gcc/config/rs6000/aix72.h | 4 ++-- 4 files changed, 15 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e38af8e..843c49e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-06 David Edelsohn + + PR target/94065 + * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for + cmodel=large. + (TARGET_NO_FP_IN_TOC): Same. + * config/rs6000/aix71.h: Same. + * config/rs6000/aix72.h: Same. + 2020-03-06 Andrew Pinski Jeff Law diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h index 0b14f7e..13c3e09 100644 --- a/gcc/config/rs6000/aix61.h +++ b/gcc/config/rs6000/aix61.h @@ -49,8 +49,8 @@ do { \ } \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + TARGET_NO_FP_IN_TOC = 1; \ + TARGET_NO_SUM_IN_TOC = 1; \ } \ if (rs6000_current_cmodel == CMODEL_MEDIUM) \ { \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index b93d257..3be0cbe 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -49,8 +49,8 @@ do { \ } \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + TARGET_NO_FP_IN_TOC = 1; \ + TARGET_NO_SUM_IN_TOC = 1; \ } \ if (rs6000_current_cmodel == CMODEL_MEDIUM) \ { \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index f5e4d3e..292e67f 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -49,8 +49,8 @@ do { \ } \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + TARGET_NO_FP_IN_TOC = 1; \ + TARGET_NO_SUM_IN_TOC = 1; \ } \ if (rs6000_current_cmodel == CMODEL_MEDIUM) \ { \ -- cgit v1.1 From 4a5c938bbfd4586f16ff0dfde00970c2a1b0f636 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Fri, 6 Mar 2020 16:21:33 +0000 Subject: [AArch64][SVE] Add missing movprfx attribute to some ternary arithmetic patterns The two affected SVE2 patterns in this patch output a movprfx'ed instruction in their second alternative but don't set the "movprfx" attribute, which will result in the wrong instruction length being assumed by the midend. This patch fixes that in the same way as the other SVE patterns in the backend. Bootstrapped and tested on aarch64-none-linux-gnu. 2020-03-06 Kyrylo Tkachov * config/aarch64/aarch64-sve2.md (@aarch64_sve_: Specify movprfx attribute. (@aarch64_sve__lane_): Likewise. --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64-sve2.md | 2 ++ 2 files changed, 8 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 843c49e..957c4cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-06 Kyrylo Tkachov + + * config/aarch64/aarch64-sve2.md (@aarch64_sve_: + Specify movprfx attribute. + (@aarch64_sve__lane_): Likewise. + 2020-03-06 David Edelsohn PR target/94065 diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index f82e60e..e18b9fe 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -690,6 +690,7 @@ "@ \t%0., %2., %3. movprfx\t%0, %1\;\t%0., %2., %3." + [(set_attr "movprfx" "*,yes")] ) (define_insn "@aarch64_sve__lane_" @@ -706,6 +707,7 @@ "@ \t%0., %2., %3.[%4] movprfx\t%0, %1\;\t%0., %2., %3.[%4]" + [(set_attr "movprfx" "*,yes")] ) ;; ------------------------------------------------------------------------- -- cgit v1.1 From 3e5c062e96c11a6eaef1cbf94b5992391a850dbf Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Fri, 6 Mar 2020 18:19:46 +0000 Subject: [AArch64] Fix lane specifier syntax The syntax for lane specifiers uses a vector element rather than a vector: fmls v0.2s, v1.2s, v1.s[1] // rather than v1.2s[1] Fix all the lane specifiers to use Vetype which uses the correct element type. gcc/ * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. (aarch64_mla_elt_): Likewise. (aarch64_mls_elt): Likewise. (aarch64_mls_elt_): Likewise. (aarch64_fma4_elt): Likewise. (aarch64_fma4_elt_): Likewise. (aarch64_fma4_elt_to_64v2df): Likewise. (aarch64_fnma4_elt): Likewise. (aarch64_fnma4_elt_): Likewise. (aarch64_fnma4_elt_to_64v2df): Likewise. testsuite/ * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise. * gcc.target/aarch64/mla_intrinsic_1.c: Likewise. * gcc.target/aarch64/mls_intrinsic_1.c: Likewise. --- gcc/ChangeLog | 13 +++++++++++++ gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++---------- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c | 6 +++--- gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c | 6 +++--- gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c | 4 ++-- 7 files changed, 40 insertions(+), 20 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 957c4cc..1cb6694 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2020-03-06 Wilco Dijkstra + + * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. + (aarch64_mla_elt_): Likewise. + (aarch64_mls_elt): Likewise. + (aarch64_mls_elt_): Likewise. + (aarch64_fma4_elt): Likewise. + (aarch64_fma4_elt_): Likewise. + (aarch64_fma4_elt_to_64v2df): Likewise. + (aarch64_fnma4_elt): Likewise. + (aarch64_fnma4_elt_): Likewise. + (aarch64_fnma4_elt_to_64v2df): Likewise. + 2020-03-06 Kyrylo Tkachov * config/aarch64/aarch64-sve2.md (@aarch64_sve_: diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 035f316..e5cf4e4 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1350,7 +1350,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mla\t%0., %3., %1.[%2]"; + return "mla\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1368,7 +1368,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mla\t%0., %3., %1.[%2]"; + return "mla\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1408,7 +1408,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mls\t%0., %3., %1.[%2]"; + return "mls\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1426,7 +1426,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mls\t%0., %3., %1.[%2]"; + return "mls\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -2003,7 +2003,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmla\\t%0., %3., %1.[%2]"; + return "fmla\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2020,7 +2020,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmla\\t%0., %3., %1.[%2]"; + return "fmla\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2048,7 +2048,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2])); - return "fmla\\t%0.2d, %3.2d, %1.2d[%2]"; + return "fmla\\t%0.2d, %3.2d, %1.d[%2]"; } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) @@ -2077,7 +2077,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmls\\t%0., %3., %1.[%2]"; + return "fmls\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2095,7 +2095,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmls\\t%0., %3., %1.[%2]"; + return "fmls\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2125,7 +2125,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2])); - return "fmls\\t%0.2d, %3.2d, %1.2d[%2]"; + return "fmls\\t%0.2d, %3.2d, %1.d[%2]"; } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ea9bc42..59c9988 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-06 Wilco Dijkstra + + * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. + * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise. + * gcc.target/aarch64/mla_intrinsic_1.c: Likewise. + * gcc.target/aarch64/mls_intrinsic_1.c: Likewise. + 2020-03-06 Claudiu Zissulescu * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. diff --git a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c index 5b34882..59ad41e 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c @@ -98,11 +98,11 @@ main (int argc, char **argv) /* vfma_laneq_f32. vfma_lane_f32. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfmaq_lane_f32. vfmaq_laneq_f32. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfma_lane_f64. */ /* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */ @@ -110,6 +110,6 @@ main (int argc, char **argv) /* vfmaq_lane_f64. vfma_laneq_f64. vfmaq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c index 6c194a0..2d5a3d3 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c @@ -99,11 +99,11 @@ main (int argc, char **argv) /* vfms_laneq_f32. vfms_lane_f32. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfmsq_lane_f32. vfmsq_laneq_f32. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfms_lane_f64. */ /* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */ @@ -111,6 +111,6 @@ main (int argc, char **argv) /* vfmsq_lane_f64. vfms_laneq_f64. vfmsq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c index 4bdfac7..46b3c78 100644 --- a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c @@ -78,6 +78,6 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */ -/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c index 4b13faf..e01a4f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c @@ -83,6 +83,6 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */ -/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */ -- cgit v1.1 From 0b8393221177617f19e7c5c5c692b8c59f85fffb Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Fri, 6 Mar 2020 18:29:02 +0000 Subject: [AArch64] Use intrinsics for widening multiplies (PR91598) Inline assembler instructions don't have latency info and the scheduler does not attempt to schedule them at all - it does not even honor latencies of asm source operands. As a result, SIMD intrinsics which are implemented using inline assembler perform very poorly, particularly on in-order cores. Add new patterns and intrinsics for widening multiplies, which results in a 63% speedup for the example in the PR, thus fixing the reported regression. gcc/ PR target/91598 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define. * config/aarch64/aarch64-simd.md (aarch64_vec_mult_lane): Add new insn for widening lane mul. (aarch64_vec_mlal_lane): Likewise. * config/aarch64/aarch64-simd-builtins.def: Add intrinsics. * config/aarch64/arm_neon.h: (vmlal_lane_s16): Expand using intrinsics rather than inline asm. (vmlal_lane_u16): Likewise. (vmlal_lane_s32): Likewise. (vmlal_lane_u32): Likewise. (vmlal_laneq_s16): Likewise. (vmlal_laneq_u16): Likewise. (vmlal_laneq_s32): Likewise. (vmlal_laneq_u32): Likewise. (vmull_lane_s16): Likewise. (vmull_lane_u16): Likewise. (vmull_lane_s32): Likewise. (vmull_lane_u32): Likewise. (vmull_laneq_s16): Likewise. (vmull_laneq_u16): Likewise. (vmull_laneq_s32): Likewise. (vmull_laneq_u32): Likewise. * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul. (Qlane): Likewise. --- gcc/ChangeLog | 28 +++ gcc/config/aarch64/aarch64-builtins.c | 5 + gcc/config/aarch64/aarch64-simd-builtins.def | 9 + gcc/config/aarch64/aarch64-simd.md | 40 ++++ gcc/config/aarch64/arm_neon.h | 296 +++++++++------------------ gcc/config/aarch64/iterators.md | 7 + 6 files changed, 185 insertions(+), 200 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1cb6694..2bc6f39 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,33 @@ 2020-03-06 Wilco Dijkstra + PR target/91598 + * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define. + * config/aarch64/aarch64-simd.md + (aarch64_vec_mult_lane): Add new insn for widening lane mul. + (aarch64_vec_mlal_lane): Likewise. + * config/aarch64/aarch64-simd-builtins.def: Add intrinsics. + * config/aarch64/arm_neon.h: + (vmlal_lane_s16): Expand using intrinsics rather than inline asm. + (vmlal_lane_u16): Likewise. + (vmlal_lane_s32): Likewise. + (vmlal_lane_u32): Likewise. + (vmlal_laneq_s16): Likewise. + (vmlal_laneq_u16): Likewise. + (vmlal_laneq_s32): Likewise. + (vmlal_laneq_u32): Likewise. + (vmull_lane_s16): Likewise. + (vmull_lane_u16): Likewise. + (vmull_lane_s32): Likewise. + (vmull_lane_u32): Likewise. + (vmull_laneq_s16): Likewise. + (vmull_laneq_u16): Likewise. + (vmull_laneq_s32): Likewise. + (vmull_laneq_u32): Likewise. + * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul. + (Qlane): Likewise. + +2020-03-06 Wilco Dijkstra + * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. (aarch64_mla_elt_): Likewise. (aarch64_mls_elt): Likewise. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 9c9c6d8..5744e68 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -175,6 +175,11 @@ aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_unsigned, qualifier_unsigned }; #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers) static enum aarch64_type_qualifiers +aarch64_types_ternopu_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned, qualifier_lane_index }; +#define TYPES_TERNOPU_LANE (aarch64_types_ternopu_lane_qualifiers) +static enum aarch64_type_qualifiers aarch64_types_ternopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, qualifier_immediate }; diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index cc0bd0e..332a0b6 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -191,6 +191,15 @@ BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10) BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10) + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0) + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0) + BUILTIN_VSD_HSI (BINOP, sqdmull, 0) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e5cf4e4..24a11fb 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1892,6 +1892,46 @@ } ) +;; vmull_lane_s16 intrinsics +(define_insn "aarch64_vec_mult_lane" + [(set (match_operand: 0 "register_operand" "=w") + (mult: + (ANY_EXTEND: + (match_operand: 1 "register_operand" "w")) + (ANY_EXTEND: + (vec_duplicate: + (vec_select: + (match_operand:VDQHS 2 "register_operand" "") + (parallel [(match_operand:SI 3 "immediate_operand" "i")]))))))] + "TARGET_SIMD" + { + operands[3] = aarch64_endian_lane_rtx (mode, INTVAL (operands[3])); + return "mull\\t%0., %1., %2.[%3]"; + } + [(set_attr "type" "neon_mul__scalar_long")] +) + +;; vmlal_lane_s16 intrinsics +(define_insn "aarch64_vec_mlal_lane" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (mult: + (ANY_EXTEND: + (match_operand: 2 "register_operand" "w")) + (ANY_EXTEND: + (vec_duplicate: + (vec_select: + (match_operand:VDQHS 3 "register_operand" "") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))))) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (mode, INTVAL (operands[4])); + return "mlal\\t%0., %2., %3.[%4]"; + } + [(set_attr "type" "neon_mla__scalar_long")] +) + ;; FP vector operations. ;; AArch64 AdvSIMD supports single-precision (32-bit) and ;; double-precision (64-bit) floating-point data types and arithmetic as diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index cc4ce76..50f8b23 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -7700,117 +7700,61 @@ vmlal_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) return __result; } -#define vmlal_lane_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x4_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_lane_s16 (int32x4_t __acc, int16x4_t __a, int16x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_smlal_lane_v4hi (__acc, __a, __b, __c); +} -#define vmlal_lane_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x2_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_lane_s32 (int64x2_t __acc, int32x2_t __a, int32x2_t __b, const int __c) +{ + return __builtin_aarch64_vec_smlal_lane_v2si (__acc, __a, __b, __c); +} -#define vmlal_lane_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x4_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_lane_u16 (uint32x4_t __acc, uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_umlal_lane_v4hi_uuuus (__acc, __a, __b, __c); +} -#define vmlal_lane_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x2_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_lane_u32 (uint64x2_t __acc, uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return __builtin_aarch64_vec_umlal_lane_v2si_uuuus (__acc, __a, __b, __c); +} -#define vmlal_laneq_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x8_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_laneq_s16 (int32x4_t __acc, int16x4_t __a, int16x8_t __b, const int __c) +{ + return __builtin_aarch64_vec_smlal_laneq_v4hi (__acc, __a, __b, __c); +} -#define vmlal_laneq_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x4_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_laneq_s32 (int64x2_t __acc, int32x2_t __a, int32x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_smlal_laneq_v2si (__acc, __a, __b, __c); +} -#define vmlal_laneq_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x8_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_laneq_u16 (uint32x4_t __acc, uint16x4_t __a, uint16x8_t __b, const int __c) +{ + return __builtin_aarch64_vec_umlal_laneq_v4hi_uuuus (__acc, __a, __b, __c); +} -#define vmlal_laneq_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x4_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_laneq_u32 (uint64x2_t __acc, uint32x2_t __a, uint32x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_umlal_laneq_v2si_uuuus (__acc, __a, __b, __c); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -9289,109 +9233,61 @@ vmull_high_u32 (uint32x4_t __a, uint32x4_t __b) return __builtin_aarch64_vec_widen_umult_hi_v4si_uuu (__a, __b); } -#define vmull_lane_s16(a, b, c) \ - __extension__ \ - ({ \ - int16x4_t b_ = (b); \ - int16x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smull %0.4s,%1.4h,%2.h[%3]" \ - : "=w"(result) \ - : "w"(a_), "x"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_smult_lane_v4hi (__a, __b, __c); +} -#define vmull_lane_s32(a, b, c) \ - __extension__ \ - ({ \ - int32x2_t b_ = (b); \ - int32x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smull %0.2d,%1.2s,%2.s[%3]" \ - : "=w"(result) \ - : "w"(a_), "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) +{ + return __builtin_aarch64_vec_smult_lane_v2si (__a, __b, __c); +} -#define vmull_lane_u16(a, b, c) \ - __extension__ \ - ({ \ - uint16x4_t b_ = (b); \ - uint16x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umull %0.4s,%1.4h,%2.h[%3]" \ - : "=w"(result) \ - : "w"(a_), "x"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_umult_lane_v4hi_uuus (__a, __b, __c); +} -#define vmull_lane_u32(a, b, c) \ - __extension__ \ - ({ \ - uint32x2_t b_ = (b); \ - uint32x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umull %0.2d, %1.2s, %2.s[%3]" \ - : "=w"(result) \ - : "w"(a_), "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c) +{ + return __builtin_aarch64_vec_umult_lane_v2si_uuus (__a, __b, __c); +} -#define vmull_laneq_s16(a, b, c) \ - __extension__ \ - ({ \ - int16x8_t b_ = (b); \ - int16x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smull %0.4s, %1.4h, %2.h[%3]" \ - : "=w"(result) \ - : "w"(a_), "x"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c) +{ + return __builtin_aarch64_vec_smult_laneq_v4hi (__a, __b, __c); +} -#define vmull_laneq_s32(a, b, c) \ - __extension__ \ - ({ \ - int32x4_t b_ = (b); \ - int32x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smull %0.2d, %1.2s, %2.s[%3]" \ - : "=w"(result) \ - : "w"(a_), "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_smult_laneq_v2si (__a, __b, __c); +} -#define vmull_laneq_u16(a, b, c) \ - __extension__ \ - ({ \ - uint16x8_t b_ = (b); \ - uint16x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umull %0.4s, %1.4h, %2.h[%3]" \ - : "=w"(result) \ - : "w"(a_), "x"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_laneq_u16 (uint16x4_t __a, uint16x8_t __b, const int __c) +{ + return __builtin_aarch64_vec_umult_laneq_v4hi_uuus (__a, __b, __c); +} -#define vmull_laneq_u32(a, b, c) \ - __extension__ \ - ({ \ - uint32x4_t b_ = (b); \ - uint32x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umull %0.2d, %1.2s, %2.s[%3]" \ - : "=w"(result) \ - : "w"(a_), "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_laneq_u32 (uint32x2_t __a, uint32x4_t __b, const int __c) +{ + return __builtin_aarch64_vec_umult_laneq_v2si_uuus (__a, __b, __c); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index b56a050..95fa3e4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -986,6 +986,13 @@ (V4SF "4s") (V2DF "2d") (V4HF "4h") (V8HF "8h")]) +;; Map mode to type used in widening multiplies. +(define_mode_attr Vcondtype [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")]) + +;; Map lane mode to name +(define_mode_attr Qlane [(V4HI "_v4hi") (V8HI "q_v4hi") + (V2SI "_v2si") (V4SI "q_v2si")]) + (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") (V4SI "32") (V2DI "64")]) -- cgit v1.1 From 191bcd0f30dd37dec773efb0125afdcae9bd90ef Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 6 Mar 2020 10:51:26 -0800 Subject: Fix mangling ICE [PR94027] PR c++/94027 * mangle.c (find_substitution): Don't call same_type_p on template args that cannot match. Now same_type_p rejects argument packs, we need to be more careful calling it with template argument vector contents. The mangler needs to do some comparisons to find the special substitutions. While that code looks a little ugly, this seems the smallest fix. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/mangle.c | 4 +++- gcc/testsuite/g++.dg/pr94027.C | 22 ++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/pr94027.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index f01563e..98640a6 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-06 Nathan Sidwell + + PR c++/94027 + * mangle.c (find_substitution): Don't call same_type_p on template + args that cannot match. + 2020-03-04 Martin Sebor PR c++/90938 diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c index a0e888f..1fc78bf 100644 --- a/gcc/cp/mangle.c +++ b/gcc/cp/mangle.c @@ -628,6 +628,8 @@ find_substitution (tree node) { tree args = CLASSTYPE_TI_ARGS (type); if (TREE_VEC_LENGTH (args) == 3 + && (TREE_CODE (TREE_VEC_ELT (args, 0)) + == TREE_CODE (char_type_node)) && same_type_p (TREE_VEC_ELT (args, 0), char_type_node) && is_std_substitution_char (TREE_VEC_ELT (args, 1), SUBID_CHAR_TRAITS) @@ -652,7 +654,7 @@ find_substitution (tree node) args > . */ tree args = CLASSTYPE_TI_ARGS (type); if (TREE_VEC_LENGTH (args) == 2 - && TYPE_P (TREE_VEC_ELT (args, 0)) + && TREE_CODE (TREE_VEC_ELT (args, 0)) == TREE_CODE (char_type_node) && same_type_p (TREE_VEC_ELT (args, 0), char_type_node) && is_std_substitution_char (TREE_VEC_ELT (args, 1), SUBID_CHAR_TRAITS)) diff --git a/gcc/testsuite/g++.dg/pr94027.C b/gcc/testsuite/g++.dg/pr94027.C new file mode 100644 index 0000000..03cd68f --- /dev/null +++ b/gcc/testsuite/g++.dg/pr94027.C @@ -0,0 +1,22 @@ +// { dg-do compile { target c++11 } } +// PR 94027 ICE mangling + +class a { +public: + a (char); +}; +struct b { + b (a); +}; +template +void ax (int) +{ + struct c : b { + c () : b {sizeof...(aw)} + {} + }; +} + +void az() { + ax ({}); +} -- cgit v1.1 From 41f99ba6c576b84ca0f2de7d66ebc087454e93cf Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Thu, 5 Mar 2020 12:06:58 -0500 Subject: analyzer: improvements to state dumping This patch fixes a bug in which summarized state dumps involving a non-NULL pointer to a region for which get_representative_path_var returned NULL were erroneously dumped as "NULL". It also extends sm-state dumps so that they show representative tree values, where available. Finally, it adds some selftest coverage for such dumps. Doing so requires replacing some %qE with a dump_quoted_tree, to avoid C vs C++ differences between "make selftest-c" and "make selftest-c++". gcc/analyzer/ChangeLog: * analyzer.h (dump_quoted_tree): New decl. * engine.cc (exploded_node::dump_dot): Pass region model to sm_state_map::print. * program-state.cc: Include diagnostic-core.h. (sm_state_map::print): Add "model" param and use it to print representative trees. Only print origin information if non-null. (sm_state_map::dump): Pass NULL for model to print call. (program_state::print): Pass region model to sm_state_map::print. (program_state::dump_to_pp): Use spaces rather than newlines when summarizing. Pass region_model to sm_state_map::print. (ana::selftest::assert_dump_eq): New function. (ASSERT_DUMP_EQ): New macro. (ana::selftest::test_program_state_dumping): New function. (ana::selftest::analyzer_program_state_cc_tests): Call it. * program-state.h (program_state::print): Add model param. * region-model.cc (dump_quoted_tree): New function. (map_region::print_fields): Use dump_quoted_tree rather than %qE to avoid lang-dependent output. (map_region::dump_child_label): Likewise. (region_model::dump_summary_of_map): For SK_REGION, when get_representative_path_var fails, print the region id rather than erroneously printing NULL. * sm.cc (state_machine::get_state_by_name): New function. * sm.h (state_machine::get_state_by_name): New decl. --- gcc/analyzer/ChangeLog | 27 +++++++++ gcc/analyzer/analyzer.h | 8 ++- gcc/analyzer/engine.cc | 2 +- gcc/analyzer/program-state.cc | 128 ++++++++++++++++++++++++++++++++++++++---- gcc/analyzer/program-state.h | 3 +- gcc/analyzer/region-model.cc | 29 ++++++---- gcc/analyzer/sm.cc | 15 +++++ gcc/analyzer/sm.h | 2 + 8 files changed, 188 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 4a95fa6..84c619e 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,30 @@ +2020-03-06 David Malcolm + + * analyzer.h (dump_quoted_tree): New decl. + * engine.cc (exploded_node::dump_dot): Pass region model to + sm_state_map::print. + * program-state.cc: Include diagnostic-core.h. + (sm_state_map::print): Add "model" param and use it to print + representative trees. Only print origin information if non-null. + (sm_state_map::dump): Pass NULL for model to print call. + (program_state::print): Pass region model to sm_state_map::print. + (program_state::dump_to_pp): Use spaces rather than newlines when + summarizing. Pass region_model to sm_state_map::print. + (ana::selftest::assert_dump_eq): New function. + (ASSERT_DUMP_EQ): New macro. + (ana::selftest::test_program_state_dumping): New function. + (ana::selftest::analyzer_program_state_cc_tests): Call it. + * program-state.h (program_state::print): Add model param. + * region-model.cc (dump_quoted_tree): New function. + (map_region::print_fields): Use dump_quoted_tree rather than + %qE to avoid lang-dependent output. + (map_region::dump_child_label): Likewise. + (region_model::dump_summary_of_map): For SK_REGION, when + get_representative_path_var fails, print the region id rather than + erroneously printing NULL. + * sm.cc (state_machine::get_state_by_name): New function. + * sm.h (state_machine::get_state_by_name): New decl. + 2020-03-04 David Malcolm * region-model.cc (region::validate): Convert model param from ptr diff --git a/gcc/analyzer/analyzer.h b/gcc/analyzer/analyzer.h index 5364edb..78d6009 100644 --- a/gcc/analyzer/analyzer.h +++ b/gcc/analyzer/analyzer.h @@ -21,12 +21,12 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_ANALYZER_ANALYZER_H #define GCC_ANALYZER_ANALYZER_H -/* Forward decls of common types, with indentation to show inheritance. */ - class graphviz_out; namespace ana { +/* Forward decls of common types, with indentation to show inheritance. */ + class supergraph; class supernode; class superedge; @@ -71,6 +71,10 @@ class state_purge_per_ssa_name; class state_change; class rewind_info_t; +/* Forward decls of functions. */ + +extern void dump_quoted_tree (pretty_printer *pp, tree t); + } // namespace ana extern bool is_special_named_call_p (const gcall *call, const char *funcname, diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc index e411d5b..2431ae3 100644 --- a/gcc/analyzer/engine.cc +++ b/gcc/analyzer/engine.cc @@ -869,7 +869,7 @@ exploded_node::dump_dot (graphviz_out *gv, const dump_args_t &args) const if (!smap->is_empty_p ()) { pp_printf (pp, "%s: ", ext_state.get_name (i)); - smap->print (ext_state.get_sm (i), pp); + smap->print (ext_state.get_sm (i), state.m_region_model, pp); pp_newline (pp); } } diff --git a/gcc/analyzer/program-state.cc b/gcc/analyzer/program-state.cc index 971e8e0..804800f 100644 --- a/gcc/analyzer/program-state.cc +++ b/gcc/analyzer/program-state.cc @@ -22,6 +22,7 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tree.h" +#include "diagnostic-core.h" #include "diagnostic.h" #include "function.h" #include "analyzer/analyzer.h" @@ -147,10 +148,13 @@ sm_state_map::clone_with_remapping (const one_way_svalue_id_map &id_map) const return result; } -/* Print this sm_state_map (for SM) to PP. */ +/* Print this sm_state_map (for SM) to PP. + If MODEL is non-NULL, print representative tree values where + available. */ void -sm_state_map::print (const state_machine &sm, pretty_printer *pp) const +sm_state_map::print (const state_machine &sm, const region_model *model, + pretty_printer *pp) const { bool first = true; pp_string (pp, "{"); @@ -170,10 +174,27 @@ sm_state_map::print (const state_machine &sm, pretty_printer *pp) const sid.print (pp); entry_t e = (*iter).second; - pp_printf (pp, ": %s (origin: ", - sm.get_state_name (e.m_state)); - e.m_origin.print (pp); - pp_string (pp, ")"); + pp_printf (pp, ": %s", sm.get_state_name (e.m_state)); + if (model) + if (tree rep = model->get_representative_tree (sid)) + { + pp_string (pp, " ("); + dump_quoted_tree (pp, rep); + pp_character (pp, ')'); + } + if (!e.m_origin.null_p ()) + { + pp_string (pp, " (origin: "); + e.m_origin.print (pp); + if (model) + if (tree rep = model->get_representative_tree (e.m_origin)) + { + pp_string (pp, " ("); + dump_quoted_tree (pp, rep); + pp_character (pp, ')'); + } + pp_string (pp, ")"); + } } pp_string (pp, "}"); } @@ -186,7 +207,7 @@ sm_state_map::dump (const state_machine &sm) const pretty_printer pp; pp_show_color (&pp) = pp_show_color (global_dc->printer); pp.buffer->stream = stderr; - print (sm, &pp); + print (sm, NULL, &pp); pp_newline (&pp); pp_flush (&pp); } @@ -696,7 +717,7 @@ program_state::print (const extrinsic_state &ext_state, if (!smap->is_empty_p ()) { pp_printf (pp, "%s: ", ext_state.get_name (i)); - smap->print (ext_state.get_sm (i), pp); + smap->print (ext_state.get_sm (i), m_region_model, pp); pp_newline (pp); } } @@ -707,7 +728,9 @@ program_state::print (const extrinsic_state &ext_state, } } -/* Dump a multiline representation of this state to PP. */ +/* Dump a representation of this state to PP. + If SUMMARIZE is true, print a one-line summary; + if false, print a detailed multiline representation. */ void program_state::dump_to_pp (const extrinsic_state &ext_state, @@ -723,16 +746,22 @@ program_state::dump_to_pp (const extrinsic_state &ext_state, { if (!smap->is_empty_p ()) { + if (summarize) + pp_space (pp); pp_printf (pp, "%s: ", ext_state.get_name (i)); - smap->print (ext_state.get_sm (i), pp); - pp_newline (pp); + smap->print (ext_state.get_sm (i), m_region_model, pp); + if (!summarize) + pp_newline (pp); } } if (!m_valid) { + if (summarize) + pp_space (pp); pp_printf (pp, "invalid state"); - pp_newline (pp); + if (!summarize) + pp_newline (pp); } } @@ -1231,6 +1260,30 @@ state_change::validate (const program_state &new_state, namespace selftest { +/* Implementation detail of ASSERT_DUMP_EQ. */ + +static void +assert_dump_eq (const location &loc, + const program_state &state, + const extrinsic_state &ext_state, + bool summarize, + const char *expected) +{ + auto_fix_quotes sentinel; + pretty_printer pp; + pp_format_decoder (&pp) = default_tree_printer; + state.dump_to_pp (ext_state, summarize, &pp); + ASSERT_STREQ_AT (loc, pp_formatted_text (&pp), expected); +} + +/* Assert that STATE.dump_to_pp (SUMMARIZE) is EXPECTED. */ + +#define ASSERT_DUMP_EQ(STATE, EXT_STATE, SUMMARIZE, EXPECTED) \ + SELFTEST_BEGIN_STMT \ + assert_dump_eq ((SELFTEST_LOCATION), (STATE), (EXT_STATE), (SUMMARIZE), \ + (EXPECTED)); \ + SELFTEST_END_STMT + /* Tests for sm_state_map. */ static void @@ -1364,6 +1417,56 @@ test_sm_state_map () // TODO: coverage for purging } +/* Verify that program_state::dump_to_pp works as expected. */ + +static void +test_program_state_dumping () +{ + /* Create a program_state for a global ptr "p" that has + malloc sm-state, pointing to a region on the heap. */ + tree p = build_global_decl ("p", ptr_type_node); + + state_machine *sm = make_malloc_state_machine (NULL); + const state_machine::state_t UNCHECKED_STATE + = sm->get_state_by_name ("unchecked"); + auto_delete_vec checkers; + checkers.safe_push (sm); + extrinsic_state ext_state (checkers); + + program_state s (ext_state); + region_model *model = s.m_region_model; + region_id new_rid = model->add_new_malloc_region (); + svalue_id ptr_sid + = model->get_or_create_ptr_svalue (ptr_type_node, new_rid); + model->set_value (model->get_lvalue (p, NULL), + ptr_sid, NULL); + sm_state_map *smap = s.m_checker_states[0]; + + smap->impl_set_state (ptr_sid, UNCHECKED_STATE, svalue_id::null ()); + ASSERT_EQ (smap->get_state (ptr_sid), UNCHECKED_STATE); + + ASSERT_DUMP_EQ + (s, ext_state, false, + "rmodel: r0: {kind: `root', parent: null, sval: null}\n" + "|-heap: r1: {kind: `heap', parent: r0, sval: sv0}\n" + "| |: sval: sv0: {poisoned: uninit}\n" + "| `-r2: {kind: `symbolic', parent: r1, sval: null}\n" + "`-globals: r3: {kind: `globals', parent: r0, sval: null, map: {`p': r4}}\n" + " `-`p': r4: {kind: `primitive', parent: r3, sval: sv1, type: `void *'}\n" + " |: sval: sv1: {type: `void *', &r2}\n" + " |: type: `void *'\n" + "svalues:\n" + " sv0: {poisoned: uninit}\n" + " sv1: {type: `void *', &r2}\n" + "constraint manager:\n" + " equiv classes:\n" + " constraints:\n" + "malloc: {sv1: unchecked (`p')}\n"); + + ASSERT_DUMP_EQ (s, ext_state, true, + "rmodel: p: &r2 malloc: {sv1: unchecked (`p')}"); +} + /* Verify that program_states with identical sm-state can be merged, and that the merged program_state preserves the sm-state. */ @@ -1466,6 +1569,7 @@ void analyzer_program_state_cc_tests () { test_sm_state_map (); + test_program_state_dumping (); test_program_state_merging (); test_program_state_merging_2 (); } diff --git a/gcc/analyzer/program-state.h b/gcc/analyzer/program-state.h index 2c778cc..3637516 100644 --- a/gcc/analyzer/program-state.h +++ b/gcc/analyzer/program-state.h @@ -146,7 +146,8 @@ public: sm_state_map * clone_with_remapping (const one_way_svalue_id_map &id_map) const; - void print (const state_machine &sm, pretty_printer *pp) const; + void print (const state_machine &sm, const region_model *model, + pretty_printer *pp) const; void dump (const state_machine &sm) const; bool is_empty_p () const; diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 0ceeab4..e7e517a 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -73,6 +73,17 @@ dump_tree (pretty_printer *pp, tree t) dump_generic_node (pp, t, 0, TDF_SLIM, 0); } +/* Dump T to PP in language-independent form in quotes, for + debugging/logging/dumping purposes. */ + +void +dump_quoted_tree (pretty_printer *pp, tree t) +{ + pp_begin_quote (pp, pp_show_color (pp)); + dump_tree (pp, t); + pp_end_quote (pp, pp_show_color (pp)); +} + /* Equivalent to pp_printf (pp, "%qT", t), to avoid nesting pp_printf calls within other pp_printf calls. @@ -1595,7 +1606,8 @@ map_region::print_fields (const region_model &model, pp_string (pp, ", "); tree expr = (*iter).first; region_id child_rid = (*iter).second; - pp_printf (pp, "%qE: ", expr); + dump_quoted_tree (pp, expr); + pp_string (pp, ": "); child_rid.print (pp); } pp_string (pp, "}"); @@ -1665,10 +1677,8 @@ map_region::dump_child_label (const region_model &model, if (child_rid == (*iter).second) { tree key = (*iter).first; - if (DECL_P (key)) - pp_printf (pp, "%qD: ", key); - else - pp_printf (pp, "%qE: ", key); + dump_quoted_tree (pp, key); + pp_string (pp, ": "); } } } @@ -3706,17 +3716,16 @@ region_model::dump_summary_of_map (pretty_printer *pp, { region_svalue *region_sval = as_a (sval); region_id pointee_rid = region_sval->get_pointee (); + gcc_assert (!pointee_rid.null_p ()); tree pointee = get_representative_path_var (pointee_rid).m_tree; dump_separator (pp, is_first); dump_tree (pp, key); pp_string (pp, ": "); + pp_character (pp, '&'); if (pointee) - { - pp_character (pp, '&'); - dump_tree (pp, pointee); - } + dump_tree (pp, pointee); else - pp_string (pp, "NULL"); + pointee_rid.print (pp); } break; case SK_CONSTANT: diff --git a/gcc/analyzer/sm.cc b/gcc/analyzer/sm.cc index b1f156f..affb5aa 100644 --- a/gcc/analyzer/sm.cc +++ b/gcc/analyzer/sm.cc @@ -84,6 +84,21 @@ state_machine::get_state_name (state_t s) const return m_state_names[s]; } +/* Get the state with name NAME, which must exist. + This is purely intended for use in selftests. */ + +state_machine::state_t +state_machine::get_state_by_name (const char *name) +{ + unsigned i; + const char *iter_name; + FOR_EACH_VEC_ELT (m_state_names, i, iter_name) + if (!strcmp (name, iter_name)) + return i; + /* Name not found. */ + gcc_unreachable (); +} + /* Assert that S is a valid state for this state_machine. */ void diff --git a/gcc/analyzer/sm.h b/gcc/analyzer/sm.h index 2f00aae..ebd067a 100644 --- a/gcc/analyzer/sm.h +++ b/gcc/analyzer/sm.h @@ -57,6 +57,8 @@ public: const char *get_state_name (state_t s) const; + state_t get_state_by_name (const char *name); + /* Return true if STMT is a function call recognized by this sm. */ virtual bool on_stmt (sm_context *sm_ctxt, const supernode *node, -- cgit v1.1 From 90f7c3007d58c5cb538d00351c038f3f2cfcaf67 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Fri, 6 Mar 2020 10:13:59 -0500 Subject: analyzer: improvements to region_model::get_representative_tree This patch extends region_model::get_representative_tree so that dumps are able to refer to string literals, which I've found useful in investigating a state-bloat issue. Doing so uncovered a bug in the handling of views I introduced in r10-7024-ge516294a1acb28aaaad44cfd583cc6a80354044e where the code was erroneously using TREE_TYPE on the view region's type, rather than just using its type, which the patch also fixes. gcc/analyzer/ChangeLog: * analyzer.h (class array_region): New forward decl. * program-state.cc (selftest::test_program_state_dumping_2): New. (selftest::analyzer_program_state_cc_tests): Call it. * region-model.cc (array_region::constant_from_key): New. (region_model::get_representative_tree): Handle region_svalue by generating an ADDR_EXPR. (region_model::get_representative_path_var): In view handling, remove erroneous TREE_TYPE when determining the type of the tree. Handle array regions and STRING_CST. (selftest::assert_dump_tree_eq): New. (ASSERT_DUMP_TREE_EQ): New macro. (selftest::test_get_representative_tree): New selftest. (selftest::analyzer_region_model_cc_tests): Call it. * region-model.h (region::dyn_cast_array_region): New vfunc. (array_region::dyn_cast_array_region): New vfunc implementation. (array_region::constant_from_key): New decl. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/malloc-4.c: Update expected output of leak to reflect fix to region_model::get_representative_path_var, adding the missing "*" from the cast. --- gcc/analyzer/ChangeLog | 19 ++++++ gcc/analyzer/analyzer.h | 1 + gcc/analyzer/program-state.cc | 46 ++++++++++++++ gcc/analyzer/region-model.cc | 100 +++++++++++++++++++++++++++++-- gcc/analyzer/region-model.h | 3 + gcc/testsuite/ChangeLog | 6 ++ gcc/testsuite/gcc.dg/analyzer/malloc-4.c | 2 +- 7 files changed, 172 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 84c619e..e51a1cd 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,5 +1,24 @@ 2020-03-06 David Malcolm + * analyzer.h (class array_region): New forward decl. + * program-state.cc (selftest::test_program_state_dumping_2): New. + (selftest::analyzer_program_state_cc_tests): Call it. + * region-model.cc (array_region::constant_from_key): New. + (region_model::get_representative_tree): Handle region_svalue by + generating an ADDR_EXPR. + (region_model::get_representative_path_var): In view handling, + remove erroneous TREE_TYPE when determining the type of the tree. + Handle array regions and STRING_CST. + (selftest::assert_dump_tree_eq): New. + (ASSERT_DUMP_TREE_EQ): New macro. + (selftest::test_get_representative_tree): New selftest. + (selftest::analyzer_region_model_cc_tests): Call it. + * region-model.h (region::dyn_cast_array_region): New vfunc. + (array_region::dyn_cast_array_region): New vfunc implementation. + (array_region::constant_from_key): New decl. + +2020-03-06 David Malcolm + * analyzer.h (dump_quoted_tree): New decl. * engine.cc (exploded_node::dump_dot): Pass region model to sm_state_map::print. diff --git a/gcc/analyzer/analyzer.h b/gcc/analyzer/analyzer.h index 78d6009..8d0d169 100644 --- a/gcc/analyzer/analyzer.h +++ b/gcc/analyzer/analyzer.h @@ -43,6 +43,7 @@ class svalue; class setjmp_svalue; class region; class map_region; + class array_region; class symbolic_region; class region_model; class region_model_context; diff --git a/gcc/analyzer/program-state.cc b/gcc/analyzer/program-state.cc index 804800f..24b6783 100644 --- a/gcc/analyzer/program-state.cc +++ b/gcc/analyzer/program-state.cc @@ -1467,6 +1467,51 @@ test_program_state_dumping () "rmodel: p: &r2 malloc: {sv1: unchecked (`p')}"); } +/* Verify that program_state::dump_to_pp works for string literals. */ + +static void +test_program_state_dumping_2 () +{ + /* Create a program_state for a global ptr "p" that points to + a string constant. */ + tree p = build_global_decl ("p", ptr_type_node); + + tree string_cst_ptr = build_string_literal (4, "foo"); + + auto_delete_vec checkers; + extrinsic_state ext_state (checkers); + + program_state s (ext_state); + region_model *model = s.m_region_model; + region_id p_rid = model->get_lvalue (p, NULL); + svalue_id str_sid = model->get_rvalue (string_cst_ptr, NULL); + model->set_value (p_rid, str_sid, NULL); + + ASSERT_DUMP_EQ + (s, ext_state, false, + "rmodel: r0: {kind: `root', parent: null, sval: null}\n" + "|-globals: r1: {kind: `globals', parent: r0, sval: null, map: {`p': r2}}\n" + "| `-`p': r2: {kind: `primitive', parent: r1, sval: sv3, type: `void *'}\n" + "| |: sval: sv3: {type: `void *', &r4}\n" + "| |: type: `void *'\n" + "`-r3: {kind: `array', parent: r0, sval: sv0, type: `const char[4]', array: {[0]: r4}}\n" + " |: sval: sv0: {type: `const char[4]', `\"foo\"'}\n" + " |: type: `const char[4]'\n" + " `-[0]: r4: {kind: `primitive', parent: r3, sval: null, type: `const char'}\n" + " |: type: `const char'\n" + "svalues:\n" + " sv0: {type: `const char[4]', `\"foo\"'}\n" + " sv1: {type: `int', `0'}\n" + " sv2: {type: `const char *', &r4}\n" + " sv3: {type: `void *', &r4}\n" + "constraint manager:\n" + " equiv classes:\n" + " constraints:\n"); + + ASSERT_DUMP_EQ (s, ext_state, true, + "rmodel: p: &\"foo\"[0]"); +} + /* Verify that program_states with identical sm-state can be merged, and that the merged program_state preserves the sm-state. */ @@ -1570,6 +1615,7 @@ analyzer_program_state_cc_tests () { test_sm_state_map (); test_program_state_dumping (); + test_program_state_dumping_2 (); test_program_state_merging (); test_program_state_merging_2 (); } diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index e7e517a..87980e7 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -2494,6 +2494,16 @@ array_region::key_from_constant (tree cst) return result; } +/* Convert array_region::key_t KEY into a tree constant. */ + +tree +array_region::constant_from_key (key_t key) +{ + tree array_type = get_type (); + tree index_type = TYPE_DOMAIN (array_type); + return build_int_cst (index_type, key); +} + /* class function_region : public map_region. */ /* Compare the fields of this function_region with OTHER, returning true @@ -5669,9 +5679,7 @@ region_model::add_new_malloc_region () return add_region (new symbolic_region (heap_rid, NULL_TREE, true)); } -/* Attempt to return a tree that represents SID, or return NULL_TREE. - Find the first region that stores the value (e.g. a local) and - generate a representative tree for it. */ +/* Attempt to return a tree that represents SID, or return NULL_TREE. */ tree region_model::get_representative_tree (svalue_id sid) const @@ -5679,6 +5687,8 @@ region_model::get_representative_tree (svalue_id sid) const if (sid.null_p ()) return NULL_TREE; + /* Find the first region that stores the value (e.g. a local) and + generate a representative tree for it. */ unsigned i; region *region; FOR_EACH_VEC_ELT (m_regions, i, region) @@ -5689,6 +5699,18 @@ region_model::get_representative_tree (svalue_id sid) const return pv.m_tree; } + /* Handle string literals and various other pointers. */ + svalue *sval = get_svalue (sid); + if (region_svalue *ptr_sval = sval->dyn_cast_region_svalue ()) + { + region_id rid = ptr_sval->get_pointee (); + path_var pv = get_representative_path_var (rid); + if (pv.m_tree) + return build1 (ADDR_EXPR, + TREE_TYPE (sval->get_type ()), + pv.m_tree); + } + return maybe_get_constant (sid); } @@ -5727,7 +5749,7 @@ region_model::get_representative_path_var (region_id rid) const path_var parent_pv = get_representative_path_var (parent_rid); if (parent_pv.m_tree && reg->get_type ()) return path_var (build1 (NOP_EXPR, - TREE_TYPE (reg->get_type ()), + reg->get_type (), parent_pv.m_tree), parent_pv.m_stack_depth); } @@ -5750,6 +5772,32 @@ region_model::get_representative_path_var (region_id rid) const } } + /* Handle elements within an array. */ + if (array_region *array_reg = parent_region->dyn_cast_array_region ()) + { + array_region::key_t key; + if (array_reg->get_key_for_child_region (rid, &key)) + { + path_var parent_pv = get_representative_path_var (parent_rid); + if (parent_pv.m_tree && reg->get_type ()) + { + tree index = array_reg->constant_from_key (key); + return path_var (build4 (ARRAY_REF, + reg->get_type (), + parent_pv.m_tree, index, + NULL_TREE, NULL_TREE), + parent_pv.m_stack_depth); + } + } + } + + /* Handle string literals. */ + svalue_id sid = reg->get_value_direct (); + if (svalue *sval = get_svalue (sid)) + if (tree cst = sval->maybe_get_constant ()) + if (TREE_CODE (cst) == STRING_CST) + return path_var (cst, 0); + return path_var (NULL_TREE, 0); } @@ -7273,6 +7321,25 @@ assert_condition (const location &loc, ASSERT_EQ_AT (loc, actual, expected); } +/* Implementation detail of ASSERT_DUMP_TREE_EQ. */ + +static void +assert_dump_tree_eq (const location &loc, tree t, const char *expected) +{ + auto_fix_quotes sentinel; + pretty_printer pp; + pp_format_decoder (&pp) = default_tree_printer; + dump_tree (&pp, t); + ASSERT_STREQ_AT (loc, pp_formatted_text (&pp), expected); +} + +/* Assert that dump_tree (T) is EXPECTED. */ + +#define ASSERT_DUMP_TREE_EQ(T, EXPECTED) \ + SELFTEST_BEGIN_STMT \ + assert_dump_tree_eq ((SELFTEST_LOCATION), (T), (EXPECTED)); \ + SELFTEST_END_STMT + /* Implementation detail of ASSERT_DUMP_EQ. */ static void @@ -7321,6 +7388,30 @@ test_dump () ASSERT_DUMP_EQ (model, true, ""); } +/* Verify that region_model::get_representative_tree works as expected. */ + +static void +test_get_representative_tree () +{ + /* STRING_CST. */ + { + tree string_cst = build_string (4, "foo"); + region_model m; + svalue_id str_sid = m.get_rvalue (string_cst, NULL); + tree rep = m.get_representative_tree (str_sid); + ASSERT_EQ (rep, string_cst); + } + + /* String literal. */ + { + tree string_cst_ptr = build_string_literal (4, "foo"); + region_model m; + svalue_id str_sid = m.get_rvalue (string_cst_ptr, NULL); + tree rep = m.get_representative_tree (str_sid); + ASSERT_DUMP_TREE_EQ (rep, "&\"foo\"[0]"); + } +} + /* Verify that calling region_model::get_rvalue repeatedly on the same tree constant retrieves the same svalue_id. */ @@ -8372,6 +8463,7 @@ analyzer_region_model_cc_tests () { test_tree_cmp_on_constants (); test_dump (); + test_get_representative_tree (); test_unique_constants (); test_svalue_equality (); test_region_equality (); diff --git a/gcc/analyzer/region-model.h b/gcc/analyzer/region-model.h index c782e93..c1fe592 100644 --- a/gcc/analyzer/region-model.h +++ b/gcc/analyzer/region-model.h @@ -844,6 +844,7 @@ public: virtual enum region_kind get_kind () const = 0; virtual map_region *dyn_cast_map_region () { return NULL; } + virtual array_region *dyn_cast_array_region () { return NULL; } virtual const symbolic_region *dyn_cast_symbolic_region () const { return NULL; } @@ -1354,6 +1355,7 @@ public: /* region vfuncs. */ region *clone () const FINAL OVERRIDE; enum region_kind get_kind () const FINAL OVERRIDE { return RK_ARRAY; } + array_region *dyn_cast_array_region () { return this; } region_id get_element (region_model *model, region_id this_rid, @@ -1400,6 +1402,7 @@ public: void validate (const region_model &model) const FINAL OVERRIDE; static key_t key_from_constant (tree cst); + tree constant_from_key (key_t key); private: static int key_cmp (const void *, const void *); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 59c9988..358d1de 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-06 David Malcolm + + * gcc.dg/analyzer/malloc-4.c: Update expected output of leak to + reflect fix to region_model::get_representative_path_var, adding + the missing "*" from the cast. + 2020-03-06 Wilco Dijkstra * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. diff --git a/gcc/testsuite/gcc.dg/analyzer/malloc-4.c b/gcc/testsuite/gcc.dg/analyzer/malloc-4.c index 94d2825..c9c275a 100644 --- a/gcc/testsuite/gcc.dg/analyzer/malloc-4.c +++ b/gcc/testsuite/gcc.dg/analyzer/malloc-4.c @@ -17,4 +17,4 @@ void a5 (void) { struct bar *qb = NULL; hv (&qb); -} /* { dg-warning "leak of '\\(struct foo\\)qb'" } */ +} /* { dg-warning "leak of '\\(struct foo \\*\\)qb'" } */ -- cgit v1.1 From 2a4c59d9aa6b1018fa8f86dd8c0573c1fed3f199 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 7 Mar 2020 00:16:29 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f54c682..94dc107 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200306 +20200307 -- cgit v1.1 From 6733ecaf3fe77871d86bfb36bcda5497ae2aaba7 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 8 Mar 2020 05:01:03 -0700 Subject: gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c" PR target/89229 PR target/89346 * gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c", instead of "pr89229-5a.c". --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/i386/pr89229-3c.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 358d1de..6fa77ce 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-08 H.J. Lu + + PR target/89229 + PR target/89346 + * gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c", instead + of "pr89229-5a.c". + 2020-03-06 David Malcolm * gcc.dg/analyzer/malloc-4.c: Update expected output of leak to diff --git a/gcc/testsuite/gcc.target/i386/pr89229-3c.c b/gcc/testsuite/gcc.target/i386/pr89229-3c.c index 529a520..3e69cdb 100644 --- a/gcc/testsuite/gcc.target/i386/pr89229-3c.c +++ b/gcc/testsuite/gcc.target/i386/pr89229-3c.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ -#include "pr89229-5a.c" +#include "pr89229-3a.c" /* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ -- cgit v1.1 From ff0a62841e27b838f17a9d6253d131206072df6f Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Fri, 6 Mar 2020 13:19:13 -0500 Subject: c++: Fix pretty printing of TYPENAME_TYPEs I noticed that in some concepts diagnostic messages, we were printing typename types incorrectly, e.g. printing remove_reference_t as typename remove_reference::remove_reference_t instead of typename remove_reference::type. Fix this by printing the TYPENAME_TYPE_FULLNAME instead of the TYPE_NAME in cxx_pretty_printer::simple_type_specifier, which is consistent with how dump_typename in error.c does it. gcc/cp/ChangeLog: * cxx-pretty-print.c (cxx_pretty_printer::simple_type_specifier) [TYPENAME_TYPE]: Print the TYPENAME_TYPE_FULLNAME instead of the TYPE_NAME. gcc/testsuite/ChangeLog: * g++.dg/concepts/diagnostic4.C: New test. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/cxx-pretty-print.c | 2 +- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/concepts/diagnostic4.C | 18 ++++++++++++++++++ 4 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic4.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 98640a6..48ef75c 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-08 Patrick Palka + + * cxx-pretty-print.c (cxx_pretty_printer::simple_type_specifier) + [TYPENAME_TYPE]: Print the TYPENAME_TYPE_FULLNAME instead of the + TYPE_NAME. + 2020-03-06 Nathan Sidwell PR c++/94027 diff --git a/gcc/cp/cxx-pretty-print.c b/gcc/cp/cxx-pretty-print.c index 397bdbf..100154e 100644 --- a/gcc/cp/cxx-pretty-print.c +++ b/gcc/cp/cxx-pretty-print.c @@ -1360,7 +1360,7 @@ cxx_pretty_printer::simple_type_specifier (tree t) case TYPENAME_TYPE: pp_cxx_ws_string (this, "typename"); pp_cxx_nested_name_specifier (this, TYPE_CONTEXT (t)); - pp_cxx_unqualified_id (this, TYPE_NAME (t)); + pp_cxx_unqualified_id (this, TYPENAME_TYPE_FULLNAME (t)); break; default: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6fa77ce..99e2e42 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-08 Patrick Palka + + * g++.dg/concepts/diagnostic4.C: New test. + 2020-03-08 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/g++.dg/concepts/diagnostic4.C b/gcc/testsuite/g++.dg/concepts/diagnostic4.C new file mode 100644 index 0000000..677bc86 --- /dev/null +++ b/gcc/testsuite/g++.dg/concepts/diagnostic4.C @@ -0,0 +1,18 @@ +// { dg-do compile { target c++2a } } + +template + struct remove_reference + { using type = T; }; + +template + using remove_reference_t = remove_reference::type; + +template + inline constexpr bool blah = false; + +template + requires blah> + // { dg-message "typename remove_reference::type" "" { target *-*-* } .-1 } + void foo() { } + +void bar() { foo (); } // { dg-error "use of" } -- cgit v1.1 From 5e1b4e60c1823115ba7ff0e8c4b35f6058ad9969 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Tue, 3 Mar 2020 12:27:33 -0500 Subject: c++: Fix missing SFINAE when binding a bit-field to a reference (PR 93729) We are unconditionally emitting an error here, without first checking complain. gcc/cp/ChangeLog: PR c++/93729 * call.c (convert_like_real): Check complain before emitting an error about binding a bit-field to a reference. gcc/testsuite/ChangeLog: PR c++/93729 * g++.dg/concepts/pr93729.C: New test. --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/call.c | 21 ++++++++++++--------- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/g++.dg/concepts/pr93729.C | 15 +++++++++++++++ 4 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/g++.dg/concepts/pr93729.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 48ef75c..f32c27e 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2020-03-08 Patrick Palka + PR c++/93729 + * call.c (convert_like_real): Check complain before emitting an error + about binding a bit-field to a reference. + * cxx-pretty-print.c (cxx_pretty_printer::simple_type_specifier) [TYPENAME_TYPE]: Print the TYPENAME_TYPE_FULLNAME instead of the TYPE_NAME. diff --git a/gcc/cp/call.c b/gcc/cp/call.c index 85bbd04..c0340d9 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -7730,15 +7730,18 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, { /* If the reference is volatile or non-const, we cannot create a temporary. */ - if (lvalue & clk_bitfield) - error_at (loc, "cannot bind bit-field %qE to %qT", - expr, ref_type); - else if (lvalue & clk_packed) - error_at (loc, "cannot bind packed field %qE to %qT", - expr, ref_type); - else - error_at (loc, "cannot bind rvalue %qE to %qT", - expr, ref_type); + if (complain & tf_error) + { + if (lvalue & clk_bitfield) + error_at (loc, "cannot bind bit-field %qE to %qT", + expr, ref_type); + else if (lvalue & clk_packed) + error_at (loc, "cannot bind packed field %qE to %qT", + expr, ref_type); + else + error_at (loc, "cannot bind rvalue %qE to %qT", + expr, ref_type); + } return error_mark_node; } /* If the source is a packed field, and we must use a copy diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 99e2e42..a1a371b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-08 Patrick Palka + PR c++/93729 + * g++.dg/concepts/pr93729.C: New test. + * g++.dg/concepts/diagnostic4.C: New test. 2020-03-08 H.J. Lu diff --git a/gcc/testsuite/g++.dg/concepts/pr93729.C b/gcc/testsuite/g++.dg/concepts/pr93729.C new file mode 100644 index 0000000..7397edb --- /dev/null +++ b/gcc/testsuite/g++.dg/concepts/pr93729.C @@ -0,0 +1,15 @@ +// { dg-do compile { target c++2a } } + +// PR c++/93729 + +struct B +{ + int a:4; + int b:4; +}; + +template +concept c1 + = requires(T x, void(f)(int &)) { f(x.a); }; // { dg-bogus "cannot bind" } + +static_assert(!c1); -- cgit v1.1 From 9de42a8e995451cb13dceb3970ae23ff88240bff Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Sun, 8 Mar 2020 18:52:35 +0000 Subject: Patch and ChangeLogs for PR93581 --- gcc/fortran/ChangeLog | 8 ++++++ gcc/fortran/resolve.c | 33 ++++++++++++++++++++++-- gcc/fortran/trans-array.c | 18 +++++++++++++ gcc/testsuite/ChangeLog | 7 ++++- gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 | 24 +++++++++++++++++ 5 files changed, 87 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 90e1cab..b3ff063 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,11 @@ +2020-03-08 Paul Thomas + + PR fortran/93581 + * resolve.c (gfc_resolve_ref): Modify array refs to be elements + if the ref chain ends in INQUIRY_LEN. + * trans-array.c (gfc_get_dataptr_offset): Provide the offsets + for INQUIRY_RE and INQUIRY_IM. + 2020-03-05 Steven G. Kargl PR fortran/93792 diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c index 8f5267f..b5813a7 100644 --- a/gcc/fortran/resolve.c +++ b/gcc/fortran/resolve.c @@ -5199,8 +5199,8 @@ gfc_resolve_substring_charlen (gfc_expr *e) bool gfc_resolve_ref (gfc_expr *expr) { - int current_part_dimension, n_components, seen_part_dimension; - gfc_ref *ref, **prev; + int current_part_dimension, n_components, seen_part_dimension, dim; + gfc_ref *ref, **prev, *array_ref; bool equal_length; for (ref = expr->ref; ref; ref = ref->next) @@ -5246,12 +5246,14 @@ gfc_resolve_ref (gfc_expr *expr) current_part_dimension = 0; seen_part_dimension = 0; n_components = 0; + array_ref = NULL; for (ref = expr->ref; ref; ref = ref->next) { switch (ref->type) { case REF_ARRAY: + array_ref = ref; switch (ref->u.ar.type) { case AR_FULL: @@ -5267,6 +5269,7 @@ gfc_resolve_ref (gfc_expr *expr) break; case AR_ELEMENT: + array_ref = NULL; current_part_dimension = 0; break; @@ -5306,7 +5309,33 @@ gfc_resolve_ref (gfc_expr *expr) break; case REF_SUBSTRING: + break; + case REF_INQUIRY: + /* Implement requirement in note 9.7 of F2018 that the result of the + LEN inquiry be a scalar. */ + if (ref->u.i == INQUIRY_LEN && array_ref) + { + array_ref->u.ar.type = AR_ELEMENT; + expr->rank = 0; + /* INQUIRY_LEN is not evaluated from the the rest of the expr + but directly from the string length. This means that setting + the array indices to one does not matter but might trigger + a runtime bounds error. Suppress the check. */ + expr->no_bounds_check = 1; + for (dim = 0; dim < array_ref->u.ar.dimen; dim++) + { + array_ref->u.ar.dimen_type[dim] = DIMEN_ELEMENT; + if (array_ref->u.ar.start[dim]) + gfc_free_expr (array_ref->u.ar.start[dim]); + array_ref->u.ar.start[dim] + = gfc_get_int_expr (gfc_default_integer_kind, NULL, 1); + if (array_ref->u.ar.end[dim]) + gfc_free_expr (array_ref->u.ar.end[dim]); + if (array_ref->u.ar.stride[dim]) + gfc_free_expr (array_ref->u.ar.stride[dim]); + } + } break; } diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c index 65ba84c..a4b1cba 100644 --- a/gcc/fortran/trans-array.c +++ b/gcc/fortran/trans-array.c @@ -6947,6 +6947,24 @@ gfc_get_dataptr_offset (stmtblock_t *block, tree parm, tree desc, tree offset, tmp = gfc_build_array_ref (tmp, index, NULL); break; + case REF_INQUIRY: + switch (ref->u.i) + { + case INQUIRY_RE: + tmp = fold_build1_loc (input_location, REALPART_EXPR, + TREE_TYPE (TREE_TYPE (tmp)), tmp); + break; + + case INQUIRY_IM: + tmp = fold_build1_loc (input_location, IMAGPART_EXPR, + TREE_TYPE (TREE_TYPE (tmp)), tmp); + break; + + default: + break; + } + break; + default: gcc_unreachable (); break; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a1a371b..722a473 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-08 Paul Thomas + + PR fortran/93581 + * gfortran.dg/inquiry_type_ref_6.f90 : New test. + 2020-03-08 Patrick Palka PR c++/93729 @@ -20,7 +25,7 @@ 2020-03-06 Wilco Dijkstra - * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. + * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise. * gcc.target/aarch64/mla_intrinsic_1.c: Likewise. * gcc.target/aarch64/mls_intrinsic_1.c: Likewise. diff --git a/gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 b/gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 new file mode 100644 index 0000000..ffe09b0 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 @@ -0,0 +1,24 @@ +! { dg-do run } +! { dg-options "-fcheck=all" } +! +! Test the fix for PR93581 and the implementation of note 9.7 of F2018. +! The latter requires that the result of the LEN inquiry be a scalar +! even for array expressions. +! +! Contributed by Gerhard Steinmetz +! +program p + complex, target :: z(2) = [(1.0, 2.0),(3.0, 4.0)] + character(:), allocatable, target :: c(:) + real, pointer :: r(:) + character(:), pointer :: s(:) + + r => z%re + if (any (r .ne. real (z))) stop 1 + r => z%im + if (any (r .ne. imag (z))) stop 2 + + allocate (c, source = ['abc','def']) + s(-2:-1) => c(1:2) + if (s%len .ne. len (c)) stop 3 +end -- cgit v1.1 From 0b4ee25bdd7e67b3533295b5bdc7f98f379d8984 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 9 Mar 2020 00:16:14 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 94dc107..cfc79aa 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200307 +20200309 -- cgit v1.1 From d5114529228f97c2a433fa72ddea3fadeb6465b3 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Sun, 8 Mar 2020 21:34:13 -0500 Subject: [testsuite] Fix PR94023 to guard case under vect_hw_misalign As PR94023 shows, the expected SLP requires misaligned vector access support. This patch is to guard the check under the target condition vect_hw_misalign to ensure that. gcc/testsuite/ChangeLog 2020-03-09 Kewen Lin PR testsuite/94023 * gcc.dg/vect/slp-perm-12.c: Expect loop vectorized messages only on vect_hw_misalign targets. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/vect/slp-perm-12.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 722a473..2126a24 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-09 Kewen Lin + + PR testsuite/94023 + * gcc.dg/vect/slp-perm-12.c: Expect loop vectorized messages only on + vect_hw_misalign targets. + 2020-03-08 Paul Thomas PR fortran/93581 diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-12.c b/gcc/testsuite/gcc.dg/vect/slp-perm-12.c index 4d4c534..113223a 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-12.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-12.c @@ -49,4 +49,4 @@ int main() return 0; } -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_perm } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_perm && vect_hw_misalign } } } } */ -- cgit v1.1 From cb2c60206f4f2218f84ccde21663b00de068d8c7 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Sun, 8 Mar 2020 21:55:11 -0500 Subject: [testsuite] Fix PR94019 to check vector char when vect_hw_misalign As PR94019 shows, without misaligned vector access support but with realign load, the vectorized loop will end up with realign scheme. It generates mask (control vector) with return type vector signed char which breaks the not check. gcc/testsuite/ChangeLog 2020-03-09 Kewen Lin PR testsuite/94019 * gcc.dg/vect/vect-over-widen-17.c: Don't expect vector char if it's without misaligned vector access support. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2126a24..b72b9cb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2020-03-09 Kewen Lin + PR testsuite/94019 + * gcc.dg/vect/vect-over-widen-17.c: Don't expect vector char if it's + without misaligned vector access support. + +2020-03-09 Kewen Lin + PR testsuite/94023 * gcc.dg/vect/slp-perm-12.c: Expect loop vectorized messages only on vect_hw_misalign targets. diff --git a/gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c b/gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c index 0448260..333d74a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c +++ b/gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c @@ -41,6 +41,9 @@ main (void) } /* { dg-final { scan-tree-dump-not {vect_recog_over_widening_pattern: detected} "vect" } } */ -/* { dg-final { scan-tree-dump-not {vector[^\n]*char} "vect" } } */ +/* On Power, if there is no vect_hw_misalign support, unaligned vector access + adopts realign_load scheme. It requires rs6000_builtin_mask_for_load to + generate mask whose return type is vector char. */ +/* { dg-final { scan-tree-dump-not {vector[^\n]*char} "vect" { target vect_hw_misalign } } } */ /* { dg-final { scan-tree-dump-not {vector[^ ]* int} "vect" } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loop" 1 "vect" } } */ -- cgit v1.1 From 016d0f9e43c1d2bd8227751b5b20a309c94edc90 Mon Sep 17 00:00:00 2001 From: Bin Cheng Date: Mon, 9 Mar 2020 18:54:57 +0800 Subject: Insert default return_void at the end of coroutine body Exception in coroutine is not correctly handled because the default return_void call is now inserted before the finish suspend point, rather than at the end of the original coroutine body. This patch fixes the issue by expanding code as following: co_await promise.initial_suspend(); try { // The original coroutine body promise.return_void(); // The default return_void call. } catch (...) { promise.unhandled_exception(); } final_suspend: // ... gcc/cp/ * coroutines.cc (build_actor_fn): Factor out code inserting the default return_void call to... (morph_fn_to_coro): ...here, also hoist local var declarations. gcc/testsuite/ * g++.dg/coroutines/torture/co-ret-15-default-return_void.C: New. --- gcc/cp/ChangeLog | 6 ++ gcc/cp/coroutines.cc | 68 ++++++++++++---------- gcc/testsuite/ChangeLog | 4 ++ .../torture/co-ret-15-default-return_void.C | 55 +++++++++++++++++ 4 files changed, 102 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-ret-15-default-return_void.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index f32c27e..128880b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-09 Bin Cheng + + * coroutines.cc (build_actor_fn): Factor out code inserting the + default return_void call to... + (morph_fn_to_coro): ...here, also hoist local var declarations. + 2020-03-08 Patrick Palka PR c++/93729 diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc index bca4f1e..920575b 100644 --- a/gcc/cp/coroutines.cc +++ b/gcc/cp/coroutines.cc @@ -2161,21 +2161,6 @@ build_actor_fn (location_t loc, tree coro_frame_type, tree actor, tree fnbody, r = coro_build_expr_stmt (initial_await, loc); add_stmt (r); - /* Now we've built the promise etc, process fnbody for co_returns. - We want the call to return_void () below and it has no params so - we can create it once here. - Calls to return_value () will have to be checked and created as - required. */ - - tree return_void = NULL_TREE; - tree rvm - = lookup_promise_method (orig, coro_return_void_identifier, loc, - /*musthave=*/false); - if (rvm && rvm != error_mark_node) - return_void - = build_new_method_call (ap, rvm, NULL, NULL_TREE, LOOKUP_NORMAL, NULL, - tf_warning_or_error); - /* co_return branches to the final_suspend label, so declare that now. */ tree fs_label = create_named_label_with_ctx (loc, "final.suspend", actor); @@ -2190,15 +2175,6 @@ build_actor_fn (location_t loc, tree coro_frame_type, tree actor, tree fnbody, /* Add in our function body with the co_returns rewritten to final form. */ add_stmt (fnbody); - /* [stmt.return.coroutine] (2.2 : 3) if p.return_void() is a valid - expression, flowing off the end of a coroutine is equivalent to - co_return; otherwise UB. - We just inject the call to p.return_void() here, and fall through to - the final_suspend: label (eliding the goto). If the function body has - a co_return, then this statement will be unreachable and DCEd. */ - if (return_void != NULL_TREE) - add_stmt (return_void); - /* Final suspend starts here. */ r = build_stmt (loc, LABEL_EXPR, fs_label); add_stmt (r); @@ -3815,18 +3791,48 @@ morph_fn_to_coro (tree orig, tree *resumer, tree *destroyer) BIND_EXPR_BLOCK (first) = replace_blk; } + /* actor's version of the promise. */ + tree actor_frame = build1_loc (fn_start, INDIRECT_REF, coro_frame_type, + DECL_ARGUMENTS (actor)); + tree ap_m = lookup_member (coro_frame_type, get_identifier ("__p"), 1, 0, + tf_warning_or_error); + tree ap = build_class_member_access_expr (actor_frame, ap_m, NULL_TREE, + false, tf_warning_or_error); + + /* Now we've built the promise etc, process fnbody for co_returns. + We want the call to return_void () below and it has no params so + we can create it once here. + Calls to return_value () will have to be checked and created as + required. */ + + tree return_void = NULL_TREE; + tree rvm + = lookup_promise_method (orig, coro_return_void_identifier, fn_start, + /*musthave=*/false); + if (rvm && rvm != error_mark_node) + return_void + = build_new_method_call (ap, rvm, NULL, NULL_TREE, LOOKUP_NORMAL, NULL, + tf_warning_or_error); + + /* [stmt.return.coroutine] (2.2 : 3) if p.return_void() is a valid + expression, flowing off the end of a coroutine is equivalent to + co_return; otherwise UB. + We just inject the call to p.return_void() here, and fall through to + the final_suspend: label (eliding the goto). If the function body has + a co_return, then this statement will be unreachable and DCEd. */ + if (return_void != NULL_TREE) + { + tree append = push_stmt_list (); + add_stmt (fnbody); + add_stmt (return_void); + fnbody = pop_stmt_list(append); + } + if (flag_exceptions) { tree ueh_meth = lookup_promise_method (orig, coro_unhandled_exception_identifier, fn_start, /*musthave=*/true); - /* actor's version of the promise. */ - tree actor_frame = build1_loc (fn_start, INDIRECT_REF, coro_frame_type, - DECL_ARGUMENTS (actor)); - tree ap_m = lookup_member (coro_frame_type, get_identifier ("__p"), 1, 0, - tf_warning_or_error); - tree ap = build_class_member_access_expr (actor_frame, ap_m, NULL_TREE, - false, tf_warning_or_error); /* Build promise.unhandled_exception(); */ tree ueh = build_new_method_call (ap, ueh_meth, NULL, NULL_TREE, LOOKUP_NORMAL, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b72b9cb..cf7243d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-09 Bin Cheng + + * g++.dg/coroutines/torture/co-ret-15-default-return_void.C: New. + 2020-03-09 Kewen Lin PR testsuite/94019 diff --git a/gcc/testsuite/g++.dg/coroutines/torture/co-ret-15-default-return_void.C b/gcc/testsuite/g++.dg/coroutines/torture/co-ret-15-default-return_void.C new file mode 100644 index 0000000..e600fea --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/co-ret-15-default-return_void.C @@ -0,0 +1,55 @@ +// { dg-do run } +// +// Check if default return_void is insert at correct position. +#include +#include "../coro.h" + +class resumable { +public: + class promise_type; + using coro_handle = std::coroutine_handle; + resumable(coro_handle handle) : handle_(handle) { assert(handle); } + resumable(resumable&) = delete; + resumable(resumable&&) = delete; + bool resume() { + if (!handle_.done()) + handle_.resume(); + return !handle_.done(); + } + int recent_val(); + ~resumable() { handle_.destroy(); } +private: + coro_handle handle_; +}; + +class resumable::promise_type { +public: + friend class resumable; + using coro_handle = std::coroutine_handle; + auto get_return_object() { return coro_handle::from_promise(*this); } + auto initial_suspend() { return std::suspend_always(); } + auto final_suspend() { return std::suspend_always(); } + void return_void() { value_ = -1; } + void unhandled_exception() {} +private: + int value_ = 0; +}; + +int resumable::recent_val() {return handle_.promise().value_;} + +resumable foo(int n){ + co_await std::suspend_always(); + throw 1; +} + +int bar (int n) { + resumable res = foo(n); + while(res.resume()); + return res.recent_val(); +} + +int main() { + int res = bar(3); + assert(res == 0); + return 0; +} -- cgit v1.1 From 2e94d3ee47be0742df843d95e3d1bf1da11e4796 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 9 Mar 2020 13:38:23 +0100 Subject: alias: Punt after walking too many VALUEs during a toplevel find_base_term call [PR94045] As mentioned in the PR, on a largish C++ testcase the compile time on i686-linux is about 16 minutes on a fast box, mostly spent in find_base_term recursive calls dealing with very deep chains of preserved VALUEs during var-tracking. The following patch punts after we process many VALUEs (we already have code to punt if we run into a VALUE cycle). I've gathered statistics on when we punt this way (with BITS_PER_WORD, TU, function columns piped through sort | uniq -c | sort -n): 36 32 ../../gcc/asan.c _Z29initialize_sanitizer_builtinsv.part.0 108 32 _first_test.go reflect_test.reflect_test..import 1005 32 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/pr85180.c foo 1005 32 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/pr87985.c foo 1005 64 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/pr85180.c foo 1005 64 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/pr87985.c foo 2534 32 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/stack-check-9.c f3 6346 32 ../../gcc/brig/brig-lang.c brig_define_builtins 6398 32 ../../gcc/d/d-builtins.cc d_define_builtins 8816 32 ../../gcc/c-family/c-common.c c_common_nodes_and_builtins 8824 32 ../../gcc/lto/lto-lang.c lto_define_builtins 41413 32 /home/jakub/src/gcc/gcc/testsuite/gcc.dg/pr43058.c test Additionally, for most of these (for the builtins definitions tested just one) I've verified with a different alias.c change which didn't punt but in the toplevel find_base_term recorded if visited_vals reached the limit whether the return value was NULL_RTX or something different, and in all these cases the end result was NULL_RTX, so at least in these cases it should just shorten the time until it returns NULL. 2020-03-09 Jakub Jelinek PR rtl-optimization/94045 * params.opt (-param=max-find-base-term-values=): New option. * alias.c (find_base_term): Add cut-off for number of visited VALUEs in a single toplevel find_base_term call. --- gcc/ChangeLog | 7 +++++++ gcc/alias.c | 3 +++ gcc/params.opt | 4 ++++ 3 files changed, 14 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bc6f39..c9c4e75 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-09 Jakub Jelinek + + PR rtl-optimization/94045 + * params.opt (-param=max-find-base-term-values=): New option. + * alias.c (find_base_term): Add cut-off for number of visited VALUEs + in a single toplevel find_base_term call. + 2020-03-06 Wilco Dijkstra PR target/91598 diff --git a/gcc/alias.c b/gcc/alias.c index d38e386..82a27f6 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -2005,6 +2005,9 @@ find_base_term (rtx x, vec (unsigned) param_max_find_base_term_values) + return ret; + f = val->locs; /* Reset val->locs to avoid infinite recursion. */ if (f) diff --git a/gcc/params.opt b/gcc/params.opt index ea0c2bf..e39216a 100644 --- a/gcc/params.opt +++ b/gcc/params.opt @@ -662,6 +662,10 @@ Max. size of loc list for which reverse ops should be added. Common Joined UInteger Var(param_max_vartrack_size) Init(50000000) Param Optimization Max. size of var tracking hash tables. +-param=max-find-base-term-values= +Common Joined UInteger Var(param_max_find_base_term_values) Init(2000) Param Optimization +Maximum number of VALUEs handled during a single find_base_term call. + -param=max-vrp-switch-assertions= Common Joined UInteger Var(param_max_vrp_switch_assertions) Init(10) Param Optimization Maximum number of assertions to add along the default edge of a switch statement during VRP. -- cgit v1.1 From 314b91220a07bd63f13c58e37f1b5b9430a3702b Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 9 Mar 2020 14:13:04 +0100 Subject: Restore alignment in rs6000 target. PR target/93800 * config/rs6000/rs6000.c (rs6000_option_override_internal): Remove set of str_align_loops and str_align_jumps as these should be set in previous 2 conditions in the function. PR target/93800 * gcc.target/powerpc/pr93800.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.c | 5 ----- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/pr93800.c | 14 ++++++++++++++ 4 files changed, 26 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93800.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9c4e75..6c4a505 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-09 Martin Liska + + PR target/93800 + * config/rs6000/rs6000.c (rs6000_option_override_internal): + Remove set of str_align_loops and str_align_jumps as these + should be set in previous 2 conditions in the function. + 2020-03-09 Jakub Jelinek PR rtl-optimization/94045 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ecbf7ae..848a4ef 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4363,11 +4363,6 @@ rs6000_option_override_internal (bool global_init_p) str_align_loops = "16"; } } - - if (flag_align_jumps && !str_align_jumps) - str_align_jumps = "16"; - if (flag_align_loops && !str_align_loops) - str_align_loops = "16"; } /* Arrange to save and restore machine status around nested functions. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cf7243d..e4885b2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-09 Martin Liska + + PR target/93800 + * gcc.target/powerpc/pr93800.c: New test. + 2020-03-09 Bin Cheng * g++.dg/coroutines/torture/co-ret-15-default-return_void.C: New. diff --git a/gcc/testsuite/gcc.target/powerpc/pr93800.c b/gcc/testsuite/gcc.target/powerpc/pr93800.c new file mode 100644 index 0000000..f8dfbe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr93800.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=860 -O2" } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-final { scan-assembler-not "\\.p2align 4" } } */ + +volatile int g; +int f(int a, int b) +{ + int i; + + for (i = 0; i < b; i++) + a += g; + return a; +} -- cgit v1.1 From 157e23d8803dda38d7d38404bcc4284ce2dce3b5 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 9 Mar 2020 13:15:10 +0000 Subject: [testsuite][arm] Fix typo in fuse-caller-save.c 2020-03-09 Christophe Lyon * gcc.target/arm/fuse-caller-save.c: Fix DejaGnu typo. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arm/fuse-caller-save.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e4885b2..d8719a4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-09 Christophe Lyon + + * gcc.target/arm/fuse-caller-save.c: Fix DejaGnu typo. + 2020-03-09 Martin Liska PR target/93800 diff --git a/gcc/testsuite/gcc.target/arm/fuse-caller-save.c b/gcc/testsuite/gcc.target/arm/fuse-caller-save.c index 1308c98..8fa189f 100644 --- a/gcc/testsuite/gcc.target/arm/fuse-caller-save.c +++ b/gcc/testsuite/gcc.target/arm/fuse-caller-save.c @@ -22,4 +22,4 @@ main (void) /* For thumb1, r3 is considered likely spilled, and treated differently in ira_build_conflicts, which inhibits the fipa-ra optimization. */ -/* { dg-final { scan-assembler-times "mov\tr[123], r0" 1 { target { ! arm_thumb1 } } } } */ +/* { dg-final { scan-assembler-times "mov\tr\[123\], r0" 1 { target { ! arm_thumb1 } } } } */ -- cgit v1.1 From 8475f2902a2e2ca5f7ace8bc5265bd1a815dda20 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Thu, 5 Mar 2020 14:07:25 -0500 Subject: c++: Fix ABI issue with alignas on armv7hl [PR94050] The static_assert in the following test was failing on armv7hl because we were disregarding the alignas specifier on Cell. BaseShape's data takes up 20B on 32-bit architectures, but we failed to round up its TYPE_SIZE. This happens since the patch: here, in layout_class_type for TenuredCell, we see that the size of TenuredCell and its CLASSTYPE_AS_BASE match, so we set CLASSTYPE_AS_BASE (t) = t; While TYPE_USER_ALIGN of TenuredCell was 0, because finalize_type_size called from finish_record_layout reset it, TYPE_USER_ALIGN of its CLASSTYPE_AS_BASE still remained 1. After we replace it, it's no longer 1. Then we perform layout_empty_base_or_field for TenuredCell and since TYPE_USER_ALIGN of its CLASSTYPE_AS_BASE is now 0, we don't do this adjustment: if (CLASSTYPE_USER_ALIGN (type)) { rli->record_align = MAX (rli->record_align, CLASSTYPE_ALIGN (type)); if (warn_packed) rli->unpacked_align = MAX (rli->unpacked_align, CLASSTYPE_ALIGN (type)); TYPE_USER_ALIGN (rli->t) = 1; } where rli->t is BaseShape. Then finalize_record_size won't use the correct rli->record_align and therefore /* Round the size up to be a multiple of the required alignment. */ TYPE_SIZE (rli->t) = round_up (unpadded_size, TYPE_ALIGN (rli->t)); after this we end up with the wrong size. Since the original fix was to avoid creating extra copies for LTO purposes, I think the following fix should be acceptable. PR c++/94050 - ABI issue with alignas on armv7hl. * class.c (layout_class_type): Don't replace a class's CLASSTYPE_AS_BASE if their TYPE_USER_ALIGN don't match. * g++.dg/abi/align3.C: New test. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/class.c | 4 ++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/abi/align3.C | 12 ++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/g++.dg/abi/align3.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 128880b..5fc3e7d 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-09 Marek Polacek + + PR c++/94050 - ABI issue with alignas on armv7hl. + * class.c (layout_class_type): Don't replace a class's + CLASSTYPE_AS_BASE if their TYPE_USER_ALIGN don't match. + 2020-03-09 Bin Cheng * coroutines.cc (build_actor_fn): Factor out code inserting the diff --git a/gcc/cp/class.c b/gcc/cp/class.c index b3787f7..5340799 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -6705,6 +6705,10 @@ layout_class_type (tree t, tree *virtuals_p) /* If we didn't end up needing an as-base type, don't use it. */ if (CLASSTYPE_AS_BASE (t) != t + /* If T's CLASSTYPE_AS_BASE is TYPE_USER_ALIGN, but T is not, + replacing the as-base type would change CLASSTYPE_USER_ALIGN, + causing us to lose the user-specified alignment as in PR94050. */ + && TYPE_USER_ALIGN (t) == TYPE_USER_ALIGN (CLASSTYPE_AS_BASE (t)) && tree_int_cst_equal (TYPE_SIZE (t), TYPE_SIZE (CLASSTYPE_AS_BASE (t)))) CLASSTYPE_AS_BASE (t) = t; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d8719a4..6c0fab6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-09 Marek Polacek + + PR c++/94050 - ABI issue with alignas on armv7hl. + * g++.dg/abi/align3.C: New test. + 2020-03-09 Christophe Lyon * gcc.target/arm/fuse-caller-save.c: Fix DejaGnu typo. diff --git a/gcc/testsuite/g++.dg/abi/align3.C b/gcc/testsuite/g++.dg/abi/align3.C new file mode 100644 index 0000000..a56693a --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/align3.C @@ -0,0 +1,12 @@ +// PR c++/94050 - ABI issue with alignas on armv7hl. +// { dg-do compile { target c++11 } } + +struct alignas(8) Cell {}; +struct TenuredCell : public Cell {}; +struct BaseShape : public TenuredCell { + void *p; + unsigned q, r; + void *s; + __UINTPTR_TYPE__ t; +}; +static_assert (sizeof (BaseShape) % 8 == 0, ""); -- cgit v1.1 From 9439378f7a08cf9c8f524c9f3758a37d804ac106 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Thu, 5 Mar 2020 12:52:35 -0600 Subject: rs6000: Fix -mlong-double documentation gcc/ChangeLog 2020-03-09 Carl Love * config/rs6000/rs6000.opt: Update the description of the command line option. --- gcc/config/rs6000/rs6000.opt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index ed3b44a..f95b827 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -414,7 +414,8 @@ Warn about deprecated 'vector long ...' AltiVec type usage. mlong-double- Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save --mlong-double-[64,128] Specify size of long double. +Use -mlong-double-64 for 64-bit IEEE floating point format. Use +-mlong-double-128 for 128-bit floating point format (either IEEE or IBM). ; This option existed in the past, but now is always on. mlra -- cgit v1.1 From a931bb50fe77446058166b50eea4e53223ad7ef7 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Mon, 9 Mar 2020 09:45:23 -0700 Subject: Fix 'A' operand modifier: PR inline-asm/94095 The problem here is there was a typo in the documentation for the 'A' modifier in the table, it was recorded as 'a' in the table on the modifier column. Committed as obvious. 2020-03-09 Andrew Pinski PR inline-asm/94095 * doc/extend.texi (x86 Operand Modifiers): Fix column for 'A' modifier. --- gcc/ChangeLog | 6 ++++++ gcc/doc/extend.texi | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6c4a505..99f0011 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-09 Andrew Pinski + + PR inline-asm/94095 + * doc/extend.texi (x86 Operand Modifiers): Fix column + for 'A' modifier. + 2020-03-09 Martin Liska PR target/93800 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 11b79a5..e0e7f54 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -10437,7 +10437,7 @@ The table below shows the list of supported modifiers and their effects. @multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} {@samp{att}} {@samp{intel}} @headitem Modifier @tab Description @tab Operand @tab @samp{att} @tab @samp{intel} -@item @code{a} +@item @code{A} @tab Print an absolute memory reference. @tab @code{%A0} @tab @code{*%rax} -- cgit v1.1 From 5dc1390b41db5c1765e25fd21dad1a930a015aac Mon Sep 17 00:00:00 2001 From: "Vladimir N. Makarov" Date: Mon, 9 Mar 2020 14:05:09 -0400 Subject: Revert: One more patch for PR93564: Prefer smaller hard regno when we do not honor reg alloc order. 2020-03-09 Vladimir Makarov Revert: 2020-02-28 Vladimir Makarov PR rtl-optimization/93564 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we do not honor reg alloc order. --- gcc/ChangeLog | 10 ++++++++++ gcc/ira-color.c | 4 +--- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 99f0011..6c20ddba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2020-03-09 Vladimir Makarov + + Revert: + + 2020-02-28 Vladimir Makarov + + PR rtl-optimization/93564 + * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we + do not honor reg alloc order. + 2020-03-09 Andrew Pinski PR inline-asm/94095 diff --git a/gcc/ira-color.c b/gcc/ira-color.c index a2bf108..0ffdd19 100644 --- a/gcc/ira-color.c +++ b/gcc/ira-color.c @@ -1925,9 +1925,7 @@ assign_hard_reg (ira_allocno_t a, bool retry_p) } if (min_cost > cost) min_cost = cost; - if (min_full_cost > full_cost - || (!HONOR_REG_ALLOC_ORDER && min_full_cost == full_cost - && best_hard_regno > hard_regno)) + if (min_full_cost > full_cost) { min_full_cost = full_cost; best_hard_regno = hard_regno; -- cgit v1.1 From 81fa6d7321dd9b645d86de4a8a6967c603f176e3 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 9 Mar 2020 21:52:18 +0100 Subject: c++: Readd [LR]ROTATE_EXPR support to constexpr.c [PR94067] Since r10-6527-gaaa26bf496a646778ac861aed124d960b5bf549f fold_for_warn will perform maybe_constant_value even on some cp_fold produced trees and so can include rotate exprs which were removed last fall from constexpr.c 2020-03-09 Jakub Jelinek PR c++/94067 Revert 2019-10-11 Paolo Carlini * constexpr.c (cxx_eval_constant_expression): Do not handle RROTATE_EXPR and LROTATE_EXPR. * g++.dg/warn/Wconversion-pr94067.C: New test. --- gcc/cp/ChangeLog | 9 +++++++++ gcc/cp/constexpr.c | 4 ++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C | 9 +++++++++ 4 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 5fc3e7d..7b3b956 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,12 @@ +2020-03-09 Jakub Jelinek + + PR c++/94067 + Revert + 2019-10-11 Paolo Carlini + + * constexpr.c (cxx_eval_constant_expression): Do not handle + RROTATE_EXPR and LROTATE_EXPR. + 2020-03-09 Marek Polacek PR c++/94050 - ABI issue with alignas on armv7hl. diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c index 521c87f..76af0d7 100644 --- a/gcc/cp/constexpr.c +++ b/gcc/cp/constexpr.c @@ -5730,6 +5730,8 @@ cxx_eval_constant_expression (const constexpr_ctx *ctx, tree t, case MAX_EXPR: case LSHIFT_EXPR: case RSHIFT_EXPR: + case LROTATE_EXPR: + case RROTATE_EXPR: case BIT_IOR_EXPR: case BIT_XOR_EXPR: case BIT_AND_EXPR: @@ -7853,6 +7855,8 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, bool now, case MAX_EXPR: case LSHIFT_EXPR: case RSHIFT_EXPR: + case LROTATE_EXPR: + case RROTATE_EXPR: case BIT_IOR_EXPR: case BIT_XOR_EXPR: case BIT_AND_EXPR: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6c0fab6..44f65ff 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-09 Jakub Jelinek + + PR c++/94067 + * g++.dg/warn/Wconversion-pr94067.C: New test. + 2020-03-09 Marek Polacek PR c++/94050 - ABI issue with alignas on armv7hl. diff --git a/gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C b/gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C new file mode 100644 index 0000000..c103101 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C @@ -0,0 +1,9 @@ +// PR c++/94067 +// { dg-do compile } +// { dg-options "-Wconversion" } + +static inline unsigned short +swap (unsigned short x) +{ + return (x >> 8) | static_cast(x << 8); +} -- cgit v1.1 From d417b4f5414d9076300ab41974a14424f722688c Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Fri, 28 Feb 2020 16:57:04 -0500 Subject: c++: Fix convert_like in template [PR91465, PR93870, PR92031, PR94068] The point of this patch is to fix the recurring problem of trees generated by convert_like while processing a template that break when substituting. For instance, when convert_like creates a CALL_EXPR while in a template, substituting such a call breaks in finish_call_expr because we have two 'this' arguments. Another problem is that we can create &TARGET_EXPR<> and then fail when substituting because we're taking the address of an rvalue. I've analyzed some of the already fixed PRs and also some of the currently open ones: In c++/93870 we create EnumWrapper::operator E(&operator~(E)). In c++/87145 we create S::operator int (&{N}). In c++/92031 we create &TARGET_EXPR <0>. The gist of the problem is when convert_like_real creates a call for a ck_user or wraps a TARGET_EXPR in & in a template. So in these cases use IMPLICIT_CONV_EXPR. In a template we shouldn't need to perform the actual conversion, we only need it's result type. perform_direct_initialization_if_possible and perform_implicit_conversion_flags can also create an IMPLICIT_CONV_EXPR. Given the change above, build_converted_constant_expr can return an IMPLICIT_CONV_EXPR so call fold_non_dependent_expr rather than maybe_constant_value to deal with that. To avoid the problem of instantiating something twice in a row I'm removing a call to instantiate_non_dependent_expr_sfinae in compute_array_index_type_loc. And the build_converted_constant_expr pattern can now be simplified. 2020-03-09 Marek Polacek PR c++/92031 - bogus taking address of rvalue error. PR c++/91465 - ICE with template codes in check_narrowing. PR c++/93870 - wrong error when converting template non-type arg. PR c++/94068 - ICE with template codes in check_narrowing. * call.c (convert_like_real): Return IMPLICIT_CONV_EXPR in a template when not ck_identity and we're dealing with a class. (convert_like_real) : Return IMPLICIT_CONV_EXPR in a template if we need a temporary. * decl.c (compute_array_index_type_loc): Remove instantiate_non_dependent_expr_sfinae call. Call fold_non_dependent_expr instead of maybe_constant_value. (build_explicit_specifier): Don't instantiate or create a sentinel before converting the expression. * except.c (build_noexcept_spec): Likewise. * pt.c (convert_nontype_argument): Don't build IMPLICIT_CONV_EXPR. Set IMPLICIT_CONV_EXPR_NONTYPE_ARG if that's what build_converted_constant_expr returned. * typeck2.c (check_narrowing): Call fold_non_dependent_expr instead of maybe_constant_value. * g++.dg/cpp0x/conv-tmpl2.C: New test. * g++.dg/cpp0x/conv-tmpl3.C: New test. * g++.dg/cpp0x/conv-tmpl4.C: New test. * g++.dg/cpp0x/conv-tmpl5.C: New test. * g++.dg/cpp0x/conv-tmpl6.C: New test. * g++.dg/cpp1z/conv-tmpl1.C: New test. --- gcc/cp/ChangeLog | 22 ++++++++++++++++++++++ gcc/cp/call.c | 18 ++++++++++++++++++ gcc/cp/decl.c | 9 +++------ gcc/cp/except.c | 4 +--- gcc/cp/pt.c | 25 +++++-------------------- gcc/cp/typeck2.c | 6 +++++- gcc/testsuite/ChangeLog | 13 +++++++++++++ gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C | 21 +++++++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C | 16 ++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C | 33 +++++++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C | 13 +++++++++++++ gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C | 16 ++++++++++++++++ gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C | 10 ++++++++++ 13 files changed, 176 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 7b3b956..d9807ad 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,25 @@ +2020-03-09 Marek Polacek + + PR c++/92031 - bogus taking address of rvalue error. + PR c++/91465 - ICE with template codes in check_narrowing. + PR c++/93870 - wrong error when converting template non-type arg. + PR c++/94068 - ICE with template codes in check_narrowing. + * call.c (convert_like_real): Return IMPLICIT_CONV_EXPR + in a template when not ck_identity and we're dealing with a class. + (convert_like_real) : Return IMPLICIT_CONV_EXPR + in a template if we need a temporary. + * decl.c (compute_array_index_type_loc): Remove + instantiate_non_dependent_expr_sfinae call. Call + fold_non_dependent_expr instead of maybe_constant_value. + (build_explicit_specifier): Don't instantiate or create a sentinel + before converting the expression. + * except.c (build_noexcept_spec): Likewise. + * pt.c (convert_nontype_argument): Don't build IMPLICIT_CONV_EXPR. + Set IMPLICIT_CONV_EXPR_NONTYPE_ARG if that's what + build_converted_constant_expr returned. + * typeck2.c (check_narrowing): Call fold_non_dependent_expr instead + of maybe_constant_value. + 2020-03-09 Jakub Jelinek PR c++/94067 diff --git a/gcc/cp/call.c b/gcc/cp/call.c index c0340d9..5767a8b 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -7377,6 +7377,16 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, if (issue_conversion_warnings && (complain & tf_warning)) conversion_null_warnings (totype, expr, fn, argnum); + /* Creating &TARGET_EXPR<> in a template breaks when substituting, + and creating a CALL_EXPR in a template breaks in finish_call_expr + so use an IMPLICIT_CONV_EXPR for this conversion. We would have + created such codes e.g. when calling a user-defined conversion + function. */ + if (processing_template_decl + && convs->kind != ck_identity + && (CLASS_TYPE_P (totype) || CLASS_TYPE_P (TREE_TYPE (expr)))) + return build1 (IMPLICIT_CONV_EXPR, totype, expr); + switch (convs->kind) { case ck_user: @@ -7763,6 +7773,14 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, expr = convert_bitfield_to_declared_type (expr); expr = fold_convert (type, expr); } + + /* Creating &TARGET_EXPR<> in a template would break when + tsubsting the expression, so use an IMPLICIT_CONV_EXPR + instead. This can happen even when there's no class + involved, e.g., when converting an integer to a reference + type. */ + if (processing_template_decl) + return build1 (IMPLICIT_CONV_EXPR, totype, expr); expr = build_target_expr_with_type (expr, type, complain); } diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index e3f4b43..bb24274 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -10276,13 +10276,12 @@ compute_array_index_type_loc (location_t name_loc, tree name, tree size, NOP_EXPR with TREE_SIDE_EFFECTS; don't fold in that case. */; else { - size = instantiate_non_dependent_expr_sfinae (size, complain); size = build_converted_constant_expr (size_type_node, size, complain); /* Pedantically a constant expression is required here and so __builtin_is_constant_evaluated () should fold to true if it is successfully folded into a constant. */ - size = maybe_constant_value (size, NULL_TREE, - /*manifestly_const_eval=*/true); + size = fold_non_dependent_expr (size, complain, + /*manifestly_const_eval=*/true); if (!TREE_CONSTANT (size)) size = origsize; @@ -17607,10 +17606,8 @@ build_explicit_specifier (tree expr, tsubst_flags_t complain) /* Wait for instantiation, tsubst_function_decl will handle it. */ return expr; - expr = instantiate_non_dependent_expr_sfinae (expr, complain); - /* Don't let convert_like_real create more template codes. */ - processing_template_decl_sentinel s; expr = build_converted_constant_bool_expr (expr, complain); + expr = instantiate_non_dependent_expr_sfinae (expr, complain); expr = cxx_constant_value (expr); return expr; } diff --git a/gcc/cp/except.c b/gcc/cp/except.c index 788b96d..262ba5d 100644 --- a/gcc/cp/except.c +++ b/gcc/cp/except.c @@ -1299,10 +1299,8 @@ build_noexcept_spec (tree expr, tsubst_flags_t complain) if (TREE_CODE (expr) != DEFERRED_NOEXCEPT && !value_dependent_expression_p (expr)) { - expr = instantiate_non_dependent_expr_sfinae (expr, complain); - /* Don't let convert_like_real create more template codes. */ - processing_template_decl_sentinel s; expr = build_converted_constant_bool_expr (expr, complain); + expr = instantiate_non_dependent_expr_sfinae (expr, complain); expr = cxx_constant_value (expr); } if (TREE_CODE (expr) == INTEGER_CST) diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 1c721b3..49ee392 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -7068,26 +7068,6 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) else if (INTEGRAL_OR_ENUMERATION_TYPE_P (type) || cxx_dialect >= cxx17) { - /* Calling build_converted_constant_expr might create a call to - a conversion function with a value-dependent argument, which - could invoke taking the address of a temporary representing - the result of the conversion. */ - if (!same_type_ignoring_top_level_qualifiers_p (type, expr_type) - && ((COMPOUND_LITERAL_P (expr) - && CONSTRUCTOR_IS_DEPENDENT (expr) - && MAYBE_CLASS_TYPE_P (expr_type) - && TYPE_HAS_CONVERSION (expr_type)) - /* Similarly, converting e.g. an integer to a class - involves a constructor call. convert_like would - create a TARGET_EXPR, but in a template we can't - use AGGR_INIT_EXPR, and the TARGET_EXPR would lead - to a bogus error. */ - || (val_dep_p && MAYBE_CLASS_TYPE_P (type)))) - { - expr = build1 (IMPLICIT_CONV_EXPR, type, expr); - IMPLICIT_CONV_EXPR_NONTYPE_ARG (expr) = true; - return expr; - } /* C++17: A template-argument for a non-type template-parameter shall be a converted constant expression (8.20) of the type of the template-parameter. */ @@ -7096,6 +7076,11 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) /* Make sure we return NULL_TREE only if we have really issued an error, as described above. */ return (complain & tf_error) ? NULL_TREE : error_mark_node; + else if (TREE_CODE (expr) == IMPLICIT_CONV_EXPR) + { + IMPLICIT_CONV_EXPR_NONTYPE_ARG (expr) = true; + return expr; + } expr = maybe_constant_value (expr, NULL_TREE, /*manifestly_const_eval=*/true); expr = convert_from_reference (expr); diff --git a/gcc/cp/typeck2.c b/gcc/cp/typeck2.c index 4892089..bff4ddb 100644 --- a/gcc/cp/typeck2.c +++ b/gcc/cp/typeck2.c @@ -981,7 +981,11 @@ check_narrowing (tree type, tree init, tsubst_flags_t complain, return ok; } - init = maybe_constant_value (init); + /* Even non-dependent expressions can still have template + codes like CAST_EXPR, so use *_non_dependent_expr to cope. */ + init = fold_non_dependent_expr (init, complain); + if (init == error_mark_node) + return ok; /* If we were asked to only check constants, return early. */ if (const_only && !TREE_CONSTANT (init)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 44f65ff..f91af78 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2020-03-09 Marek Polacek + + PR c++/92031 - bogus taking address of rvalue error. + PR c++/91465 - ICE with template codes in check_narrowing. + PR c++/93870 - wrong error when converting template non-type arg. + PR c++/94068 - ICE with template codes in check_narrowing. + * g++.dg/cpp0x/conv-tmpl2.C: New test. + * g++.dg/cpp0x/conv-tmpl3.C: New test. + * g++.dg/cpp0x/conv-tmpl4.C: New test. + * g++.dg/cpp0x/conv-tmpl5.C: New test. + * g++.dg/cpp0x/conv-tmpl6.C: New test. + * g++.dg/cpp1z/conv-tmpl1.C: New test. + 2020-03-09 Jakub Jelinek PR c++/94067 diff --git a/gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C new file mode 100644 index 0000000..8a50576 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C @@ -0,0 +1,21 @@ +// PR c++/92031 - bogus taking address of rvalue error. +// { dg-do compile { target c++11 } } + +struct x { const int& l; }; + +void a(const x&) {} + +template +void f() { + a(x { 0 }); +} + +void g() { + a(x { 0 }); +} + +void +test () +{ + f(); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C new file mode 100644 index 0000000..e2021aa --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C @@ -0,0 +1,16 @@ +// PR c++/91465 - ICE with template codes in check_narrowing. +// { dg-do compile { target c++11 } } + +enum class D { X }; +enum class S { Z }; + +D foo(S) { return D{}; } +D foo(double) { return D{}; } + +template +struct Bar { + D baz(S s) + { + return D{foo(s)}; + } +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C new file mode 100644 index 0000000..966a2e1 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C @@ -0,0 +1,33 @@ +// PR c++/93870 - wrong error when converting template non-type arg. +// { dg-do compile { target c++11 } } + +template struct EnumWrapper +{ + ENUM value; + + constexpr operator ENUM() const + { + return value; + } +}; + +enum E : int { V }; + +constexpr EnumWrapper operator ~(E a) +{ + return {E(~int(a))}; +} + +template struct R +{ + static void Func(); +}; + +template struct S : R<~X> +{ +}; + +void Test() +{ + S::Func(); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C new file mode 100644 index 0000000..c83e6d8 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C @@ -0,0 +1,13 @@ +// PR c++/94068 - ICE with template codes in check_narrowing. +// { dg-do compile { target c++11 } } + +enum class A { A1, A2 }; +A foo (); +long foo (int); + +template +void +bar () +{ + const auto c{foo ()}; +} diff --git a/gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C new file mode 100644 index 0000000..2df3a6c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C @@ -0,0 +1,16 @@ +// { dg-do compile { target c++11 } } + +struct A +{ + constexpr A(int) { } + constexpr operator int() const { return 1; }; +}; + +template +struct B +{ + static constexpr A a = A(N); + int ar[a]; +}; + +B b; diff --git a/gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C b/gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C new file mode 100644 index 0000000..5b12053 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C @@ -0,0 +1,10 @@ +// PR c++/91465 - ICE with template codes in check_narrowing. +// { dg-do compile { target c++17 } } + +enum class E { Z }; + +template +void foo(F) +{ + E{char(0)}; +} -- cgit v1.1 From 983a6e7a50217f79f883ed618e696be5ce78095f Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 10 Mar 2020 00:16:15 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index cfc79aa..966f032 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200309 +20200310 -- cgit v1.1 From 8fc3727402191c1f97ab4124db442f139f7c54d3 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Mon, 9 Mar 2020 16:42:41 -0400 Subject: gdbinit.in: Fix typo. gcc/ChangeLog 2020-03-09 Jason Merrill * gdbinit.in (pgs): Fix typo in documentation. --- gcc/ChangeLog | 4 ++++ gcc/gdbinit.in | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6c20ddba..085ef66 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-03-09 Jason Merrill + + * gdbinit.in (pgs): Fix typo in documentation. + 2020-03-09 Vladimir Makarov Revert: diff --git a/gcc/gdbinit.in b/gcc/gdbinit.in index c4f400c..e951c19 100644 --- a/gcc/gdbinit.in +++ b/gcc/gdbinit.in @@ -129,7 +129,7 @@ call debug_generic_stmt ($debug_arg) end document pgs -GCC hook: pgq [tree] +GCC hook: pgs [tree] Print given GENERIC statement in C syntax. See also 'help-gcc-hooks'. end -- cgit v1.1 From c1263058ba0bc67d1767b487a1b41657db15e579 Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Tue, 10 Mar 2020 00:53:37 +0000 Subject: Update gcc sv.po. * sv.po: Update. --- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 320 +++++++++++++++++++++++++++---------------------------- 2 files changed, 163 insertions(+), 161 deletions(-) (limited to 'gcc') diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index 0f40550..baf2c0b 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2020-03-10 Joseph Myers + + * sv.po: Update. + 2020-02-27 Joseph Myers * fr.po: Update. diff --git a/gcc/po/sv.po b/gcc/po/sv.po index e649856..1459163 100644 --- a/gcc/po/sv.po +++ b/gcc/po/sv.po @@ -1,13 +1,14 @@ # Swedish messages for GCCs. -# Copyright © 2000, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019 Free Software Foundation, Inc. +# Copyright © 2000, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020 Free Software Foundation, Inc. # This file is distributed under the same license as the gcc package. # Dennis Björklund , 2000, 2001, 2002. -# Göran Uddeborg , 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019. +# Göran Uddeborg , 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020. # # Reminder to translator: GCC team does not want RCS keywords in the header! # # Dictionary: # assumed type antagen typ +# bundle bunt # cast typkonvertering # chunk stycke # kind sort @@ -22,10 +23,10 @@ # thunk snutt msgid "" msgstr "" -"Project-Id-Version: gcc 9.1.0\n" +"Project-Id-Version: gcc 10.1-b20200209\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2020-02-07 22:33+0000\n" -"PO-Revision-Date: 2019-06-04 10:48+0200\n" +"PO-Revision-Date: 2020-03-09 17:35+0100\n" "Last-Translator: Göran Uddeborg \n" "Language-Team: Swedish \n" "Language: sv\n" @@ -536,12 +537,12 @@ msgstr "Trådmodell: %s\n" #: gcc.c:6797 #, c-format msgid "Supported LTO compression algorithms: zlib" -msgstr "" +msgstr "Stödda LTO-komprimeringsalgoritmer: zlib" #: gcc.c:6799 #, c-format msgid " zstd" -msgstr "" +msgstr " zstd" #: gcc.c:6801 gcov.c:1408 gcov.c:1476 gcov.c:2813 #, c-format @@ -788,10 +789,9 @@ msgstr "" "Fel på översättningen rapporteras till \n" #: gcov-tool.c:528 -#, fuzzy, c-format -#| msgid "Copyright %s 2019 Free Software Foundation, Inc.\n" +#, c-format msgid "Copyright %s 2020 Free Software Foundation, Inc.\n" -msgstr "Copyright %s 2019 Free Software Foundation, Inc.\n" +msgstr "Copyright %s 2020 Free Software Foundation, Inc.\n" #: gcov-tool.c:531 gcov.c:929 #, c-format @@ -1266,10 +1266,8 @@ msgid "%s Same as %s." msgstr "%s Samma som %s." #: opts.c:1395 -#, fuzzy -#| msgid "variable" msgid "[available in " -msgstr "variabel" +msgstr "[tillgänglig i " #: opts.c:1427 msgid "[default]" @@ -1278,7 +1276,7 @@ msgstr "[standard]" #: opts.c:1436 #, c-format msgid "%llu bytes" -msgstr "" +msgstr "%llu byte" #: opts.c:1473 msgid "[enabled]" @@ -1329,10 +1327,8 @@ msgid "The following options are language-independent" msgstr "Följande flaggor är språkoberoende" #: opts.c:1633 -#, fuzzy -#| msgid "The following options control optimizations" msgid "The following options control parameters" -msgstr "Följande flaggor styr optimeringar" +msgstr "Följande flaggor styr parametrar" #: opts.c:1639 msgid "The following options are specific to just the language " @@ -1382,10 +1378,8 @@ msgid "*** WARNING *** there are active plugins, do not report this as a bug unl msgstr "*** VARNING *** det finns aktiva insticksmoduler, rapportera inte detta som ett fel med mindre än att du kan reproducera det utan att aktivera några insticksmoduler.\n" #: postreload-gcse.c:1354 -#, fuzzy -#| msgid "Reschedule instructions after register allocation." msgid "using simple load CSE after register allocation" -msgstr "Schemalägg om instruktioner efter registertilldelning." +msgstr "användning av enkel laddning av CSE efter registertilldelning." #. It's the compiler's fault. #: reload1.c:5997 @@ -1528,10 +1522,8 @@ msgid "call is unlikely and code size would grow" msgstr "anrop är osannolikt och kodstorleken skulle växa" #: cif-code.def:88 -#, fuzzy -#| msgid "call is unlikely and code size would grow" msgid "call is considered never executed and code size would grow" -msgstr "anrop är osannolikt och kodstorleken skulle växa" +msgstr "anropet anses aldrig kört och kodstorleken skulle växa" #: cif-code.def:92 msgid "function not declared inline and code size would grow" @@ -1626,7 +1618,7 @@ msgstr "felsökning: " #. a range of events within a path. #: diagnostic.def:44 msgid "path: " -msgstr "" +msgstr "sökväg: " #. These two would be re-classified as DK_WARNING or DK_ERROR, so the #. prefix does not matter. @@ -1985,7 +1977,7 @@ msgstr "ogiltig konvertering till typ %qT från typ %qT" #: config/aarch64/aarch64.c:21894 config/aarch64/aarch64.c:21910 #: config/arm/arm.c:32849 config/arm/arm.c:32865 msgid "operation not permitted on type %" -msgstr "" +msgstr "operationen är inte tillåten på typen %" #: config/alpha/alpha.c:5076 config/i386/i386.c:12789 #: config/rs6000/rs6000.c:13261 config/sparc/sparc.c:9354 @@ -3995,6 +3987,12 @@ msgid "" " BIND(C) feature of standard Fortran instead. */\n" "\n" msgstr "" +"/* Prototyper för externa procedurer genererade från %s\n" +" av GNU Fortran %s%s.\n" +"\n" +" Användning av detta gränssnitt avrådes ifrån, överväg att använda\n" +" funktionaliteten BIND(C) i standard Fortran istället. */\n" +"\n" #: fortran/error.c:876 msgid "Fortran 2018 deleted feature:" @@ -4423,7 +4421,7 @@ msgstr "Olika teckenlängder (%ld/%ld) i %s" #: fortran/trans-intrinsic.c:6181 #, c-format msgid "POS argument (%ld) out of range 0:%ld in intrinsic BTEST" -msgstr "" +msgstr "POS-argumentet (%ld) är utanför intervallet 0:%ld i inbyggd BTEST" #: fortran/trans-intrinsic.c:6276 #, fuzzy, c-format @@ -4434,17 +4432,17 @@ msgstr "argument ”a%d” och ”a%d” för inbyggd ”%s”" #: fortran/trans-intrinsic.c:6323 #, c-format msgid "POS argument (%ld) out of range 0:%ld in intrinsic IBITS" -msgstr "" +msgstr "POS-argumentet (%ld) är utanför intervallet 0:%ld i inbyggd IBITS" #: fortran/trans-intrinsic.c:6333 #, c-format msgid "LEN argument (%ld) out of range 0:%ld in intrinsic IBITS" -msgstr "" +msgstr "LEN-argumentet (%ld) är utanför intervallet 0:%ld i inbyggd IBITS" #: fortran/trans-intrinsic.c:6340 #, c-format msgid "POS(%ld)+LEN(%ld)>BIT_SIZE(%ld) in intrinsic IBITS" -msgstr "" +msgstr "POS(%ld)+LEN(%ld)>BIT_SIZE(%ld) i inbyggd IBITS" #: fortran/trans-intrinsic.c:6484 #, fuzzy, c-format @@ -4455,17 +4453,17 @@ msgstr "argument ”a%d” och ”a%d” för inbyggd ”%s”" #: fortran/trans-intrinsic.c:6552 #, c-format msgid "SHIFT argument (%ld) out of range -%ld:%ld in intrinsic ISHFT" -msgstr "" +msgstr "SHIFT-argumentet (%ld) är utanför intervallet -%ld:%ld i inbyggd ISHFT" #: fortran/trans-intrinsic.c:6618 #, c-format msgid "SIZE argument (%ld) out of range 1:%ld in intrinsic ISHFTC" -msgstr "" +msgstr "SIZE-argumentet (%ld) är utanför intervallet 1:%ld i inbyggd ISHFTC" #: fortran/trans-intrinsic.c:6626 fortran/trans-intrinsic.c:6671 #, c-format msgid "SHIFT argument (%ld) out of range -%ld:%ld in intrinsic ISHFTC" -msgstr "" +msgstr "SHIFT-argumentet (%ld) är utanför intervallet -%ld:%ld i inbyggd ISHFTC" #: fortran/trans-intrinsic.c:8943 #, c-format @@ -4536,7 +4534,7 @@ msgstr "Försök att DEALLOCATE oallokerad ”%s”" #: fortran/trans.c:1716 #, c-format msgid "Error reallocating to %lu bytes" -msgstr "" +msgstr "Fel vid reallokering till %lu byte" #. The remainder are real diagnostic types. #: fortran/gfc-diagnostic.def:33 @@ -4655,7 +4653,7 @@ msgstr " kodgenereringsflaggor som står i konflikt används" #: config/darwin.h:137 msgid "the y option is obsolete and ignored" -msgstr "" +msgstr "flaggan y är föråldrad och ignoreras" #: config/darwin.h:143 msgid "rdynamic is not supported" @@ -4761,7 +4759,7 @@ msgstr "%qD är inte en mall" #: config/i386/darwin.h:135 msgid "Darwin does not support -mfentry or associated options" -msgstr "" +msgstr "Darwin stödjer inte -mfentry eller tillhörande flaggor" #: config/i386/sol2.h:59 #, fuzzy @@ -4787,11 +4785,11 @@ msgstr "detta mål har omvänd byteordning" #: config/msp430/msp430.h:92 msgid "-mcode-region requires the large memory model (-mlarge)" -msgstr "" +msgstr "-mcode-region kräver den stora minnesmodellen (-mlarge)" #: config/msp430/msp430.h:94 msgid "-mdata-region requires the large memory model (-mlarge)" -msgstr "" +msgstr "-mdata-region kräver den stora minnesmodellen (-mlarge)" #: config/nios2/elf.h:44 msgid "You need a C startup file for -msys-crt0=" @@ -4969,7 +4967,7 @@ msgstr "Varna för USE-satser som inte har någon ONLY-kvalificerare." #: fortran/lang.opt:294 msgid "Warn that -fno-automatic may break recursion." -msgstr "" +msgstr "Varna för att -fno-automatic kan göra sönder rekursion." #: fortran/lang.opt:302 msgid "Warn about real-literal-constants with 'q' exponent-letter." @@ -5043,7 +5041,7 @@ msgstr "Alla inbyggda procedurer är tillgängliga oavsett av vald standard." #: fortran/lang.opt:390 msgid "Allow a BOZ literal constant to appear in an invalid context and with X instead of Z." -msgstr "" +msgstr "Tillåt en BOZ-litteralkonstant att finnas i en ogiltig kontext och med X istället för Z." #: fortran/lang.opt:398 msgid "Do not treat local variables and COMMON blocks as if they were named in SAVE statements." @@ -5103,7 +5101,7 @@ msgstr "Möjliggör användning av de korta laddinstruktionerna." #: fortran/lang.opt:465 msgid "Enable the use of character literals in assignments and data statements for non-character variables." -msgstr "" +msgstr "Aktivera användningen av teckenlitteraler i tilldelningar och datasatser för icke-teckenvariabler." #: fortran/lang.opt:470 msgid "Enable legacy parsing of INCLUDE as statement." @@ -5111,7 +5109,7 @@ msgstr "Aktivera gammaldags tolkning av INCLUDE som en sats." #: fortran/lang.opt:474 msgid "Enable default widths for i, f and g format specifiers." -msgstr "" +msgstr "Aktivera standardbredder för i-, f- och g-formatspecificerarna." #: fortran/lang.opt:478 msgid "Enable kind-specific variants of integer intrinsic functions." @@ -5265,7 +5263,7 @@ msgstr "-finit-real=\tInitiera lokala reella variabler." #: fortran/lang.opt:652 msgid "-finline-arg-packing\tPerform argument packing inline." -msgstr "" +msgstr "-finline-arg-packing\tUtför argumentpackning inline:at." #: fortran/lang.opt:656 msgid "-finline-matmul-limit=\tSpecify the size of the largest matrix for which matmul will be inlined." @@ -5373,7 +5371,7 @@ msgstr "Använd negativt tecken på nollvärden." #: fortran/lang.opt:799 msgid "Disallow tail call optimization when a calling routine may have omitted character lengths." -msgstr "" +msgstr "Tillåt inte svansanrposoptimering när en anropande rutin kan ha utelämnat teckenlängder." #: fortran/lang.opt:803 msgid "Append underscores to externally visible names." @@ -5946,7 +5944,7 @@ msgstr "Varna när indenteringen av koden inte avspeglar blockstrukturen." #: c-family/c.opt:760 msgid "Warn when a class is redeclared or referenced using a mismatched class-key." -msgstr "" +msgstr "Varna när en klass är om deklarerad eller refereras med en klassnyckel som inte stämmer." #: c-family/c.opt:764 msgid "Warn about possibly missing braces around initializers." @@ -5978,7 +5976,7 @@ msgstr "Varna när fält i en post med attributet packed är feljusterade." #: c-family/c.opt:792 msgid "Warn when a class or enumerated type is referenced using a redundant class-key." -msgstr "" +msgstr "Varna när en klass eller uppräkningstyp refereras med en överflödig klassnyckel." #: c-family/c.opt:796 msgid "Warn about missing sized deallocation functions." @@ -5998,7 +5996,7 @@ msgstr "Varna när sizeof används på en parameter som är deklarerad som en ve #: c-family/c.opt:812 msgid "Warn about calls to strcmp and strncmp used in equality expressions that are necessarily true or false due to the length of one and size of the other argument." -msgstr "" +msgstr "Varna för anrop till strcmp och strncmp som används i likhetsuttryck som nödvändigtvis är sanna eller falska på grund av längden på det ena och storleken på det andra argumentet." #: c-family/c.opt:818 msgid "Warn about buffer overflow in string manipulation functions like memcpy and strcpy." @@ -6038,7 +6036,7 @@ msgstr "Varna för hopptabeller med booleska styruttryck." #: c-family/c.opt:857 msgid "Warn about switch values that are outside of the switch's type range." -msgstr "" +msgstr "Varna för switch-värden som är utanför switch:ens typintervall." #: c-family/c.opt:861 msgid "Warn on primary template declaration." @@ -6242,7 +6240,7 @@ msgstr "Varna vid vänsterskift med ett negativt värde." #: c-family/c.opt:1112 msgid "Warn if conversion of the result of arithmetic might change the value even though converting the operands cannot." -msgstr "" +msgstr "Varna om konverteringar av resultatet av aritmetik kan ändra värdet även om konvertering av operanderna inte kan det." #: c-family/c.opt:1116 msgid "Warn about signed-unsigned comparisons." @@ -6589,7 +6587,7 @@ msgstr "Tillåt implicit konvertering mellan vektorer med olika antal underdelar #: c-family/c.opt:1629 msgid "fmax-include-depth= Set the maximum depth of the nested #include." -msgstr "" +msgstr "fmax-include-depth= Ange meximalt djup på nästade #include." #: c-family/c.opt:1633 msgid "Don't warn about uses of Microsoft extensions." @@ -7028,7 +7026,7 @@ msgstr "Anta att vi avslutar för phsa och dess libhsail-rt. Aktiverar ytterlig #: ada/gcc-interface/lang.opt:61 msgid "Dump Source Coverage Obligations." -msgstr "" +msgstr "Dumpa källkodstäckningskrav." #: ada/gcc-interface/lang.opt:65 msgid "Synonym of -gnatk8." @@ -7290,27 +7288,27 @@ msgstr "Dumpa optimeringspass." #: analyzer/analyzer.opt:27 msgid "The maximum number of 'after supernode' exploded nodes within the analyzer per supernode, before terminating analysis." -msgstr "" +msgstr "Maximala antalet ”efter supernod”-exploderade noder inom analyseraren per supernod, före analysen avslutas." #: analyzer/analyzer.opt:31 msgid "The maximum number of exploded nodes per program point within the analyzer, before terminating analysis of that point." -msgstr "" +msgstr "Det maximala antalet exploderade noder per programpunkt inom analyseraren, före analysen avslutas vid den punkten." #: analyzer/analyzer.opt:35 msgid "The maximum number of times a callsite can appear in a call stack within the analyzer, before terminating analysis of a call tha would recurse deeper." -msgstr "" +msgstr "Det maximala antalet gånger en anropssajt kan förekomma i en anropsstack inom analyseraren, före analysen avslutas av ett anrop som skulle göra en djupare rekursion." #: analyzer/analyzer.opt:39 msgid "The minimum number of supernodes within a function for the analyzer to consider summarizing its effects at call sites." -msgstr "" +msgstr "Det minsta antalet supernoder inom en funktion för att analyseraren skall överväga att summera dess effekter vid anropssajter." #: analyzer/analyzer.opt:43 msgid "Warn about code paths in which a stdio FILE can be closed more than once." -msgstr "" +msgstr "Varna för kodvägar i vilka en stdio FILE kan stängas mer än en gång." #: analyzer/analyzer.opt:47 msgid "Warn about code paths in which a pointer can be freed more than once." -msgstr "" +msgstr "Varna för kodvägar i vilka en pekare kan frigöras mer än en gång." #: analyzer/analyzer.opt:51 #, fuzzy @@ -7338,19 +7336,19 @@ msgstr "Varna för anrop med implicit gränssnitt." #: analyzer/analyzer.opt:67 msgid "Warn about code paths in which a possibly-NULL value is passed to a must-not-be-NULL function argument." -msgstr "" +msgstr "Varna för kodvägar i vilka ett möjligt NULL-värde skickas till ett får-inte-vara-NULL-funktionsargument." #: analyzer/analyzer.opt:71 msgid "Warn about code paths in which a possibly-NULL pointer is dereferenced." -msgstr "" +msgstr "Varna för kodvägar i vilka en möjlig NULL-pekare derefereras." #: analyzer/analyzer.opt:75 msgid "Warn about code paths in which an async-signal-unsafe function is called from a signal handler." -msgstr "" +msgstr "Varna för kodvägar i vilka en async-signal-unsafe-funktion anropas från en signalhanterare." #: analyzer/analyzer.opt:79 msgid "Warn about code paths in which NULL is passed to a must-not-be-NULL function argument." -msgstr "" +msgstr "Varna för kodvägar i vilka NULL skickas till ett får-inte-vara-NULL-funktionsargument" #: analyzer/analyzer.opt:83 #, fuzzy @@ -7360,11 +7358,11 @@ msgstr "Varna för fångsthanterare av icke-referenstyper." #: analyzer/analyzer.opt:87 msgid "Warn about code paths in which a longjmp rewinds to a jmp_buf saved in a stack frame that has returned." -msgstr "" +msgstr "Varna för kodvägar i vilka en longjmp hoppar tillbaka till en jmp_buf som sparades i en stackram som har returnerat." #: analyzer/analyzer.opt:91 msgid "Warn about code paths in which an unsanitized value is used as an array index." -msgstr "" +msgstr "Varna för kodvägar i vilka ett osanerat värde används som ett vektorindex." #: analyzer/analyzer.opt:95 #, fuzzy @@ -7386,79 +7384,79 @@ msgstr "Varna för variabler som initieras till sig själva." #: analyzer/analyzer.opt:107 msgid "Warn if the code is too complicated for the analyzer to fully explore." -msgstr "" +msgstr "Varna om koden är för komplicerad för att analyseraren skall kunna utforska den fullständigt." #: analyzer/analyzer.opt:111 msgid "Restrict the analyzer to run just the named checker." -msgstr "" +msgstr "Begränsa analyseraren till att köra just den namngivna kontrollen." #: analyzer/analyzer.opt:115 msgid "Avoid combining multiple statements into one exploded edge." -msgstr "" +msgstr "Undvik att kombinera flera satser till en exploderad båge." #: analyzer/analyzer.opt:119 msgid "Purge unneeded state during analysis." -msgstr "" +msgstr "Rensa ut tillstånd som inte behövs under analysen." #: analyzer/analyzer.opt:123 msgid "Merge similar-enough states during analysis." -msgstr "" +msgstr "Slå samman tillräckligt lika tillstånd under analysen." #: analyzer/analyzer.opt:127 msgid "Enable transitivity of constraints during analysis." -msgstr "" +msgstr "Aktivera transitivtet av begränsningar under analysen." #: analyzer/analyzer.opt:131 msgid "Approximate the effect of function calls to simplify analysis." -msgstr "" +msgstr "Approximera effekten av funktionsanrop för att förenkla analysen." #: analyzer/analyzer.opt:135 msgid "Emit more verbose descriptions of control flow in diagnostics." -msgstr "" +msgstr "Mata ut mer utförliga beskrivningar av styrflödet i felmeddelanden." #: analyzer/analyzer.opt:139 msgid "Emit more verbose descriptions of state changes in diagnostics." -msgstr "" +msgstr "Mata ut mer utförliga beskrivningar av tillståndsändringar i felmeddelanden." #: analyzer/analyzer.opt:143 msgid "Control which events are displayed in diagnostic paths." -msgstr "" +msgstr "Styr vilka händelser som visas i diagnostikvägar." #: analyzer/analyzer.opt:147 msgid "Dump internal details about what the analyzer is doing to SRCFILE.analyzer.txt." -msgstr "" +msgstr "Dumpa interna detaljer om vad analyseraren gör till KÄLLFIL.analyzer.txt." #: analyzer/analyzer.opt:151 msgid "Dump internal details about what the analyzer is doing to stderr." -msgstr "" +msgstr "Dumpa interna detaljer om vad analyseraren gör till standard fel." #: analyzer/analyzer.opt:155 msgid "Dump the analyzer supergraph to a SRCFILE.callgraph.dot file." -msgstr "" +msgstr "Dumpa analyserarens supergraf till en fil KÄLLFIL.callgraph.dot." #: analyzer/analyzer.opt:159 msgid "Dump the analyzer exploded graph to a SRCFILE.eg.dot file." -msgstr "" +msgstr "Dumpa analyserarens exploderade graf till en fil KÄLLFIL.eg.dot." #: analyzer/analyzer.opt:163 msgid "Emit diagnostics showing the location of nodes in the exploded graph." -msgstr "" +msgstr "Mata ut meddelanden som visar platsen för noder i den exploderade grafen." #: analyzer/analyzer.opt:167 msgid "Dump a textual representation of the exploded graph to SRCFILE.eg.txt." -msgstr "" +msgstr "Dumpa en textuell representation av den exploderade grafen till KÄLLFIL.eg.txt." #: analyzer/analyzer.opt:171 msgid "Dump a textual representation of the exploded graph to SRCFILE.eg-ID.txt." -msgstr "" +msgstr "Dumpa en textuell representation av den exploderade grafen till KÄLLFIL.eg-ID.txt." #: analyzer/analyzer.opt:175 msgid "Dump state-purging information to a SRCFILE.state-purge.dot file." -msgstr "" +msgstr "Dumpa tillståndsrensningsinformation till en fil KÄLLFIL.state-purge.dot." #: analyzer/analyzer.opt:179 msgid "Dump the analyzer supergraph to a SRCFILE.supergraph.dot file." -msgstr "" +msgstr "Dumpa analyserarens supergraf till en fil KÄLLFIL.supergraph.dot." #: config/vms/vms.opt:27 msgid "Malloc data into P2 space." @@ -7652,19 +7650,19 @@ msgstr "Versionen av ld64 som används för denna verktygskedja." #: config/darwin.opt:94 msgid "Loads all members of archive libraries" -msgstr "" +msgstr "Läser in alla medlemmar av arkivbibliotek" #: config/darwin.opt:98 msgid "-allowable_client \tThe output dylib is private to the client(s) named" -msgstr "" +msgstr "-allowable_client \tDylib-utdata är privat till de namngivna klienterna" #: config/darwin.opt:102 msgid "-arch \tSpecify that the output file should be generated for architecture \"name\"" -msgstr "" +msgstr "-arch \tAnge att utdatafilen skall genereras för arkitekturen ”namn”" #: config/darwin.opt:106 msgid "Mismatches between file architecture and the \"-arch\" are errors instead of warnings" -msgstr "" +msgstr "Brist på överensstämmelse mellan filarkitekturen och ”-arch” är fel istället för varningar" #: config/darwin.opt:110 #, fuzzy @@ -7674,55 +7672,55 @@ msgstr "Den tidigaste MacOS X-versionen som detta program kommer köra på." #: config/darwin.opt:114 msgid "Produce an output file that will bind symbols on load, rather than lazily." -msgstr "" +msgstr "Producera en utdatafil som kommer binda symboler vid laddning, snarare än lat." #: config/darwin.opt:118 msgid "Produce a Mach-O bundle (file type MH_BUNDLE)" -msgstr "" +msgstr "Producera en Mach-O-bunt (filtyp MH_BUNDLE)" #: config/darwin.opt:122 msgid "-bundle_loader \tTreat \"executable\" (that will be loading this bundle) as if it was one of the dynamic libraries the bundle is linked against for symbol resolution" -msgstr "" +msgstr "-bundle_loader \tBehandla ”körbar” (som kommer att ladda denna bunt) som om den vore en av de dynamiska bibliotek bunten länkas mot vid symbolupplösning" #: config/darwin.opt:126 msgid "-client_name \tEnable the executable being built to link against a private dylib (using allowable_client)" -msgstr "" +msgstr "-client_name \tAktivera tt den körbara byggs för att länka mot ett privat dylib (användande allowable_client)" #: config/darwin.opt:130 msgid "-compatibility_version \tSet the minimum version for the client interface. Clients must record a greater number than this or the binding will fail at runtime" -msgstr "" +msgstr "-compatibility_version \tSätt den minsta versionen för klientgränssnittet. Klienter måste registrera ett högre nummer än detta eller så kommer bindningen misslyckas vid körtillfället" #: config/darwin.opt:134 msgid "-current_version \tSet the current version for the library." -msgstr "" +msgstr "-current_version \tSätt den aktuella versionen på bibliteket." #: config/darwin.opt:138 msgid "Remove code and data that is unreachable from any exported symbol (including the entry point)" -msgstr "" +msgstr "Ta bort kod och data som är onåbar från exporterade symboler (inklusive ingångspunkten)" #: config/darwin.opt:145 msgid "Produce a Mach-O dylinker (file type MH_DYLINKER), only used for building dyld." -msgstr "" +msgstr "Producera en Mach-O-dylinker (filtyp MH_DYLINKER), endast använd för att bygga dyld." #: config/darwin.opt:149 msgid "-dylinker_install_name \tOnly used for building dyld." -msgstr "" +msgstr "-dylinker_install_name \tAnvänds endast för att bygga dyld." #: config/darwin.opt:153 msgid "The default (and opposite of -static), implied by user mode executables, shared libraries and bundles." -msgstr "" +msgstr "Standard (och motsats till -static), implicerat av användarläges körbara, delade bibliotek och buntar." #: config/darwin.opt:157 msgid "Produce a Mach-O shared library (file type MH_DYLIB), synonym for -shared" -msgstr "" +msgstr "Producera ett Mach-O delat bibliotek (filtyp MH_DYLIB), synonym till -shared" #: config/darwin.opt:161 msgid "-exported_symbols_list \tGlobal symbols in \"filename\" will be exported from the linked output file, any symbols not mentioned will be treated as hidden." -msgstr "" +msgstr "-exported_symbols_list \tBlobala symboler i ”filenamn” kommer att exporteras från den länkade utdatafilen, alla symboler som inte näns kommer hanteras som dolda." #: config/darwin.opt:165 msgid "Supply a list of objects to be linked from a file, rather than the command line" -msgstr "" +msgstr "Ge en lista av objekt att länkas från en fil, istället för kommandoraden" #: config/darwin.opt:169 config/darwin.opt:189 #, fuzzy @@ -7732,71 +7730,71 @@ msgstr "Generera kod för darwin laddbara kärnutvidgningar." #: config/darwin.opt:173 msgid "Ignore the normal two-level namespace; resolve symbols in command line order and do not record which library provided the resolved symbol." -msgstr "" +msgstr "Ignorera den normala tvånivånamnrymden; slå upp symboler i kommandoradsordning och notera inte vilket bibliotek som tillhandahäll den upplösta symbolen." #: config/darwin.opt:177 msgid "For the assembler (and linker) permit any architecture sub-variant to be used without error." -msgstr "" +msgstr "För assemblern (och länkaren) tillåt alla arkitekturundervarienter att användas utan fel." #: config/darwin.opt:181 msgid "Set the output object such that, on loading, dyld will ignore any two-level information and resolve symbols in the discovery order for loaded libs." -msgstr "" +msgstr "Sätt utdataobjektet så att, vid laddning, dyld kommer ignorera tvånivåinformation och lösa upp symboler i upptäcktsordning från de laddade biblioteken." #: config/darwin.opt:185 msgid "-framework \tThe linker should search for the named framework in the framework search path." -msgstr "" +msgstr "-framework \tLäkaren skall söka efter det namngivna ramverket i sökvägen för ramverk." #: config/darwin.opt:193 msgid "Abbreviation for \"-g -fno-eliminate-unused-debug-symbols\"" -msgstr "" +msgstr "Förkortning för ”-g -fno-eliminate-unused-debug-symbols”" #: config/darwin.opt:197 msgid "Abbreviation for \"-g -feliminate-unused-debug-symbols\"" -msgstr "" +msgstr "Förkortning för ”-g -feliminate-unused-debug-symbols”" #: config/darwin.opt:201 msgid "Automatically adds space for longer path names in load commands (up to MAXPATHLEN)" -msgstr "" +msgstr "Lägger automatiskt till mellanslag för längre sökvägsnamn i laddkommandon (upp till MAXPATHLEN)" #: config/darwin.opt:205 msgid "-image_base
\tChoose a base address for a dylib or bundle." -msgstr "" +msgstr "-image_base \tVälj en basadress för ett dylib eller en bunt." #: config/darwin.opt:209 msgid "-init \tThe symbol \"symbol_name\" will be used as the first initialiser for a dylib." -msgstr "" +msgstr "-init \tSymbolen ”symbolnamn” kommer användas som den första initieraren för ett dylib." #: config/darwin.opt:213 msgid "-install_name \tSet the install name for a dylib." -msgstr "" +msgstr "-install_name \tAnge installationsnamnet för ett dylib." #: config/darwin.opt:217 msgid "Usually \"private extern\" (hidden) symbols are made local when linking, this command suppresses that such that they remain exported." -msgstr "" +msgstr "Vanligen görs ”private extern” (dolda) symboler lokala vid länkning, detta kommando undertrycker det så att de behålls exporterade." #: config/darwin.opt:221 msgid "(Obsolete after 10.4) Multi modules are ignored at runtime since MacOS 10.4" -msgstr "" +msgstr "(Föråldrat efter 10.4) Multimoduler ignoreras vid körtillfället sedan MacOS 10.4" #: config/darwin.opt:225 msgid "(Obsolete after 10.4) -multiply_defined Provided a mechanism for warning about symbols defined in multiple dylibs." -msgstr "" +msgstr "(Föråldrat efter 10.4) -multiply_defined Tillhandahåller en mekanism för varningar för symboler definierade i flera dylib.\"" #: config/darwin.opt:229 msgid "(Obsolete after 10.4) -multiply_defined_unused \tProvided a mechanism for warning about symbols defined in the current executable also being defined in linked dylibs." -msgstr "" +msgstr "(Föråldrat efter 10.4) -multiply_defined_unused \tTillhandahåller en mekansism för varningar för symboler definierade i den aktuella körbara som också är definierade i inlänkade dylib." #: config/darwin.opt:233 msgid "(Obsolete) The linker never dead strips these items, so the option is not needed." -msgstr "" +msgstr "(Föråldrat) Länkaren dödrensar aldrig dessa poster, så flaggan behövs inte." #: config/darwin.opt:237 msgid "(Obsolete after 10.3.9) Set MH_NOPREFIXBINDING, in an exectuable." -msgstr "" +msgstr "(Föråldrat efter 10.3.9) Sätt MH_NOPREFIXBINDING i en körbar." #: config/darwin.opt:241 msgid "(Obsolete after 10.4)\tSet MH_NOMULTIDEFS in an umbrella framework." -msgstr "" +msgstr "(Föråldrat efter 10.4)\tSätt MH_NOMULTIDEFS i ett paraplyramverk." #: config/darwin.opt:245 config/darwin.opt:260 config/darwin.opt:264 #, fuzzy @@ -7812,47 +7810,47 @@ msgstr "Lagrar dubbla i 32 bitar. Detta är standard." #: config/darwin.opt:256 msgid "-pagezero_size size\tAllows setting the page 0 size to 4kb for certain special cases." -msgstr "" +msgstr "-pagezero_size storlek\tTillåter att sätta storleken på sida 0 till 4 kb för vissa specialfall." #: config/darwin.opt:268 msgid "Produces a Mach-O file suitable for embedded/ROM use." -msgstr "" +msgstr "Producerar en Mach-O-fil lämplig för inbäddad/ROM-användning." #: config/darwin.opt:272 msgid "(Obsolete) Allowed linking to proceed with \"-flat_namespace\" when a linked bundle contained a symbol also exported from the main executable." -msgstr "" +msgstr "(Föråldrat) Tillåt läkningen att gå vidare med ”-flat_namespace” när en läkad bunt innehåller en symbol som också exporteras från huvudprogrammet." #: config/darwin.opt:279 msgid "Synonym for \"-export-dynamic\" for linker versions that support it." -msgstr "" +msgstr "Synonym för ”-export-dynamic” för läkarversioner som stödjer det." #: config/darwin.opt:283 msgid "-read_only_relocs \tThis will allow relocs in read-only pages (not advisable)." -msgstr "" +msgstr "-read_only_relocs \tDetta kommer tillåta omlokaliseringar i endast läsbara sidor (inte att rekommendera)." #: config/darwin.opt:287 msgid "-sectalign \tSet section \"sectname\" in segment \"segname\" to have alignment \"value\" which must be an integral power of two expressed in hexadecimal form." -msgstr "" +msgstr "-sectalign \tSätt sektionen ”sektnamn” i segment ”segnamn” till att ha justeringen ”värde” vilket måste vara en heltalspotens av två uttryckt på hexadecimal form." #: config/darwin.opt:291 msgid "-sectcreate \tCreate section \"sectname\" in segment \"segname\" from the contents of \"file\"." -msgstr "" +msgstr "-sectcreate \tSkapa sektionen ”sektname” i segmentet ”segnamn” från innehållet i ”file”." #: config/darwin.opt:295 msgid "(Obsolete) -sectobjectsymbols \tSetting a local symbol at the start of a section is no longer supported." -msgstr "" +msgstr "(Föråldrat) -sectobjectsymbols \tAtt sätta en lokal symbol vid början av en sektion stödjs inte längre." #: config/darwin.opt:299 msgid "(Obsolete) -sectorder orderfile\tReplaced by a more general option \"-order_file\"." -msgstr "" +msgstr "(Föråldrat) -sectorder ordningsfil\tErsatt av en mer generell flagga ”-order_file”." #: config/darwin.opt:303 msgid "-seg_addr_table \tSpecify the base addresses for dynamic libraries, \"file\" contains a line for each library." -msgstr "" +msgstr "-seg_addr_table \tAnge basadresserna för dynamiska bibliotek, ”fil” innehåller en rad för varje bibliotek." #: config/darwin.opt:308 msgid "(Obsolete, ld_classic only) -seg_addr_table_filename " -msgstr "" +msgstr "(Föråldrat, endast ld_classic) -seg_addr_table_filename " #: config/darwin.opt:312 #, fuzzy @@ -7862,27 +7860,27 @@ msgstr "Synonym för -Wcomment." #: config/darwin.opt:316 msgid "-segaddr
\tSet the base address of segment \"name\" to \"address\" which must be aligned to a page boundary (currently 4kb)." -msgstr "" +msgstr "-segaddr \tSätt basadressen för segment ”namn” till ”adress” som måste vara justerad till en sidgräns (för närvarande 4 kB)." #: config/darwin.opt:321 msgid "(Obsolete, ld_classic only) -sectcreate segname sectname file" -msgstr "" +msgstr "(Föråldrat, endast ld_classic) -sectcreate segnamn sektnamn fil" #: config/darwin.opt:325 msgid "(Obsolete) Object files with LINKEDIT sections are no longer supported." -msgstr "" +msgstr "(Föråldrat) Objektfiler med LINKEDIT-sektioner stödjs inte längre." #: config/darwin.opt:329 msgid "-segprot max_prot init_prot\tThe protection values are \"r\", \"w\", \"x\" or \"-\" the latter meaning \"no access\"." -msgstr "" +msgstr "-segprot max_skydd init_skydd\tSkyddsvärden är ”r”, ”w”, ”x” eller ”-” det sistnmända betyder ”ingen åtkomst”." #: config/darwin.opt:333 msgid "-segs_read_only_addr address \tAllows specifying the address of the read only portion of a dylib." -msgstr "" +msgstr "-segs_read_only_addr adress \tMöjliggör att ange adressen till den endast läsbara delen av ett dylib." #: config/darwin.opt:337 msgid "-segs_read_write_addr address \tAllows specifying the address of the read/write portion of a dylib." -msgstr "" +msgstr "-segs_read_write_addr adress \tMöjliggör att ange adressen till den läs-/skrivbara delen av ett dylib." #: config/darwin.opt:341 #, fuzzy @@ -7892,11 +7890,11 @@ msgstr "Lagrar dubbla i 32 bitar. Detta är standard." #: config/darwin.opt:345 msgid "-sub_library \tLibrary named \"name\" will be re-exported (only useful for dylibs)." -msgstr "" +msgstr "-sub_library \tBiblioteket med namnet ”namn” kommer omexporteras (endast meningsfullt för dylib:ar)." #: config/darwin.opt:349 msgid "-sub_umbrella \tFramework named \"name\" will be re-exported (only useful for dylibs)." -msgstr "" +msgstr "-sub_umbrella \tRamverket med namnet ”namn” kommer omexporteras (endast meningsfullt för dylib:ar)." #: config/darwin.opt:353 #, fuzzy @@ -7906,39 +7904,39 @@ msgstr "detta är den första default-etiketten" #: config/darwin.opt:357 msgid "Specifies content that can speed up dynamic loading when the binaries are unchanged." -msgstr "" +msgstr "Anger innehåll som kan snabba upp den dynamiska laddningen när binärer är oförändrade." #: config/darwin.opt:361 msgid "-umbrella \tThe specified framework will be re-exported." -msgstr "" +msgstr "-umbrella \tDet angivna ramverket kommer omexporteras." #: config/darwin.opt:365 msgid "-undefined \tSpecify the handling for undefined symbols (default is error)." -msgstr "" +msgstr "-undefined \tAnge hanteringen av odefinierade symboler (standard är fel)." #: config/darwin.opt:369 msgid "-unexported_symbols_list \tDon't export global symbols listed in filename." -msgstr "" +msgstr "-unexported_symbols_list \tExportera inte globala symboler uppräknade i filnamn." #: config/darwin.opt:373 msgid "-weak_reference_mismatches \tSpecifies what to do if a symbol import conflicts between file (weak in one and not in another) the default is to treat the symbol as non-weak." -msgstr "" +msgstr "-weak_reference_mismatches \tAnger vad som skall göras om en symbolimport orsakar en konflikt mellan filer (svag i en och inte i en annan) standard är att hantera symbolen som icke svag." #: config/darwin.opt:377 msgid "Logs the object files the linker loads" -msgstr "" +msgstr "Loggar objektfiler och länkarladdningar" #: config/darwin.opt:381 msgid "Logs which symbol(s) caused an object to be loaded." -msgstr "" +msgstr "Loggar vilka symboler som orsakade att ett objekt laddades." #: config/darwin.opt:389 msgid "(Obsolete, ignored)\tOld support similar to whyload." -msgstr "" +msgstr "(Föråldrat, ignoreras)\tGammalt stöd liknande whyload." #: config/darwin.opt:393 msgid "(Obsolete and unhandled by ld64, ignored)\tld should produce an executable (only handled by ld_classic)." -msgstr "" +msgstr "(Föråldrat och ohanterat av ld64, ignoreras)\tld skall skapa en körbar (endast hanterat av ld_classic)." #: config/bfin/bfin.opt:40 config/msp430/msp430.opt:3 config/c6x/c6x.opt:38 msgid "Use simulator runtime." @@ -8297,7 +8295,7 @@ msgstr "-memregs=\tAntal memreg-byte (standard: 16, intervall: 0..16)." #: config/msp430/msp430.opt:7 msgid "Use a lightweight configuration of printf and puts to reduce code size. For single-threaded applications, not requiring reentrant I/O only. Requires Newlib Nano IO." -msgstr "" +msgstr "Använd en lättviktig konfiguration av printf och puts för att reducera kodstorlek. För enkeltrådade program kräver ej återanropsbar I/O. Kräver Newlib Nano IO." #: config/msp430/msp430.opt:11 msgid "Force assembly output to always use hex constants." @@ -8313,7 +8311,7 @@ msgstr "Varna om ett MCU-namn inte känns igen eller står i konflikt med andra #: config/msp430/msp430.opt:23 msgid "Warn if devices.csv is not found or there are problem parsing it (default: on)." -msgstr "" +msgstr "Varna om devices.csv inte finns eller det är problem med att tolkan den (standard: på)." #: config/msp430/msp430.opt:27 msgid "Specify the ISA to build for: msp430, msp430x, msp430xv2." @@ -8341,15 +8339,15 @@ msgstr "Ange typen av hårdvarumultiplikation att stödja." #: config/msp430/msp430.opt:75 msgid "Specify whether functions should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower)." -msgstr "" +msgstr "Ange huruvida funktioner skall placeras i de lägre eller övre minnesregionerna, eller om de skall blandas mellan regionerna (endera) för bästa passning (standard: nedre)." #: config/msp430/msp430.opt:79 msgid "Specify whether variables should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower)." -msgstr "" +msgstr "Ange huruvida variabler skall placeras i de lägre eller övre minnesregionerna, eller om de skall blandas mellan regionerna (endera) för bästa passning (standard: nedre)." #: config/msp430/msp430.opt:83 msgid "Add the .lower prefix to section names when compiling with -m{code,data}-region=lower (disabled by default)." -msgstr "" +msgstr "Lägg till prefixet .lower till sektionsnamn vid kompilering med -m{code,data}-region=lower (avaktiverat som standard)." #: config/msp430/msp430.opt:102 msgid "Passes on a request to the assembler to enable fixes for various silicon errata." @@ -8361,7 +8359,7 @@ msgstr "Skickar vidare en begäran till assemblern att varna för diverse kisele #: config/msp430/msp430.opt:110 msgid "The path to devices.csv. The GCC driver can normally locate devices.csv itself and pass this option to the compiler, so the user shouldn't need to pass this." -msgstr "" +msgstr "Söktvägen till devices.csv. GCC drivrutinen kan normalt hitta devices.csv själv och skicka denna flagga till kompilatorn, så skall inte behöva skicka denna." #: config/aarch64/aarch64.opt:43 msgid "The possible TLS dialects:" @@ -8502,7 +8500,7 @@ msgstr "Generera ett anrop till abort om en noreturn-funktion returnerar." #: config/aarch64/aarch64.opt:264 msgid "When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization." -msgstr "" +msgstr "Vid vektorisering för SVE, överväg att använda opackade vektorer för mindre element och använd kostnadsmodellen för att välja den billigaste metoden. Använd även kostnadsmodellen för att välja mellan SVE- och avanserad SIMD-vektorisering." #: config/linux.opt:24 msgid "Use Bionic C library." @@ -8832,11 +8830,11 @@ msgstr "Skicka inte ut utökade register på stacken i övervakningsfunktioner." #: config/pru/pru.opt:31 msgid "-mmcu=MCU\tSelect the target System-On-Chip variant that embeds this PRU." -msgstr "" +msgstr "-mmcu=MCU\tVälj målsystemkretsvariant (SoC) som bäddar in denna PRU." #: config/pru/pru.opt:35 msgid "Make GCC pass the --no-relax command-line option to the linker instead of the --relax option." -msgstr "" +msgstr "Låt GCC skicka kommandoradsflaggan --no-relax till länkaren istället för flaggan --relax." #: config/pru/pru.opt:40 #, fuzzy @@ -9726,7 +9724,7 @@ msgstr "Anroparen kopierar funktionsargument som skickas via dold referens." #: config/pa/pa.opt:50 msgid "Use ldcw/ldcd coherent cache-control hint." -msgstr "" +msgstr "Använd koherent cache-styrningstipsen ldcw/ldcd." #: config/pa/pa.opt:54 msgid "Disable FP regs." @@ -9762,7 +9760,7 @@ msgstr "Avaktivera utrymmesregister." #: config/pa/pa.opt:99 msgid "Assume memory references are ordered and barriers are not needed." -msgstr "" +msgstr "Anta att minnesreferenser är ordnade och att barriärer inte behövs." #: config/pa/pa.opt:115 msgid "Use portable calling conventions." @@ -10074,11 +10072,11 @@ msgstr "Anta att all data i statisk lagring kan kommas åt med LDS/STS. Denna f #: config/avr/avr.opt:120 msgid "-mdouble=\tUse bits wide double type." -msgstr "" +msgstr "-mdouble=\tAnvänd bitar bred double-typ." #: config/avr/avr.opt:124 msgid "-mlong-double=\tUse bits wide long double type." -msgstr "" +msgstr "-mlong-double=\tAnvänd bitar bred long double-typ." #: config/avr/avr.opt:128 msgid "Do not link against the device-specific library lib.a." @@ -10092,7 +10090,7 @@ msgstr "Länka inte mot det enhetsspecifika biblioteket lib.a." #: config/avr/avr.opt:136 msgid "Available BITS selections:" -msgstr "" +msgstr "Tillgängliga val av BITAR:" #: config/m32r/m32r.opt:34 msgid "Compile for the m32rx." @@ -11257,23 +11255,23 @@ msgstr "Konfigurera kortspecifik körtid." #: config/or1k/elf.opt:32 msgid "This option is ignored; it is provided for compatibility purposes only. This used to select linker and preprocessor options for use with newlib." -msgstr "" +msgstr "Denna flagga ignoreras; den tillhandahålls endast för kompatibilitetsskäl. Detta brukade välja flaggor till länkare och preprocessor för användning med newlib." #: config/or1k/or1k.opt:26 msgid "Enable generation of hardware divide (l.div, l.divu) instructions. This is the default; use -msoft-div to override." -msgstr "" +msgstr "Aktivera generering av hårdvarudivisionsinstruktioner (l.div, l.divu). Detta är standard; använd -msoft-div för att åsidosätta." #: config/or1k/or1k.opt:31 msgid "Enable generation of binaries which use functions from libgcc to perform divide operations. The default is -mhard-div." -msgstr "" +msgstr "Aktivera generering av binärer som använder funktioner från libgcc för att utföra divisionsoperationer. Standard är -mhard-div." #: config/or1k/or1k.opt:36 msgid "Enable generation of hardware multiply instructions (l.mul, l.muli) instructions. This is the default; use -msoft-mul to override." -msgstr "" +msgstr "Aktivera generering av hårdvarumultiplikationsinstruktioner (l.mul, l.muli). Detta är standard; använd -msoft-mul för att åsidosätta." #: config/or1k/or1k.opt:41 msgid "Enable generation of binaries which use functions from libgcc to perform multiply operations. The default is -mhard-mul." -msgstr "" +msgstr "Aktivera generering av binärer som använder funktioner från libgcc för att utföra multiplikationsoperationer. Standard är -mhard-mul." #: config/or1k/or1k.opt:46 msgid "Enable generation of binaries which use functions from libgcc to perform floating point operations. This is the default; use -mhard-float to override." -- cgit v1.1 From cc5c935937d01d96c6b070dae31854180249064c Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 10 Mar 2020 09:26:44 +0100 Subject: i386: Fix up *testqi_ext_3 insn&split for the *testdi_1 changes [PR94088] In r10-1938-g460bf043c8266dd080308f4783137aee0d0f862c *testdi_1 has been changed, so that if the mask has upper 32-bits 0 and then at least one bit set, it requires CCZmode rather than CCNOmode, because in that case it uses testl instruction rather than testq and so the SF flag wouldn't respect the state of the 64-bit result. The *testqi_ext_3 define_insn_and_split needs to match that though, otherwise it can create an RTL pattern that used to match *testdi_1 but doesn't anymore and we'd ICE due to an unrecognizable insn. 2020-03-10 Jakub Jelinek PR target/94088 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with CCZmode instead of CCNOmode if operands[2] has DImode and pos + len is 32. * gcc.target/i386/pr94088.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/i386.md | 17 +++++++++++------ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr94088.c | 9 +++++++++ 4 files changed, 32 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr94088.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 085ef66..5d5bbf4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-10 Jakub Jelinek + + PR target/94088 + * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with + CCZmode instead of CCNOmode if operands[2] has DImode and pos + len + is 32. + 2020-03-09 Jason Merrill * gdbinit.in (pgs): Fix typo in documentation. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a4ee549..8b5ae34 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8826,18 +8826,23 @@ (match_operand 3 "const_int_operand" "n") (match_operand 4 "const_int_operand" "n")) (const_int 0)]))] - "ix86_match_ccmode (insn, CCNOmode) - && ((TARGET_64BIT && GET_MODE (operands[2]) == DImode) - || GET_MODE (operands[2]) == SImode - || GET_MODE (operands[2]) == HImode - || GET_MODE (operands[2]) == QImode) + "((TARGET_64BIT && GET_MODE (operands[2]) == DImode) + || GET_MODE (operands[2]) == SImode + || GET_MODE (operands[2]) == HImode + || GET_MODE (operands[2]) == QImode) /* Ensure that resulting mask is zero or sign extended operand. */ && INTVAL (operands[4]) >= 0 && ((INTVAL (operands[3]) > 0 && INTVAL (operands[3]) + INTVAL (operands[4]) <= 32) || (mode == DImode && INTVAL (operands[3]) > 32 - && INTVAL (operands[3]) + INTVAL (operands[4]) == 64))" + && INTVAL (operands[3]) + INTVAL (operands[4]) == 64)) + && ix86_match_ccmode (insn, + /* *testdi_1 requires CCZmode if the mask has bit + 31 set and all bits above it clear. */ + GET_MODE (operands[2]) == DImode + && INTVAL (operands[3]) + INTVAL (operands[4]) == 32 + ? CCZmode : CCNOmode)" "#" "&& 1" [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f91af78..5ed497d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-10 Jakub Jelinek + + PR target/94088 + * gcc.target/i386/pr94088.c: New test. + 2020-03-09 Marek Polacek PR c++/92031 - bogus taking address of rvalue error. diff --git a/gcc/testsuite/gcc.target/i386/pr94088.c b/gcc/testsuite/gcc.target/i386/pr94088.c new file mode 100644 index 0000000..d8cdba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94088.c @@ -0,0 +1,9 @@ +/* PR target/94088 */ +/* { dg-do compile } */ +/* { dg-options "-mtbm -O1 -fira-loop-pressure -fno-dce" } */ + +double +foo (int x) +{ + return x / (4294950402U % -65472 + 161); +} -- cgit v1.1 From aed151bb53b44d523e2732ca6add9324c4ff9798 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Tue, 10 Mar 2020 08:38:14 -0600 Subject: Revert "Fix regression reported by tester due to recent IRA changes" This reverts commit d48e1175279a551bf90aa5b165fc46a1d5a2c07e. 2020-03-10 Jeff Law Revert: 2020-02-29 Jeff Law * gcc.target/xstormy16/sfr/06_sfrw_to_var.c: Update expected output. --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5ed497d..089874e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-10 Jeff Law + + Revert: + 2020-02-29 Jeff Law + + * gcc.target/xstormy16/sfr/06_sfrw_to_var.c: Update expected output. + 2020-03-10 Jakub Jelinek PR target/94088 diff --git a/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c b/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c index 54c9baf..39cbab5 100644 --- a/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c +++ b/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c @@ -1,5 +1,5 @@ /* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */ -/* { dg-final { scan-assembler "mov.w r1,32532" } } */ +/* { dg-final { scan-assembler "mov.w r6,32532" } } */ #define SFR (*((volatile unsigned short*)0x7f14)) unsigned short *p = (unsigned short *) 0x7f14; -- cgit v1.1 From cfd90eb9ed01f652cb253c57ed6d13e96e9a5f47 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 10 Mar 2020 17:39:21 +0100 Subject: testsuite: Scan for SSE reg-reg moves only in pr80481.C The function needs more than 8 SSE registers, avoid false positives triggered by SSE spills for 32bit targets. * g++.dg/pr80481.C (dg-final): Scan for SSE reg-reg moves only. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/pr80481.C | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 089874e..1935ebc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-10 Uroš Bizjak + + * g++.dg/pr80481.C (dg-final): Scan for SSE reg-reg moves only. + 2020-03-10 Jeff Law Revert: diff --git a/gcc/testsuite/g++.dg/pr80481.C b/gcc/testsuite/g++.dg/pr80481.C index c565ad2..78c463b 100644 --- a/gcc/testsuite/g++.dg/pr80481.C +++ b/gcc/testsuite/g++.dg/pr80481.C @@ -1,11 +1,9 @@ // { dg-do compile { target { i?86-*-* x86_64-*-* } && { ! *-*-solaris* } } } // { dg-options "-Ofast -funroll-loops -fopenmp -march=knl" } -// { dg-final { scan-assembler-not "vmovaps" } } // Disabling epilogues until we find a better way to deal with scans. // { dg-additional-options "--param vect-epilogues-nomask=0" } - #include #include @@ -72,3 +70,5 @@ void foo (Sdata *in, int idx, float *out) _mm_free(y3); _mm_free(y4); } + +// { dg-final { scan-assembler-not "vmovaps\[^\n\r]*zmm\[0-9]+,\[^\n\r]*zmm\[0-9]+" } } -- cgit v1.1 From 90b5ebd76934b6c297b92946a2989c5ed9cc13cc Mon Sep 17 00:00:00 2001 From: Roman Zhuykov Date: Tue, 10 Mar 2020 19:47:53 +0300 Subject: minor: fix intendation in ddg.c gcc/ChangeLog: * ddg.c (create_ddg): Fix intendation. (set_recurrence_length): Likewise. (create_ddg_all_sccs): Likewise. --- gcc/ChangeLog | 6 ++++++ gcc/ddg.c | 34 +++++++++++++++++----------------- 2 files changed, 23 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5d5bbf4..ca90147 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-10 Roman Zhuykov + + * ddg.c (create_ddg): Fix intendation. + (set_recurrence_length): Likewise. + (create_ddg_all_sccs): Likewise. + 2020-03-10 Jakub Jelinek PR target/94088 diff --git a/gcc/ddg.c b/gcc/ddg.c index aae92ad..ca8cb74 100644 --- a/gcc/ddg.c +++ b/gcc/ddg.c @@ -633,7 +633,7 @@ create_ddg (basic_block bb, int closing_branch_deps) g->nodes[i].aux.count = -1; g->nodes[i].max_dist = XCNEWVEC (int, num_nodes); for (j = 0; j < num_nodes; j++) - g->nodes[i].max_dist[j] = -1; + g->nodes[i].max_dist[j] = -1; g->nodes[i++].insn = insn; first_note = NULL; @@ -838,7 +838,7 @@ set_recurrence_length (ddg_scc_ptr scc) int length = src->max_dist[dest->cuid]; if (length < 0) - continue; + continue; length += backarc->latency; result = MAX (result, (length / distance)); @@ -1069,8 +1069,8 @@ create_ddg_all_sccs (ddg_ptr g) n->max_dist[k] = 0; for (e = n->out; e; e = e->next_out) - if (e->distance == 0 && g->nodes[e->dest->cuid].aux.count == n->aux.count) - n->max_dist[e->dest->cuid] = e->latency; + if (e->distance == 0 && g->nodes[e->dest->cuid].aux.count == n->aux.count) + n->max_dist[e->dest->cuid] = e->latency; } /* Run main Floid-Warshall loop. We use only non-backarc edges @@ -1079,19 +1079,19 @@ create_ddg_all_sccs (ddg_ptr g) { scc = g->nodes[k].aux.count; if (scc != -1) - { - for (i = 0; i < num_nodes; i++) - if (g->nodes[i].aux.count == scc) - for (j = 0; j < num_nodes; j++) - if (g->nodes[j].aux.count == scc - && g->nodes[i].max_dist[k] >= 0 - && g->nodes[k].max_dist[j] >= 0) - { - way = g->nodes[i].max_dist[k] + g->nodes[k].max_dist[j]; - if (g->nodes[i].max_dist[j] < way) - g->nodes[i].max_dist[j] = way; - } - } + { + for (i = 0; i < num_nodes; i++) + if (g->nodes[i].aux.count == scc) + for (j = 0; j < num_nodes; j++) + if (g->nodes[j].aux.count == scc + && g->nodes[i].max_dist[k] >= 0 + && g->nodes[k].max_dist[j] >= 0) + { + way = g->nodes[i].max_dist[k] + g->nodes[k].max_dist[j]; + if (g->nodes[i].max_dist[j] < way) + g->nodes[i].max_dist[j] = way; + } + } } /* Calculate recurrence_length using max_dist info. */ -- cgit v1.1 From b888a051deb7df7587acbe8865513b86d2a1d49f Mon Sep 17 00:00:00 2001 From: Roman Zhuykov Date: Tue, 10 Mar 2020 19:54:50 +0300 Subject: loop-iv: make find_simple_exit static Function 'find_simple_exit' is used only from loop-iv.c In 2004-2006 it was also used in predict.c, but since r118694 (992c31e62304ed5d34247dbdef2db276d08fac05) it does not. gcc/ChangeLog: * loop-iv.c (find_simple_exit): Make it static. * cfgloop.h: Remove the corresponding prototype. --- gcc/ChangeLog | 5 +++++ gcc/cfgloop.h | 1 - gcc/loop-iv.c | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca90147..c78d01a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-03-10 Roman Zhuykov + * loop-iv.c (find_simple_exit): Make it static. + * cfgloop.h: Remove the corresponding prototype. + +2020-03-10 Roman Zhuykov + * ddg.c (create_ddg): Fix intendation. (set_recurrence_length): Likewise. (create_ddg_all_sccs): Likewise. diff --git a/gcc/cfgloop.h b/gcc/cfgloop.h index 11378ca..1c49a8b 100644 --- a/gcc/cfgloop.h +++ b/gcc/cfgloop.h @@ -499,7 +499,6 @@ extern bool iv_analyze_expr (rtx_insn *, scalar_int_mode, rtx, class rtx_iv *); extern rtx get_iv_value (class rtx_iv *, rtx); extern bool biv_p (rtx_insn *, scalar_int_mode, rtx); -extern void find_simple_exit (class loop *, class niter_desc *); extern void iv_analysis_done (void); extern class niter_desc *get_simple_loop_desc (class loop *loop); diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c index 6a59954..d7b3d90 100644 --- a/gcc/loop-iv.c +++ b/gcc/loop-iv.c @@ -2915,7 +2915,7 @@ check_simple_exit (class loop *loop, edge e, class niter_desc *desc) /* Finds a simple exit of LOOP and stores its description into DESC. */ -void +static void find_simple_exit (class loop *loop, class niter_desc *desc) { unsigned i; -- cgit v1.1 From e00cb200f39d8144de226e76c5d0257b613dbbf6 Mon Sep 17 00:00:00 2001 From: Will Schmidt Date: Tue, 10 Mar 2020 14:38:13 -0500 Subject: PR90763: PowerPC vec_xl_len should take const argument. PR target/90763 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add clause to handle P9V_BUILTIN_VEC_LXVL with const arguments. * gcc.target/powerpc/pr90763.c: New. --- gcc/ChangeLog | 6 ++ gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 4 files changed, 112 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c78d01a..c525661 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-10 Will Schmidt + + PR target/90763 + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add + clause to handle P9V_BUILTIN_VEC_LXVL with const arguments. + 2020-03-10 Roman Zhuykov * loop-iv.c (find_simple_exit): Make it static. diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 37c74cf..8c1fbbf 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1638,6 +1638,19 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, arg = fold_convert (type, arg); } + /* For P9V_BUILTIN_VEC_LXVL, convert any const * to its non constant + equivalent to simplify the overload matching below. */ + if (fcode == P9V_BUILTIN_VEC_LXVL) + { + if (POINTER_TYPE_P (type) + && TYPE_READONLY (TREE_TYPE (type))) + { + type = build_pointer_type (build_qualified_type ( + TREE_TYPE (type),0)); + arg = fold_convert (type, arg); + } + } + args[n] = arg; types[n] = type; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1935ebc..da525a3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-10 Will Schmidt + + PR target/90763 + * gcc.target/powerpc/pr90763.c: New. + 2020-03-10 Uroš Bizjak * g++.dg/pr80481.C (dg-final): Scan for SSE reg-reg moves only. diff --git a/gcc/testsuite/gcc.target/powerpc/pr90763.c b/gcc/testsuite/gcc.target/powerpc/pr90763.c new file mode 100644 index 0000000..55f1d46 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr90763.c @@ -0,0 +1,88 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* PR90763: PowerPC vec_xl_len should take const. +*/ + +#include + +vector unsigned char vec_load_uc(unsigned char *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned char vec_load_const_uc(const unsigned char *p, int num) { + return vec_xl_len(p, num); +} +vector signed char vec_load_sc(signed char *p, int num) { + return vec_xl_len(p, num); +} +vector signed char vec_load_const_sc(const signed char *p, int num) { + return vec_xl_len(p, num); +} + +vector signed short vec_load_ss(signed short *p, int num) { + return vec_xl_len(p, num); +} +vector signed short vec_load_const_ss(const signed short *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned short vec_load_us(unsigned short *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned short vec_load_const_us(const unsigned short *p, int num) { + return vec_xl_len(p, num); +} + +vector signed int vec_load_si(signed int *p, int num) { + return vec_xl_len(p, num); +} +vector signed int vec_load_const_si(const signed int *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned int vec_load_ui(unsigned int *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned int vec_load_const_ui(const unsigned int *p, int num) { + return vec_xl_len(p, num); +} + +vector signed long long vec_load_sll(signed long long *p, int num) { + return vec_xl_len(p, num); +} +vector signed long long vec_load_const_sll(const signed long long *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned long long vec_load_ull(unsigned long long *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned long long vec_load_const_ull(const unsigned long long *p, int num) { + return vec_xl_len(p, num); +} + +vector signed __int128 vec_load_si128(signed __int128 *p, int num) { + return vec_xl_len(p, num); +} +vector signed __int128 vec_load_const_si128(const signed __int128 *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned __int128 vec_load_ui128(unsigned __int128 *p, int num) { + return vec_xl_len(p, num); +} +vector unsigned __int128 vec_load_const_ui128(const unsigned __int128 *p, int num) { + return vec_xl_len(p, num); +} + +vector float vec_load_f(float *p, int num) { + return vec_xl_len(p, num); +} +vector float vec_load_const_f(const float *p, int num) { + return vec_xl_len(p, num); +} + +vector double vec_load_d(double *p, int num) { + return vec_xl_len(p, num); +} +vector double vec_load_const_d(const double *p, int num) { + return vec_xl_len(p, num); +} + -- cgit v1.1 From 14af5d9b19b0f4ee1d929e505e245ae5c2f6bdc6 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 10 Mar 2020 16:05:18 -0400 Subject: c++: Partially revert patch for PR66139. The patch for 66139 exposed a long-standing bug with split_nonconstant_init (since 4.7, apparently): initializion of individual elements of an aggregate are not a full-expressions, but split_nonconstant_init was making full-expressions out of them. My fix for 66139 extended the use of split_nonconstant_init, and thus the bug, to aggregate initialization of temporaries within an expression, in which context (PR94041) the bug is more noticeable. PR93922 is a problem with my implementation strategy of splitting out at gimplification time, introducing function calls that weren't in the GENERIC. So I'm going to revert the patch now and try again for GCC 11. gcc/cp/ChangeLog 2020-03-10 Jason Merrill PR c++/93922 PR c++/94041 PR c++/52320 PR c++/66139 * cp-gimplify.c (cp_gimplify_init_expr): Partially revert patch for 66139: Don't split_nonconstant_init. Remove pre_p parameter. --- gcc/cp/ChangeLog | 9 +++++ gcc/cp/cp-gimplify.c | 20 +--------- gcc/testsuite/g++.dg/cpp0x/initlist116.C | 29 -------------- gcc/testsuite/g++.dg/cpp0x/initlist117.C | 40 ------------------- gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C | 34 ---------------- gcc/testsuite/g++.dg/eh/aggregate1.C | 56 --------------------------- 6 files changed, 11 insertions(+), 177 deletions(-) delete mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist116.C delete mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist117.C delete mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C delete mode 100644 gcc/testsuite/g++.dg/eh/aggregate1.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index d9807ad..e62aefd 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,12 @@ +2020-03-10 Jason Merrill + + PR c++/93922 + PR c++/94041 + PR c++/52320 + PR c++/66139 + * cp-gimplify.c (cp_gimplify_init_expr): Partially revert patch for + 66139: Don't split_nonconstant_init. Remove pre_p parameter. + 2020-03-09 Marek Polacek PR c++/92031 - bogus taking address of rvalue error. diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index 10ab995..23a25e5 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -513,7 +513,7 @@ gimplify_expr_stmt (tree *stmt_p) /* Gimplify initialization from an AGGR_INIT_EXPR. */ static void -cp_gimplify_init_expr (tree *expr_p, gimple_seq *pre_p) +cp_gimplify_init_expr (tree *expr_p) { tree from = TREE_OPERAND (*expr_p, 1); tree to = TREE_OPERAND (*expr_p, 0); @@ -526,22 +526,6 @@ cp_gimplify_init_expr (tree *expr_p, gimple_seq *pre_p) if (TREE_CODE (from) == TARGET_EXPR && TARGET_EXPR_INITIAL (from)) from = TARGET_EXPR_INITIAL (from); - /* If we might need to clean up a partially constructed object, break down - the CONSTRUCTOR with split_nonconstant_init. */ - if (TREE_CODE (from) == CONSTRUCTOR - && flag_exceptions - && TREE_SIDE_EFFECTS (from) - && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (to))) - { - gimplify_expr (&to, pre_p, NULL, is_gimple_lvalue, fb_lvalue); - replace_placeholders (from, to); - from = split_nonconstant_init (to, from); - cp_genericize_tree (&from, false); - copy_if_shared (&from); - *expr_p = from; - return; - } - /* Look through any COMPOUND_EXPRs, since build_compound_expr pushes them inside the TARGET_EXPR. */ for (t = from; t; ) @@ -734,7 +718,7 @@ cp_gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) LHS of an assignment might also be involved in the RHS, as in bug 25979. */ case INIT_EXPR: - cp_gimplify_init_expr (expr_p, pre_p); + cp_gimplify_init_expr (expr_p); if (TREE_CODE (*expr_p) != INIT_EXPR) return GS_OK; /* Fall through. */ diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist116.C b/gcc/testsuite/g++.dg/cpp0x/initlist116.C deleted file mode 100644 index 90dd8d7..0000000 --- a/gcc/testsuite/g++.dg/cpp0x/initlist116.C +++ /dev/null @@ -1,29 +0,0 @@ -// PR c++/66139 -// { dg-do run { target c++11 } } - -int constructed = 0; - -class lock_guard_ext{ -public: - lock_guard_ext() { ++constructed; } - ~lock_guard_ext() { --constructed; } -}; - -struct Access { - lock_guard_ext lock; - int value; -}; - -int t() { - throw 0; -} - -Access foo1() { - return { {}, t() }; -} - -int main () { - try { foo1(); } catch (int) {} - if (constructed != 0) - __builtin_abort(); -} diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist117.C b/gcc/testsuite/g++.dg/cpp0x/initlist117.C deleted file mode 100644 index 415a5de..0000000 --- a/gcc/testsuite/g++.dg/cpp0x/initlist117.C +++ /dev/null @@ -1,40 +0,0 @@ -// PR c++/66139 -// { dg-do run { target c++11 } } - -#include - -int c, d; - -struct a -{ - a (int i) { if (i) throw i; c++; } - ~a () { d++; } -}; - -void check (void (*f) ()) -{ - try - { - c = d = 0; - f (); - } - catch (int) - { - if (c != 1 || d != 1) - __builtin_abort (); - return; - } - __builtin_abort (); -} - -int main () -{ - struct s { a x, y; }; - check ([] { s t { 0, 1 }; }); - check ([] { s { 0, 1 }; }); - check ([] { a t[2] { 0, 1 }; }); - using array = a[2]; - check ([] { array { 0, 1 }; }); - check ([] { std::initializer_list t { 0, 1 }; }); - check ([] { std::initializer_list { 0, 1 }; }); -} diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C deleted file mode 100644 index 4d1f4f3..0000000 --- a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C +++ /dev/null @@ -1,34 +0,0 @@ -// Test that we properly clean up if we get an exception in the middle of -// constructing the closure object. - -// { dg-do run } -// { dg-require-effective-target c++11 } - -struct A -{ - A() {} - A(const A&) { throw 1; } -}; - -int bs; -struct B -{ - B() { ++bs; } - B(const B&) { ++bs; } - ~B() { --bs; } -}; - -int main() -{ - { - B b1, b2; - A a; - - try - { - [b1, a, b2]{ }; - } - catch(...) {} - } - return bs; -} diff --git a/gcc/testsuite/g++.dg/eh/aggregate1.C b/gcc/testsuite/g++.dg/eh/aggregate1.C deleted file mode 100644 index 38dba89..0000000 --- a/gcc/testsuite/g++.dg/eh/aggregate1.C +++ /dev/null @@ -1,56 +0,0 @@ -// PR c++/52320 -// { dg-do run } - -#if DEBUG -extern "C" int printf (const char *, ...); -#define FUNCTION_NAME __PRETTY_FUNCTION__ -#define TRACE_FUNCTION printf ("%p->%s\n", this, FUNCTION_NAME); -#else -#define TRACE_FUNCTION -#endif -int c,d; -#define TRACE_CTOR TRACE_FUNCTION ++c -#define TRACE_DTOR TRACE_FUNCTION ++d - -int throw_at = 0; - -struct A { - A() { int i = c+1; if (i == throw_at) throw i; TRACE_CTOR; } - A(int i) { if (i == throw_at) throw i; TRACE_CTOR; } - A(const A&) { throw 10; } - A &operator=(const A&) { throw 11; return *this; } - ~A() { TRACE_DTOR; } -}; - -int fails; - -void try_idx (int i) -{ -#if DEBUG - printf ("trying %d\n", i); -#endif - throw_at = i; - c = d = 0; - int t = 10; - try { - struct X { - A e1[2], e2; - } - x2[3] = { { 1, 2, 3 }, { 4, 5, 6 } }; - } catch (int x) { t = x; } - if (t != i || c != d || c != i-1) - { -#if DEBUG - printf ("%d FAIL\n", i); -#endif - ++fails; - } -} - -int main() -{ - for (int i = 1; i <= 10; ++i) - try_idx (i); - - return fails; -} -- cgit v1.1 From b269a014771776f860730874095dffb34839a466 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 10 Mar 2020 16:43:58 -0400 Subject: c++: Add tests for PR93922 and PR94041. --- gcc/testsuite/g++.dg/cpp0x/initlist121.C | 31 +++++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/initlist122.C | 16 ++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist121.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist122.C (limited to 'gcc') diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist121.C b/gcc/testsuite/g++.dg/cpp0x/initlist121.C new file mode 100644 index 0000000..c12006c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist121.C @@ -0,0 +1,31 @@ +// PR c++/93922 +// { dg-do link { target c++11 } } + +template +struct A { + A () {} + template + A (A const &) {} + ~A () {} +}; +int t; +struct B {}; +struct C : B { C (B const &) { if (t) throw 1; } }; +struct S { A x; C y; }; + +A +bar (B *) +{ + return A (); +} + +S * +foo (B *x, B const &y) +{ + return new S {bar (x), y}; +} + +int +main () +{ +} diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist122.C b/gcc/testsuite/g++.dg/cpp0x/initlist122.C new file mode 100644 index 0000000..002bc1e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist122.C @@ -0,0 +1,16 @@ +// PR c++/94041 +// { dg-do run { target c++11 } } + +bool gone; +struct Temp { ~Temp() { gone = true; } }; +struct A{ A() {}; A(const Temp&) noexcept {}; }; +struct B{ ~B() {}; }; +struct Pair{ A a; B b; }; + +void foo(const Pair&) noexcept { if (gone) __builtin_abort(); } + +int main() +{ + foo({A(Temp{}), B()}); + if (!gone) __builtin_abort (); +} -- cgit v1.1 From 76743c8a6abbe29fe0f20fc55d5d691ff62dee6a Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 11 Mar 2020 00:16:14 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 966f032..6b5fa91 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200310 +20200311 -- cgit v1.1 From 37e0df8a9be5a8232f4ccb73cdadb02121ba523f Mon Sep 17 00:00:00 2001 From: Jiufu Guo Date: Tue, 10 Mar 2020 13:51:57 +0800 Subject: rs6000: Check -+0 and NaN for smax/smin generation PR93709 mentioned regressions on maxlocval_4.f90 and minlocval_f.f90 which relates to max of '-inf' and 'nan'. This regression occur on P9 because P9 new instruction 'xsmaxcdp' is generated. And for C code `a < b ? b : a` is also generated as `xsmaxcdp` under -O2 for P9. While this instruction behavior more like C/C++ semantic (a>b?a:b). This generates prevents 'xsmaxcdp' to be generated for those cases. 'xsmincdp' also is handled in patch. gcc/ 2020-03-10 Jiufu Guo PR target/93709 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check NAN and SIGNED_ZEROR for smax/smin. gcc/testsuite 2020-03-10 Jiufu Guo PR target/93709 * gcc.target/powerpc/p9-minmax-3.c: New test. --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 6 +++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 17 +++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c525661..5b67b79 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-10 Jiufu Guo + + PR target/93709 + * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check + NAN and SIGNED_ZEROR for smax/smin. + 2020-03-10 Will Schmidt PR target/90763 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 848a4ef..46b7dec 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -14831,7 +14831,11 @@ rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond) if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond)) ; - else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond)) + /* Only when NaNs and signed-zeros are not in effect, smax could be + used for `op0 < op1 ? op1 : op0`, and smin could be used for + `op0 > op1 ? op1 : op0`. */ + else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond) + && !HONOR_NANS (compare_mode) && !HONOR_SIGNED_ZEROS (compare_mode)) max_p = !max_p; else diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index da525a3..c76d891 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-10 Jiufu Guo + + PR target/93709 + * gcc.target/powerpc/p9-minmax-3.c: New test. + 2020-03-10 Will Schmidt PR target/90763 diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c new file mode 100644 index 0000000..141603e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2 -mpower9-minmax" } */ +/* { dg-final { scan-assembler-not "xsmaxcdp" } } */ +/* { dg-final { scan-assembler-not "xsmincdp" } } */ + +double +dbl_max1 (double a, double b) +{ + return a < b ? b : a; +} + +double +dbl_min1 (double a, double b) +{ + return a > b ? b : a; +} -- cgit v1.1 From df15a82804e1f7f4a7432670b33387779de46549 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 10 Mar 2020 17:51:46 -0400 Subject: c++: Fix ICE with omitted template args [PR93956]. reshape_init only wants to work on BRACE_ENCLOSED_INITIALIZER_P, i.e. raw initializer lists, and here was getting a CONSTRUCTOR that had already been processed for type A. maybe_aggr_guide should also use that test. gcc/cp/ChangeLog 2020-03-10 Jason Merrill PR c++/93956 * pt.c (maybe_aggr_guide): Check BRACE_ENCLOSED_INITIALIZER_P. --- gcc/cp/ChangeLog | 5 +++++ gcc/cp/pt.c | 2 +- gcc/testsuite/g++.dg/cpp1z/class-deduction70.C | 7 +++++++ 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction70.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index e62aefd..b60b1ec 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,10 @@ 2020-03-10 Jason Merrill + PR c++/93956 + * pt.c (maybe_aggr_guide): Check BRACE_ENCLOSED_INITIALIZER_P. + +2020-03-10 Jason Merrill + PR c++/93922 PR c++/94041 PR c++/52320 diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 49ee392..179716b 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -28182,7 +28182,7 @@ maybe_aggr_guide (tree tmpl, tree init, vec *args) tsubst_flags_t complain = tf_none; tree parms = NULL_TREE; - if (TREE_CODE (init) == CONSTRUCTOR) + if (BRACE_ENCLOSED_INITIALIZER_P (init)) { init = reshape_init (type, init, complain); if (init == error_mark_node) diff --git a/gcc/testsuite/g++.dg/cpp1z/class-deduction70.C b/gcc/testsuite/g++.dg/cpp1z/class-deduction70.C new file mode 100644 index 0000000..f14bdf0 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/class-deduction70.C @@ -0,0 +1,7 @@ +// PR c++/93596 + +template struct A {}; +template struct B {}; +template struct C { + void foo () { B a = A { foo }; } // { dg-error "" } +}; -- cgit v1.1 From 481fcfe6fec156ca2a6baea4b623076e2eefa6a6 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 10 Mar 2020 17:31:33 -0400 Subject: c++: Fix deferred noexcept on constructor [PR93901]. My change in r10-4394 to only update clones when we actually instantiate a deferred noexcept-spec broke this because deferred parsing updates the primary function but not the clones. For GCC 10, let's just revert it. gcc/cp/ChangeLog 2020-03-10 Jason Merrill PR c++/93901 * pt.c (maybe_instantiate_noexcept): Always update clones. --- gcc/cp/ChangeLog | 5 +++++ gcc/cp/pt.c | 14 +++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b60b1ec..9e0b488 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,10 @@ 2020-03-10 Jason Merrill + PR c++/93901 + * pt.c (maybe_instantiate_noexcept): Always update clones. + +2020-03-10 Jason Merrill + PR c++/93956 * pt.c (maybe_aggr_guide): Check BRACE_ENCLOSED_INITIALIZER_P. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 179716b..cb237ba 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -25097,14 +25097,14 @@ maybe_instantiate_noexcept (tree fn, tsubst_flags_t complain) TREE_TYPE (fn) = build_exception_variant (fntype, spec); if (orig_fn) TREE_TYPE (orig_fn) = TREE_TYPE (fn); + } - FOR_EACH_CLONE (clone, fn) - { - if (TREE_TYPE (clone) == fntype) - TREE_TYPE (clone) = TREE_TYPE (fn); - else - TREE_TYPE (clone) = build_exception_variant (TREE_TYPE (clone), spec); - } + FOR_EACH_CLONE (clone, fn) + { + if (TREE_TYPE (clone) == fntype) + TREE_TYPE (clone) = TREE_TYPE (fn); + else + TREE_TYPE (clone) = build_exception_variant (TREE_TYPE (clone), spec); } return true; -- cgit v1.1 From e11d05c1ed26257493130762a8ae240f1bc06e87 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Tue, 10 Mar 2020 18:55:42 -0400 Subject: c++: Fix wrong conversion error with non-viable overload [PR94124] This is a bad interaction between sharing a constructor for an array and stripping its trailing zero-initializers. Here we reuse a ctor and then strip its 0s. This breaks overload resolution in this test: D can be initialized from {} but not from {0}, so if we truncate the constructor not to include the zero, the F(D) overload becomes valid and then we get the ambiguous conversion error. PR c++/94124 - wrong conversion error with non-viable overload. * decl.c (reshape_init_array_1): Unshare a constructor if we stripped trailing zero-initializers. * g++.dg/cpp0x/initlist-overload1.C: New test. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/decl.c | 7 +++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C | 15 +++++++++++++++ 4 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 9e0b488..ebccb51 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-10 Marek Polacek + + PR c++/94124 - wrong conversion error with non-viable overload. + * decl.c (reshape_init_array_1): Unshare a constructor if we + stripped trailing zero-initializers. + 2020-03-10 Jason Merrill PR c++/93901 diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index bb24274..aa58e5f 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -6062,6 +6062,13 @@ reshape_init_array_1 (tree elt_type, tree max_index, reshape_iter *d, else if (last_nonzero < nelts - 1) nelts = last_nonzero + 1; + /* Sharing a stripped constructor can get in the way of + overload resolution. E.g., initializing a class from + {{0}} might be invalid while initializing the same class + from {{}} might be valid. */ + if (reuse) + new_init = unshare_constructor (new_init); + vec_safe_truncate (CONSTRUCTOR_ELTS (new_init), nelts); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c76d891..d243255 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-10 Marek Polacek + + PR c++/94124 - wrong conversion error with non-viable overload. + * g++.dg/cpp0x/initlist-overload1.C: New test. + 2020-03-10 Jiufu Guo PR target/93709 diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C b/gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C new file mode 100644 index 0000000..12bb606 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C @@ -0,0 +1,15 @@ +// PR c++/94124 - wrong conversion error with non-viable overload. +// { dg-do compile { target c++11 } } + +template struct A { typedef int _Type[N]; }; +template struct B { typename A::_Type _M_elems; }; +class C { }; +struct D { + D(C); +}; + +struct F { + F(B<2>); + F(D); // This overload should not be viable. +}; +F fn1() { return {{{0}}}; } -- cgit v1.1 From 5115542a5cc17c5096e6e498c363e75d5bc14276 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Tue, 10 Mar 2020 22:16:19 -0600 Subject: Fix length computation for movsi_insv which resulted in regressions due to out of range branches on the bfin port. * config/bfin/bfin.md (movsi_insv): Add length attribute. --- gcc/ChangeLog | 4 ++++ gcc/config/bfin/bfin.md | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5b67b79..887a550 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-03-10 Jeff Law + + * config/bfin/bfin.md (movsi_insv): Add length attribute. + 2020-03-10 Jiufu Guo PR target/93709 diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index bb71a37..aecb813 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -752,7 +752,8 @@ "@ %d0 = %h1 << 0%! %d0 = %1;" - [(set_attr "type" "dsp32shiftimm,mvi")]) + [(set_attr "type" "dsp32shiftimm,mvi") + (set_attr "length" "*,4")]) (define_expand "insv" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") -- cgit v1.1 From 05ac4d9c7b336e30413dd80c3630981151499f9e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 11 Mar 2020 09:32:22 +0100 Subject: ldist: Further fixes for -ftrapv [PR94114] As the testcase shows, arithmetics that for -ftrapv would need multiple basic blocks can show up not just in nb_bytes expressions where we are calling rewrite_to_non_trapping_overflow for a while already, but also in the pointer expression to the start of the region. While the testcase covers just the first hunk and I've failed to create a testcase for the latter, it is at least in theory possible too, so I've adjusted that hunk too. 2020-03-11 Jakub Jelinek PR tree-optimization/94114 * tree-loop-distribution.c (generate_memset_builtin): Call rewrite_to_non_trapping_overflow even on mem. (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even on dest and src. * gcc.dg/pr94114.c: New test. --- gcc/ChangeLog | 8 ++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr94114.c | 13 +++++++++++++ gcc/tree-loop-distribution.c | 6 +++--- 4 files changed, 29 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94114.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 887a550..6630a20 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-11 Jakub Jelinek + + PR tree-optimization/94114 + * tree-loop-distribution.c (generate_memset_builtin): Call + rewrite_to_non_trapping_overflow even on mem. + (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even + on dest and src. + 2020-03-10 Jeff Law * config/bfin/bfin.md (movsi_insv): Add length attribute. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d243255..954c451 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-11 Jakub Jelinek + + PR tree-optimization/94114 + * gcc.dg/pr94114.c: New test. + 2020-03-10 Marek Polacek PR c++/94124 - wrong conversion error with non-viable overload. diff --git a/gcc/testsuite/gcc.dg/pr94114.c b/gcc/testsuite/gcc.dg/pr94114.c new file mode 100644 index 0000000..8d6d0eb --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94114.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/94114 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-loop-distribute-patterns -ftrapv" } */ + +void +foo (int *x, int *y, int *z, long int w) +{ + while (y + w > z) + { + x[w] = 0; + --w; + } +} diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c index a4f0b1e..35d3821 100644 --- a/gcc/tree-loop-distribution.c +++ b/gcc/tree-loop-distribution.c @@ -1151,7 +1151,7 @@ generate_memset_builtin (class loop *loop, partition *partition) nb_bytes = rewrite_to_non_trapping_overflow (builtin->size); nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE, false, GSI_CONTINUE_LINKING); - mem = builtin->dst_base; + mem = rewrite_to_non_trapping_overflow (builtin->dst_base); mem = force_gimple_operand_gsi (&gsi, mem, true, NULL_TREE, false, GSI_CONTINUE_LINKING); @@ -1205,8 +1205,8 @@ generate_memcpy_builtin (class loop *loop, partition *partition) nb_bytes = rewrite_to_non_trapping_overflow (builtin->size); nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE, false, GSI_CONTINUE_LINKING); - dest = builtin->dst_base; - src = builtin->src_base; + dest = rewrite_to_non_trapping_overflow (builtin->dst_base); + src = rewrite_to_non_trapping_overflow (builtin->src_base); if (partition->kind == PKIND_MEMCPY || ! ptr_derefs_may_alias_p (dest, src)) kind = BUILT_IN_MEMCPY; -- cgit v1.1 From 312992f5a07ca25f94d538b08401789c2c764293 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 11 Mar 2020 09:33:52 +0100 Subject: dfp: Fix decimal_to_binary [PR94111] As e.g. decimal_from_decnumber shows, the REAL_VALUE_TYPE representation contains a decimal128 embedded in ->sig only if it is rvc_normal, for other kinds like rvc_inf or rvc_nan, ->sig is ignored and everything is contained in the REAL_VALUE_TYPE flags (cl, sign, signalling and decimal). decimal_to_binary which is used when folding a decimal{32,64,128} constant to a binary floating point type ignores this and thus folds infinities and NaNs into +0.0. The following patch fixes that by only doing that for rvc_normal. Similarly to the binary to decimal folding, it goes through a string, in order to e.g. deal with canonical NaN mantissas, or binary float formats that don't support infinities and/or NaNs. 2020-03-11 Jakub Jelinek PR middle-end/94111 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl is rvc_normal, otherwise use real_to_decimal to print the number to string. * gcc.dg/dfp/pr94111.c: New test. --- gcc/ChangeLog | 5 +++++ gcc/dfp.c | 10 +++++++--- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 ++++++++++++ 4 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/dfp/pr94111.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6630a20..b2d8ee1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-03-11 Jakub Jelinek + PR middle-end/94111 + * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl + is rvc_normal, otherwise use real_to_decimal to print the number to + string. + PR tree-optimization/94114 * tree-loop-distribution.c (generate_memset_builtin): Call rewrite_to_non_trapping_overflow even on mem. diff --git a/gcc/dfp.c b/gcc/dfp.c index 688fab4..fef39a5 100644 --- a/gcc/dfp.c +++ b/gcc/dfp.c @@ -342,9 +342,13 @@ decimal_to_binary (REAL_VALUE_TYPE *to, const REAL_VALUE_TYPE *from, const real_format *fmt) { char string[256]; - const decimal128 *const d128 = (const decimal128 *) from->sig; - - decimal128ToString (d128, string); + if (from->cl == rvc_normal) + { + const decimal128 *const d128 = (const decimal128 *) from->sig; + decimal128ToString (d128, string); + } + else + real_to_decimal (string, from, sizeof (string), 0, 1); real_from_string3 (to, string, fmt); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 954c451..3a4acce 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-11 Jakub Jelinek + PR middle-end/94111 + * gcc.dg/dfp/pr94111.c: New test. + PR tree-optimization/94114 * gcc.dg/pr94114.c: New test. diff --git a/gcc/testsuite/gcc.dg/dfp/pr94111.c b/gcc/testsuite/gcc.dg/dfp/pr94111.c new file mode 100644 index 0000000..ea3a132 --- /dev/null +++ b/gcc/testsuite/gcc.dg/dfp/pr94111.c @@ -0,0 +1,12 @@ +/* PR middle-end/94111 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +int +main () +{ + _Decimal32 d = (_Decimal32) __builtin_inff (); + if (!__builtin_isinf ((double) d)) + __builtin_abort (); + return 0; +} -- cgit v1.1 From 60342fdbfb0630243d2b85d2ca45204ded990b17 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 11 Mar 2020 09:34:59 +0100 Subject: value-prof: Fix abs uses in value-prof.c [PR93962] Jeff has recently fixed dump_histogram_value to use std::abs instead of abs, because on FreeBSD apparently the ::abs isn't overloaded and only has int abs (int); Seems on Solaris /usr/include/iso/stdlib_iso.h abs has: int abs (int); long abs (long); overloads but already not long long abs (long long); and there is another abs use in get_nth_most_common_value, also on int64_t. The long long std::abs (long long); overload is there only in C++11 and we in GCC10 still support C++98. Martin has said that a counter should never be INT64_MIN, so IMHO it is better to use abs_hwi which will assert that. 2020-03-11 Jakub Jelinek PR bootstrap/93962 * value-prof.c (dump_histogram_value): Use abs_hwi instead of std::abs. (get_nth_most_common_value): Use abs_hwi instead of abs. --- gcc/ChangeLog | 5 +++++ gcc/value-prof.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b2d8ee1..e4b74dd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-03-11 Jakub Jelinek + PR bootstrap/93962 + * value-prof.c (dump_histogram_value): Use abs_hwi instead of + std::abs. + (get_nth_most_common_value): Use abs_hwi instead of abs. + PR middle-end/94111 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl is rvc_normal, otherwise use real_to_decimal to print the number to diff --git a/gcc/value-prof.c b/gcc/value-prof.c index 585b909..45677be 100644 --- a/gcc/value-prof.c +++ b/gcc/value-prof.c @@ -266,7 +266,7 @@ dump_histogram_value (FILE *dump_file, histogram_value hist) if (hist->hvalue.counters) { fprintf (dump_file, " all: %" PRId64 "%s, values: ", - std::abs ((int64_t) hist->hvalue.counters[0]), + (int64_t) abs_hwi (hist->hvalue.counters[0]), hist->hvalue.counters[0] < 0 ? " (values missing)": ""); for (unsigned i = 0; i < GCOV_TOPN_VALUES; i++) @@ -743,7 +743,7 @@ get_nth_most_common_value (gimple *stmt, const char *counter_type, *count = 0; *value = 0; - gcov_type read_all = abs (hist->hvalue.counters[0]); + gcov_type read_all = abs_hwi (hist->hvalue.counters[0]); gcov_type v = hist->hvalue.counters[2 * n + 1]; gcov_type c = hist->hvalue.counters[2 * n + 2]; -- cgit v1.1 From 42bc589e87a326282be2156ddeb18588677c645d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 11 Mar 2020 10:54:22 +0100 Subject: aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] abs_hwi asserts that the argument is not HOST_WIDE_INT_MIN and as the (invalid) testcase shows, the function can be called with such an offset. The following patch is IMHO minimal fix, absu_hwi unlike abs_hwi allows even that value and will return (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN in that case. The function then uses moffset in two spots which wouldn't care if the value is (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN or HOST_WIDE_INT_MIN and wouldn't accept it (!moffset and aarch64_uimm12_shift (moffset)), then in one spot where the signedness of moffset does matter and using unsigned is the right thing - moffset < 0x1000000 - and finally has code which will handle even this value right; the assembler doesn't really care for DImode immediates if mov x1, -9223372036854775808 or mov x1, 9223372036854775808 is used and similarly it doesn't matter if we add or sub it in DImode. 2020-03-11 Jakub Jelinek PR target/94121 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT. * gcc.dg/pr94121.c: New test. --- gcc/ChangeLog | 4 ++++ gcc/config/aarch64/aarch64.c | 2 +- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.dg/pr94121.c | 16 ++++++++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/pr94121.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e4b74dd..1fc6ff3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2020-03-11 Jakub Jelinek + PR target/94121 + * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi + instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT. + PR bootstrap/93962 * value-prof.c (dump_histogram_value): Use abs_hwi instead of std::abs. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4b9747b..c320d5ba 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3713,7 +3713,7 @@ aarch64_add_offset_1 (scalar_int_mode mode, rtx dest, gcc_assert (emit_move_imm || temp1 != NULL_RTX); gcc_assert (temp1 == NULL_RTX || !reg_overlap_mentioned_p (temp1, src)); - HOST_WIDE_INT moffset = abs_hwi (offset); + unsigned HOST_WIDE_INT moffset = absu_hwi (offset); rtx_insn *insn; if (!moffset) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3a4acce..af94cb4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-11 Jakub Jelinek + PR target/94121 + * gcc.dg/pr94121.c: New test. + PR middle-end/94111 * gcc.dg/dfp/pr94111.c: New test. diff --git a/gcc/testsuite/gcc.dg/pr94121.c b/gcc/testsuite/gcc.dg/pr94121.c new file mode 100644 index 0000000..2a4261a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94121.c @@ -0,0 +1,16 @@ +/* PR target/94121 */ +/* { dg-do compile { target pie } } */ +/* { dg-options "-O2 -fpie -w" } */ + +#define DIFF_MAX __PTRDIFF_MAX__ +#define DIFF_MIN (-DIFF_MAX - 1) + +extern void foo (char *); +extern char v[]; + +void +bar (void) +{ + char *p = v; + foo (&p[DIFF_MIN]); +} -- cgit v1.1 From a5aac267e64c578d55e6e269fa9e331f0d01da98 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 11 Mar 2020 10:47:34 +0100 Subject: Fix internal error on locally-defined subpools If the type is derived in the current compilation unit, and Allocate is not overridden on derivation (as is typically the case with Root_Storage_Pool_With_Subpools), the entity for Allocate of the derived type is an alias for System.Storage_Pools.Subpools.Allocate. The main assertion in gnat_to_gnu_entity fails in this case, since this is not a definition and Is_Public is false (since the entity is nested in the same compilation unit). 2020-03-11 Richard Wai * gcc-interface/decl.c (gnat_to_gnu_entity): Also test Is_Public on the Alias of the entitiy, if is present, in the main assertion. --- gcc/ada/ChangeLog | 5 +++ gcc/ada/gcc-interface/decl.c | 9 +++- gcc/testsuite/ChangeLog | 4 ++ gcc/testsuite/gnat.dg/subpools1.adb | 82 +++++++++++++++++++++++++++++++++++++ 4 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gnat.dg/subpools1.adb (limited to 'gcc') diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 64b2572..9df3840 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,8 @@ +2020-03-11 Richard Wai + + * gcc-interface/decl.c (gnat_to_gnu_entity): Also test Is_Public on + the Alias of the entitiy, if is present, in the main assertion. + 2020-02-06 Alexandre Oliva * raise-gcc.c (personality_body) [__ARM_EABI_UNWINDER__]: diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 871a309..80dfc55 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -446,7 +446,12 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) /* If we get here, it means we have not yet done anything with this entity. If we are not defining it, it must be a type or an entity that is defined - elsewhere or externally, otherwise we should have defined it already. */ + elsewhere or externally, otherwise we should have defined it already. + + One exception is for an entity, typically an inherited operation, which is + a local alias for the parent's operation. It is neither defined, since it + is an inherited operation, nor public, since it is declared in the current + compilation unit, so we test Is_Public on the Alias entity instead. */ gcc_assert (definition || is_type || kind == E_Discriminant @@ -454,6 +459,8 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) || kind == E_Label || (kind == E_Constant && Present (Full_View (gnat_entity))) || Is_Public (gnat_entity) + || (Present (Alias (gnat_entity)) + && Is_Public (Alias (gnat_entity))) || type_annotate_only); /* Get the name of the entity and set up the line number and filename of diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index af94cb4..f43da84 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Richard Wai + + * gnat.dg/subpools1.adb: New test. + 2020-03-11 Jakub Jelinek PR target/94121 diff --git a/gcc/testsuite/gnat.dg/subpools1.adb b/gcc/testsuite/gnat.dg/subpools1.adb new file mode 100644 index 0000000..b38a4ca --- /dev/null +++ b/gcc/testsuite/gnat.dg/subpools1.adb @@ -0,0 +1,82 @@ +-- { dg-do compile } + +with System.Storage_Elements; +with System.Storage_Pools.Subpools; + +procedure Subpools1 is + + use System.Storage_Pools.Subpools; + + package Local_Pools is + + use System.Storage_Elements; + + type Local_Pool is new Root_Storage_Pool_With_Subpools with null record; + + overriding + function Create_Subpool (Pool: in out Local_Pool) + return not null Subpool_Handle; + + overriding + procedure Allocate_From_Subpool + (Pool : in out Local_Pool; + Storage_Address : out System.Address; + Size_In_Storage_Elements: in Storage_Count; + Alignment : in Storage_Count; + Subpool : in not null Subpool_Handle); + + overriding + procedure Deallocate_Subpool + (Pool : in out Local_Pool; + Subpool: in out Subpool_Handle) is null; + + end Local_Pools; + + package body Local_Pools is + + type Local_Subpool is new Root_Subpool with null record; + + Dummy_Subpool: aliased Local_Subpool; + + overriding + function Create_Subpool (Pool: in out Local_Pool) + return not null Subpool_Handle + is + begin + return Result: not null Subpool_Handle + := Dummy_Subpool'Unchecked_Access + do + Set_Pool_Of_Subpool (Result, Pool); + end return; + end; + + overriding + procedure Allocate_From_Subpool + (Pool : in out Local_Pool; + Storage_Address : out System.Address; + Size_In_Storage_Elements: in Storage_Count; + Alignment : in Storage_Count; + Subpool : in not null Subpool_Handle) + is + type Storage_Array_Access is access Storage_Array; + + New_Alloc: Storage_Array_Access + := new Storage_Array (1 .. Size_In_Storage_Elements + Alignment); + begin + for SE of New_Alloc.all loop + Storage_Address := SE'Address; + exit when Storage_Address mod Alignment = 0; + end loop; + end; + + end Local_Pools; + + A_Pool: Local_Pools.Local_Pool; + + type Integer_Access is access Integer with Storage_Pool => A_Pool; + + X: Integer_Access := new Integer; + +begin + null; +end; -- cgit v1.1 From e835226bab5b3575c8a55c048dcfed3d4cde5e0e Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 11 Mar 2020 11:29:39 +0100 Subject: Fix GIMPLE verification failure in LTO mode on Ada code The issue is that tree_is_indexable doesn't return the same result for a FIELD_DECL with QUAL_UNION_TYPE and the QUAL_UNION_TYPE, resulting in two instances of the QUAL_UNION_TYPE in the bytecode. The result for the type is the correct one (false, since it is variably modified) while the result for the field is falsely true because: else if (TREE_CODE (t) == FIELD_DECL && lto_variably_modified_type_p (DECL_CONTEXT (t))) return false; is not satisfied. The reason for this is that the DECL_QUALIFIER of fields of a QUAL_UNION_TYPE depends on a discriminant in Ada, which means that the size of the type does too (CONTAINS_PLACEHOLDER_P), which in turn means that it is reset to a mere PLACEHOLDER_EXPR by free_lang_data, which finally means that the size of DECL_CONTEXT is too, so RETURN_TRUE_IF_VAR is false. In other words, the CONTAINS_PLACEHOLDER_P property of the DECL_QUALIFIER of fields of a QUAL_UNION_TYPE hides the variably_modified_type_p property of these fields, if you look from the outside. PR middle-end/93961 * tree.c (variably_modified_type_p) : Recurse into fields whose type is a qualified union. --- gcc/ChangeLog | 6 ++++++ gcc/ada/ChangeLog | 2 +- gcc/tree.c | 10 ++++++++++ 3 files changed, 17 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fc6ff3..0a79692 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-11 Eric Botcazou + + PR middle-end/93961 + * tree.c (variably_modified_type_p) : Recurse into fields + whose type is a qualified union. + 2020-03-11 Jakub Jelinek PR target/94121 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 9df3840..5349fd9 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,7 +1,7 @@ 2020-03-11 Richard Wai * gcc-interface/decl.c (gnat_to_gnu_entity): Also test Is_Public on - the Alias of the entitiy, if is present, in the main assertion. + the Alias of the entitiy, if it is present, in the main assertion. 2020-02-06 Alexandre Oliva diff --git a/gcc/tree.c b/gcc/tree.c index 66d52c7..905563f 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -9206,8 +9206,18 @@ variably_modified_type_p (tree type, tree fn) RETURN_TRUE_IF_VAR (DECL_SIZE (t)); RETURN_TRUE_IF_VAR (DECL_SIZE_UNIT (t)); + /* If the type is a qualified union, then the DECL_QUALIFIER + of fields can also be an expression containing a variable. */ if (TREE_CODE (type) == QUAL_UNION_TYPE) RETURN_TRUE_IF_VAR (DECL_QUALIFIER (t)); + + /* If the field is a qualified union, then it's only a container + for what's inside so we look into it. That's necessary in LTO + mode because the sizes of the field tested above have been set + to PLACEHOLDER_EXPRs by free_lang_data. */ + if (TREE_CODE (TREE_TYPE (t)) == QUAL_UNION_TYPE + && variably_modified_type_p (TREE_TYPE (t), fn)) + return true; } break; -- cgit v1.1 From d564c5e254df744a470a658690753dc193a4fa78 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Wed, 11 Mar 2020 14:06:21 +0000 Subject: [testsuite] Add @ lines to check-function-bodies fluff When using `check-function-bodies`, the subroutine `parse_function_bodies` uses the `fluff` regexp to remove uninteresting assembly lines. Arm targets generate assembly with some lines prefixed by `@`, these lines are left by this process. As an example of some lines prefixed by `@': the assembly output from the `stacktest1` function in "bfloat16_simd_3_1.c" is: .align 2 .global stacktest1 .arch armv8.2-a .syntax unified .arm .fpu neon-fp-armv8 .type stacktest1, %function stacktest1: @ args = 0, pretend = 0, frame = 8 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. sub sp, sp, #8 add r3, sp, #6 vst1.16 {d0[0]}, [r3] vld1.16 {d0[0]}, [r3] add sp, sp, #8 @ sp needed bx lr .size stacktest1, .-stacktest1 It seems that previous uses of `check-function-bodies` in the arm backend have avoided problems with such lines since they use the `...` regexp in each place such fluff occurs. I'm currently writing a patch that I'd like to match the entire function body, so I'd like to remove such `@` lines automatically. gcc/testsuite/ChangeLog: 2020-03-11 Matthew Malcomson * lib/scanasm.exp (parse_function_bodies): Lines starting with '@' also counted as fluff. --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/lib/scanasm.exp | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f43da84..0e8d77a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-11 Matthew Malcomson + + * lib/scanasm.exp (parse_function_bodies): Lines starting with '@' also + counted as fluff. + 2020-03-11 Richard Wai * gnat.dg/subpools1.adb: New test. diff --git a/gcc/testsuite/lib/scanasm.exp b/gcc/testsuite/lib/scanasm.exp index 5ca58d4..f7d2773 100644 --- a/gcc/testsuite/lib/scanasm.exp +++ b/gcc/testsuite/lib/scanasm.exp @@ -569,7 +569,7 @@ proc parse_function_bodies { filename result } { set terminator {^\s*\.size} # Regexp for lines that aren't interesting. - set fluff {^\s*(?:\.|//)} + set fluff {^\s*(?:\.|//|@)} set fd [open $filename r] set in_function 0 -- cgit v1.1 From cb99630f254aaec6591e0a200b79905b31d24eb3 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 11 Mar 2020 15:34:47 +0100 Subject: fold undefined pointer offsetting This avoids breaking the old broken pointer offsetting via (T)(ptr - ((T)0)->x) which should have used offsetof. Breakage was exposed by the introduction of POINTER_DIFF_EXPR and making PTA not considering that producing a pointer. The mitigation for simple cases is to canonicalize _2 = _1 - 8B; o_9 = (struct obj *) _2; to o_9 = &MEM[_1 + -8B]; eliding one statement and the offending pointer subtraction. 2020-03-11 Richard Biener * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): New pattern. * gcc.dg/torture/20200311-1.c: New testcase. --- gcc/ChangeLog | 5 +++++ gcc/match.pd | 9 +++++++++ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/torture/20200311-1.c | 26 ++++++++++++++++++++++++++ 4 files changed, 44 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/20200311-1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a79692..73339dc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-11 Richard Biener + + * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): + New pattern. + 2020-03-11 Eric Botcazou PR middle-end/93961 diff --git a/gcc/match.pd b/gcc/match.pd index 19df0c4..9cb3774 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -1864,6 +1864,15 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (if (ptr_difference_const (@0, @1, &diff)) { build_int_cst_type (type, diff); })))) +/* Canonicalize (T *)(ptr - ptr-cst) to &MEM[ptr + -ptr-cst]. */ +(simplify + (convert (pointer_diff @0 INTEGER_CST@1)) + (if (POINTER_TYPE_P (type)) + { build_fold_addr_expr_with_type + (build2 (MEM_REF, char_type_node, @0, + wide_int_to_tree (ptr_type_node, wi::neg (wi::to_wide (@1)))), + type); })) + /* If arg0 is derived from the address of an object or function, we may be able to fold this expression using the object or function's alignment. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0e8d77a..11061ad 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Richard Biener + + * gcc.dg/torture/20200311-1.c: New testcase. + 2020-03-11 Matthew Malcomson * lib/scanasm.exp (parse_function_bodies): Lines starting with '@' also diff --git a/gcc/testsuite/gcc.dg/torture/20200311-1.c b/gcc/testsuite/gcc.dg/torture/20200311-1.c new file mode 100644 index 0000000..ac82b6b --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/20200311-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ + +struct list { struct list *n; }; + +struct obj { + int n; + struct list l; +} _o; + +struct list _l = { .n = &_o.l }; + +int main(int argc, char *argv[]) +{ + struct obj *o = &_o; + _o.l.n = &_l; + while (&o->l != &_l) + /* Note the following is invoking undefined behavior but in + this kind of "obvious" cases we don't want to break things + unnecessarily and thus we avoid analyzing o as pointing + to nothing via the undefined pointer subtraction. Instead + we canonicalize the pointer subtraction followed by the + pointer conversion to pointer offsetting. */ + o = ((struct obj *)((const char *)(o->l.n) + - (const char *)&((struct obj *)0)->l)); + return 0; +} -- cgit v1.1 From 5fea87cc7902c7c03c0d3c8cf7784cd99db8315d Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 11 Mar 2020 17:48:10 +0800 Subject: RISC-V: Fix testsuite regression due to recent IRA changes. After IRA changes, atomic version will use one more register, but non-atomic still use 2 registers, however this testcase isn't testing for atomic feature, so I decide change the testcase to always use COUNT++ to test. ChangeLog gcc/testsuite/ Kito Cheng * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/riscv/interrupt-2.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 11061ad..e2442fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Kito Cheng + + * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. + 2020-03-11 Richard Biener * gcc.dg/torture/20200311-1.c: New testcase. diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-2.c index 9559007..82e3fb2 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-2.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-2.c @@ -8,10 +8,6 @@ foo2 (void) INTERRUPT_FLAG = 0; extern volatile int COUNTER; -#ifdef __riscv_atomic - __atomic_fetch_add (&COUNTER, 1, __ATOMIC_RELAXED); -#else COUNTER++; -#endif } /* { dg-final { scan-assembler-times "s\[wd\]\ta\[0-7\],\[0-9\]+\\(sp\\)" 2 } } */ -- cgit v1.1 From d42ff1d3b62521829d90e5b972baba2a0339e2bf Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 11 Mar 2020 18:35:13 +0100 Subject: pdp11: Fix handling of common (local and global) vars [PR94134] As mentioned in the PR, the generic code decides to put the a variable into lcomm_section, which is a NOSWITCH section and thus the generic code doesn't switch into a particular section before using ASM_OUTPUT{_ALIGNED{,_DECL}_}_LOCAL, on many targets that results just in .lcomm (or for non-local .comm) directives which don't need a switch to some section, other targets put switch_to_section (bss_section) at the start of that macro. pdp11 doesn't do that (and doesn't have bss_section), and so emits the lcomm/comm variables in whatever section is current (it has only .text/.data and for DEC assembler rodata). The following patch fixes that by putting it always into data section, and additionally avoids emitting an empty line in the assembly for the lcomm vars. 2020-03-11 Jakub Jelinek PR target/94134 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section at the start to switch to data section. Don't print extra newline if .globl directive has not been emitted. * gcc.c-torture/execute/pr94134.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/config/pdp11/pdp11.c | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 ++++++++++++++ 4 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94134.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73339dc..818cf19 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-11 Jakub Jelinek + + PR target/94134 + * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section + at the start to switch to data section. Don't print extra newline if + .globl directive has not been emitted. + 2020-03-11 Richard Biener * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index c8612ad..25590be 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -743,6 +743,7 @@ void pdp11_asm_output_var (FILE *file, const char *name, int size, int align, bool global) { + switch_to_section (data_section); if (align > 8) fprintf (file, "\t.even\n"); if (TARGET_DEC_ASM) @@ -763,8 +764,8 @@ pdp11_asm_output_var (FILE *file, const char *name, int size, { fprintf (file, ".globl "); assemble_name (file, name); + fprintf (file, "\n"); } - fprintf (file, "\n"); assemble_name (file, name); fputs (":", file); ASM_OUTPUT_SKIP (file, size); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e2442fb..ba4cd14 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-11 Jakub Jelinek + + PR target/94134 + * gcc.c-torture/execute/pr94134.c: New test. + 2020-03-11 Kito Cheng * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94134.c b/gcc/testsuite/gcc.c-torture/execute/pr94134.c new file mode 100644 index 0000000..b1b44c3 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr94134.c @@ -0,0 +1,14 @@ +/* PR target/94134 */ + +static volatile int a = 0; +static volatile int b = 1; + +int +main () +{ + a++; + b++; + if (a != 1 || b != 2) + __builtin_abort (); + return 0; +} -- cgit v1.1 From 1c43ee69f4f6148fff4b5ace80d709d7f8b250d7 Mon Sep 17 00:00:00 2001 From: Delia Burduv Date: Wed, 11 Mar 2020 18:01:26 +0000 Subject: Bug fix: cannot convert 'const short int*' to 'const __bf16*' This patch fixes a bug introduced by my earlier patch ( https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ). It introduces a new scalar builtin type that was missing in the original patch. Bootstrapped cleanly on arm-none-linux-gnueabihf. Tested for regression on arm-none-linux-gnueabihf. No regression from before the original patch. Tests that failed or became unsupported because of the original tests now work as they did before it. * config/arm/arm-builtins.c (arm_init_simd_builtin_scalar_types): New. * config/arm/arm_neon.h (vld2_bf16): Used new builtin type. (vld2q_bf16): Used new builtin type. (vld3_bf16): Used new builtin type. (vld3q_bf16): Used new builtin type. (vld4_bf16): Used new builtin type. (vld4q_bf16): Used new builtin type. (vld2_dup_bf16): Used new builtin type. (vld2q_dup_bf16): Used new builtin type. (vld3_dup_bf16): Used new builtin type. (vld3q_dup_bf16): Used new builtin type. (vld4_dup_bf16): Used new builtin type. (vld4q_dup_bf16): Used new builtin type. --- gcc/ChangeLog | 17 +++++++++++++++++ gcc/config/arm/arm-builtins.c | 4 +++- gcc/config/arm/arm_neon.h | 24 ++++++++++++------------ 3 files changed, 32 insertions(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 818cf19..dfc9b8e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2020-03-11 Delia Burduv + + * config/arm/arm-builtins.c + (arm_init_simd_builtin_scalar_types): New. + * config/arm/arm_neon.h (vld2_bf16): Used new builtin type. + (vld2q_bf16): Used new builtin type. + (vld3_bf16): Used new builtin type. + (vld3q_bf16): Used new builtin type. + (vld4_bf16): Used new builtin type. + (vld4q_bf16): Used new builtin type. + (vld2_dup_bf16): Used new builtin type. + (vld2q_dup_bf16): Used new builtin type. + (vld3_dup_bf16): Used new builtin type. + (vld3q_dup_bf16): Used new builtin type. + (vld4_dup_bf16): Used new builtin type. + (vld4q_dup_bf16): Used new builtin type. + 2020-03-11 Jakub Jelinek PR target/94134 diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index e0561c5..1f55898 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -784,6 +784,7 @@ const char *arm_scalar_builtin_types[] = { "__builtin_neon_oi", "__builtin_neon_ci", "__builtin_neon_xi", + "__builtin_neon_bf", NULL }; @@ -1101,7 +1102,8 @@ arm_init_simd_builtin_scalar_types (void) "__builtin_neon_df"); (*lang_hooks.types.register_builtin_type) (intTI_type_node, "__builtin_neon_ti"); - + (*lang_hooks.types.register_builtin_type) (arm_bf16_type_node, + "__builtin_neon_bf"); /* Unsigned integer types for various mode sizes. */ (*lang_hooks.types.register_builtin_type) (unsigned_intQI_type_node, "__builtin_neon_uqi"); diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index f5ccf18..aa21730 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -19562,7 +19562,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2_bf16 (bfloat16_t const * __ptr) { union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; - __rv.__o = __builtin_neon_vld2v4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld2v4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19571,7 +19571,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2q_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld2v8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld2v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19580,7 +19580,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld3_bf16 (const bfloat16_t * __ptr) { union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; - __rv.__o = __builtin_neon_vld3v4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld3v4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19589,7 +19589,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld3q_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld3v8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld3v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19598,7 +19598,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld4_bf16 (const bfloat16_t * __ptr) { union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld4v4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld4v4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19607,7 +19607,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld4q_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld4v8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld4v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19616,7 +19616,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; - __rv.__o = __builtin_neon_vld2_dupv4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld2_dupv4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19625,7 +19625,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2q_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld2_dupv8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld2_dupv8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19634,7 +19634,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld3_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; - __rv.__o = __builtin_neon_vld3_dupv4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld3_dupv4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19643,7 +19643,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld3q_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld3_dupv8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld3_dupv8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19652,7 +19652,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld4_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld4_dupv4bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld4_dupv4bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } @@ -19661,7 +19661,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld4q_dup_bf16 (const bfloat16_t * __ptr) { union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__o = __builtin_neon_vld4_dupv8bf ((const __builtin_neon_hi *) __ptr); + __rv.__o = __builtin_neon_vld4_dupv8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } -- cgit v1.1 From 7eb5be6ab91ec03f93038ac2bcf3028cf2e7c82b Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Fri, 6 Mar 2020 17:30:11 -0500 Subject: c++: Fix wrong modifying const object error for COMPONENT_REF [PR94074] I got a report that building Chromium fails with the "modifying a const object" error. After some poking I realized it's a bug in GCC, not in their codebase. Much like with ARRAY_REFs, which can be const even though the array itself isn't, COMPONENT_REFs can be const although neither the object nor the field were declared const. So let's dial down the checking. Here the COMPONENT_REF was const because of the "const_cast(m)" thing -- cxx_eval_component_reference then builds a COMPONENT_REF with TREE_TYPE (t). While looking into this I noticed that we don't detect modifying a const object in certain cases like in . That's because we never evaluate an X::X() CALL_EXPR -- there's none. Fixed as per Jason's suggestion by setting TREE_READONLY on a CONSTRUCTOR after initialization in cxx_eval_store_expression. 2020-03-11 Marek Polacek Jason Merrill PR c++/94074 - wrong modifying const object error for COMPONENT_REF. * constexpr.c (cref_has_const_field): New function. (modifying_const_object_p): Consider a COMPONENT_REF const only if any of its fields are const. (cxx_eval_store_expression): Mark a CONSTRUCTOR of a const type as readonly after its initialization has been done. * g++.dg/cpp1y/constexpr-tracking-const17.C: New test. * g++.dg/cpp1y/constexpr-tracking-const18.C: New test. * g++.dg/cpp1y/constexpr-tracking-const19.C: New test. * g++.dg/cpp1y/constexpr-tracking-const20.C: New test. * g++.dg/cpp1y/constexpr-tracking-const21.C: New test. * g++.dg/cpp1y/constexpr-tracking-const22.C: New test. --- gcc/cp/ChangeLog | 10 ++++++ gcc/cp/constexpr.c | 42 +++++++++++++++++++++- gcc/testsuite/ChangeLog | 10 ++++++ .../g++.dg/cpp1y/constexpr-tracking-const17.C | 23 ++++++++++++ .../g++.dg/cpp1y/constexpr-tracking-const18.C | 23 ++++++++++++ .../g++.dg/cpp1y/constexpr-tracking-const19.C | 23 ++++++++++++ .../g++.dg/cpp1y/constexpr-tracking-const20.C | 28 +++++++++++++++ .../g++.dg/cpp1y/constexpr-tracking-const21.C | 28 +++++++++++++++ .../g++.dg/cpp1y/constexpr-tracking-const22.C | 17 +++++++++ 9 files changed, 203 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const17.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const18.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const19.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const20.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ebccb51..da768cd 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2020-03-11 Marek Polacek + Jason Merrill + + PR c++/94074 - wrong modifying const object error for COMPONENT_REF. + * constexpr.c (cref_has_const_field): New function. + (modifying_const_object_p): Consider a COMPONENT_REF + const only if any of its fields are const. + (cxx_eval_store_expression): Mark a CONSTRUCTOR of a const type + as readonly after its initialization has been done. + 2020-03-10 Marek Polacek PR c++/94124 - wrong conversion error with non-viable overload. diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c index 76af0d7..192face 100644 --- a/gcc/cp/constexpr.c +++ b/gcc/cp/constexpr.c @@ -4384,6 +4384,22 @@ maybe_simplify_trivial_copy (tree &target, tree &init) } } +/* Returns true if REF, which is a COMPONENT_REF, has any fields + of constant type. This does not check for 'mutable', so the + caller is expected to be mindful of that. */ + +static bool +cref_has_const_field (tree ref) +{ + while (TREE_CODE (ref) == COMPONENT_REF) + { + if (CP_TYPE_CONST_P (TREE_TYPE (TREE_OPERAND (ref, 1)))) + return true; + ref = TREE_OPERAND (ref, 0); + } + return false; +} + /* Return true if we are modifying something that is const during constant expression evaluation. CODE is the code of the statement, OBJ is the object in question, MUTABLE_P is true if one of the subobjects were @@ -4401,7 +4417,23 @@ modifying_const_object_p (tree_code code, tree obj, bool mutable_p) if (mutable_p) return false; - return (TREE_READONLY (obj) || CP_TYPE_CONST_P (TREE_TYPE (obj))); + if (TREE_READONLY (obj)) + return true; + + if (CP_TYPE_CONST_P (TREE_TYPE (obj))) + { + /* Although a COMPONENT_REF may have a const type, we should + only consider it modifying a const object when any of the + field components is const. This can happen when using + constructs such as const_cast(m), making something + const even though it wasn't declared const. */ + if (TREE_CODE (obj) == COMPONENT_REF) + return cref_has_const_field (obj); + else + return true; + } + + return false; } /* Evaluate an INIT_EXPR or MODIFY_EXPR. */ @@ -4759,6 +4791,14 @@ cxx_eval_store_expression (const constexpr_ctx *ctx, tree t, else *valp = init; + /* After initialization, 'const' semantics apply to the value of the + object. Make a note of this fact by marking the CONSTRUCTOR + TREE_READONLY. */ + if (TREE_CODE (t) == INIT_EXPR + && TREE_CODE (*valp) == CONSTRUCTOR + && TYPE_READONLY (type)) + TREE_READONLY (*valp) = true; + /* Update TREE_CONSTANT and TREE_SIDE_EFFECTS on enclosing CONSTRUCTORs, if any. */ tree elt; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ba4cd14..1ed0071 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2020-03-06 Marek Polacek + + PR c++/94074 - wrong modifying const object error for COMPONENT_REF. + * g++.dg/cpp1y/constexpr-tracking-const17.C: New test. + * g++.dg/cpp1y/constexpr-tracking-const18.C: New test. + * g++.dg/cpp1y/constexpr-tracking-const19.C: New test. + * g++.dg/cpp1y/constexpr-tracking-const20.C: New test. + * g++.dg/cpp1y/constexpr-tracking-const21.C: New test. + * g++.dg/cpp1y/constexpr-tracking-const22.C: New test. + 2020-03-11 Jakub Jelinek PR target/94134 diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const17.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const17.C new file mode 100644 index 0000000..3f215d2 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const17.C @@ -0,0 +1,23 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +typedef decltype (sizeof (0)) size_t; + +template +struct array +{ + constexpr const E &operator[](size_t n) const noexcept { return elems[n]; } + E elems[N]; +}; + +template +struct S { + using U = array; + U m; + constexpr S(int) : m{} + { + const_cast(const_cast(m)[0]) = 42; + } +}; + +constexpr S p = { 10 }; diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const18.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const18.C new file mode 100644 index 0000000..11a6804 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const18.C @@ -0,0 +1,23 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +typedef decltype (sizeof (0)) size_t; + +template +struct array +{ + constexpr const E &operator[](size_t n) const noexcept { return elems[n]; } + E elems[N]; +}; + +template +struct S { + using U = array; + const U m; + constexpr S(int) : m{} + { + const_cast(const_cast(m)[0]) = 42; // { dg-error "modifying a const object" } + } +}; + +constexpr S p = { 10 }; // { dg-message "originally declared" } diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const19.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const19.C new file mode 100644 index 0000000..c31222f --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const19.C @@ -0,0 +1,23 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +typedef decltype (sizeof (0)) size_t; + +template +struct array +{ + constexpr const E &operator[](size_t n) const noexcept { return elems[n]; } + const E elems[N]; +}; + +template +struct S { + using U = array; + U m; + constexpr S(int) : m{} + { + const_cast(const_cast(m)[0]) = 42; // { dg-error "modifying a const object" } + } +}; + +constexpr S p = { 10 }; // { dg-message "originally declared" } diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const20.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const20.C new file mode 100644 index 0000000..2d50349 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const20.C @@ -0,0 +1,28 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +typedef decltype (sizeof (0)) size_t; + +template +struct array +{ + constexpr const E &operator[](size_t n) const noexcept { return elems[n]; } + E elems[N]; +}; + +template +struct array2 { + array a; +}; + +template +struct S { + using U = array2; + U m; + constexpr S(int) : m{} + { + const_cast(const_cast(m).a[0]) = 42; + } +}; + +constexpr S p = { 10 }; diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C new file mode 100644 index 0000000..0b16193 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C @@ -0,0 +1,28 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +typedef decltype (sizeof (0)) size_t; + +template +struct array +{ + constexpr const E &operator[](size_t n) const noexcept { return elems[n]; } + E elems[N]; +}; + +template +struct array2 { + array a; +}; + +template +struct S { + using U = array2; + const U m; + constexpr S(int) : m{} + { + const_cast(m.a[0]) = 42; // { dg-error "modifying a const object" } + } +}; + +constexpr S p = { 10 }; // { dg-message "originally declared" } diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C new file mode 100644 index 0000000..216cf16 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C @@ -0,0 +1,17 @@ +// PR c++/94074 - wrong modifying const object error for COMPONENT_REF. +// { dg-do compile { target c++14 } } + +struct X { + int i; +}; + +template +struct S { + const X x; + constexpr S(int) : x{} + { + const_cast(x).i = 19; // { dg-error "modifying a const object" } + } +}; + +constexpr S p = { 10 }; // { dg-message "originally declared" } -- cgit v1.1 From bde31a76ba48be49dbe26317ce5e19d10ae9f310 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Wed, 11 Mar 2020 00:53:01 -0400 Subject: c++: Fix ICE with concepts and aliases [PR93907]. The problem here was that we were checking satisfaction once with 'e', a typedef of 'void', and another time with 'void' directly, and treated them as different for hashing based on the assumption that canonicalize_type_argument would have already removed a typedef that wasn't a complex dependent alias. But that wasn't happening here, so let's add a call. gcc/cp/ChangeLog 2020-03-11 Jason Merrill PR c++/93907 * constraint.cc (tsubst_parameter_mapping): Canonicalize type argument. --- gcc/cp/ChangeLog | 6 ++++ gcc/cp/constraint.cc | 6 +++- gcc/cp/cp-tree.h | 1 + gcc/cp/pt.c | 2 +- gcc/testsuite/g++.dg/cpp2a/concepts-using2.C | 45 ++++++++++++++++++++++++++++ 5 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-using2.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index da768cd..8cde300 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-11 Jason Merrill + + PR c++/93907 + * constraint.cc (tsubst_parameter_mapping): Canonicalize type + argument. + 2020-03-11 Marek Polacek Jason Merrill diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc index 4bb4a3f..697ed67 100644 --- a/gcc/cp/constraint.cc +++ b/gcc/cp/constraint.cc @@ -2232,7 +2232,11 @@ tsubst_parameter_mapping (tree map, tree args, subst_info info) else if (ARGUMENT_PACK_P (arg)) new_arg = tsubst_argument_pack (arg, args, complain, in_decl); if (!new_arg) - new_arg = tsubst_template_arg (arg, args, complain, in_decl); + { + new_arg = tsubst_template_arg (arg, args, complain, in_decl); + if (TYPE_P (new_arg)) + new_arg = canonicalize_type_argument (new_arg, complain); + } if (new_arg == error_mark_node) return error_mark_node; diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 0a7381c..757cdd8 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -7016,6 +7016,7 @@ extern tree resolve_nondeduced_context_or_error (tree, tsubst_flags_t); extern hashval_t iterative_hash_template_arg (tree arg, hashval_t val); extern tree coerce_template_parms (tree, tree, tree); extern tree coerce_template_parms (tree, tree, tree, tsubst_flags_t); +extern tree canonicalize_type_argument (tree, tsubst_flags_t); extern void register_local_specialization (tree, tree); extern tree retrieve_local_specialization (tree); extern tree extract_fnparm_pack (tree, tree *); diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index cb237ba..789ccdb 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -7943,7 +7943,7 @@ template_template_parm_bindings_ok_p (tree tparms, tree targs) /* Since type attributes aren't mangled, we need to strip them from template type arguments. */ -static tree +tree canonicalize_type_argument (tree arg, tsubst_flags_t complain) { if (!arg || arg == error_mark_node || arg == TYPE_CANONICAL (arg)) diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C b/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C new file mode 100644 index 0000000..b1a45d5 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C @@ -0,0 +1,45 @@ +// PR c++/93907 +// { dg-options -std=gnu++20 } + +template struct c { + static constexpr int d = a; + typedef c e; +}; +template struct f; +template using g = typename f::e; +struct b; +template struct f { using e = b; }; +template struct m { typedef g aj; }; +template class n { typedef typename m::aj e; }; +template using an = typename n::e; +template constexpr bool ao = c::d; +template constexpr bool i = c<1>::d; +template concept bb = i; +using cc = __int128; +template concept cd = bb; +template concept ce = requires { requires cd; }; +template concept h = ce; +template concept l = h; +template concept cl = ao; +template concept cp = requires(b j) { + requires h>; +}; +struct o { + template requires cp auto operator()(b) {} +}; +template using cm = decltype(o{}(b())); +template concept ct = l; +template concept dd = ct>; +template concept de = dd; +struct { + template void operator()(da, b); +} di; +class p { + void begin(); +}; +template using df = p; +template void q() { + df k; + int d; + di(k, d); +} -- cgit v1.1 From 923e1785276034ad2bc82ba996f13f66116228fb Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 12 Mar 2020 00:16:14 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6b5fa91..e2b9f19 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200311 +20200312 -- cgit v1.1 From 690de2b706baaec628b7534a82f7feb1c42df3b5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 12 Mar 2020 01:28:55 +0100 Subject: testsuite: Fix concepts-using2.C failure on 32-bit targets [PR93907] The test FAILs on 32-bit targets that don't have __int128 type. 2020-03-12 Jakub Jelinek PR c++/93907 * g++.dg/cpp2a/concepts-using2.C (cc): Use long long instead of __int128 if __SIZEOF_INT128__ isn't defined. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/g++.dg/cpp2a/concepts-using2.C | 4 ++++ 2 files changed, 10 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1ed0071..18427eb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-12 Jakub Jelinek + + PR c++/93907 + * g++.dg/cpp2a/concepts-using2.C (cc): Use long long instead of + __int128 if __SIZEOF_INT128__ isn't defined. + 2020-03-06 Marek Polacek PR c++/94074 - wrong modifying const object error for COMPONENT_REF. diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C b/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C index b1a45d5..206b54a 100644 --- a/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-using2.C @@ -15,7 +15,11 @@ template using an = typename n::e; template constexpr bool ao = c::d; template constexpr bool i = c<1>::d; template concept bb = i; +#ifdef __SIZEOF_INT128__ using cc = __int128; +#else +using cc = long long; +#endif template concept cd = bb; template concept ce = requires { requires cd; }; template concept h = ce; -- cgit v1.1 From f457ae2218c74c9816d98d695058619a67ded6ba Mon Sep 17 00:00:00 2001 From: Bin Bin Lv Date: Wed, 11 Mar 2020 22:25:31 -0400 Subject: [rs6000] Fix a wrong GC issue The source file rs6000.c was split up into several smaller source files through commit 1acf024. However, variable "altivec_builtin_mask_for_load" and "builtin_mode_to_type[MAX_MACHINE_MODE][2]" were marked with the wrong syntax "GTY(([options])) type name", which led these two variables were not marked as roots correctly and wrongly GCed. And when "altivec_builtin_mask_for_load" was wrongly GCed, the compiling for openJDK is failed with ICEs enabling precompiled header under mcpu=power7. So roots must be declared using one of the following syntaxes: "extern GTY(([options])) type name;" and "static GTY(([options])) type name;". And the following patch adds variable "altivec_builtin_mask_for_load" and "builtin_mode_to_type[MAX_MACHINE_MODE][2]" into the roots array. Bootstrap and regression tests were done on powerpc64le-linux-gnu (LE) with no regressions. gcc/ChangeLog 2020-03-11 Bin Bin Lv * config/rs6000/rs6000-internal.h (altivec_builtin_mask_for_load, builtin_mode_to_type): Remove the declaration. * config/rs6000/rs6000.h (altivec_builtin_mask_for_load, builtin_mode_to_type): Add an extern GTY(()) declaration. * config/rs6000/rs6000.c (altivec_builtin_mask_for_load, builtin_mode_to_type): Remove the GTY(()) declaration. --- gcc/config/rs6000/rs6000-internal.h | 2 -- gcc/config/rs6000/rs6000.c | 4 ++-- gcc/config/rs6000/rs6000.h | 3 +++ 3 files changed, 5 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index a23e956..d331b9e 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -187,7 +187,5 @@ extern bool rs6000_passes_long_double; extern bool rs6000_passes_vector; extern bool rs6000_returns_struct; extern bool cpu_builtin_p; -extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; -extern GTY(()) tree altivec_builtin_mask_for_load; #endif diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 46b7dec..24598af 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -99,7 +99,7 @@ #endif /* Support targetm.vectorize.builtin_mask_for_load. */ -GTY(()) tree altivec_builtin_mask_for_load; +tree altivec_builtin_mask_for_load; #ifdef USING_ELFOS_H /* Counter for labels which are to be placed in .fixup. */ @@ -196,7 +196,7 @@ enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; int rs6000_vector_align[NUM_MACHINE_MODES]; /* Map selected modes to types for builtins. */ -GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; +tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; /* What modes to automatically generate reciprocal divide estimate (fre) and reciprocal sqrt (frsqrte) for. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 1697186..79b3dd6 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2490,6 +2490,9 @@ extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; #ifndef USED_FOR_TARGET +extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; +extern GTY(()) tree altivec_builtin_mask_for_load; + /* A C structure for machine-specific, per-function data. This is added to the cfun structure. */ typedef struct GTY(()) machine_function -- cgit v1.1 From 4069adf4bbc90d16b603e0308b48499c36b2b637 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 12 Mar 2020 08:28:05 +0100 Subject: c++: Tweak reshape_init_array_1 [PR94124] Isn't it wasteful to first copy perhaps a large constructor (recursively) and then truncate it to very few elts (zero in this case)? > We should certainly avoid copying if they're the same. The code above for > only copying the bits that aren't going to be thrown away seems pretty > straightforward, might as well use it even if the savings aren't likely to > be large. Calling vec_safe_truncate with the same number of elts the vector already has is a nop, so IMHO we just should make sure we only unshare if it changed. 2020-03-12 Jakub Jelinek PR c++/94124 * decl.c (reshape_init_array_1): Don't unshare constructor if there aren't any trailing zero elts, otherwise only unshare the first nelts. --- gcc/cp/ChangeLog | 9 ++++++++- gcc/cp/decl.c | 19 +++++++++++++++---- 2 files changed, 23 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 8cde300..b94e3bb 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2020-03-12 Jakub Jelinek + + PR c++/94124 + * decl.c (reshape_init_array_1): Don't unshare constructor if there + aren't any trailing zero elts, otherwise only unshare the first + nelts. + 2020-03-11 Jason Merrill PR c++/93907 @@ -27,7 +34,7 @@ 2020-03-10 Jason Merrill - PR c++/93956 + PR c++/93596 * pt.c (maybe_aggr_guide): Check BRACE_ENCLOSED_INITIALIZER_P. 2020-03-10 Jason Merrill diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index aa58e5f..d240436 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -6066,10 +6066,21 @@ reshape_init_array_1 (tree elt_type, tree max_index, reshape_iter *d, overload resolution. E.g., initializing a class from {{0}} might be invalid while initializing the same class from {{}} might be valid. */ - if (reuse) - new_init = unshare_constructor (new_init); - - vec_safe_truncate (CONSTRUCTOR_ELTS (new_init), nelts); + if (reuse && nelts < CONSTRUCTOR_NELTS (new_init)) + { + vec *v; + vec_alloc (v, nelts); + for (unsigned int i = 0; i < nelts; i++) + { + constructor_elt elt = *CONSTRUCTOR_ELT (new_init, i); + if (TREE_CODE (elt.value) == CONSTRUCTOR) + elt.value = unshare_constructor (elt.value); + v->quick_push (elt); + } + new_init = build_constructor (TREE_TYPE (new_init), v); + } + else + vec_safe_truncate (CONSTRUCTOR_ELTS (new_init), nelts); } return new_init; -- cgit v1.1 From 349ab34dc64a10fe0b1eda66d13b62862878b73e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 12 Mar 2020 09:34:00 +0100 Subject: tree-dse: Fix mem* head trimming if call has lhs [PR94130] As the testcase shows, if DSE decides to head trim {mem{set,cpy,move},strncpy} and the call has lhs, it is incorrect to leave the lhs as is, because it will then point to the adjusted address (base + head_trim) instead of the original base. The following patch fixes that by dropping the lhs of the call and assigning lhs the original base in a following statement. 2020-03-12 Jakub Jelinek PR tree-optimization/94130 * tree-ssa-dse.c: Include gimplify.h. (increment_start_addr): If stmt has lhs, drop the lhs from call and set it after the call to the original value of the first argument. Formatting fixes. (decrement_count): Formatting fix. * gcc.c-torture/execute/pr94130.c: New test. --- gcc/ChangeLog | 9 +++++++++ gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 ++++++++++++++++ gcc/tree-ssa-dse.c | 22 ++++++++++++++++------ 4 files changed, 44 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94130.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dfc9b8e..d6a7508 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-12 Jakub Jelinek + + PR tree-optimization/94130 + * tree-ssa-dse.c: Include gimplify.h. + (increment_start_addr): If stmt has lhs, drop the lhs from call and + set it after the call to the original value of the first argument. + Formatting fixes. + (decrement_count): Formatting fix. + 2020-03-11 Delia Burduv * config/arm/arm-builtins.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 18427eb..5e232c6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-12 Jakub Jelinek + PR tree-optimization/94130 + * gcc.c-torture/execute/pr94130.c: New test. + PR c++/93907 * g++.dg/cpp2a/concepts-using2.C (cc): Use long long instead of __int128 if __SIZEOF_INT128__ isn't defined. diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94130.c b/gcc/testsuite/gcc.c-torture/execute/pr94130.c new file mode 100644 index 0000000..044e578 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr94130.c @@ -0,0 +1,16 @@ +/* PR tree-optimization/94130 */ + +int +main () +{ + int a[8]; + char *b = __builtin_memset (a, 0, sizeof (a)); + a[0] = 1; + a[1] = 2; + a[2] = 3; + if (b != (char *) a) + __builtin_abort (); + else + asm volatile ("" : : "g" (a) : "memory"); + return 0; +} diff --git a/gcc/tree-ssa-dse.c b/gcc/tree-ssa-dse.c index f2a4ed9..3ab15e2 100644 --- a/gcc/tree-ssa-dse.c +++ b/gcc/tree-ssa-dse.c @@ -38,6 +38,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-dse.h" #include "builtins.h" #include "gimple-fold.h" +#include "gimplify.h" /* This file implements dead store elimination. @@ -422,29 +423,38 @@ decrement_count (gimple *stmt, int decrement) gcc_assert (TREE_CODE (*countp) == INTEGER_CST); *countp = wide_int_to_tree (TREE_TYPE (*countp), (TREE_INT_CST_LOW (*countp) - decrement)); - } static void increment_start_addr (gimple *stmt, tree *where, int increment) { + if (tree lhs = gimple_call_lhs (stmt)) + if (where == gimple_call_arg_ptr (stmt, 0)) + { + gassign *newop = gimple_build_assign (lhs, unshare_expr (*where)); + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + gsi_insert_after (&gsi, newop, GSI_SAME_STMT); + gimple_call_set_lhs (stmt, NULL_TREE); + update_stmt (stmt); + } + if (TREE_CODE (*where) == SSA_NAME) { tree tem = make_ssa_name (TREE_TYPE (*where)); gassign *newop - = gimple_build_assign (tem, POINTER_PLUS_EXPR, *where, + = gimple_build_assign (tem, POINTER_PLUS_EXPR, *where, build_int_cst (sizetype, increment)); gimple_stmt_iterator gsi = gsi_for_stmt (stmt); gsi_insert_before (&gsi, newop, GSI_SAME_STMT); *where = tem; - update_stmt (gsi_stmt (gsi)); + update_stmt (stmt); return; } *where = build_fold_addr_expr (fold_build2 (MEM_REF, char_type_node, - *where, - build_int_cst (ptr_type_node, - increment))); + *where, + build_int_cst (ptr_type_node, + increment))); } /* STMT is builtin call that writes bytes in bitmap ORIG, some bytes are dead -- cgit v1.1 From b73f69020f08208d2d969fcf8879bd294a6e3596 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 12 Mar 2020 09:35:30 +0100 Subject: doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description When looking into PR94134, I've noticed bugs in the ASM_OUTPUT_ALIGNED_DECL_LOCAL documentation. varasm.c has: #if defined ASM_OUTPUT_ALIGNED_DECL_LOCAL unsigned int align = symtab_node::get (decl)->definition_alignment (); ASM_OUTPUT_ALIGNED_DECL_LOCAL (asm_out_file, decl, name, size, align); return true; #elif defined ASM_OUTPUT_ALIGNED_LOCAL unsigned int align = symtab_node::get (decl)->definition_alignment (); ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size, align); return true; #else ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded); return false; #endif and the ASM_OUTPUT_ALIGNED_LOCAL documentation properly mentions: Like @code{ASM_OUTPUT_LOCAL} and mentions the same macro in another place. The ASM_OUTPUT_ALIGNED_DECL_LOCAL description mentions non-existing macros ASM_OUTPUT_ALIGNED_DECL and ASM_OUTPUT_DECL instead of the right ones ASM_OUTPUT_ALIGNED_LOCAL and ASM_OUTPUT_LOCAL. 2020-03-12 Jakub Jelinek * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL. * doc/tm.texi: Regenerated. --- gcc/ChangeLog | 5 +++++ gcc/doc/tm.texi | 6 +++--- gcc/doc/tm.texi.in | 6 +++--- 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6a7508..a09c478 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-03-12 Jakub Jelinek + * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change + ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL + and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL. + * doc/tm.texi: Regenerated. + PR tree-optimization/94130 * tree-ssa-dse.c: Include gimplify.h. (increment_start_addr): If stmt has lhs, drop the lhs from call and diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 19985ad..3560cfa 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -8384,11 +8384,11 @@ as the number of bits. @end defmac @defmac ASM_OUTPUT_ALIGNED_DECL_LOCAL (@var{stream}, @var{decl}, @var{name}, @var{size}, @var{alignment}) -Like @code{ASM_OUTPUT_ALIGNED_DECL} except that @var{decl} of the +Like @code{ASM_OUTPUT_ALIGNED_LOCAL} except that @var{decl} of the variable to be output, if there is one, or @code{NULL_TREE} if there is no corresponding variable. If you define this macro, GCC will use it -in place of both @code{ASM_OUTPUT_DECL} and -@code{ASM_OUTPUT_ALIGNED_DECL}. Define this macro when you need to see +in place of both @code{ASM_OUTPUT_LOCAL} and +@code{ASM_OUTPUT_ALIGNED_LOCAL}. Define this macro when you need to see the variable's decl in order to chose what to output. @end defmac diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 1a16150..e31cdb2 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -5410,11 +5410,11 @@ as the number of bits. @end defmac @defmac ASM_OUTPUT_ALIGNED_DECL_LOCAL (@var{stream}, @var{decl}, @var{name}, @var{size}, @var{alignment}) -Like @code{ASM_OUTPUT_ALIGNED_DECL} except that @var{decl} of the +Like @code{ASM_OUTPUT_ALIGNED_LOCAL} except that @var{decl} of the variable to be output, if there is one, or @code{NULL_TREE} if there is no corresponding variable. If you define this macro, GCC will use it -in place of both @code{ASM_OUTPUT_DECL} and -@code{ASM_OUTPUT_ALIGNED_DECL}. Define this macro when you need to see +in place of both @code{ASM_OUTPUT_LOCAL} and +@code{ASM_OUTPUT_ALIGNED_LOCAL}. Define this macro when you need to see the variable's decl in order to chose what to output. @end defmac -- cgit v1.1 From 98aeb1ef510204bf90e94b6cc85e5ba68df93d00 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Thu, 12 Mar 2020 10:57:56 +0100 Subject: [Fortran, OpenACC] Reject vars of different scope in $acc declare (PR94120) 2020-03-12 Tobias Burnus PR middle-end/94120 * openmp.c (gfc_match_oacc_declare): Accept function-result variables; reject variables declared in a different scoping unit. 2020-03-12 Tobias Burnus PR middle-end/94120 * gfortran.dg/goacc/pr78260-2.f90: Correct scan-tree-dump-times. Extend test case to result variables. * gfortran.dg/goacc/declare-2.f95: Actually check module-declaration restriction of OpenACC. * gfortran.dg/goacc/declare-3.f95: Remove case where this restriction is violated. * gfortran.dg/goacc/pr94120-1.f90: New. * gfortran.dg/goacc/pr94120-2.f90: New. * gfortran.dg/goacc/pr94120-3.f90: New. --- gcc/fortran/ChangeLog | 6 ++++++ gcc/fortran/openmp.c | 12 +++++++++++- gcc/testsuite/ChangeLog | 13 +++++++++++++ gcc/testsuite/gfortran.dg/goacc/declare-2.f95 | 21 ++++++++++++++++----- gcc/testsuite/gfortran.dg/goacc/declare-3.f95 | 10 +--------- gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 | 13 +++++++++++-- gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 | 11 +++++++++++ gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 | 12 ++++++++++++ gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 | 13 +++++++++++++ 9 files changed, 94 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index b3ff063..661e4ce 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2020-03-12 Tobias Burnus + + PR middle-end/94120 + * openmp.c (gfc_match_oacc_declare): Accept function-result + variables; reject variables declared in a different scoping unit. + 2020-03-08 Paul Thomas PR fortran/93581 diff --git a/gcc/fortran/openmp.c b/gcc/fortran/openmp.c index 35f6b2f..930bca5 100644 --- a/gcc/fortran/openmp.c +++ b/gcc/fortran/openmp.c @@ -2155,7 +2155,8 @@ gfc_match_oacc_declare (void) { gfc_symbol *s = n->sym; - if (s->ns->proc_name && s->ns->proc_name->attr.proc == PROC_MODULE) + if (gfc_current_ns->proc_name + && gfc_current_ns->proc_name->attr.flavor == FL_MODULE) { if (n->u.map_op != OMP_MAP_ALLOC && n->u.map_op != OMP_MAP_TO) { @@ -2174,6 +2175,15 @@ gfc_match_oacc_declare (void) return MATCH_ERROR; } + if ((s->result == s && s->ns->contained != gfc_current_ns) + || ((s->attr.flavor == FL_UNKNOWN || s->attr.flavor == FL_VARIABLE) + && s->ns != gfc_current_ns)) + { + gfc_error ("Variable %qs shall be declared in the same scoping unit " + "as !$ACC DECLARE at %L", s->name, &where); + return MATCH_ERROR; + } + if ((s->attr.dimension || s->attr.codimension) && s->attr.dummy && s->as->type != AS_EXPLICIT) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5e232c6..a1f0e3a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2020-03-12 Tobias Burnus + + PR middle-end/94120 + * gfortran.dg/goacc/pr78260-2.f90: Correct scan-tree-dump-times. + Extend test case to result variables. + * gfortran.dg/goacc/declare-2.f95: Actually check module-declaration + restriction of OpenACC. + * gfortran.dg/goacc/declare-3.f95: Remove case where this + restriction is violated. + * gfortran.dg/goacc/pr94120-1.f90: New. + * gfortran.dg/goacc/pr94120-2.f90: New. + * gfortran.dg/goacc/pr94120-3.f90: New. + 2020-03-12 Jakub Jelinek PR tree-optimization/94130 diff --git a/gcc/testsuite/gfortran.dg/goacc/declare-2.f95 b/gcc/testsuite/gfortran.dg/goacc/declare-2.f95 index 7aa3dab..bad5de9 100644 --- a/gcc/testsuite/gfortran.dg/goacc/declare-2.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/declare-2.f95 @@ -1,9 +1,5 @@ module amod - -contains - -subroutine asubr (b) implicit none integer :: b(8) @@ -16,9 +12,24 @@ subroutine asubr (b) !$acc declare present_or_create (b) ! { dg-error "present on multiple" } !$acc declare deviceptr (b) ! { dg-error "Invalid clause in module" } !$acc declare create (b) copyin (b) ! { dg-error "present on multiple" } +end module +module amod2 +contains +subroutine asubr (a, b, c, d, e, f, g, h, i, j, k) + implicit none + integer, dimension(8) :: a, b, c, d, e, f, g, h, i, j, k + + !$acc declare copy (a) + !$acc declare copyout (b) + !$acc declare present (c) + !$acc declare present_or_copy (d) + !$acc declare present_or_copyin (e) + !$acc declare present_or_copyout (f) + !$acc declare present_or_create (g) + !$acc declare deviceptr (h) + !$acc declare create (j) copyin (k) end subroutine - end module module bmod diff --git a/gcc/testsuite/gfortran.dg/goacc/declare-3.f95 b/gcc/testsuite/gfortran.dg/goacc/declare-3.f95 index 80d9903..9127cba 100644 --- a/gcc/testsuite/gfortran.dg/goacc/declare-3.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/declare-3.f95 @@ -14,12 +14,6 @@ module mod_b !$acc declare copyin (b) end module -module mod_c - implicit none - integer :: c - !$acc declare deviceptr (c) -end module - module mod_d implicit none integer :: d @@ -35,7 +29,6 @@ end module subroutine sub1 use mod_a use mod_b - use mod_c use mod_d use mod_e end subroutine sub1 @@ -43,11 +36,10 @@ end subroutine sub1 program test use mod_a use mod_b - use mod_c use mod_d use mod_e - ! { dg-final { scan-tree-dump {(?n)#pragma acc data map\(force_alloc:d\) map\(force_deviceptr:c\) map\(force_to:b\) map\(force_alloc:a\)$} original } } + ! { dg-final { scan-tree-dump {(?n)#pragma acc data map\(force_alloc:d\) map\(force_to:b\) map\(force_alloc:a\)$} original } } end program test ! { dg-final { scan-tree-dump-times {#pragma acc data} 1 original } } diff --git a/gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 b/gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 index e28564d..f8a3dc8 100644 --- a/gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 @@ -4,6 +4,8 @@ ! PR fortran/78260 +! Loosely related to PR fortran/94120 + module m implicit none integer :: n = 0 @@ -14,7 +16,14 @@ contains f1 = 5 !$acc end kernels end function f1 + integer function g1() result(g1res) + !$acc declare present(g1res) + !$acc kernels copyin(g1res) + g1res = 5 + !$acc end kernels + end function g1 end module m ! { dg-final { scan-tree-dump-times "#pragma acc data map\\(force_present:__result_f1\\)" 1 "original" } } -! { dg-final { scan-tree-dump-times "#pragma acc data map\\(force_present:__result_f1\\)" 1 "original" } } - +! { dg-final { scan-tree-dump-times "#pragma acc kernels map\\(to:__result_f1\\)" 1 "original" } } +! { dg-final { scan-tree-dump-times "#pragma acc data map\\(force_present:g1res\\)" 1 "original" } } +! { dg-final { scan-tree-dump-times "#pragma acc kernels map\\(to:g1res\\)" 1 "original" } } diff --git a/gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 b/gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 new file mode 100644 index 0000000..8d1fc16 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 @@ -0,0 +1,11 @@ +! { dg-do compile } +! +! PR fortran/94120 +! +implicit none +integer :: i +contains + subroutine f() + !$acc declare copy(i) ! { dg-error "Variable 'i' shall be declared in the same scoping unit as !.ACC DECLARE" } + end +end diff --git a/gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 b/gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 new file mode 100644 index 0000000..216c04b --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 @@ -0,0 +1,12 @@ +! { dg-do compile } +! +! PR fortran/94120 +! +! BLOCK is not supported in OpenACC <= 3.0 +! +subroutine f() + block + integer :: k + !$acc declare copy(j) ! { dg-error "Sorry, !.ACC DECLARE at .1. is not allowed in BLOCK construct" } + end block +end diff --git a/gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 b/gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 new file mode 100644 index 0000000..1eec90a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 @@ -0,0 +1,13 @@ +! { dg-do compile } +! +! PR fortran/94120 +! +! Note: BLOCK is not supported in OpenACC <= 3.0 – but the following check comes earlier: +! It is also invalid because the variable is in a different scoping unit +! +subroutine g() + integer :: k + block + !$acc declare copy(k) ! { dg-error "Variable 'k' shall be declared in the same scoping unit as !.ACC DECLARE" } + end block +end -- cgit v1.1 From 54f46d82f54ba7a4110cef102b7c18eaf8b4b6bd Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 12 Mar 2020 03:47:45 -0700 Subject: i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV There is no need to set mode attribute to XImode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI, MODE_V1DF and MODE_V2SF. * config/i386/mmx.md (MMXMODE:*mov_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand check. --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/i386.c | 19 +++++++++++++++++++ gcc/config/i386/mmx.md | 29 ++--------------------------- 3 files changed, 30 insertions(+), 27 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a09c478..22ba5ed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-12 H.J. Lu + + PR target/89229 + * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI, + MODE_V1DF and MODE_V2SF. + * config/i386/mmx.md (MMXMODE:*mov_internal): Call + ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand + check. + 2020-03-12 Jakub Jelinek * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7bbfbb4..6d83855 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5118,6 +5118,25 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands) case MODE_V4SF: return ix86_get_ssemov (operands, 16, insn_mode, mode); + case MODE_DI: + /* Handle broken assemblers that require movd instead of movq. */ + if (!HAVE_AS_IX86_INTERUNIT_MOVQ + && (GENERAL_REG_P (operands[0]) + || GENERAL_REG_P (operands[1]))) + return "%vmovd\t{%1, %0|%0, %1}"; + else + return "%vmovq\t{%1, %0|%0, %1}"; + + case MODE_V1DF: + gcc_assert (!TARGET_AVX); + return "movlpd\t{%1, %0|%0, %1}"; + + case MODE_V2SF: + if (TARGET_AVX && REG_P (operands[0])) + return "vmovlps\t{%1, %d0|%d0, %1}"; + else + return "%vmovlps\t{%1, %0|%0, %1}"; + default: gcc_unreachable (); } diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index e1c8b0a..c3f195bb 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -118,29 +118,7 @@ return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_DI: - /* Handle broken assemblers that require movd instead of movq. */ - if (!HAVE_AS_IX86_INTERUNIT_MOVQ - && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) - return "%vmovd\t{%1, %0|%0, %1}"; - return "%vmovq\t{%1, %0|%0, %1}"; - case MODE_TI: - return "%vmovdqa\t{%1, %0|%0, %1}"; - case MODE_XI: - return "vmovdqa64\t{%g1, %g0|%g0, %g1}"; - - case MODE_V2SF: - if (TARGET_AVX && REG_P (operands[0])) - return "vmovlps\t{%1, %0, %0|%0, %0, %1}"; - return "%vmovlps\t{%1, %0|%0, %1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); default: gcc_unreachable (); @@ -189,10 +167,7 @@ (cond [(eq_attr "alternative" "2") (const_string "SI") (eq_attr "alternative" "11,12") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) - (const_string "XI") - (match_test "mode == V2SFmode") + (cond [(match_test "mode == V2SFmode") (const_string "V4SF") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) -- cgit v1.1 From 1dc00a8ec9aeba86b74b16bff6f171824bb7b4a1 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 12 Mar 2020 14:18:35 +0100 Subject: tree-optimization/94103 avoid CSE of loads with padding VN currently replaces a load of a 16 byte entity 128 bits of precision (TImode) with the result of a load of a 16 byte entity with 80 bits of mode precision (XFmode). That will go downhill since if the padding bits are not actually filled with memory contents those bits are missing. 2020-03-12 Richard Biener PR tree-optimization/94103 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type punning when the mode precision is not sufficient. * gcc.target/i386/pr94103.c: New testcase. --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr94103.c | 17 +++++++++++++++++ gcc/tree-ssa-sccvn.c | 23 ++++++++++++++++------- 4 files changed, 44 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr94103.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 22ba5ed..a43b453 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-12 Richard Biener + + PR tree-optimization/94103 + * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type + punning when the mode precision is not sufficient. + 2020-03-12 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a1f0e3a..a5730eb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-12 Richard Biener + + PR tree-optimization/94103 + * gcc.target/i386/pr94103.c: New testcase. + 2020-03-12 Tobias Burnus PR middle-end/94120 diff --git a/gcc/testsuite/gcc.target/i386/pr94103.c b/gcc/testsuite/gcc.target/i386/pr94103.c new file mode 100644 index 0000000..91b5fc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94103.c @@ -0,0 +1,17 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O3" } */ + +int main() +{ + long double x; + unsigned long u[2] = {0xEEEEEEEEEEEEEEEEUL, 0xEEEEEEEEEEEEEEEEUL}; + __builtin_memcpy(&x, &u, sizeof x); + __builtin_memcpy(&u, &x, sizeof u); + ++*(unsigned char *)&x; + (void)-x; + __builtin_memcpy(&u, &x, sizeof u); + if (u[1] != 0xEEEEEEEEEEEEEEEEUL + || u[0] != 0xEEEEEEEEEEEEEEEFUL) + __builtin_abort (); + return 0; +} diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index b7174cd..150ddad 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -4899,13 +4899,22 @@ visit_reference_op_load (tree lhs, tree op, gimple *stmt) if (result && !useless_type_conversion_p (TREE_TYPE (result), TREE_TYPE (op))) { - /* We will be setting the value number of lhs to the value number - of VIEW_CONVERT_EXPR (result). - So first simplify and lookup this expression to see if it - is already available. */ - gimple_match_op res_op (gimple_match_cond::UNCOND, - VIEW_CONVERT_EXPR, TREE_TYPE (op), result); - result = vn_nary_build_or_lookup (&res_op); + /* Avoid the type punning in case the result mode has padding where + the op we lookup has not. */ + if (maybe_lt (GET_MODE_PRECISION (TYPE_MODE (TREE_TYPE (result))), + GET_MODE_PRECISION (TYPE_MODE (TREE_TYPE (op))))) + result = NULL_TREE; + else + { + /* We will be setting the value number of lhs to the value number + of VIEW_CONVERT_EXPR (result). + So first simplify and lookup this expression to see if it + is already available. */ + gimple_match_op res_op (gimple_match_cond::UNCOND, + VIEW_CONVERT_EXPR, TREE_TYPE (op), result); + result = vn_nary_build_or_lookup (&res_op); + } + /* When building the conversion fails avoid inserting the reference again. */ if (!result) -- cgit v1.1 From daf2852b883762d921361462dad1f99320faca2a Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 12 Mar 2020 13:41:28 -0600 Subject: Support for the CPEN control register was removed in rev .50 of the RXv1 Instruction Set Architecture manual in Feb 2009. This patch removes it from GCC. * config/rx/rx.md (CTRLREG_CPEN): Remove. * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support. --- gcc/ChangeLog | 5 +++++ gcc/config/rx/rx.c | 1 - gcc/config/rx/rx.md | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a43b453..b184a1a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-12 Darius Galis + + * config/rx/rx.md (CTRLREG_CPEN): Remove. + * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support. + 2020-03-12 Richard Biener PR tree-optimization/94103 diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index 0a51124..151ad39 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -641,7 +641,6 @@ rx_print_operand (FILE * file, rtx op, int letter) case CTRLREG_PSW: fprintf (file, "psw"); break; case CTRLREG_USP: fprintf (file, "usp"); break; case CTRLREG_FPSW: fprintf (file, "fpsw"); break; - case CTRLREG_CPEN: fprintf (file, "cpen"); break; case CTRLREG_BPSW: fprintf (file, "bpsw"); break; case CTRLREG_BPC: fprintf (file, "bpc"); break; case CTRLREG_ISP: fprintf (file, "isp"); break; diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 0cf5025..df08a9e 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -79,7 +79,6 @@ (CTRLREG_PSW 0) (CTRLREG_USP 2) (CTRLREG_FPSW 3) - (CTRLREG_CPEN 4) (CTRLREG_BPSW 8) (CTRLREG_BPC 9) (CTRLREG_ISP 10) -- cgit v1.1 From 4aded535ea6ad7c362ab62d99af70e53c186d582 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 12 Mar 2020 16:09:27 -0600 Subject: Remove no-op register to register copies in CSE just like we remove no-op memory to memory copies. PR rtl-optimization/90275 * cse.c (cse_insn): Delete no-op register moves too. PR rtl-optimization/90275 * gcc.c-torture/compile/pr90275.c: New test. --- gcc/ChangeLog | 5 +++++ gcc/cse.c | 14 ++++++++------ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.c-torture/compile/pr90275.c | 27 +++++++++++++++++++++++++++ 4 files changed, 45 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr90275.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b184a1a..f1a1984 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-12 Richard Sandiford + + PR rtl-optimization/90275 + * cse.c (cse_insn): Delete no-op register moves too. + 2020-03-12 Darius Galis * config/rx/rx.md (CTRLREG_CPEN): Remove. diff --git a/gcc/cse.c b/gcc/cse.c index 79ee0ce..08984c1 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -4625,7 +4625,7 @@ cse_insn (rtx_insn *insn) for (i = 0; i < n_sets; i++) { bool repeat = false; - bool mem_noop_insn = false; + bool noop_insn = false; rtx src, dest; rtx src_folded; struct table_elt *elt = 0, *p; @@ -5324,9 +5324,11 @@ cse_insn (rtx_insn *insn) } /* Similarly, lots of targets don't allow no-op - (set (mem x) (mem x)) moves. */ + (set (mem x) (mem x)) moves. Even (set (reg x) (reg x)) + might be impossible for certain registers (like CC registers). */ else if (n_sets == 1 - && MEM_P (trial) + && !CALL_P (insn) + && (MEM_P (trial) || REG_P (trial)) && MEM_P (dest) && rtx_equal_p (trial, dest) && !side_effects_p (dest) @@ -5334,7 +5336,7 @@ cse_insn (rtx_insn *insn) || insn_nothrow_p (insn))) { SET_SRC (sets[i].rtl) = trial; - mem_noop_insn = true; + noop_insn = true; break; } @@ -5562,8 +5564,8 @@ cse_insn (rtx_insn *insn) sets[i].rtl = 0; } - /* Similarly for no-op MEM moves. */ - else if (mem_noop_insn) + /* Similarly for no-op moves. */ + else if (noop_insn) { if (cfun->can_throw_non_call_exceptions && can_throw_internal (insn)) cse_cfg_altered = true; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a5730eb..6d8eac2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-12 Jeff Law + + PR rtl-optimization/90275 + * gcc.c-torture/compile/pr90275.c: New test. + 2020-03-12 Richard Biener PR tree-optimization/94103 diff --git a/gcc/testsuite/gcc.c-torture/compile/pr90275.c b/gcc/testsuite/gcc.c-torture/compile/pr90275.c new file mode 100644 index 0000000..83e0df7 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr90275.c @@ -0,0 +1,27 @@ +a, b, c; + +long long d; + +e() { + + char f; + + for (;;) { + + c = a = c ? 5 : 0; + + if (f) { + + b = a; + + f = d; + + } + + (d || b) < (a > e) ?: (b ? 0 : f) || (d -= f); + + } + +} + + -- cgit v1.1 From 54e69cb00da0b50e4fa228a0617e4e8713bbc998 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 13 Mar 2020 00:16:15 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e2b9f19..a30f6fc 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200312 +20200313 -- cgit v1.1 From 82f620e2ba4c440c5e89bb1f73d10a11ed0f2eb4 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Fri, 13 Mar 2020 09:16:29 +0100 Subject: Fix unaligned load with small memcpy on the ARM store_integral_bit_field is ready to handle BLKmode fields, there is even a subtlety with their handling on big-endian targets, see e.g. PR middle-end/50325, but not if they are unaligned, so the fix is simply to call extract_bit_field for them in order to generate an unaligned load. As a bonus, this subsumes the big-endian specific path that was added under PR middle-end/50325. PR middle-end/92071 * expmed.c (store_integral_bit_field): For fields larger than a word, call extract_bit_field on the value if the mode is BLKmode. Remove specific path for big-endian targets and tidy things up a little bit. --- gcc/ChangeLog | 7 +++ gcc/expmed.c | 55 +++++++++++------------- gcc/testsuite/ChangeLog | 4 ++ gcc/testsuite/gcc.c-torture/compile/20200313-1.c | 14 ++++++ 4 files changed, 50 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/20200313-1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f1a1984..7b573c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-03-13 Eric Botcazou + + PR middle-end/92071 + * expmed.c (store_integral_bit_field): For fields larger than a word, + call extract_bit_field on the value if the mode is BLKmode. Remove + specific path for big-endian targets and tidy things up a little bit. + 2020-03-12 Richard Sandiford PR rtl-optimization/90275 diff --git a/gcc/expmed.c b/gcc/expmed.c index 0461027..e7c03fb 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -933,8 +933,7 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, However, only do that if the value is not BLKmode. */ const bool backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode; - unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; - unsigned int i; + const int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; rtx_insn *last; /* This is the mode we must force value to, so that there will be enough @@ -950,35 +949,31 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, value_mode = smallest_int_mode_for_size (nwords * BITS_PER_WORD); last = get_last_insn (); - for (i = 0; i < nwords; i++) + for (int i = 0; i < nwords; i++) { - /* If I is 0, use the low-order word in both field and target; - if I is 1, use the next to lowest word; and so on. */ - unsigned int wordnum = (backwards - ? GET_MODE_SIZE (value_mode) / UNITS_PER_WORD - - i - 1 - : i); - unsigned int bit_offset = (backwards ^ reverse - ? MAX ((int) bitsize - ((int) i + 1) - * BITS_PER_WORD, - 0) - : (int) i * BITS_PER_WORD); - rtx value_word = operand_subword_force (value, wordnum, value_mode); - unsigned HOST_WIDE_INT new_bitsize = - MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD); - - /* If the remaining chunk doesn't have full wordsize we have - to make sure that for big-endian machines the higher order - bits are used. */ - if (new_bitsize < BITS_PER_WORD && BYTES_BIG_ENDIAN && !backwards) - { - int shift = BITS_PER_WORD - new_bitsize; - rtx shift_rtx = gen_int_shift_amount (word_mode, shift); - value_word = simplify_expand_binop (word_mode, lshr_optab, - value_word, shift_rtx, - NULL_RTX, true, - OPTAB_LIB_WIDEN); - } + /* Number of bits to be stored in this iteration, i.e. BITS_PER_WORD + except maybe for the last iteration. */ + const unsigned HOST_WIDE_INT new_bitsize + = MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD); + /* Bit offset from the starting bit number in the target. */ + const unsigned int bit_offset + = backwards ^ reverse + ? MAX ((int) bitsize - (i + 1) * BITS_PER_WORD, 0) + : i * BITS_PER_WORD; + /* Starting word number in the value. */ + const unsigned int wordnum + = backwards + ? GET_MODE_SIZE (value_mode) / UNITS_PER_WORD - (i + 1) + : i; + /* The chunk of the value in word_mode. We use bit-field extraction + in BLKmode to handle unaligned memory references and to shift the + last chunk right on big-endian machines if need be. */ + rtx value_word + = fieldmode == BLKmode + ? extract_bit_field (value, new_bitsize, wordnum * BITS_PER_WORD, + 1, NULL_RTX, word_mode, word_mode, false, + NULL) + : operand_subword_force (value, wordnum, value_mode); if (!store_bit_field_1 (op0, new_bitsize, bitnum + bit_offset, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6d8eac2..e695b9b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-03-13 Eric Botcazou + + * gcc.c-torture/compile/20200313-1.c: New test. + 2020-03-12 Jeff Law PR rtl-optimization/90275 diff --git a/gcc/testsuite/gcc.c-torture/compile/20200313-1.c b/gcc/testsuite/gcc.c-torture/compile/20200313-1.c new file mode 100644 index 0000000..4791bad --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/20200313-1.c @@ -0,0 +1,14 @@ +/* PR middle-end/92071 */ +/* Testcase by David Binderman */ + +void *a; +union U { double c; char d[8]; }; +void bar (union U); + +void +foo (void) +{ + union U b; + __builtin_memcpy (b.d, a, 8); + bar (b); +} -- cgit v1.1 From 3e6ab5cefa81165e90fb62abf50e515f85a17e9a Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Fri, 13 Mar 2020 09:58:44 +0100 Subject: Fix incorrect filling of delay slots in branchy code at -O2 The issue is that relax_delay_slots can streamline the CFG in some cases, in particular remove BARRIERs, but removing BARRIERs changes the way the instructions are associated with (basic) blocks by the liveness analysis code in resource.c (find_basic_block) and thus can cause entries in the cache maintained by resource.c to become outdated, thus producing wrong answers downstream. The fix is to invalidate the cache entries affected by the removal of BARRIERs in relax_delay_slots, i.e. for the instructions down to the next BARRIER. PR rtl-optimization/94119 * resource.h (clear_hashed_info_until_next_barrier): Declare. * resource.c (clear_hashed_info_until_next_barrier): New function. * reorg.c (add_to_delay_list): Fix formatting. (relax_delay_slots): Call clear_hashed_info_until_next_barrier on the next instruction after removing a BARRIER. --- gcc/ChangeLog | 9 +++++++++ gcc/reorg.c | 26 +++++++++++++++++++------- gcc/resource.c | 21 ++++++++++++++++++++- gcc/resource.h | 1 + 4 files changed, 49 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7b573c0..6198289 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2019-03-13 Eric Botcazou + PR rtl-optimization/94119 + * resource.h (clear_hashed_info_until_next_barrier): Declare. + * resource.c (clear_hashed_info_until_next_barrier): New function. + * reorg.c (add_to_delay_list): Fix formatting. + (relax_delay_slots): Call clear_hashed_info_until_next_barrier on + the next instruction after removing a BARRIER. + +2019-03-13 Eric Botcazou + PR middle-end/92071 * expmed.c (store_integral_bit_field): For fields larger than a word, call extract_bit_field on the value if the mode is BLKmode. Remove diff --git a/gcc/reorg.c b/gcc/reorg.c index dfd7494..84beb93 100644 --- a/gcc/reorg.c +++ b/gcc/reorg.c @@ -575,8 +575,9 @@ add_to_delay_list (rtx_insn *insn, vec *delay_list) { /* If INSN has its block number recorded, clear it since we may be moving the insn to a new block. */ - clear_hashed_info_for_insn (insn); - delay_list->safe_push (insn); + clear_hashed_info_for_insn (insn); + + delay_list->safe_push (insn); } /* Delete INSN from the delay slot of the insn that it is in, which may @@ -3211,7 +3212,14 @@ relax_delay_slots (rtx_insn *first) if (invert_jump (jump_insn, label, 1)) { - delete_related_insns (next); + rtx_insn *from = delete_related_insns (next); + + /* We have just removed a BARRIER, which means that the block + number of the next insns has effectively been changed (see + find_basic_block in resource.c), so clear it. */ + if (from) + clear_hashed_info_until_next_barrier (from); + next = jump_insn; } @@ -3484,18 +3492,22 @@ relax_delay_slots (rtx_insn *first) if (invert_jump (delay_jump_insn, label, 1)) { - int i; - /* Must update the INSN_FROM_TARGET_P bits now that the branch is reversed, so that mark_target_live_regs will handle the delay slot insn correctly. */ - for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) + for (int i = 1; i < XVECLEN (PATTERN (insn), 0); i++) { rtx slot = XVECEXP (PATTERN (insn), 0, i); INSN_FROM_TARGET_P (slot) = ! INSN_FROM_TARGET_P (slot); } - delete_related_insns (next); + /* We have just removed a BARRIER, which means that the block + number of the next insns has effectively been changed (see + find_basic_block in resource.c), so clear it. */ + rtx_insn *from = delete_related_insns (next); + if (from) + clear_hashed_info_until_next_barrier (from); + next = insn; } diff --git a/gcc/resource.c b/gcc/resource.c index d26217c..32faa73 100644 --- a/gcc/resource.c +++ b/gcc/resource.c @@ -1282,7 +1282,26 @@ clear_hashed_info_for_insn (rtx_insn *insn) tinfo->block = -1; } } - + +/* Clear any hashed information that we have stored for instructions + between INSN and the next BARRIER that follow a JUMP or a LABEL. */ + +void +clear_hashed_info_until_next_barrier (rtx_insn *insn) +{ + while (insn && !BARRIER_P (insn)) + { + if (JUMP_P (insn) || LABEL_P (insn)) + { + rtx_insn *next = next_active_insn (insn); + if (next) + clear_hashed_info_for_insn (next); + } + + insn = next_nonnote_insn (insn); + } +} + /* Increment the tick count for the basic block that contains INSN. */ void diff --git a/gcc/resource.h b/gcc/resource.h index e3edb24..c4f8aa2 100644 --- a/gcc/resource.h +++ b/gcc/resource.h @@ -46,6 +46,7 @@ extern void mark_set_resources (rtx, struct resources *, int, enum mark_resource_type); extern void mark_referenced_resources (rtx, struct resources *, bool); extern void clear_hashed_info_for_insn (rtx_insn *); +extern void clear_hashed_info_until_next_barrier (rtx_insn *); extern void incr_ticks_for_insn (rtx_insn *); extern void mark_end_of_function_resources (rtx, bool); extern void init_resource_info (rtx_insn *); -- cgit v1.1 From dbf3dc75888623e9d4bb7cc5e9c30caa9b24ffe7 Mon Sep 17 00:00:00 2001 From: Bu Le Date: Thu, 12 Mar 2020 22:39:12 +0000 Subject: aarch64: Add --params to control the number of recip steps [PR94154] -mlow-precision-div hard-coded the number of iterations to 2 for double and 1 for float. This patch adds a --param to control the number. 2020-03-13 Bu Le gcc/ PR target/94154 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=) (-param=aarch64-double-recp-precision=): New options. * doc/invoke.texi: Document them. * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them instead of hard-coding the choice of 1 for float and 2 for double. --- gcc/ChangeLog | 9 +++++++++ gcc/config/aarch64/aarch64.c | 8 +++++--- gcc/config/aarch64/aarch64.opt | 9 +++++++++ gcc/doc/invoke.texi | 11 +++++++++++ 4 files changed, 34 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6198289..ac8940a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-13 Bu Le + + PR target/94154 + * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=) + (-param=aarch64-double-recp-precision=): New options. + * doc/invoke.texi: Document them. + * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them + instead of hard-coding the choice of 1 for float and 2 for double. + 2019-03-13 Eric Botcazou PR rtl-optimization/94119 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c320d5ba..2c81f86 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -12911,10 +12911,12 @@ aarch64_emit_approx_div (rtx quo, rtx num, rtx den) /* Iterate over the series twice for SF and thrice for DF. */ int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2; - /* Optionally iterate over the series once less for faster performance, - while sacrificing the accuracy. */ + /* Optionally iterate over the series less for faster performance, + while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */ if (flag_mlow_precision_div) - iterations--; + iterations = (GET_MODE_INNER (mode) == DFmode + ? aarch64_double_recp_precision + : aarch64_float_recp_precision); /* Iterate over the series to calculate the approximate reciprocal. */ rtx xtmp = gen_reg_rtx (mode); diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 77df0b7..37181b5 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -262,3 +262,12 @@ Generate local calls to out-of-line atomic operations. -param=aarch64-sve-compare-costs= Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization. + +-param=aarch64-float-recp-precision= +Target Joined UInteger Var(aarch64_float_recp_precision) Init(1) IntegerRange(1, 5) Param +The number of Newton iterations for calculating the reciprocal for float type. The precision of division is proportional to this param when division approximation is enabled. The default value is 1. + +-param=aarch64-double-recp-precision= +Target Joined UInteger Var(aarch64_double_recp_precision) Init(2) IntegerRange(1, 5) Param +The number of Newton iterations for calculating the reciprocal for double type. The precision of division is proportional to this param when division approximation is enabled. The default value is 2. + diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index af28015..96a9516 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13179,6 +13179,17 @@ Also use the cost model to choose between SVE and Advanced SIMD vectorization. Using unpacked vectors includes storing smaller elements in larger containers and accessing elements with extending loads and truncating stores. + +@item aarch64-float-recp-precision +The number of Newton iterations for calculating the reciprocal for float type. +The precision of division is proportional to this param when division +approximation is enabled. The default value is 1. + +@item aarch64-double-recp-precision +The number of Newton iterations for calculating the reciprocal for double type. +The precision of division is propotional to this param when division +approximation is enabled. The default value is 2. + @end table @end table -- cgit v1.1 From fd8679974b2ded884ffd7d912efef7fe13e4ff4f Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Fri, 13 Mar 2020 02:48:59 -0700 Subject: i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV There is no need to set mode attribute to XImode nor V8DFmode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. gcc/ PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF. * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256, TARGET_AVX512VL and ext_sse_reg_operand check. gcc/testsuite/ PR target/89229 * gcc.target/i386/pr89229-4a.c: New test. * gcc.target/i386/pr89229-4b.c: Likewise. * gcc.target/i386/pr89229-4c.c: Likewise. --- gcc/ChangeLog | 8 ++++++ gcc/config/i386/i386.c | 6 ++++ gcc/config/i386/i386.md | 44 ++---------------------------- gcc/testsuite/ChangeLog | 7 +++++ gcc/testsuite/gcc.target/i386/pr89229-4a.c | 16 +++++++++++ gcc/testsuite/gcc.target/i386/pr89229-4b.c | 7 +++++ gcc/testsuite/gcc.target/i386/pr89229-4c.c | 6 ++++ 7 files changed, 53 insertions(+), 41 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4c.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ac8940a..25abfcf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-13 H.J. Lu + + PR target/89229 + * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF. + * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov + for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256, + TARGET_AVX512VL and ext_sse_reg_operand check. + 2020-03-13 Bu Le PR target/94154 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 6d83855..924f955 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5127,6 +5127,12 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands) else return "%vmovq\t{%1, %0|%0, %1}"; + case MODE_DF: + if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) + return "vmovsd\t{%d1, %0|%0, %d1}"; + else + return "%vmovsd\t{%1, %0|%0, %1}"; + case MODE_V1DF: gcc_assert (!TARGET_AVX); return "movlpd\t{%1, %0|%0, %1}"; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 8b5ae34..0f57f939 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3355,37 +3355,7 @@ return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_DF: - if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) - return "vmovsd\t{%d1, %0|%0, %d1}"; - return "%vmovsd\t{%1, %0|%0, %1}"; - - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - case MODE_V8DF: - return "vmovapd\t{%g1, %g0|%g0, %g1}"; - case MODE_V2DF: - return "%vmovapd\t{%1, %0|%0, %1}"; - - case MODE_V2SF: - gcc_assert (!TARGET_AVX); - return "movlps\t{%1, %0|%0, %1}"; - case MODE_V1DF: - gcc_assert (!TARGET_AVX); - return "movlpd\t{%1, %0|%0, %1}"; - - case MODE_DI: - /* Handle broken assemblers that require movd instead of movq. */ - if (!HAVE_AS_IX86_INTERUNIT_MOVQ - && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) - return "%vmovd\t{%1, %0|%0, %1}"; - return "%vmovq\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); default: gcc_unreachable (); @@ -3439,10 +3409,7 @@ /* xorps is one byte shorter for non-AVX targets. */ (eq_attr "alternative" "12,16") - (cond [(and (match_test "TARGET_AVX512F") - (not (match_test "TARGET_PREFER_AVX256"))) - (const_string "XI") - (match_test "TARGET_AVX") + (cond [(match_test "TARGET_AVX") (const_string "V2DF") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) @@ -3458,12 +3425,7 @@ /* movaps is one byte shorter for non-AVX targets. */ (eq_attr "alternative" "13,17") - (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256")) - (not (match_test "TARGET_AVX512VL"))) - (ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand"))) - (const_string "V8DF") - (match_test "TARGET_AVX") + (cond [(match_test "TARGET_AVX") (const_string "DF") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e695b9b..5060981 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-13 H.J. Lu + + PR target/89229 + * gcc.target/i386/pr89229-4a.c: New test. + * gcc.target/i386/pr89229-4b.c: Likewise. + * gcc.target/i386/pr89229-4c.c: Likewise. + 2019-03-13 Eric Botcazou * gcc.c-torture/compile/20200313-1.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr89229-4a.c b/gcc/testsuite/gcc.target/i386/pr89229-4a.c new file mode 100644 index 0000000..5bc10d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-4a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern double d; + +void +foo1 (double x) +{ + register double xmm16 __asm ("xmm16") = x; + asm volatile ("" : "+v" (xmm16)); + register double xmm17 __asm ("xmm17") = xmm16; + asm volatile ("" : "+v" (xmm17)); + d = xmm17; +} + +/* { dg-final { scan-assembler-not "vmovapd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-4b.c b/gcc/testsuite/gcc.target/i386/pr89229-4b.c new file mode 100644 index 0000000..228aeb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-4b.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */ + +#include "pr89229-4a.c" + +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ +/* { dg-final { scan-assembler-not "vmovapd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-4c.c b/gcc/testsuite/gcc.target/i386/pr89229-4c.c new file mode 100644 index 0000000..537c82f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-4c.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ + +#include "pr89229-4a.c" + +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ -- cgit v1.1 From 7aa605c9d4643dc6e0a0460e5697c02457cd7278 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 13 Mar 2020 11:33:16 +0100 Subject: aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] > I'm getting this ICE with -mabi=ilp32: > > during RTL pass: fwprop1 > /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c: In function 'bar': > /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c:16:1: internal compiler error: in decompose, at rtl.h:2279 That is a preexisting issue, caused by another bug in the same function. When mode is SImode and moffset is 0x80000000 (or anything else with the bit 31 set), we need to sign-extend it. 2020-03-13 Jakub Jelinek PR target/94121 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode instead of GEN_INT. --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64.c | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 25abfcf..448c1e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Jakub Jelinek + + PR target/94121 + * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode + instead of GEN_INT. + 2020-03-13 H.J. Lu PR target/89229 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 2c81f86..b0cbb6e2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3757,7 +3757,8 @@ aarch64_add_offset_1 (scalar_int_mode mode, rtx dest, if (emit_move_imm) { gcc_assert (temp1 != NULL_RTX || can_create_pseudo_p ()); - temp1 = aarch64_force_temporary (mode, temp1, GEN_INT (moffset)); + temp1 = aarch64_force_temporary (mode, temp1, + gen_int_mode (moffset, mode)); } insn = emit_insn (offset < 0 ? gen_sub3_insn (dest, src, temp1) -- cgit v1.1 From 43d513af3f2026420312cc709dd729c81862de0c Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Fri, 13 Mar 2020 05:51:21 -0500 Subject: [testsuite] Fix PR93935 to guard case under vect_hw_misalign This patch is to apply the same fix as r267528 to another similar case bb-slp-over-widen-2.c which requires misaligned vector access. gcc/testsuite/ChangeLog PR testsuite/93935 * gcc.dg/vect/bb-slp-over-widen-2.c: Expect basic block vectorized messages only on vect_hw_misalign targets. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5060981..4c6d7ed 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Kewen Lin + + PR testsuite/93935 + * gcc.dg/vect/bb-slp-over-widen-2.c: Expect basic block vectorized + messages only on vect_hw_misalign targets. + 2020-03-13 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c b/gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c index 3750fb7..042b7e9 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c @@ -63,4 +63,4 @@ main (void) /* { dg-final { scan-tree-dump "demoting int to signed short" "slp2" { target { ! vect_widen_shift } } } } */ /* { dg-final { scan-tree-dump "demoting int to unsigned short" "slp2" { target { ! vect_widen_shift } } } } */ /* { dg-final { scan-tree-dump {\.AVG_FLOOR} "slp2" { target vect_avg_qi } } } */ -/* { dg-final { scan-tree-dump-times "basic block vectorized" 2 "slp2" } } */ +/* { dg-final { scan-tree-dump-times "basic block vectorized" 2 "slp2" { target vect_hw_misalign } } } */ -- cgit v1.1 From 98ff89d1ac5872f29020fe5b5edfdf5abce59014 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 13 Mar 2020 13:50:01 +0100 Subject: Do not strcat to result of getenv. PR lto/94157 * lto-wrapper.c (run_gcc): Use concat for appending to collect_gcc_options. PR lto/94157 * gcc.dg/lto/pr94157_0.c: New test. --- gcc/ChangeLog | 6 ++++++ gcc/lto-wrapper.c | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/lto/pr94157_0.c | 6 ++++++ 4 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/lto/pr94157_0.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 448c1e1..679296f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Martin Liska + + PR lto/94157 + * lto-wrapper.c (run_gcc): Use concat for appending + to collect_gcc_options. + 2020-03-13 Jakub Jelinek PR target/94121 diff --git a/gcc/lto-wrapper.c b/gcc/lto-wrapper.c index b8a35c8..46a88b2 100644 --- a/gcc/lto-wrapper.c +++ b/gcc/lto-wrapper.c @@ -1317,7 +1317,8 @@ run_gcc (unsigned argc, char *argv[]) char *xassembler_opts_string = XOBFINISH (&temporary_obstack, char *); - strcat (collect_gcc_options, xassembler_opts_string); + collect_gcc_options = concat (collect_gcc_options, xassembler_opts_string, + NULL); } get_options_from_collect_gcc_options (collect_gcc, collect_gcc_options, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4c6d7ed..6e2099b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-13 Martin Liska + + PR lto/94157 + * gcc.dg/lto/pr94157_0.c: New test. + 2020-03-13 Kewen Lin PR testsuite/93935 diff --git a/gcc/testsuite/gcc.dg/lto/pr94157_0.c b/gcc/testsuite/gcc.dg/lto/pr94157_0.c new file mode 100644 index 0000000..3bca677 --- /dev/null +++ b/gcc/testsuite/gcc.dg/lto/pr94157_0.c @@ -0,0 +1,6 @@ +/* { dg-lto-do link } */ +/* { dg-lto-options { { -O0 -fipa-vrp -flto -Wa,--noexecstack -Wa,--noexecstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack } } } */ + +int main() { + +} -- cgit v1.1 From 3604480a6fe493c51d6ebd53d9b1abeebbbb828f Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 13 Mar 2020 13:56:26 +0100 Subject: tree-optimization/94163 constrain alignment set by PRE This avoids HWI -> unsigned truncation to end up with zero alignment which set_ptr_info_alignment ICEs on. 2020-03-13 Richard Biener PR tree-optimization/94163 * tree-ssa-pre.c (create_expression_by_pieces): Check whether alignment would be zero. --- gcc/ChangeLog | 6 ++++++ gcc/tree-ssa-pre.c | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 679296f..18745fb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Richard Biener + + PR tree-optimization/94163 + * tree-ssa-pre.c (create_expression_by_pieces): Check + whether alignment would be zero. + 2020-03-13 Martin Liska PR lto/94157 diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c index 29987d8..0c1654f 100644 --- a/gcc/tree-ssa-pre.c +++ b/gcc/tree-ssa-pre.c @@ -2815,7 +2815,8 @@ create_expression_by_pieces (basic_block block, pre_expr expr, unsigned HOST_WIDE_INT hmisalign = args.length () == 3 ? tree_to_uhwi (args[2]) : 0; if ((halign & (halign - 1)) == 0 - && (hmisalign & ~(halign - 1)) == 0) + && (hmisalign & ~(halign - 1)) == 0 + && (unsigned int)halign != 0) set_ptr_info_alignment (get_ptr_info (forcedname), halign, hmisalign); } -- cgit v1.1 From 80a13af724aedfb360893dcc16aa7cc12ca49799 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Thu, 12 Mar 2020 14:38:42 -0400 Subject: c++: Redundant -Wdeprecated-declarations warning in build_over_call [PR67960] In build_over_call, we are emitting a redundant -Wdeprecated-declarations warning about the deprecated callee function, first from mark_used and again from build_addr_func <- decay_conversion <- cp_build_addr_expr <- mark_used. It seems this second deprecation warning coming from build_addr_func will always be redundant, so we can safely use a warning_sentinel to disable it before calling build_addr_func. (And any deprecation warning that could come from build_addr_func would be for FN, so we wouldn't be suppressing too much.) gcc/cp/ChangeLog: PR c++/67960 * call.c (build_over_call): Use a warning_sentinel to disable warn_deprecated_decl before calling build_addr_func. gcc/testsuite/ChangeLog: PR c++/67960 * g++.dg/diagnostic/pr67960.C: New test. * g++.dg/diagnostic/pr67960-2.C: New test. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/call.c | 5 +++++ gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/g++.dg/diagnostic/pr67960-2.C | 13 +++++++++++++ gcc/testsuite/g++.dg/diagnostic/pr67960.C | 13 +++++++++++++ 5 files changed, 43 insertions(+) create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960-2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b94e3bb..eea795d 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Patrick Palka + + PR c++/67960 + * call.c (build_over_call): Use a warning_sentinel to disable + warn_deprecated_decl before calling build_addr_func. + 2020-03-12 Jakub Jelinek PR c++/94124 diff --git a/gcc/cp/call.c b/gcc/cp/call.c index 5767a8b..1715acc 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -9062,6 +9062,11 @@ build_over_call (struct z_candidate *cand, int flags, tsubst_flags_t complain) } else { + /* If FN is marked deprecated, then we've already issued a deprecated-use + warning from mark_used above, so avoid redundantly issuing another one + from build_addr_func. */ + warning_sentinel w (warn_deprecated_decl); + fn = build_addr_func (fn, complain); if (fn == error_mark_node) return error_mark_node; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6e2099b..2f738fa 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Patrick Palka + + PR c++/67960 + * g++.dg/diagnostic/pr67960.C: New test. + * g++.dg/diagnostic/pr67960-2.C: New test. + 2020-03-13 Martin Liska PR lto/94157 diff --git a/gcc/testsuite/g++.dg/diagnostic/pr67960-2.C b/gcc/testsuite/g++.dg/diagnostic/pr67960-2.C new file mode 100644 index 0000000..d2ba509 --- /dev/null +++ b/gcc/testsuite/g++.dg/diagnostic/pr67960-2.C @@ -0,0 +1,13 @@ +// PR c++/67960 +// { dg-do compile } +// { dg-additional-options "-Werror -fmax-errors=1" } +__attribute__((deprecated)) void doNothing(){} + +int +main() +{ + doNothing(); // { dg-error "is deprecated" } +} + +// { dg-message "all warnings being treated as errors" "" { target *-*-* } 0 } +// { dg-bogus "compilation terminated" "" { target *-*-* } 0 } diff --git a/gcc/testsuite/g++.dg/diagnostic/pr67960.C b/gcc/testsuite/g++.dg/diagnostic/pr67960.C new file mode 100644 index 0000000..d7b1a2d0 --- /dev/null +++ b/gcc/testsuite/g++.dg/diagnostic/pr67960.C @@ -0,0 +1,13 @@ +// PR c++/67960 +// { dg-do compile { target c++14 } } +// { dg-additional-options "-Werror -fmax-errors=1" } +[[deprecated]] void doNothing(){} + +int +main() +{ + doNothing(); // { dg-error "is deprecated" } +} + +// { dg-message "all warnings being treated as errors" "" { target *-*-* } 0 } +// { dg-bogus "compilation terminated" "" { target *-*-* } 0 } -- cgit v1.1 From 5c7e6d4bdf879b437b43037e10453275acabf521 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Thu, 12 Mar 2020 07:12:50 +0000 Subject: df: Don't abuse bb->aux (PR94148, PR94042) The df dataflow solvers use the aux field in the basic_block struct, although that is reserved for any use by passes. And not only that, it is required that you set all such fields to NULL before calling the solvers, or you quietly get wrong results. This changes the solvers to use a local array for last_change_age instead, just like it already had a local array for last_visit_age. PR rtl-optimization/94148 PR rtl-optimization/94042 * df-core.c (BB_LAST_CHANGE_AGE): Delete. (df_worklist_propagate_forward): New parameter last_change_age, use that instead of bb->aux. (df_worklist_propagate_backward): Ditto. (df_worklist_dataflow_doublequeue): Use a local array last_change_age. --- gcc/ChangeLog | 10 ++++++++++ gcc/df-core.c | 35 ++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 18745fb..3f4eb1a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2020-03-13 Segher Boessenkool + + PR rtl-optimization/94148 + PR rtl-optimization/94042 + * df-core.c (BB_LAST_CHANGE_AGE): Delete. + (df_worklist_propagate_forward): New parameter last_change_age, use + that instead of bb->aux. + (df_worklist_propagate_backward): Ditto. + (df_worklist_dataflow_doublequeue): Use a local array last_change_age. + 2020-03-13 Richard Biener PR tree-optimization/94163 diff --git a/gcc/df-core.c b/gcc/df-core.c index 346849e..9875a26 100644 --- a/gcc/df-core.c +++ b/gcc/df-core.c @@ -871,9 +871,6 @@ make_pass_df_finish (gcc::context *ctxt) The general data flow analysis engine. ----------------------------------------------------------------------------*/ -/* Return time BB when it was visited for last time. */ -#define BB_LAST_CHANGE_AGE(bb) ((ptrdiff_t)(bb)->aux) - /* Helper function for df_worklist_dataflow. Propagate the dataflow forward. Given a BB_INDEX, do the dataflow propagation @@ -897,7 +894,8 @@ df_worklist_propagate_forward (struct dataflow *dataflow, unsigned *bbindex_to_postorder, bitmap pending, sbitmap considered, - ptrdiff_t age) + vec &last_change_age, + int age) { edge e; edge_iterator ei; @@ -908,7 +906,8 @@ df_worklist_propagate_forward (struct dataflow *dataflow, if (EDGE_COUNT (bb->preds) > 0) FOR_EACH_EDGE (e, ei, bb->preds) { - if (age <= BB_LAST_CHANGE_AGE (e->src) + if (bbindex_to_postorder[e->src->index] < last_change_age.length () + && age <= last_change_age[bbindex_to_postorder[e->src->index]] && bitmap_bit_p (considered, e->src->index)) changed |= dataflow->problem->con_fun_n (e); } @@ -942,7 +941,8 @@ df_worklist_propagate_backward (struct dataflow *dataflow, unsigned *bbindex_to_postorder, bitmap pending, sbitmap considered, - ptrdiff_t age) + vec &last_change_age, + int age) { edge e; edge_iterator ei; @@ -953,7 +953,8 @@ df_worklist_propagate_backward (struct dataflow *dataflow, if (EDGE_COUNT (bb->succs) > 0) FOR_EACH_EDGE (e, ei, bb->succs) { - if (age <= BB_LAST_CHANGE_AGE (e->dest) + if (bbindex_to_postorder[e->dest->index] < last_change_age.length () + && age <= last_change_age[bbindex_to_postorder[e->dest->index]] && bitmap_bit_p (considered, e->dest->index)) changed |= dataflow->problem->con_fun_n (e); } @@ -991,10 +992,10 @@ df_worklist_propagate_backward (struct dataflow *dataflow, worklists (we are processing WORKLIST and storing new BBs to visit in PENDING). - As an optimization we maintain ages when BB was changed (stored in bb->aux) - and when it was last visited (stored in last_visit_age). This avoids need - to re-do confluence function for edges to basic blocks whose source - did not change since destination was visited last time. */ + As an optimization we maintain ages when BB was changed (stored in + last_change_age) and when it was last visited (stored in last_visit_age). + This avoids need to re-do confluence function for edges to basic blocks + whose source did not change since destination was visited last time. */ static void df_worklist_dataflow_doublequeue (struct dataflow *dataflow, @@ -1010,11 +1011,11 @@ df_worklist_dataflow_doublequeue (struct dataflow *dataflow, int age = 0; bool changed; vec last_visit_age = vNULL; + vec last_change_age = vNULL; int prev_age; - basic_block bb; - int i; last_visit_age.safe_grow_cleared (n_blocks); + last_change_age.safe_grow_cleared (n_blocks); /* Double-queueing. Worklist is for the current iteration, and pending is for the next. */ @@ -1032,30 +1033,30 @@ df_worklist_dataflow_doublequeue (struct dataflow *dataflow, bitmap_clear_bit (pending, index); bb_index = blocks_in_postorder[index]; - bb = BASIC_BLOCK_FOR_FN (cfun, bb_index); prev_age = last_visit_age[index]; if (dir == DF_FORWARD) changed = df_worklist_propagate_forward (dataflow, bb_index, bbindex_to_postorder, pending, considered, + last_change_age, prev_age); else changed = df_worklist_propagate_backward (dataflow, bb_index, bbindex_to_postorder, pending, considered, + last_change_age, prev_age); last_visit_age[index] = ++age; if (changed) - bb->aux = (void *)(ptrdiff_t)age; + last_change_age[index] = age; } bitmap_clear (worklist); } - for (i = 0; i < n_blocks; i++) - BASIC_BLOCK_FOR_FN (cfun, blocks_in_postorder[i])->aux = NULL; BITMAP_FREE (worklist); BITMAP_FREE (pending); last_visit_age.release (); + last_change_age.release (); /* Dump statistics. */ if (dump_file) -- cgit v1.1 From 9ae8bc027743d7c2d25f90d6752a1f4e0dc153cf Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Fri, 13 Mar 2020 16:34:32 +0100 Subject: testsuite: Assorted x32 testsuite fixes * gcc.target/i386/pr64409.c: Do not limit compilation to x32 targets. (dg-error): Quote 'ms_abi' attribute. * gcc.target/i386/pr71958.c: Do not limit compilation to x32 targets. Require maybe_x32 effective target. (dg-options): Add -mx32. (dg-error): Quote 'ms_abi' attribute. * gcc.target/i386/pr90096.c (dg-error): Update relative location of target x32 error. --- gcc/testsuite/ChangeLog | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr64409.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr71958.c | 7 ++++--- gcc/testsuite/gcc.target/i386/pr90096.c | 2 +- 4 files changed, 18 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f738fa..e7b8c88 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2020-03-13 Uroš Bizjak + + * gcc.target/i386/pr64409.c: Do not limit compilation to x32 targets. + (dg-error): Quote 'ms_abi' attribute. + * gcc.target/i386/pr71958.c: Do not limit compilation to x32 targets. + Require maybe_x32 effective target. + (dg-options): Add -mx32. + (dg-error): Quote 'ms_abi' attribute. + * gcc.target/i386/pr90096.c (dg-error): Update relative + location of target x32 error. + 2020-03-13 Patrick Palka PR c++/67960 diff --git a/gcc/testsuite/gcc.target/i386/pr64409.c b/gcc/testsuite/gcc.target/i386/pr64409.c index 7bf9d1e..9df9c18 100644 --- a/gcc/testsuite/gcc.target/i386/pr64409.c +++ b/gcc/testsuite/gcc.target/i386/pr64409.c @@ -1,6 +1,6 @@ -/* { dg-do compile { target x32 } } */ +/* { dg-do compile } */ /* { dg-require-effective-target maybe_x32 } */ /* { dg-options "-O0 -mx32" } */ int a; -int* __attribute__ ((ms_abi)) fn1 () { return &a; } /* { dg-error "X32 does not support ms_abi attribute" } */ +int* __attribute__ ((ms_abi)) fn1 () { return &a; } /* { dg-error "X32 does not support 'ms_abi' attribute" } */ diff --git a/gcc/testsuite/gcc.target/i386/pr71958.c b/gcc/testsuite/gcc.target/i386/pr71958.c index 5e60d17..81102fc 100644 --- a/gcc/testsuite/gcc.target/i386/pr71958.c +++ b/gcc/testsuite/gcc.target/i386/pr71958.c @@ -1,6 +1,7 @@ -/* { dg-do compile { target x32 } } */ -/* { dg-options "-mabi=ms" } */ -/* { dg-error "-mabi=ms not supported with X32 ABI" "" { target *-*-* } 0 } */ +/* { dg-do compile } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mx32 -mabi=ms" } */ +/* { dg-error "'-mabi=ms' not supported with X32 ABI" "" { target *-*-* } 0 } */ void main () { diff --git a/gcc/testsuite/gcc.target/i386/pr90096.c b/gcc/testsuite/gcc.target/i386/pr90096.c index fe29e3c..871e0ff 100644 --- a/gcc/testsuite/gcc.target/i386/pr90096.c +++ b/gcc/testsuite/gcc.target/i386/pr90096.c @@ -19,6 +19,6 @@ bar (__m128 *p) { return _mm_cvtt_roundss_u64 (*p, _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC); /* { dg-error "needs isa option -m64 -mavx512f" "" { target lp64 } .-1 } */ - /* { dg-error "needs isa option -mx32 -mavx512f" "" { target x32 } .-1 } */ + /* { dg-error "needs isa option -mx32 -mavx512f" "" { target x32 } .-2 } */ } #endif -- cgit v1.1 From f2e9fe5f97d88fc876c44e6ffa57a2e85150adf9 Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Fri, 13 Mar 2020 10:28:26 -0600 Subject: PR c/94040 - ICE on a call to an invalid redeclaration of strftime gcc/c/ChangeLog: PR c/94040 * c-decl.c (builtin_structptr_type_count): New constant. (match_builtin_function_types): Reject decls that are incompatible in types pointed to by pointers. (diagnose_mismatched_decls): Adjust comments. gcc/testsuite/ChangeLog: PR c/94040 * gcc.dg/Wbuiltin-declaration-mismatch-12.c: Relax test to look for warning name rather than the exact text. * gcc.dg/Wbuiltin-declaration-mismatch-14.c: New test. * gcc.dg/Wbuiltin-declaration-mismatch-15.c: New test. * gcc.dg/pr62090.c: Prune expected warning. * gcc.dg/pr89314.c: Look for warning name rather than text. --- gcc/c/ChangeLog | 8 +++ gcc/c/c-decl.c | 66 ++++++++++++------- gcc/testsuite/ChangeLog | 10 +++ .../gcc.dg/Wbuiltin-declaration-mismatch-12.c | 4 +- .../gcc.dg/Wbuiltin-declaration-mismatch-14.c | 77 ++++++++++++++++++++++ .../gcc.dg/Wbuiltin-declaration-mismatch-15.c | 56 ++++++++++++++++ gcc/testsuite/gcc.dg/pr62090.c | 2 + gcc/testsuite/gcc.dg/pr89314.c | 2 +- 8 files changed, 198 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c (limited to 'gcc') diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 5b8236d..d3a3b2f 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,11 @@ +2020-03-13 Martin Sebor + + PR c/94040 + * c-decl.c (builtin_structptr_type_count): New constant. + (match_builtin_function_types): Reject decls that are incompatible + in types pointed to by pointers. + (diagnose_mismatched_decls): Adjust comments. + 2020-03-05 Joseph Myers PR c/93577 diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c index c819fd0..87a0734 100644 --- a/gcc/c/c-decl.c +++ b/gcc/c/c-decl.c @@ -1641,13 +1641,17 @@ c_bind (location_t loc, tree decl, bool is_global) } -/* Stores the first FILE*, const struct tm* etc. argument type (whatever it - is) seen in a declaration of a file I/O etc. built-in. Subsequent - declarations of such built-ins are expected to refer to it rather than to - fileptr_type_node etc. which is just void* (or to any other type). +/* Stores the first FILE*, const struct tm* etc. argument type (whatever + it is) seen in a declaration of a file I/O etc. built-in, corresponding + to the builtin_structptr_types array. Subsequent declarations of such + built-ins are expected to refer to it rather than to fileptr_type_node, + etc. which is just void* (or to any other type). Used only by match_builtin_function_types. */ -static GTY(()) tree last_structptr_types[6]; +static const unsigned builtin_structptr_type_count + = sizeof builtin_structptr_types / sizeof builtin_structptr_types[0]; + +static GTY(()) tree last_structptr_types[builtin_structptr_type_count]; /* Returns true if types T1 and T2 representing return types or types of function arguments are close enough to be considered interchangeable @@ -1692,10 +1696,13 @@ match_builtin_function_types (tree newtype, tree oldtype, tree newargs = TYPE_ARG_TYPES (newtype); tree tryargs = newargs; - gcc_checking_assert ((sizeof (last_structptr_types) - / sizeof (last_structptr_types[0])) - == (sizeof (builtin_structptr_types) - / sizeof (builtin_structptr_types[0]))); + const unsigned nlst + = sizeof last_structptr_types / sizeof last_structptr_types[0]; + const unsigned nbst + = sizeof builtin_structptr_types / sizeof builtin_structptr_types[0]; + + gcc_checking_assert (nlst == nbst); + for (unsigned i = 1; oldargs || newargs; ++i) { if (!oldargs @@ -1710,11 +1717,12 @@ match_builtin_function_types (tree newtype, tree oldtype, if (!types_close_enough_to_match (oldtype, newtype)) return NULL_TREE; - unsigned j = (sizeof (builtin_structptr_types) - / sizeof (builtin_structptr_types[0])); + unsigned j = nbst; if (POINTER_TYPE_P (oldtype)) - for (j = 0; j < (sizeof (builtin_structptr_types) - / sizeof (builtin_structptr_types[0])); ++j) + /* Iterate over well-known struct types like FILE (whose types + aren't known to us) and compare the pointer to each to + the pointer argument. */ + for (j = 0; j < nbst; ++j) { if (TREE_VALUE (oldargs) != builtin_structptr_types[j].node) continue; @@ -1734,13 +1742,26 @@ match_builtin_function_types (tree newtype, tree oldtype, last_structptr_types[j] = newtype; break; } - if (j == (sizeof (builtin_structptr_types) - / sizeof (builtin_structptr_types[0])) - && !*strict - && !comptypes (oldtype, newtype)) + + if (j == nbst && !comptypes (oldtype, newtype)) { - *argno = i; - *strict = oldtype; + if (POINTER_TYPE_P (oldtype)) + { + /* For incompatible pointers, only reject differences in + the unqualified variants of the referenced types but + consider differences in qualifiers as benign (report + those to caller via *STRICT below). */ + tree oldref = TYPE_MAIN_VARIANT (TREE_TYPE (oldtype)); + tree newref = TYPE_MAIN_VARIANT (TREE_TYPE (newtype)); + if (!comptypes (oldref, newref)) + return NULL_TREE; + } + + if (!*strict) + { + *argno = i; + *strict = oldtype; + } } oldargs = TREE_CHAIN (oldargs); @@ -1965,9 +1986,8 @@ diagnose_mismatched_decls (tree newdecl, tree olddecl, { /* Accept "harmless" mismatches in function types such as missing qualifiers or int vs long when they're the same - size. However, with -Wextra in effect, diagnose return and - argument types that are incompatible according to language - rules. */ + size. However, diagnose return and argument types that are + incompatible according to language rules. */ tree mismatch_expect; unsigned mismatch_argno; @@ -2002,8 +2022,6 @@ diagnose_mismatched_decls (tree newdecl, tree olddecl, if (mismatch_expect && extra_warnings) { - /* If types match only loosely, print a warning but accept - the redeclaration. */ location_t newloc = DECL_SOURCE_LOCATION (newdecl); bool warned = false; if (mismatch_argno) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e7b8c88..a379b40 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2020-03-13 Martin Sebor + + PR c/94040 + * gcc.dg/Wbuiltin-declaration-mismatch-12.c: Relax test to look + for warning name rather than the exact text. + * gcc.dg/Wbuiltin-declaration-mismatch-14.c: New test. + * gcc.dg/Wbuiltin-declaration-mismatch-15.c: New test. + * gcc.dg/pr62090.c: Prune expected warning. + * gcc.dg/pr89314.c: Look for warning name rather than text. + 2020-03-13 Uroš Bizjak * gcc.target/i386/pr64409.c: Do not limit compilation to x32 targets. diff --git a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-12.c b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-12.c index 6bf9762..f12ef6a 100644 --- a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-12.c +++ b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-12.c @@ -3,6 +3,6 @@ { dg-do compile } { dg-options "-Wbuiltin-declaration-mismatch -Wextra" } */ -extern void __clear_cache (char*, char*); /* { dg-warning "mismatch in argument 1 type of built-in function .__clear_cache.; expected .void \\\*." } */ +extern void __clear_cache (char*, char*); // { dg-warning "\\\[-Wbuiltin-declaration-mismatch" } -void __builtin_prefetch (const char *, ...); /* { dg-warning "mismatch in argument 1 type of built-in function .__builtin_prefetch.; expected .const void \\\*." } */ +void __builtin_prefetch (const char *, ...); // { dg-warning "\\\[-Wbuiltin-declaration-mismatch" } diff --git a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c new file mode 100644 index 0000000..cc536d7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c @@ -0,0 +1,77 @@ +/* PR c/94040 - ICE on a call to an invalid redeclaration of strftime + { dg-do compile } + { dg-options "-Wall" } */ + +typedef __SIZE_TYPE__ size_t; + +struct tm; + +size_t strftime (char *, size_t, int *, struct tm *); // { dg-warning "-Wbuiltin-declaration-mismatch" } + +size_t call_strftime (char *d, size_t n, int *f, struct tm *t) +{ + size_t r = 0; + r += strftime (0, 0, 0, 0); + r += strftime (d, 0, 0, 0); + r += strftime (d, n, 0, 0); + r += strftime (d, n, f, 0); + r += strftime (d, n, f, t); + return r; +} + + +char* strchr (char*, char*); // { dg-warning "-Wbuiltin-declaration-mismatch" } + +// Verify that missing/extra qualifiers aren't diagnosed without -Wextra. + +int strcmp (char*, char*); +int strncmp (volatile char*, volatile char*, size_t); + +// Verify that a difference in pointers is diagnosed. + +size_t strlen (const char**); +// { dg-warning "-Wbuiltin-declaration-mismatch" "pointer" { target *-*-* } .-1 } + + size_t strnlen (const char* const*, size_t); +// { dg-warning "-Wbuiltin-declaration-mismatch" "pointer" { target *-*-* } .-1 } + + +// Verify that calls to the compatibly-redeclared built-ins are treated +// as those to the built-ins and diagnosed. + +int test_builtin_calls (size_t n) +{ + int r = 0; + r += strcmp ((char*)0, ""); // { dg-warning "\\\[-Wnonnull]" } + r += strcmp ("", (char*)0); // { dg-warning "\\\[-Wnonnull]" } + + r += strncmp ((char*)0, "", n); // { dg-warning "\\\[-Wnonnull]" } + r += strncmp ("", (char*)0, n); // { dg-warning "\\\[-Wnonnull]" } + + return r; +} + + +// Verify that calls to the incompatibly-redeclared built-ins are not +// treated as those to the built-ins by the middle-end. It doesn't +// matter if the front-end diagnoses them but the middle-end should +// not because it shouldn't recognize them as built-ins. + +#pragma GCC optimize "2" + +size_t test_nonbuiltin_calls (char *s, int c) +{ + void *null = 0; + + char *r; + r = strchr ((char*)null, s); + r = strchr (r, (char*)null); + *s = *r; // use the result + + size_t n = 0; + n += strftime (0, 0, 0, 0); + n += strlen ((const char**)null); + n += strnlen ((const char**)null, n); + + return n; +} diff --git a/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c new file mode 100644 index 0000000..3c32a5f --- /dev/null +++ b/gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c @@ -0,0 +1,56 @@ +/* PR c/94040 - ICE on a call to an invalid redeclaration of strftime + { dg-do compile } + { dg-options "-Wall -Wextra" } */ + +typedef __SIZE_TYPE__ size_t; + +struct tm; + +size_t strftime (const char *, size_t, char *, struct tm *); +// { dg-warning "-Wbuiltin-declaration-mismatch" "arg 1" { target *-*-* } .-1 } + +// Verify that missing/extra qualifiers are diagnosed with -Wextra. + +int strcmp (char*, const char*); +// { dg-warning "-Wbuiltin-declaration-mismatch" "arg 1" { target *-*-* } .-1 } + +int strncmp (const char*, volatile char*, size_t); +// { dg-warning "-Wbuiltin-declaration-mismatch" "arg 2" { target *-*-* } .-1 } + +size_t strlen (char*); +// { dg-warning "-Wbuiltin-declaration-mismatch" "arg 1" { target *-*-* } .-1 } + + +// Verify that calls to built-ins declared with missing/extra qualifiers +// are still treated as those to built-ins by the front-end. + +int test_builtin_calls_fe (size_t n) +{ + int r = 0; + r += strcmp ((char*)0, ""); // { dg-warning "\\\[-Wnonnull]" } + r += strcmp ("", (char*)0); // { dg-warning "\\\[-Wnonnull]" } + + r += strncmp ((char*)0, "", n); // { dg-warning "\\\[-Wnonnull]" } + r += strncmp ("", (char*)0, n); // { dg-warning "\\\[-Wnonnull]" } + + r += strlen ((char*)0); // { dg-warning "\\\[-Wnonnull]" } + return r; +} + + +// Ditto but by the middle-end. + +#pragma GCC optimize "2" + +int test_builtin_calls_me (void) +{ + char *null1 = 0; + char *null2 = null1; + char *null3 = null2; + + int r = 0; + r += strcmp (null1, "123"); // { dg-warning "\\\[-Wnonnull]" } + r += strncmp ("2345", null2, 4); // { dg-warning "\\\[-Wnonnull]" } + r += strlen (null3); // { dg-warning "\\\[-Wnonnull]" } + return r; +} diff --git a/gcc/testsuite/gcc.dg/pr62090.c b/gcc/testsuite/gcc.dg/pr62090.c index 53089cf..42f1345 100644 --- a/gcc/testsuite/gcc.dg/pr62090.c +++ b/gcc/testsuite/gcc.dg/pr62090.c @@ -15,3 +15,5 @@ log_bad_request () { b += sprintf (0, "foo"); } + +/* { dg-prune-output "\\\[-Wbuiltin-declaration-mismatch]" } */ diff --git a/gcc/testsuite/gcc.dg/pr89314.c b/gcc/testsuite/gcc.dg/pr89314.c index e35dd8c..27b3a51 100644 --- a/gcc/testsuite/gcc.dg/pr89314.c +++ b/gcc/testsuite/gcc.dg/pr89314.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Wbuiltin-declaration-mismatch -Wextra" } */ -extern __SIZE_TYPE__ strlen (const float *); /* { dg-warning "mismatch in argument 1 type of built-in function" } */ +extern __SIZE_TYPE__ strlen (const float *); /* { dg-warning "\\\[-Wbuiltin-declaration-mismatch" } */ void bar (void); void -- cgit v1.1 From 3b515f748412bbfc10c46cfa467ece89a25c04c5 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Fri, 13 Mar 2020 18:02:40 +0100 Subject: Fix wrong year in ChangeLog. --- gcc/ChangeLog | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3f4eb1a..d63b831 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -43,7 +43,7 @@ * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them instead of hard-coding the choice of 1 for float and 2 for double. -2019-03-13 Eric Botcazou +2020-03-13 Eric Botcazou PR rtl-optimization/94119 * resource.h (clear_hashed_info_until_next_barrier): Declare. @@ -52,7 +52,7 @@ (relax_delay_slots): Call clear_hashed_info_until_next_barrier on the next instruction after removing a BARRIER. -2019-03-13 Eric Botcazou +2020-03-13 Eric Botcazou PR middle-end/92071 * expmed.c (store_integral_bit_field): For fields larger than a word, -- cgit v1.1 From 45ee7a35f347e59f003d65bce0d43d5123d827cf Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Fri, 13 Mar 2020 12:29:33 -0600 Subject: PR c/94040 - ICE on a call to an invalid redeclaration of strftime gcc/testsuite/ChangeLog: * gcc.dg/torture/pr54261-1.c: Correct built-in declartion. --- gcc/testsuite/ChangeLog | 1 + gcc/testsuite/gcc.dg/torture/pr54261-1.c | 14 +++++++------- 2 files changed, 8 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a379b40..e3d1fc3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -7,6 +7,7 @@ * gcc.dg/Wbuiltin-declaration-mismatch-15.c: New test. * gcc.dg/pr62090.c: Prune expected warning. * gcc.dg/pr89314.c: Look for warning name rather than text. + * gcc.dg/torture/pr54261-1.c: Correct built-in declartion. 2020-03-13 Uroš Bizjak diff --git a/gcc/testsuite/gcc.dg/torture/pr54261-1.c b/gcc/testsuite/gcc.dg/torture/pr54261-1.c index 071b323..7286124 100644 --- a/gcc/testsuite/gcc.dg/torture/pr54261-1.c +++ b/gcc/testsuite/gcc.dg/torture/pr54261-1.c @@ -8,23 +8,23 @@ a PASS. Where the bug trigs (at the time this test-case was added), cas_int is also false but the fallback isn't used. */ __attribute__((__noinline__, __noclone__)) -int +unsigned # if __INT_MAX__ == 0x7fff __sync_fetch_and_add_2 # else __sync_fetch_and_add_4 # endif - (int *at, int val) + (volatile void *at, unsigned val) { - int tmp = *at; + unsigned tmp = *(volatile unsigned*)at; asm (""); - *at = tmp + val; + *(volatile unsigned*)at = tmp + val; return tmp; } #endif __attribute__((__noinline__, __noclone__)) -void g (int *at, int val) +void g (unsigned *at, unsigned val) { asm (""); __sync_fetch_and_add (at, val); @@ -35,8 +35,8 @@ int main(void) /* On PTX it is not valid to perform atomic operations on auto variables, which end up in .local. Making this static places it in .global. */ - static int x = 41; - int a = 1; + static unsigned x = 41; + unsigned a = 1; g (&x, a); if (x != 42) -- cgit v1.1 From a4504f32c056db781a2bdc104dffa1b29684c930 Mon Sep 17 00:00:00 2001 From: "Vladimir N. Makarov" Date: Fri, 13 Mar 2020 14:58:57 -0400 Subject: PR92303: Try to simplify memory subreg. 2020-03-13 Vladimir Makarov PR rtl-optimization/92303 * lra-spills.c (remove_pseudos): Try to simplify memory subreg. --- gcc/ChangeLog | 5 +++++ gcc/lra-spills.c | 11 ++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d63b831..4ea81e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-13 Vladimir Makarov + + PR rtl-optimization/92303 + * lra-spills.c (remove_pseudos): Try to simplify memory subreg. + 2020-03-13 Segher Boessenkool PR rtl-optimization/94148 diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c index 0022611..01256e7 100644 --- a/gcc/lra-spills.c +++ b/gcc/lra-spills.c @@ -421,7 +421,16 @@ remove_pseudos (rtx *loc, rtx_insn *insn) if (*loc == NULL_RTX) return res; code = GET_CODE (*loc); - if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER + if (code == SUBREG && REG_P (SUBREG_REG (*loc))) + { + /* Try to remove memory subregs to simplify LRA job + and avoid LRA cycling in case of subreg memory reload. */ + res = remove_pseudos (&SUBREG_REG (*loc), insn); + if (GET_CODE (SUBREG_REG (*loc)) == MEM) + alter_subreg (loc, false); + return res; + } + else if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER && lra_get_regno_hard_regno (i) < 0 /* We do not want to assign memory for former scratches because it might result in an address reload for some targets. In -- cgit v1.1 From db3fa3476e9e922ca3e283df03ebd14be7220b6e Mon Sep 17 00:00:00 2001 From: Vasee Vinayagamoorthy Date: Fri, 13 Mar 2020 19:43:34 +0000 Subject: testsuite: Fix misquoted string in bfcvt-nosimd.c 2020-03-13 Vasee Vinayagamoorthy gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Fix DejaGnu typo. --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e3d1fc3..296ea8f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-13 Vasee Vinayagamoorthy + + * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Fix DejaGnu + typo. + 2020-03-13 Martin Sebor PR c/94040 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c index c2631a5..05c3058 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c @@ -1,7 +1,7 @@ /* { dg-do assemble { target { aarch64*-*-* } } } */ /* { dg-require-effective-target aarch64_asm_bf16_ok } */ /* { dg-additional-options "-save-temps -march=armv8.2-a+bf16+nosimd" } */ -/* { dg-final { check-function-bodies "**" "" "-O[^0]" } } */ +/* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */ #include -- cgit v1.1 From 5b74dd0a2278365eb562d9d1999c3c11cddb733c Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Fri, 13 Mar 2020 21:03:02 +0100 Subject: d/dmd: Merge upstream dmd e9420cfbf 1. Implement DIP 1010 - (Static foreach) Support for 'static foreach' has been added. 'static foreach' is a conditional compilation construct that is to 'foreach' what 'static if' is to 'if'. It is a convenient way to generate declarations and statements by iteration. import std.conv: to; static foreach(i; 0 .. 10) { // a 'static foreach' body does not introduce a nested scope // (similar to 'static if'). // The following mixin declaration is at module scope: // declares 10 variables x0, x1, ..., x9 mixin('enum x' ~ to!string(i) ~ ' = i;'); } import std.range: iota; // all aggregate types that can be iterated with a standard 'foreach' // loop are also supported by static foreach: static foreach(i; iota(10)) { // we access the declarations generated in the first 'static foreach' pragma(msg, "x", i, ": ", mixin(`x` ~ to!string(i))); static assert(mixin(`x` ~ to!string(i)) == i); } void main() { import std.conv: text; import std.typecons: tuple; import std.algorithm: map; import std.stdio: writeln; // 'static foreach' has both declaration and statement forms // (similar to 'static if'). static foreach(x; iota(3).map!(i => tuple(text("x", i), i))) { // generates three local variables x0, x1 and x2. mixin(text(`int `,x[0],` = x[1];`)); scope(exit) // this is within the scope of 'main' { writeln(mixin(x[0])); } } writeln(x0," ",x1," ",x2); // first runtime output } 2. Aliases can be created directly from a '__trait'. Aliases can be created directly from the traits that return symbol(s) or tuples. This includes 'getMember', 'allMembers', 'derivedMembers', 'parent', 'getOverloads', 'getVirtualFunctions', 'getVirtualMethods', 'getUnitTests', 'getAttributes' and finally 'getAliasThis'. Previously an 'AliasSeq' was necessary in order to alias their return. Now the grammar allows to write shorter declarations: struct Foo { static int a; } alias oldWay = AliasSeq!(__traits(getMember, Foo, "a"))[0]; alias newWay = __traits(getMember, Foo, "a"); To permit this it was more interesting to include '__trait' in the basic types rather than just changing the alias syntax. So additionally, wherever a type appears a '__trait' can be used, for example in a variable declaration: struct Foo { static struct Bar {} } const(__traits(getMember, Foo, "Bar")) fooBar; static assert(is(typeof(fooBar) == const(Foo.Bar))); 3. fix Issue 10100 - Identifiers with double underscores and allMembers The identifer whitelist has been converted into a blacklist of all possible internal D language declarations. Reviewed-on: https://github.com/dlang/dmd/pull/10791 --- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/attrib.c | 189 ++++- gcc/d/dmd/attrib.h | 9 +- gcc/d/dmd/cond.c | 333 +++++++- gcc/d/dmd/cond.h | 5 +- gcc/d/dmd/cppmangle.c | 2 +- gcc/d/dmd/declaration.c | 9 + gcc/d/dmd/dinterpret.c | 4 + gcc/d/dmd/dmangle.c | 1 + gcc/d/dmd/dsymbol.c | 100 ++- gcc/d/dmd/dsymbol.h | 2 + gcc/d/dmd/expression.c | 10 + gcc/d/dmd/expression.h | 2 + gcc/d/dmd/expressionsem.c | 27 +- gcc/d/dmd/func.c | 4 +- gcc/d/dmd/hdrgen.c | 68 +- gcc/d/dmd/init.c | 2 +- gcc/d/dmd/intrange.c | 2 +- gcc/d/dmd/json.c | 4 + gcc/d/dmd/mtype.c | 152 +++- gcc/d/dmd/mtype.h | 18 + gcc/d/dmd/parse.c | 304 +++++--- gcc/d/dmd/parse.h | 3 + gcc/d/dmd/scope.h | 3 +- gcc/d/dmd/statement.c | 120 +++ gcc/d/dmd/statement.h | 9 +- gcc/d/dmd/statementsem.c | 581 ++++++++++---- gcc/d/dmd/traits.c | 34 +- gcc/d/dmd/visitor.h | 4 + gcc/testsuite/gdc.test/compilable/b12001.d | 9 + gcc/testsuite/gdc.test/compilable/json.d | 21 + gcc/testsuite/gdc.test/compilable/staticforeach.d | 842 +++++++++++++++++++++ gcc/testsuite/gdc.test/compilable/test11169.d | 15 + gcc/testsuite/gdc.test/compilable/test17819.d | 17 + gcc/testsuite/gdc.test/compilable/test18871.d | 15 + gcc/testsuite/gdc.test/compilable/test7815.d | 65 ++ gcc/testsuite/gdc.test/compilable/test7886.d | 5 + gcc/testsuite/gdc.test/fail_compilation/e7804_1.d | 11 + gcc/testsuite/gdc.test/fail_compilation/e7804_2.d | 19 + .../gdc.test/fail_compilation/fail11169.d | 28 - .../gdc.test/fail_compilation/fail19182.d | 18 + .../gdc.test/fail_compilation/fail19336.d | 17 + .../gdc.test/fail_compilation/fail19520.d | 21 + gcc/testsuite/gdc.test/fail_compilation/fail2195.d | 18 + gcc/testsuite/gdc.test/fail_compilation/fail7815.d | 65 -- gcc/testsuite/gdc.test/fail_compilation/fail7886.d | 5 - .../gdc.test/fail_compilation/staticforeach1.d | 13 + .../gdc.test/fail_compilation/staticforeach2.d | 13 + .../gdc.test/fail_compilation/staticforeach3.d | 7 + .../gdc.test/fail_compilation/test17307.d | 12 + .../gdc.test/fail_compilation/traits_alone.d | 10 + gcc/testsuite/gdc.test/runnable/arrayop.d | 3 +- gcc/testsuite/gdc.test/runnable/constfold.d | 18 +- gcc/testsuite/gdc.test/runnable/e7804.d | 179 +++++ .../gdc.test/runnable/imports/template13478a.d | 5 +- gcc/testsuite/gdc.test/runnable/staticforeach.d | 45 ++ gcc/testsuite/gdc.test/runnable/test42.d | 60 +- gcc/testsuite/gdc.test/runnable/traits.d | 38 +- 58 files changed, 3108 insertions(+), 489 deletions(-) create mode 100644 gcc/testsuite/gdc.test/compilable/b12001.d create mode 100644 gcc/testsuite/gdc.test/compilable/staticforeach.d create mode 100644 gcc/testsuite/gdc.test/compilable/test17819.d create mode 100644 gcc/testsuite/gdc.test/compilable/test18871.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7815.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_2.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail11169.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19182.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19336.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19520.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail2195.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7815.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/test17307.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/traits_alone.d create mode 100644 gcc/testsuite/gdc.test/runnable/e7804.d create mode 100644 gcc/testsuite/gdc.test/runnable/staticforeach.d (limited to 'gcc') diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index 578f3fc..b017c03 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -b37a537d36c2ac69afa505a3110e2328c9fc0114 +e9420cfbf5cd0cf9e6e398603e009ccc8e14d324 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/attrib.c b/gcc/d/dmd/attrib.c index 6cd715c..86485d2 100644 --- a/gcc/d/dmd/attrib.c +++ b/gcc/d/dmd/attrib.c @@ -31,6 +31,7 @@ bool definitelyValueParameter(Expression *e); Expression *semantic(Expression *e, Scope *sc); StringExp *semanticString(Scope *sc, Expression *exp, const char *s); +Dsymbols *makeTupleForeachStaticDecl(Scope *sc, ForeachStatement *fs, Dsymbols *dbody, bool needExpansion); /********************************* AttribDeclaration ****************************/ @@ -42,6 +43,9 @@ AttribDeclaration::AttribDeclaration(Dsymbols *decl) Dsymbols *AttribDeclaration::include(Scope *, ScopeDsymbol *) { + if (errors) + return NULL; + return decl; } @@ -752,6 +756,7 @@ void AnonDeclaration::semantic(Scope *sc) { ::error(loc, "%s can only be a part of an aggregate, not %s %s", kind(), p->kind(), p->toChars()); + errors = true; return; } @@ -1219,6 +1224,10 @@ bool ConditionalDeclaration::oneMember(Dsymbol **ps, Identifier *ident) Dsymbols *ConditionalDeclaration::include(Scope *sc, ScopeDsymbol *sds) { //printf("ConditionalDeclaration::include(sc = %p) _scope = %p\n", sc, _scope); + + if (errors) + return NULL; + assert(condition); return condition->include(_scope ? _scope : sc, sds) ? decl : elsedecl; } @@ -1275,6 +1284,7 @@ StaticIfDeclaration::StaticIfDeclaration(Condition *condition, //printf("StaticIfDeclaration::StaticIfDeclaration()\n"); scopesym = NULL; addisdone = false; + onStack = false; } Dsymbol *StaticIfDeclaration::syntaxCopy(Dsymbol *s) @@ -1293,12 +1303,17 @@ Dsymbols *StaticIfDeclaration::include(Scope *sc, ScopeDsymbol *) { //printf("StaticIfDeclaration::include(sc = %p) _scope = %p\n", sc, _scope); + if (errors || onStack) + return NULL; + onStack = true; + Dsymbols *d; + if (condition->inc == 0) { assert(scopesym); // addMember is already done assert(_scope); // setScope is already done - Dsymbols *d = ConditionalDeclaration::include(_scope, scopesym); + d = ConditionalDeclaration::include(_scope, scopesym); if (d && !addisdone) { @@ -1318,11 +1333,14 @@ Dsymbols *StaticIfDeclaration::include(Scope *sc, ScopeDsymbol *) addisdone = true; } + onStack = false; return d; } else { - return ConditionalDeclaration::include(sc, scopesym); + d = ConditionalDeclaration::include(sc, scopesym); + onStack = false; + return d; } } @@ -1366,6 +1384,173 @@ const char *StaticIfDeclaration::kind() const return "static if"; } +/***************************** StaticForeachDeclaration ***********************/ + +/* Static foreach at declaration scope, like: + * static foreach (i; [0, 1, 2]){ } + */ + +StaticForeachDeclaration::StaticForeachDeclaration(StaticForeach *sfe, Dsymbols *decl) + : AttribDeclaration(decl) +{ + this->sfe = sfe; + this->scopesym = NULL; + this->onStack = false; + this->cached = false; + this->cache = NULL; +} + +Dsymbol *StaticForeachDeclaration::syntaxCopy(Dsymbol *s) +{ + assert(!s); + return new StaticForeachDeclaration( + sfe->syntaxCopy(), + Dsymbol::arraySyntaxCopy(decl)); +} + +bool StaticForeachDeclaration::oneMember(Dsymbol **ps, Identifier *ident) +{ + // Required to support IFTI on a template that contains a + // `static foreach` declaration. `super.oneMember` calls + // include with a `null` scope. As `static foreach` requires + // the scope for expansion, `oneMember` can only return a + // precise result once `static foreach` has been expanded. + if (cached) + { + return AttribDeclaration::oneMember(ps, ident); + } + *ps = NULL; // a `static foreach` declaration may in general expand to multiple symbols + return false; +} + +Dsymbols *StaticForeachDeclaration::include(Scope *, ScopeDsymbol *) +{ + if (errors || onStack) + return NULL; + if (cached) + { + assert(!onStack); + return cache; + } + onStack = true; + + if (_scope) + { + staticForeachPrepare(sfe, _scope); // lower static foreach aggregate + } + if (!staticForeachReady(sfe)) + { + onStack = false; + return NULL; // TODO: ok? + } + + // expand static foreach + Dsymbols *d = makeTupleForeachStaticDecl(_scope, sfe->aggrfe, decl, sfe->needExpansion); + if (d) // process generated declarations + { + // Add members lazily. + for (size_t i = 0; i < d->dim; i++) + { + Dsymbol *s = (*d)[i]; + s->addMember(_scope, scopesym); + } + // Set the member scopes lazily. + for (size_t i = 0; i < d->dim; i++) + { + Dsymbol *s = (*d)[i]; + s->setScope(_scope); + } + } + onStack = false; + cached = true; + cache = d; + return d; +} + +void StaticForeachDeclaration::addMember(Scope *, ScopeDsymbol *sds) +{ + // used only for caching the enclosing symbol + this->scopesym = sds; +} + +void StaticForeachDeclaration::addComment(const utf8_t *) +{ + // do nothing + // change this to give semantics to documentation comments on static foreach declarations +} + +void StaticForeachDeclaration::setScope(Scope *sc) +{ + // do not evaluate condition before semantic pass + // But do set the scope, in case we need it for forward referencing + Dsymbol::setScope(sc); +} + +void StaticForeachDeclaration::importAll(Scope *) +{ + // do not evaluate aggregate before semantic pass +} + +void StaticForeachDeclaration::semantic(Scope *sc) +{ + AttribDeclaration::semantic(sc); +} + +const char *StaticForeachDeclaration::kind() const +{ + return "static foreach"; +} + +/*********************************************************** + * Collection of declarations that stores foreach index variables in a + * local symbol table. Other symbols declared within are forwarded to + * another scope, like: + * + * static foreach (i; 0 .. 10) // loop variables for different indices do not conflict. + * { // this body is expanded into 10 ForwardingAttribDeclarations, where `i` has storage class STClocal + * mixin("enum x" ~ to!string(i) ~ " = i"); // ok, can access current loop variable + * } + * + * static foreach (i; 0.. 10) + * { + * pragma(msg, mixin("x" ~ to!string(i))); // ok, all 10 symbols are visible as they were forwarded to the global scope + * } + * + * static assert (!is(typeof(i))); // loop index variable is not visible outside of the static foreach loop + * + * A StaticForeachDeclaration generates one + * ForwardingAttribDeclaration for each expansion of its body. The + * AST of the ForwardingAttribDeclaration contains both the `static + * foreach` variables and the respective copy of the `static foreach` + * body. The functionality is achieved by using a + * ForwardingScopeDsymbol as the parent symbol for the generated + * declarations. + */ + +ForwardingAttribDeclaration::ForwardingAttribDeclaration(Dsymbols *decl) + : AttribDeclaration(decl) +{ + sym = new ForwardingScopeDsymbol(NULL); + sym->symtab = new DsymbolTable(); +} + +/************************************** + * Use the ForwardingScopeDsymbol as the parent symbol for members. + */ +Scope *ForwardingAttribDeclaration::newScope(Scope *sc) +{ + return sc->push(sym); +} + +/*************************************** + * Lazily initializes the scope to forward to. + */ +void ForwardingAttribDeclaration::addMember(Scope *sc, ScopeDsymbol *sds) +{ + parent = sym->parent = sym->forward = sds; + return AttribDeclaration::addMember(sc, sym); +} + /***************************** CompileDeclaration *****************************/ // These are mixin declarations, like mixin("int x"); diff --git a/gcc/d/dmd/attrib.h b/gcc/d/dmd/attrib.h index d1f265a..ccfcdda 100644 --- a/gcc/d/dmd/attrib.h +++ b/gcc/d/dmd/attrib.h @@ -191,6 +191,7 @@ class StaticIfDeclaration : public ConditionalDeclaration public: ScopeDsymbol *scopesym; bool addisdone; + bool onStack; StaticIfDeclaration(Condition *condition, Dsymbols *decl, Dsymbols *elsedecl); Dsymbol *syntaxCopy(Dsymbol *s); @@ -203,14 +204,16 @@ public: void accept(Visitor *v) { v->visit(this); } }; -class StaticForeachDeclaration : public ConditionalDeclaration +class StaticForeachDeclaration : public AttribDeclaration { public: StaticForeach *sfe; ScopeDsymbol *scopesym; + bool onStack; bool cached; Dsymbols *cache; + StaticForeachDeclaration(StaticForeach *sfe, Dsymbols *decl); Dsymbol *syntaxCopy(Dsymbol *s); bool oneMember(Dsymbol **ps, Identifier *ident); Dsymbols *include(Scope *sc, ScopeDsymbol *sds); @@ -223,14 +226,16 @@ public: void accept(Visitor *v) { v->visit(this); } }; -class ForwardingAttribDeclaration : AttribDeclaration +class ForwardingAttribDeclaration : public AttribDeclaration { public: ForwardingScopeDsymbol *sym; + ForwardingAttribDeclaration(Dsymbols *decl); Scope *newScope(Scope *sc); void addMember(Scope *sc, ScopeDsymbol *sds); ForwardingAttribDeclaration *isForwardingAttribDeclaration() { return this; } + void accept(Visitor *v) { v->visit(this); } }; // Mixin declarations diff --git a/gcc/d/dmd/cond.c b/gcc/d/dmd/cond.c index 9d7df5f..c75399d 100644 --- a/gcc/d/dmd/cond.c +++ b/gcc/d/dmd/cond.c @@ -13,6 +13,7 @@ #include "mars.h" #include "id.h" #include "init.h" +#include "aggregate.h" #include "declaration.h" #include "identifier.h" #include "expression.h" @@ -21,6 +22,7 @@ #include "template.h" #include "mtype.h" #include "scope.h" +#include "statement.h" #include "arraytypes.h" #include "tokens.h" @@ -53,6 +55,327 @@ Condition::Condition(Loc loc) /* ============================================================ */ +StaticForeach::StaticForeach(Loc loc, ForeachStatement *aggrfe, ForeachRangeStatement *rangefe) +{ + assert(!!aggrfe ^ !!rangefe); + this->loc = loc; + this->aggrfe = aggrfe; + this->rangefe = rangefe; + this->needExpansion = false; +} + +StaticForeach *StaticForeach::syntaxCopy() +{ + return new StaticForeach( + loc, + aggrfe ? (ForeachStatement *)aggrfe->syntaxCopy() : NULL, + rangefe ? (ForeachRangeStatement *)rangefe->syntaxCopy() : NULL + ); +} + +/***************************************** + * Turn an aggregate which is an array into an expression tuple + * of its elements. I.e., lower + * static foreach (x; [1, 2, 3, 4]) { ... } + * to + * static foreach (x; AliasSeq!(1, 2, 3, 4)) { ... } + */ + +static void lowerArrayAggregate(StaticForeach *sfe, Scope *sc) +{ + Expression *aggr = sfe->aggrfe->aggr; + Expression *el = new ArrayLengthExp(aggr->loc, aggr); + sc = sc->startCTFE(); + el = semantic(el, sc); + sc = sc->endCTFE(); + el = el->optimize(WANTvalue); + el = el->ctfeInterpret(); + if (el->op == TOKint64) + { + dinteger_t length = el->toInteger(); + Expressions *es = new Expressions(); + for (size_t i = 0; i < length; i++) + { + IntegerExp *index = new IntegerExp(sfe->loc, i, Type::tsize_t); + Expression *value = new IndexExp(aggr->loc, aggr, index); + es->push(value); + } + sfe->aggrfe->aggr = new TupleExp(aggr->loc, es); + sfe->aggrfe->aggr = semantic(sfe->aggrfe->aggr, sc); + sfe->aggrfe->aggr = sfe->aggrfe->aggr->optimize(WANTvalue); + } + else + { + sfe->aggrfe->aggr = new ErrorExp(); + } +} + +/***************************************** + * Wrap a statement into a function literal and call it. + * + * Params: + * loc = The source location. + * s = The statement. + * Returns: + * AST of the expression `(){ s; }()` with location loc. + */ + +static Expression *wrapAndCall(Loc loc, Statement *s) +{ + TypeFunction *tf = new TypeFunction(new Parameters(), NULL, 0, LINKdefault, 0); + FuncLiteralDeclaration *fd = new FuncLiteralDeclaration(loc, loc, tf, TOKreserved, NULL); + fd->fbody = s; + FuncExp *fe = new FuncExp(loc, fd); + Expression *ce = new CallExp(loc, fe, new Expressions()); + return ce; +} + +/***************************************** + * Create a `foreach` statement from `aggrefe/rangefe` with given + * `foreach` variables and body `s`. + * + * Params: + * loc = The source location. + * parameters = The foreach variables. + * s = The `foreach` body. + * Returns: + * `foreach (parameters; aggregate) s;` or + * `foreach (parameters; lower .. upper) s;` + * Where aggregate/lower, upper are as for the current StaticForeach. + */ + +static Statement *createForeach(StaticForeach *sfe, Loc loc, Parameters *parameters, Statement *s) +{ + if (sfe->aggrfe) + { + return new ForeachStatement(loc, sfe->aggrfe->op, parameters, sfe->aggrfe->aggr->syntaxCopy(), s, loc); + } + else + { + assert(sfe->rangefe && parameters->dim == 1); + return new ForeachRangeStatement(loc, sfe->rangefe->op, (*parameters)[0], + sfe->rangefe->lwr->syntaxCopy(), + sfe->rangefe->upr->syntaxCopy(), s, loc); + } +} + +/***************************************** + * For a `static foreach` with multiple loop variables, the + * aggregate is lowered to an array of tuples. As D does not have + * built-in tuples, we need a suitable tuple type. This generates + * a `struct` that serves as the tuple type. This type is only + * used during CTFE and hence its typeinfo will not go to the + * object file. + * + * Params: + * loc = The source location. + * e = The expressions we wish to store in the tuple. + * sc = The current scope. + * Returns: + * A struct type of the form + * struct Tuple + * { + * typeof(AliasSeq!(e)) tuple; + * } + */ + +static TypeStruct *createTupleType(Loc loc, Expressions *e) +{ // TODO: move to druntime? + Identifier *sid = Identifier::generateId("Tuple"); + StructDeclaration *sdecl = new StructDeclaration(loc, sid, false); + sdecl->storage_class |= STCstatic; + sdecl->members = new Dsymbols(); + Identifier *fid = Identifier::idPool("tuple"); + Type *ty = new TypeTypeof(loc, new TupleExp(loc, e)); + sdecl->members->push(new VarDeclaration(loc, ty, fid, NULL)); + TypeStruct *r = (TypeStruct *)sdecl->type; + r->vtinfo = TypeInfoStructDeclaration::create(r); // prevent typeinfo from going to object file + return r; +} + +/***************************************** + * Create the AST for an instantiation of a suitable tuple type. + * + * Params: + * loc = The source location. + * type = A Tuple type, created with createTupleType. + * e = The expressions we wish to store in the tuple. + * Returns: + * An AST for the expression `Tuple(e)`. + */ + +static Expression *createTuple(Loc loc, TypeStruct *type, Expressions *e) +{ // TODO: move to druntime? + return new CallExp(loc, new TypeExp(loc, type), e); +} + +/***************************************** + * Lower any aggregate that is not an array to an array using a + * regular foreach loop within CTFE. If there are multiple + * `static foreach` loop variables, an array of tuples is + * generated. In thise case, the field `needExpansion` is set to + * true to indicate that the static foreach loop expansion will + * need to expand the tuples into multiple variables. + * + * For example, `static foreach (x; range) { ... }` is lowered to: + * + * static foreach (x; { + * typeof({ + * foreach (x; range) return x; + * }())[] __res; + * foreach (x; range) __res ~= x; + * return __res; + * }()) { ... } + * + * Finally, call `lowerArrayAggregate` to turn the produced + * array into an expression tuple. + * + * Params: + * sc = The current scope. + */ + +static void lowerNonArrayAggregate(StaticForeach *sfe, Scope *sc) +{ + size_t nvars = sfe->aggrfe ? sfe->aggrfe->parameters->dim : 1; + Loc aloc = sfe->aggrfe ? sfe->aggrfe->aggr->loc : sfe->rangefe->lwr->loc; + // We need three sets of foreach loop variables because the + // lowering contains three foreach loops. + Parameters *pparams[3] = {new Parameters(), new Parameters(), new Parameters()}; + for (size_t i = 0; i < nvars; i++) + { + for (size_t j = 0; j < 3; j++) + { + Parameters *params = pparams[j]; + Parameter *p = sfe->aggrfe ? (*sfe->aggrfe->parameters)[i] : sfe->rangefe->prm; + params->push(new Parameter(p->storageClass, p->type, p->ident, NULL)); + } + } + Expression *res[2]; + TypeStruct *tplty = NULL; + if (nvars == 1) // only one `static foreach` variable, generate identifiers. + { + for (size_t i = 0; i < 2; i++) + { + res[i] = new IdentifierExp(aloc, (*pparams[i])[0]->ident); + } + } + else // multiple `static foreach` variables, generate tuples. + { + for (size_t i = 0; i < 2; i++) + { + Expressions *e = new Expressions(); + for (size_t j = 0; j < pparams[0]->dim; j++) + { + Parameter *p = (*pparams[i])[j]; + e->push(new IdentifierExp(aloc, p->ident)); + } + if (!tplty) + { + tplty = createTupleType(aloc, e); + } + res[i] = createTuple(aloc, tplty, e); + } + sfe->needExpansion = true; // need to expand the tuples later + } + // generate remaining code for the new aggregate which is an + // array (see documentation comment). + if (sfe->rangefe) + { + sc = sc->startCTFE(); + sfe->rangefe->lwr = semantic(sfe->rangefe->lwr, sc); + sfe->rangefe->lwr = resolveProperties(sc, sfe->rangefe->lwr); + sfe->rangefe->upr = semantic(sfe->rangefe->upr, sc); + sfe->rangefe->upr = resolveProperties(sc, sfe->rangefe->upr); + sc = sc->endCTFE(); + sfe->rangefe->lwr = sfe->rangefe->lwr->optimize(WANTvalue); + sfe->rangefe->lwr = sfe->rangefe->lwr->ctfeInterpret(); + sfe->rangefe->upr = sfe->rangefe->upr->optimize(WANTvalue); + sfe->rangefe->upr = sfe->rangefe->upr->ctfeInterpret(); + } + Statements *s1 = new Statements(); + Statements *sfebody = new Statements(); + if (tplty) sfebody->push(new ExpStatement(sfe->loc, tplty->sym)); + sfebody->push(new ReturnStatement(aloc, res[0])); + s1->push(createForeach(sfe, aloc, pparams[0], new CompoundStatement(aloc, sfebody))); + s1->push(new ExpStatement(aloc, new AssertExp(aloc, new IntegerExp(aloc, 0, Type::tint32)))); + Type *ety = new TypeTypeof(aloc, wrapAndCall(aloc, new CompoundStatement(aloc, s1))); + Type *aty = ety->arrayOf(); + Identifier *idres = Identifier::generateId("__res"); + VarDeclaration *vard = new VarDeclaration(aloc, aty, idres, NULL); + Statements *s2 = new Statements(); + s2->push(new ExpStatement(aloc, vard)); + Expression *catass = new CatAssignExp(aloc, new IdentifierExp(aloc, idres), res[1]); + s2->push(createForeach(sfe, aloc, pparams[1], new ExpStatement(aloc, catass))); + s2->push(new ReturnStatement(aloc, new IdentifierExp(aloc, idres))); + Expression *aggr = wrapAndCall(aloc, new CompoundStatement(aloc, s2)); + sc = sc->startCTFE(); + aggr = semantic(aggr, sc); + aggr = resolveProperties(sc, aggr); + sc = sc->endCTFE(); + aggr = aggr->optimize(WANTvalue); + aggr = aggr->ctfeInterpret(); + + assert(!!sfe->aggrfe ^ !!sfe->rangefe); + sfe->aggrfe = new ForeachStatement(sfe->loc, TOKforeach, pparams[2], aggr, + sfe->aggrfe ? sfe->aggrfe->_body : sfe->rangefe->_body, + sfe->aggrfe ? sfe->aggrfe->endloc : sfe->rangefe->endloc); + sfe->rangefe = NULL; + lowerArrayAggregate(sfe, sc); // finally, turn generated array into expression tuple +} + +/***************************************** + * Perform `static foreach` lowerings that are necessary in order + * to finally expand the `static foreach` using + * `ddmd.statementsem.makeTupleForeach`. + */ + +void staticForeachPrepare(StaticForeach *sfe, Scope *sc) +{ + assert(sc); + if (sfe->aggrfe) + { + sc = sc->startCTFE(); + sfe->aggrfe->aggr = semantic(sfe->aggrfe->aggr, sc); + sc = sc->endCTFE(); + sfe->aggrfe->aggr = sfe->aggrfe->aggr->optimize(WANTvalue); + Type *tab = sfe->aggrfe->aggr->type->toBasetype(); + if (tab->ty != Ttuple) + { + sfe->aggrfe->aggr = sfe->aggrfe->aggr->ctfeInterpret(); + } + } + + if (sfe->aggrfe && sfe->aggrfe->aggr->type->toBasetype()->ty == Terror) + { + return; + } + + if (!staticForeachReady(sfe)) + { + if (sfe->aggrfe && sfe->aggrfe->aggr->type->toBasetype()->ty == Tarray) + { + lowerArrayAggregate(sfe, sc); + } + else + { + lowerNonArrayAggregate(sfe, sc); + } + } +} + +/***************************************** + * Returns: + * `true` iff ready to call `ddmd.statementsem.makeTupleForeach`. + */ + +bool staticForeachReady(StaticForeach *sfe) +{ + return sfe->aggrfe && sfe->aggrfe->aggr && sfe->aggrfe->aggr->type && + sfe->aggrfe->aggr->type->toBasetype()->ty == Ttuple; +} + +/* ============================================================ */ + DVCondition::DVCondition(Module *mod, unsigned level, Identifier *ident) : Condition(Loc()) { @@ -324,7 +647,6 @@ StaticIfCondition::StaticIfCondition(Loc loc, Expression *exp) : Condition(loc) { this->exp = exp; - this->nest = 0; } Condition *StaticIfCondition::syntaxCopy() @@ -336,13 +658,6 @@ int StaticIfCondition::include(Scope *sc, ScopeDsymbol *sds) { if (inc == 0) { - if (exp->op == TOKerror || nest > 100) - { - error(loc, (nest > 1000) ? "unresolvable circular static if expression" - : "error evaluating static if expression"); - goto Lerror; - } - if (!sc) { error(loc, "static if conditional cannot be at global scope"); @@ -350,14 +665,12 @@ int StaticIfCondition::include(Scope *sc, ScopeDsymbol *sds) return 0; } - ++nest; sc = sc->push(sc->scopesym); sc->sds = sds; // sds gets any addMember() bool errors = false; bool result = evalStaticCondition(sc, exp, exp, errors); sc->pop(); - --nest; // Prevent repeated condition evaluation. // See: fail_compilation/fail7815.d diff --git a/gcc/d/dmd/cond.h b/gcc/d/dmd/cond.h index 8e33b16..576de8c 100644 --- a/gcc/d/dmd/cond.h +++ b/gcc/d/dmd/cond.h @@ -53,9 +53,13 @@ public: bool needExpansion; + StaticForeach(Loc loc, ForeachStatement *aggrfe, ForeachRangeStatement *rangefe); StaticForeach *syntaxCopy(); }; +void staticForeachPrepare(StaticForeach *sfe, Scope *sc); +bool staticForeachReady(StaticForeach *sfe); + class DVCondition : public Condition { public: @@ -100,7 +104,6 @@ class StaticIfCondition : public Condition { public: Expression *exp; - int nest; // limit circular dependencies StaticIfCondition(Loc loc, Expression *exp); Condition *syntaxCopy(); diff --git a/gcc/d/dmd/cppmangle.c b/gcc/d/dmd/cppmangle.c index 9b24fd2..6179bfd 100644 --- a/gcc/d/dmd/cppmangle.c +++ b/gcc/d/dmd/cppmangle.c @@ -261,7 +261,7 @@ class CppMangleVisitor : public Visitor fatal(); } } - else if(tp->isTemplateThisParameter()) + else if (tp->isTemplateThisParameter()) { ti->error("Internal Compiler Error: C++ `%s` template this parameter is not supported", o->toChars()); fatal(); diff --git a/gcc/d/dmd/declaration.c b/gcc/d/dmd/declaration.c index 0018d95..806e29d 100644 --- a/gcc/d/dmd/declaration.c +++ b/gcc/d/dmd/declaration.c @@ -340,6 +340,9 @@ void AliasDeclaration::semantic(Scope *sc) void AliasDeclaration::aliasSemantic(Scope *sc) { //printf("AliasDeclaration::semantic() %s\n", toChars()); + // TypeTraits needs to know if it's located in an AliasDeclaration + sc->flags |= SCOPEalias; + if (aliassym) { FuncDeclaration *fd = aliassym->isFuncLiteralDeclaration(); @@ -347,7 +350,10 @@ void AliasDeclaration::aliasSemantic(Scope *sc) if (fd || (td && td->literal)) { if (fd && fd->semanticRun >= PASSsemanticdone) + { + sc->flags &= ~SCOPEalias; return; + } Expression *e = new FuncExp(loc, aliassym); e = ::semantic(e, sc); @@ -361,11 +367,13 @@ void AliasDeclaration::aliasSemantic(Scope *sc) aliassym = NULL; type = Type::terror; } + sc->flags &= ~SCOPEalias; return; } if (aliassym->isTemplateInstance()) aliassym->semantic(sc); + sc->flags &= ~SCOPEalias; return; } inuse = 1; @@ -470,6 +478,7 @@ void AliasDeclaration::aliasSemantic(Scope *sc) if (!overloadInsert(sx)) ScopeDsymbol::multiplyDefined(Loc(), sx, this); } + sc->flags &= ~SCOPEalias; } bool AliasDeclaration::overloadInsert(Dsymbol *s) diff --git a/gcc/d/dmd/dinterpret.c b/gcc/d/dmd/dinterpret.c index a1658bb..61f5cdb 100644 --- a/gcc/d/dmd/dinterpret.c +++ b/gcc/d/dmd/dinterpret.c @@ -4649,6 +4649,10 @@ public: result = getVarExp(e->loc, istate, ((SymbolExp *)ea)->var, ctfeNeedRvalue); else if (ea->op == TOKaddress) result = interpret(((AddrExp *)ea)->e1, istate); + // https://issues.dlang.org/show_bug.cgi?id=18871 + // https://issues.dlang.org/show_bug.cgi?id=18819 + else if (ea->op == TOKarrayliteral) + result = interpret((ArrayLiteralExp *)ea, istate); else assert(0); if (CTFEExp::isCantExp(result)) diff --git a/gcc/d/dmd/dmangle.c b/gcc/d/dmd/dmangle.c index 44f4f82..f41f628 100644 --- a/gcc/d/dmd/dmangle.c +++ b/gcc/d/dmd/dmangle.c @@ -80,6 +80,7 @@ void initTypeMangle() mangleChar[Tslice] = "@"; mangleChar[Treturn] = "@"; mangleChar[Tvector] = "@"; + mangleChar[Ttraits] = "@"; mangleChar[Tnull] = "n"; // same as TypeNone diff --git a/gcc/d/dmd/dsymbol.c b/gcc/d/dmd/dsymbol.c index 9aec87a..05ab04c 100644 --- a/gcc/d/dmd/dsymbol.c +++ b/gcc/d/dmd/dsymbol.c @@ -321,12 +321,12 @@ Dsymbol *Dsymbol::toAlias2() */ Dsymbol *Dsymbol::pastMixin() { - Dsymbol *s = this; - //printf("Dsymbol::pastMixin() %s\n", toChars()); - while (s && s->isTemplateMixin()) - s = s->parent; - return s; + if (!isTemplateMixin() && !isForwardingAttribDeclaration() && !isForwardingScopeDsymbol()) + return this; + if (!parent) + return NULL; + return parent->pastMixin(); } /// ditto @@ -334,7 +334,8 @@ Dsymbol *Dsymbol::pastMixinAndNspace() { //printf("Dsymbol::pastMixinAndNspace() %s\n", toChars()); Nspace *ns = isNspace(); - if (!(ns && ns->mangleOnly) && !isTemplateMixin() && !isForwardingAttribDeclaration()) + if (!(ns && ns->mangleOnly) && + !isTemplateMixin() && !isForwardingAttribDeclaration() && !isForwardingScopeDsymbol()) return this; if (!parent) return NULL; @@ -382,10 +383,12 @@ Dsymbol *Dsymbol::toParent() /// ditto Dsymbol *Dsymbol::toParent2() { - Dsymbol *s = parent; - while (s && s->isTemplateInstance()) - s = s->parent; - return s; + if (!parent || + (!parent->isTemplateInstance() && + !parent->isForwardingAttribDeclaration() && + !parent->isForwardingScopeDsymbol())) + return parent; + return parent->toParent2(); } /// ditto @@ -951,6 +954,83 @@ const char *OverloadSet::kind() const } +/********************************* ForwardingScopeDsymbol ******************/ + +ForwardingScopeDsymbol::ForwardingScopeDsymbol(ScopeDsymbol *forward) + : ScopeDsymbol() +{ + this->forward = forward; +} + +Dsymbol *ForwardingScopeDsymbol::symtabInsert(Dsymbol *s) +{ + assert(forward); + if (Declaration *d = s->isDeclaration()) + { + if (d->storage_class & STClocal) + { + // Symbols with storage class STClocal are not + // forwarded, but stored in the local symbol + // table. (Those are the `static foreach` variables.) + if (!symtab) + { + symtab = new DsymbolTable(); + } + return ScopeDsymbol::symtabInsert(s); // insert locally + } + } + if (!forward->symtab) + { + forward->symtab = new DsymbolTable(); + } + // Non-STClocal symbols are forwarded to `forward`. + return forward->symtabInsert(s); +} + +/************************ + * This override handles the following two cases: + * static foreach (i, i; [0]) { ... } + * and + * static foreach (i; [0]) { enum i = 2; } + */ +Dsymbol *ForwardingScopeDsymbol::symtabLookup(Dsymbol *s, Identifier *id) +{ + assert(forward); + // correctly diagnose clashing foreach loop variables. + if (Declaration *d = s->isDeclaration()) + { + if (d->storage_class & STClocal) + { + if (!symtab) + { + symtab = new DsymbolTable(); + } + return ScopeDsymbol::symtabLookup(s,id); + } + } + // Declarations within `static foreach` do not clash with + // `static foreach` loop variables. + if (!forward->symtab) + { + forward->symtab = new DsymbolTable(); + } + return forward->symtabLookup(s,id); +} + +void ForwardingScopeDsymbol::importScope(Dsymbol *s, Prot protection) +{ + forward->importScope(s, protection); +} + +void ForwardingScopeDsymbol::semantic(Scope *) +{ +} + +const char *ForwardingScopeDsymbol::kind() const +{ + return "local scope"; +} + /********************************* ScopeDsymbol ****************************/ ScopeDsymbol::ScopeDsymbol() diff --git a/gcc/d/dmd/dsymbol.h b/gcc/d/dmd/dsymbol.h index a840261..788b67e 100644 --- a/gcc/d/dmd/dsymbol.h +++ b/gcc/d/dmd/dsymbol.h @@ -376,8 +376,10 @@ public: class ForwardingScopeDsymbol : public ScopeDsymbol { +public: ScopeDsymbol *forward; + ForwardingScopeDsymbol(ScopeDsymbol *forward); Dsymbol *symtabInsert(Dsymbol *s); Dsymbol *symtabLookup(Dsymbol *s, Identifier *id); void importScope(Dsymbol *s, Prot protection); diff --git a/gcc/d/dmd/expression.c b/gcc/d/dmd/expression.c index 5f1bfa8..ccfb4b6 100644 --- a/gcc/d/dmd/expression.c +++ b/gcc/d/dmd/expression.c @@ -2185,6 +2185,11 @@ StringExp *Expression::toStringExp() return NULL; } +TupleExp *Expression::toTupleExp() +{ + return NULL; +} + /*************************************** * Return !=0 if expression is an lvalue. */ @@ -4542,6 +4547,11 @@ Expression *TupleExp::syntaxCopy() return new TupleExp(loc, e0 ? e0->syntaxCopy() : NULL, arraySyntaxCopy(exps)); } +TupleExp *TupleExp::toTupleExp() +{ + return this; +} + /******************************** FuncExp *********************************/ FuncExp::FuncExp(Loc loc, Dsymbol *s) diff --git a/gcc/d/dmd/expression.h b/gcc/d/dmd/expression.h index b460e8c..6044860 100644 --- a/gcc/d/dmd/expression.h +++ b/gcc/d/dmd/expression.h @@ -157,6 +157,7 @@ public: virtual real_t toImaginary(); virtual complex_t toComplex(); virtual StringExp *toStringExp(); + virtual TupleExp *toTupleExp(); virtual bool isLvalue(); virtual Expression *toLvalue(Scope *sc, Expression *e); virtual Expression *modifiableLvalue(Scope *sc, Expression *e); @@ -397,6 +398,7 @@ public: TupleExp(Loc loc, Expression *e0, Expressions *exps); TupleExp(Loc loc, Expressions *exps); TupleExp(Loc loc, TupleDeclaration *tup); + TupleExp *toTupleExp(); Expression *syntaxCopy(); bool equals(RootObject *o); diff --git a/gcc/d/dmd/expressionsem.c b/gcc/d/dmd/expressionsem.c index c23e332..781bd3e 100644 --- a/gcc/d/dmd/expressionsem.c +++ b/gcc/d/dmd/expressionsem.c @@ -1758,15 +1758,30 @@ public: else { // Disallow shadowing - for (Scope *scx = sc->enclosing; scx && scx->func == sc->func; scx = scx->enclosing) + for (Scope *scx = sc->enclosing; scx && (scx->func == sc->func || (scx->func && sc->func->fes)); scx = scx->enclosing) { Dsymbol *s2; if (scx->scopesym && scx->scopesym->symtab && (s2 = scx->scopesym->symtab->lookup(s->ident)) != NULL && s != s2) { - e->error("%s %s is shadowing %s %s", s->kind(), s->ident->toChars(), s2->kind(), s2->toPrettyChars()); - return setError(); + // allow STClocal symbols to be shadowed + // TODO: not reallly an optimal design + Declaration *decl = s2->isDeclaration(); + if (!decl || !(decl->storage_class & STClocal)) + { + if (sc->func->fes) + { + e->deprecation("%s `%s` is shadowing %s `%s`. Rename the `foreach` variable.", + s->kind(), s->ident->toChars(), s2->kind(), s2->toPrettyChars()); + } + else + { + e->error("%s %s is shadowing %s %s", + s->kind(), s->ident->toChars(), s2->kind(), s2->toPrettyChars()); + return setError(); + } + } } } } @@ -7930,6 +7945,12 @@ public: if (f1 || f2) return setError(); + if (exp->e1->op == TOKtype || exp->e2->op == TOKtype) + { + result = exp->incompatibleTypes(); + return; + } + exp->type = Type::tbool; if (exp->e1->type != exp->e2->type && exp->e1->type->isfloating() && exp->e2->type->isfloating()) diff --git a/gcc/d/dmd/func.c b/gcc/d/dmd/func.c index 11e4b2f..ab74dc5 100644 --- a/gcc/d/dmd/func.c +++ b/gcc/d/dmd/func.c @@ -1491,8 +1491,7 @@ void FuncDeclaration::semantic3(Scope *sc) * e.g. * class C { int x; static assert(is(typeof({ this.x = 1; }))); } * - * To properly accept it, mark these lambdas as member functions - - * isThis() returns true and isNested() returns false. + * To properly accept it, mark these lambdas as member functions. */ if (FuncLiteralDeclaration *fld = isFuncLiteralDeclaration()) { @@ -1510,7 +1509,6 @@ void FuncDeclaration::semantic3(Scope *sc) if (fld->tok != TOKfunction) fld->tok = TOKdelegate; } - assert(!isNested()); } } diff --git a/gcc/d/dmd/hdrgen.c b/gcc/d/dmd/hdrgen.c index 395aa32..2436f6e 100644 --- a/gcc/d/dmd/hdrgen.c +++ b/gcc/d/dmd/hdrgen.c @@ -249,7 +249,7 @@ public: buf->writenl(); } - void visit(ForeachStatement *s) + void foreachWithoutBody(ForeachStatement *s) { buf->writestring(Token::toChars(s->op)); buf->writestring(" ("); @@ -269,6 +269,11 @@ public: s->aggr->accept(this); buf->writeByte(')'); buf->writenl(); + } + + void visit(ForeachStatement *s) + { + foreachWithoutBody(s); buf->writeByte('{'); buf->writenl(); buf->level++; @@ -279,7 +284,7 @@ public: buf->writenl(); } - void visit(ForeachRangeStatement *s) + void foreachRangeWithoutBody(ForeachRangeStatement *s) { buf->writestring(Token::toChars(s->op)); buf->writestring(" ("); @@ -297,6 +302,11 @@ public: buf->writenl(); buf->writeByte('{'); buf->writenl(); + } + + void visit(ForeachRangeStatement *s) + { + foreachRangeWithoutBody(s); buf->level++; if (s->_body) s->_body->accept(this); @@ -305,6 +315,20 @@ public: buf->writenl(); } + void visit(StaticForeachStatement *s) + { + buf->writestring("static "); + if (s->sfe->aggrfe) + { + visit(s->sfe->aggrfe); + } + else + { + assert(s->sfe->rangefe); + visit(s->sfe->rangefe); + } + } + void visit(IfStatement *s) { buf->writestring("if ("); @@ -767,6 +791,12 @@ public: buf->writestring(t->dstring); } + void visit(TypeTraits *t) + { + //printf("TypeBasic::toCBuffer2(t.mod = %d)\n", t.mod); + t->exp->accept(this); + } + void visit(TypeVector *t) { //printf("TypeVector::toCBuffer2(t->mod = %d)\n", t->mod); @@ -1360,6 +1390,32 @@ public: buf->writenl(); } + void visit(ForwardingStatement *s) + { + s->statement->accept(this); + } + + void visit(StaticForeachDeclaration *s) + { + buf->writestring("static "); + if (s->sfe->aggrfe) + { + foreachWithoutBody(s->sfe->aggrfe); + } + else + { + assert(s->sfe->rangefe); + foreachRangeWithoutBody(s->sfe->rangefe); + } + buf->writeByte('{'); + buf->writenl(); + buf->level++; + visit((AttribDeclaration *)s); + buf->level--; + buf->writeByte('}'); + buf->writenl(); + } + void visit(CompileDeclaration *d) { buf->writestring("mixin("); @@ -1787,6 +1843,8 @@ public: void visit(AliasDeclaration *d) { + if (d->storage_class & STClocal) + return; buf->writestring("alias "); if (d->aliassym) { @@ -1818,6 +1876,8 @@ public: void visit(VarDeclaration *d) { + if (d->storage_class & STClocal) + return; visitVarDecl(d, false); buf->writeByte(';'); buf->writenl(); @@ -2653,7 +2713,8 @@ public: void visit(TraitsExp *e) { buf->writestring("__traits("); - buf->writestring(e->ident->toChars()); + if (e->ident) + buf->writestring(e->ident->toChars()); if (e->args) { for (size_t i = 0; i < e->args->dim; i++) @@ -3241,6 +3302,7 @@ const char *stcToChars(StorageClass& stc) { STCsystem, TOKat, "@system" }, { STCdisable, TOKat, "@disable" }, { STCfuture, TOKat, "@__future" }, + { STClocal, TOKat, "__local" }, { 0, TOKreserved, NULL } }; diff --git a/gcc/d/dmd/init.c b/gcc/d/dmd/init.c index b40ebe3..7bd44ab 100644 --- a/gcc/d/dmd/init.c +++ b/gcc/d/dmd/init.c @@ -238,7 +238,7 @@ bool hasNonConstPointers(Expression *e) return arrayHasNonConstPointers(ae->keys); return false; } - if(e->op == TOKaddress) + if (e->op == TOKaddress) { AddrExp *ae = (AddrExp *)e; if (ae->e1->op == TOKstructliteral) diff --git a/gcc/d/dmd/intrange.c b/gcc/d/dmd/intrange.c index e0e2472..c56d7ba 100644 --- a/gcc/d/dmd/intrange.c +++ b/gcc/d/dmd/intrange.c @@ -610,7 +610,7 @@ IntRange IntRange::operator/(const IntRange& rhs) const { r.imax.value--; } - else if(r.imin.value == 0) + else if (r.imin.value == 0) { r.imin.value++; } diff --git a/gcc/d/dmd/json.c b/gcc/d/dmd/json.c index acdafa5..fa49e92 100644 --- a/gcc/d/dmd/json.c +++ b/gcc/d/dmd/json.c @@ -454,6 +454,8 @@ public: void jsonProperties(Declaration *d) { + if (d->storage_class & STClocal) + return; jsonProperties((Dsymbol *)d); propertyStorageClass("storageClass", d->storage_class); @@ -843,6 +845,8 @@ public: void visit(VarDeclaration *d) { + if (d->storage_class & STClocal) + return; objectStart(); jsonProperties(d); diff --git a/gcc/d/dmd/mtype.c b/gcc/d/dmd/mtype.c index b76b5ba..aa18806 100644 --- a/gcc/d/dmd/mtype.c +++ b/gcc/d/dmd/mtype.c @@ -202,6 +202,7 @@ void Type::_init() sizeTy[Terror] = sizeof(TypeError); sizeTy[Tnull] = sizeof(TypeNull); sizeTy[Tvector] = sizeof(TypeVector); + sizeTy[Ttraits] = sizeof(TypeTraits); initTypeMangle(); @@ -6459,7 +6460,7 @@ Type *TypeDelegate::addStorageClass(StorageClass stc) * alias dg_t = void* delegate(); * scope dg_t dg = ...; */ - if(stc & STCscope) + if (stc & STCscope) { Type *n = t->next->addStorageClass(STCscope | STCscopeinferred); if (n != t->next) @@ -6554,7 +6555,156 @@ bool TypeDelegate::hasPointers() return true; } +/***************************** TypeTraits ********************************/ + +TypeTraits::TypeTraits(const Loc &loc, TraitsExp *exp) + : Type(Ttraits) +{ + this->loc = loc; + this->exp = exp; + this->sym = NULL; +} + +Type *TypeTraits::syntaxCopy() +{ + TraitsExp *te = (TraitsExp *) exp->syntaxCopy(); + TypeTraits *tt = new TypeTraits(loc, te); + tt->mod = mod; + return tt; +} +Type *TypeTraits::semantic(Loc, Scope *sc) +{ + if (ty == Terror) + return this; + + const int inAlias = (sc->flags & SCOPEalias) != 0; + if (exp->ident != Id::allMembers && + exp->ident != Id::derivedMembers && + exp->ident != Id::getMember && + exp->ident != Id::parent && + exp->ident != Id::getOverloads && + exp->ident != Id::getVirtualFunctions && + exp->ident != Id::getVirtualMethods && + exp->ident != Id::getAttributes && + exp->ident != Id::getUnitTests && + exp->ident != Id::getAliasThis) + { + static const char *ctxt[2] = {"as type", "in alias"}; + ::error(loc, "trait `%s` is either invalid or not supported %s", + exp->ident->toChars(), ctxt[inAlias]); + ty = Terror; + return this; + } + + Type *result = NULL; + + if (Expression *e = semanticTraits(exp, sc)) + { + switch (e->op) + { + case TOKdotvar: + sym = ((DotVarExp *)e)->var; + break; + case TOKvar: + sym = ((VarExp *)e)->var; + break; + case TOKfunction: + { + FuncExp *fe = (FuncExp *)e; + if (fe->td) + sym = fe->td; + else + sym = fe->fd; + break; + } + case TOKdottd: + sym = ((DotTemplateExp*)e)->td; + break; + case TOKdsymbol: + sym = ((DsymbolExp *)e)->s; + break; + case TOKtemplate: + sym = ((TemplateExp *)e)->td; + break; + case TOKscope: + sym = ((ScopeExp *)e)->sds; + break; + case TOKtuple: + { + TupleExp *te = e->toTupleExp(); + Objects *elems = new Objects; + elems->setDim(te->exps->dim); + for (size_t i = 0; i < elems->dim; i++) + { + Expression *src = (*te->exps)[i]; + switch (src->op) + { + case TOKtype: + (*elems)[i] = ((TypeExp *)src)->type; + break; + case TOKdottype: + (*elems)[i] = ((DotTypeExp *)src)->type; + break; + case TOKoverloadset: + (*elems)[i] = ((OverExp *)src)->type; + break; + default: + if (Dsymbol *sym = isDsymbol(src)) + (*elems)[i] = sym; + else + (*elems)[i] = src; + } + } + TupleDeclaration *td = new TupleDeclaration(e->loc, + Identifier::generateId("__aliastup"), elems); + sym = td; + break; + } + case TOKdottype: + result = isType(((DotTypeExp *)e)->sym); + break; + case TOKtype: + result = ((TypeExp *)e)->type; + break; + case TOKoverloadset: + result = ((OverExp *)e)->type; + break; + default: + break; + } + } + + if (result) + result = result->addMod(mod); + if (!inAlias && !result) + { + if (!global.errors) + ::error(loc, "`%s` does not give a valid type", toChars()); + return Type::terror; + } + + return result; +} + +void TypeTraits::resolve(Loc loc, Scope *sc, Expression **pe, Type **pt, Dsymbol **ps, bool) +{ + *pt = NULL; + *pe = NULL; + *ps = NULL; + + if (Type *t = semantic(loc, sc)) + *pt = t; + else if (sym) + *ps = sym; + else + *pt = Type::terror; +} + +d_uns64 TypeTraits::size(Loc) +{ + return SIZE_INVALID; +} /***************************** TypeQualified *****************************/ diff --git a/gcc/d/dmd/mtype.h b/gcc/d/dmd/mtype.h index aab0d03..22fabf5 100644 --- a/gcc/d/dmd/mtype.h +++ b/gcc/d/dmd/mtype.h @@ -94,6 +94,7 @@ enum ENUMTY Tvector, Tint128, Tuns128, + Ttraits, TMAX }; typedef unsigned char TY; // ENUMTY @@ -659,6 +660,23 @@ public: void accept(Visitor *v) { v->visit(this); } }; +class TypeTraits : public Type +{ +public: + Loc loc; + /// The expression to resolve as type or symbol. + TraitsExp *exp; + /// The symbol when exp doesn't represent a type. + Dsymbol *sym; + + TypeTraits(const Loc &loc, TraitsExp *exp); + Type *syntaxCopy(); + Type *semantic(Loc loc, Scope *sc); + void resolve(Loc loc, Scope *sc, Expression **pe, Type **pt, Dsymbol **ps, bool intypeid = false); + d_uns64 size(Loc loc); + void accept(Visitor *v) { v->visit(this); } +}; + class TypeQualified : public Type { public: diff --git a/gcc/d/dmd/parse.c b/gcc/d/dmd/parse.c index 9da58af..b66bddb 100644 --- a/gcc/d/dmd/parse.c +++ b/gcc/d/dmd/parse.c @@ -351,6 +351,7 @@ Dsymbols *Parser::parseDeclDefs(int once, Dsymbol **pLastDecl, PrefixAttributes case TOKunion: case TOKclass: case TOKinterface: + case TOKtraits: Ldeclaration: a = parseDeclarations(false, pAttrs, pAttrs->comment); if (a && a->dim) @@ -485,6 +486,10 @@ Dsymbols *Parser::parseDeclDefs(int once, Dsymbol **pLastDecl, PrefixAttributes a = parseImport(); // keep pLastDecl } + else if (next == TOKforeach || next == TOKforeach_reverse) + { + s = parseForeachStaticDecl(token.loc, pLastDecl); + } else { stc = STCstatic; @@ -3144,6 +3149,18 @@ Type *Parser::parseBasicType(bool dontLookDotIdents) t = parseVector(); break; + case TOKtraits: + if (TraitsExp *te = (TraitsExp *) parsePrimaryExp()) + { + if (te->ident && te->args) + { + t = new TypeTraits(token.loc, te); + break; + } + } + t = new TypeError(); + break; + case TOKconst: // const(type) nextToken(); @@ -4700,6 +4717,161 @@ void Parser::checkCstyleTypeSyntax(Loc loc, Type *t, int alt, Identifier *ident) } /***************************************** + * Parses `foreach` statements, `static foreach` statements and + * `static foreach` declarations. The template parameter + * `isStatic` is true, iff a `static foreach` should be parsed. + * If `isStatic` is true, `isDecl` can be true to indicate that a + * `static foreach` declaration should be parsed. + */ +Statement *Parser::parseForeach(Loc loc, bool *isRange, bool isDecl) +{ + TOK op = token.value; + + nextToken(); + check(TOKlparen); + + Parameters *parameters = new Parameters(); + + while (1) + { + Identifier *ai = NULL; + Type *at; + + StorageClass storageClass = 0; + StorageClass stc = 0; + Lagain: + if (stc) + { + storageClass = appendStorageClass(storageClass, stc); + nextToken(); + } + switch (token.value) + { + case TOKref: + stc = STCref; + goto Lagain; + + case TOKenum: + stc = STCmanifest; + goto Lagain; + + case TOKalias: + storageClass = appendStorageClass(storageClass, STCalias); + nextToken(); + break; + + case TOKconst: + if (peekNext() != TOKlparen) + { + stc = STCconst; + goto Lagain; + } + break; + + case TOKimmutable: + if (peekNext() != TOKlparen) + { + stc = STCimmutable; + goto Lagain; + } + break; + + case TOKshared: + if (peekNext() != TOKlparen) + { + stc = STCshared; + goto Lagain; + } + break; + + case TOKwild: + if (peekNext() != TOKlparen) + { + stc = STCwild; + goto Lagain; + } + break; + + default: + break; + } + if (token.value == TOKidentifier) + { + Token *t = peek(&token); + if (t->value == TOKcomma || t->value == TOKsemicolon) + { ai = token.ident; + at = NULL; // infer argument type + nextToken(); + goto Larg; + } + } + at = parseType(&ai); + if (!ai) + error("no identifier for declarator %s", at->toChars()); + Larg: + Parameter *p = new Parameter(storageClass, at, ai, NULL); + parameters->push(p); + if (token.value == TOKcomma) + { nextToken(); + continue; + } + break; + } + check(TOKsemicolon); + + Expression *aggr = parseExpression(); + if (token.value == TOKslice && parameters->dim == 1) + { + Parameter *p = (*parameters)[0]; + delete parameters; + nextToken(); + Expression *upr = parseExpression(); + check(TOKrparen); + Loc endloc; + Statement *body = (!isDecl) ? parseStatement(0, NULL, &endloc) : NULL; + if (isRange) + *isRange = true; + return new ForeachRangeStatement(loc, op, p, aggr, upr, body, endloc); + } + else + { + check(TOKrparen); + Loc endloc; + Statement *body = (!isDecl) ? parseStatement(0, NULL, &endloc) : NULL; + if (isRange) + *isRange = false; + return new ForeachStatement(loc, op, parameters, aggr, body, endloc); + } +} + +Dsymbol *Parser::parseForeachStaticDecl(Loc loc, Dsymbol **pLastDecl) +{ + nextToken(); + + bool isRange = false; + Statement *s = parseForeach(loc, &isRange, true); + + return new StaticForeachDeclaration( + new StaticForeach(loc, isRange ? NULL : (ForeachStatement *)s, + isRange ? (ForeachRangeStatement *)s : NULL), + parseBlock(pLastDecl) + ); +} + +Statement *Parser::parseForeachStatic(Loc loc) +{ + nextToken(); + + bool isRange = false; + Statement *s = parseForeach(loc, &isRange, false); + + return new StaticForeachStatement(loc, + new StaticForeach(loc, isRange ? NULL : (ForeachStatement *)s, + isRange ? (ForeachRangeStatement *)s : NULL) + ); +} + +/***************************************** * Input: * flags PSxxxx * Output: @@ -4757,6 +4929,7 @@ Statement *Parser::parseStatement(int flags, const utf8_t** endPtr, Loc *pEndloc case TOKdot: case TOKtypeof: case TOKvector: + case TOKtraits: /* Bugzilla 15163: If tokens can be handled as * old C-style declaration or D expression, prefer the latter. */ @@ -4805,7 +4978,6 @@ Statement *Parser::parseStatement(int flags, const utf8_t** endPtr, Loc *pEndloc case TOKtypeid: case TOKis: case TOKlbracket: - case TOKtraits: case TOKfile: case TOKfilefullpath: case TOKline: @@ -4834,6 +5006,13 @@ Statement *Parser::parseStatement(int flags, const utf8_t** endPtr, Loc *pEndloc cond = parseStaticIfCondition(); goto Lcondition; } + else if (t->value == TOKforeach || t->value == TOKforeach_reverse) + { + s = parseForeachStatic(loc); + if (flags & PSscope) + s = new ScopeStatement(loc, s, token.loc); + break; + } if (t->value == TOKimport) { Dsymbols *imports = parseImport(); @@ -5086,106 +5265,7 @@ Statement *Parser::parseStatement(int flags, const utf8_t** endPtr, Loc *pEndloc case TOKforeach: case TOKforeach_reverse: { - TOK op = token.value; - - nextToken(); - check(TOKlparen); - - Parameters *parameters = new Parameters(); - - while (1) - { - Identifier *ai = NULL; - Type *at; - - StorageClass storageClass = 0; - StorageClass stc = 0; - Lagain: - if (stc) - { - storageClass = appendStorageClass(storageClass, stc); - nextToken(); - } - switch (token.value) - { - case TOKref: - stc = STCref; - goto Lagain; - - case TOKconst: - if (peekNext() != TOKlparen) - { - stc = STCconst; - goto Lagain; - } - break; - case TOKimmutable: - if (peekNext() != TOKlparen) - { - stc = STCimmutable; - goto Lagain; - } - break; - case TOKshared: - if (peekNext() != TOKlparen) - { - stc = STCshared; - goto Lagain; - } - break; - case TOKwild: - if (peekNext() != TOKlparen) - { - stc = STCwild; - goto Lagain; - } - break; - default: - break; - } - if (token.value == TOKidentifier) - { - Token *t = peek(&token); - if (t->value == TOKcomma || t->value == TOKsemicolon) - { ai = token.ident; - at = NULL; // infer argument type - nextToken(); - goto Larg; - } - } - at = parseType(&ai); - if (!ai) - error("no identifier for declarator %s", at->toChars()); - Larg: - Parameter *p = new Parameter(storageClass, at, ai, NULL); - parameters->push(p); - if (token.value == TOKcomma) - { nextToken(); - continue; - } - break; - } - check(TOKsemicolon); - - Expression *aggr = parseExpression(); - if (token.value == TOKslice && parameters->dim == 1) - { - Parameter *p = (*parameters)[0]; - delete parameters; - nextToken(); - Expression *upr = parseExpression(); - check(TOKrparen); - Loc endloc; - Statement *body = parseStatement(0, NULL, &endloc); - s = new ForeachRangeStatement(loc, op, p, aggr, upr, body, endloc); - } - else - { - check(TOKrparen); - Loc endloc; - Statement *body = parseStatement(0, NULL, &endloc); - s = new ForeachStatement(loc, op, parameters, aggr, body, endloc); - } + s = parseForeach(loc, NULL, false); break; } @@ -6001,6 +6081,27 @@ bool Parser::isBasicType(Token **pt) goto Lfalse; goto L3; + case TOKtraits: + { + // __traits(getMember + t = peek(t); + if (t->value != TOKlparen) + goto Lfalse; + Token *lp = t; + t = peek(t); + if (t->value != TOKidentifier || t->ident != Id::getMember) + goto Lfalse; + if (!skipParens(lp, &lp)) + goto Lfalse; + // we are in a lookup for decl VS statement + // so we expect a declarator following __trait if it's a type. + // other usages wont be ambiguous (alias, template instance, type qual, etc.) + if (lp->value != TOKidentifier) + goto Lfalse; + + break; + } + case TOKconst: case TOKimmutable: case TOKshared: @@ -7390,6 +7491,7 @@ Expression *Parser::parseUnaryExp() case TOKfunction: case TOKdelegate: case TOKtypeof: + case TOKtraits: case TOKvector: case TOKfile: case TOKfilefullpath: diff --git a/gcc/d/dmd/parse.h b/gcc/d/dmd/parse.h index 97630dc..c5ef0b2 100644 --- a/gcc/d/dmd/parse.h +++ b/gcc/d/dmd/parse.h @@ -120,6 +120,9 @@ public: FuncDeclaration *parseContracts(FuncDeclaration *f); void checkDanglingElse(Loc elseloc); void checkCstyleTypeSyntax(Loc loc, Type *t, int alt, Identifier *ident); + Statement *parseForeach(Loc loc, bool *isRange, bool isDecl); + Dsymbol *parseForeachStaticDecl(Loc loc, Dsymbol **pLastDecl); + Statement *parseForeachStatic(Loc loc); /** endPtr used for documented unittests */ Statement *parseStatement(int flags, const utf8_t** endPtr = NULL, Loc *pEndloc = NULL); Initializer *parseInitializer(); diff --git a/gcc/d/dmd/scope.h b/gcc/d/dmd/scope.h index 37a15fc..d34a0e7 100644 --- a/gcc/d/dmd/scope.h +++ b/gcc/d/dmd/scope.h @@ -61,9 +61,10 @@ enum PINLINE; #define SCOPEctfe 0x0080 // inside a ctfe-only expression #define SCOPEcompile 0x0100 // inside __traits(compile) #define SCOPEignoresymbolvisibility 0x0200 // ignore symbol visibility (Bugzilla 15907) -#define SCOPEfullinst 0x1000 // fully instantiate templates #define SCOPEfree 0x8000 // is on free list +#define SCOPEfullinst 0x10000 // fully instantiate templates +#define SCOPEalias 0x20000 // inside alias declaration struct Scope { diff --git a/gcc/d/dmd/statement.c b/gcc/d/dmd/statement.c index 450b3f4..6c3443c 100644 --- a/gcc/d/dmd/statement.c +++ b/gcc/d/dmd/statement.c @@ -32,6 +32,7 @@ bool checkEscapeRef(Scope *sc, Expression *e, bool gag); VarDeclaration *copyToTemp(StorageClass stc, const char *name, Expression *e); Expression *semantic(Expression *e, Scope *sc); StringExp *semanticString(Scope *sc, Expression *exp, const char *s); +Statement *makeTupleForeachStatic(Scope *sc, ForeachStatement *fs, bool needExpansion); Identifier *fixupLabelName(Scope *sc, Identifier *ident) { @@ -410,6 +411,7 @@ Statement *toStatement(Dsymbol *s) void visit(ProtDeclaration *d) { result = visitMembers(d->loc, d->decl); } void visit(AlignDeclaration *d) { result = visitMembers(d->loc, d->decl); } void visit(UserAttributeDeclaration *d) { result = visitMembers(d->loc, d->decl); } + void visit(ForwardingAttribDeclaration *d) { result = visitMembers(d->loc, d->decl); } void visit(StaticAssert *) {} void visit(Import *) {} @@ -420,6 +422,12 @@ Statement *toStatement(Dsymbol *s) result = visitMembers(d->loc, d->include(NULL, NULL)); } + void visit(StaticForeachDeclaration *d) + { + assert(d->sfe && !!d->sfe->aggrfe ^ !!d->sfe->rangefe); + result = visitMembers(d->loc, d->include(NULL, NULL)); + } + void visit(CompileDeclaration *d) { result = visitMembers(d->loc, d->include(NULL, NULL)); @@ -682,6 +690,72 @@ bool ScopeStatement::hasContinue() return statement ? statement->hasContinue() : false; } +/******************************** ForwardingStatement **********************/ + +/* Statement whose symbol table contains foreach index variables in a + * local scope and forwards other members to the parent scope. This + * wraps a statement. + * + * Also see: `ddmd.attrib.ForwardingAttribDeclaration` + */ + +ForwardingStatement::ForwardingStatement(Loc loc, ForwardingScopeDsymbol *sym, Statement *s) + : Statement(loc) +{ + this->sym = sym; + assert(s); + this->statement = s; +} + +ForwardingStatement::ForwardingStatement(Loc loc, Statement *s) + : Statement(loc) +{ + this->sym = new ForwardingScopeDsymbol(NULL); + this->sym->symtab = new DsymbolTable(); + assert(s); + this->statement = s; +} + +Statement *ForwardingStatement::syntaxCopy() +{ + return new ForwardingStatement(loc, statement->syntaxCopy()); +} + +/*********************** + * ForwardingStatements are distributed over the flattened + * sequence of statements. This prevents flattening to be + * "blocked" by a ForwardingStatement and is necessary, for + * example, to support generating scope guards with `static + * foreach`: + * + * static foreach(i; 0 .. 10) scope(exit) writeln(i); + * writeln("this is printed first"); + * // then, it prints 10, 9, 8, 7, ... + */ + +Statements *ForwardingStatement::flatten(Scope *sc) +{ + if (!statement) + { + return NULL; + } + sc = sc->push(sym); + Statements *a = statement->flatten(sc); + sc = sc->pop(); + if (!a) + { + return a; + } + Statements *b = new Statements(); + b->setDim(a->dim); + for (size_t i = 0; i < a->dim; i++) + { + Statement *s = (*a)[i]; + (*b)[i] = s ? new ForwardingStatement(s->loc, sym, s) : NULL; + } + return b; +} + /******************************** WhileStatement ***************************/ WhileStatement::WhileStatement(Loc loc, Expression *c, Statement *b, Loc endloc) @@ -935,6 +1009,52 @@ Statements *ConditionalStatement::flatten(Scope *sc) return a; } +/******************************** StaticForeachStatement ********************/ + +/* Static foreach statements, like: + * void main() + * { + * static foreach(i; 0 .. 10) + * { + * pragma(msg, i); + * } + * } + */ + +StaticForeachStatement::StaticForeachStatement(Loc loc, StaticForeach *sfe) + : Statement(loc) +{ + this->sfe = sfe; +} + +Statement *StaticForeachStatement::syntaxCopy() +{ + return new StaticForeachStatement(loc, sfe->syntaxCopy()); +} + +Statements *StaticForeachStatement::flatten(Scope *sc) +{ + staticForeachPrepare(sfe, sc); + if (staticForeachReady(sfe)) + { + Statement *s = makeTupleForeachStatic(sc, sfe->aggrfe, sfe->needExpansion); + Statements *result = s->flatten(sc); + if (result) + { + return result; + } + result = new Statements(); + result->push(s); + return result; + } + else + { + Statements *result = new Statements(); + result->push(new ErrorStatement()); + return result; + } +} + /******************************** PragmaStatement ***************************/ PragmaStatement::PragmaStatement(Loc loc, Identifier *ident, Expressions *args, Statement *body) diff --git a/gcc/d/dmd/statement.h b/gcc/d/dmd/statement.h index fae0862..8f69383 100644 --- a/gcc/d/dmd/statement.h +++ b/gcc/d/dmd/statement.h @@ -232,15 +232,13 @@ public: class ForwardingStatement : public Statement { +public: ForwardingScopeDsymbol *sym; Statement *statement; + ForwardingStatement(Loc loc, ForwardingScopeDsymbol *sym, Statement *s); + ForwardingStatement(Loc loc, Statement *s); Statement *syntaxCopy(); - Statement *getRelatedLabeled(); - bool hasBreak(); - bool hasContinue(); - Statement *scopeCode(Scope *sc, Statement **sentry, Statement **sexception, Statement **sfinally); - Statement *last(); Statements *flatten(Scope *sc); ForwardingStatement *isForwardingStatement() { return this; } void accept(Visitor *v) { v->visit(this); } @@ -384,6 +382,7 @@ class StaticForeachStatement : public Statement public: StaticForeach *sfe; + StaticForeachStatement(Loc loc, StaticForeach *sfe); Statement *syntaxCopy(); Statements *flatten(Scope *sc); diff --git a/gcc/d/dmd/statementsem.c b/gcc/d/dmd/statementsem.c index cc2b63e..26e5950 100644 --- a/gcc/d/dmd/statementsem.c +++ b/gcc/d/dmd/statementsem.c @@ -13,6 +13,7 @@ #include "errors.h" #include "statement.h" +#include "attrib.h" #include "expression.h" #include "cond.h" #include "init.h" @@ -303,11 +304,10 @@ public: void visit(ScopeStatement *ss) { - ScopeDsymbol *sym; //printf("ScopeStatement::semantic(sc = %p)\n", sc); if (ss->statement) { - sym = new ScopeDsymbol(); + ScopeDsymbol *sym = new ScopeDsymbol(); sym->parent = sc->scopesym; sym->endlinnum = ss->endloc.linnum; sc = sc->push(sym); @@ -348,6 +348,22 @@ public: result = ss; } + void visit(ForwardingStatement *ss) + { + assert(ss->sym); + for (Scope *csc = sc; !ss->sym->forward; csc = csc->enclosing) + { + assert(csc); + ss->sym->forward = csc->scopesym; + } + sc = sc->push(ss->sym); + sc->sbreak = ss; + sc->scontinue = ss; + ss->statement = semantic(ss->statement, sc); + sc = sc->pop(); + result = ss->statement; + } + void visit(WhileStatement *ws) { /* Rewrite as a for(;condition;) loop @@ -478,6 +494,347 @@ public: result = fs; } + /*********************** + * Declares a unrolled `foreach` loop variable or a `static foreach` variable. + * + * Params: + * storageClass = The storage class of the variable. + * type = The declared type of the variable. + * ident = The name of the variable. + * e = The initializer of the variable (i.e. the current element of the looped over aggregate). + * t = The type of the initializer. + * Returns: + * `true` iff the declaration was successful. + */ + bool declareVariable(ForeachStatement *fs, Type *paramtype, TupleExp *te, + bool needExpansion, bool isStatic, Statements *statements, Dsymbols *declarations, + StorageClass storageClass, Type *type, Identifier *ident, Expression *e, Type *t) + { + Loc loc = fs->loc; + if (storageClass & (STCout | STClazy) || + (storageClass & STCref && !te)) + { + fs->error("no storage class for value %s", ident->toChars()); + return false; + } + Declaration *var; + if (e) + { + Type *tb = e->type->toBasetype(); + Dsymbol *ds = NULL; + if (!(storageClass & STCmanifest)) + { + if ((isStatic || tb->ty == Tfunction || tb->ty == Tsarray || storageClass & STCalias) && e->op == TOKvar) + ds = ((VarExp *)e)->var; + else if (e->op == TOKtemplate) + ds = ((TemplateExp *)e)->td; + else if (e->op == TOKscope) + ds = ((ScopeExp *)e)->sds; + else if (e->op == TOKfunction) + { + FuncExp *fe = (FuncExp *)e; + ds = fe->td ? (Dsymbol *)fe->td : fe->fd; + } + } + else if (storageClass & STCalias) + { + fs->error("foreach loop variable cannot be both enum and alias"); + return false; + } + + if (ds) + { + var = new AliasDeclaration(loc, ident, ds); + if (storageClass & STCref) + { + fs->error("symbol %s cannot be ref", ds->toChars()); + return false; + } + if (paramtype) + { + fs->error("cannot specify element type for symbol %s", ds->toChars()); + return false; + } + } + else if (e->op == TOKtype) + { + var = new AliasDeclaration(loc, ident, e->type); + if (paramtype) + { + fs->error("cannot specify element type for type %s", e->type->toChars()); + return false; + } + } + else + { + e = resolveProperties(sc, e); + type = e->type; + if (paramtype) + type = paramtype; + Initializer *ie = new ExpInitializer(Loc(), e); + VarDeclaration *v = new VarDeclaration(loc, type, ident, ie); + if (storageClass & STCref) + v->storage_class |= STCref | STCforeach; + if (isStatic || storageClass & STCmanifest || e->isConst() || + e->op == TOKstring || + e->op == TOKstructliteral || + e->op == TOKarrayliteral) + { + if (v->storage_class & STCref) + { + if (!isStatic || !needExpansion) + { + fs->error("constant value %s cannot be ref", ie->toChars()); + } + else + { + fs->error("constant value %s cannot be ref", ident->toChars()); + } + return false; + } + else + v->storage_class |= STCmanifest; + } + var = v; + } + } + else + { + var = new AliasDeclaration(loc, ident, t); + if (paramtype) + { + fs->error("cannot specify element type for symbol %s", fs->toChars()); + return false; + } + } + if (isStatic) + var->storage_class |= STClocal; + if (statements) + statements->push(new ExpStatement(loc, var)); + else if (declarations) + declarations->push(var); + else + assert(0); + return true; + } + + bool makeTupleForeachBody(ForeachStatement *fs, size_t k, + Type *paramtype, TupleExp *te, TypeTuple *tuple, + bool needExpansion, bool isStatic, bool isDecl, + Statements *statements, Dsymbols *declarations, Dsymbols *dbody) + { + Loc loc = fs->loc; + Expression *e = NULL; + Type *t = NULL; + if (te) + e = (*te->exps)[k]; + else + t = Parameter::getNth(tuple->arguments, k)->type; + Parameter *p = (*fs->parameters)[0]; + Statements *stmts = (isDecl) ? NULL : new Statements(); + Dsymbols *decls = (isDecl) ? new Dsymbols() : NULL; + + size_t dim = fs->parameters->dim; + if (!needExpansion && dim == 2) + { + // Declare key + if (p->storageClass & (STCout | STCref | STClazy)) + { + fs->error("no storage class for key %s", p->ident->toChars()); + return false; + } + if (isStatic) + { + if (!p->type) + { + p->type = Type::tsize_t; + } + } + p->type = p->type->semantic(loc, sc); + TY keyty = p->type->ty; + if (keyty != Tint32 && keyty != Tuns32) + { + if (global.params.isLP64) + { + if (keyty != Tint64 && keyty != Tuns64) + { + fs->error("foreach: key type must be int or uint, long or ulong, not %s", p->type->toChars()); + return false; + } + } + else + { + fs->error("foreach: key type must be int or uint, not %s", p->type->toChars()); + return false; + } + } + Initializer *ie = new ExpInitializer(Loc(), new IntegerExp(k)); + VarDeclaration *var = new VarDeclaration(loc, p->type, p->ident, ie); + var->storage_class |= STCmanifest; + if (isStatic) + var->storage_class |= STClocal; + if (!isDecl) + stmts->push(new ExpStatement(loc, var)); + else + decls->push(var); + p = (*fs->parameters)[1]; // value + } + + if (!isStatic || !needExpansion) + { + // Declare value + if (!declareVariable(fs, paramtype, te, needExpansion, isStatic, stmts, decls, + p->storageClass, p->type, p->ident, e, t)) + { + return false; + } + } + else + { + // expand tuples into multiple `static foreach` variables. + assert(e && !t); + Identifier *ident = Identifier::generateId("__value"); + declareVariable(fs, paramtype, te, needExpansion, isStatic, stmts, decls, + 0, e->type, ident, e, NULL); + Identifier *field = Identifier::idPool("tuple"); + Expression *access = new DotIdExp(loc, e, field); + access = semantic(access, sc); + if (!tuple) + return false; + //printf("%s\n", tuple->toChars()); + for (size_t l = 0; l < dim; l++) + { + Parameter *cp = (*fs->parameters)[l]; + Expression *init_ = new IndexExp(loc, access, new IntegerExp(loc, l, Type::tsize_t)); + init_ = semantic(init_, sc); + assert(init_->type); + declareVariable(fs, paramtype, te, needExpansion, isStatic, stmts, decls, + p->storageClass, init_->type, cp->ident, init_, NULL); + } + } + Statement *fwdstmt = NULL; + Dsymbol *fwddecl = NULL; + if (!isDecl) + { + if (fs->_body) + stmts->push(fs->_body->syntaxCopy()); + fwdstmt = new CompoundStatement(loc, stmts); + } + else + { + decls->append(Dsymbol::arraySyntaxCopy(dbody)); + } + if (!isStatic) + { + fwdstmt = new ScopeStatement(loc, fwdstmt, fs->endloc); + } + else if (!isDecl) + { + fwdstmt = new ForwardingStatement(loc, fwdstmt); + } + else + { + fwddecl = new ForwardingAttribDeclaration(decls); + } + + if (statements) + statements->push(fwdstmt); + else if (declarations) + declarations->push(fwddecl); + else + assert(0); + return true; + } + + /******************* + * Type check and unroll `foreach` over an expression tuple as well + * as `static foreach` statements and `static foreach` + * declarations. For `static foreach` statements and `static + * foreach` declarations, the visitor interface is used (and the + * result is written into the `result` field.) For `static + * foreach` declarations, the resulting Dsymbols* are returned + * directly. + * + * The unrolled body is wrapped into a + * - UnrolledLoopStatement, for `foreach` over an expression tuple. + * - ForwardingStatement, for `static foreach` statements. + * - ForwardingAttribDeclaration, for `static foreach` declarations. + * + * `static foreach` variables are declared as `STClocal`, such + * that they are inserted into the local symbol tables of the + * forwarding constructs instead of forwarded. For `static + * foreach` with multiple foreach loop variables whose aggregate + * has been lowered into a sequence of tuples, this function + * expands the tuples into multiple `STClocal` `static foreach` + * variables. + */ + bool makeTupleForeach(ForeachStatement *fs, bool needExpansion, bool isStatic, bool isDecl, + Statements *statements, Dsymbols *declarations, Dsymbols *dbody) + { + Loc loc = fs->loc; + size_t dim = fs->parameters->dim; + if (!needExpansion && (dim < 1 || dim > 2)) + { + fs->error("only one (value) or two (key,value) arguments for tuple foreach"); + return false; + } + + Type *paramtype = (*fs->parameters)[dim-1]->type; + if (paramtype) + { + paramtype = paramtype->semantic(loc, sc); + if (paramtype->ty == Terror) + return false; + } + + Type *tab = fs->aggr->type->toBasetype(); + TypeTuple *tuple = (TypeTuple *)tab; + //printf("aggr: op = %d, %s\n", fs->aggr->op, fs->aggr->toChars()); + size_t n; + TupleExp *te = NULL; + if (fs->aggr->op == TOKtuple) // expression tuple + { + te = (TupleExp *)fs->aggr; + n = te->exps->dim; + } + else if (fs->aggr->op == TOKtype) // type tuple + { + n = Parameter::dim(tuple->arguments); + } + else + assert(0); + for (size_t j = 0; j < n; j++) + { + size_t k = (fs->op == TOKforeach) ? j : n - 1 - j; + if (!makeTupleForeachBody(fs, k, paramtype, te, tuple, + needExpansion, isStatic, isDecl, + statements, declarations, dbody)) + return false; + } + return true; + } + + Dsymbols *makeTupleForeachStaticDecl(ForeachStatement *fs, Dsymbols *dbody, bool needExpansion) + { + assert(sc); + Dsymbols *declarations = new Dsymbols(); + if (!makeTupleForeach(fs, needExpansion, true, true, NULL, declarations, dbody)) + return NULL; + + return declarations; + } + + void makeTupleForeachStatic(ForeachStatement *fs, bool needExpansion) + { + Loc loc = fs->loc; + assert(sc); + Statements *statements = new Statements(); + if (!makeTupleForeach(fs, needExpansion, true, false, statements, NULL, NULL)) + return setError(); + + result = new CompoundStatement(loc, statements); + } + void visit(ForeachStatement *fs) { //printf("ForeachStatement::semantic() %p\n", fs); @@ -575,177 +932,22 @@ public: if (tab->ty == Ttuple) // don't generate new scope for tuple loops { - if (dim < 1 || dim > 2) - { - fs->error("only one (value) or two (key,value) arguments for tuple foreach"); + Statements *statements = new Statements(); + if (!makeTupleForeach(fs, false, false, false, statements, NULL, NULL)) return setError(); - } - Type *paramtype = (*fs->parameters)[dim-1]->type; - if (paramtype) - { - paramtype = paramtype->semantic(loc, sc); - if (paramtype->ty == Terror) - return setError(); - } - - TypeTuple *tuple = (TypeTuple *)tab; - Statements *statements = new Statements(); - //printf("aggr: op = %d, %s\n", fs->aggr->op, fs->aggr->toChars()); - size_t n; - TupleExp *te = NULL; - if (fs->aggr->op == TOKtuple) // expression tuple - { - te = (TupleExp *)fs->aggr; - n = te->exps->dim; - } - else if (fs->aggr->op == TOKtype) // type tuple + result = new UnrolledLoopStatement(loc, statements); + if (LabelStatement *ls = checkLabeledLoop(sc, fs)) + ls->gotoTarget = result; + if (fs->aggr->op == TOKtuple) { - n = Parameter::dim(tuple->arguments); + TupleExp *te = (TupleExp *)fs->aggr; + if (te->e0) + result = new CompoundStatement(loc, new ExpStatement(te->e0->loc, te->e0), result); } - else - assert(0); - for (size_t j = 0; j < n; j++) - { - size_t k = (fs->op == TOKforeach) ? j : n - 1 - j; - Expression *e = NULL; - Type *t = NULL; - if (te) - e = (*te->exps)[k]; - else - t = Parameter::getNth(tuple->arguments, k)->type; - Parameter *p = (*fs->parameters)[0]; - Statements *st = new Statements(); - - if (dim == 2) - { - // Declare key - if (p->storageClass & (STCout | STCref | STClazy)) - { - fs->error("no storage class for key %s", p->ident->toChars()); - return setError(); - } - p->type = p->type->semantic(loc, sc); - TY keyty = p->type->ty; - if (keyty != Tint32 && keyty != Tuns32) - { - if (global.params.isLP64) - { - if (keyty != Tint64 && keyty != Tuns64) - { - fs->error("foreach: key type must be int or uint, long or ulong, not %s", p->type->toChars()); - return setError(); - } - } - else - { - fs->error("foreach: key type must be int or uint, not %s", p->type->toChars()); - return setError(); - } - } - Initializer *ie = new ExpInitializer(Loc(), new IntegerExp(k)); - VarDeclaration *var = new VarDeclaration(loc, p->type, p->ident, ie); - var->storage_class |= STCmanifest; - st->push(new ExpStatement(loc, var)); - p = (*fs->parameters)[1]; // value - } - // Declare value - if (p->storageClass & (STCout | STClazy) || - (p->storageClass & STCref && !te)) - { - fs->error("no storage class for value %s", p->ident->toChars()); - return setError(); - } - Dsymbol *var; - if (te) - { - Type *tb = e->type->toBasetype(); - Dsymbol *ds = NULL; - if ((tb->ty == Tfunction || tb->ty == Tsarray) && e->op == TOKvar) - ds = ((VarExp *)e)->var; - else if (e->op == TOKtemplate) - ds = ((TemplateExp *)e)->td; - else if (e->op == TOKscope) - ds = ((ScopeExp *)e)->sds; - else if (e->op == TOKfunction) - { - FuncExp *fe = (FuncExp *)e; - ds = fe->td ? (Dsymbol *)fe->td : fe->fd; - } - - if (ds) - { - var = new AliasDeclaration(loc, p->ident, ds); - if (p->storageClass & STCref) - { - fs->error("symbol %s cannot be ref", s->toChars()); - return setError(); - } - if (paramtype) - { - fs->error("cannot specify element type for symbol %s", ds->toChars()); - return setError(); - } - } - else if (e->op == TOKtype) - { - var = new AliasDeclaration(loc, p->ident, e->type); - if (paramtype) - { - fs->error("cannot specify element type for type %s", e->type->toChars()); - return setError(); - } - } - else - { - p->type = e->type; - if (paramtype) - p->type = paramtype; - Initializer *ie = new ExpInitializer(Loc(), e); - VarDeclaration *v = new VarDeclaration(loc, p->type, p->ident, ie); - if (p->storageClass & STCref) - v->storage_class |= STCref | STCforeach; - if (e->isConst() || e->op == TOKstring || - e->op == TOKstructliteral || e->op == TOKarrayliteral) - { - if (v->storage_class & STCref) - { - fs->error("constant value %s cannot be ref", ie->toChars()); - return setError(); - } - else - v->storage_class |= STCmanifest; - } - var = v; - } - } - else - { - var = new AliasDeclaration(loc, p->ident, t); - if (paramtype) - { - fs->error("cannot specify element type for symbol %s", s->toChars()); - return setError(); - } - } - st->push(new ExpStatement(loc, var)); - - if (fs->_body) - st->push(fs->_body->syntaxCopy()); - s = new CompoundStatement(loc, st); - s = new ScopeStatement(loc, s, fs->endloc); - statements->push(s); - } - - s = new UnrolledLoopStatement(loc, statements); - if (LabelStatement *ls = checkLabeledLoop(sc, fs)) - ls->gotoTarget = s; - if (te && te->e0) - s = new CompoundStatement(loc, new ExpStatement(te->e0->loc, te->e0), s); if (vinit) - s = new CompoundStatement(loc, new ExpStatement(loc, vinit), s); - s = semantic(s, sc); - result = s; + result = new CompoundStatement(loc, new ExpStatement(loc, vinit), result); + result = semantic(result, sc); return; } @@ -756,6 +958,19 @@ public: sc2->noctor++; + for (size_t i = 0; i < dim; i++) + { + Parameter *p = (*fs->parameters)[i]; + if (p->storageClass & STCmanifest) + { + fs->error("cannot declare enum loop variables for non-unrolled foreach"); + } + if (p->storageClass & STCalias) + { + fs->error("cannot declare alias loop variables for non-unrolled foreach"); + } + } + switch (tab->ty) { case Tarray: @@ -1949,6 +2164,11 @@ public: if (ps->_body) { + if (ps->ident == Id::msg || ps->ident == Id::startaddress) + { + ps->error("`pragma(%s)` is missing a terminating `;`", ps->ident->toChars()); + return setError(); + } ps->_body = semantic(ps->_body, sc); } result = ps->_body; @@ -2862,6 +3082,10 @@ public: bs->error("break is not inside a loop or switch"); return setError(); } + else if (sc->sbreak->isForwardingStatement()) + { + bs->error("must use labeled `break` within `static foreach`"); + } result = bs; } @@ -2944,6 +3168,10 @@ public: cs->error("continue is not inside a loop"); return setError(); } + else if (sc->scontinue->isForwardingStatement()) + { + cs->error("must use labeled `continue` within `static foreach`"); + } result = cs; } @@ -3663,3 +3891,20 @@ Statement *semanticScope(Statement *s, Scope *sc, Statement *sbreak, Statement * scd->pop(); return s; } + +/******************* + * See StatementSemanticVisitor.makeTupleForeach. This is a simple + * wrapper that returns the generated statements/declarations. + */ +Statement *makeTupleForeachStatic(Scope *sc, ForeachStatement *fs, bool needExpansion) +{ + StatementSemanticVisitor v = StatementSemanticVisitor(sc); + v.makeTupleForeachStatic(fs, needExpansion); + return v.result; +} + +Dsymbols *makeTupleForeachStaticDecl(Scope *sc, ForeachStatement *fs, Dsymbols *dbody, bool needExpansion) +{ + StatementSemanticVisitor v = StatementSemanticVisitor(sc); + return v.makeTupleForeachStaticDecl(fs, dbody, needExpansion); +} diff --git a/gcc/d/dmd/traits.c b/gcc/d/dmd/traits.c index 2430383..04726c3 100644 --- a/gcc/d/dmd/traits.c +++ b/gcc/d/dmd/traits.c @@ -1182,16 +1182,27 @@ Expression *semanticTraits(TraitsExp *e, Scope *sc) { if (!sm) return 1; + + // skip local symbols, such as static foreach loop variables + if (Declaration *decl = sm->isDeclaration()) + { + if (decl->storage_class & STClocal) + { + return 0; + } + } + //printf("\t[%i] %s %s\n", i, sm->kind(), sm->toChars()); if (sm->ident) { - const char *idx = sm->ident->toChars(); - if (idx[0] == '_' && idx[1] == '_' && - sm->ident != Id::ctor && - sm->ident != Id::dtor && - sm->ident != Id::__xdtor && - sm->ident != Id::postblit && - sm->ident != Id::__xpostblit) + // https://issues.dlang.org/show_bug.cgi?id=10096 + // https://issues.dlang.org/show_bug.cgi?id=10100 + // Skip over internal members in __traits(allMembers) + if ((sm->isCtorDeclaration() && sm->ident != Id::ctor) || + (sm->isDtorDeclaration() && sm->ident != Id::dtor) || + (sm->isPostBlitDeclaration() && sm->ident != Id::postblit) || + sm->isInvariantDeclaration() || + sm->isUnitTestDeclaration()) { return 0; } @@ -1352,6 +1363,13 @@ Expression *semanticTraits(TraitsExp *e, Scope *sc) RootObject *o1 = (*e->args)[0]; RootObject *o2 = (*e->args)[1]; + + // issue 12001, allow isSame, , + Type *t1 = isType(o1); + Type *t2 = isType(o2); + if (t1 && t2 && t1->equals(t2)) + return True(e); + Dsymbol *s1 = getDsymbol(o1); Dsymbol *s2 = getDsymbol(o2); //printf("isSame: %s, %s\n", o1->toChars(), o2->toChars()); @@ -1411,7 +1429,7 @@ Expression *semanticTraits(TraitsExp *e, Scope *sc) TupleExp *te= new TupleExp(e->loc, exps); return semantic(te, sc); } - else if(e->ident == Id::getVirtualIndex) + else if (e->ident == Id::getVirtualIndex) { if (dim != 1) return dimError(e, 1, dim); diff --git a/gcc/d/dmd/visitor.h b/gcc/d/dmd/visitor.h index 4c92670..df549da2 100644 --- a/gcc/d/dmd/visitor.h +++ b/gcc/d/dmd/visitor.h @@ -81,6 +81,7 @@ class TypeClass; class TypeTuple; class TypeSlice; class TypeNull; +class TypeTraits; class Dsymbol; @@ -107,6 +108,7 @@ class StaticIfDeclaration; class CompileDeclaration; class StaticForeachDeclaration; class UserAttributeDeclaration; +class ForwardingAttribDeclaration; class ScopeDsymbol; class TemplateDeclaration; @@ -373,6 +375,7 @@ public: virtual void visit(TypeTuple *t) { visit((Type *)t); } virtual void visit(TypeSlice *t) { visit((TypeNext *)t); } virtual void visit(TypeNull *t) { visit((Type *)t); } + virtual void visit(TypeTraits *t) { visit((Type *)t); } virtual void visit(Dsymbol *) { assert(0); } @@ -399,6 +402,7 @@ public: virtual void visit(StaticForeachDeclaration *s) { visit((AttribDeclaration *)s); } virtual void visit(CompileDeclaration *s) { visit((AttribDeclaration *)s); } virtual void visit(UserAttributeDeclaration *s) { visit((AttribDeclaration *)s); } + virtual void visit(ForwardingAttribDeclaration *s) { visit((AttribDeclaration *)s); } virtual void visit(ScopeDsymbol *s) { visit((Dsymbol *)s); } virtual void visit(TemplateDeclaration *s) { visit((ScopeDsymbol *)s); } diff --git a/gcc/testsuite/gdc.test/compilable/b12001.d b/gcc/testsuite/gdc.test/compilable/b12001.d new file mode 100644 index 0000000..f67c895 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/b12001.d @@ -0,0 +1,9 @@ +void main() +{ + static assert(__traits(isSame, int, int)); + static assert(__traits(isSame, int[][], int[][])); + static assert(__traits(isSame, bool*, bool*)); + + static assert(!__traits(isSame, bool*, bool[])); + static assert(!__traits(isSame, float, double)); +} diff --git a/gcc/testsuite/gdc.test/compilable/json.d b/gcc/testsuite/gdc.test/compilable/json.d index b5a560d..e2b0860 100644 --- a/gcc/testsuite/gdc.test/compilable/json.d +++ b/gcc/testsuite/gdc.test/compilable/json.d @@ -111,3 +111,24 @@ enum Numbers } template IncludeConstraint(T) if (T == string) {} + +static foreach(enum i; 0..3) +{ + mixin("int a" ~ i.stringof ~ " = 1;"); +} + +alias Seq(T...) = T; + +static foreach(int i, alias a; Seq!(a0, a1, a2)) +{ + mixin("alias b" ~ i.stringof ~ " = a;"); +} + +mixin template test18211(int n) +{ + static foreach (i; 0 .. n>10 ? 10 : n) + { + mixin("enum x" ~ cast(char)('0' + i)); + } + static if (true) {} +} diff --git a/gcc/testsuite/gdc.test/compilable/staticforeach.d b/gcc/testsuite/gdc.test/compilable/staticforeach.d new file mode 100644 index 0000000..48d06b4 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/staticforeach.d @@ -0,0 +1,842 @@ +// REQUIRED_ARGS: -o- +// PERMUTE_ARGS: +// EXTRA_FILES: imports/imp12242a1.d imports/imp12242a2.d +/* +TEST_OUTPUT: +--- +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +S(1, 2, 3, [0, 1, 2]) +x0: 1 +x1: 2 +x2: 3 +a: [0, 1, 2] +(int[], char[], bool[], Object[]) +[0, 0] +x0: int +x1: double +x2: char +test(0)→ 0 +test(1)→ 1 +test(2)→ 2 +test(3)→ 3 +test(4)→ 4 +test(5)→ 5 +test(6)→ 6 +test(7)→ 7 +test(8)→ 8 +test(9)→ 9 +test(10)→ -1 +test(11)→ -1 +test(12)→ -1 +test(13)→ -1 +test(14)→ -1 +1 +[1, 2, 3] +2 +[1, 2, 3] +3 +[1, 2, 3] +0 1 +1 2 +2 3 +1 +3 +4 +object +Tuple +tuple +main +front +popFront +empty +back +popBack +Iota +iota +map +to +text +all +any +join +S +s +Seq +Overloads +Parameters +forward +foo +A +B +C +D +E +Types +Visitor +testVisitor +staticMap +arrayOf +StaticForeachLoopVariable +StaticForeachScopeExit +StaticForeachReverseHiding +UnrolledForeachReverse +StaticForeachReverse +StaticForeachByAliasDefault +NestedStaticForeach +TestAliasOutsideFunctionScope +OpApplyMultipleStaticForeach +OpApplyMultipleStaticForeachLowered +RangeStaticForeach +OpApplySingleStaticForeach +TypeStaticForeach +AliasForeach +EnumForeach +TestUninterpretable +SeqForeachConstant +SeqForeachBreakContinue +TestStaticForeach +testtest +fun +testEmpty +bug17660 +breakContinueBan +MixinTemplate +testToStatement +bug17688 +T +foo2 +T2 +1 2 '3' +2 3 '4' +0 1 +1 2 +2 3 +--- +*/ + +module staticforeach; + +struct Tuple(T...){ + T expand; + alias expand this; +} +auto tuple(T...)(T t){ return Tuple!T(t); } + +/+struct TupleStaticForeach{ // should work, but is not the fault of the static foreach implementation. + //pragma(msg, [tuple(1,"2",'3'),tuple(2,"3",'4')].map!((x)=>x)); + static foreach(a,b,c;[tuple(1,"2",'3'),tuple(2,"3",'4')].map!((x)=>x)){ + pragma(msg,a," ",b," ",c); + } +}+/ + +void main(){ + static foreach(a,b,c;[tuple(1,"2",'3'),tuple(2,"3",'4')].map!((x)=>x)){ + pragma(msg, a," ",b," ",c); + } + static struct S{ + // (aggregate scope, forward referencing possible) + static assert(stripA("123")==1); + static assert(stripA([1],2)==2); + static foreach(i;0..2){ + mixin(`import imports.imp12242a`~text(i+1)~`;`); + static assert(stripA("123")==1); + static assert(stripA([1],2)==2); + } + static assert(stripA("123")==1); + static assert(stripA([1],2)==2); + } + static foreach(i;0..2){ + // (function scope, no forward referencing) + mixin(`import imports.imp12242a`~text(i+1)~`;`); + static assert(stripA("123")==1); + static if(i) static assert(stripA([1],2)==2); + } + static assert(stripA("123")==1); + static assert(stripA([1],2)==2); +} + +auto front(T)(T[] a){ return a[0]; } +auto popFront(T)(ref T[] a){ a=a[1..$]; } +auto empty(T)(T[] a){ return !a.length; } +auto back(T)(T[] a){ return a[$-1]; } +auto popBack(T)(ref T[] a){ a=a[0..$-1]; } + +struct Iota(T){ + T s,e; + @property bool empty(){ return s>=e; } + @property T front(){ return s; } + @property T back(){ return cast(T)(e-1); } + void popFront(){ s++; } + void popBack(){ e--; } +} +auto iota(T)(T s, T e){ return Iota!T(s,e); } + +template map(alias a){ + struct Map(R){ + R r; + @property front(){ return a(r.front); } + @property back(){ return a(r.back); } + @property bool empty(){ return r.empty; } + void popFront(){ r.popFront(); } + void popBack(){ r.popBack(); } + } + auto map(R)(R r){ return Map!R(r); } +} + +template to(T:string){ + string to(S)(S x)if(is(S:int)||is(S:size_t)||is(S:char)){ + static if(is(S==char)) return cast(string)[x]; + if(x<0) return "-"~to(-1 * x); + if(x==0) return "0"; + return (x>=10?to(x/10):"")~cast(char)(x%10+'0'); + } +} +auto text(T)(T arg){ return to!string(arg); }; + +template all(alias a){ + bool all(R)(R r){ + foreach(x;r) if(!a(x)) return false; + return true; + } +} +template any(alias a){ + bool any(R)(R r){ + foreach(x;r) if(a(x)) return true; + return false; + } +} +auto join(R)(R r,string sep=""){ + string a; + int first=0; + foreach(x;r){ + if(first++) a~=sep; + a~=x; + } + return a; +} + +static foreach_reverse(x;iota(0,10).map!(to!string)){ + pragma(msg, x); +} + +// create struct members iteratively +struct S{ + static foreach(i;a){ + mixin("int x"~to!string(i)~";"); + } + immutable int[] a = [0,1,2]; +} +enum s=S(1,2,3); +pragma(msg, s); + +// loop over struct members +static foreach(member;__traits(allMembers,S)){ + pragma(msg, member,": ",mixin("s."~member)); +} + +// print prime numbers using overload sets as state variables. +/+ +static assert(is(typeof(bad57))); +static assert(!is(typeof(bad53))); + +static foreach(x;iota(2,100)){ + static foreach(y;iota(2,x)){ + static if(!(x%y)){ + mixin("void bad"~to!string(x)~"();"); + } + } + static if(!is(typeof(mixin("bad"~to!string(x))))){ + static assert(iota(2,x).all!(y=>!!(x%y))); + pragma(msg, x); + }else{ + static assert(iota(2,x).any!(y=>!(x%y))); + } +} ++/ + + +alias Seq(T...)=T; + +alias Overloads(alias a) = Seq!(__traits(getOverloads, __traits(parent, a), __traits(identifier, a))); + +template Parameters(alias f){ + static if(is(typeof(f) P == function)) alias Parameters=P; +} + +template forward(alias a){ + enum x=2; + static foreach(f;Overloads!a){ + auto ref forward(Parameters!f args){ + return f(args); + } + } + enum y=3; +} + +int foo(int x){ return x; } +string foo(string x){ return x; } + +static assert(forward!foo(2)==2 && forward!foo("hi") == "hi"); + + +// simple boilerplate-free visitor pattern +static foreach(char T;'A'..'F'){ + mixin("class "~T~q{{ + void accept(Visitor v){ + return v.visit(this); + } + }}); +} +alias Types = Seq!(mixin("Seq!("~iota('A','F').map!(to!string).join(", ")~")")); +abstract class Visitor{ + static foreach(T;Types){ + abstract void visit(T); + } +} + +string testVisitor(){ + string r; + void writeln(T...)(T args){ + static foreach(x;args) r~=x; + r~='\n'; + } + class Visitor: .Visitor{ + static foreach(T;Types){ + override void visit(T){ + writeln("visited: ",T.stringof); + } + } + } + void main(){ + auto v=new Visitor; + static foreach(T;Types){ + v.visit(new T); + } + } + main(); + return r; +} +static assert(testVisitor()=="visited: A +visited: B +visited: C +visited: D +visited: E +"); + +// iterative computation over AliasSeq: +template staticMap(alias F,T...){ + alias state0=Seq!(); + static foreach(i,A;T){ + mixin("alias state"~to!string(i+1)~" = Seq!(state"~to!string(i)~",F!A);"); + } + alias staticMap = Seq!(mixin("state"~to!string(T.length))); +} + +alias arrayOf(T)=T[]; +static assert(is(staticMap!(arrayOf,int,char,bool,Object)==Seq!(int[], char[], bool[], Object[]))); +pragma(msg, staticMap!(arrayOf,int,char,bool,Object)); + + +struct StaticForeachLoopVariable{ + int x; + static foreach(i;0..1){ + mixin("enum x"~text(i)~" = i;"); + } + int y; + static assert(__traits(allMembers, StaticForeachLoopVariable).length==3); + static assert(!is(typeof(StaticForeachLoopVariable.i))); + static assert(!is(typeof(__traits(getMember, StaticForeachLoopVariable, "i")))); +} + +struct StaticForeachScopeExit{ +static: + int[] test(){ + int[] r; + scope(exit) r ~= 1234; + { + static foreach(i;0..5){ + scope(exit) r ~= i; + } + r ~= 5; + } + return r; + } + static assert(test()==[5,4,3,2,1,0]); +} + +struct StaticForeachReverseHiding{ + static foreach(i;[0]){ + enum i = 1; // TODO: disallow? + static assert(i==0); + } +} + +struct UnrolledForeachReverse{ +static: + alias Seq(T...)=T; + int[] test(){ + int[] r; + foreach_reverse(i;Seq!(0,1,2,3)){ + r~=i; + } + return r; + } + static assert(test()==[3,2,1,0]); +} + +struct StaticForeachReverse{ +static: + alias Seq(T...)=T; + int[] test(){ + int[] r; + static foreach_reverse(i;0..4){ + r~=i; + } + return r; + } + static assert(test()==[3,2,1,0]); + + int[] test2(){ + int[] r; + static foreach_reverse(i;[0,1,2,3]){ + r~=i; + } + return r; + } + static assert(test2()==[3,2,1,0]); + + int[] test3(){ + static struct S{ + int opApplyReverse(scope int delegate(int) dg){ + foreach_reverse(i;0..4) if(auto r=dg(i)) return r; + return 0; + } + } + int[] r; + static foreach_reverse(i;S()){ + r~=i; + } + return r; + } + static assert(test3()==[3,2,1,0]); + + int[] test4(){ + int[] r; + static foreach_reverse(i;Seq!(0,1,2,3)){ + r~=i; + } + return r; + } + static assert(test()==[3,2,1,0]); +} + +struct StaticForeachByAliasDefault{ +static: + alias Seq(T...)=T; + + int[] test(){ + int a,b,c; + static foreach(i,x;Seq!(a,b,c)) x=i; + return [a,b,c]; + } + static assert(test()==[0,1,2]); + + int[] test2(){ + int x=0; + int foo(){ return ++x; } + static foreach(y;Seq!foo) + return [y,y,y]; + } + static assert(test2()==[1,2,3]); + + void test3(){ + int x=0; + int foo(){ return ++x; } + static assert(!is(typeof({ + static foreach(enum y;Seq!foo) + return [y,y,y]; + }))); + } +} + +struct NestedStaticForeach{ + static: + static foreach(i,name;["a"]){ + static foreach(j,name2;["d"]){ + mixin("enum int[] "~name~name2~"=[i, j];"); + } + } + pragma(msg, ad); +} + +struct TestAliasOutsideFunctionScope{ +static: + alias Seq(T...)=T; + int a; + static foreach(alias x;Seq!(a)){ + } +} + +struct OpApplyMultipleStaticForeach{ +static: + struct OpApply{ + int opApply(scope int delegate(int,int) dg){ + foreach(i;0..10) if(auto r=dg(i,i*i)) return r; + return 0; + } + } + static foreach(a,b;OpApply()){ + mixin(`enum x`~cast(char)('0'+a)~"=b;"); + } + static foreach(i;0..10){ + static assert(mixin(`x`~cast(char)('0'+i))==i*i); + } +} + + +struct OpApplyMultipleStaticForeachLowered{ +static: + struct OpApply{ + int opApply(scope int delegate(int,int) dg){ + foreach(i;0..10) if(auto r=dg(i,i*i)) return r; + return 0; + } + } + static foreach(x;{ + static struct S(T...){ this(T k){ this.x=k; } T x; } + static s(T...)(T a){ return S!T(a); } + typeof({ foreach(a,b;OpApply()){ return s(a,b); } assert(0);}())[] r; + foreach(a,b;OpApply()) r~=s(a,b); + return r; + }()){ + mixin(`enum x`~cast(char)('0'+x.x[0])~"=x.x[1];"); + } + static foreach(i;0..10){ + static assert(mixin(`x`~cast(char)('0'+i))==i*i); + } +} + +struct RangeStaticForeach{ + static: + struct Range{ + int x=0; + this(int x){ this.x=x; } + @property int front(){ return x; } + void popFront(){ x += 2; } + @property bool empty(){ return x>=10; } + } + static foreach(i;Range()){ + mixin(`enum x`~cast(char)('0'+i)~"=i;"); + } + static foreach(i;0..5){ + static assert(mixin(`x`~cast(char)('0'+2*i))==2*i); + } + static assert(!is(typeof({ + struct S{ + static foreach(i,k;Range()){} + } + }))); + static foreach(k;Range()){} // ok +} + +struct OpApplySingleStaticForeach{ + static: + struct OpApply{ + int opApply(scope int delegate(int) dg){ + foreach(i;0..10) if(auto r=dg(i)) return r; + return 0; + } + } + static foreach(b;OpApply()){ + mixin(`enum x`~cast(char)('0'+b)~"=b;"); + } + static foreach(i;0..10){ + static assert(mixin(`x`~cast(char)('0'+i))==i); + } +} + +struct TypeStaticForeach{ +static: + alias Seq(T...)=T; + static foreach(i,alias T;Seq!(int,double,char)){ + mixin(`T x`~cast(char)('0'+i)~";"); + } + pragma(msg, "x0: ",typeof(x0)); + pragma(msg, "x1: ",typeof(x1)); + pragma(msg, "x2: ",typeof(x2)); + static assert(is(typeof(x0)==int)); + static assert(is(typeof(x1)==double)); + static assert(is(typeof(x2)==char)); +} + +struct AliasForeach{ +static: + alias Seq(T...)=T; + int[] test(){ + int a,b,c; + static foreach(x;Seq!(a,b,c,2)){ + static if(is(typeof({x=2;}))) x=2; + } + int x,y,z; + static foreach(alias k;Seq!(x,y,z,2)){ + static if(is(typeof({k=2;}))) k=2; + } + int j,k,l; + static assert(!is(typeof({ + static foreach(ref x;Seq!(j,k,l,2)){ + static if(is(typeof({x=2;}))) x=2; + } + }))); + return [x,y,z]; + } + static assert(test()==[2,2,2]); +} + +struct EnumForeach{ +static: + alias Seq(T...)=T; + int a=1; + int fun(){ return 1; } + int gun(){ return 2; } + int hun(){ return 3;} + auto test(){ + static foreach(i,enum x;Seq!(fun,gun,hun)){ + static assert(i+1==x); + } + foreach(i,enum x;Seq!(fun,gun,hun)){ + static assert(i+1==x); + } + } +} + +struct TestUninterpretable{ +static: + alias Seq(T...)=T; + auto test(){ + int k; + static assert(!is(typeof({ + static foreach(x;[k]){} + }))); + static assert(!is(typeof({ + foreach(enum x;[1,2,3]){} + }))); + static assert(!is(typeof({ + foreach(alias x;[1,2,3]){} + }))); + foreach(enum x;Seq!(1,2,3)){} // ok + foreach(alias x;Seq!(1,2,3)){} // ok + static foreach(enum x;[1,2,3]){} // ok + static foreach(alias x;[1,2,3]){} // ok + static assert(!is(typeof({ + static foreach(enum alias x;[1,2,3]){} + }))); + int x; + static foreach(i;Seq!x){ } // ok + static foreach(i,j;Seq!(1,2,x)){ } // ok + static assert(!is(typeof({ + static foreach(ref x;[1,2,3]){} + }))); + } +} + +struct SeqForeachConstant{ +static: + alias Seq(T...)=T; + static assert(!is(typeof({ + foreach(x;Seq!1) x=2; + }))); + int test2(){ + int r=0; + foreach(x;Seq!(1,2,3)){ + enum k=x; + r+=k; + } + return r; + } + static assert(test2()==6); +} + +struct SeqForeachBreakContinue{ +static: + alias Seq(T...)=T; + int[] test(){ + int[] r; + foreach(i;Seq!(0,1,2,3,4,5)){ + if(i==2) continue; + if(i==4) break; + r~=i; + } + return r; + } + static assert(test()==[0,1,3]); +} + +struct TestStaticForeach{ +static: + int test(int x){ + int r=0; + label: switch(x){ + static foreach(i;0..10){ + case i: r=i; break label; // TODO: remove label when restriction is lifted + } + default: r=-1; break label; + } + return r; + } + static foreach(i;0..15){ + pragma(msg, "test(",i,")→ ",test(i)); + static assert(test(i)==(i<10?i:-1)); + } + + enum x=[1,2,3]; + + static foreach(i;x){ + mixin("enum x"~cast(char)('0'+i)~"="~cast(char)('0'+i)~";"); + } + + static foreach(i;x){ + pragma(msg, mixin("x"~cast(char)('0'+i))); + pragma(msg,x); + } + + int[] noBreakNoContinue(){ + int[] r; + static foreach(i;0..1){ + // if(i==3) continue; // TODO: error? + // if(i==7) break; // TODO: error? + r~=i; + } + return r; + } + + mixin("enum k=3;"); +} + +static foreach(i,j;[1,2,3]){ + pragma(msg, int(i)," ",j); +} + +void testtest(){ + static foreach(i,v;[1,2,3]){ + pragma(msg, int(i)," ",v); + static assert(i+1 == v); + } +} + + +static foreach(i;Seq!(1,2,3,4,int)){ + static if(!is(i) && i!=2){ + pragma(msg, i); + } +} + +int fun(int x){ + int r=0; + label: switch(x){ + static foreach(i;Seq!(0,1,2,3,4,5,6)){ + static if (i < 5) + case i: r=i; break label; // TODO: remove label when restriction is lifted + } + default: r=-1; break label; + } + return r; +} + +static foreach(i;0..10) static assert(fun(i)==(i<5?i:-1)); + +static foreach(i;0..0) { } +void testEmpty(){ + static foreach(i;0..0) { } +} + +auto bug17660(){ + int x; + static foreach (i; 0 .. 1) { return 3; } + return x; +} +static assert(bug17660()==3); + +int breakContinueBan(){ + static assert(!is(typeof({ + for(;;){ + static foreach(i;0..1){ + break; + } + } + }))); + static assert(!is(typeof({ + for(;;){ + static foreach(i;0..1){ + continue; + } + } + }))); + Louter1: for(;;){ + static foreach(i;0..1){ + break Louter1; + } + } + Louter2: foreach(i;0..10){ + static foreach(j;0..1){ + continue Louter2; + } + return 0; + } + static foreach(i;0..1){ + for(;;){ break; } // ok + } + return 1; +} +static assert(breakContinueBan()==1); + +mixin template MixinTemplate(){ + static foreach(i;0..2){ + mixin(`enum x`~cast(char)('0'+i)~"=i;"); + } + static foreach(i;[0,1]){ + mixin(`enum y`~cast(char)('0'+i)~"=i;"); + } +} +void testToStatement(){ + mixin MixinTemplate; + static assert(x0==0 && x1==1); + static assert(y0==0 && y1==1); +} + +void bug17688(){ + final switch(1) static foreach(x;0..1){ int y=3; case 1: return; } + static assert(!is(typeof(y))); +} + +struct T{ enum n = 1; } +T foo(T v)@nogc{ + static foreach(x;0..v.n){ } + return T.init; +} +T foo2(T v)@nogc{ + static foreach(_;0..typeof(return).n){ } + return T.init; +} + +//https://issues.dlang.org/show_bug.cgi?id=18698 + +static foreach(m; __traits(allMembers, staticforeach)) +{ + pragma(msg, m); +} + +//https://issues.dlang.org/show_bug.cgi?id=20072 +struct T2{ + static foreach(i;0..1) + struct S{} +} +static assert(is(__traits(parent,T2.S)==T2)); diff --git a/gcc/testsuite/gdc.test/compilable/test11169.d b/gcc/testsuite/gdc.test/compilable/test11169.d index 10a3df2..79863e1 100644 --- a/gcc/testsuite/gdc.test/compilable/test11169.d +++ b/gcc/testsuite/gdc.test/compilable/test11169.d @@ -43,3 +43,18 @@ void main() static assert(!__traits(compiles, { auto b = new B2(); })); static assert(!__traits(compiles, { auto b = new B3(); })); } + +class B : A +{ + // __traits(isAbstractClass) is not usable in static if condition. + static assert (!__traits(isAbstractClass, typeof(this))); + + override void foo() + { + } +} + +void main2() +{ + B b = new B(); +} diff --git a/gcc/testsuite/gdc.test/compilable/test17819.d b/gcc/testsuite/gdc.test/compilable/test17819.d new file mode 100644 index 0000000..f1266a0 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test17819.d @@ -0,0 +1,17 @@ +static if (__traits(allMembers, __traits(parent,{}))[0]=="object") { + enum test = 0; +} + +static foreach (m; __traits(allMembers, __traits(parent,{}))) { + mixin("enum new"~m~"=`"~m~"`;"); +} + +static assert([__traits(allMembers, __traits(parent,{}))] == ["object", "test", "newobject", "newWorld", "newBuildStuff", "World", "BuildStuff"]); + +struct World { + mixin BuildStuff; +} + +template BuildStuff() { + static foreach(elem; __traits(allMembers, typeof(this))) {} +} diff --git a/gcc/testsuite/gdc.test/compilable/test18871.d b/gcc/testsuite/gdc.test/compilable/test18871.d new file mode 100644 index 0000000..44486f2 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test18871.d @@ -0,0 +1,15 @@ +// https://issues.dlang.org/show_bug.cgi?id=18871 +// and https://issues.dlang.org/show_bug.cgi?id=18819 + +struct Problem +{ + ~this() {} +} +struct S +{ + Problem[1] payload; +} +enum theTemplateB = { + static foreach (e; S.init.tupleof) {} + return true; +}(); diff --git a/gcc/testsuite/gdc.test/compilable/test7815.d b/gcc/testsuite/gdc.test/compilable/test7815.d new file mode 100644 index 0000000..405d9fc --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test7815.d @@ -0,0 +1,65 @@ +// REQUIRED_ARGS: -o- +/* +TEST_OUTPUT: +--- +--- +*/ + +mixin template Helpers() +{ + static if (is(Flags!Move)) + { + Flags!Move flags; + } + else + { + pragma(msg, "X: ", __traits(derivedMembers, Flags!Move)); + } +} + +template Flags(T) +{ + mixin({ + int defs = 1; + foreach (name; __traits(derivedMembers, Move)) + { + defs++; + } + if (defs) + { + return "struct Flags { bool x; }"; + } + else + { + return ""; + } + }()); +} + +struct Move +{ + int a; + mixin Helpers!(); +} + +enum a7815 = Move.init.flags; + +/+ +This originally was an invalid case: +When the Move struct member is analyzed: +1. mixin Helpers!() is instantiated. +2. In Helpers!(), static if and its condition is(Flags!Move)) evaluated. +3. In Flags!Move, string mixin evaluates and CTFE lambda. +4. __traits(derivedMembers, Move) tries to see the member of Move. + 4a. mixin Helpers!() member is analyzed. + 4b. `static if (is(Flags!Move))` in Helpers!() is evaluated + 4c. The Flags!Move instantiation is already in progress, so it cannot be resolved. + 4d. `static if` fails because Flags!Move cannot be determined as a type. +5. __traits(derivedMembers, Move) returns a 1-length tuple("a"). +6. The lambda in Flags!Move returns a string "struct Flags {...}", then + Flags!Move is instantiated to a new struct Flags. +7. Finally Move struct does not have flags member, then the `enum a7815` + definition will fail in its initializer. + +Now, static if will behave like a string mixin: it is invisible during its own expansion. ++/ diff --git a/gcc/testsuite/gdc.test/compilable/test7886.d b/gcc/testsuite/gdc.test/compilable/test7886.d new file mode 100644 index 0000000..fd3ade4 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test7886.d @@ -0,0 +1,5 @@ +// https://issues.dlang.org/show_bug.cgi?id=7886 + +struct A { + static assert (__traits(derivedMembers, A).length == 0); +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/e7804_1.d b/gcc/testsuite/gdc.test/fail_compilation/e7804_1.d new file mode 100644 index 0000000..38c25fb --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/e7804_1.d @@ -0,0 +1,11 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/e7804_1.d(10): Error: trait `farfelu` is either invalid or not supported as type +fail_compilation/e7804_1.d(11): Error: trait `farfelu` is either invalid or not supported in alias +--- +*/ +module e7804_1; + +__traits(farfelu, Aggr, "member") a; +alias foo = __traits(farfelu, Aggr, "member"); diff --git a/gcc/testsuite/gdc.test/fail_compilation/e7804_2.d b/gcc/testsuite/gdc.test/fail_compilation/e7804_2.d new file mode 100644 index 0000000..ef9b784 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/e7804_2.d @@ -0,0 +1,19 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/e7804_2.d(17): Error: `__traits(getMember, Foo, "func")` does not give a valid type +--- +*/ + +module e7804_2; + +class Foo +{ + void func(){} +} + +void test() +{ + __traits(getMember, Foo, "func") var; + auto a = cast(__traits(getMember, Foo, "func")) 0; +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail11169.d b/gcc/testsuite/gdc.test/fail_compilation/fail11169.d deleted file mode 100644 index e6ab4a6..0000000 --- a/gcc/testsuite/gdc.test/fail_compilation/fail11169.d +++ /dev/null @@ -1,28 +0,0 @@ -/* -TEST_OUTPUT: ---- -fail_compilation/fail11169.d(16): Error: error evaluating static if expression ---- -*/ - -class A -{ - abstract void foo(); -} - -class B : A -{ - // __traits(isAbstractClass) is not usable in static if condition. - static if (__traits(isAbstractClass, typeof(this))) - { - } - - override void foo() - { - } -} - -void main() -{ - B b = new B(); -} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail19182.d b/gcc/testsuite/gdc.test/fail_compilation/fail19182.d new file mode 100644 index 0000000..388c460 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail19182.d @@ -0,0 +1,18 @@ +// REQUIRED_ARGS: -c +/* +TEST_OUTPUT: +--- +gigi +fail_compilation/fail19182.d(12): Error: `pragma(msg)` is missing a terminating `;` +--- +*/ + +void foo() +{ + pragma(msg, "gigi") // Here + static foreach (e; []) + { + pragma(msg, "lili"); + } + +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail19336.d b/gcc/testsuite/gdc.test/fail_compilation/fail19336.d new file mode 100644 index 0000000..fc15be5 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail19336.d @@ -0,0 +1,17 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/fail19336.d(14): Error: template instance `Template!()` template `Template` is not defined +fail_compilation/fail19336.d(14): Error: circular reference to `fail19336.Foo.a` +fail_compilation/fail19336.d(17): Error: circular reference to `fail19336.b` +--- +*/ + +// https://issues.dlang.org/show_bug.cgi?id=19336 + +struct Foo +{ + Template!() a(a.x); +} + +int b(b.x); diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail19520.d b/gcc/testsuite/gdc.test/fail_compilation/fail19520.d new file mode 100644 index 0000000..305e055 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail19520.d @@ -0,0 +1,21 @@ +/* https://issues.dlang.org/show_bug.cgi?id=19520 +TEST_OUTPUT: +--- +fail_compilation/fail19520.d(17): Error: incompatible types for `(Empty) is (Empty)`: cannot use `is` with types +fail_compilation/fail19520.d(17): while evaluating: `static assert((Empty) is (Empty))` +fail_compilation/fail19520.d(18): Error: incompatible types for `(WithSym) is (WithSym)`: cannot use `is` with types +fail_compilation/fail19520.d(18): while evaluating: `static assert((WithSym) is (WithSym))` +fail_compilation/fail19520.d(19): Error: incompatible types for `(Empty) is (Empty)`: cannot use `is` with types +fail_compilation/fail19520.d(20): Error: incompatible types for `(WithSym) is (WithSym)`: cannot use `is` with types +--- +*/ +struct Empty { } +struct WithSym { int i; } + +void test() +{ + static assert(Empty is Empty); + static assert(WithSym is WithSym); + assert(Empty is Empty); + assert(WithSym is WithSym); +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail2195.d b/gcc/testsuite/gdc.test/fail_compilation/fail2195.d new file mode 100644 index 0000000..b6d5304 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail2195.d @@ -0,0 +1,18 @@ +// https://issues.dlang.org/show_bug.cgi?id=2195 +// REQUIRED_ARGS: -de +/* +TEST_OUTPUT: +--- +fail_compilation/fail2195.d(16): Deprecation: variable `variable` is shadowing variable `fail2195.main.variable`. Rename the `foreach` variable. +--- +*/ + +void main() +{ + int[int] arr; + int variable; + foreach (i, j; arr) + { + int variable; // shadowing is disallowed but not detected + } +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail7815.d b/gcc/testsuite/gdc.test/fail_compilation/fail7815.d deleted file mode 100644 index ceb5923..0000000 --- a/gcc/testsuite/gdc.test/fail_compilation/fail7815.d +++ /dev/null @@ -1,65 +0,0 @@ -// REQUIRED_ARGS: -o- -/* -TEST_OUTPUT: ---- -X: tuple("x") -fail_compilation/fail7815.d(47): Error: no property 'flags' for type 'Move' ---- -*/ - -mixin template Helpers() -{ - static if (is(Flags!Move)) - { - Flags!Move flags; - } - else - { - pragma(msg, "X: ", __traits(derivedMembers, Flags!Move)); - } -} - -template Flags(T) -{ - mixin({ - int defs = 1; - foreach (name; __traits(derivedMembers, Move)) - { - defs++; - } - if (defs) - { - return "struct Flags { bool x; }"; - } - else - { - return ""; - } - }()); -} - -struct Move -{ - int a; - mixin Helpers!(); -} - -enum a7815 = Move.init.flags; - -/+ -This is an invalid case. -When the Move struct member is analyzed: -1. mixin Helpers!() is instantiated. -2. In Helpers!(), static if and its condition is(Flags!Move)) evaluated. -3. In Flags!Move, string mixin evaluates and CTFE lambda. -4. __traits(derivedMembers, Move) tries to see the member of Move. - 4a. mixin Helpers!() member is analyzed. - 4b. `static if (is(Flags!Move))` in Helpers!() is evaluated - 4c. The Flags!Move instantiation is already in progress, so it cannot be resolved. - 4d. `static if` fails because Flags!Move cannot be determined as a type. -5. __traits(derivedMembers, Move) returns a 1-length tuple("a"). -6. The lambda in Flags!Move returns a string "struct Flags {...}", then - Flags!Move is instantiated to a new struct Flags. -7. Finally Move struct does not have flags member, then the `enum a7815` - definition will fail in its initializer. -+/ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail7886.d b/gcc/testsuite/gdc.test/fail_compilation/fail7886.d deleted file mode 100644 index b939aad..0000000 --- a/gcc/testsuite/gdc.test/fail_compilation/fail7886.d +++ /dev/null @@ -1,5 +0,0 @@ -// 7886 - -struct A { - static if (__traits(derivedMembers, A).length) {} -} diff --git a/gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d b/gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d new file mode 100644 index 0000000..b58f520 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d @@ -0,0 +1,13 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/staticforeach1.d(10): Error: must use labeled `break` within `static foreach` +--- +*/ +void main(){ + for(;;){ + static foreach(i;0..1){ + break; + } + } +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d b/gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d new file mode 100644 index 0000000..25e283e --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d @@ -0,0 +1,13 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/staticforeach2.d(10): Error: must use labeled `continue` within `static foreach` +--- +*/ +void main(){ + for(;;){ + static foreach(i;0..1){ + continue; + } + } +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d b/gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d new file mode 100644 index 0000000..a93d20b --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d @@ -0,0 +1,7 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/staticforeach3.d(7): Error: variable `staticforeach3.__anonymous.i` conflicts with variable `staticforeach3.__anonymous.i` at fail_compilation/staticforeach3.d(7) +--- +*/ +static foreach(i,i;[0]){} diff --git a/gcc/testsuite/gdc.test/fail_compilation/test17307.d b/gcc/testsuite/gdc.test/fail_compilation/test17307.d new file mode 100644 index 0000000..470cfed --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/test17307.d @@ -0,0 +1,12 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/test17307.d(9): Error: anonymous struct can only be a part of an aggregate, not module `test17307` +--- + * https://issues.dlang.org/show_bug.cgi?id=17307 + */ + +struct { enum bitsPerWord = size_t; } + +void main() +{ } diff --git a/gcc/testsuite/gdc.test/fail_compilation/traits_alone.d b/gcc/testsuite/gdc.test/fail_compilation/traits_alone.d new file mode 100644 index 0000000..8f6f145 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/traits_alone.d @@ -0,0 +1,10 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/traits_alone.d(11): Error: found `End of File` when expecting `(` +fail_compilation/traits_alone.d(11): Error: `__traits(identifier, args...)` expected +fail_compilation/traits_alone.d(11): Error: no identifier for declarator `_error_` +--- +*/ +//used to segfault +__traits diff --git a/gcc/testsuite/gdc.test/runnable/arrayop.d b/gcc/testsuite/gdc.test/runnable/arrayop.d index 99bf800..e3749be 100644 --- a/gcc/testsuite/gdc.test/runnable/arrayop.d +++ b/gcc/testsuite/gdc.test/runnable/arrayop.d @@ -919,8 +919,7 @@ int main() } else { - pragma(msg, "arrayop.d:test1 Test skipped because arrayop evaluation" - " order is ill-defined. See GDC issue #8"); + //pragma(msg, "Test skipped because arrayop evaluation order is ill-defined."); } test3(); test4(); diff --git a/gcc/testsuite/gdc.test/runnable/constfold.d b/gcc/testsuite/gdc.test/runnable/constfold.d index 57da8b7..0708056 100644 --- a/gcc/testsuite/gdc.test/runnable/constfold.d +++ b/gcc/testsuite/gdc.test/runnable/constfold.d @@ -252,15 +252,15 @@ void test2() // This test only tests undefined, architecture-dependant behavior. // E.g. the result of converting a float whose value doesn't fit into the integer // leads to an undefined result. - version(GNU) - return; - - float f = float.infinity; - int i = cast(int) f; - writeln(i); - writeln(cast(int)float.max); - assert(i == cast(int)float.max); - assert(i == 0x80000000); + version (DigitalMars) + { + float f = float.infinity; + int i = cast(int) f; + writeln(i); + writeln(cast(int)float.max); + assert(i == cast(int)float.max); + assert(i == 0x80000000); + } } /************************************/ diff --git a/gcc/testsuite/gdc.test/runnable/e7804.d b/gcc/testsuite/gdc.test/runnable/e7804.d new file mode 100644 index 0000000..d325310 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/e7804.d @@ -0,0 +1,179 @@ +/* REQUIRED_ARGS: -unittest +*/ +module e7804; + +struct Bar {static struct B{}} +alias BarB = __traits(getMember, Bar, "B"); +static assert(is(BarB == Bar.B)); +static assert(is(const(__traits(getMember, Bar, "B")) == const(Bar.B))); + +alias BarBParent = __traits(parent, BarB); +static assert(is(BarBParent == Bar)); + +struct Foo {alias MyInt = int;} +alias FooInt = __traits(getMember, Foo, "MyInt"); +static immutable FooInt fi = 42; +static assert(fi == 42); +void declVsStatementSupport() +{ + __traits(getMember, Foo, "MyInt") i1 = 1; + const(__traits(getMember, Foo, "MyInt")) i2 = 1; + assert(i1 == i2); + __traits(getMember, Foo, "MyInt") i3 = __traits(getMember, Foo, "MyInt").max; + assert(i3 == int.max); +} + + +enum __traits(getMember, Foo, "MyInt") a0 = 12; +static assert(is(typeof(a0) == int)); +static assert(a0 == 12); + + +const __traits(getMember, Foo, "MyInt") a1 = 46; + + +__traits(getMember, Foo, "MyInt") a2 = 78; + + +const(__traits(getMember, Foo, "MyInt")) a3 = 63; + + +struct WithSym {static int foo; static int bar(){return 42;}} +alias m1 = __traits(getMember, WithSym, "foo"); +alias m2 = WithSym.foo; +static assert(__traits(isSame, m1, m2)); +alias f1 = __traits(getMember, WithSym, "bar"); +alias f2 = WithSym.bar; +static assert(__traits(isSame, f1, f2)); + + +auto ovld(const(char)[] s){return s;} +auto ovld(int i){return i;} +alias ovlds = __traits(getOverloads, e7804, "ovld"); + + +struct TmpPrm(T) +if (is(T == int)){T t;} +TmpPrm!(__traits(getMember, Foo, "MyInt")) tpt = TmpPrm!(__traits(getMember, Foo, "MyInt"))(42); + + +@Foo @(1) class Class +{ + final void virtual(){} + int virtual(int p){return p;} + void test(this T)() + { + alias vf = __traits(getVirtualFunctions, Class, "virtual"); + assert(vf.length == 2); + alias vm = __traits(getVirtualMethods, Class, "virtual"); + assert(vm.length == 1); + assert(vm[0](42) == 42); + alias attribs = __traits(getAttributes, Class); + assert(attribs.length == 2); + assert(is(typeof(attribs[0]()) == Foo)); + assert(attribs[1] == 1); + + alias objectAll = __traits(allMembers, Object); + alias classDerived = __traits(derivedMembers, Class); + alias classAll = __traits(allMembers, Class); + enum Seq(T...) = T; + static assert (classAll == Seq!(classDerived, objectAll)); + } +} + + +struct UnitTests +{ + static int count; + unittest { count++; } + unittest {++++count;} + static void test() + { + alias tests = __traits(getUnitTests, UnitTests); + static assert(tests.length == 2); + foreach(t; tests) t(); + assert(count == 6); // not 3 because executed automatically (DRT) then manually + } +} + + +class One +{ + void foo(){} + void foo(int){} +} + +class Two : One +{ + void test() + { + alias Seq(T...) = T; + alias p1 = Seq!(__traits(getMember, super, "foo"))[0]; + alias p2 = __traits(getMember, super, "foo"); + static assert(__traits(isSame, p1, p2)); + } +} + + +class SingleSymTuple +{ + int foo(){return 42;} + void test() + { + alias f = __traits(getMember, this, "foo"); + assert(f() == 42); + } +} + + +struct WithAliasThis +{ + auto getter(){return 42;} + alias getter this; + void test() + { + alias getterCall = __traits(getAliasThis, typeof(this)); + assert(mixin(getterCall[0]) == 42); + } +} + +void main() +{ + declVsStatementSupport(); + assert(a1 == 46); + assert(a2 == 78); + assert(a3 == 63); + assert(f1() == f2()); + Foo.MyInt fmi = cast(__traits(getMember, Foo, "MyInt")) 0; + auto c = __traits(getMember, Foo, "MyInt").max; + assert(c == int.max); + assert(ovlds[0]("farfelu") == "farfelu"); + assert(ovlds[1](42) == 42); + (new Class).test(); + UnitTests.test(); + (new WithAliasThis).test(); + (new Two).test(); + (new SingleSymTuple).test(); +} + +/* https://issues.dlang.org/show_bug.cgi?id=19708 */ +struct Foo19708 {} +struct Bar19708 {} +template Baz19708(T) { struct Baz19708{T t;} } +int symbol19708; + +@Foo19708 @Bar19708 @Baz19708 @symbol19708 int bar19708; + +alias TR19708 = __traits(getAttributes, bar19708); +alias TRT = __traits(getAttributes, bar19708)[2]; + +TR19708[0] a119708; +TR19708[1] a219708; +alias A3 = TRT!int; + +alias C19708 = TR19708[0]; +alias D19708 = TR19708[1]; +C19708 c1; +D19708 d1; + +static assert(__traits(isSame, TR19708[3], symbol19708)); diff --git a/gcc/testsuite/gdc.test/runnable/imports/template13478a.d b/gcc/testsuite/gdc.test/runnable/imports/template13478a.d index 9fcecf3..0c390bc 100644 --- a/gcc/testsuite/gdc.test/runnable/imports/template13478a.d +++ b/gcc/testsuite/gdc.test/runnable/imports/template13478a.d @@ -1,9 +1,8 @@ module imports.template13478a; -import gcc.attribute; - -@attribute("noinline") bool foo(T)() { +bool foo(T)() { // Make sure this is not inlined so template13478.o actually // needs to reference it. + pragma(inline, false); return false; } diff --git a/gcc/testsuite/gdc.test/runnable/staticforeach.d b/gcc/testsuite/gdc.test/runnable/staticforeach.d new file mode 100644 index 0000000..bf6dc98 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/staticforeach.d @@ -0,0 +1,45 @@ +// REQUIRED_ARGS: + +/**********************************/ +// https://issues.dlang.org/show_bug.cgi?id=19479 + +mixin template genInts19479a() +{ + static foreach (t; 0..1) + int i = 5; +} + +mixin template genInts19479b() +{ + static foreach (t; 0..2) + mixin("int i" ~ cast(char)('0' + t) ~ " = 5;"); +} + +void test19479() +{ + { + static foreach (t; 0..1) + int i = 5; + assert(i == 5); + } + { + mixin genInts19479a!(); + assert(i == 5); + } + { + static foreach (t; 0..2) + mixin("int i" ~ cast(char)('0' + t) ~ " = 5;"); + assert(i0 == 5); + assert(i1 == 5); + } + { + mixin genInts19479b!(); + assert(i0 == 5); + assert(i1 == 5); + } +} + +void main() +{ + test19479(); +} diff --git a/gcc/testsuite/gdc.test/runnable/test42.d b/gcc/testsuite/gdc.test/runnable/test42.d index 76f8e21..6e0c42b 100644 --- a/gcc/testsuite/gdc.test/runnable/test42.d +++ b/gcc/testsuite/gdc.test/runnable/test42.d @@ -1682,54 +1682,13 @@ void test101() /***************************************************/ -version(GNU) -{ -int x103; - -void external(int a, ...) -{ - va_list ap; - va_start(ap, a); - auto ext = va_arg!int(ap); - printf("external: %d\n", ext); - x103 = ext; - va_end(ap); -} - -class C103 -{ - void method () - { - void internal (int a, ...) - { - va_list ap; - va_start(ap, a); - auto internal = va_arg!int(ap); - printf("internal: %d\n", internal); - x103 = internal; - va_end(ap); - } - - internal (0, 43); - assert(x103 == 43); - } -} - -void test103() -{ - external(0, 42); - assert(x103 == 42); - (new C103).method (); -} -} -else version(X86) -{ int x103; void external(...) { - printf("external: %d\n", *cast (int *) _argptr); - x103 = *cast (int *) _argptr; + int arg = va_arg!int(_argptr); + printf("external: %d\n", arg); + x103 = arg; } class C103 @@ -1738,8 +1697,9 @@ class C103 { void internal (...) { - printf("internal: %d\n", *cast (int *)_argptr); - x103 = *cast (int *) _argptr; + int arg = va_arg!int(_argptr); + printf("internal: %d\n", arg); + x103 = arg; } internal (43); @@ -1753,14 +1713,6 @@ void test103() assert(x103 == 42); (new C103).method (); } -} -else version(X86_64) -{ - pragma(msg, "Not ported to x86-64 compatible varargs, yet."); - void test103() {} -} -else - static assert(false, "Unknown platform"); /***************************************************/ diff --git a/gcc/testsuite/gdc.test/runnable/traits.d b/gcc/testsuite/gdc.test/runnable/traits.d index ef23e9f..6c3bf78 100644 --- a/gcc/testsuite/gdc.test/runnable/traits.d +++ b/gcc/testsuite/gdc.test/runnable/traits.d @@ -1247,14 +1247,35 @@ struct S10096X invariant() {} invariant() {} unittest {} + unittest {} this(int) {} this(this) {} ~this() {} + + string getStr() in(str) out(r; r == str) { return str; } } static assert( [__traits(allMembers, S10096X)] == - ["str", "__ctor", "__postblit", "__dtor", "__xdtor", "__xpostblit", "opAssign"]); + ["str", "__ctor", "__postblit", "__dtor", "getStr", "__xdtor", "__xpostblit", "opAssign"]); + +class C10096X +{ + string str; + + invariant() {} + invariant() {} + unittest {} + unittest {} + + this(int) {} + ~this() {} + + string getStr() in(str) out(r; r == str) { return str; +} +static assert( + [__traits(allMembers, C10096X)] == + ["str", "__ctor", "__dtor", "getStr", "__xdtor", "toString", "toHash", "opCmp", "opEquals", "Monitor", "factory"]); // -------- @@ -1526,6 +1547,21 @@ void async(ARGS...)(ARGS) alias test17495 = async!(int, int); /********************************************************/ +// https://issues.dlang.org/show_bug.cgi?id=10100 + +enum E10100 +{ + value, + _value, + __value, + ___value, + ____value, +} +static assert( + [__traits(allMembers, E10100)] == + ["value", "_value", "__value", "___value", "____value"]); + +/********************************************************/ int main() { -- cgit v1.1 From 5c048755ec98645f8436b630df3f9294ca9cbc2a Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 10 Mar 2020 19:03:37 -0400 Subject: analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] PR analyzer/94099 and PR analyzer/94105 both report ICEs relating to calling region_model::get_lvalue on a NOP_EXPR. PR analyzer/94099's ICE happens when generating a checker_path when encountering an unhandled tree code (NOP_EXPR) in get_lvalue with a NULL context (from for_each_state_change). PR analyzer/94105 ICE happens when handling an ARRAY_REF where the first operand is a NOP_EXPR: the unhandled tree code gives us a symbolic_region, but the case for ARRAY_REF assumes we have an array_region. This patch fixes the ICEs by handling NOP_EXPR within region_model::get_lvalue, and bulletproofs both of the above sources of failure. gcc/analyzer/ChangeLog: PR analyzer/94099 PR analyzer/94105 * diagnostic-manager.cc (for_each_state_change): Bulletproof against errors in get_rvalue by passing a tentative_region_model_context and rejecting if there's an error. * region-model.cc (region_model::get_lvalue_1): When handling ARRAY_REF, handle results of error-handling. Handle NOP_EXPR. gcc/testsuite/ChangeLog: PR analyzer/94099 PR analyzer/94105 * gcc.dg/analyzer/pr94099.c: New test. * gcc.dg/analyzer/pr94105.c: New test. --- gcc/analyzer/ChangeLog | 10 ++++++++++ gcc/analyzer/diagnostic-manager.cc | 5 +++-- gcc/analyzer/region-model.cc | 14 +++++++++++++- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.dg/analyzer/pr94099.c | 27 +++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/analyzer/pr94105.c | 3 +++ 6 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94099.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94105.c (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index e51a1cd..8fc5dc4 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,13 @@ +2020-03-13 David Malcolm + + PR analyzer/94099 + PR analyzer/94105 + * diagnostic-manager.cc (for_each_state_change): Bulletproof + against errors in get_rvalue by passing a + tentative_region_model_context and rejecting if there's an error. + * region-model.cc (region_model::get_lvalue_1): When handling + ARRAY_REF, handle results of error-handling. Handle NOP_EXPR. + 2020-03-06 David Malcolm * analyzer.h (class array_region): New forward decl. diff --git a/gcc/analyzer/diagnostic-manager.cc b/gcc/analyzer/diagnostic-manager.cc index 1b2c3ce..bea566d 100644 --- a/gcc/analyzer/diagnostic-manager.cc +++ b/gcc/analyzer/diagnostic-manager.cc @@ -768,9 +768,10 @@ for_each_state_change (const program_state &src_state, if (dst_pv->m_stack_depth >= src_state.m_region_model->get_stack_depth ()) continue; + tentative_region_model_context ctxt; svalue_id src_sid - = src_state.m_region_model->get_rvalue (*dst_pv, NULL); - if (src_sid.null_p ()) + = src_state.m_region_model->get_rvalue (*dst_pv, &ctxt); + if (src_sid.null_p () || ctxt.had_errors_p ()) continue; state_machine::state_t src_sm_val = src_smap.get_state (src_sid); if (dst_sm_val != src_sm_val) diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 87980e7..45a1902 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -4749,7 +4749,18 @@ region_model::get_lvalue_1 (path_var pv, region_model_context *ctxt) region_id array_rid = get_lvalue (array, ctxt); svalue_id index_sid = get_rvalue (index, ctxt); - array_region *array_reg = get_region (array_rid); + region *base_array_reg = get_region (array_rid); + array_region *array_reg = base_array_reg->dyn_cast_array_region (); + if (!array_reg) + { + /* Normally, array_rid ought to refer to an array_region, since + array's type will be ARRAY_TYPE. However, if we have an + unexpected tree code for array, we could have a + symbolic_region here. If so, we're in error-handling. */ + gcc_assert (base_array_reg->get_type () == NULL_TREE); + return make_region_for_unexpected_tree_code (ctxt, expr, + dump_location_t ()); + } return array_reg->get_element (this, array_rid, index_sid, ctxt); } break; @@ -4849,6 +4860,7 @@ region_model::get_lvalue_1 (path_var pv, region_model_context *ctxt) } break; + case NOP_EXPR: case VIEW_CONVERT_EXPR: { tree obj = TREE_OPERAND (expr, 0); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 296ea8f..75d6041 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-13 David Malcolm + + PR analyzer/94099 + PR analyzer/94105 + * gcc.dg/analyzer/pr94099.c: New test. + * gcc.dg/analyzer/pr94105.c: New test. + 2020-03-13 Vasee Vinayagamoorthy * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Fix DejaGnu diff --git a/gcc/testsuite/gcc.dg/analyzer/pr94099.c b/gcc/testsuite/gcc.dg/analyzer/pr94099.c new file mode 100644 index 0000000..0a34f56 --- /dev/null +++ b/gcc/testsuite/gcc.dg/analyzer/pr94099.c @@ -0,0 +1,27 @@ +/* { dg-additional-options "-O1" } */ + +struct cg { + int hk; + int *bg; +}; + +union vb { + struct cg gk; +}; + +void +l3 (union vb *); + +void +pl (void) +{ + union vb th = { 0, }; + int sc; + + for (sc = 0; sc < 1; ++sc) + { + th.gk.hk = 0; + th.gk.bg[sc] = 0; /* { dg-warning "uninitialized" } */ + l3 (&th); + } +} diff --git a/gcc/testsuite/gcc.dg/analyzer/pr94105.c b/gcc/testsuite/gcc.dg/analyzer/pr94105.c new file mode 100644 index 0000000..8220723 --- /dev/null +++ b/gcc/testsuite/gcc.dg/analyzer/pr94105.c @@ -0,0 +1,3 @@ +/* { dg-do compile } */ + +#include "../../c-c++-common/torture/pr58794-1.c" -- cgit v1.1 From 50c96067c8ed60f4b3fcbee89fe31c905241b356 Mon Sep 17 00:00:00 2001 From: Aaron Sawdey Date: Fri, 13 Mar 2020 18:14:22 -0500 Subject: Fix UBSAN error, shifting 64 bit value by 64. 2020-03-13 Aaron Sawdey PR target/92379 * config/rs6000/rs6000.c (num_insns_constant_multi) Don't shift a 64-bit value by 64 bits (UB). --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4ea81e6..2daa351 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Aaron Sawdey + + PR target/92379 + * config/rs6000/rs6000.c (num_insns_constant_multi) Don't shift a + 64-bit value by 64 bits (UB). + 2020-03-13 Vladimir Makarov PR rtl-optimization/92303 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 24598af..5798f92 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5612,7 +5612,10 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode) && rs6000_is_valid_and_mask (GEN_INT (low), DImode)) insns = 2; total += insns; - value >>= BITS_PER_WORD; + /* If BITS_PER_WORD is the number of bits in HOST_WIDE_INT, doing + it all at once would be UB. */ + value >>= (BITS_PER_WORD - 1); + value >>= 1; } return total; } -- cgit v1.1 From 0034955eb16f7a3a79e242750c27fcad62d90147 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 14 Mar 2020 00:16:22 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index a30f6fc..3f10b5f 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200313 +20200314 -- cgit v1.1 From 53b28abf8e4ba37e47d3bb05476e0a80ae761567 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sat, 14 Mar 2020 08:15:08 +0100 Subject: Fix doubled indefinite articles, mostly in comments. 2020-03-14 Jakub Jelinek * gimple-fold.c (gimple_fold_builtin_strncpy): Change "a an" to "an" in a comment. * hsa-common.h (is_a_helper): Likewise. * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise. * config/arc/arc.c (arc600_corereg_hazard): Likewise. * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise. * logic.cc (formula::formula): Change "a an" to "an" in a comment. * parser.c (cp_debug_parser): Change "a an" to "an" in a string literal. --- gcc/ChangeLog | 9 +++++++++ gcc/config/arc/arc.c | 2 +- gcc/config/s390/s390.c | 2 +- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/logic.cc | 2 +- gcc/cp/parser.c | 2 +- gcc/gimple-fold.c | 2 +- gcc/hsa-common.h | 2 +- gcc/tree-ssa-strlen.c | 2 +- 9 files changed, 22 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2daa351..0f79a7c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-14 Jakub Jelinek + + * gimple-fold.c (gimple_fold_builtin_strncpy): Change + "a an" to "an" in a comment. + * hsa-common.h (is_a_helper): Likewise. + * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise. + * config/arc/arc.c (arc600_corereg_hazard): Likewise. + * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise. + 2020-03-13 Aaron Sawdey PR target/92379 diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index c98bd6c..537af79 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -9353,7 +9353,7 @@ arc600_corereg_hazard (rtx_insn *pred, rtx_insn *succ) continue; } rtx dest = XEXP (x, 0); - /* Check if this sets a an extension register. N.B. we use 61 for the + /* Check if this sets an extension register. N.B. we use 61 for the condition codes, which is definitely not an extension register. */ if (REG_P (dest) && REGNO (dest) >= 32 && REGNO (dest) < 61 /* Check if the same register is used by the PAT. */ diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index ae2be36..b6bc334 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -13252,7 +13252,7 @@ s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, assemble_end_function (thunk, fnname); } -/* Output either an indirect jump or a an indirect call +/* Output either an indirect jump or an indirect call (RETURN_ADDR_REGNO != INVALID_REGNUM) with target register REGNO using a branch trampoline disabling branch target prediction. */ diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index eea795d..79434c9 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-14 Jakub Jelinek + + * logic.cc (formula::formula): Change "a an" to "an" in a comment. + * parser.c (cp_debug_parser): Change "a an" to "an" in a string + literal. + 2020-03-13 Patrick Palka PR c++/67960 diff --git a/gcc/cp/logic.cc b/gcc/cp/logic.cc index e0ffbd8..4e376fd 100644 --- a/gcc/cp/logic.cc +++ b/gcc/cp/logic.cc @@ -238,7 +238,7 @@ struct formula formula (tree t) { - /* This should call emplace_back(). There's a an extra copy being + /* This should call emplace_back(). There's an extra copy being invoked by using push_back(). */ m_clauses.push_back (t); m_current = m_clauses.begin (); diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 24f7167..0c7db8b 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -556,7 +556,7 @@ cp_debug_parser (FILE *file, cp_parser *parser) parser->in_statement & IN_SWITCH_STMT); cp_debug_print_flag (file, "Parsing a structured OpenMP block", parser->in_statement & IN_OMP_BLOCK); - cp_debug_print_flag (file, "Parsing a an OpenMP loop", + cp_debug_print_flag (file, "Parsing an OpenMP loop", parser->in_statement & IN_OMP_FOR); cp_debug_print_flag (file, "Parsing an if statement", parser->in_statement & IN_IF_STMT); diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index fa7a396..9e45cc5 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -1857,7 +1857,7 @@ gimple_fold_builtin_strncpy (gimple_stmt_iterator *gsi, /* If the LEN parameter is zero, return DEST. */ if (integer_zerop (len)) { - /* Avoid warning if the destination refers to a an array/pointer + /* Avoid warning if the destination refers to an array/pointer decorate with attribute nonstring. */ if (!nonstring) { diff --git a/gcc/hsa-common.h b/gcc/hsa-common.h index e12ffb1..ffeaaba 100644 --- a/gcc/hsa-common.h +++ b/gcc/hsa-common.h @@ -199,7 +199,7 @@ private: void operator delete (void *) {} }; -/* Report whether or not P is a an immediate operand. */ +/* Report whether or not P is an immediate operand. */ template <> template <> diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index 8815cdb..0d70f3c 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -3081,7 +3081,7 @@ maybe_diag_stxncpy_trunc (gimple_stmt_iterator gsi, tree src, tree cnt) return false; } - /* Likewise, if the destination refers to a an array/pointer declared + /* Likewise, if the destination refers to an array/pointer declared nonstring return early. */ if (get_attr_nonstring_decl (dstdecl, &ref)) return false; -- cgit v1.1 From 9a6408bd18fe893a59297d80010fbd3660300347 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Mon, 17 Feb 2020 12:13:21 +0000 Subject: rs6000/test: Fix selector in fold-vec-mule-misc.c Run tests should use vmx_hw, not just powerpc_altivec_ok. gcc/testsuite/ PR target/94176 * gcc.target/powerpc/fold-vec-mule-misc.c: Use vmx_hw selector. --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 75d6041..0f84567 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-14 Segher Boessenkool + + PR target/94176 + * gcc.target/powerpc/fold-vec-mule-misc.c: Use vmx_hw selector. + 2020-03-13 David Malcolm PR analyzer/94099 diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c index 9b89118..7daf302 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c @@ -1,7 +1,7 @@ /* PR target/79941 */ /* { dg-do run } */ -/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-require-effective-target vmx_hw } */ /* { dg-options "-maltivec -O2 -save-temps" } */ #include -- cgit v1.1 From c393c99d3dc8329dc1a36011e70faa9700185051 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Sat, 14 Mar 2020 17:10:39 -0400 Subject: c++: Fix CTAD with multiple-arg ctor template [93248]. When cp_unevaluated_operand is set, tsubst_decl thinks that if it sees a PARM_DECL that isn't already in local_specializations, we're in a decltype in a trailing return type or some such, and so we only want a substitution for a single PARM_DECL. In this case, we want the whole chain, so make sure cp_unevaluated_operand is cleared. gcc/cp/ChangeLog 2020-03-14 Jason Merrill PR c++/93248 * pt.c (build_deduction_guide): Clear cp_unevaluated_operand for substituting DECL_ARGUMENTS. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/pt.c | 5 ++++- gcc/testsuite/g++.dg/cpp1z/class-deduction71.C | 6 ++++++ 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction71.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 79434c9..b4fa150 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-14 Jason Merrill + + PR c++/93248 + * pt.c (build_deduction_guide): Clear cp_unevaluated_operand for + substituting DECL_ARGUMENTS. + 2020-03-14 Jakub Jelinek * logic.cc (formula::formula): Change "a an" to "an" in a comment. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 789ccdb..0f3c2ad 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -28071,10 +28071,13 @@ build_deduction_guide (tree type, tree ctor, tree outer_args, tsubst_flags_t com complain, ctor); if (fparms == error_mark_node) ok = false; - fargs = tsubst (fargs, tsubst_args, complain, ctor); if (ci) ci = tsubst_constraint_info (ci, tsubst_args, complain, ctor); + /* Parms are to have DECL_CHAIN tsubsted, which would be skipped if + cp_unevaluated_operand. */ + cp_evaluated ev; + fargs = tsubst (fargs, tsubst_args, complain, ctor); current_template_parms = save_parms; } diff --git a/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C b/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C new file mode 100644 index 0000000..2fc71de --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C @@ -0,0 +1,6 @@ +// PR c++/93248 +// { dg-do compile { target c++17 } } + +template struct S +{ template S (T, V, long = 0); }; +using U = decltype(S{0, 4u}); -- cgit v1.1 From b3b0c671cc341fd04afc045a8d42d7a845d7f73c Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Sat, 14 Mar 2020 17:10:39 -0400 Subject: c++: Find parameter pack in typedef in lambda [92909]. find_parameter_packs_r doesn't look through typedefs, which is normally correct, but that means we need to handle their declarations specially. gcc/cp/ChangeLog 2020-03-14 Jason Merrill PR c++/92909 * pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk DECL_ORIGINAL_TYPE of a typedef. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/pt.c | 16 ++++++++++++---- gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C | 12 ++++++++++++ 3 files changed, 30 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b4fa150..bb7f590 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,11 @@ 2020-03-14 Jason Merrill + PR c++/92909 + * pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk + DECL_ORIGINAL_TYPE of a typedef. + +2020-03-14 Jason Merrill + PR c++/93248 * pt.c (build_deduction_guide): Clear cp_unevaluated_operand for substituting DECL_ARGUMENTS. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 0f3c2ad..bd2f9be 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -3916,10 +3916,18 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data) return NULL_TREE; case DECL_EXPR: - /* Ignore the declaration of a capture proxy for a parameter pack. */ - if (is_capture_proxy (DECL_EXPR_DECL (t))) - *walk_subtrees = 0; - return NULL_TREE; + { + tree decl = DECL_EXPR_DECL (t); + /* Ignore the declaration of a capture proxy for a parameter pack. */ + if (is_capture_proxy (decl)) + *walk_subtrees = 0; + if (is_typedef_decl (decl)) + /* Since we stop at typedefs above, we need to look through them at + the point of the DECL_EXPR. */ + cp_walk_tree (&DECL_ORIGINAL_TYPE (decl), + &find_parameter_packs_r, ppd, ppd->visited); + return NULL_TREE; + } case TEMPLATE_DECL: if (!DECL_TEMPLATE_TEMPLATE_PARM_P (t)) diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C new file mode 100644 index 0000000..052283e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C @@ -0,0 +1,12 @@ +// PR c++/92909 +// { dg-do compile { target c++11 } } + +template +void foo() +{ + [] + { + using T = Ts; + }(); // { dg-error "not expanded" } +} +template void foo<>(); -- cgit v1.1 From 3a285529ee338ef2867ae7add26b6493f004bf0d Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Sat, 14 Mar 2020 17:10:39 -0400 Subject: c++: Fix ICE-after-error on partial spec [92068] Here the template arguments for the partial specialization are valid arguments for the template, but not for a partial specialization, because 'd' can never be deduced to anything other than an empty pack. gcc/cp/ChangeLog 2020-03-14 Jason Merrill PR c++/92068 * pt.c (process_partial_specialization): Error rather than crash on extra pack expansion. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/pt.c | 9 ++++++++- gcc/testsuite/g++.dg/cpp0x/variadic178.C | 6 ++++++ 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic178.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index bb7f590..c9375234 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,11 @@ 2020-03-14 Jason Merrill + PR c++/92068 + * pt.c (process_partial_specialization): Error rather than crash on + extra pack expansion. + +2020-03-14 Jason Merrill + PR c++/92909 * pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk DECL_ORIGINAL_TYPE of a typedef. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index bd2f9be..48ac486 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -5038,6 +5038,14 @@ process_partial_specialization (tree decl) return decl; } + else if (nargs > DECL_NTPARMS (maintmpl)) + { + error ("too many arguments for partial specialization %qT", type); + inform (DECL_SOURCE_LOCATION (maintmpl), "primary template here"); + /* Avoid crash below. */ + return decl; + } + /* If we aren't in a dependent class, we can actually try deduction. */ else if (tpd.level == 1 /* FIXME we should be able to handle a partial specialization of a @@ -5064,7 +5072,6 @@ process_partial_specialization (tree decl) Also, we verify that pack expansions only occur at the end of the argument list. */ - gcc_assert (nargs == DECL_NTPARMS (maintmpl)); tpd2.parms = 0; for (i = 0; i < nargs; ++i) { diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic178.C b/gcc/testsuite/g++.dg/cpp0x/variadic178.C new file mode 100644 index 0000000..f0e6595 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/variadic178.C @@ -0,0 +1,6 @@ +// PR c++/92068 +// { dg-do compile { target c++11 } } + +template struct a; +template +struct a { }; // { dg-error "arguments" } -- cgit v1.1 From 824722e45f80b22e2f035a61300f494b2a10d6f4 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sat, 14 Mar 2020 16:06:55 -0700 Subject: i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV There is no need to set mode attribute to XImode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. gcc/ PR target/89229 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL check. gcc/testsuite/ PR target/89229 * gcc.target/i386/pr89229-5a.c: New test. * gcc.target/i386/pr89229-5b.c: Likewise. * gcc.target/i386/pr89229-5c.c: Likewise. --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/i386.md | 31 ++---------------------------- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/i386/pr89229-5a.c | 17 ++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89229-5b.c | 6 ++++++ gcc/testsuite/gcc.target/i386/pr89229-5c.c | 7 +++++++ 6 files changed, 46 insertions(+), 29 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5c.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f79a7c..91e9467 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-14 H.J. Lu + + PR target/89229 + * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov + for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL + check. + 2020-03-14 Jakub Jelinek * gimple-fold.c (gimple_fold_builtin_strncpy): Change diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0f57f939..6fa5db0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2054,31 +2054,7 @@ return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_DI: - /* Handle broken assemblers that require movd instead of movq. */ - if (!HAVE_AS_IX86_INTERUNIT_MOVQ - && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) - return "%vmovd\t{%1, %0|%0, %1}"; - return "%vmovq\t{%1, %0|%0, %1}"; - - case MODE_TI: - /* Handle AVX512 registers set. */ - if (EXT_REX_SSE_REG_P (operands[0]) - || EXT_REX_SSE_REG_P (operands[1])) - return "vmovdqa64\t{%1, %0|%0, %1}"; - return "%vmovdqa\t{%1, %0|%0, %1}"; - - case MODE_V2SF: - gcc_assert (!TARGET_AVX); - return "movlps\t{%1, %0|%0, %1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); case TYPE_SSECVT: if (SSE_REG_P (operands[0])) @@ -2164,10 +2140,7 @@ (cond [(eq_attr "alternative" "2") (const_string "SI") (eq_attr "alternative" "12,13") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) - (const_string "TI") - (match_test "TARGET_AVX") + (cond [(match_test "TARGET_AVX") (const_string "TI") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0f84567..2e75884 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-14 H.J. Lu + + PR target/89229 + * gcc.target/i386/pr89229-5a.c: New test. + * gcc.target/i386/pr89229-5b.c: Likewise. + * gcc.target/i386/pr89229-5c.c: Likewise. + 2020-03-14 Segher Boessenkool PR target/94176 diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5a.c b/gcc/testsuite/gcc.target/i386/pr89229-5a.c new file mode 100644 index 0000000..cb9b071 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-5a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ + +extern long long i; + +long long +foo1 (void) +{ + register long long xmm16 __asm ("xmm16") = i; + asm volatile ("" : "+v" (xmm16)); + register long long xmm17 __asm ("xmm17") = xmm16; + asm volatile ("" : "+v" (xmm17)); + return xmm17; +} + +/* { dg-final { scan-assembler-times "vmovdqa64\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5b.c b/gcc/testsuite/gcc.target/i386/pr89229-5b.c new file mode 100644 index 0000000..261f2e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-5b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */ + +#include "pr89229-5a.c" + +/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5c.c b/gcc/testsuite/gcc.target/i386/pr89229-5c.c new file mode 100644 index 0000000..5fe537f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-5c.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ + +#include "pr89229-5a.c" + +/* { dg-final { scan-assembler-times "vmovdqa64\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ -- cgit v1.1 From 89769d70af2362bbae1f93800ffc8b74f553acfd Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 15 Mar 2020 00:16:14 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3f10b5f..d1f8c59 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200314 +20200315 -- cgit v1.1 From 9c3cdb43c2bdaf8a8d2e62db010b04f6086d76b7 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sun, 15 Mar 2020 01:27:40 +0100 Subject: tree-nested: Fix handling of *reduction clauses with C array sections [PR93566] tree-nested.c didn't handle C array sections in {,task_,in_}reduction clauses. 2020-03-14 Jakub Jelinek PR middle-end/93566 * tree-nested.c (convert_nonlocal_omp_clauses, convert_local_omp_clauses): Handle {,in_,task_}reduction clauses with C/C++ array sections. * testsuite/libgomp.c/pr93566.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/tree-nested.c | 37 ++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 91e9467..883e13f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-14 Jakub Jelinek + + PR middle-end/93566 + * tree-nested.c (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle {,in_,task_}reduction clauses + with C/C++ array sections. + 2020-03-14 H.J. Lu PR target/89229 diff --git a/gcc/tree-nested.c b/gcc/tree-nested.c index 2bb1106..6f696da 100644 --- a/gcc/tree-nested.c +++ b/gcc/tree-nested.c @@ -1188,7 +1188,7 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) { struct nesting_info *const info = (struct nesting_info *) wi->info; bool need_chain = false, need_stmts = false; - tree clause, decl; + tree clause, decl, *pdecl; int dummy; bitmap new_suppress; @@ -1197,6 +1197,7 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) for (clause = *pclauses; clause ; clause = OMP_CLAUSE_CHAIN (clause)) { + pdecl = NULL; switch (OMP_CLAUSE_CODE (clause)) { case OMP_CLAUSE_REDUCTION: @@ -1204,6 +1205,15 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_TASK_REDUCTION: if (OMP_CLAUSE_REDUCTION_PLACEHOLDER (clause)) need_stmts = true; + if (TREE_CODE (OMP_CLAUSE_DECL (clause)) == MEM_REF) + { + pdecl = &TREE_OPERAND (OMP_CLAUSE_DECL (clause), 0); + if (TREE_CODE (*pdecl) == POINTER_PLUS_EXPR) + pdecl = &TREE_OPERAND (*pdecl, 0); + if (TREE_CODE (*pdecl) == INDIRECT_REF + || TREE_CODE (*pdecl) == ADDR_EXPR) + pdecl = &TREE_OPERAND (*pdecl, 0); + } goto do_decl_clause; case OMP_CLAUSE_LASTPRIVATE: @@ -1230,7 +1240,9 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_USE_DEVICE_ADDR: case OMP_CLAUSE_IS_DEVICE_PTR: do_decl_clause: - decl = OMP_CLAUSE_DECL (clause); + if (pdecl == NULL) + pdecl = &OMP_CLAUSE_DECL (clause); + decl = *pdecl; if (VAR_P (decl) && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) break; @@ -1239,7 +1251,7 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) if (OMP_CLAUSE_CODE (clause) == OMP_CLAUSE_SHARED) OMP_CLAUSE_SHARED_READONLY (clause) = 0; bitmap_set_bit (new_suppress, DECL_UID (decl)); - OMP_CLAUSE_DECL (clause) = get_nonlocal_debug_decl (info, decl); + *pdecl = get_nonlocal_debug_decl (info, decl); if (OMP_CLAUSE_CODE (clause) != OMP_CLAUSE_PRIVATE) need_chain = true; } @@ -1909,7 +1921,7 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) { struct nesting_info *const info = (struct nesting_info *) wi->info; bool need_frame = false, need_stmts = false; - tree clause, decl; + tree clause, decl, *pdecl; int dummy; bitmap new_suppress; @@ -1918,6 +1930,7 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) for (clause = *pclauses; clause ; clause = OMP_CLAUSE_CHAIN (clause)) { + pdecl = NULL; switch (OMP_CLAUSE_CODE (clause)) { case OMP_CLAUSE_REDUCTION: @@ -1925,6 +1938,15 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_TASK_REDUCTION: if (OMP_CLAUSE_REDUCTION_PLACEHOLDER (clause)) need_stmts = true; + if (TREE_CODE (OMP_CLAUSE_DECL (clause)) == MEM_REF) + { + pdecl = &TREE_OPERAND (OMP_CLAUSE_DECL (clause), 0); + if (TREE_CODE (*pdecl) == POINTER_PLUS_EXPR) + pdecl = &TREE_OPERAND (*pdecl, 0); + if (TREE_CODE (*pdecl) == INDIRECT_REF + || TREE_CODE (*pdecl) == ADDR_EXPR) + pdecl = &TREE_OPERAND (*pdecl, 0); + } goto do_decl_clause; case OMP_CLAUSE_LASTPRIVATE: @@ -1951,7 +1973,9 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_USE_DEVICE_ADDR: case OMP_CLAUSE_IS_DEVICE_PTR: do_decl_clause: - decl = OMP_CLAUSE_DECL (clause); + if (pdecl == NULL) + pdecl = &OMP_CLAUSE_DECL (clause); + decl = *pdecl; if (VAR_P (decl) && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) break; @@ -1964,8 +1988,7 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) if (OMP_CLAUSE_CODE (clause) == OMP_CLAUSE_SHARED) OMP_CLAUSE_SHARED_READONLY (clause) = 0; bitmap_set_bit (new_suppress, DECL_UID (decl)); - OMP_CLAUSE_DECL (clause) - = get_local_debug_decl (info, decl, field); + *pdecl = get_local_debug_decl (info, decl, field); need_frame = true; } } -- cgit v1.1 From b408e010ccf6cacc1f36cef8fca3252cfa677094 Mon Sep 17 00:00:00 2001 From: Lewis Hyatt Date: Sun, 15 Mar 2020 08:58:30 -0400 Subject: driver: Fix redundant descriptions in options Addresses issues where the two-column format of options descriptions was used, but the columns were separated by spaces rather than a single tab, causing the help output to be more verbose than intended. gcc/ChangeLog: 2020-03-15 Lewis Hyatt * common.opt: Avoid redundancy in the help text. * config/arc/arc.opt: Likewise. * config/cr16/cr16.opt: Likewise. gcc/c-family/ChangeLog: 2020-03-15 Lewis Hyatt * c.opt: Avoid redundancy in the help text. gcc/fortran/ChangeLog: 2020-03-15 Lewis Hyatt * lang.opt: Avoid redundancy in the help text. gcc/testsuite/ChangeLog: 2020-03-15 Lewis Hyatt * gcc.misc-tests/help.exp: Adapt to new output for -Walloc-size-larger-than= option. --- gcc/ChangeLog | 6 ++++++ gcc/c-family/ChangeLog | 4 ++++ gcc/c-family/c.opt | 22 +++++++++++----------- gcc/common.opt | 20 ++++++++++---------- gcc/config/arc/arc.opt | 4 ++-- gcc/config/cr16/cr16.opt | 2 +- gcc/fortran/ChangeLog | 4 ++++ gcc/fortran/lang.opt | 2 +- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.misc-tests/help.exp | 2 +- 10 files changed, 45 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 883e13f..af96a9b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-15 Lewis Hyatt + + * common.opt: Avoid redundancy in the help text. + * config/arc/arc.opt: Likewise. + * config/cr16/cr16.opt: Likewise. + 2020-03-14 Jakub Jelinek PR middle-end/93566 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 2e11b00..f03e44f 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,7 @@ +2020-03-15 Lewis Hyatt + + * c.opt: Avoid redundancy in the help text. + 2020-03-02 Marek Polacek PR c++/93958 - add missing -std=gnu++20. diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index 1cd585f..a1e0f4c 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -309,16 +309,16 @@ Warn on any use of alloca. Walloc-size-larger-than= C ObjC C++ LTO ObjC++ Var(warn_alloc_size_limit) Joined Host_Wide_Int ByteSize Warning Init(HOST_WIDE_INT_MAX) --Walloc-size-larger-than= Warn for calls to allocation functions that +-Walloc-size-larger-than= Warn for calls to allocation functions that attempt to allocate objects larger than the specified number of bytes. Wno-alloc-size-larger-than C ObjC C++ LTO ObjC++ Alias(Walloc-size-larger-than=,18446744073709551615EiB,none) Warning --Wno-alloc-size-larger-than Disable Walloc-size-larger-than= warning. Equivalent to Walloc-size-larger-than= or larger. +Disable Walloc-size-larger-than= warning. Equivalent to Walloc-size-larger-than= or larger. Walloc-zero C ObjC C++ ObjC++ Var(warn_alloc_zero) Warning --Walloc-zero Warn for calls to allocation functions that specify zero bytes. +Warn for calls to allocation functions that specify zero bytes. Walloca-larger-than= C ObjC C++ LTO ObjC++ Var(warn_alloca_limit) Warning Joined Host_Wide_Int ByteSize Init(HOST_WIDE_INT_MAX) @@ -328,7 +328,7 @@ alloca, and on bounded uses of alloca whose bound can be larger than Wno-alloca-larger-than C ObjC C++ LTO ObjC++ Alias(Walloca-larger-than=,18446744073709551615EiB,none) Warning --Wno-alloca-larger-than Disable Walloca-larger-than= warning. Equivalent to Walloca-larger-than= or larger. +Disable Walloca-larger-than= warning. Equivalent to Walloca-larger-than= or larger. Warray-bounds LangEnabledBy(C ObjC C++ LTO ObjC++) @@ -1252,7 +1252,7 @@ larger than bytes. Wno-vla-larger-than C ObjC C++ LTO ObjC++ Alias(Wvla-larger-than=,18446744073709551615EiB,none) Warning --Wno-vla-larger-than Disable Wvla-larger-than= warning. Equivalent to Wvla-larger-than= or larger. +Disable Wvla-larger-than= warning. Equivalent to Wvla-larger-than= or larger. Wvolatile C++ ObjC++ Var(warn_volatile) Warning @@ -1313,7 +1313,7 @@ Enforce class member access control semantics. fada-spec-parent= C ObjC C++ ObjC++ RejectNegative Joined Var(ada_specs_parent) --fada-spec-parent=unit Dump Ada specs as child units of given parent. +-fada-spec-parent=unit Dump Ada specs as child units of given parent. faligned-new C++ ObjC++ Alias(faligned-new=,1,0) @@ -1321,7 +1321,7 @@ Support C++17 allocation of over-aligned types. faligned-new= C++ ObjC++ Joined RejectNegative Var(aligned_new_threshold) UInteger Init(-1) --faligned-new= Use C++17 over-aligned type allocation for alignments greater than N. +-faligned-new= Use C++17 over-aligned type allocation for alignments greater than N. fall-virtual C++ ObjC++ WarnRemoved @@ -1515,7 +1515,7 @@ Permit '$' as an identifier character. fmacro-prefix-map= C ObjC C++ ObjC++ Joined RejectNegative --fmacro-prefix-map== Map one directory name to another in __FILE__, __BASE_FILE__, and __builtin_FILE(). +-fmacro-prefix-map== Map one directory name to another in __FILE__, __BASE_FILE__, and __builtin_FILE(). fdump-ada-spec C ObjC C++ ObjC++ RejectNegative Var(flag_dump_ada_spec) @@ -1530,7 +1530,7 @@ C++ ObjC++ Var(flag_elide_constructors) Init(1) felide-type C++ ObjC++ Var(flag_elide_type) Init(1) --fno-elide-type Do not elide common elements in template comparisons. +Do not elide common elements in template comparisons. fenforce-eh-specs C++ ObjC++ Var(flag_enforce_eh_specs) Init(1) @@ -1778,11 +1778,11 @@ C ObjC C++ ObjC++ JoinedOrMissing RejectNegative UInteger ftrack-macro-expansion= C ObjC C++ ObjC++ JoinedOrMissing RejectNegative UInteger --ftrack-macro-expansion=<0|1|2> Track locations of tokens coming from macro expansion and display them in error messages. +-ftrack-macro-expansion=<0|1|2> Track locations of tokens coming from macro expansion and display them in error messages. fpretty-templates C++ ObjC++ Var(flag_pretty_templates) Init(1) --fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments. +Do not pretty-print template specializations as the template signature followed by the arguments. fprintf-return-value C ObjC C++ ObjC++ LTO Optimization Var(flag_printf_return_value) Init(1) diff --git a/gcc/common.opt b/gcc/common.opt index fa9da50..4368910 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -1196,11 +1196,11 @@ Common RejectNegative Joined Var(common_deferred_options) Defer fdebug-prefix-map= Common Joined RejectNegative Var(common_deferred_options) Defer --fdebug-prefix-map== Map one directory name to another in debug information. +-fdebug-prefix-map== Map one directory name to another in debug information. ffile-prefix-map= Common Joined RejectNegative Var(common_deferred_options) Defer --ffile-prefix-map== Map one directory name to another in compilation result. +-ffile-prefix-map== Map one directory name to another in compilation result. fdebug-types-section Common Report Var(flag_debug_types_section) Init(0) @@ -1311,7 +1311,7 @@ Enum(diagnostic_url_rule) String(auto) Value(DIAGNOSTICS_URL_AUTO) fdiagnostics-format= Common Joined RejectNegative Enum(diagnostics_output_format) --fdiagnostics-format=[text|json] Select output format. +-fdiagnostics-format=[text|json] Select output format. ; Required for these enum values. SourceInclude @@ -1368,11 +1368,11 @@ Set minimum width of left margin of source code when showing source. fdisable- Common Joined RejectNegative Var(common_deferred_options) Defer --fdisable-[tree|rtl|ipa]-=range1+range2 disables an optimization pass. +-fdisable-[tree|rtl|ipa]-=range1+range2 Disable an optimization pass. fenable- Common Joined RejectNegative Var(common_deferred_options) Defer --fenable-[tree|rtl|ipa]-=range1+range2 enables an optimization pass. +-fenable-[tree|rtl|ipa]-=range1+range2 Enable an optimization pass. fdump- Common Joined RejectNegative Var(common_deferred_options) Defer @@ -1755,11 +1755,11 @@ Instrument function entry and exit with profiling calls. finstrument-functions-exclude-function-list= Common RejectNegative Joined --finstrument-functions-exclude-function-list=name,... Do not instrument listed functions. +-finstrument-functions-exclude-function-list=name,... Do not instrument listed functions. finstrument-functions-exclude-file-list= Common RejectNegative Joined --finstrument-functions-exclude-file-list=filename,... Do not instrument functions listed in files. +-finstrument-functions-exclude-file-list=filename,... Do not instrument functions listed in files. fipa-cp Common Report Var(flag_ipa_cp) Optimization @@ -2020,11 +2020,11 @@ Support synchronous non-call exceptions. foffload= Common Driver Joined MissingArgError(options or targets missing after %qs) --foffload== Specify offloading targets and options for them. +-foffload== Specify offloading targets and options for them. foffload-abi= Common Joined RejectNegative Enum(offload_abi) Var(flag_offload_abi) Init(OFFLOAD_ABI_UNSET) --foffload-abi=[lp64|ilp32] Set the ABI to use in an offload compiler. +-foffload-abi=[lp64|ilp32] Set the ABI to use in an offload compiler. Enum Name(offload_abi) Type(enum offload_abi) UnknownError(unknown offload ABI %qs) @@ -2182,7 +2182,7 @@ Enum(profile_reproducibility) String(multithreaded) Value(PROFILE_REPRODUCIBILIT fprofile-reproducible Common Joined RejectNegative Var(flag_profile_reproducible) Enum(profile_reproducibility) Init(PROFILE_REPRODUCIBILITY_SERIAL) --fprofile-reproducible=[serial|parallel-runs|multithreaded] Control level of reproducibility of profile gathered by -fprofile-generate. +-fprofile-reproducible=[serial|parallel-runs|multithreaded] Control level of reproducibility of profile gathered by -fprofile-generate. Enum Name(profile_update) Type(enum profile_update) UnknownError(unknown profile update method %qs) diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 7b99423..c6c64af 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -59,7 +59,7 @@ Force all calls to be made via a jli instruction. mmpy-option= Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option) --mmpy-option=MPY Compile ARCv2 code with a multiplier design option. +-mmpy-option=MPY Compile ARCv2 code with a multiplier design option. Enum Name(arc_mpy) Type(int) @@ -251,7 +251,7 @@ Cost to assume for a multiply instruction, with 4 being equal to a normal insn. mtune= Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE) --mcpu=TUNE Tune code for given ARC variant. +-mtune=TUNE Tune code for given ARC variant. Enum Name(arc_tune_attr) Type(int) diff --git a/gcc/config/cr16/cr16.opt b/gcc/config/cr16/cr16.opt index 0396c8d..f82c1d6 100644 --- a/gcc/config/cr16/cr16.opt +++ b/gcc/config/cr16/cr16.opt @@ -20,7 +20,7 @@ msim Target --msim Use simulator runtime. +Use simulator runtime. mbit-ops Target Report Mask(BIT_OPS) diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 661e4ce..dd0487d 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,7 @@ +2020-03-15 Lewis Hyatt + + * lang.opt: Avoid redundancy in the help text. + 2020-03-12 Tobias Burnus PR middle-end/94120 diff --git a/gcc/fortran/lang.opt b/gcc/fortran/lang.opt index 59523f7..da4b1aa 100644 --- a/gcc/fortran/lang.opt +++ b/gcc/fortran/lang.opt @@ -415,7 +415,7 @@ Produce a warning at runtime if a array temporary has been created for a procedu fconvert= Fortran RejectNegative Joined Enum(gfc_convert) Var(flag_convert) Init(GFC_FLAG_CONVERT_NATIVE) --fconvert= The endianness used for unformatted files. +-fconvert= The endianness used for unformatted files. Enum Name(gfc_convert) Type(enum gfc_convert) UnknownError(Unrecognized option to endianness value: %qs) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2e75884..02205f1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-15 Lewis Hyatt + + * gcc.misc-tests/help.exp: Adapt to new output for + -Walloc-size-larger-than= option. + 2020-03-14 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/gcc.misc-tests/help.exp b/gcc/testsuite/gcc.misc-tests/help.exp index a9ee892..bcb62e0 100644 --- a/gcc/testsuite/gcc.misc-tests/help.exp +++ b/gcc/testsuite/gcc.misc-tests/help.exp @@ -115,7 +115,7 @@ check_for_options c "-Q --help=warnings" { # Verify that an option that expects a byte-size argument is shown with # a meaningful byte-size argument as the value. check_for_options c "-Q --help=warnings" { --Walloc-size-larger-than=[ \t]+[1-9][0-9]+ bytes +-Walloc-size-larger-than=[ \t]+[1-9][0-9]+ bytes -Wlarger-than=[^\n\r]+[1-9][0-9]+ bytes } "" "" -- cgit v1.1 From ced66da313526c3481ceb57ea1becca7b712444b Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Sun, 15 Mar 2020 14:22:18 +0000 Subject: coroutines: Fix indentation (NFC). Whitespace-only change. gcc/cp/ChangeLog: 2020-03-15 Iain Sandoe * coroutines.cc (co_await_expander): Fix indentation. --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/coroutines.cc | 8 ++++---- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index c9375234..661ba2b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,7 @@ +2020-03-15 Iain Sandoe + + * coroutines.cc (co_await_expander): Fix indentation. + 2020-03-14 Jason Merrill PR c++/92068 diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc index 920575b..f70b3ab 100644 --- a/gcc/cp/coroutines.cc +++ b/gcc/cp/coroutines.cc @@ -1471,10 +1471,10 @@ co_await_expander (tree *stmt, int * /*do_subtree*/, void *d) dtor = NULL_TREE; else { - /* Initialize the var from the provided 'o' expression. */ - r = build2 (INIT_EXPR, await_type, var, expr); - r = coro_build_cvt_void_expr_stmt (r, loc); - append_to_statement_list (r, &stmt_list); + /* Initialize the var from the provided 'o' expression. */ + r = build2 (INIT_EXPR, await_type, var, expr); + r = coro_build_cvt_void_expr_stmt (r, loc); + append_to_statement_list (r, &stmt_list); } /* Use the await_ready() call to test if we need to suspend. */ -- cgit v1.1 From 9d74caf21be7025db8fef997e87ebf3b85acaf4a Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 15 Mar 2020 10:21:08 -0700 Subject: i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV There is no need to set mode attribute to V16SFmode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. gcc/ PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and MODE_SF. * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL and ext_sse_reg_operand check. gcc/testsuite/ PR target/89229 * gcc.target/i386/pr89229-6a.c: New test. * gcc.target/i386/pr89229-6b.c: Likewise. * gcc.target/i386/pr89229-6c.c: Likewise. --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/i386.c | 9 +++++++++ gcc/config/i386/i386.md | 26 ++------------------------ gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/i386/pr89229-6a.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89229-6b.c | 6 ++++++ gcc/testsuite/gcc.target/i386/pr89229-6c.c | 6 ++++++ 7 files changed, 55 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6c.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index af96a9b..6718f71 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-15 H.J. Lu + + PR target/89229 + * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and + MODE_SF. + * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov + for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL + and ext_sse_reg_operand check. + 2020-03-15 Lewis Hyatt * common.opt: Avoid redundancy in the help text. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 924f955..d1910b4 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5127,12 +5127,21 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands) else return "%vmovq\t{%1, %0|%0, %1}"; + case MODE_SI: + return "%vmovd\t{%1, %0|%0, %1}"; + case MODE_DF: if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) return "vmovsd\t{%d1, %0|%0, %d1}"; else return "%vmovsd\t{%1, %0|%0, %1}"; + case MODE_SF: + if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) + return "vmovss\t{%d1, %0|%0, %d1}"; + else + return "%vmovss\t{%1, %0|%0, %1}"; + case MODE_V1DF: gcc_assert (!TARGET_AVX); return "movlpd\t{%1, %0|%0, %1}"; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6fa5db0..af39f90 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3490,24 +3490,7 @@ return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_SF: - if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) - return "vmovss\t{%d1, %0|%0, %d1}"; - return "%vmovss\t{%1, %0|%0, %1}"; - - case MODE_V16SF: - return "vmovaps\t{%g1, %g0|%g0, %g1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - case MODE_SI: - return "%vmovd\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); case TYPE_MMXMOV: switch (get_attr_mode (insn)) @@ -3579,12 +3562,7 @@ better to maintain the whole registers in single format to avoid problems on using packed logical operations. */ (eq_attr "alternative" "6") - (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256")) - (not (match_test "TARGET_AVX512VL"))) - (ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand"))) - (const_string "V16SF") - (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY") + (cond [(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY") (match_test "TARGET_SSE_SPLIT_REGS")) (const_string "V4SF") ] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 02205f1..f79f1c7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-15 H.J. Lu + + PR target/89229 + * gcc.target/i386/pr89229-6a.c: New test. + * gcc.target/i386/pr89229-6b.c: Likewise. + * gcc.target/i386/pr89229-6c.c: Likewise. + 2020-03-15 Lewis Hyatt * gcc.misc-tests/help.exp: Adapt to new output for diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6a.c b/gcc/testsuite/gcc.target/i386/pr89229-6a.c new file mode 100644 index 0000000..856115b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-6a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern float d; + +void +foo1 (float x) +{ + register float xmm16 __asm ("xmm16") = x; + asm volatile ("" : "+v" (xmm16)); + register float xmm17 __asm ("xmm17") = xmm16; + asm volatile ("" : "+v" (xmm17)); + d = xmm17; +} + +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6b.c b/gcc/testsuite/gcc.target/i386/pr89229-6b.c new file mode 100644 index 0000000..a74f716 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-6b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */ + +#include "pr89229-6a.c" + +/* { dg-final { scan-assembler-times "vmovaps\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6c.c b/gcc/testsuite/gcc.target/i386/pr89229-6c.c new file mode 100644 index 0000000..7a4d254 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-6c.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ + +#include "pr89229-6a.c" + +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ -- cgit v1.1 From 5e5ce5371f6a8199108eeade587261bf5593dedf Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 16 Mar 2020 00:16:17 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index d1f8c59..777d8ef 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200315 +20200316 -- cgit v1.1 From e4e9a59105a81cdd6c1328b0a5ed9fe4cc82840e Mon Sep 17 00:00:00 2001 From: Bin Cheng Date: Mon, 16 Mar 2020 11:09:14 +0800 Subject: Update post order number for merged SCC. Function loop_distribution::break_alias_scc_partitions needs to compute SCC with runtime alias edges skipped. As a result, partitions could be re-assigned larger post order number than SCC's precedent partition and distributed before the precedent one. This fixes the issue by updating the merged partition to the minimal post order in SCC. gcc/ PR tree-optimization/94125 * tree-loop-distribution.c (loop_distribution::break_alias_scc_partitions): Update post order number for merged scc. gcc/testsuite/ PR tree-optimization/94125 * gcc.dg/tree-ssa/pr94125.c: New test. --- gcc/ChangeLog | 7 ++++++ gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 +++++++++++++++++++++++++++++++++ gcc/tree-loop-distribution.c | 13 ++++------- 4 files changed, 58 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr94125.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6718f71..53c9622 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-16 Bin Cheng + + PR tree-optimization/94125 + * tree-loop-distribution.c + (loop_distribution::break_alias_scc_partitions): Update post order + number for merged scc. + 2020-03-15 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f79f1c7..ab04066 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Bin Cheng + + PR tree-optimization/94125 + * gcc.dg/tree-ssa/pr94125.c: New test. + 2020-03-15 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr94125.c b/gcc/testsuite/gcc.dg/tree-ssa/pr94125.c new file mode 100644 index 0000000..c339e51 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr94125.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ + +unsigned char b, f; +short d[1][8][1], *g = &d[0][3][0]; + +void __attribute__((noinline)) foo () +{ + int k[256] = { 0, 0, 0, 4, 0, 0 }; + for (int c = 252; c >= 0; c--) + { + b = f; + *g = k[c + 3]; + k[c + 1] = 0; + } + for (int i = 0; i < 8; i++) + if (d[0][i][0] != 0) + __builtin_abort (); +} + +void __attribute__((noinline)) bar () +{ + int k[256] = { 0, 0, 0, 4, 0, 0 }; + k[255] = 4; + for (int c = 0; c <=252; c++) + { + b = f; + *g = k[c + 3]; + k[c + 1] = 0; + } + for (int i = 0; i < 8; i++) + if ((i == 3 && d[0][i][0] != 4) || (i != 3 && d[0][i][0] != 0)) + __builtin_abort (); +} + +int main () +{ + foo (); + bar (); + return 0; +} diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c index 35d3821..4442321 100644 --- a/gcc/tree-loop-distribution.c +++ b/gcc/tree-loop-distribution.c @@ -2489,14 +2489,11 @@ loop_distribution::break_alias_scc_partitions (struct graph *rdg, if (cbdata.vertices_component[k] != i) continue; - /* Update postorder number so that merged reduction partition is - sorted after other partitions. */ - if (!partition_reduction_p (first) - && partition_reduction_p (partition)) - { - gcc_assert (pg->vertices[k].post < pg->vertices[j].post); - pg->vertices[j].post = pg->vertices[k].post; - } + /* Update to the minimal postordeer number of vertices in scc so + that merged partition is sorted correctly against others. */ + if (pg->vertices[j].post > pg->vertices[k].post) + pg->vertices[j].post = pg->vertices[k].post; + partition_merge_into (NULL, first, partition, FUSE_SAME_SCC); (*partitions)[k] = NULL; partition_free (partition); -- cgit v1.1 From 5ba25b2ef179aec8ba4c47612fbc5c388f41cb36 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 16 Mar 2020 09:02:21 +0100 Subject: tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] The following testcase fails with -fcompare-debug. The problem is that bar is marked as address_taken only with -g and not without. I've tracked it down to insert_init_stmt calling gimple_regimplify_operands even on DEBUG_STMTs. That function will just insert normal stmts before the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant. While DCE will turn those statements into debug temporaries, it can cause differences in SSA_NAMEs and more importantly, the ipa references are generated from those before the DCE happens. On the testcase, the DEBUG_STMT value is (int)bar. We could generate DEBUG_STMTs with debug temporaries instead, but I fail to see the reason to do that, DEBUG_STMTs allow other expressions and all we want to ensure is that the expressions aren't too large (arbitrarily complex), but during inlining/function versioning I don't see why something would queue a DEBUG_STMT with arbitrarily complex expressions in there. 2020-03-16 Jakub Jelinek PR tree-optimization/94166 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION as secondary comparison key. * gcc.dg/pr94166.c: New test. --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr94166.c | 24 ++++++++++++++++++++++++ gcc/tree-ssa-reassoc.c | 7 +++++-- 4 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94166.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 53c9622..8709f0c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-16 Jakub Jelinek + + PR tree-optimization/94166 + * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION + as secondary comparison key. + 2020-03-16 Bin Cheng PR tree-optimization/94125 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ab04066..d52cd1e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Jakub Jelinek + + PR tree-optimization/94166 + * gcc.dg/pr94166.c: New test. + 2020-03-16 Bin Cheng PR tree-optimization/94125 diff --git a/gcc/testsuite/gcc.dg/pr94166.c b/gcc/testsuite/gcc.dg/pr94166.c new file mode 100644 index 0000000..71917c4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94166.c @@ -0,0 +1,24 @@ +/* PR tree-optimization/94166 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +typedef int __m128i __attribute__((__may_alias__, __vector_size__(4 * sizeof (int)))); +unsigned int b[512]; + +void +foo (unsigned int *x, __m128i *y) +{ +#define A(n) __m128i v##n = y[n]; +#define B(n) A(n##0) A(n##1) A(n##2) A(n##3) A(n##4) A(n##5) A(n##6) A(n##7) \ + A(n##8) A(n##9) A(n##a) A(n##b) A(n##c) A(n##d) A(n##e) A(n##f) +#define C(n) B(n##0) B(n##1) B(n##2) B(n##3) B(n##4) B(n##5) B(n##6) B(n##7) + C(0x) +#undef A +#define A(n) *(__m128i *) &b[4 * n] = v##n; + C(0x) +#undef A +#define A(n) + b[4 * n] + b[4 * n + 1] + b[4 * n + 2] + b[4 * n + 3] + *x = *x + C(0x) + ; +} diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c index 359ccae..79871a8 100644 --- a/gcc/tree-ssa-reassoc.c +++ b/gcc/tree-ssa-reassoc.c @@ -1793,8 +1793,11 @@ sort_by_mach_mode (const void *p_i, const void *p_j) return 1; else if (mode1 < mode2) return -1; - else - return 0; + if (SSA_NAME_VERSION (tr1) < SSA_NAME_VERSION (tr2)) + return -1; + else if (SSA_NAME_VERSION (tr1) > SSA_NAME_VERSION (tr2)) + return 1; + return 0; } /* Cleanup hash map for VECTOR information. */ -- cgit v1.1 From 6d44c881286762628afce5169d921a388ae6a1ff Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 16 Mar 2020 09:03:59 +0100 Subject: tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] The following testcase fails with -fcompare-debug. The problem is that bar is marked as address_taken only with -g and not without. I've tracked it down to insert_init_stmt calling gimple_regimplify_operands even on DEBUG_STMTs. That function will just insert normal stmts before the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant. While DCE will turn those statements into debug temporaries, it can cause differences in SSA_NAMEs and more importantly, the ipa references are generated from those before the DCE happens. On the testcase, the DEBUG_STMT value is (int)bar. We could generate DEBUG_STMTs with debug temporaries instead, but I fail to see the reason to do that, DEBUG_STMTs allow other expressions and all we want to ensure is that the expressions aren't too large (arbitrarily complex), but during inlining/function versioning I don't see why something would queue a DEBUG_STMT with arbitrarily complex expressions in there. 2020-03-16 Jakub Jelinek PR debug/94167 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands DEBUG_STMTs. * gcc.dg/pr94167.c: New test. --- gcc/ChangeLog | 4 ++++ gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.dg/pr94167.c | 33 +++++++++++++++++++++++++++++++++ gcc/tree-inline.c | 4 ++-- 4 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94167.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8709f0c..81582dd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2020-03-16 Jakub Jelinek + PR debug/94167 + * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands + DEBUG_STMTs. + PR tree-optimization/94166 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION as secondary comparison key. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d52cd1e..1297954 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-16 Jakub Jelinek + PR debug/94167 + * gcc.dg/pr94167.c: New test. + PR tree-optimization/94166 * gcc.dg/pr94166.c: New test. diff --git a/gcc/testsuite/gcc.dg/pr94167.c b/gcc/testsuite/gcc.dg/pr94167.c new file mode 100644 index 0000000..4b819d3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94167.c @@ -0,0 +1,33 @@ +/* PR debug/94167 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +struct S { int g, h; signed char i; int j; signed char k; int l[4]; } a, c; +struct T { signed char g; } e; +int *b, d; +static void foo (); + +void +bar (void) +{ + while (d) + { + int k; + struct T f[3]; + foo (bar, a); + for (k = 0;; k++) + f[k] = e; + } +} + +static inline void +foo (int x, struct S y, struct T z) +{ + for (z.g = 2; z.g; z.g--) + { + c = a = y; + *b |= 6; + if (y.g) + break; + } +} diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c index 59798ec..f095795 100644 --- a/gcc/tree-inline.c +++ b/gcc/tree-inline.c @@ -3361,10 +3361,10 @@ insert_init_stmt (copy_body_data *id, basic_block bb, gimple *init_stmt) gimple_assign_set_rhs1 (init_stmt, rhs); } gsi_insert_after (&si, init_stmt, GSI_NEW_STMT); - gimple_regimplify_operands (init_stmt, &si); - if (!is_gimple_debug (init_stmt)) { + gimple_regimplify_operands (init_stmt, &si); + tree def = gimple_assign_lhs (init_stmt); insert_init_debug_bind (id, bb, def, def, init_stmt); } -- cgit v1.1 From e41d4a0a567f1091f646d076d8c9fad91422572b Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Mon, 16 Mar 2020 09:48:54 +0100 Subject: d/dmd: Merge upstream dmd b061bd744 Fixes an ICE in the parser, and deprecates a previously allowed style of syntax that deviated from GNU-style extended asm. Reviewed-on: https://github.com/dlang/dmd/pull/10916 gcc/testsuite/ChangeLog: 2020-03-16 Iain Buclaw * gdc.dg/asm1.d: Add new test for ICE in asm parser. * gdc.dg/asm5.d: New test. --- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/iasmgcc.c | 30 +++++++++++++++++++++++++++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gdc.dg/asm1.d | 9 +++++++++ gcc/testsuite/gdc.dg/asm5.d | 12 ++++++++++++ 5 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gdc.dg/asm5.d (limited to 'gcc') diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index b017c03..6cbc4e3 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -e9420cfbf5cd0cf9e6e398603e009ccc8e14d324 +b061bd744cb4eb94a7118581387d988d4ec25e97 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/iasmgcc.c b/gcc/d/dmd/iasmgcc.c index cecbdef..5484533 100644 --- a/gcc/d/dmd/iasmgcc.c +++ b/gcc/d/dmd/iasmgcc.c @@ -13,6 +13,7 @@ #include "scope.h" #include "declaration.h" +#include "errors.h" #include "parse.h" #include "statement.h" @@ -23,8 +24,8 @@ Statement *semantic(Statement *s, Scope *sc); * Parse list of extended asm input or output operands. * Grammar: * | Operands: - * | SymbolicName(opt) StringLiteral AssignExpression - * | SymbolicName(opt) StringLiteral AssignExpression , Operands + * | SymbolicName(opt) StringLiteral ( AssignExpression ) + * | SymbolicName(opt) StringLiteral ( AssignExpression ), Operands * | * | SymbolicName: * | [ Identifier ] @@ -54,7 +55,9 @@ static int parseExtAsmOperands(Parser *p, GccAsmStatement *s) case TOKlbracket: if (p->peekNext() == TOKidentifier) { + // Skip over openings `[` p->nextToken(); + // Store the symbolic name name = p->token.ident; p->nextToken(); } @@ -63,12 +66,32 @@ static int parseExtAsmOperands(Parser *p, GccAsmStatement *s) p->error(s->loc, "expected identifier after `[`"); goto Lerror; } + // Look for closing `]` p->check(TOKrbracket); + // Look for the string literal and fall through + if (p->token.value != TOKstring) + goto Ldefault; // fall through case TOKstring: constraint = p->parsePrimaryExp(); - arg = p->parseAssignExp(); + // @@@DEPRECATED@@@ + // Old parser allowed omitting parentheses around the expression. + // Deprecated in 2.091. Can be made permanent error after 2.100 + if (p->token.value != TOKlparen) + { + arg = p->parseAssignExp(); + deprecation(arg->loc, "`%s` must be surrounded by parentheses", arg->toChars()); + } + else + { + // Look for the opening `(` + p->check(TOKlparen); + // Parse the assign expression + arg = p->parseAssignExp(); + // Look for the closing `)` + p->check(TOKrparen); + } if (!s->args) { @@ -86,6 +109,7 @@ static int parseExtAsmOperands(Parser *p, GccAsmStatement *s) break; default: + Ldefault: p->error("expected constant string constraint for operand, not `%s`", p->token.toChars()); goto Lerror; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1297954..0f87a04 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Iain Buclaw + + * gdc.dg/asm1.d: Add new test for ICE in asm parser. + * gdc.dg/asm5.d: New test. + 2020-03-16 Jakub Jelinek PR debug/94167 diff --git a/gcc/testsuite/gdc.dg/asm1.d b/gcc/testsuite/gdc.dg/asm1.d index 7b00e4d..3fcfd6a 100644 --- a/gcc/testsuite/gdc.dg/asm1.d +++ b/gcc/testsuite/gdc.dg/asm1.d @@ -29,6 +29,15 @@ void parse3() // { dg-error "found 'EOF' when expecting ';'" "" { target *-*-* } .-4 } } +void parse4() +{ + int expr; + asm + { + "%name" : [name] string (expr); // { dg-error "expected constant string constraint for operand, not 'string'" } + } +} + void semantic1() { { diff --git a/gcc/testsuite/gdc.dg/asm5.d b/gcc/testsuite/gdc.dg/asm5.d new file mode 100644 index 0000000..b525a21 --- /dev/null +++ b/gcc/testsuite/gdc.dg/asm5.d @@ -0,0 +1,12 @@ +// https://issues.dlang.org/show_bug.cgi?id=20593 +// { dg-do compile } +// { dg-options "-Wall -Wdeprecated -Werror" } +module asm5; + +void test(int a) +{ + asm + { + "cpuid" : : "a" a; // { dg-error "'a' must be surrounded by parentheses" } + } +} -- cgit v1.1 From 5a3c42b227bbe9e7acb5335088d2255262311bd8 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Mon, 16 Mar 2020 03:48:55 -0700 Subject: i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV There is no need to set mode attribute to XImode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. Remove ext_sse_reg_operand since it is no longer needed. gcc/ PR target/89229 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL check. * config/i386/predicates.md (ext_sse_reg_operand): Removed. gcc/testsuite/ PR target/89229 * gcc.target/i386/pr89229-7a.c: New test. * gcc.target/i386/pr89229-7b.c: Likewise. * gcc.target/i386/pr89229-7c.c: Likewise. --- gcc/ChangeLog | 8 ++++++++ gcc/config/i386/i386.md | 25 ++----------------------- gcc/config/i386/predicates.md | 5 ----- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/i386/pr89229-7a.c | 17 +++++++++++++++++ gcc/testsuite/gcc.target/i386/pr89229-7b.c | 6 ++++++ gcc/testsuite/gcc.target/i386/pr89229-7c.c | 7 +++++++ 7 files changed, 47 insertions(+), 28 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7c.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 81582dd..8ae1371 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-16 H.J. Lu + + PR target/89229 + * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov + for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL + check. + * config/i386/predicates.md (ext_sse_reg_operand): Removed. + 2020-03-16 Jakub Jelinek PR debug/94167 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index af39f90..3051624d 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2261,25 +2261,7 @@ gcc_unreachable (); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_SI: - return "%vmovd\t{%1, %0|%0, %1}"; - case MODE_TI: - return "%vmovdqa\t{%1, %0|%0, %1}"; - case MODE_XI: - return "vmovdqa32\t{%g1, %g0|%g0, %g1}"; - - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - case MODE_SF: - gcc_assert (!TARGET_AVX); - return "movss\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); case TYPE_MMX: return "pxor\t%0, %0"; @@ -2345,10 +2327,7 @@ (cond [(eq_attr "alternative" "2,3") (const_string "DI") (eq_attr "alternative" "8,9") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) - (const_string "XI") - (match_test "TARGET_AVX") + (cond [(match_test "TARGET_AVX") (const_string "TI") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 1119366..71f4cb1 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -61,11 +61,6 @@ (and (match_code "reg") (match_test "SSE_REGNO_P (REGNO (op))"))) -;; True if the operand is an AVX-512 new register. -(define_predicate "ext_sse_reg_operand" - (and (match_code "reg") - (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))"))) - ;; Return true if op is a QImode register. (define_predicate "any_QIreg_operand" (and (match_code "reg") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0f87a04..b133809 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-16 H.J. Lu + + PR target/89229 + * gcc.target/i386/pr89229-7a.c: New test. + * gcc.target/i386/pr89229-7b.c: Likewise. + * gcc.target/i386/pr89229-7c.c: Likewise. + 2020-03-16 Iain Buclaw * gdc.dg/asm1.d: Add new test for ICE in asm parser. diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7a.c b/gcc/testsuite/gcc.target/i386/pr89229-7a.c new file mode 100644 index 0000000..fd56f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-7a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512" } */ + +extern int i; + +int +foo1 (void) +{ + register int xmm16 __asm ("xmm16") = i; + asm volatile ("" : "+v" (xmm16)); + register int xmm17 __asm ("xmm17") = xmm16; + asm volatile ("" : "+v" (xmm17)); + return xmm17; +} + +/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7b.c b/gcc/testsuite/gcc.target/i386/pr89229-7b.c new file mode 100644 index 0000000..d3a56e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-7b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */ + +#include "pr89229-7a.c" + +/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7c.c b/gcc/testsuite/gcc.target/i386/pr89229-7c.c new file mode 100644 index 0000000..e14634e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-7c.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */ + +#include "pr89229-7a.c" + +/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ -- cgit v1.1 From f19b40bd377f0cf402bbfbf47596ef9c46563457 Mon Sep 17 00:00:00 2001 From: Aaron Sawdey Date: Mon, 16 Mar 2020 09:29:05 -0500 Subject: Fix ChangeLog formatting from my commit last friday. --- gcc/ChangeLog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8ae1371..cbeca73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -64,7 +64,7 @@ 2020-03-13 Aaron Sawdey PR target/92379 - * config/rs6000/rs6000.c (num_insns_constant_multi) Don't shift a + * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a 64-bit value by 64 bits (UB). 2020-03-13 Vladimir Makarov -- cgit v1.1 From 63c8f7d6a082b1cd0519fe06d4ed506b04280921 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 16 Mar 2020 17:06:29 +0000 Subject: [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. This patch creates the required framework for MVE ACLE intrinsics. The following changes are done in this patch to support MVE ACLE intrinsics. Header file arm_mve.h is added to source code, which contains the definitions of MVE ACLE intrinsics and different data types used in MVE. Machine description file mve.md is also added which contains the RTL patterns defined for MVE. A new reigster "p0" is added which is used in by MVE predicated patterns. A new register class "VPR_REG" is added and its contents are defined in REG_CLASS_CONTENTS. The vec-common.md file is modified to support the standard move patterns. The prefix of neon functions which are also used by MVE is changed from "neon_" to "simd_". eg: neon_immediate_valid_for_move changed to simd_immediate_valid_for_move. In the patch standard patterns mve_move, mve_store and move_load for MVE are added and neon.md and vfp.md files are modified to support this common patterns. Please refer to Arm reference manual [1] for more details. [1] https://developer.arm.com/docs/ddi0553/latest 2020-03-06 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config.gcc (arm_mve.h): Include mve intrinsics header file. * config/arm/aout.h (p0): Add new register name for MVE predicated cases. * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro common to Neon and MVE. (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. (arm_init_simd_builtin_types): Disable poly types for MVE. (arm_init_neon_builtins): Move a check to arm_init_builtins function. (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of ARM_BUILTIN_NEON_LANE_CHECK. (mve_dereference_pointer): Add function. (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is enabled. (arm_expand_neon_builtin): Moved to arm_expand_builtin function. (arm_expand_builtin): Moved from arm_expand_neon_builtin function. * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE with floating point enabled. * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Renamed from neon_immediate_valid_for_move function. * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate error if vfpv2 feature bit is disabled and mve feature bit is also disabled for HARD_FLOAT_ABI. (use_return_insn): Check to not push VFP regs for MVE. (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard as Neon. (aapcs_vfp_allocate_return_reg): Likewise. (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 address operand for MVE. (arm_rtx_costs_internal): MVE check to determine cost of rtx. (neon_valid_immediate): Rename to simd_valid_immediate. (simd_valid_immediate): Rename from neon_valid_immediate. (simd_valid_immediate): MVE check on size of vector is 128 bits. (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Rename from neon_immediate_valid_for_move. (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate function. (neon_make_constant): Modify call to neon_valid_immediate function. (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC for MVE. (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. (arm_compute_frame_layout): Calculate space for saved VFP registers for MVE. (arm_save_coproc_regs): Save coproc registers for MVE. (arm_print_operand): Add case 'E' to print memory operands for MVE. (arm_print_operand_address): Check to print register number for MVE. (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. (arm_modes_tieable_p): Check to allow structure mode for MVE. (arm_regno_class): Add VPR_REGNUM check. (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code for APCS frame. (arm_expand_epilogue): MVE check for enabling pop instructions in epilogue. (arm_print_asm_arch_directives): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". (arm_vector_mode_supported_p): Check for modes available in MVE interger and MVE floating point. (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode pointer support. (arm_conditional_register_usage): Enable usage of conditional regsiter for MVE. (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. (arm_declare_function_name): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and when target general registers are required. (TARGET_HAVE_MVE_FLOAT): Likewise. (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c for MVE. (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS which indicate this is not available for across function calls. (FIRST_PSEUDO_REGISTER): Modify. (VALID_MVE_MODE): Define valid MVE mode. (VALID_MVE_SI_MODE): Define valid MVE SI mode. (VALID_MVE_SF_MODE): Define valid MVE SF mode. (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence for MVE. (IS_VPR_REGNUM): Macro to check for VPR_REG register. (REG_ALLOC_ORDER): Add VPR_REGNUM entry. (enum reg_class): Add VPR_REG entry. (REG_CLASS_NAMES): Add VPR_REG entry. * config/arm/arm.md (VPR_REGNUM): Define. (conds): Check is_mve_type attrbiute to differentiate "conditional" and "unconditional" instructions. (arm_movsf_soft_insn): Modify RTL to not allow for MVE. (movdf_soft_insn): Modify RTL to not allow for MVE. (vfp_pop_multiple_with_writeback): Enable for MVE. (include "mve.md"): Include mve.md file. * config/arm/arm_mve.h: Add MVE intrinsics head file. * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE for vector predicated operands. * config/arm/iterators.md (VNIM1): Define. (VNINOTM1): Define. (VHFBF_split): Define * config/arm/mve.md: New file. (mve_mov): Define RTL for move, store and load in MVE. (mve_mov): Define move RTL pattern with vec_duplicate operator for second operand. * config/arm/neon.md (neon_immediate_valid_for_move): Rename with simd_immediate_valid_for_move. (neon_mov): Split pattern and move expand pattern "movv8hf" which is common to MVE and NEON to vec-common.md file. (vec_init): Add TARGET_HAVE_MVE check. * config/arm/predicates.md (vpr_register_operand): Define. * config/arm/t-arm: Add mve.md file. * config/arm/types.md (mve_move): Add MVE instructions mve_move to attribute "type". (mve_store): Add MVE instructions mve_store to attribute "type". (mve_load): Add MVE instructions mve_load to attribute "type". (is_mve_type): Define attribute. * config/arm/vec-common.md (mov): Modify RTL expand to support standard move patterns in MVE along with NEON and IWMMXT with mode iterator VNIM1. (mov): Modify RTL expand to support standard move patterns in NEON and IWMMXT with mode iterator V8HF. (movv8hf): Define RTL expand to support standard "movv8hf" pattern in NEON and MVE. * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test. * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. * gcc.target/arm/mve/mve.exp: New file. * lib/target-supports.exp (check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check armv8.1-m.main+mve.fp and returning corresponding options. (check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of MVE with floating point on the current target. (add_options_for_arm_v8_1m_mve_fp): Proc to call check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding compiler options for MVE with floating point. (check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and return hard float-abi on success. --- gcc/ChangeLog | 131 +++++++++++ gcc/config.gcc | 2 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 166 ++++++++----- gcc/config/arm/arm-c.c | 10 + gcc/config/arm/arm-protos.h | 2 +- gcc/config/arm/arm.c | 261 ++++++++++++++++----- gcc/config/arm/arm.h | 51 +++- gcc/config/arm/arm.md | 21 +- gcc/config/arm/arm_mve.h | 59 +++++ gcc/config/arm/constraints.md | 4 +- gcc/config/arm/iterators.md | 10 + gcc/config/arm/mve.md | 85 +++++++ gcc/config/arm/neon.md | 14 +- gcc/config/arm/predicates.md | 10 +- gcc/config/arm/t-arm | 1 + gcc/config/arm/types.md | 18 +- gcc/config/arm/vec-common.md | 41 +++- gcc/config/arm/vfp.md | 2 +- gcc/testsuite/ChangeLog | 26 ++ .../arm/mve/intrinsics/mve_vector_float.c | 27 +++ .../arm/mve/intrinsics/mve_vector_float1.c | 31 +++ .../arm/mve/intrinsics/mve_vector_float2.c | 27 +++ .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 49 ++++ .../arm/mve/intrinsics/mve_vector_int1.c | 54 +++++ .../arm/mve/intrinsics/mve_vector_int2.c | 49 ++++ .../arm/mve/intrinsics/mve_vector_uint.c | 49 ++++ .../arm/mve/intrinsics/mve_vector_uint1.c | 54 +++++ .../arm/mve/intrinsics/mve_vector_uint2.c | 49 ++++ gcc/testsuite/gcc.target/arm/mve/mve.exp | 47 ++++ gcc/testsuite/lib/target-supports.exp | 45 +++- 31 files changed, 1249 insertions(+), 152 deletions(-) create mode 100644 gcc/config/arm/arm_mve.h create mode 100644 gcc/config/arm/mve.md create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve.exp (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cbeca73..e814da1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,134 @@ +2020-03-16 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config.gcc (arm_mve.h): Include mve intrinsics header file. + * config/arm/aout.h (p0): Add new register name for MVE predicated + cases. + * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro + common to Neon and MVE. + (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. + (arm_init_simd_builtin_types): Disable poly types for MVE. + (arm_init_neon_builtins): Move a check to arm_init_builtins function. + (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of + ARM_BUILTIN_NEON_LANE_CHECK. + (mve_dereference_pointer): Add function. + (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is + enabled. + (arm_expand_neon_builtin): Moved to arm_expand_builtin function. + (arm_expand_builtin): Moved from arm_expand_neon_builtin function. + * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE + with floating point enabled. + * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to + simd_immediate_valid_for_move. + (simd_immediate_valid_for_move): Renamed from + neon_immediate_valid_for_move function. + * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate + error if vfpv2 feature bit is disabled and mve feature bit is also + disabled for HARD_FLOAT_ABI. + (use_return_insn): Check to not push VFP regs for MVE. + (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard + as Neon. + (aapcs_vfp_allocate_return_reg): Likewise. + (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 + address operand for MVE. + (arm_rtx_costs_internal): MVE check to determine cost of rtx. + (neon_valid_immediate): Rename to simd_valid_immediate. + (simd_valid_immediate): Rename from neon_valid_immediate. + (simd_valid_immediate): MVE check on size of vector is 128 bits. + (neon_immediate_valid_for_move): Rename to + simd_immediate_valid_for_move. + (simd_immediate_valid_for_move): Rename from + neon_immediate_valid_for_move. + (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate + function. + (neon_make_constant): Modify call to neon_valid_immediate function. + (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC + for MVE. + (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. + (arm_compute_frame_layout): Calculate space for saved VFP registers for + MVE. + (arm_save_coproc_regs): Save coproc registers for MVE. + (arm_print_operand): Add case 'E' to print memory operands for MVE. + (arm_print_operand_address): Check to print register number for MVE. + (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. + (arm_modes_tieable_p): Check to allow structure mode for MVE. + (arm_regno_class): Add VPR_REGNUM check. + (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code + for APCS frame. + (arm_expand_epilogue): MVE check for enabling pop instructions in + epilogue. + (arm_print_asm_arch_directives): Modify function to disable print of + .arch_extension "mve" and "fp" for cases where MVE is enabled with + "SOFT FLOAT ABI". + (arm_vector_mode_supported_p): Check for modes available in MVE interger + and MVE floating point. + (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode + pointer support. + (arm_conditional_register_usage): Enable usage of conditional regsiter + for MVE. + (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. + (arm_declare_function_name): Modify function to disable print of + .arch_extension "mve" and "fp" for cases where MVE is enabled with + "SOFT FLOAT ABI". + * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and + when target general registers are required. + (TARGET_HAVE_MVE_FLOAT): Likewise. + (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c + for MVE. + (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS + which indicate this is not available for across function calls. + (FIRST_PSEUDO_REGISTER): Modify. + (VALID_MVE_MODE): Define valid MVE mode. + (VALID_MVE_SI_MODE): Define valid MVE SI mode. + (VALID_MVE_SF_MODE): Define valid MVE SF mode. + (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. + (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence + for MVE. + (IS_VPR_REGNUM): Macro to check for VPR_REG register. + (REG_ALLOC_ORDER): Add VPR_REGNUM entry. + (enum reg_class): Add VPR_REG entry. + (REG_CLASS_NAMES): Add VPR_REG entry. + * config/arm/arm.md (VPR_REGNUM): Define. + (conds): Check is_mve_type attrbiute to differentiate "conditional" and + "unconditional" instructions. + (arm_movsf_soft_insn): Modify RTL to not allow for MVE. + (movdf_soft_insn): Modify RTL to not allow for MVE. + (vfp_pop_multiple_with_writeback): Enable for MVE. + (include "mve.md"): Include mve.md file. + * config/arm/arm_mve.h: Add MVE intrinsics head file. + * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE + for vector predicated operands. + * config/arm/iterators.md (VNIM1): Define. + (VNINOTM1): Define. + (VHFBF_split): Define + * config/arm/mve.md: New file. + (mve_mov): Define RTL for move, store and load in MVE. + (mve_mov): Define move RTL pattern with vec_duplicate operator for + second operand. + * config/arm/neon.md (neon_immediate_valid_for_move): Rename with + simd_immediate_valid_for_move. + (neon_mov): Split pattern and move expand pattern "movv8hf" which + is common to MVE and NEON to vec-common.md file. + (vec_init): Add TARGET_HAVE_MVE check. + * config/arm/predicates.md (vpr_register_operand): Define. + * config/arm/t-arm: Add mve.md file. + * config/arm/types.md (mve_move): Add MVE instructions mve_move to + attribute "type". + (mve_store): Add MVE instructions mve_store to attribute "type". + (mve_load): Add MVE instructions mve_load to attribute "type". + (is_mve_type): Define attribute. + * config/arm/vec-common.md (mov): Modify RTL expand to support + standard move patterns in MVE along with NEON and IWMMXT with mode + iterator VNIM1. + (mov): Modify RTL expand to support standard move patterns in NEON + and IWMMXT with mode iterator V8HF. + (movv8hf): Define RTL expand to support standard "movv8hf" pattern in + NEON and MVE. + * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to + simd_immediate_valid_for_move. + + 2020-03-16 H.J. Lu PR target/89229 diff --git a/gcc/config.gcc b/gcc/config.gcc index 2df4b36..13e3cb7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -346,7 +346,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index 88d85ea..afcef1d 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -53,7 +53,9 @@ /* The assembler's names for the registers. Note that the ?xx registers are there so that VFPv3/NEON registers D16-D31 have the same spacing as D0-D15 (each of which is overlaid on two S registers), although there are no - actual single-precision registers which correspond to D16-D31. */ + actual single-precision registers which correspond to D16-D31. New register + p0 is added which is used for MVE predicated cases. */ + #ifndef REGISTER_NAMES #define REGISTER_NAMES \ { \ @@ -72,7 +74,7 @@ "wr8", "wr9", "wr10", "wr11", \ "wr12", "wr13", "wr14", "wr15", \ "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ - "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge" \ + "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \ } #endif diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 1f55898..1a9a38d 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -698,6 +698,7 @@ enum arm_builtins ARM_BUILTIN_SET_FPSCR, ARM_BUILTIN_CMSE_NONSECURE_CALLER, + ARM_BUILTIN_SIMD_LANE_CHECK, #undef CRYPTO1 #undef CRYPTO2 @@ -723,7 +724,6 @@ enum arm_builtins #include "arm_vfp_builtins.def" ARM_BUILTIN_NEON_BASE, - ARM_BUILTIN_NEON_LANE_CHECK = ARM_BUILTIN_NEON_BASE, #include "arm_neon_builtins.def" @@ -987,28 +987,37 @@ arm_init_simd_builtin_types (void) an entry in our mangling table, consequently, they get default mangling. As a further gotcha, poly8_t and poly16_t are signed types, poly64_t and poly128_t are unsigned types. */ - arm_simd_polyQI_type_node - = build_distinct_type_copy (intQI_type_node); - (*lang_hooks.types.register_builtin_type) (arm_simd_polyQI_type_node, - "__builtin_neon_poly8"); - arm_simd_polyHI_type_node - = build_distinct_type_copy (intHI_type_node); - (*lang_hooks.types.register_builtin_type) (arm_simd_polyHI_type_node, - "__builtin_neon_poly16"); - arm_simd_polyDI_type_node - = build_distinct_type_copy (unsigned_intDI_type_node); - (*lang_hooks.types.register_builtin_type) (arm_simd_polyDI_type_node, - "__builtin_neon_poly64"); - arm_simd_polyTI_type_node - = build_distinct_type_copy (unsigned_intTI_type_node); - (*lang_hooks.types.register_builtin_type) (arm_simd_polyTI_type_node, - "__builtin_neon_poly128"); - - /* Prevent front-ends from transforming poly vectors into string - literals. */ - TYPE_STRING_FLAG (arm_simd_polyQI_type_node) = false; - TYPE_STRING_FLAG (arm_simd_polyHI_type_node) = false; - + if (!TARGET_HAVE_MVE) + { + arm_simd_polyQI_type_node + = build_distinct_type_copy (intQI_type_node); + (*lang_hooks.types.register_builtin_type) (arm_simd_polyQI_type_node, + "__builtin_neon_poly8"); + arm_simd_polyHI_type_node + = build_distinct_type_copy (intHI_type_node); + (*lang_hooks.types.register_builtin_type) (arm_simd_polyHI_type_node, + "__builtin_neon_poly16"); + arm_simd_polyDI_type_node + = build_distinct_type_copy (unsigned_intDI_type_node); + (*lang_hooks.types.register_builtin_type) (arm_simd_polyDI_type_node, + "__builtin_neon_poly64"); + arm_simd_polyTI_type_node + = build_distinct_type_copy (unsigned_intTI_type_node); + (*lang_hooks.types.register_builtin_type) (arm_simd_polyTI_type_node, + "__builtin_neon_poly128"); + /* Init poly vector element types with scalar poly types. */ + arm_simd_types[Poly8x8_t].eltype = arm_simd_polyQI_type_node; + arm_simd_types[Poly8x16_t].eltype = arm_simd_polyQI_type_node; + arm_simd_types[Poly16x4_t].eltype = arm_simd_polyHI_type_node; + arm_simd_types[Poly16x8_t].eltype = arm_simd_polyHI_type_node; + /* Note: poly64x2_t is defined in arm_neon.h, to ensure it gets default + mangling. */ + + /* Prevent front-ends from transforming poly vectors into string + literals. */ + TYPE_STRING_FLAG (arm_simd_polyQI_type_node) = false; + TYPE_STRING_FLAG (arm_simd_polyHI_type_node) = false; + } /* Init all the element types built by the front-end. */ arm_simd_types[Int8x8_t].eltype = intQI_type_node; arm_simd_types[Int8x16_t].eltype = intQI_type_node; @@ -1025,11 +1034,6 @@ arm_init_simd_builtin_types (void) arm_simd_types[Uint32x4_t].eltype = unsigned_intSI_type_node; arm_simd_types[Uint64x2_t].eltype = unsigned_intDI_type_node; - /* Init poly vector element types with scalar poly types. */ - arm_simd_types[Poly8x8_t].eltype = arm_simd_polyQI_type_node; - arm_simd_types[Poly8x16_t].eltype = arm_simd_polyQI_type_node; - arm_simd_types[Poly16x4_t].eltype = arm_simd_polyHI_type_node; - arm_simd_types[Poly16x8_t].eltype = arm_simd_polyHI_type_node; /* Note: poly64x2_t is defined in arm_neon.h, to ensure it gets default mangling. */ @@ -1051,6 +1055,8 @@ arm_init_simd_builtin_types (void) tree eltype = arm_simd_types[i].eltype; machine_mode mode = arm_simd_types[i].mode; + if (eltype == NULL) + continue; if (arm_simd_types[i].itype == NULL) arm_simd_types[i].itype = build_distinct_type_copy @@ -1290,15 +1296,6 @@ arm_init_neon_builtins (void) system. */ arm_init_simd_builtin_scalar_types (); - tree lane_check_fpr = build_function_type_list (void_type_node, - intSI_type_node, - intSI_type_node, - NULL); - arm_builtin_decls[ARM_BUILTIN_NEON_LANE_CHECK] = - add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr, - ARM_BUILTIN_NEON_LANE_CHECK, BUILT_IN_MD, - NULL, NULL_TREE); - for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++) { arm_builtin_datum *d = &neon_builtin_data[i]; @@ -2017,6 +2014,15 @@ arm_init_builtins (void) if (TARGET_MAYBE_HARD_FLOAT) { + tree lane_check_fpr = build_function_type_list (void_type_node, + intSI_type_node, + intSI_type_node, + NULL); + arm_builtin_decls[ARM_BUILTIN_SIMD_LANE_CHECK] + = add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr, + ARM_BUILTIN_SIMD_LANE_CHECK, BUILT_IN_MD, + NULL, NULL_TREE); + arm_init_neon_builtins (); arm_init_vfp_builtins (); arm_init_crypto_builtins (); @@ -2263,6 +2269,47 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode, build_int_cst (build_pointer_type (array_type), 0)); } +/* EXP is a pointer argument to a vector scatter store intrinsics. + + Consider the following example: + VSTRW.
Qd, [Qm{, #+/-}]! + When used as the base register for the target address, + this function is used to derive and return an expression for the + accessed memory. + + The intrinsic function operates on a block of registers that has mode + REG_MODE. This block contains vectors of type TYPE_MODE. The function + references the memory at EXP of type TYPE and in mode MEM_MODE. This + mode may be BLKmode if no more suitable mode is available. */ + +static tree +mve_dereference_pointer (tree exp, tree type, machine_mode reg_mode, + machine_mode vector_mode) +{ + HOST_WIDE_INT reg_size, vector_size, nelems; + tree elem_type, upper_bound, array_type; + + /* Work out the size of each vector in bytes. */ + vector_size = GET_MODE_SIZE (vector_mode); + + /* Work out the size of the register block in bytes. */ + reg_size = GET_MODE_SIZE (reg_mode); + + /* Work out the type of each element. */ + gcc_assert (POINTER_TYPE_P (type)); + elem_type = TREE_TYPE (type); + + nelems = reg_size / vector_size; + + /* Create a type that describes the full access. */ + upper_bound = build_int_cst (size_type_node, nelems - 1); + array_type = build_array_type (elem_type, build_index_type (upper_bound)); + + /* Dereference EXP using that type. */ + return fold_build2 (MEM_REF, array_type, exp, + build_int_cst (build_pointer_type (array_type), 0)); +} + /* Expand a builtin. */ static rtx arm_expand_builtin_args (rtx target, machine_mode map_mode, int fcode, @@ -2301,10 +2348,17 @@ arm_expand_builtin_args (rtx target, machine_mode map_mode, int fcode, { machine_mode other_mode = insn_data[icode].operand[1 - opno].mode; - arg[argc] = neon_dereference_pointer (arg[argc], + if (TARGET_HAVE_MVE && mode[argc] != other_mode) + { + arg[argc] = mve_dereference_pointer (arg[argc], TREE_VALUE (formals), - mode[argc], other_mode, - map_mode); + other_mode, map_mode); + } + else + arg[argc] = neon_dereference_pointer (arg[argc], + TREE_VALUE (formals), + mode[argc], other_mode, + map_mode); } /* Use EXPAND_MEMORY for ARG_BUILTIN_MEMORY and @@ -2625,22 +2679,6 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target) return const0_rtx; } - if (fcode == ARM_BUILTIN_NEON_LANE_CHECK) - { - /* Builtin is only to check bounds of the lane passed to some intrinsics - that are implemented with gcc vector extensions in arm_neon.h. */ - - tree nlanes = CALL_EXPR_ARG (exp, 0); - gcc_assert (TREE_CODE (nlanes) == INTEGER_CST); - rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1)); - if (CONST_INT_P (lane_idx)) - neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp); - else - error ("%Klane index must be a constant immediate", exp); - /* Don't generate any RTL. */ - return const0_rtx; - } - arm_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START]; @@ -2702,6 +2740,22 @@ arm_expand_builtin (tree exp, int mask; int imm; + if (fcode == ARM_BUILTIN_SIMD_LANE_CHECK) + { + /* Builtin is only to check bounds of the lane passed to some intrinsics + that are implemented with gcc vector extensions in arm_neon.h. */ + + tree nlanes = CALL_EXPR_ARG (exp, 0); + gcc_assert (TREE_CODE (nlanes) == INTEGER_CST); + rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1)); + if (CONST_INT_P (lane_idx)) + neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp); + else + error ("%Klane index must be a constant immediate", exp); + /* Don't generate any RTL. */ + return const0_rtx; + } + if (fcode >= ARM_BUILTIN_ACLE_BASE) return arm_expand_acle_builtin (fcode, exp, target); diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 38edaff..73bdb9c 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -79,6 +79,16 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX); def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); + cpp_undef (pfile, "__ARM_FEATURE_MVE"); + if (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT) + { + builtin_define_with_int_value ("__ARM_FEATURE_MVE", 3); + } + else if (TARGET_HAVE_MVE) + { + builtin_define_with_int_value ("__ARM_FEATURE_MVE", 1); + } + cpp_undef (pfile, "__ARM_FEATURE_CMSE"); if (arm_arch8 && !arm_arch_notm) { diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index eaff654..b6710a6 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -86,7 +86,7 @@ extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode, extern bool clear_operation_p (rtx, bool); extern int arm_const_double_rtx (rtx); extern int vfp3_const_double_rtx (rtx); -extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *); +extern int simd_immediate_valid_for_move (rtx, machine_mode, rtx *, int *); extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *, int *); extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *, diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9cc7bc0..c769104 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3823,7 +3823,8 @@ arm_options_perform_arch_sanity_checks (void) else if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; - if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) + if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2) + && !bitmap_bit_p (arm_active_target.isa, isa_bit_mve)) error ("%<-mfloat-abi=hard%>: selected processor lacks an FPU"); } else @@ -4294,7 +4295,7 @@ use_return_insn (int iscond, rtx sibling) /* Can't be done if any of the VFP regs are pushed, since this also requires an insn. */ - if (TARGET_HARD_FLOAT) + if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) if (df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno)) return 0; @@ -6385,7 +6386,7 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode, { pcum->aapcs_vfp_reg_alloc = mask << regno; if (mode == BLKmode - || (mode == TImode && ! TARGET_NEON) + || (mode == TImode && ! (TARGET_NEON || TARGET_HAVE_MVE)) || ! arm_hard_regno_mode_ok (FIRST_VFP_REGNUM + regno, mode)) { int i; @@ -6393,7 +6394,7 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode, int rshift = shift; machine_mode rmode = pcum->aapcs_vfp_rmode; rtx par; - if (!TARGET_NEON) + if (!(TARGET_NEON || TARGET_HAVE_MVE)) { /* Avoid using unsupported vector modes. */ if (rmode == V2SImode) @@ -6439,7 +6440,7 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, if (mode == BLKmode || (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_SIZE (mode) >= GET_MODE_SIZE (TImode) - && !TARGET_NEON)) + && !(TARGET_NEON || TARGET_HAVE_MVE))) { int count; machine_mode ag_mode; @@ -6450,7 +6451,7 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type, &ag_mode, &count); - if (!TARGET_NEON) + if (!(TARGET_NEON || TARGET_HAVE_MVE)) { if (ag_mode == V2SImode) ag_mode = DImode; @@ -8349,7 +8350,9 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p) && CONST_INT_P (XEXP (XEXP (x, 0), 1))))) return 1; - else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) + else if (mode == TImode + || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)) + || (TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE (mode))) return 0; else if (code == PLUS) @@ -9902,7 +9905,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, /* Assume that most copies can be done with a single insn, unless we don't have HW FP, in which case everything larger than word mode will require two insns. */ - *cost = COSTS_N_INSNS (((!TARGET_HARD_FLOAT + *cost = COSTS_N_INSNS (((!(TARGET_HARD_FLOAT || TARGET_HAVE_MVE) && GET_MODE_SIZE (mode) > 4) || mode == DImode) ? 2 : 1); @@ -11383,10 +11386,10 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, case CONST_VECTOR: /* Fixme. */ - if (TARGET_NEON - && TARGET_HARD_FLOAT - && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) - && neon_immediate_valid_for_move (x, mode, NULL, NULL)) + if (((TARGET_NEON && TARGET_HARD_FLOAT + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) + || TARGET_HAVE_MVE) + && simd_immediate_valid_for_move (x, mode, NULL, NULL)) *cost = COSTS_N_INSNS (1); else *cost = COSTS_N_INSNS (4); @@ -12430,8 +12433,8 @@ vfp3_const_double_rtx (rtx x) return vfp3_const_double_index (x) != -1; } -/* Recognize immediates which can be used in various Neon instructions. Legal - immediates are described by the following table (for VMVN variants, the +/* Recognize immediates which can be used in various Neon and MVE instructions. + Legal immediates are described by the following table (for VMVN variants, the bitwise inverse of the constant shown is recognized. In either case, VMOV is output and the correct instruction to use for a given constant is chosen by the assembler). The constant shown is replicated across all elements of @@ -12482,7 +12485,7 @@ vfp3_const_double_rtx (rtx x) -1 if the given value doesn't match any of the listed patterns. */ static int -neon_valid_immediate (rtx op, machine_mode mode, int inverse, +simd_valid_immediate (rtx op, machine_mode mode, int inverse, rtx *modconst, int *elementwidth) { #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ @@ -12514,6 +12517,10 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse, innersize = GET_MODE_UNIT_SIZE (mode); + /* Only support 128-bit vectors for MVE. */ + if (TARGET_HAVE_MVE && (!vector || n_elts * innersize != 16)) + return -1; + /* Vectors of float constants. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) { @@ -12662,18 +12669,19 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse, #undef CHECK } -/* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, - VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for - float elements), and a modified constant (whatever should be output for a - VMOV) in *MODCONST. */ - +/* Return TRUE if rtx X is legal for use as either a Neon or MVE VMOV (or, + implicitly, VMVN) immediate. Write back width per element to *ELEMENTWIDTH + (or zero for float elements), and a modified constant (whatever should be + output for a VMOV) in *MODCONST. "neon_immediate_valid_for_move" function is + modified to "simd_immediate_valid_for_move" as this function will be used + both by neon and mve. */ int -neon_immediate_valid_for_move (rtx op, machine_mode mode, +simd_immediate_valid_for_move (rtx op, machine_mode mode, rtx *modconst, int *elementwidth) { rtx tmpconst; int tmpwidth; - int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); + int retval = simd_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); if (retval == -1) return 0; @@ -12690,7 +12698,7 @@ neon_immediate_valid_for_move (rtx op, machine_mode mode, /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If the immediate is valid, write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to - *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ + *ELEMENTWIDTH. See simd_valid_immediate for description of INVERSE. */ int neon_immediate_valid_for_logic (rtx op, machine_mode mode, int inverse, @@ -12698,7 +12706,7 @@ neon_immediate_valid_for_logic (rtx op, machine_mode mode, int inverse, { rtx tmpconst; int tmpwidth; - int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); + int retval = simd_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); if (retval < 0 || retval > 5) return 0; @@ -12905,7 +12913,7 @@ neon_make_constant (rtx vals) gcc_unreachable (); if (const_vec != NULL - && neon_immediate_valid_for_move (const_vec, mode, NULL, NULL)) + && simd_immediate_valid_for_move (const_vec, mode, NULL, NULL)) /* Load using VMOV. On Cortex-A8 this takes one cycle. */ return const_vec; else if ((target = neon_vdup_constant (vals)) != NULL_RTX) @@ -13182,6 +13190,15 @@ neon_vector_mem_operand (rtx op, int type, bool strict) && (INTVAL (XEXP (ind, 1)) & 3) == 0) return TRUE; + if (type == 1 && TARGET_HAVE_MVE + && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) + { + rtx ind1 = XEXP (ind, 0); + if (!REG_P (ind1)) + return 0; + return VFP_REGNO_OK_FOR_SINGLE (REGNO (ind1)); + } + return FALSE; } @@ -20050,7 +20067,7 @@ output_move_neon (rtx *operands) { case POST_INC: /* We have to use vldm / vstm for too-large modes. */ - if (nregs > 4) + if (nregs > 4 || (TARGET_HAVE_MVE && nregs >= 2)) { templ = "v%smia%%?\t%%0!, %%h1"; ops[0] = XEXP (addr, 0); @@ -20079,7 +20096,7 @@ output_move_neon (rtx *operands) /* We have to use vldm / vstm for too-large modes. */ if (nregs > 1) { - if (nregs > 4) + if (nregs > 4 || (TARGET_HAVE_MVE && nregs >= 2)) templ = "v%smia%%?\t%%m0, %%h1"; else templ = "v%s1.64\t%%h1, %%A0"; @@ -20094,29 +20111,47 @@ output_move_neon (rtx *operands) { int i; int overlap = -1; - for (i = 0; i < nregs; i++) + if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN + && GET_CODE (addr) != LABEL_REF) + { + sprintf (buff, "v%srw.32\t%%q0, %%1", load ? "ld" : "st"); + ops[0] = reg; + ops[1] = mem; + output_asm_insn (buff, ops); + } + else { - /* We're only using DImode here because it's a convenient size. */ - ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); - ops[1] = adjust_address (mem, DImode, 8 * i); - if (reg_overlap_mentioned_p (ops[0], mem)) + for (i = 0; i < nregs; i++) { - gcc_assert (overlap == -1); - overlap = i; + /* We're only using DImode here because it's a convenient + size. */ + ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); + ops[1] = adjust_address (mem, DImode, 8 * i); + if (reg_overlap_mentioned_p (ops[0], mem)) + { + gcc_assert (overlap == -1); + overlap = i; + } + else + { + if (TARGET_HAVE_MVE && GET_CODE (addr) == LABEL_REF) + sprintf (buff, "v%sr.64\t%%P0, %%1", load ? "ld" : "st"); + else + sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); + output_asm_insn (buff, ops); + } } - else + if (overlap != -1) { - sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); + ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); + ops[1] = adjust_address (mem, SImode, 8 * overlap); + if (TARGET_HAVE_MVE && GET_CODE (addr) == LABEL_REF) + sprintf (buff, "v%sr.32\t%%P0, %%1", load ? "ld" : "st"); + else + sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); output_asm_insn (buff, ops); } } - if (overlap != -1) - { - ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); - ops[1] = adjust_address (mem, SImode, 8 * overlap); - sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); - output_asm_insn (buff, ops); - } return ""; } @@ -22329,7 +22364,7 @@ arm_compute_frame_layout (void) func_type = arm_current_func_type (); /* Space for saved VFP registers. */ if (! IS_VOLATILE (func_type) - && TARGET_HARD_FLOAT) + && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)) saved += arm_get_vfp_saved_size (); /* Allocate space for saving/restoring FPCXTNS in Armv8.1-M Mainline @@ -22553,7 +22588,7 @@ arm_save_coproc_regs(void) saved_size += 8; } - if (TARGET_HARD_FLOAT) + if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) { start_reg = FIRST_VFP_REGNUM; @@ -23858,6 +23893,53 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + /* To print the memory operand with "Us" constraint. Based on the rtx_code + the memory operands output looks like following. + 1. [Rn], #+/- + 2. [Rn, #+/-]! + 3. [Rn]. */ + case 'E': + { + rtx addr; + rtx postinc_reg = NULL; + unsigned inc_val = 0; + enum rtx_code code; + + gcc_assert (MEM_P (x)); + addr = XEXP (x, 0); + code = GET_CODE (addr); + if (code == POST_INC || code == POST_DEC || code == PRE_INC + || code == PRE_DEC) + { + asm_fprintf (stream, "[%r", REGNO (XEXP (addr, 0))); + inc_val = GET_MODE_SIZE (GET_MODE (x)); + if (code == POST_INC || code == POST_DEC) + asm_fprintf (stream, "], #%s%d",(code == POST_INC) + ? "": "-", inc_val); + else + asm_fprintf (stream, ", #%s%d]!",(code == PRE_INC) + ? "": "-", inc_val); + } + else if (code == POST_MODIFY || code == PRE_MODIFY) + { + asm_fprintf (stream, "[%r", REGNO (XEXP (addr, 0))); + postinc_reg = XEXP ( XEXP (x, 1), 1); + if (postinc_reg && CONST_INT_P (postinc_reg)) + { + if (code == POST_MODIFY) + asm_fprintf (stream, "], #%wd",INTVAL (postinc_reg)); + else + asm_fprintf (stream, ", #%wd]!",INTVAL (postinc_reg)); + } + } + else + { + gcc_assert (REG_P (addr)); + asm_fprintf (stream, "[%r]",REGNO (addr)); + } + } + return; + case 'C': { rtx addr; @@ -24035,9 +24117,10 @@ arm_print_operand_address (FILE *stream, machine_mode mode, rtx x) REGNO (XEXP (x, 0)), GET_CODE (x) == PRE_DEC ? "-" : "", GET_MODE_SIZE (mode)); + else if (TARGET_HAVE_MVE && (mode == OImode || mode == XImode)) + asm_fprintf (stream, "[%r]!", REGNO (XEXP (x,0))); else - asm_fprintf (stream, "[%r], #%s%d", - REGNO (XEXP (x, 0)), + asm_fprintf (stream, "[%r], #%s%d", REGNO (XEXP (x, 0)), GET_CODE (x) == POST_DEC ? "-" : "", GET_MODE_SIZE (mode)); } @@ -24882,12 +24965,15 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) { if (GET_MODE_CLASS (mode) == MODE_CC) return (regno == CC_REGNUM - || (TARGET_HARD_FLOAT + || ((TARGET_HARD_FLOAT || TARGET_HAVE_MVE) && regno == VFPCC_REGNUM)); if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC) return false; + if (IS_VPR_REGNUM (regno)) + return true; + if (TARGET_THUMB1) /* For the Thumb we only allow values bigger than SImode in registers 0 - 6, so that there is always a second low @@ -24896,7 +24982,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) start of an even numbered register pair. */ return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); - if (TARGET_HARD_FLOAT && IS_VFP_REGNUM (regno)) + if ((TARGET_HARD_FLOAT || TARGET_HAVE_MVE) && IS_VFP_REGNUM (regno)) { if (mode == DFmode) return VFP_REGNO_OK_FOR_DOUBLE (regno); @@ -24914,6 +25000,10 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); + if (TARGET_HAVE_MVE) + return ((VALID_MVE_MODE (mode) && NEON_REGNO_OK_FOR_QUAD (regno)) + || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) + || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8))); return false; } @@ -24963,13 +25053,18 @@ arm_modes_tieable_p (machine_mode mode1, machine_mode mode2) /* We specifically want to allow elements of "structure" modes to be tieable to the structure. This more general condition allows other rarer situations too. */ - if (TARGET_NEON - && (VALID_NEON_DREG_MODE (mode1) - || VALID_NEON_QREG_MODE (mode1) - || VALID_NEON_STRUCT_MODE (mode1)) - && (VALID_NEON_DREG_MODE (mode2) - || VALID_NEON_QREG_MODE (mode2) - || VALID_NEON_STRUCT_MODE (mode2))) + if ((TARGET_NEON + && (VALID_NEON_DREG_MODE (mode1) + || VALID_NEON_QREG_MODE (mode1) + || VALID_NEON_STRUCT_MODE (mode1)) + && (VALID_NEON_DREG_MODE (mode2) + || VALID_NEON_QREG_MODE (mode2) + || VALID_NEON_STRUCT_MODE (mode2))) + || (TARGET_HAVE_MVE + && (VALID_MVE_MODE (mode1) + || VALID_MVE_STRUCT_MODE (mode1)) + && (VALID_MVE_MODE (mode2) + || VALID_MVE_STRUCT_MODE (mode2)))) return true; return false; @@ -24984,6 +25079,9 @@ arm_regno_class (int regno) if (regno == PC_REGNUM) return NO_REGS; + if (IS_VPR_REGNUM (regno)) + return VPR_REG; + if (TARGET_THUMB1) { if (regno == STACK_POINTER_REGNUM) @@ -26835,7 +26933,7 @@ arm_expand_epilogue_apcs_frame (bool really_return) floats_from_frame += 4; } - if (TARGET_HARD_FLOAT) + if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) { int start_reg; rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); @@ -27081,7 +27179,7 @@ arm_expand_epilogue (bool really_return) } } - if (TARGET_HARD_FLOAT) + if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) { /* Generate VFP register multi-pop. */ int end_reg = LAST_VFP_REGNUM + 1; @@ -27255,7 +27353,7 @@ arm_expand_epilogue (bool really_return) add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); RTX_FRAME_RELATED_P (insn) = 1; } - } + } if (!really_return) return; @@ -27696,6 +27794,20 @@ arm_print_asm_arch_directives () { arm_initialize_isa (opt_bits, opt->isa_bits); + /* For the cases "-march=armv8.1-m.main+mve -mfloat-abi=soft" and + "-march=armv8.1-m.main+mve.fp -mfloat-abi=soft" MVE and MVE with + floating point instructions is disabled. So the following check + restricts the printing of ".arch_extension mve" and + ".arch_extension fp" (for mve.fp) in the assembly file. MVE needs + this special behaviour because the feature bit "mve" and + "mve_float" are not part of "fpu bits", so they are not cleared + when -mfloat-abi=soft (i.e nofp) but the marco TARGET_HAVE_MVE and + TARGET_HAVE_MVE_FLOAT are disabled. */ + if ((bitmap_bit_p (opt_bits, isa_bit_mve) && !TARGET_HAVE_MVE) + || (bitmap_bit_p (opt_bits, isa_bit_mve_float) + && !TARGET_HAVE_MVE_FLOAT)) + continue; + /* If every feature bit of this option is set in the target ISA specification, print out the option name. However, don't print anything if all the bits are part of the @@ -28505,6 +28617,15 @@ arm_vector_mode_supported_p (machine_mode mode) || mode == V2HAmode)) return true; + if (TARGET_HAVE_MVE + && (mode == V2DImode || mode == V4SImode || mode == V8HImode + || mode == V16QImode)) + return true; + + if (TARGET_HAVE_MVE_FLOAT + && (mode == V2DFmode || mode == V4SFmode || mode == V8HFmode)) + return true; + return false; } @@ -28522,6 +28643,10 @@ arm_array_mode_supported_p (machine_mode mode, && (nelems >= 2 && nelems <= 4)) return true; + if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN + && VALID_MVE_MODE (mode) && (nelems == 2 || nelems == 4)) + return true; + return false; } @@ -29574,7 +29699,7 @@ arm_conditional_register_usage (void) if (TARGET_THUMB1) fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; - if (TARGET_32BIT && TARGET_HARD_FLOAT) + if (TARGET_32BIT && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)) { /* VFPv3 registers are disabled when earlier VFP versions are selected due to the definition of @@ -29586,6 +29711,8 @@ arm_conditional_register_usage (void) call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 || regno >= FIRST_VFP_REGNUM + 32; } + if (TARGET_HAVE_MVE) + fixed_regs[VPR_REGNUM] = 0; } if (TARGET_REALLY_IWMMXT && !TARGET_GENERAL_REGS_ONLY) @@ -32306,6 +32433,20 @@ arm_declare_function_name (FILE *stream, const char *name, tree decl) if (!opt->remove) { arm_initialize_isa (opt_bits, opt->isa_bits); + /* For the cases "-march=armv8.1-m.main+mve -mfloat-abi=soft" + and "-march=armv8.1-m.main+mve.fp -mfloat-abi=soft" MVE and + MVE with floating point instructions is disabled. So the + following check restricts the printing of ".arch_extension + mve" and ".arch_extension fp" (for mve.fp) in the assembly + file. MVE needs this special behaviour because the + feature bit "mve" and "mve_float" are not part of + "fpu bits", so they are not cleared when -mfloat-abi=soft + (i.e nofp) but the marco TARGET_HAVE_MVE and + TARGET_HAVE_MVE_FLOAT are disabled. */ + if ((bitmap_bit_p (opt_bits, isa_bit_mve) && !TARGET_HAVE_MVE) + || (bitmap_bit_p (opt_bits, isa_bit_mve_float) + && !TARGET_HAVE_MVE_FLOAT)) + continue; if (bitmap_subset_p (opt_bits, arm_active_target.isa) && !bitmap_subset_p (opt_bits, isa_all_fpubits_internal)) asm_fprintf (asm_out_file, "\t.arch_extension %s\n", diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index e07cf03..a0283ed 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -324,11 +324,15 @@ emission of floating point pcs attributes. */ instructions (most are floating-point related). */ #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) -#define TARGET_HAVE_MVE (bitmap_bit_p (arm_active_target.isa, \ - isa_bit_mve)) +#define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_mve) \ + && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_HAVE_MVE_FLOAT (bitmap_bit_p (arm_active_target.isa, \ - isa_bit_mve_float)) +#define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_mve_float) \ + && !TARGET_GENERAL_REGS_ONLY) /* Nonzero if integer division instructions supported. */ #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ @@ -767,7 +771,8 @@ extern int arm_arch_bf16; /* s0-s15 VFP scratch (aka d0-d7). s16-s31 S VFP variable (aka d8-d15). vfpcc Not a real register. Represents the VFP condition - code flags. */ + code flags. + vpr Used to represent MVE VPR predication. */ /* The stack backtrace structure is as follows: fp points to here: | save code pointer | [fp] @@ -808,7 +813,7 @@ extern int arm_arch_bf16; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1 \ + 1,1,1,1,1,1,1 \ } /* 1 for registers not available across function calls. @@ -838,7 +843,7 @@ extern int arm_arch_bf16; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1 \ + 1,1,1,1,1,1,1 \ } #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE @@ -1014,10 +1019,10 @@ extern int arm_arch_bf16; && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP - + 1 APSRQ + 1 APSRGE. */ + + 1 APSRQ + 1 APSRGE + 1 VPR. */ /* Intel Wireless MMX Technology registers add 16 + 4 more. */ /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ -#define FIRST_PSEUDO_REGISTER 106 +#define FIRST_PSEUDO_REGISTER 107 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) @@ -1047,11 +1052,26 @@ extern int arm_arch_bf16; || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ || (MODE) == V8BFmode) +#define VALID_MVE_MODE(MODE) \ + ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ + || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ + || (MODE) == V2DFmode) + +#define VALID_MVE_SI_MODE(MODE) \ + ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ + || (MODE) == V16QImode) + +#define VALID_MVE_SF_MODE(MODE) \ + ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) + /* Structure modes valid for Neon registers. */ #define VALID_NEON_STRUCT_MODE(MODE) \ ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ || (MODE) == CImode || (MODE) == XImode) +#define VALID_MVE_STRUCT_MODE(MODE) \ + ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) + /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ extern int arm_regs_in_sequence[]; @@ -1103,9 +1123,13 @@ extern int arm_regs_in_sequence[]; /* Registers not for general use. */ \ CC_REGNUM, VFPCC_REGNUM, \ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ - SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, APSRGE_REGNUM \ + SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ + APSRGE_REGNUM, VPR_REGNUM \ } +#define IS_VPR_REGNUM(REGNUM) \ + ((REGNUM) == VPR_REGNUM) + /* Use different register alloc ordering for Thumb. */ #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () @@ -1142,6 +1166,7 @@ enum reg_class VFPCC_REG, SFP_REG, AFP_REG, + VPR_REG, ALL_REGS, LIM_REG_CLASSES }; @@ -1149,7 +1174,7 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ -#define REG_CLASS_NAMES \ +#define REG_CLASS_NAMES \ { \ "NO_REGS", \ "LO_REGS", \ @@ -1169,6 +1194,7 @@ enum reg_class "VFPCC_REG", \ "SFP_REG", \ "AFP_REG", \ + "VPR_REG", \ "ALL_REGS" \ } @@ -1195,7 +1221,8 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ - { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ + { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ } #define FP_SYSREGS \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b48a4f4..8f8c91d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -41,6 +41,7 @@ (VFPCC_REGNUM 101) ; VFP Condition code pseudo register (APSRQ_REGNUM 104) ; Q bit pseudo register (APSRGE_REGNUM 105) ; GE bits pseudo register + (VPR_REGNUM 106) ; Vector Predication Register - MVE register. ] ) ;; 3rd operand to select_dominance_cc_mode @@ -300,9 +301,11 @@ (ior (eq_attr "is_thumb1" "yes") (eq_attr "type" "call")) (const_string "clob") - (if_then_else (eq_attr "is_neon_type" "no") - (const_string "nocond") - (const_string "unconditional")))) + (if_then_else + (ior (eq_attr "is_neon_type" "no") + (eq_attr "is_mve_type" "no")) + (const_string "nocond") + (const_string "unconditional")))) ; Predicable means that the insn can be conditionally executed based on ; an automatically added predicate (additional patterns are generated by @@ -7307,7 +7310,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") (match_operand:SF 1 "general_operand" "r,mE,r"))] "TARGET_32BIT - && TARGET_SOFT_FLOAT + && TARGET_SOFT_FLOAT && !TARGET_HAVE_MVE && (!MEM_P (operands[0]) || register_operand (operands[1], SFmode))" { @@ -7430,8 +7433,8 @@ (define_insn "*movdf_soft_insn" [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m") - (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] - "TARGET_32BIT && TARGET_SOFT_FLOAT + (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] + "TARGET_32BIT && TARGET_SOFT_FLOAT && !TARGET_HAVE_MVE && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" "* @@ -11755,7 +11758,7 @@ (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] - "TARGET_32BIT && TARGET_HARD_FLOAT" + "TARGET_32BIT && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)" "* { int num_regs = XVECLEN (operands[0], 0); @@ -12698,7 +12701,7 @@ (set_attr "length" "8")] ) -;; Vector bits common to IWMMXT and Neon +;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns (include "iwmmxt.md") @@ -12716,3 +12719,5 @@ (include "sync.md") ;; Fixed-point patterns (include "arm-fixed.md") +;; M-profile Vector Extension +(include "mve.md") diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h new file mode 100644 index 0000000..7347d46 --- /dev/null +++ b/gcc/config/arm/arm_mve.h @@ -0,0 +1,59 @@ +/* Arm MVE intrinsics include file. + + Copyright (C) 2019-2020 Free Software Foundation, Inc. + Contributed by Arm. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef _GCC_ARM_MVE_H +#define _GCC_ARM_MVE_H + +#if !__ARM_FEATURE_MVE +#error "MVE feature not supported" +#endif + +#include +#ifndef __cplusplus +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +typedef __fp16 float16_t; +typedef float float32_t; +typedef __simd128_float16_t float16x8_t; +typedef __simd128_float32_t float32x4_t; +#endif + +typedef uint16_t mve_pred16_t; +typedef __simd128_uint8_t uint8x16_t; +typedef __simd128_uint16_t uint16x8_t; +typedef __simd128_uint32_t uint32x4_t; +typedef __simd128_uint64_t uint64x2_t; +typedef __simd128_int8_t int8x16_t; +typedef __simd128_int16_t int16x8_t; +typedef __simd128_int32_t int32x4_t; +typedef __simd128_int64_t int64x2_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _GCC_ARM_MVE_H. */ diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index fd120df..a12de97 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -38,11 +38,13 @@ ;; in all states: Pf, Pg ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us +;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up ;; in ARM state: Uq ;; in Thumb state: Uu, Uw ;; in all states: Q +(define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS" + "MVE VPR register") (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 2440852..6af7658 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -66,6 +66,12 @@ ;; Integer and float modes supported by Neon and IWMMXT. (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) +;; Integer and float modes supported by Neon, IWMMXT and MVE. +(define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) + +;; Integer and float modes supported by Neon and IWMMXT but not MVE. +(define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF]) + ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) @@ -224,6 +230,10 @@ ;; 16-bit floating-point vector modes suitable for moving (includes BFmode). (define_mode_iterator VHFBF [V8HF V4HF V4BF V8BF]) +;; 16-bit floating-point vector modes suitable for moving (includes BFmode, +;; without V8HF ). +(define_mode_iterator VHFBF_split [V4HF V4BF V8BF]) + ;; 16-bit floating-point scalar modes suitable for moving (includes BFmode). (define_mode_iterator HFBF [HF BF]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md new file mode 100644 index 0000000..c32adf1 --- /dev/null +++ b/gcc/config/arm/mve.md @@ -0,0 +1,85 @@ +;; Arm M-profile Vector Extension Machine Description +;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) +(define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32") + (V2DI "u64")]) + +(define_insn "*mve_mov" + [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") + (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))] + "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" +{ + if (which_alternative == 3 || which_alternative == 6) + { + int width, is_valid; + static char templ[40]; + + is_valid = simd_immediate_valid_for_move (operands[1], mode, + &operands[1], &width); + + gcc_assert (is_valid != 0); + + if (width == 0) + return "vmov.f32\t%q0, %1 @ "; + else + sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ ", width); + return templ; + } + switch (which_alternative) + { + case 0: + return "vmov\t%q0, %q1"; + case 1: + return "vmov\t%e0, %Q1, %R1 @ \;vmov\t%f0, %J1, %K1"; + case 2: + return "vmov\t%Q0, %R0, %e1 @ \;vmov\t%J0, %K0, %f1"; + case 4: + if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode)) + || (MEM_P (operands[1]) + && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF)) + return output_move_neon (operands); + else + return "vldrb.8 %q0, %E1"; + case 5: + return output_move_neon (operands); + case 7: + return "vstrb.8 %q1, %E0"; + default: + gcc_unreachable (); + return ""; + } +} + [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store") + (set_attr "length" "4,8,8,4,8,8,4,4") + (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) + +(define_insn "*mve_mov" + [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w") + (vec_duplicate:MVE_types + (match_operand:SI 1 "nonmemory_operand" "r,i")))] + "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" +{ + if (which_alternative == 0) + return "vdup.\t%q0, %1"; + return "vmov.\t%q0, %1"; +} + [(set_attr "length" "4,4") + (set_attr "type" "mve_move,mve_move")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index ead3e28..b6a8eb6 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -47,7 +47,7 @@ int width, is_valid; static char templ[40]; - is_valid = neon_immediate_valid_for_move (operands[1], mode, + is_valid = simd_immediate_valid_for_move (operands[1], mode, &operands[1], &width); gcc_assert (is_valid != 0); @@ -94,7 +94,7 @@ int width, is_valid; static char templ[40]; - is_valid = neon_immediate_valid_for_move (operands[1], mode, + is_valid = simd_immediate_valid_for_move (operands[1], mode, &operands[1], &width); gcc_assert (is_valid != 0); @@ -160,9 +160,13 @@ } }) +;; The pattern mov where mode is v8hf, v4hf, v4bf and v8bf are split into +;; two groups. The pattern movv8hf is common for MVE and NEON, so it is moved +;; into vec-common.md file. Remaining mov expand patterns with half float and +;; bfloats are implemented below. (define_expand "mov" - [(set (match_operand:VHFBF 0 "s_register_operand") - (match_operand:VHFBF 1 "s_register_operand"))] + [(set (match_operand:VHFBF_split 0 "s_register_operand") + (match_operand:VHFBF_split 1 "s_register_operand"))] "TARGET_NEON" { gcc_checking_assert (aligned_operand (operands[0], mode)); @@ -489,7 +493,7 @@ (define_expand "vec_init" [(match_operand:VDQ 0 "s_register_operand") (match_operand 1 "" "")] - "TARGET_NEON" + "TARGET_NEON || TARGET_HAVE_MVE" { neon_expand_vector_init (operands[0], operands[1]); DONE; diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 3a3941e..fb12371 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -48,6 +48,14 @@ return guard_addr_operand (XEXP (op, 0), mode); }) +(define_predicate "vpr_register_operand" + (match_code "reg") +{ + return REG_P (op) + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || IS_VPR_REGNUM (REGNO (op))); +}) + (define_predicate "imm_for_neon_inv_logic_operand" (match_code "const_vector") { @@ -688,7 +696,7 @@ (define_predicate "imm_for_neon_mov_operand" (match_code "const_vector,const_int") { - return neon_immediate_valid_for_move (op, mode, NULL, NULL); + return simd_immediate_valid_for_move (op, mode, NULL, NULL); }) (define_predicate "imm_for_neon_lshift_operand" diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index b883f79..2d98083 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -55,6 +55,7 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \ $(srcdir)/config/arm/ldmstm.md \ $(srcdir)/config/arm/ldrdstrd.md \ $(srcdir)/config/arm/marvell-f-iwmmxt.md \ + $(srcdir)/config/arm/mve.md \ $(srcdir)/config/arm/neon.md \ $(srcdir)/config/arm/predicates.md \ $(srcdir)/config/arm/sync.md \ diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index e6a317e..83983452 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -550,6 +550,11 @@ ; The classification below is for TME instructions ; ; tme +; The classification below is for M-profile Vector Extension instructions +; +; mve_move +; mve_store +; mve_load (define_attr "type" "adc_imm,\ @@ -1097,7 +1102,10 @@ crypto_sm4,\ coproc,\ tme,\ - memtag" + memtag,\ + mve_move,\ + mve_store,\ + mve_load" (const_string "untyped")) ; Is this an (integer side) multiply with a 32-bit (or smaller) result? @@ -1222,6 +1230,14 @@ (const_string "yes") (const_string "no"))) +;; YES if the "type" attribute assigned to the insn denotes an MVE instruction, +;; No otherwise. +(define_attr "is_mve_type" "yes,no" + (if_then_else (eq_attr "type" + "mve_move, mve_load, mve_store, mrs") + (const_string "yes") + (const_string "no"))) + (define_insn_reservation "no_reservation" 0 (eq_attr "type" "no_insn") "nothing") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 5f35ccd..916e491 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -21,8 +21,31 @@ ;; Vector Moves (define_expand "mov" - [(set (match_operand:VALL 0 "nonimmediate_operand") - (match_operand:VALL 1 "general_operand"))] + [(set (match_operand:VNIM1 0 "nonimmediate_operand") + (match_operand:VNIM1 1 "general_operand"))] + "TARGET_NEON + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) + || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" + { + gcc_checking_assert (aligned_operand (operands[0], mode)); + gcc_checking_assert (aligned_operand (operands[1], mode)); + if (can_create_pseudo_p ()) + { + if (!REG_P (operands[0])) + operands[1] = force_reg (mode, operands[1]); + else if ((TARGET_NEON || TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT) + && (CONSTANT_P (operands[1]))) + { + operands[1] = neon_make_constant (operands[1]); + gcc_assert (operands[1] != NULL_RTX); + } + } +}) + +(define_expand "mov" + [(set (match_operand:VNINOTM1 0 "nonimmediate_operand") + (match_operand:VNINOTM1 1 "general_operand"))] "TARGET_NEON || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" { @@ -40,6 +63,20 @@ } }) +(define_expand "movv8hf" + [(set (match_operand:V8HF 0 "s_register_operand") + (match_operand:V8HF 1 "s_register_operand"))] + "TARGET_NEON || TARGET_HAVE_MVE_FLOAT" +{ + gcc_checking_assert (aligned_operand (operands[0], E_V8HFmode)); + gcc_checking_assert (aligned_operand (operands[1], E_V8HFmode)); + if (can_create_pseudo_p ()) + { + if (!REG_P (operands[0])) + operands[1] = force_reg (E_V8HFmode, operands[1]); + } +}) + ;; Vector arithmetic. Expanders are blank, then unnamed insns implement ;; patterns separately for IWMMXT and Neon. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 99d6be4..ab16a6b 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -311,7 +311,7 @@ && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode)) && !(TARGET_NEON && CONST_INT_P (operands[1]) - && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" + && simd_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" "* switch (which_alternative) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b133809..82bfc05 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,29 @@ +2020-03-16 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test. + * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. + * gcc.target/arm/mve/mve.exp: New file. + * lib/target-supports.exp + (check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check + armv8.1-m.main+mve.fp and returning corresponding options. + (check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call + check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of + MVE with floating point on the current target. + (add_options_for_arm_v8_1m_mve_fp): Proc to call + check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding + compiler options for MVE with floating point. + (check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and + return hard float-abi on success. + 2020-03-16 H.J. Lu PR target/89229 diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c new file mode 100644 index 0000000..ac51f7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ + +#include "arm_mve.h" + +float32x4_t +foo32 (float32x4_t value) +{ + float32x4_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldmia.*" } } */ + +float16x8_t +foo16 (float16x8_t value) +{ + float16x8_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldmia.*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c new file mode 100644 index 0000000..d41900c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ + +#include "arm_mve.h" + +float32x4_t value; + +float32x4_t +foo32 () +{ + float32x4_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldmia.*" } } */ + +float16x8_t value1; + +float16x8_t +foo16 () +{ + float16x8_t b = value1; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldmia.*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c new file mode 100644 index 0000000..f02dd8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ + +#include "arm_mve.h" + +float32x4_t +foo32 () +{ + float32x4_t b = {10.0, 12.0, 14.0, 16.0}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64*" } } */ + +float16x8_t +foo16 () +{ + float16x8_t b = {32.01}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c new file mode 100644 index 0000000..dfe08b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +int8x16_t +foo8 (int8x16_t value) +{ + int8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +int16x8_t +foo16 (int16x8_t value) +{ + int16x8_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +int32x4_t +foo32 (int32x4_t value) +{ + int32x4_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +int64x2_t +foo64 (int64x2_t value) +{ + int64x2_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c new file mode 100644 index 0000000..cb96eb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +int8x16_t value1; +int16x8_t value2; +int32x4_t value3; +int64x2_t value4; + +int8x16_t +foo8 () +{ + int8x16_t b = value1; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +int16x8_t +foo16 () +{ + int16x8_t b = value2; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +int32x4_t +foo32 () +{ + int32x4_t b = value3; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8" } } */ + +int64x2_t +foo64 () +{ + int64x2_t b = value4; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c new file mode 100644 index 0000000..32f589a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +int8x16_t +foo8 () +{ + int8x16_t b = {1, 2, 3, 4}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +int16x8_t +foo16 (int16x8_t value) +{ + int16x8_t b = {1, 2, 3}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +int32x4_t +foo32 (int32x4_t value) +{ + int32x4_t b = {1, 2}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +int64x2_t +foo64 (int64x2_t value) +{ + int64x2_t b = {1}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c new file mode 100644 index 0000000..1957d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +uint8x16_t +foo8 (uint8x16_t value) +{ + uint8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint16x8_t +foo16 (uint16x8_t value) +{ + uint16x8_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint32x4_t +foo32 (uint32x4_t value) +{ + uint32x4_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint64x2_t +foo64 (uint64x2_t value) +{ + uint64x2_t b = value; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c new file mode 100644 index 0000000..0561178 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +uint8x16_t value1; +uint16x8_t value2; +uint32x4_t value3; +uint64x2_t value4; + +uint8x16_t +foo8 () +{ + uint8x16_t b = value1; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint16x8_t +foo16 () +{ + uint16x8_t b = value2; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint32x4_t +foo32 () +{ + uint32x4_t b = value3; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ + +uint64x2_t +foo64 () +{ + uint64x2_t b = value4; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldrb.8*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c new file mode 100644 index 0000000..8b4f4cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include "arm_mve.h" + +uint8x16_t +foo8 (uint8x16_t value) +{ + uint8x16_t b = {1, 2, 3, 4}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +uint16x8_t +foo16 (uint16x8_t value) +{ + uint16x8_t b = {1, 2, 3}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +uint32x4_t +foo32 (uint32x4_t value) +{ + uint32x4_t b = {1, 2}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ + +uint64x2_t +foo64 (uint64x2_t value) +{ + uint64x2_t b = {1}; + return b; +} + +/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */ +/* { dg-final { scan-assembler "vstrb.*" } } */ +/* { dg-final { scan-assembler "vldr.64.*" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/mve.exp b/gcc/testsuite/gcc.target/arm/mve/mve.exp new file mode 100644 index 0000000..e841d56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/mve.exp @@ -0,0 +1,47 @@ +# Copyright (C) 2019-2020 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# This variable should only apply to tests called in this exp file. +global dg_runtest_extra_prunes +set dg_runtest_extra_prunes "" +lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch" + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/intrinsics/*.\[cCS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +set dg_runtest_extra_prunes "" +dg-finish diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ca3895c..4413c26 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4691,6 +4691,49 @@ proc check_effective_target_default_branch_protection { } { return [check_configured_with "enable-standard-branch-protection"] } +# Return 1 if the target supports ARMv8.1-M MVE with floating point +# instructions, 0 otherwise. The test is valid for ARM. +# Record the command line options needed. + +proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } { + global et_arm_v8_1m_mve_fp_flags + set et_arm_v8_1m_mve_fp_flags "" + + if { ![istarget arm*-*-*] } { + return 0; + } + + # Iterate through sets of options to find the compiler flags that + # need to be added to the -march option. + foreach flags {"" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp"} { + if { [check_no_compiler_messages_nocache \ + arm_v8_1m_mve_fp_ok object { + #include + #if !(__ARM_FEATURE_MVE & 2) + #error "__ARM_FEATURE_MVE for floating point not defined" + #endif + } "$flags -mthumb"] } { + set et_arm_v8_1m_mve_fp_flags "$flags -mthumb" + return 1 + } + } + + return 0; +} + +proc check_effective_target_arm_v8_1m_mve_fp_ok { } { + return [check_cached_effective_target arm_v8_1m_mve_fp_ok \ + check_effective_target_arm_v8_1m_mve_fp_ok_nocache] +} + +proc add_options_for_arm_v8_1m_mve_fp { flags } { + if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } { + return "$flags" + } + global et_arm_v8_1m_mve_fp_flags + return "$flags $et_arm_v8_1m_mve_fp_flags" +} + # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 # otherwise. The test is valid for AArch64 and ARM. Record the command # line options needed. @@ -4842,7 +4885,7 @@ proc check_effective_target_arm_v8_1m_mve_ok_nocache { } { # Iterate through sets of options to find the compiler flags that # need to be added to the -march option. - foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} { + foreach flags {"" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve"} { if { [check_no_compiler_messages_nocache \ arm_v8_1m_mve_ok object { #if !defined (__ARM_FEATURE_MVE) -- cgit v1.1 From c7be0832b54669b39dfb56bd91c783dd91aad766 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 16 Mar 2020 17:22:39 +0000 Subject: [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. This patch is part of MVE ACLE intrinsics framework. This patches add support to update (read/write) the APSR (Application Program Status Register) register and FPSCR (Floating-point Status and Control Register) register for MVE. This patch also enables thumb2 mov RTL patterns for MVE. A new feature bit vfp_base is added. This bit is enabled for all VFP, MVE and MVE with floating point extensions. This bit is used to enable the macro TARGET_VFP_BASE. For all the VFP instructions, RTL patterns, status and control registers are guarded by TARGET_HAVE_FLOAT. But this patch modifies that and the common instructions, RTL patterns, status and control registers bewteen MVE and VFP are guarded by TARGET_VFP_BASE macro. The RTL pattern set_fpscr and get_fpscr are updated to use VFPCC_REGNUM because few MVE intrinsics set/get carry bit of FPSCR register. Please refer to Arm reference manual [1] for more details. [1] https://developer.arm.com/docs/ddi0553/latest 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base feature bit is on and -mfpu=auto is passed as compiler option, do not generate error on not finding any matching fpu. Because in this case fpu is not required. * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is enabled for MVE and also for all VFP extensions. (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 is enabled. (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 along with feature bits mve_float. (mve): Modify add options in armv8.1-m.main arch for MVE. (mve.fp): Modify add options in armv8.1-m.main arch for MVE with floating point. * config/arm/arm.c (use_return_insn): Replace the check with TARGET_VFP_BASE. (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE. (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as well. (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE as well. (arm_compute_frame_layout): Likewise. (arm_save_coproc_regs): Likewise. (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM in MVE as well. (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. (arm_expand_epilogue_apcs_frame): Likewise. (arm_expand_epilogue): Likewise. (arm_conditional_register_usage): Likewise. (arm_declare_function_name): Add check to skip printing .fpu directive in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is "softvfp". * config/arm/arm.h (TARGET_VFP_BASE): Define. * config/arm/arm.md (arch): Add "mve" to arch. (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. * config/arm/constraints.md (Uf): Define to allow modification to FPCCR in MVE. * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard to not allow for MVE. * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs enum. (VUNSPEC_GET_FPSCR): Define. * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS instructions which move to general-purpose Register from Floating-point Special register and vice-versa. (thumb2_movhi_fp16): Likewise. (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along with MCR and MRC instructions which set and get Floating-point Status and Control Register (FPSCR). (movdi_vfp): Modify pattern to enable Single-precision scalar float move in MVE. (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar float move patterns in MVE. (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding TARGET_VFP_BASE check. (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. 2020-03-16 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test. * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. --- gcc/ChangeLog | 77 ++++++++++++ gcc/common/config/arm/arm-common.c | 3 +- gcc/config/arm/arm-cpus.in | 14 ++- gcc/config/arm/arm.c | 29 ++--- gcc/config/arm/arm.h | 13 +++ gcc/config/arm/arm.md | 8 +- gcc/config/arm/constraints.md | 5 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vfp.md | 129 +++++++++++++-------- gcc/testsuite/ChangeLog | 9 ++ .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 14 +++ .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 14 +++ .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 14 +++ .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 14 +++ .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 12 ++ 16 files changed, 287 insertions(+), 72 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e814da1..ec4e4e7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,83 @@ Mihail Ionescu Srinath Parvathaneni + * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base + feature bit is on and -mfpu=auto is passed as compiler option, do not + generate error on not finding any matching fpu. Because in this case + fpu is not required. + * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is + enabled for MVE and also for all VFP extensions. + (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 + is enabled. + (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. + (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 + along with feature bits mve_float. + (mve): Modify add options in armv8.1-m.main arch for MVE. + (mve.fp): Modify add options in armv8.1-m.main arch for MVE with + floating point. + * config/arm/arm.c (use_return_insn): Replace the + check with TARGET_VFP_BASE. + (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with + TARGET_VFP_BASE. + (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" + with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as + well. + (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with + TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE + as well. + (arm_compute_frame_layout): Likewise. + (arm_save_coproc_regs): Likewise. + (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM + in MVE as well. + (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" + with equivalent macro TARGET_VFP_BASE. + (arm_expand_epilogue_apcs_frame): Likewise. + (arm_expand_epilogue): Likewise. + (arm_conditional_register_usage): Likewise. + (arm_declare_function_name): Add check to skip printing .fpu directive + in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is + "softvfp". + * config/arm/arm.h (TARGET_VFP_BASE): Define. + * config/arm/arm.md (arch): Add "mve" to arch. + (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. + (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT + || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. + * config/arm/constraints.md (Uf): Define to allow modification to FPCCR + in MVE. + * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard + to not allow for MVE. + * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs + enum. + (VUNSPEC_GET_FPSCR): Define. + * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS + instructions which move to general-purpose Register from Floating-point + Special register and vice-versa. + (thumb2_movhi_fp16): Likewise. + (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along + with MCR and MRC instructions which set and get Floating-point Status + and Control Register (FPSCR). + (movdi_vfp): Modify pattern to enable Single-precision scalar float move + in MVE. + (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar + float move patterns in MVE. + (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional + code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. + (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional + code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. + (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding + TARGET_VFP_BASE check. + (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern + using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR + register. + (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern + using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR + register. + + +2020-03-16 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config.gcc (arm_mve.h): Include mve intrinsics header file. * config/arm/aout.h (p0): Add new register name for MVE predicated cases. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 30a2a1d..78a779c 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -1009,7 +1009,8 @@ arm_asm_auto_mfpu (int argc, const char **argv) } } - gcc_assert (i != TARGET_FPU_auto); + gcc_assert (i != TARGET_FPU_auto + || bitmap_bit_p (target_isa, isa_bit_vfp_base)); } auto_fpu = (char *) xmalloc (strlen (fpuname) + sizeof ("-mfpu=")); diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 96f584d..77b4309 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -135,6 +135,10 @@ define feature armv8_1m_main # Floating point and Neon extensions. # VFPv1 is not supported in GCC. +# This feature bit is enabled for all VFP, MVE and +# MVE with floating point extensions. +define feature vfp_base + # Vector floating point v2. define feature vfpv2 @@ -234,7 +238,7 @@ define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL # List of all FPU bits to strip out if -mfpu is used to override the # default. fp16 is deliberately missing from this list. -define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL +define fgroup ALL_FPU_INTERNAL vfp_base vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL # Similarly, but including fp16 and other extensions that aren't part of # -mfpu support. define fgroup ALL_FPU_EXTERNAL fp16 bf16 @@ -279,10 +283,12 @@ define fgroup ARMv8r ARMv8a define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main # Useful combinations. -define fgroup VFPv2 vfpv2 +define fgroup VFPv2 vfp_base vfpv2 define fgroup VFPv3 VFPv2 vfpv3 define fgroup VFPv4 VFPv3 vfpv4 fp16conv define fgroup FPv5 VFPv4 fpv5 +define fgroup MVE mve vfp_base armv7em +define fgroup MVE_FP MVE FPv5 fp16 mve_float define fgroup FP_DBL fp_dbl define fgroup FP_D32 FP_DBL fp_d32 @@ -699,8 +705,8 @@ begin arch armv8.1-m.main option fp add FPv5 fp16 option fp.dp add FPv5 FP_DBL fp16 option nofp remove ALL_FP - option mve add mve armv7em - option mve.fp add mve FPv5 fp16 mve_float armv7em + option mve add MVE + option mve.fp add MVE_FP end arch armv8.1-m.main begin arch iwmmxt diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c769104..b40904a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -4295,7 +4295,7 @@ use_return_insn (int iscond, rtx sibling) /* Can't be done if any of the VFP regs are pushed, since this also requires an insn. */ - if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + if (TARGET_VFP_BASE) for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) if (df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno)) return 0; @@ -6289,7 +6289,7 @@ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) return false; return (TARGET_32BIT && TARGET_HARD_FLOAT && - (TARGET_VFP_DOUBLE || !is_double)); + (TARGET_VFP_DOUBLE || !is_double)); } /* Return true if an argument whose type is TYPE, or mode is MODE, is @@ -8512,7 +8512,7 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p) /* ??? Combine arm and thumb2 coprocessor addressing modes. */ /* Standard coprocessor addressing modes. */ - if (TARGET_HARD_FLOAT + if (TARGET_VFP_BASE && (mode == SFmode || mode == DFmode)) return (code == CONST_INT && INTVAL (index) < 1024 /* Thumb-2 allows only > -256 index range for it's core register @@ -9905,7 +9905,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, /* Assume that most copies can be done with a single insn, unless we don't have HW FP, in which case everything larger than word mode will require two insns. */ - *cost = COSTS_N_INSNS (((!(TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + *cost = COSTS_N_INSNS (((!TARGET_VFP_BASE && GET_MODE_SIZE (mode) > 4) || mode == DImode) ? 2 : 1); @@ -20821,7 +20821,7 @@ arm_get_vfp_saved_size (void) saved = 0; /* Space for saved VFP registers. */ - if (TARGET_HARD_FLOAT) + if (TARGET_VFP_BASE) { count = 0; for (regno = FIRST_VFP_REGNUM; @@ -22364,7 +22364,7 @@ arm_compute_frame_layout (void) func_type = arm_current_func_type (); /* Space for saved VFP registers. */ if (! IS_VOLATILE (func_type) - && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)) + && TARGET_VFP_BASE) saved += arm_get_vfp_saved_size (); /* Allocate space for saving/restoring FPCXTNS in Armv8.1-M Mainline @@ -22588,7 +22588,7 @@ arm_save_coproc_regs(void) saved_size += 8; } - if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + if (TARGET_VFP_BASE) { start_reg = FIRST_VFP_REGNUM; @@ -24546,7 +24546,7 @@ arm_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) return false; *p1 = CC_REGNUM; - *p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM; + *p2 = TARGET_VFP_BASE ? VFPCC_REGNUM : INVALID_REGNUM; return true; } @@ -24965,7 +24965,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) { if (GET_MODE_CLASS (mode) == MODE_CC) return (regno == CC_REGNUM - || ((TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + || (TARGET_VFP_BASE && regno == VFPCC_REGNUM)); if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC) @@ -24982,7 +24982,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) start of an even numbered register pair. */ return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); - if ((TARGET_HARD_FLOAT || TARGET_HAVE_MVE) && IS_VFP_REGNUM (regno)) + if (TARGET_VFP_BASE && IS_VFP_REGNUM (regno)) { if (mode == DFmode) return VFP_REGNO_OK_FOR_DOUBLE (regno); @@ -26933,7 +26933,7 @@ arm_expand_epilogue_apcs_frame (bool really_return) floats_from_frame += 4; } - if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + if (TARGET_VFP_BASE) { int start_reg; rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); @@ -27179,7 +27179,7 @@ arm_expand_epilogue (bool really_return) } } - if (TARGET_HARD_FLOAT || TARGET_HAVE_MVE) + if (TARGET_VFP_BASE) { /* Generate VFP register multi-pop. */ int end_reg = LAST_VFP_REGNUM + 1; @@ -29699,7 +29699,7 @@ arm_conditional_register_usage (void) if (TARGET_THUMB1) fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; - if (TARGET_32BIT && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)) + if (TARGET_32BIT && TARGET_VFP_BASE) { /* VFPv3 registers are disabled when earlier VFP versions are selected due to the definition of @@ -32478,7 +32478,8 @@ arm_declare_function_name (FILE *stream, const char *name, tree decl) = TARGET_SOFT_FLOAT ? "softvfp" : arm_identify_fpu_from_isa (arm_active_target.isa); - if (fpu_to_print != arm_last_printed_arch_string) + if (!(!strcmp (fpu_to_print.c_str (), "softvfp") && TARGET_VFP_BASE) + && (fpu_to_print != arm_last_printed_arch_string)) { asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_to_print.c_str ()); arm_last_printed_fpu_string = fpu_to_print; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index a0283ed..c745341 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -334,6 +334,19 @@ emission of floating point pcs attributes. */ isa_bit_mve_float) \ && !TARGET_GENERAL_REGS_ONLY) +/* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM + alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few + registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All + the VFP instructions, RTL patterns and register are guarded by + TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers + between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE + hereafter. */ + +#define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_vfp_base) \ + && !TARGET_GENERAL_REGS_ONLY) + /* Nonzero if integer division instructions supported. */ #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ || (TARGET_THUMB && arm_arch_thumb_hwdiv)) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8f8c91d..5387f97 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -134,7 +134,7 @@ ; arm_arch6. "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M ; Baseline. This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon" +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon,mve" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -188,6 +188,10 @@ (and (eq_attr "arch" "neon") (match_test "TARGET_NEON")) (const_string "yes") + + (and (eq_attr "arch" "mve") + (match_test "TARGET_HAVE_MVE")) + (const_string "yes") ] (const_string "no"))) @@ -11758,7 +11762,7 @@ (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] - "TARGET_32BIT && (TARGET_HARD_FLOAT || TARGET_HAVE_MVE)" + "TARGET_32BIT && TARGET_VFP_BASE" "* { int num_regs = XVECLEN (operands[0], 0); diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index a12de97..bf8f4ff 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -38,7 +38,7 @@ ;; in all states: Pf, Pg ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up +;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf ;; in ARM state: Uq ;; in Thumb state: Uu, Uw ;; in all states: Q @@ -46,6 +46,9 @@ (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS" "MVE VPR register") +(define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS" + "MVE FPCCR register") + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index b0d3bd1..793f670 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -517,7 +517,7 @@ [(match_operand 4 "cc_register" "") (const_int 0)]) (match_operand:SF 1 "s_register_operand" "0,r") (match_operand:SF 2 "s_register_operand" "r,0")))] - "TARGET_THUMB2 && TARGET_SOFT_FLOAT" + "TARGET_THUMB2 && TARGET_SOFT_FLOAT && !TARGET_HAVE_MVE" "@ it\\t%D3\;mov%D3\\t%0, %2 it\\t%d3\;mov%d3\\t%0, %1" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index f0b1f46..e76609f 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,6 +170,7 @@ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. + UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. ]) @@ -216,7 +217,6 @@ VUNSPEC_SLX ; Represent a store-register-release-exclusive. VUNSPEC_LDA ; Represent a store-register-acquire. VUNSPEC_STL ; Represent a store-register-release. - VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index ab16a6b..eb6ae7b 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -74,10 +74,10 @@ (define_insn "*thumb2_movhi_vfp" [(set (match_operand:HI 0 "nonimmediate_operand" - "=rk, r, l, r, m, r, *t, r, *t") + "=rk, r, l, r, m, r, *t, r, *t, Up, r") (match_operand:HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT + "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + "TARGET_THUMB2 && TARGET_VFP_BASE && !TARGET_VFP_FP16INST && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -99,20 +99,24 @@ return "vmov%?\t%0, %1\t%@ int"; case 8: return "vmov%?.f32\t%0, %1\t%@ int"; + case 9: + return "vmsr%?\t P0, %1\t@ movhi"; + case 10: + return "vmrs%?\t %0, P0\t@ movhi"; default: gcc_unreachable (); } } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" - "yes, no, yes, no, no, no, no, no, no") + "yes, no, yes, no, no, no, no, no, no, no, no") (set_attr "type" "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\ - f_mcr, f_mrc, fmov") - (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *") - (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *") - (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *") - (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")] + f_mcr, f_mrc, fmov, mve_move, mve_move") + (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *, mve, mve") + (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *, *, *") + (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *, *, *") + (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4")] ) ;; Patterns for HI moves which provide more data transfer instructions when FP16 @@ -170,10 +174,10 @@ (define_insn "*thumb2_movhi_fp16" [(set (match_operand:HI 0 "nonimmediate_operand" - "=rk, r, l, r, m, r, *t, r, *t") + "=rk, r, l, r, m, r, *t, r, *t, Up, r") (match_operand:HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t"))] - "TARGET_THUMB2 && TARGET_VFP_FP16INST + "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + "TARGET_THUMB2 && (TARGET_VFP_FP16INST || TARGET_HAVE_MVE) && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" { @@ -194,21 +198,25 @@ return "vmov.f16\t%0, %1\t%@ int"; case 8: return "vmov%?.f32\t%0, %1\t%@ int"; + case 9: + return "vmsr%?\tP0, %1\t%@ movhi"; + case 10: + return "vmrs%?\t%0, P0\t%@ movhi"; default: gcc_unreachable (); } } [(set_attr "predicable" - "yes, yes, yes, yes, yes, yes, no, no, yes") + "yes, yes, yes, yes, yes, yes, no, no, yes, yes, yes") (set_attr "predicable_short_it" - "yes, no, yes, no, no, no, no, no, no") + "yes, no, yes, no, no, no, no, no, no, no, no") (set_attr "type" "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\ - f_mcr, f_mrc, fmov") - (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *") - (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *") - (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *") - (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")] + f_mcr, f_mrc, fmov, mve_move, mve_move") + (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *, mve, mve") + (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *, *, *") + (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *, *, *") + (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4")] ) ;; SImode moves @@ -258,9 +266,11 @@ ;; is chosen with length 2 when the instruction is predicated for ;; arm_restrict_it. (define_insn "*thumb2_movsi_vfp" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m,*t, r,*t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,lk*r, r,*t,*t,*UvTu,*t"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l,*hk,m,*m,*t,\ + r,*t,*t,*Uv, Up, r,Uf,r") + (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk,r,*t,\ + *t,*UvTu,*t, r, Up,r,Uf"))] + "TARGET_THUMB2 && TARGET_VFP_BASE && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" "* @@ -275,30 +285,44 @@ case 4: return \"movw%?\\t%0, %1\"; case 5: + case 6: /* Cannot load it directly, split to load it via MOV / MOVT. */ if (!MEM_P (operands[1]) && arm_disable_literal_pool) return \"#\"; return \"ldr%?\\t%0, %1\"; - case 6: - return \"str%?\\t%1, %0\"; case 7: - return \"vmov%?\\t%0, %1\\t%@ int\"; case 8: - return \"vmov%?\\t%0, %1\\t%@ int\"; + return \"str%?\\t%1, %0\"; case 9: + return \"vmov%?\\t%0, %1\\t%@ int\"; + case 10: + return \"vmov%?\\t%0, %1\\t%@ int\"; + case 11: return \"vmov%?.f32\\t%0, %1\\t%@ int\"; - case 10: case 11: + case 12: case 13: return output_move_vfp (operands); + case 14: + return \"vmsr\\t P0, %1\"; + case 15: + return \"vmrs\\t %0, P0\"; + case 16: + return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\"; + case 17: + return \"mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR\"; default: gcc_unreachable (); } " [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores") - (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4") - (set_attr "pool_range" "*,*,*,*,*,1018,*,*,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,*,*, 0,*,*,*,*,1008,*")] + (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,\ + no,no,no,no,no") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,load_4,\ + store_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores,mve_move,\ + mve_move,mrs,mrs") + (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4") + (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*,*,*,*,*") + (set_attr "arch" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,mve,mve,mve,mve") + (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*,*,*,*,*")] ) @@ -306,12 +330,12 @@ (define_insn "*movdi_vfp" [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv") - (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,UvTu,w"))] - "TARGET_32BIT && TARGET_HARD_FLOAT + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,UvTu,w"))] + "TARGET_32BIT && TARGET_VFP_BASE && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode)) - && !(TARGET_NEON && CONST_INT_P (operands[1]) - && simd_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" + && !((TARGET_NEON || TARGET_HAVE_MVE) && CONST_INT_P (operands[1]) + && simd_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" "* switch (which_alternative) { @@ -333,7 +357,7 @@ case 8: return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\"; case 9: - if (TARGET_VFP_SINGLE) + if (TARGET_VFP_SINGLE || TARGET_HAVE_MVE) return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\"; else return \"vmov%?.f64\\t%P0, %P1\\t%@ int\"; @@ -390,9 +414,15 @@ case 6: /* S register from immediate. */ return \"vmov.f16\\t%0, %1\t%@ __\"; case 7: /* S register from memory. */ - return \"vld1.16\\t{%z0}, %A1\"; + if (TARGET_HAVE_MVE) + return \"vldr.16\\t%0, %A1\"; + else + return \"vld1.16\\t{%z0}, %A1\"; case 8: /* Memory from S register. */ - return \"vst1.16\\t{%z1}, %A0\"; + if (TARGET_HAVE_MVE) + return \"vstr.16\\t%1, %A0\"; + else + return \"vst1.16\\t{%z1}, %A0\"; case 9: /* ARM register from constant. */ { long bits; @@ -593,7 +623,7 @@ (define_insn "*thumb2_movsf_vfp" [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r") (match_operand:SF 1 "hard_sf_operand" " ?r,t,Dv,UvHa,t, mHa,r,t,r"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT + "TARGET_THUMB2 && TARGET_VFP_BASE && ( s_register_operand (operands[0], SFmode) || s_register_operand (operands[1], SFmode))" "* @@ -682,7 +712,7 @@ (define_insn "*thumb2_movdf_vfp" [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r ,m,w,r") (match_operand:DF 1 "hard_df_operand" " ?r,w,Dy,G,UvHa,w, mHa,r, w,r"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT + "TARGET_THUMB2 && TARGET_VFP_BASE && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" "* @@ -760,7 +790,7 @@ [(match_operand 4 "cc_register" "") (const_int 0)]) (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && !arm_restrict_it" + "TARGET_THUMB2 && TARGET_VFP_BASE && !arm_restrict_it" "@ it\\t%D3\;vmov%D3.f32\\t%0, %2 it\\t%d3\;vmov%d3.f32\\t%0, %1 @@ -806,7 +836,8 @@ [(match_operand 4 "cc_register" "") (const_int 0)]) (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it" + "TARGET_THUMB2 && TARGET_VFP_BASE && TARGET_VFP_DOUBLE + && !arm_restrict_it" "@ it\\t%D3\;vmov%D3.f64\\t%P0, %P2 it\\t%d3\;vmov%d3.f64\\t%P0, %P1 @@ -1977,7 +2008,7 @@ [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")] UNSPEC_PUSH_MULT))])] - "TARGET_32BIT && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_VFP_BASE" "* return vfp_output_vstmd (operands);" [(set_attr "type" "f_stored")] ) @@ -2065,16 +2096,18 @@ ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)] - "TARGET_HARD_FLOAT" + [(set (reg:SI VFPCC_REGNUM) + (unspec_volatile:SI + [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))] + "TARGET_VFP_BASE" "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" [(set_attr "type" "mrs")]) ;; Read Floating-point Status and Control Register. (define_insn "get_fpscr" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] - "TARGET_HARD_FLOAT" + (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))] + "TARGET_VFP_BASE" "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" [(set_attr "type" "mrs")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 82bfc05..590fa16 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2020-03-16 Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test. + * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. + + 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c new file mode 100644 index 0000000..17ba616 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ + +#include "arm_mve.h" + +int8x16_t +foo1 (int8x16_t value) +{ + int8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler "\.fpu fpv5-sp-d16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c new file mode 100644 index 0000000..7b877c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb" } */ + +#include "arm_mve.h" + +int8x16_t +foo1 (int8x16_t value) +{ + int8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler "\.fpu fpv5-sp-d16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c new file mode 100644 index 0000000..85fbb57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ + +#include "arm_mve.h" + +int8x16_t +foo1 (int8x16_t value) +{ + int8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler-not "\.fpu softvfp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c new file mode 100644 index 0000000..23b3683 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb" } */ + +#include "arm_mve.h" + +int8x16_t +foo1 (int8x16_t value) +{ + int8x16_t b = value; + return b; +} + +/* { dg-final { scan-assembler-not "\.fpu softvfp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c new file mode 100644 index 0000000..8f7fa34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb" } */ + +int +foo1 (int value) +{ + int b = value; + return b; +} + +/* { dg-final { scan-assembler "\.fpu softvfp" } } */ -- cgit v1.1 From 5dee500b359b13985d4f9a006b70c10c526904e6 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 16 Mar 2020 17:33:03 +0000 Subject: [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. This patch is part of MVE ACLE intrinsics framework. The patch supports the use of emulation for the single-precision arithmetic operations for MVE. This changes are to support the MVE ACLE intrinsics which operates on vector floating point arithmetic operations. Please refer to Arm reference manual [1] for more details. [1] https://developer.arm.com/docs/ddi0553/latest 2020-03-16 Andre Vieira Srinath Parvathaneni * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add emulator calls for dobule precision arithmetic operations for MVE. 2020-03-16 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_libcall1.c: New test. * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise. --- gcc/ChangeLog | 6 ++ gcc/config/arm/arm.c | 22 ++++++- gcc/testsuite/ChangeLog | 5 ++ .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 67 ++++++++++++++++++++++ .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 67 ++++++++++++++++++++++ 5 files changed, 164 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ec4e4e7..03ac0d4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,10 @@ 2020-03-16 Andre Vieira + Srinath Parvathaneni + + * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add + emulator calls for dobule precision arithmetic operations for MVE. + +2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b40904a..b3dfa28 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -5754,9 +5754,25 @@ arm_libcall_uses_aapcs_base (const_rtx libcall) /* Values from double-precision helper functions are returned in core registers if the selected core only supports single-precision arithmetic, even if we are using the hard-float ABI. The same is - true for single-precision helpers, but we will never be using the - hard-float ABI on a CPU which doesn't support single-precision - operations in hardware. */ + true for single-precision helpers except in case of MVE, because in + MVE we will be using the hard-float ABI on a CPU which doesn't support + single-precision operations in hardware. In MVE the following check + enables use of emulation for the single-precision arithmetic + operations. */ + if (TARGET_HAVE_MVE) + { + add_libcall (libcall_htab, optab_libfunc (add_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (sdiv_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (smul_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (neg_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (sub_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (eq_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (lt_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (le_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (ge_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (gt_optab, SFmode)); + add_libcall (libcall_htab, optab_libfunc (unord_optab, SFmode)); + } add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode)); add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode)); add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode)); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 590fa16..36449f1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2020-03-16 Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/mve_libcall1.c: New test. + * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise. + +2020-03-16 Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test. * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c new file mode 100644 index 0000000..7c38d31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ + +float +foo (float a, float b, float c) +{ + return a + b + c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_fadd" 2 } } */ + +float +foo1 (float a, float b, float c) +{ + return a - b - c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_fsub" 2 } } */ + +float +foo2 (float a, float b, float c) +{ + return a * b * c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_fmul" 2 } } */ + +float +foo3 (float b, float c) +{ + return b / c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_fdiv" } } */ + +int +foo4 (float b, float c) +{ + return b < c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_fcmplt" } } */ + +int +foo5 (float b, float c) +{ + return b > c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_fcmpgt" } } */ + +int +foo6 (float b, float c) +{ + return b != c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_fcmpeq" } } */ + +int +foo7 (float b, float c) +{ + return b == c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_fcmpeq" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c new file mode 100644 index 0000000..773c844 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ + +double +foo (double a, double b, double c) +{ + return a + b + c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_dadd" 2 } } */ + +double +foo1 (double a, double b, double c) +{ + return a - b - c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_dsub" 2 } } */ + +double +foo2 (double a, double b, double c) +{ + return a * b * c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_dmul" 2 } } */ + +double +foo3 (double b, double c) +{ + return b / c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_ddiv" } } */ + +int +foo4 (double b, double c) +{ + return b < c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_dcmplt" } } */ + +int +foo5 (double b, double c) +{ + return b > c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_dcmpgt" } } */ + +int +foo6 (double b, double c) +{ + return b != c; +} + +/* { dg-final { scan-assembler "bl\\t__aeabi_dcmpeq" } } */ + +int +foo7 (double b, double c) +{ + return b == c; +} + +/* { dg-final { scan-assembler-times "bl\\t__aeabi_dcmpeq" 2 } } */ -- cgit v1.1 From f522810d2b5edb4008afc4a8d003b7e182aa8ba2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 12 Mar 2020 11:54:27 +0000 Subject: [testsuite] Avoid duplicate test names in sizeless tests Jeff pointed out that using: N: ... /* { dg-error {...} } */ N+1: /* { dg-error {...} "" { target *-*-* } .-1 } */ led to two identical test names for line N. Fixed by adding a proper test name instead of "". 2020-03-16 Richard Sandiford gcc/testsuite/ * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Add a test name to .-1 dg-error tests. * gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 36449f1..c3d6ecc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-16 Richard Sandiford + + * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Add a test + name to .-1 dg-error tests. + * gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise. + 2020-03-16 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_libcall1.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c index ec892a3..045963d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c @@ -31,7 +31,7 @@ union union1 { svint8_t *global_sve_sc_ptr; svint8_t *invalid_sve_sc_ptr = &(svint8_t) { *global_sve_sc_ptr }; /* { dg-error {initializer element is not constant} } */ - /* { dg-error {SVE type 'svint8_t' does not have a fixed size} "" { target *-*-* } .-1 } */ + /* { dg-error {SVE type 'svint8_t' does not have a fixed size} "2nd line" { target *-*-* } .-1 } */ /* Sizeless arguments and return values. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c index 7174393..c7282fa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c @@ -31,7 +31,7 @@ union union1 { svint8_t *global_sve_sc_ptr; svint8_t *invalid_sve_sc_ptr = &(svint8_t) { *global_sve_sc_ptr }; /* { dg-error {initializer element is not constant} } */ - /* { dg-error {SVE type 'svint8_t' does not have a fixed size} "" { target *-*-* } .-1 } */ + /* { dg-error {SVE type 'svint8_t' does not have a fixed size} "2nd line" { target *-*-* } .-1 } */ /* Sizeless arguments and return values. */ -- cgit v1.1 From bae7b38cf8a21e068ad5c0bab089dedb78af3346 Mon Sep 17 00:00:00 2001 From: "Vladimir N. Makarov" Date: Mon, 16 Mar 2020 16:42:19 -0400 Subject: Fix PR94185: Do not reuse insn alternative after changing memory subreg. 2020-03-16 Vladimir Makarov PR target/94185 * lra-spills.c (remove_pseudos): Do not reuse insn alternative after changing memory subreg. 2020-03-16 Vladimir Makarov PR target/94185 * g++.target/i386/pr94185.C: New test. --- gcc/ChangeLog | 6 ++++++ gcc/lra-spills.c | 12 +++++++++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.target/i386/pr94185.C | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/i386/pr94185.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 03ac0d4..25a27f8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-16 Vladimir Makarov + + PR target/94185 + * lra-spills.c (remove_pseudos): Do not reuse insn alternative + after changing memory subreg. + 2020-03-16 Andre Vieira Srinath Parvathaneni diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c index 01256e7..a4b955a 100644 --- a/gcc/lra-spills.c +++ b/gcc/lra-spills.c @@ -427,7 +427,17 @@ remove_pseudos (rtx *loc, rtx_insn *insn) and avoid LRA cycling in case of subreg memory reload. */ res = remove_pseudos (&SUBREG_REG (*loc), insn); if (GET_CODE (SUBREG_REG (*loc)) == MEM) - alter_subreg (loc, false); + { + alter_subreg (loc, false); + if (GET_CODE (*loc) == MEM) + { + lra_get_insn_recog_data (insn)->used_insn_alternative = -1; + if (lra_dump_file != NULL) + fprintf (lra_dump_file, + "Memory subreg was simplified in in insn #%u\n", + INSN_UID (insn)); + } + } return res; } else if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c3d6ecc..3b277ce 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Vladimir Makarov + + PR target/94185 + * g++.target/i386/pr94185.C: New test. + 2020-03-16 Richard Sandiford * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Add a test diff --git a/gcc/testsuite/g++.target/i386/pr94185.C b/gcc/testsuite/g++.target/i386/pr94185.C new file mode 100644 index 0000000..587b7ba --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr94185.C @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIE -fstack-protector-strong" } */ + +struct a { + int b; + int c(); + a() : b(c()) {} + ~a(); + char *e(); +}; +struct f { + void g(int); +}; +struct ar { + int au[256]; + f h(int); +} bb; +a i(); +a j(int); +long k(int, ar); +int d; +void l(char *, ar m, long n) { + switch (m.au[d]) + case 0: + n &= 4294967295; + bb.h(0).g(n); +} +void o() { + ar bd; + a bh, bi, attrname = j(0) = i(); + int be = k(0, bd); + l(attrname.e(), bd, be); +} -- cgit v1.1 From c015ff8ccaf3ee8e4f6393679ed790ed0df92873 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 16 Mar 2020 22:58:41 +0100 Subject: c: Handle MEM_REF in c_fully_fold* [PR94179] The recent match.pd changes can generate a MEM_REF which can be seen by the C FE folding routines. Unlike the C++ FE, they weren't expected in the C FE yet. MEM_REF should be handled like INDIRECT_REF, except that it has two operands rather than just one and that we should preserve the type of the second operand. Given that it already has to be an INTEGER_CST with pointer type, I think we are fine, the recursive call should return the INTEGER_CST unmodified and STRIP_TYPE_NOPS will not strip anything. 2020-03-16 Jakub Jelinek PR c/94179 * c-fold.c (c_fully_fold_internal): Handle MEM_REF. * gcc.c-torture/compile/pr94179.c: New test. --- gcc/c/ChangeLog | 5 +++++ gcc/c/c-fold.c | 9 +++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 +++++++++ 4 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94179.c (limited to 'gcc') diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index d3a3b2f..240859e 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Jakub Jelinek + + PR c/94179 + * c-fold.c (c_fully_fold_internal): Handle MEM_REF. + 2020-03-13 Martin Sebor PR c/94040 diff --git a/gcc/c/c-fold.c b/gcc/c/c-fold.c index fde2d55..63becfe 100644 --- a/gcc/c/c-fold.c +++ b/gcc/c/c-fold.c @@ -346,6 +346,7 @@ c_fully_fold_internal (tree expr, bool in_init, bool *maybe_const_operands, case UNGT_EXPR: case UNGE_EXPR: case UNEQ_EXPR: + case MEM_REF: /* Binary operations evaluating both arguments (increment and decrement are binary internally in GCC). */ orig_op0 = op0 = TREE_OPERAND (expr, 0); @@ -435,6 +436,14 @@ c_fully_fold_internal (tree expr, bool in_init, bool *maybe_const_operands, || TREE_CODE (TREE_TYPE (orig_op0)) == FIXED_POINT_TYPE) && TREE_CODE (TREE_TYPE (orig_op1)) == INTEGER_TYPE) warn_for_div_by_zero (loc, op1); + if (code == MEM_REF + && ret != expr + && TREE_CODE (ret) == MEM_REF) + { + TREE_READONLY (ret) = TREE_READONLY (expr); + TREE_SIDE_EFFECTS (ret) = TREE_SIDE_EFFECTS (expr); + TREE_THIS_VOLATILE (ret) = TREE_THIS_VOLATILE (expr); + } goto out; case ADDR_EXPR: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b277ce..f0d7033 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-16 Jakub Jelinek + + PR c/94179 + * gcc.c-torture/compile/pr94179.c: New test. + 2020-03-16 Vladimir Makarov PR target/94185 diff --git a/gcc/testsuite/gcc.c-torture/compile/pr94179.c b/gcc/testsuite/gcc.c-torture/compile/pr94179.c new file mode 100644 index 0000000..dfe27fe --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr94179.c @@ -0,0 +1,9 @@ +/* PR c/94179 */ + +struct S { char c, d, e[64]; } a; + +unsigned char * +foo (int b) +{ + return (unsigned char *)((char *)&a.e[b != 0] - (char *)&((struct S *)0)->d); +} -- cgit v1.1 From 447d196e75d97a9ac7c6a548dc9d0fe367adf6be Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Mon, 16 Mar 2020 23:04:49 +0100 Subject: d: Fix multiple definition error when using mixins and interfaces. gcc/d/ChangeLog: PR d/92216 * decl.cc (make_thunk): Don't set TREE_PUBLIC on thunks if the target function is external to the current compilation. gcc/testsuite/ChangeLog: PR d/92216 * gdc.dg/imports/pr92216.d: New. * gdc.dg/pr92216.d: New test. --- gcc/d/ChangeLog | 6 ++++++ gcc/d/decl.cc | 7 +++++-- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gdc.dg/imports/pr92216.d | 22 ++++++++++++++++++++++ gcc/testsuite/gdc.dg/pr92216.d | 13 +++++++++++++ 5 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gdc.dg/imports/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92216.d (limited to 'gcc') diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index fbd56b7..d9c7657 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,9 @@ +2020-03-16 Iain Buclaw + + PR d/92216 + * decl.cc (make_thunk): Don't set TREE_PUBLIC on thunks if the target + function is external to the current compilation. + 2020-01-01 Jakub Jelinek Update copyright years. diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc index 3824060..7afb1aa 100644 --- a/gcc/d/decl.cc +++ b/gcc/d/decl.cc @@ -1803,8 +1803,11 @@ make_thunk (FuncDeclaration *decl, int offset) DECL_CONTEXT (thunk) = d_decl_context (decl); - /* Thunks inherit the public access of the function they are targetting. */ - TREE_PUBLIC (thunk) = TREE_PUBLIC (function); + /* Thunks inherit the public access of the function they are targetting. + When the function is outside the current compilation unit however, then the + thunk must be kept private to not conflict. */ + TREE_PUBLIC (thunk) = TREE_PUBLIC (function) && !DECL_EXTERNAL (function); + DECL_EXTERNAL (thunk) = 0; /* Thunks are always addressable. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f0d7033..a382072 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-16 Iain Buclaw + + PR d/92216 + * gdc.dg/imports/pr92216.d: New. + * gdc.dg/pr92216.d: New test. + 2020-03-16 Jakub Jelinek PR c/94179 diff --git a/gcc/testsuite/gdc.dg/imports/pr92216.d b/gcc/testsuite/gdc.dg/imports/pr92216.d new file mode 100644 index 0000000..b8c71c0 --- /dev/null +++ b/gcc/testsuite/gdc.dg/imports/pr92216.d @@ -0,0 +1,22 @@ +module imports.pr92216; + +class B : I +{ + protected override void getStruct(){} + mixin A!(); + +} + +mixin template A() +{ + public void* getS() + { + return null; + } +} + +public interface I +{ + public void* getS(); + protected void getStruct(); +} diff --git a/gcc/testsuite/gdc.dg/pr92216.d b/gcc/testsuite/gdc.dg/pr92216.d new file mode 100644 index 0000000..330604c --- /dev/null +++ b/gcc/testsuite/gdc.dg/pr92216.d @@ -0,0 +1,13 @@ +// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92216 +// { dg-options "-I $srcdir/gdc.dg" } +// { dg-do compile } +// { dg-final { scan-assembler "_DT16_D7imports7pr922161B8__mixin24getSMFZPv\[: \t\n\]" } } +// { dg-final { scan-assembler-not "(.globl|.global)\[ \]+_DT16_D7imports7pr922161B8__mixin24getSMFZPv" } } +module pr92216; + +private import imports.pr92216; + +class C : B +{ + protected override void getStruct() {} +} -- cgit v1.1 From 2691ffe6dbaffb704593dd6220178c28848b3855 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Mon, 16 Mar 2020 23:53:20 +0100 Subject: d: Fix assignment to anonymous union member corrupts sibling members in struct gcc/d/ChangeLog: PR d/92309 * types.cc (fixup_anonymous_offset): Don't set DECL_FIELD_OFFSET on anonymous fields. gcc/testsuite/ChangeLog: PR d/92309 * gdc.dg/pr92309.d: New test. --- gcc/d/ChangeLog | 6 ++++++ gcc/d/types.cc | 10 +++++++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gdc.dg/pr92309.d | 25 +++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gdc.dg/pr92309.d (limited to 'gcc') diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index d9c7657..ea43e3e 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,5 +1,11 @@ 2020-03-16 Iain Buclaw + PR d/92309 + * types.cc (fixup_anonymous_offset): Don't set DECL_FIELD_OFFSET on + anonymous fields. + +2020-03-16 Iain Buclaw + PR d/92216 * decl.cc (make_thunk): Don't set TREE_PUBLIC on thunks if the target function is external to the current compilation. diff --git a/gcc/d/types.cc b/gcc/d/types.cc index 736f128..866da96 100644 --- a/gcc/d/types.cc +++ b/gcc/d/types.cc @@ -234,16 +234,20 @@ insert_aggregate_field (tree type, tree field, size_t offset) static void fixup_anonymous_offset (tree fields, tree offset) { + /* No adjustment in field offset required. */ + if (integer_zerop (offset)) + return; + while (fields != NULL_TREE) { - /* Traverse all nested anonymous aggregates to update their offset. - Set the anonymous decl offset to its first member. */ + /* Traverse all nested anonymous aggregates to update the offset of their + fields. Note that the anonymous field itself is not adjusted, as it + already has an offset relative to its outer aggregate. */ tree ftype = TREE_TYPE (fields); if (TYPE_NAME (ftype) && IDENTIFIER_ANON_P (TYPE_IDENTIFIER (ftype))) { tree vfields = TYPE_FIELDS (ftype); fixup_anonymous_offset (vfields, offset); - DECL_FIELD_OFFSET (fields) = DECL_FIELD_OFFSET (vfields); } else { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a382072..0146f8d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2020-03-16 Iain Buclaw + PR d/92309 + * gdc.dg/pr92309.d: New test. + +2020-03-16 Iain Buclaw + PR d/92216 * gdc.dg/imports/pr92216.d: New. * gdc.dg/pr92216.d: New test. diff --git a/gcc/testsuite/gdc.dg/pr92309.d b/gcc/testsuite/gdc.dg/pr92309.d new file mode 100644 index 0000000..01ebc40 --- /dev/null +++ b/gcc/testsuite/gdc.dg/pr92309.d @@ -0,0 +1,25 @@ +// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92309 +// { dg-do run { target hw } } +// { dg-skip-if "needs gcc/config.d" { ! d_runtime } } + +union U +{ + struct + { + size_t a; + size_t b; + union + { + size_t c; + size_t d; + } + } +} + +void main() +{ + U u; + assert(u.a == 0); + u.d = 1; + assert(u.a == 0); +} -- cgit v1.1 From b3f246f12b236f063c008a6f4487de8881f534ec Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 17 Mar 2020 00:16:15 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 777d8ef..c73081a 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200316 +20200317 -- cgit v1.1 From 950183c774134410399a5ceeeec153f7d64ebe91 Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Tue, 17 Mar 2020 00:34:39 +0000 Subject: Update gcc sv.po. * sv.po: Update. --- gcc/po/ChangeLog | 4 ++ gcc/po/sv.po | 162 +++++++++++++++++++++++++++---------------------------- 2 files changed, 85 insertions(+), 81 deletions(-) (limited to 'gcc') diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index baf2c0b..22e630a 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2020-03-17 Joseph Myers + + * sv.po: Update. + 2020-03-10 Joseph Myers * sv.po: Update. diff --git a/gcc/po/sv.po b/gcc/po/sv.po index 1459163..49a8cd7 100644 --- a/gcc/po/sv.po +++ b/gcc/po/sv.po @@ -26,7 +26,7 @@ msgstr "" "Project-Id-Version: gcc 10.1-b20200209\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2020-02-07 22:33+0000\n" -"PO-Revision-Date: 2020-03-09 17:35+0100\n" +"PO-Revision-Date: 2020-03-15 12:22+0100\n" "Last-Translator: Göran Uddeborg \n" "Language-Team: Swedish \n" "Language: sv\n" @@ -11275,7 +11275,7 @@ msgstr "Aktivera generering av binärer som använder funktioner från libgcc f #: config/or1k/or1k.opt:46 msgid "Enable generation of binaries which use functions from libgcc to perform floating point operations. This is the default; use -mhard-float to override." -msgstr "" +msgstr "Aktivera generering av binärer som använder funktioner från libgcc för att utföra flyttalsoperationer. Detta är standard; använd -mhard-float för att åsidosätta." #: config/or1k/or1k.opt:51 #, fuzzy @@ -11285,11 +11285,11 @@ msgstr "Aktivera flyttalsinstruktioner i hårdvara." #: config/or1k/or1k.opt:56 msgid "When -mhard-float is selected, enables generation of double-precision floating point instructions. By default functions from libgcc are used to perform double-precision floating point operations." -msgstr "" +msgstr "När -mhard-float är valt, aktiverar generering av instruktioner för flyttal med dubbel precision. Som standard används funktioner från libgcc för att utföra operationer på flyttal med dubbel precision." #: config/or1k/or1k.opt:62 msgid "When -mhard-float is selected, enables generation of unordered floating point compare and set flag (lf.sfun*) instructions. By default functions from libgcc are used to perform unordered floating point compare and set flag operations." -msgstr "" +msgstr "När -mhard-float är valt, aktiverar generering av instruktioner för oordnad flyttalsjämförelse och för att sätta flaggor (lf.sfun*). Som standard används funktioner från libgcc för att utföra oordnad jämförelse av flyttal och operationer för att sätta flaggor." #: config/or1k/or1k.opt:68 #, fuzzy @@ -11299,11 +11299,11 @@ msgstr "Tillåt generering av binärer som använder instruktionen l.cmov. Om d #: config/or1k/or1k.opt:73 msgid "Enable generation of rotate right (l.ror) instructions. By default functions from libgcc are used to perform rotate right operations." -msgstr "" +msgstr "Aktivera generering av instruktioner för att rotera åt höger (l.ror). Som standard används funktioner från libgcc för att utföra operationer som roterar åt höger." #: config/or1k/or1k.opt:78 msgid "Enable generation of rotate right with immediate (l.rori) instructions. By default functions from libgcc are used to perform rotate right with immediate operations." -msgstr "" +msgstr "Aktivera generering av instruktioner för att rotera åt höger med omedelbar (l.rori). Som standard används funktioner från libgcc för att utföra operationer som roterar åt höger med omedelbar." #: config/or1k/or1k.opt:84 #, fuzzy @@ -13019,7 +13019,7 @@ msgstr "Generera kod med omvänd byteordning." #: config/bpf/bpf.opt:123 msgid "Set a hard limit for the size of each stack frame, in bytes." -msgstr "" +msgstr "Sätt en hård gräns på storleken av varje ram, i byte." #: config/mips/mips.opt:32 msgid "-mabi=ABI\tGenerate code that conforms to the given ABI." @@ -13757,11 +13757,11 @@ msgstr "Läget helprogramanalys (WPA) med antal parallella jobb angivna." #: lto/lang.opt:75 msgid "Call the dump function for variables and function in IL." -msgstr "" +msgstr "Anropa dumpfunktionen för variabler och funktioner i IL." #: lto/lang.opt:79 msgid "Dump the demangled output." -msgstr "" +msgstr "Dumpa den avmanglade utdatan." #: lto/lang.opt:83 #, fuzzy @@ -13777,11 +13777,11 @@ msgstr "Varna för oinitierade automatiska variabler." #: lto/lang.opt:91 msgid "Sort the symbols alphabetically." -msgstr "" +msgstr "Sortera symbolerna alfabetiskt." #: lto/lang.opt:95 msgid "Sort the symbols according to size." -msgstr "" +msgstr "Sortera symbolerna i storleksordning." #: lto/lang.opt:99 #, fuzzy @@ -13791,19 +13791,19 @@ msgstr "Visa kompilatorns version." #: lto/lang.opt:106 msgid "Dump the details of LTO objects." -msgstr "" +msgstr "Dumpa detaljerna om LTO-objekt." #: lto/lang.opt:110 msgid "Dump the statistics of tree types." -msgstr "" +msgstr "Dumpa statistiken om trädtyper." #: lto/lang.opt:114 msgid "Dump the statistics of trees." -msgstr "" +msgstr "Dumpa statistiken om träd." #: lto/lang.opt:118 msgid "Dump the statistics of gimple statements." -msgstr "" +msgstr "Dumpa statistiken om gimple-satser." #: lto/lang.opt:128 #, fuzzy @@ -13813,7 +13813,7 @@ msgstr "okänd kommandoradsflagga %qs" #: lto/lang.opt:132 msgid "Dump the symtab callgraph." -msgstr "" +msgstr "Dumpa symboltabellanropsgrafen." #: lto/lang.opt:136 msgid "The resolution file." @@ -14403,15 +14403,15 @@ msgstr "Lägg till lämpliga diagnostiska meddelanden till kommandoradsflaggan s #: common.opt:1343 msgid "Print CWE identifiers for diagnostic messages, where available." -msgstr "" +msgstr "Skriv ut CWE-identifierare för felmeddelanden, där de är tillgängliga." #: common.opt:1347 msgid "Specify how to print any control-flow path associated with a diagnostic." -msgstr "" +msgstr "Ange hur kontrollflödesvägen associerad med ett felmeddelande skrivs ut." #: common.opt:1363 msgid "Show stack depths of events in paths." -msgstr "" +msgstr "Visa stackdjup för händelser i vägar." #: common.opt:1367 msgid "Set minimum width of left margin of source code when showing source." @@ -14511,7 +14511,7 @@ msgstr "Anta att inga NaN:er eller oändligheter genereras." #: common.opt:1494 msgid "Assume that loops with an exit will terminate and not loop indefinitely." -msgstr "" +msgstr "Anta att slingor med en utgång kommer avsluta och inte snurra i oändlighet." #: common.opt:1498 msgid "-ffixed-\tMark as being unavailable to the compiler." @@ -15023,7 +15023,7 @@ msgstr "Aktivera vanliga flaggor för att generera profileringsinformation för #: common.opt:2193 msgid "Do not assume that functions never executed during the train run are cold." -msgstr "" +msgstr "Anta inte att funktioner som aldrig exekveras under tågkörningen är kalla." #: common.opt:2197 msgid "Enable common options for performing profile feedback directed optimizations." @@ -15071,7 +15071,7 @@ msgstr "-flive-patching=[inline-only-static|inline-clone]\tStyr IPA-optimeringar #: common.opt:2272 msgid "Tell DCE to remove unused C++ allocations." -msgstr "" +msgstr "Säg till DCE att ta bort oanvända C++-allokeringar." #: common.opt:2276 msgid "Relief of register pressure through live range shrinkage." @@ -15940,7 +15940,7 @@ msgstr "Minsta heap-storlek före vi börjar samla skräp, i kilobyte." #: params.opt:143 msgid "The number of executions of a basic block which is considered hot. The parameter is used only in GIMPLE FE." -msgstr "" +msgstr "Antalet körningar av ett grundblock som betraktas som varmt. Parametern används bara i GIMPLE FE." #: params.opt:147 msgid "Whether codegen errors should be ICEs when -fchecking." @@ -15956,7 +15956,7 @@ msgstr "Maximalt antal parameter i en SCoP." #: params.opt:159 msgid "The number of elements for which hash table verification is done for each searched element." -msgstr "" +msgstr "Antalet element för vilka verfiering av hashtabellen görs för varje sökt element." #: params.opt:163 #, fuzzy @@ -15966,7 +15966,7 @@ msgstr "Välj andel av det maximala antalet repetitioner av grundblock i program #: params.opt:167 msgid "The number of most executed permilles of the profiled execution of the entire program to which the execution count of a basic block must be part of in order to be considered hot (used in LTO mode)." -msgstr "" +msgstr "Antalet mest exekverade promille av den profilerade körningen av hela programmet till vilken körningsräknaren för ett grundblock måste vara en del av för att betraktas som varm (används i LTO-läge)." #: params.opt:171 #, fuzzy @@ -15980,7 +15980,7 @@ msgstr "Nivå av pratsamhet om hsa-felsökningslagringar." #: params.opt:179 msgid "The scale (in percents) applied to inline-insns-single and auto limits when heuristics hints that inlining is very profitable." -msgstr "" +msgstr "Skalan (i procent) tillämpad på inline-insns-single och automatiska gränser när heuristik indikerar att inline:ing är väldigt lönsamt." #: params.opt:183 msgid "The minimal estimated speedup allowing inliner to ignore inline-insns-single and inline-insns-auto." @@ -16046,11 +16046,11 @@ msgstr "Maximalt antal villkorliga lagringspar som kan sänkas." #: params.opt:239 msgid "Maximal number of boundary endpoints of case ranges of switch statement used during IPA functoin summary generation." -msgstr "" +msgstr "Maximala antalet gränsändpunkter för case-intervall i switch-satser som är oanvända under IPA-funktionssammanfattningsgenerering." #: params.opt:243 msgid "Maximum pieces that IPA-SRA tracks per formal parameter, as a consequence, also the maximum number of replacements of a formal parameter." -msgstr "" +msgstr "Maximala antalet delar som IPA-SRA följer per formell parameter, och som en konsekvens, även det maximala antalet ersättningar av en formell parameter." #: params.opt:247 msgid "Maximum allowed growth of number and total size of new parameters that ipa-sra replaces a pointer to an aggregate with." @@ -16082,11 +16082,11 @@ msgstr "Gräns för antal iv-användningar i en slinga optimerad i iv-optimering #: params.opt:275 msgid "The maximum code size growth ratio when expanding into a jump table (in percent). The parameter is used when optimizing for size." -msgstr "" +msgstr "Det maximala förhållandet för tillväxt av kod vid expansion till en hopptabell (i procent). Parametern används vid optimering för storlek." #: params.opt:279 msgid "The maximum code size growth ratio when expanding into a jump table (in percent). The parameter is used when optimizing for speed." -msgstr "" +msgstr "Det maximala förhållandet för tillväxt av kod vid expansion till en hopptabell (i procent). Parametern används vid optimering för fart." #: params.opt:283 msgid "The size of L1 cache line." @@ -16483,7 +16483,7 @@ msgstr "Minsta förhållande av instruktioner till minnesoperationer för att ak #: params.opt:683 msgid "The minimum threshold for probability of semi-invariant condition statement to trigger loop split." -msgstr "" +msgstr "Den minsta tröskelvärdet för sannolikheten för semi-invarianta villkorssatser för att utlösa slingdelning." #: params.opt:687 msgid "The minimum UID to be used for a nondebug insn." @@ -16653,7 +16653,7 @@ msgstr "Tillåt passet för lagringssammanslagning att introducera ojusterade la #: params.opt:865 msgid "Maximum size of a single store merging region in bytes." -msgstr "" +msgstr "Maximala storleken på en enda lagringssammanslagningsregion i byte." #: params.opt:869 msgid "The maximum ratio between array size and switch branches for a switch conversion to take place." @@ -17228,7 +17228,7 @@ msgstr "%<(%> eller filslut förväntades" #: attribs.c:589 #, gcc-internal-format, gfc-internal-format msgid "expected between %i and %i, found %i" -msgstr "" +msgstr "värde mellan %i och %i förväntades, %i fanns" #: attribs.c:609 c-family/c-attribs.c:3795 #, gcc-internal-format @@ -17894,12 +17894,12 @@ msgstr "%Kargument %i:s värde %qE är negativt" #: calls.c:2103 #, gcc-internal-format msgid "%Kargument %i is null but the corresponding size argument %i value is %E" -msgstr "" +msgstr "%Kargument %i är null men värdet på det motsvarande storleksargumentet %i är %E" #: calls.c:2108 #, gcc-internal-format msgid "%Kargument %i is null but the corresponding size argument %i range is [%E, %E]" -msgstr "" +msgstr "%Kargument %i är null men intervallet för det motsvarande storleksargumentet %i är [%E, %E]" #: calls.c:2160 #, fuzzy, gcc-internal-format @@ -18551,42 +18551,42 @@ msgstr "antal anropande bågar är felaktigt" #: cgraph.c:3185 #, gcc-internal-format msgid "missing indirect call in speculative call sequence" -msgstr "" +msgstr "saknat indirekt anrop i en spekulativ anropssekvens" #: cgraph.c:3190 #, gcc-internal-format msgid "indirect call in speculative call sequence has no speculative flag" -msgstr "" +msgstr "indirekt anrop i en spekulativ anropssekvens har ingen spekulativ flagga" #: cgraph.c:3220 #, gcc-internal-format msgid "speculative edges are not adjacent" -msgstr "" +msgstr "spekulativa bågar är inte närliggande" #: cgraph.c:3226 #, gcc-internal-format, gfc-internal-format msgid "direct call to %s in speculative call sequence has no speculative flag" -msgstr "" +msgstr "direkt anrop av %s i en spekulativ anropssekven har ingen spekulativ flagga" #: cgraph.c:3232 cgraph.c:3262 #, gcc-internal-format, gfc-internal-format msgid "direct call to %s in speculative call sequence has speculative_uid %i out of range" -msgstr "" +msgstr "direkt anrop av %s i en spekulati anropssekven har speculative_uid %i utanför intervallet" #: cgraph.c:3239 #, gcc-internal-format, gfc-internal-format msgid "duplicate direct call to %s in speculative call sequence with speculative_uid %i" -msgstr "" +msgstr "dubblerat direkt anrop av %s i en spekulativ anropssekvens med spekulativ_uid %i" #: cgraph.c:3250 #, gcc-internal-format msgid "call stmt hash does not point to first direct edge of speculative call sequence " -msgstr "" +msgstr "call stmt-hachen pekar inte på den första direkta bågen av en spekulativ anropssekvens " #: cgraph.c:3269 #, gcc-internal-format, gfc-internal-format msgid "duplicate reference %s in speculative call sequence with speculative_uid %i" -msgstr "" +msgstr "dubblerad referens %s i en spekulativ anropssekvens med spekulativ_uid %i" #: cgraph.c:3282 #, fuzzy, gcc-internal-format, gfc-internal-format @@ -18603,7 +18603,7 @@ msgstr "barriär saknas efter block %i" #: cgraph.c:3296 #, gcc-internal-format, gfc-internal-format msgid "number of speculative targets %i mismatched with num_speculative_targets %i" -msgstr "" +msgstr "antalet spekulativa mål %i stämmer inte med num_speculative_targets %i" #: cgraph.c:3325 #, gcc-internal-format, gfc-internal-format @@ -18655,7 +18655,7 @@ msgstr "inline-klon tvingas till utdata" #: cgraph.c:3374 #, gcc-internal-format msgid "calls_comdat_local is set outside of a comdat group" -msgstr "" +msgstr "calls_comdat_local är satt utanför någon comdat-grupp" #: cgraph.c:3381 #, gcc-internal-format, gfc-internal-format @@ -18676,7 +18676,7 @@ msgstr "En indirektbåge från %s är inte markerad som indirekt eller har assoc #: cgraph.c:3403 cgraph.c:3474 #, gcc-internal-format msgid "edge has both cal_stmt and lto_stmt_uid set" -msgstr "" +msgstr "bågen har både cal_stmt och lto_stmt_uid satta" #: cgraph.c:3415 #, gcc-internal-format, gfc-internal-format @@ -18711,7 +18711,7 @@ msgstr "indirekta anropsantal stämmer inte med GB-antal" #: cgraph.c:3512 #, gcc-internal-format msgid "reference has both cal_stmt and lto_stmt_uid set" -msgstr "" +msgstr "referensen har både cal_stmt och lto_stmt_uid satta" #: cgraph.c:3523 #, gcc-internal-format @@ -18821,7 +18821,7 @@ msgstr "en indirekt båge från %s har inget motsvarande call_stmt" #: cgraph.c:3728 cgraph.c:3741 #, gcc-internal-format msgid "missing origin for a node in a nested list" -msgstr "" +msgstr "ursprung saktas för en nod i en nästad lista" #: cgraph.c:3733 #, fuzzy, gcc-internal-format @@ -18843,7 +18843,7 @@ msgstr "%s sektion %s saknas" #: cgraphunit.c:726 #, gcc-internal-format msgid "multiple versions for one symbol" -msgstr "" +msgstr "multipla versioner för en symbol" #: cgraphunit.c:737 #, fuzzy, gcc-internal-format @@ -18860,7 +18860,7 @@ msgstr "tidigare definition här" #: cgraphunit.c:745 #, gcc-internal-format msgid "symbol needs to be defined to have a version" -msgstr "" +msgstr "symbolen behöver definieras för att ha en version" #: cgraphunit.c:751 #, fuzzy, gcc-internal-format @@ -18889,7 +18889,7 @@ msgstr "svagdeklaration av %q+D måste vara publik" #: cgraphunit.c:775 #, gcc-internal-format msgid "versioned symbol must have default visibility" -msgstr "" +msgstr "versionerade symboler måste ha standardsynlighet" #: cgraphunit.c:807 #, gcc-internal-format @@ -19321,7 +19321,7 @@ msgstr "bytekodström: hittade sträng som inte var nollterminerad" #: dbgcnt.c:128 #, gcc-internal-format msgid "Interval overlap of %<-fdbg-cnt=%s%>: [%u, %u] and [%u, %u]\n" -msgstr "" +msgstr "Intervallen överlappar i %<-fdbg-cnt=%s%>: [%u, %u] och [%u, %u]\n" #: dbgcnt.c:143 #, fuzzy, gcc-internal-format @@ -20560,7 +20560,7 @@ msgstr "direktivprecisionen %<%.*s%> är utanför intervallet" #: gimple-ssa-sprintf.c:3903 msgid "%qE arguments %Z and maybe %Z overlap destination object %qE" -msgstr "" +msgstr "argumentet %qE %Z och kanske %Z överlappar destinationsobjektet %qE" #: gimple-ssa-sprintf.c:3915 #, fuzzy @@ -20582,7 +20582,7 @@ msgstr[1] "%qE-utdata på %wu byte in i en destination med storlek %wu" #: gimple-ssa-sprintf.c:3946 #, gcc-internal-format msgid "destination object referenced by %-qualified argument 1 was declared here" -msgstr "" +msgstr "destinationtionsobjektet som refereras av det %-kvalificerade argument 1 deklarerades här" #: gimple-ssa-sprintf.c:4536 #, gcc-internal-format @@ -21098,7 +21098,7 @@ msgstr "%qs %-klausulmodifierare förväntades snarare än %qs" #: gimplify.c:9696 #, gcc-internal-format msgid "%qD specified in %qs clause but not in % % clause on the containing construct" -msgstr "" +msgstr "%qD angivet i en %qs-klausul men inte i en % %-klausul av den inneslutande konstruktionen" #: gimplify.c:9906 #, gcc-internal-format @@ -21129,7 +21129,7 @@ msgstr "inkompatibel dataklausul med reduktion på %qE; befordrar till present_o #: gimplify.c:10478 #, gcc-internal-format msgid "%qD specified in % % clause but not in % directive clause" -msgstr "" +msgstr "%qD angivet i en % %-klausul men inte i en %-direktivklausul" #: gimplify.c:10497 #, gcc-internal-format @@ -21650,22 +21650,22 @@ msgstr "ipa-referenssammanfattning saknas i ltrans-enhet" #: ipa-sra.c:1466 #, gcc-internal-format msgid "Access offset before parent offset" -msgstr "" +msgstr "Åtkomstavstånd före föräldraavståndet" #: ipa-sra.c:1471 #, gcc-internal-format msgid "Access size greater or equal to its parent size" -msgstr "" +msgstr "Atkomststorleken är större eller lika med sin förälderstorlek" #: ipa-sra.c:1476 #, gcc-internal-format msgid "Access terminates outside of its parent" -msgstr "" +msgstr "Åtkomsten slutar utanför sin förälder" #: ipa-sra.c:1488 #, gcc-internal-format msgid "Access overlaps with its sibling" -msgstr "" +msgstr "Åtkomsten överlappar med sitt syskon" #: ipa-sra.c:1507 #, fuzzy, gcc-internal-format @@ -21676,12 +21676,12 @@ msgstr "HSA SSA-verifiering misslyckades" #: ipa-sra.c:2456 #, gcc-internal-format msgid "Function %qs, parameter %u, has IPA-SRA accesses which overlap" -msgstr "" +msgstr "Funktionen %qs, parametern %u, har IPA-SRA-åtkomst som överlappar" #: ipa-sra.c:2459 #, gcc-internal-format, gfc-internal-format msgid "Function %s, parameter %u, is used but does not have any certain IPA-SRA access" -msgstr "" +msgstr "Funktionen %s, parameter %u, används men har inte någon säker IPA-SRA-åtkomst" #: ira.c:2305 ira.c:2323 #, fuzzy, gcc-internal-format @@ -21795,12 +21795,12 @@ msgstr "komprimerad ström: %s" #: lto-compress.c:162 #, gcc-internal-format msgid "original not compressed with zstd" -msgstr "" +msgstr "originalet är inte komprimerat med zstd" #: lto-compress.c:164 #, gcc-internal-format msgid "original size unknown" -msgstr "" +msgstr "originalstorleken är okänd" #: lto-compress.c:170 #, fuzzy, gcc-internal-format, gfc-internal-format @@ -21857,22 +21857,22 @@ msgstr "det går inte att läsa LTO-lägestabellen från %s" #: lto-streamer-in.c:1710 #, gcc-internal-format msgid "%s - %u-bit-precision floating-point numbers unsupported (mode %qs)" -msgstr "" +msgstr "%s — %u-bitarsprecisions flyttal stödjs inte (läge %qs)" #: lto-streamer-in.c:1715 #, gcc-internal-format msgid "%s - %u-bit-precision decimal floating-point numbers unsupported (mode %qs)" -msgstr "" +msgstr "%s — %u-bitarsprecisions decimala flyttal stödjs inte (läge %qs)" #: lto-streamer-in.c:1720 #, gcc-internal-format msgid "%s - %u-bit-precision complex floating-point numbers unsupported (mode %qs)" -msgstr "" +msgstr "%s — %u-bitarsprecisions komplexa flyttal stödjs inte (läge %qs)" #: lto-streamer-in.c:1725 #, gcc-internal-format msgid "%s - %u-bit integer numbers unsupported (mode %qs)" -msgstr "" +msgstr "%s — %u-bitars heltal stödjs inte (läge %qs)" #: lto-streamer-in.c:1728 #, fuzzy, gcc-internal-format @@ -22045,7 +22045,7 @@ msgstr "%-klausul med %-modifierare refererar till en iteration #: omp-general.c:1751 #, gcc-internal-format msgid "%qs specifies a conflicting level of parallelism" -msgstr "" +msgstr "%qs anger en motstridig nivå av parallellism" #: omp-general.c:1754 #, fuzzy, gcc-internal-format @@ -22056,12 +22056,12 @@ msgstr "tidigare använt här" #: omp-general.c:1814 #, gcc-internal-format msgid "incompatible %qs clause when applying %<%s%> to %qD, which has already been marked with an OpenACC 'routine' directive" -msgstr "" +msgstr "inkompatibel %qs-klausul när %<%s%> används på %qD, som redan har markerats med ett OpenACC ”routine”-direktiv" #: omp-general.c:1821 #, gcc-internal-format msgid "missing %qs clause when applying %<%s%> to %qD, which has already been marked with an OpenACC 'routine' directive" -msgstr "" +msgstr "saknad %qs-klausul när %<%s%> används på %qD, som redan har markerats med ett OpenACC ”routine”-direktiv" #: omp-general.c:1830 #, fuzzy, gcc-internal-format @@ -22072,7 +22072,7 @@ msgstr "switch börjar här" #: omp-general.c:1838 #, gcc-internal-format msgid "... without %qs clause near to here" -msgstr "" +msgstr "… utan en %qs-klausul i närheten av här" #: omp-low.c:2380 omp-offload.c:1193 #, gcc-internal-format @@ -22110,7 +22110,7 @@ msgstr "ingen tidigare deklaration av %qD" #: omp-low.c:2525 #, gcc-internal-format msgid "nested loop in reduction needs reduction clause for %qE" -msgstr "" +msgstr "nästad slinga i en reduktion behöver en reduktionsklausul för %qE" #: omp-low.c:2818 #, gcc-internal-format @@ -22291,7 +22291,7 @@ msgstr "setjmp/longjmp inuti simd-konstruktion" #: omp-low.c:3712 #, gcc-internal-format msgid "OpenMP runtime API call %qD in a region with % clause" -msgstr "" +msgstr "OpenMP-körtids-API-anrop %qD i en region med en %-klausul" #: omp-low.c:8881 #, gcc-internal-format @@ -23134,7 +23134,7 @@ msgstr "starten på ett RTL-fragment måste vara på en tidigare rad än slutet" #: read-rtl.c:424 #, gcc-internal-format, gfc-internal-format msgid "ambiguous attribute '%s'; could be '%s' (via '%s:%s') or '%s' (via '%s:%s')" -msgstr "" +msgstr "tvetydigt attribut ”%s”; kunde vara ”%s” (via ”%s:%s”) eller ”%s” (via ”%s:%s”)" #: reg-stack.c:537 #, gcc-internal-format, gfc-internal-format @@ -23560,7 +23560,7 @@ msgstr "noden är ett alias men inte ett implicit alias" #: symtab.c:1170 #, gcc-internal-format msgid "symver target is not exported with default visibility" -msgstr "" +msgstr "symver-målet exporteras inte med standardsynlighet" #: symtab.c:1177 #, fuzzy, gcc-internal-format @@ -24050,7 +24050,7 @@ msgstr "typfel i vektorreferens" #: tree-cfg.c:3120 #, gcc-internal-format msgid "non-top-level %qs" -msgstr "" +msgstr "icke-toppnivås %qs" #: tree-cfg.c:3135 #, fuzzy, gcc-internal-format @@ -25026,7 +25026,7 @@ msgstr "direktivet %<%.*s%> skrev mellan %wu och %wu byte till en region med sto #: tree-ssa-strlen.c:2221 #, gcc-internal-format msgid "at offset %s to object %qD with size %E declared here" -msgstr "" +msgstr "vid avståndet %s till objekt %qD med storlek %E deklarerad här" #: tree-ssa-strlen.c:2225 #, fuzzy, gcc-internal-format @@ -25037,12 +25037,12 @@ msgstr "i ett anrop till funktionen %qD deklarerad här" #: tree-ssa-strlen.c:2257 #, gcc-internal-format msgid "at offset %s to an object with size %wu declared here" -msgstr "" +msgstr "vid avståndet %s till ett objekt med storlek %wu deklarerat här" #: tree-ssa-strlen.c:2265 #, gcc-internal-format msgid "at offset %s to an object with size at most %wu declared here" -msgstr "" +msgstr "vid avståndet %s till ett objekt med storlek högst %wu deklarerat här" #: tree-ssa-strlen.c:2270 #, fuzzy, gcc-internal-format, gfc-internal-format @@ -25058,7 +25058,7 @@ msgstr "" #: tree-ssa-strlen.c:2282 #, gcc-internal-format msgid "at offset %s to an object with size %wu allocated by %qE here" -msgstr "" +msgstr "vid avståndet %s till ett objekt med storlek %wu allokerad av %qE här" #: tree-ssa-strlen.c:2290 #, gcc-internal-format -- cgit v1.1 From 57e7ad5a8fd5a7bddf15e2fede6d2546cc6a2797 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Mon, 16 Mar 2020 21:16:35 -0400 Subject: c++: Add test for PR 93901. --- gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept57.C (limited to 'gcc') diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept57.C b/gcc/testsuite/g++.dg/cpp0x/noexcept57.C new file mode 100644 index 0000000..aca9891 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/noexcept57.C @@ -0,0 +1,40 @@ +// PR c++/93901 +// { dg-do compile { target c++11 } } + +void *operator new (__SIZE_TYPE__, void *p) noexcept { return p; } + +extern void *mem; + +constexpr bool YES = true; + +struct NoexceptTrueCtor { + NoexceptTrueCtor() noexcept(true); +}; +void NoexceptTrueFun() noexcept(true); + +struct NoexceptYesCtor { + NoexceptYesCtor() noexcept(YES); +}; +void NoexceptYesFun() noexcept(YES); + +struct NoexceptOneEqOneCtor { + NoexceptOneEqOneCtor() noexcept(1 == 1); +}; +void NoexceptOneEqOneFun() noexcept(1 == 1); + +struct NoNoexceptCtor { + NoNoexceptCtor(); +}; +void NoNoexceptFun(); + +static_assert(noexcept(new(mem) NoexceptTrueCtor), "2"); // OK +static_assert(noexcept(NoexceptTrueFun()), "3"); // OK + +static_assert(noexcept(new(mem) NoexceptYesCtor), "5"); // fail +static_assert(noexcept(NoexceptYesFun()), "6"); // OK + +static_assert(noexcept(new(mem) NoexceptOneEqOneCtor), "8"); // fail +static_assert(noexcept(NoexceptOneEqOneFun()), "9"); // OK + +static_assert(!noexcept(new(mem) NoNoexceptCtor), "11"); // OK +static_assert(!noexcept(NoNoexceptFun()), "12"); // OK -- cgit v1.1 From ecf2b69a629d4f79efe3c103fe54040437ea18a6 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Tue, 17 Mar 2020 09:43:46 +0100 Subject: Filter a test-case with gas. PR lto/94157 * gcc.dg/lto/pr94157_0.c: Add gas effective target filter. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/lto/pr94157_0.c | 1 + 2 files changed, 7 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0146f8d..ac9f077 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-17 Martin Liska + + PR lto/94157 + * gcc.dg/lto/pr94157_0.c: Add gas effective + target filter. + 2020-03-16 Iain Buclaw PR d/92309 diff --git a/gcc/testsuite/gcc.dg/lto/pr94157_0.c b/gcc/testsuite/gcc.dg/lto/pr94157_0.c index 3bca677..a6e308b 100644 --- a/gcc/testsuite/gcc.dg/lto/pr94157_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr94157_0.c @@ -1,4 +1,5 @@ /* { dg-lto-do link } */ +/* { dg-require-effective-target gas } */ /* { dg-lto-options { { -O0 -fipa-vrp -flto -Wa,--noexecstack -Wa,--noexecstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack -Wa,--execstack } } } */ int main() { -- cgit v1.1 From 7afa3b82918a75a486aad7818f11df9ea7504368 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 10:42:35 +0100 Subject: expand: Don't depend on warning flags in code generation of strnlen [PR94189] The following testcase FAILs with -O2 -fcompare-debug, but the reason isn't that we'd emit different code based on -g or non-debug, but rather that we emit different code depending on whether -w is used or not (or e.g. -Wno-stringop-overflow or whether some other pass emitted some other warning already on the call). Code generation shouldn't depend on whether we emit a warning or not if at all possible. The following patch punts (i.e. doesn't optimize the strnlen call to a constant value) if we would emit the warning if it was enabled. In the PR there is an alternate patch which does optimize the strnlen call no matter if we emit the warning or not, though I think I prefer the version below, e.g. the strnlen call might be crossing field boundaries, which is in strict reading undefined, but I'd be afraid people do that in the real world programs. 2020-03-17 Jakub Jelinek PR middle-end/94189 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would emit a warning if it was enabled and don't depend on TREE_NO_WARNING for code-generation. * gcc.dg/pr94189.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/builtins.c | 22 ++++++++++------------ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr94189.c | 11 +++++++++++ 4 files changed, 33 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94189.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 25a27f8..fc35cea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-17 Jakub Jelinek + + PR middle-end/94189 + * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would + emit a warning if it was enabled and don't depend on TREE_NO_WARNING + for code-generation. + 2020-03-16 Vladimir Makarov PR target/94185 diff --git a/gcc/builtins.c b/gcc/builtins.c index e4a8694..53bae59 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -3142,27 +3142,25 @@ expand_builtin_strnlen (tree exp, rtx target, machine_mode target_mode) return NULL_RTX; } - if (lendata.decl - && !TREE_NO_WARNING (exp) - && ((tree_int_cst_lt (len, bound)) - || !exact)) + if (lendata.decl && (tree_int_cst_lt (len, bound) || !exact)) { location_t warnloc = expansion_point_location_if_in_system_header (loc); - if (warning_at (warnloc, OPT_Wstringop_overflow_, - exact - ? G_("%K%qD specified bound %E exceeds the size %E " - "of unterminated array") - : G_("%K%qD specified bound %E may exceed the size " - "of at most %E of unterminated array"), - exp, func, bound, len)) + if (!TREE_NO_WARNING (exp) + && warning_at (warnloc, OPT_Wstringop_overflow_, + exact + ? G_("%K%qD specified bound %E exceeds the size " + "%E of unterminated array") + : G_("%K%qD specified bound %E may exceed the " + "size of at most %E of unterminated array"), + exp, func, bound, len)) { inform (DECL_SOURCE_LOCATION (lendata.decl), "referenced argument declared here"); TREE_NO_WARNING (exp) = true; - return NULL_RTX; } + return NULL_RTX; } if (!len) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ac9f077..879a67d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Jakub Jelinek + + PR middle-end/94189 + * gcc.dg/pr94189.c: New test. + 2020-03-17 Martin Liska PR lto/94157 diff --git a/gcc/testsuite/gcc.dg/pr94189.c b/gcc/testsuite/gcc.dg/pr94189.c new file mode 100644 index 0000000..f927d55 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94189.c @@ -0,0 +1,11 @@ +/* PR middle-end/94189 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +const char a[] = { 'a', 'b', 'c', 'd' };/* { dg-message "declared here" } */ + +int +foo (void) +{ + return __builtin_strnlen (a, 5); /* { dg-warning "specified bound 5 exceeds the size 4 of unterminated array" } */ +} -- cgit v1.1 From 741ff2a263fe0ddc343288331c0047c1a32af8b2 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 10:43:46 +0100 Subject: strlen: Punt on UB reads past end of string literal [PR94187] The gcc.dg/pr68785.c test which contains: int foo (void) { return *(int *) ""; } has UB in the program if it is ever called, but causes UB in the compiler as well as at least in theory non-reproduceable code generation. The problem is that nbytes is in this case 4, prep is the TREE_STRING_POINTER of a "" string literal with TREE_STRING_LENGTH of 1 and we do: 4890 for (const char *p = prep; p != prep + nbytes; ++p) 4891 if (*p) 4892 { 4893 *allnul = false; 4894 break; 4895 } and so read the bytes after the STRING_CST payload, which can be random. I think we should just punt in this case. 2020-03-17 Jakub Jelinek PR tree-optimization/94187 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if nchars - offset < nbytes. --- gcc/ChangeLog | 4 ++++ gcc/tree-ssa-strlen.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fc35cea..f8105cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2020-03-17 Jakub Jelinek + PR tree-optimization/94187 + * tree-ssa-strlen.c (count_nonzero_bytes): Punt if + nchars - offset < nbytes. + PR middle-end/94189 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would emit a warning if it was enabled and don't depend on TREE_NO_WARNING diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index 0d70f3c..ec33d7c 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -4822,6 +4822,8 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, of the access), set it here to the size of the string, including all internal and trailing nuls if the string has any. */ nbytes = nchars - offset; + else if (nchars - offset < nbytes) + return false; prep = TREE_STRING_POINTER (exp) + offset; } -- cgit v1.1 From fd857de80705be937d9780dbd394d006151713fe Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 17 Mar 2020 09:26:08 +0000 Subject: c: ignore initializers for elements of variable-size types [PR93577] 2020-03-17 Christophe Lyon gcc/ * c-typeck.c (process_init_element): Handle constructor_type with type size represented by POLY_INT_CST. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Remove superfluous dg-error. * gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise. --- gcc/ChangeLog | 5 +++++ gcc/c/c-typeck.c | 2 +- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c | 1 - gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c | 1 - 5 files changed, 12 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f8105cc..06c7db0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Christophe Lyon + + * c-typeck.c (process_init_element): Handle constructor_type with + type size represented by POLY_INT_CST. + 2020-03-17 Jakub Jelinek PR tree-optimization/94187 diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index d8025de..490d8fc 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -9968,7 +9968,7 @@ process_init_element (location_t loc, struct c_expr value, bool implicit, /* Ignore elements of an initializer for a variable-size type. Those are diagnosed in digest_init. */ if (COMPLETE_TYPE_P (constructor_type) - && TREE_CODE (TYPE_SIZE (constructor_type)) != INTEGER_CST) + && !poly_int_tree_p (TYPE_SIZE (constructor_type))) return; if (!implicit && warn_designated_init && !was_designated diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 879a67d..aaf973a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-17 Christophe Lyon + + * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Remove + superfluous dg-error. + * gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise. + 2020-03-17 Jakub Jelinek PR middle-end/94189 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c index 045963d..7fc51e7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-1.c @@ -83,7 +83,6 @@ statements (int n) svint8_t array[2]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ svint8_t zero_length_array[0]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ svint8_t empty_init_array[] = {}; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ - /* { dg-error {empty scalar initializer} "" { target *-*-* } .-1 } */ typedef svint8_t vla_type[n]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ /* Assignment. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c index c7282fa..3af36de 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/sizeless-2.c @@ -83,7 +83,6 @@ statements (int n) svint8_t array[2]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ svint8_t zero_length_array[0]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ svint8_t empty_init_array[] = {}; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ - /* { dg-error {empty scalar initializer} "" { target *-*-* } .-1 } */ typedef svint8_t vla_type[n]; /* { dg-error {array elements cannot have SVE type 'svint8_t'} } */ /* Assignment. */ -- cgit v1.1 From 994d48620621fa33d32018be5fb70042e38546d5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 11:12:59 +0100 Subject: testsuite: Fix pr94185.C testcase on i686-linux with C++98 [PR94185] I'm getting on i686-linux FAIL: g++.target/i386/pr94185.C -std=gnu++98 (test for excess errors) This is because of a diagnostic that 4294967295 is unsigned only in ISO C90. Adding U suffix fixes it and the testcase still ICEs with unfixed gcc and passes with current trunk. 2020-03-17 Jakub Jelinek PR target/94185 * g++.target/i386/pr94185.C (l): Use 4294967295U instead of 4294967295 to avoid FAIL with -m32 -std=c++98. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/g++.target/i386/pr94185.C | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index aaf973a..cb81b72 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-17 Jakub Jelinek + + PR target/94185 + * g++.target/i386/pr94185.C (l): Use 4294967295U instead of 4294967295 + to avoid FAIL with -m32 -std=c++98. + 2020-03-17 Christophe Lyon * gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Remove diff --git a/gcc/testsuite/g++.target/i386/pr94185.C b/gcc/testsuite/g++.target/i386/pr94185.C index 587b7ba..2b3f7a1 100644 --- a/gcc/testsuite/g++.target/i386/pr94185.C +++ b/gcc/testsuite/g++.target/i386/pr94185.C @@ -22,7 +22,7 @@ int d; void l(char *, ar m, long n) { switch (m.au[d]) case 0: - n &= 4294967295; + n &= 4294967295U; bb.h(0).g(n); } void o() { -- cgit v1.1 From 14782c8123ea7e55723cfc4fc30d726cd94851dc Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 10:19:31 +0000 Subject: [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. This patch supports MVE ACLE intrinsics vst4q_s8, vst4q_s16, vst4q_s32, vst4q_u8, vst4q_u16, vst4q_u32, vst4q_f16 and vst4q_f32. In this patch arm_mve_builtins.def file is added to the source code in which the builtins for MVE ACLE intrinsics are defined using builtin qualifiers. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (CF): Define mve_builtin_data. (VAR1): Define. (ARM_BUILTIN_MVE_PATTERN_START): Define. (arm_init_mve_builtins): Define function. (arm_init_builtins): Add TARGET_HAVE_MVE check. (arm_expand_builtin_1): Check the range of fcode. (arm_expand_mve_builtin): Define function to expand MVE builtins. (arm_expand_builtin): Check the range of fcode. * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point types. (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. (vst4q_s8): Define macro. (vst4q_s16): Likewise. (vst4q_s32): Likewise. (vst4q_u8): Likewise. (vst4q_u16): Likewise. (vst4q_u32): Likewise. (vst4q_f16): Likewise. (vst4q_f32): Likewise. (__arm_vst4q_s8): Define inline builtin. (__arm_vst4q_s16): Likewise. (__arm_vst4q_s32): Likewise. (__arm_vst4q_u8): Likewise. (__arm_vst4q_u16): Likewise. (__arm_vst4q_u32): Likewise. (__arm_vst4q_f16): Likewise. (__arm_vst4q_f32): Likewise. (__ARM_mve_typeid): Define macro with MVE types. (__ARM_mve_coerce): Define macro with _Generic feature. (vst4q): Define polymorphic variant for different vst4q builtins. * config/arm/arm_mve_builtins.def: New file. * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI modes in MVE. * config/arm/mve.md (MVE_VLD_ST): Define iterator. (unspec): Define unspec. (mve_vst4q): Define RTL pattern. * config/arm/neon.md (mov): Modify expand to allow XI and OI modes in MVE. (neon_mov): Modify RTL define_insn to allow XI and OI modes in MVE. (define_split): Allow OI mode split for MVE after reload. (define_split): Allow XI mode split for MVE after reload. * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. (arm-builtins.o): Likewise. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vst4q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. --- gcc/ChangeLog | 49 +++ gcc/config/arm/arm-builtins.c | 67 ++++- gcc/config/arm/arm_mve.h | 331 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 21 ++ gcc/config/arm/iterators.md | 3 +- gcc/config/arm/mve.md | 39 ++- gcc/config/arm/neon.md | 8 +- gcc/config/arm/t-arm | 4 +- gcc/testsuite/ChangeLog | 13 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 38 +++ .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 38 +++ 17 files changed, 829 insertions(+), 10 deletions(-) create mode 100644 gcc/config/arm/arm_mve_builtins.def create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06c7db0..21afda7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,52 @@ +2020-03-16 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm-builtins.c (CF): Define mve_builtin_data. + (VAR1): Define. + (ARM_BUILTIN_MVE_PATTERN_START): Define. + (arm_init_mve_builtins): Define function. + (arm_init_builtins): Add TARGET_HAVE_MVE check. + (arm_expand_builtin_1): Check the range of fcode. + (arm_expand_mve_builtin): Define function to expand MVE builtins. + (arm_expand_builtin): Check the range of fcode. + * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point + types. + (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. + (vst4q_s8): Define macro. + (vst4q_s16): Likewise. + (vst4q_s32): Likewise. + (vst4q_u8): Likewise. + (vst4q_u16): Likewise. + (vst4q_u32): Likewise. + (vst4q_f16): Likewise. + (vst4q_f32): Likewise. + (__arm_vst4q_s8): Define inline builtin. + (__arm_vst4q_s16): Likewise. + (__arm_vst4q_s32): Likewise. + (__arm_vst4q_u8): Likewise. + (__arm_vst4q_u16): Likewise. + (__arm_vst4q_u32): Likewise. + (__arm_vst4q_f16): Likewise. + (__arm_vst4q_f32): Likewise. + (__ARM_mve_typeid): Define macro with MVE types. + (__ARM_mve_coerce): Define macro with _Generic feature. + (vst4q): Define polymorphic variant for different vst4q builtins. + * config/arm/arm_mve_builtins.def: New file. + * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI + modes in MVE. + * config/arm/mve.md (MVE_VLD_ST): Define iterator. + (unspec): Define unspec. + (mve_vst4q): Define RTL pattern. + * config/arm/neon.md (mov): Modify expand to allow XI and OI + modes in MVE. + (neon_mov): Modify RTL define_insn to allow XI and OI modes + in MVE. + (define_split): Allow OI mode split for MVE after reload. + (define_split): Allow XI mode split for MVE after reload. + * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. + (arm-builtins.o): Likewise. + 2020-03-17 Christophe Lyon * c-typeck.c (process_init_element): Handle constructor_type with diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 1a9a38d..2f1b125 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -432,6 +432,13 @@ static arm_builtin_datum neon_builtin_data[] = }; #undef CF +#define CF(N,X) CODE_FOR_mve_##N##X +static arm_builtin_datum mve_builtin_data[] = +{ +#include "arm_mve_builtins.def" +}; + +#undef CF #undef VAR1 #define VAR1(T, N, A) \ {#N, UP (A), CODE_FOR_arm_##N, 0, T##_QUALIFIERS}, @@ -736,6 +743,13 @@ enum arm_builtins #include "arm_acle_builtins.def" + ARM_BUILTIN_MVE_BASE, + +#undef VAR1 +#define VAR1(T, N, X) \ + ARM_BUILTIN_MVE_##N##X, +#include "arm_mve_builtins.def" + ARM_BUILTIN_MAX }; @@ -745,6 +759,9 @@ enum arm_builtins #define ARM_BUILTIN_NEON_PATTERN_START \ (ARM_BUILTIN_NEON_BASE + 1) +#define ARM_BUILTIN_MVE_PATTERN_START \ + (ARM_BUILTIN_MVE_BASE + 1) + #define ARM_BUILTIN_ACLE_PATTERN_START \ (ARM_BUILTIN_ACLE_BASE + 1) @@ -1278,6 +1295,22 @@ arm_init_acle_builtins (void) } } +/* Set up all the MVE builtins mentioned in arm_mve_builtins.def file. */ +static void +arm_init_mve_builtins (void) +{ + volatile unsigned int i, fcode = ARM_BUILTIN_MVE_PATTERN_START; + + arm_init_simd_builtin_scalar_types (); + arm_init_simd_builtin_types (); + + for (i = 0; i < ARRAY_SIZE (mve_builtin_data); i++, fcode++) + { + arm_builtin_datum *d = &mve_builtin_data[i]; + arm_init_builtin (fcode, d, "__builtin_mve"); + } +} + /* Set up all the NEON builtins, even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line @@ -2022,8 +2055,10 @@ arm_init_builtins (void) = add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr, ARM_BUILTIN_SIMD_LANE_CHECK, BUILT_IN_MD, NULL, NULL_TREE); - - arm_init_neon_builtins (); + if (TARGET_HAVE_MVE) + arm_init_mve_builtins (); + else + arm_init_neon_builtins (); arm_init_vfp_builtins (); arm_init_crypto_builtins (); } @@ -2567,10 +2602,14 @@ arm_expand_builtin_1 (int fcode, tree exp, rtx target, int is_void = 0; int k; bool neon = false; + bool mve = false; if (IN_RANGE (fcode, ARM_BUILTIN_VFP_BASE, ARM_BUILTIN_ACLE_BASE - 1)) neon = true; + if (IN_RANGE (fcode, ARM_BUILTIN_MVE_BASE, ARM_BUILTIN_MAX - 1)) + mve = true; + is_void = !!(d->qualifiers[0] & qualifier_void); num_args += is_void; @@ -2612,7 +2651,7 @@ arm_expand_builtin_1 (int fcode, tree exp, rtx target, } else if (d->qualifiers[qualifiers_k] & qualifier_pointer) { - if (neon) + if (neon || mve) args[k] = ARG_BUILTIN_NEON_MEMORY; else args[k] = ARG_BUILTIN_MEMORY; @@ -2662,6 +2701,26 @@ arm_expand_acle_builtin (int fcode, tree exp, rtx target) return arm_expand_builtin_1 (fcode, exp, target, d); } +/* Expand an MVE builtin, i.e. those registered only if their respective target + constraints are met. This check happens within arm_expand_builtin. */ + +static rtx +arm_expand_mve_builtin (int fcode, tree exp, rtx target) +{ + if (fcode >= ARM_BUILTIN_MVE_BASE && !TARGET_HAVE_MVE) + { + fatal_error (input_location, + "You must enable MVE instructions" + " to use these intrinsics"); + return const0_rtx; + } + + arm_builtin_datum *d + = &mve_builtin_data[fcode - ARM_BUILTIN_MVE_PATTERN_START]; + + return arm_expand_builtin_1 (fcode, exp, target, d); +} + /* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds. Most of these are "special" because they don't have symbolic constants defined per-instruction or per instruction-variant. Instead, the @@ -2755,6 +2814,8 @@ arm_expand_builtin (tree exp, /* Don't generate any RTL. */ return const0_rtx; } + if (fcode >= ARM_BUILTIN_MVE_BASE) + return arm_expand_mve_builtin (fcode, exp, target); if (fcode >= ARM_BUILTIN_ACLE_BASE) return arm_expand_acle_builtin (fcode, exp, target); diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 7347d46..807a0d2 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -42,6 +42,13 @@ typedef __simd128_float16_t float16x8_t; typedef __simd128_float32_t float32x4_t; #endif +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +typedef struct { float16x8_t val[2]; } float16x8x2_t; +typedef struct { float16x8_t val[4]; } float16x8x4_t; +typedef struct { float32x4_t val[2]; } float32x4x2_t; +typedef struct { float32x4_t val[4]; } float32x4x4_t; +#endif + typedef uint16_t mve_pred16_t; typedef __simd128_uint8_t uint8x16_t; typedef __simd128_uint16_t uint16x8_t; @@ -52,6 +59,330 @@ typedef __simd128_int16_t int16x8_t; typedef __simd128_int32_t int32x4_t; typedef __simd128_int64_t int64x2_t; +typedef struct { int16x8_t val[2]; } int16x8x2_t; +typedef struct { int16x8_t val[4]; } int16x8x4_t; +typedef struct { int32x4_t val[2]; } int32x4x2_t; +typedef struct { int32x4_t val[4]; } int32x4x4_t; +typedef struct { int8x16_t val[2]; } int8x16x2_t; +typedef struct { int8x16_t val[4]; } int8x16x4_t; +typedef struct { uint16x8_t val[2]; } uint16x8x2_t; +typedef struct { uint16x8_t val[4]; } uint16x8x4_t; +typedef struct { uint32x4_t val[2]; } uint32x4x2_t; +typedef struct { uint32x4_t val[4]; } uint32x4x4_t; +typedef struct { uint8x16_t val[2]; } uint8x16x2_t; +typedef struct { uint8x16_t val[4]; } uint8x16x4_t; + +#ifndef __ARM_MVE_PRESERVE_USER_NAMESPACE +#define vst4q_s8( __addr, __value) __arm_vst4q_s8( __addr, __value) +#define vst4q_s16( __addr, __value) __arm_vst4q_s16( __addr, __value) +#define vst4q_s32( __addr, __value) __arm_vst4q_s32( __addr, __value) +#define vst4q_u8( __addr, __value) __arm_vst4q_u8( __addr, __value) +#define vst4q_u16( __addr, __value) __arm_vst4q_u16( __addr, __value) +#define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) +#define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) +#define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s8 (int8_t * __addr, int8x16x4_t __value) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s16 (int16_t * __addr, int16x8x4_t __value) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s32 (int32_t * __addr, int32x4x4_t __value) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u8 (uint8_t * __addr, uint8x16x4_t __value) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u16 (uint16_t * __addr, uint16x8x4_t __value) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4sf (__addr, __rv.__o); +} + +#endif + +enum { + __ARM_mve_type_float16_t = 1, + __ARM_mve_type_float16_t_ptr, + __ARM_mve_type_float16_t_const_ptr, + __ARM_mve_type_float16x8_t, + __ARM_mve_type_float16x8x2_t, + __ARM_mve_type_float16x8x4_t, + __ARM_mve_type_float32_t, + __ARM_mve_type_float32_t_ptr, + __ARM_mve_type_float32_t_const_ptr, + __ARM_mve_type_float32x4_t, + __ARM_mve_type_float32x4x2_t, + __ARM_mve_type_float32x4x4_t, + __ARM_mve_type_int16_t, + __ARM_mve_type_int16_t_ptr, + __ARM_mve_type_int16_t_const_ptr, + __ARM_mve_type_int16x8_t, + __ARM_mve_type_int16x8x2_t, + __ARM_mve_type_int16x8x4_t, + __ARM_mve_type_int32_t, + __ARM_mve_type_int32_t_ptr, + __ARM_mve_type_int32_t_const_ptr, + __ARM_mve_type_int32x4_t, + __ARM_mve_type_int32x4x2_t, + __ARM_mve_type_int32x4x4_t, + __ARM_mve_type_int64_t, + __ARM_mve_type_int64_t_ptr, + __ARM_mve_type_int64_t_const_ptr, + __ARM_mve_type_int64x2_t, + __ARM_mve_type_int8_t, + __ARM_mve_type_int8_t_ptr, + __ARM_mve_type_int8_t_const_ptr, + __ARM_mve_type_int8x16_t, + __ARM_mve_type_int8x16x2_t, + __ARM_mve_type_int8x16x4_t, + __ARM_mve_type_uint16_t, + __ARM_mve_type_uint16_t_ptr, + __ARM_mve_type_uint16_t_const_ptr, + __ARM_mve_type_uint16x8_t, + __ARM_mve_type_uint16x8x2_t, + __ARM_mve_type_uint16x8x4_t, + __ARM_mve_type_uint32_t, + __ARM_mve_type_uint32_t_ptr, + __ARM_mve_type_uint32_t_const_ptr, + __ARM_mve_type_uint32x4_t, + __ARM_mve_type_uint32x4x2_t, + __ARM_mve_type_uint32x4x4_t, + __ARM_mve_type_uint64_t, + __ARM_mve_type_uint64_t_ptr, + __ARM_mve_type_uint64_t_const_ptr, + __ARM_mve_type_uint64x2_t, + __ARM_mve_type_uint8_t, + __ARM_mve_type_uint8_t_ptr, + __ARM_mve_type_uint8_t_const_ptr, + __ARM_mve_type_uint8x16_t, + __ARM_mve_type_uint8x16x2_t, + __ARM_mve_type_uint8x16x4_t, + __ARM_mve_unsupported_type +}; + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define __ARM_mve_typeid(x) _Generic(x, \ + float16_t: __ARM_mve_type_float16_t, \ + float16_t *: __ARM_mve_type_float16_t_ptr, \ + float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ + float16x8_t: __ARM_mve_type_float16x8_t, \ + float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ + float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ + float32_t: __ARM_mve_type_float32_t, \ + float32_t *: __ARM_mve_type_float32_t_ptr, \ + float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ + float32x4_t: __ARM_mve_type_float32x4_t, \ + float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ + float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#else +#define __ARM_mve_typeid(x) _Generic(x, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#endif /* MVE Floating point. */ + +extern void *__ARM_undef; +#define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + +#else /* MVE Interger. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) + +#endif /* MVE Floating point. */ + #ifdef __cplusplus } #endif diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def new file mode 100644 index 0000000..4a7e4d0 --- /dev/null +++ b/gcc/config/arm/arm_mve_builtins.def @@ -0,0 +1,21 @@ +/* MVE builtin definitions for Arm. + Copyright (C) 2019-2020 Free Software Foundation, Inc. + Contributed by Arm. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6af7658..5c1a11b 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -131,7 +131,8 @@ (define_mode_iterator VQXMOV [V16QI V8HI V8HF V8BF V4SI V4SF V2DI TI]) ;; Opaque structure types wider than TImode. -(define_mode_iterator VSTRUCT [EI OI CI XI]) +(define_mode_iterator VSTRUCT [(EI "!TARGET_HAVE_MVE") OI + (CI "!TARGET_HAVE_MVE") XI]) ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). (define_mode_iterator VTAB [TI EI OI]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index c32adf1..b41deb0 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -17,9 +17,12 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32") (V2DI "u64")]) +(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) +(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) + +(define_c_enum "unspec" [VST4Q]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -83,3 +86,37 @@ } [(set_attr "length" "4,4") (set_attr "type" "mve_move,mve_move")]) + +;; +;; [vst4q]) +;; +(define_insn "mve_vst4q" + [(set (match_operand:XI 0 "neon_struct_operand" "=Um") + (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VST4Q)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[6]; + int regno = REGNO (operands[1]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = gen_rtx_REG (TImode, regno+4); + ops[2] = gen_rtx_REG (TImode, regno+8); + ops[3] = gen_rtx_REG (TImode, regno+12); + rtx reg = operands[0]; + while (reg && !REG_P (reg)) + reg = XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[4] = reg; + ops[5] = operands[0]; + /* Here in first three instructions data is stored to ops[4]'s location but + in the fourth instruction data is stored to operands[0], this is to + support the writeback. */ + output_asm_insn ("vst40.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst41.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst42.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst43.\t{%q0, %q1, %q2, %q3}, %5", ops); + return ""; +} + [(set_attr "length" "16")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index b6a8eb6..fbfeef2 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -149,7 +149,7 @@ (define_expand "mov" [(set (match_operand:VSTRUCT 0 "nonimmediate_operand") (match_operand:VSTRUCT 1 "general_operand"))] - "TARGET_NEON" + "TARGET_NEON || TARGET_HAVE_MVE" { gcc_checking_assert (aligned_operand (operands[0], mode)); gcc_checking_assert (aligned_operand (operands[1], mode)); @@ -181,7 +181,7 @@ (define_insn "*neon_mov" [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w") (match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))] - "TARGET_NEON + "(TARGET_NEON || TARGET_HAVE_MVE) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" { @@ -217,7 +217,7 @@ (define_split [(set (match_operand:OI 0 "s_register_operand" "") (match_operand:OI 1 "s_register_operand" ""))] - "TARGET_NEON && reload_completed" + "(TARGET_NEON || TARGET_HAVE_MVE)&& reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3))] { @@ -258,7 +258,7 @@ (define_split [(set (match_operand:XI 0 "s_register_operand" "") (match_operand:XI 1 "s_register_operand" ""))] - "TARGET_NEON && reload_completed" + "(TARGET_NEON || TARGET_HAVE_MVE) && reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5)) diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 2d98083..1f7f169 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -137,7 +137,8 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ arm-cpu-data.h \ $(srcdir)/config/arm/arm-protos.h \ $(srcdir)/config/arm/arm_neon_builtins.def \ - $(srcdir)/config/arm/arm_vfp_builtins.def + $(srcdir)/config/arm/arm_vfp_builtins.def \ + $(srcdir)/config/arm/arm_mve_builtins.def arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \ $(SYSTEM_H) coretypes.h $(TM_H) \ @@ -147,6 +148,7 @@ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \ $(srcdir)/config/arm/arm_acle_builtins.def \ $(srcdir)/config/arm/arm_neon_builtins.def \ $(srcdir)/config/arm/arm_vfp_builtins.def \ + $(srcdir)/config/arm/arm_mve_builtins.def \ $(srcdir)/config/arm/arm-simd-builtin-types.def $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/arm/arm-builtins.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cb81b72..2427201 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2020-03-16 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vst4q_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. + 2020-03-17 Jakub Jelinek PR target/94185 diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c new file mode 100644 index 0000000..8516cfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8x4_t value) +{ + vst4q_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (float16_t * addr, float16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (float16_t * addr, float16x8x4_t value) +{ + vst4q_f16 (addr, value); + addr += 32; + vst4q_f16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c new file mode 100644 index 0000000..c8b3272 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4x4_t value) +{ + vst4q_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (float32_t * addr, float32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (float32_t * addr, float32x4x4_t value) +{ + vst4q_f32 (addr, value); + addr += 16; + vst4q_f32 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c new file mode 100644 index 0000000..d06947d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8x4_t value) +{ + vst4q_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (int16_t * addr, int16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (int16_t * addr, int16x8x4_t value) +{ + vst4q_s16 (addr, value); + addr += 32; + vst4q_s16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c new file mode 100644 index 0000000..5dc6835 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4x4_t value) +{ + vst4q_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (int32_t * addr, int32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (int32_t * addr, int32x4x4_t value) +{ + vst4q_s32 (addr, value); + addr += 16; + vst4q_s32 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c new file mode 100644 index 0000000..a3cb53e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16x4_t value) +{ + vst4q_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo1 (int8_t * addr, int8x16x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo2 (int8_t * addr, int8x16x4_t value) +{ + vst4q_s8 (addr, value); + addr += 16*4; + vst4q_s8 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c new file mode 100644 index 0000000..87dd4bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8x4_t value) +{ + vst4q_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (uint16_t * addr, uint16x8x4_t value) +{ + vst4q_u16 (addr, value); + addr += 32; + vst4q_u16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c new file mode 100644 index 0000000..943aa02 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4x4_t value) +{ + vst4q_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (uint32_t * addr, uint32x4x4_t value) +{ + vst4q_u32 (addr, value); + addr += 16; + vst4q_u32 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c new file mode 100644 index 0000000..c8dcc97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16x4_t value) +{ + vst4q_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo2 (uint8_t * addr, uint8x16x4_t value) +{ + vst4q_u8 (addr, value); + addr += 16*4; + vst4q_u8 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ -- cgit v1.1 From a50f6abffc3353fa4f246cb18d6d04978d60abad Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 11:50:54 +0000 Subject: [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand. This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. (UNOP_NONE_SNONE_QUALIFIERS): Likewise. (UNOP_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vrndxq_f16): Define macro. (vrndxq_f32): Likewise. (vrndq_f16) Likewise. (vrndq_f32): Likewise. (vrndpq_f16): Likewise. (vrndpq_f32): Likewise. (vrndnq_f16): Likewise. (vrndnq_f32): Likewise. (vrndmq_f16): Likewise. (vrndmq_f32): Likewise. (vrndaq_f16): Likewise. (vrndaq_f32): Likewise. (vrev64q_f16): Likewise. (vrev64q_f32): Likewise. (vnegq_f16): Likewise. (vnegq_f32): Likewise. (vdupq_n_f16): Likewise. (vdupq_n_f32): Likewise. (vabsq_f16): Likewise. (vabsq_f32): Likewise. (vrev32q_f16): Likewise. (vcvttq_f32_f16): Likewise. (vcvtbq_f32_f16): Likewise. (vcvtq_f16_s16): Likewise. (vcvtq_f32_s32): Likewise. (vcvtq_f16_u16): Likewise. (vcvtq_f32_u32): Likewise. (__arm_vrndxq_f16): Define intrinsic. (__arm_vrndxq_f32): Likewise. (__arm_vrndq_f16): Likewise. (__arm_vrndq_f32): Likewise. (__arm_vrndpq_f16): Likewise. (__arm_vrndpq_f32): Likewise. (__arm_vrndnq_f16): Likewise. (__arm_vrndnq_f32): Likewise. (__arm_vrndmq_f16): Likewise. (__arm_vrndmq_f32): Likewise. (__arm_vrndaq_f16): Likewise. (__arm_vrndaq_f32): Likewise. (__arm_vrev64q_f16): Likewise. (__arm_vrev64q_f32): Likewise. (__arm_vnegq_f16): Likewise. (__arm_vnegq_f32): Likewise. (__arm_vdupq_n_f16): Likewise. (__arm_vdupq_n_f32): Likewise. (__arm_vabsq_f16): Likewise. (__arm_vabsq_f32): Likewise. (__arm_vrev32q_f16): Likewise. (__arm_vcvttq_f32_f16): Likewise. (__arm_vcvtbq_f32_f16): Likewise. (__arm_vcvtq_f16_s16): Likewise. (__arm_vcvtq_f32_s32): Likewise. (__arm_vcvtq_f16_u16): Likewise. (__arm_vcvtq_f32_u32): Likewise. (vrndxq): Define polymorphic variants. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. * config/arm/arm_mve_builtins.def (VAR2): Define. (VAR1): Define. * config/arm/mve.md (mve_vrndxq_f): Add RTL pattern. (mve_vrndq_f): Likewise. (mve_vrndpq_f): Likewise. (mve_vrndnq_f): Likewise. (mve_vrndmq_f): Likewise. (mve_vrndaq_f): Likewise. (mve_vrev64q_f): Likewise. (mve_vnegq_f): Likewise. (mve_vdupq_n_f): Likewise. (mve_vabsq_f): Likewise. (mve_vrev32q_fv8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtq_to_f_): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. --- gcc/ChangeLog | 91 +++++++ gcc/config/arm/arm-builtins.c | 22 ++ gcc/config/arm/arm_mve.h | 293 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 15 ++ gcc/config/arm/mve.md | 207 ++++++++++++++- gcc/testsuite/ChangeLog | 32 +++ .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 14 + 33 files changed, 1037 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 21afda7..65b3645 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,94 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. + (UNOP_NONE_SNONE_QUALIFIERS): Likewise. + (UNOP_NONE_UNONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vrndxq_f16): Define macro. + (vrndxq_f32): Likewise. + (vrndq_f16) Likewise. + (vrndq_f32): Likewise. + (vrndpq_f16): Likewise. + (vrndpq_f32): Likewise. + (vrndnq_f16): Likewise. + (vrndnq_f32): Likewise. + (vrndmq_f16): Likewise. + (vrndmq_f32): Likewise. + (vrndaq_f16): Likewise. + (vrndaq_f32): Likewise. + (vrev64q_f16): Likewise. + (vrev64q_f32): Likewise. + (vnegq_f16): Likewise. + (vnegq_f32): Likewise. + (vdupq_n_f16): Likewise. + (vdupq_n_f32): Likewise. + (vabsq_f16): Likewise. + (vabsq_f32): Likewise. + (vrev32q_f16): Likewise. + (vcvttq_f32_f16): Likewise. + (vcvtbq_f32_f16): Likewise. + (vcvtq_f16_s16): Likewise. + (vcvtq_f32_s32): Likewise. + (vcvtq_f16_u16): Likewise. + (vcvtq_f32_u32): Likewise. + (__arm_vrndxq_f16): Define intrinsic. + (__arm_vrndxq_f32): Likewise. + (__arm_vrndq_f16): Likewise. + (__arm_vrndq_f32): Likewise. + (__arm_vrndpq_f16): Likewise. + (__arm_vrndpq_f32): Likewise. + (__arm_vrndnq_f16): Likewise. + (__arm_vrndnq_f32): Likewise. + (__arm_vrndmq_f16): Likewise. + (__arm_vrndmq_f32): Likewise. + (__arm_vrndaq_f16): Likewise. + (__arm_vrndaq_f32): Likewise. + (__arm_vrev64q_f16): Likewise. + (__arm_vrev64q_f32): Likewise. + (__arm_vnegq_f16): Likewise. + (__arm_vnegq_f32): Likewise. + (__arm_vdupq_n_f16): Likewise. + (__arm_vdupq_n_f32): Likewise. + (__arm_vabsq_f16): Likewise. + (__arm_vabsq_f32): Likewise. + (__arm_vrev32q_f16): Likewise. + (__arm_vcvttq_f32_f16): Likewise. + (__arm_vcvtbq_f32_f16): Likewise. + (__arm_vcvtq_f16_s16): Likewise. + (__arm_vcvtq_f32_s32): Likewise. + (__arm_vcvtq_f16_u16): Likewise. + (__arm_vcvtq_f32_u32): Likewise. + (vrndxq): Define polymorphic variants. + (vrndq): Likewise. + (vrndpq): Likewise. + (vrndnq): Likewise. + (vrndmq): Likewise. + (vrndaq): Likewise. + (vrev64q): Likewise. + (vnegq): Likewise. + (vabsq): Likewise. + (vrev32q): Likewise. + (vcvtbq_f32): Likewise. + (vcvttq_f32): Likewise. + (vcvtq): Likewise. + * config/arm/arm_mve_builtins.def (VAR2): Define. + (VAR1): Define. + * config/arm/mve.md (mve_vrndxq_f): Add RTL pattern. + (mve_vrndq_f): Likewise. + (mve_vrndpq_f): Likewise. + (mve_vrndnq_f): Likewise. + (mve_vrndmq_f): Likewise. + (mve_vrndaq_f): Likewise. + (mve_vrev64q_f): Likewise. + (mve_vnegq_f): Likewise. + (mve_vdupq_n_f): Likewise. + (mve_vabsq_f): Likewise. + (mve_vrev32q_fv8hf): Likewise. + (mve_vcvttq_f32_f16v4sf): Likewise. + (mve_vcvtbq_f32_f16v4sf): Likewise. + (mve_vcvtq_to_f_): Likewise. + 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 2f1b125..38bf82c 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers) +/* Qualifiers for MVE builtins. */ + +static enum arm_type_qualifiers +arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_NONE_QUALIFIERS \ + (arm_unop_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_SNONE_QUALIFIERS \ + (arm_unop_none_snone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned }; +#define UNOP_NONE_UNONE_QUALIFIERS \ + (arm_unop_none_unone_qualifiers) + +/* End of Qualifier for MVE builtins. */ + /* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 807a0d2..e256c1e 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) +#define vrndxq_f32(__a) __arm_vrndxq_f32(__a) +#define vrndq_f16(__a) __arm_vrndq_f16(__a) +#define vrndq_f32(__a) __arm_vrndq_f32(__a) +#define vrndpq_f16(__a) __arm_vrndpq_f16(__a) +#define vrndpq_f32(__a) __arm_vrndpq_f32(__a) +#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) +#define vrndnq_f32(__a) __arm_vrndnq_f32(__a) +#define vrndmq_f16(__a) __arm_vrndmq_f16(__a) +#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) +#define vrndaq_f16(__a) __arm_vrndaq_f16(__a) +#define vrndaq_f32(__a) __arm_vrndaq_f32(__a) +#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) +#define vrev64q_f32(__a) __arm_vrev64q_f32(__a) +#define vnegq_f16(__a) __arm_vnegq_f16(__a) +#define vnegq_f32(__a) __arm_vnegq_f32(__a) +#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) +#define vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) +#define vabsq_f16(__a) __arm_vabsq_f16(__a) +#define vabsq_f32(__a) __arm_vabsq_f32(__a) +#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) +#define vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) +#define vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) +#define vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) +#define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) +#define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) +#define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) #endif __extension__ extern __inline void @@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) __builtin_mve_vst4qv4sf (__addr, __rv.__o); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndxq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndpq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndpq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndnq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndnq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndmq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndmq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndaq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndaq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev64q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f32 (float32x4_t __a) +{ + return __builtin_mve_vrev64q_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f16 (float16x8_t __a) +{ + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + #endif enum { @@ -368,6 +584,83 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 4a7e4d0..78fe7c4e 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -19,3 +19,18 @@ . */ VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b41deb0..9f2c7f4 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -21,8 +21,18 @@ (V2DI "u64")]) (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) +(define_mode_iterator MVE_0 [V8HF V4SF]) -(define_c_enum "unspec" [VST4Q]) +(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F + VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S + VCVTQ_TO_F_U]) + +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") + (V8HF "V8HI") (V4SF "V4SI")]) + +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")]) +(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@ return ""; } [(set_attr "length" "16")]) + +;; +;; [vrndxq_f]) +;; +(define_insn "mve_vrndxq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDXQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintx.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndq_f]) +;; +(define_insn "mve_vrndq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintz.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndpq_f]) +;; +(define_insn "mve_vrndpq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDPQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintp.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndnq_f]) +;; +(define_insn "mve_vrndnq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDNQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintn.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndmq_f]) +;; +(define_insn "mve_vrndmq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintm.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndaq_f]) +;; +(define_insn "mve_vrndaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrinta.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev64q_f]) +;; +(define_insn "mve_vrev64q_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev64.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_f]) +;; +(define_insn "mve_vnegq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VNEGQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vneg.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_f]) +;; +(define_insn "mve_vdupq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "r")] + VDUPQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vdup.%# %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_f]) +;; +(define_insn "mve_vabsq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VABSQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vabs.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_f]) +;; +(define_insn "mve_vrev32q_fv8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev32.16 %q0, %q1" + [(set_attr "type" "mve_move") +]) +;; +;; [vcvttq_f32_f16]) +;; +(define_insn "mve_vcvttq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtt.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtbq_f32_f16]) +;; +(define_insn "mve_vcvtbq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtb.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_to_f_s, vcvtq_to_f_u]) +;; +(define_insn "mve_vcvtq_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w")] + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.f%#.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2427201..6b836c1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,35 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. + 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c new file mode 100644 index 0000000..f49807c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vabsq_f16 (a); +} + +/* { dg-final { scan-assembler "vabs.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c new file mode 100644 index 0000000..ab44b31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vabsq_f32 (a); +} + +/* { dg-final { scan-assembler "vabs.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c new file mode 100644 index 0000000..bc57f26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvtbq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c new file mode 100644 index 0000000..9a7d9c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a) +{ + return vcvtq_f16_s16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c new file mode 100644 index 0000000..6aae968 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a) +{ + return vcvtq_f16_u16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c new file mode 100644 index 0000000..b563fe9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a) +{ + return vcvtq_f32_s32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c new file mode 100644 index 0000000..f5354a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a) +{ + return vcvtq_f32_u32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c new file mode 100644 index 0000000..2c0f4fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvttq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c new file mode 100644 index 0000000..616c24f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t a) +{ + return vdupq_n_f16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c new file mode 100644 index 0000000..570dfde --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t a) +{ + return vdupq_n_f32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c new file mode 100644 index 0000000..89d0162 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vnegq_f16 (a); +} + +/* { dg-final { scan-assembler "vneg.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c new file mode 100644 index 0000000..8cbdd16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vnegq_f32 (a); +} + +/* { dg-final { scan-assembler "vneg.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c new file mode 100644 index 0000000..86bf47d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev32q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c new file mode 100644 index 0000000..d7f75fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev64q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c new file mode 100644 index 0000000..131ec46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrev64q_f32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c new file mode 100644 index 0000000..d647d31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndaq_f16 (a); +} + +/* { dg-final { scan-assembler "vrinta.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c new file mode 100644 index 0000000..4d5ba50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndaq_f32 (a); +} + +/* { dg-final { scan-assembler "vrinta.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c new file mode 100644 index 0000000..996b0b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndmq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c new file mode 100644 index 0000000..fae0a5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndmq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c new file mode 100644 index 0000000..cc00b6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndnq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintn.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c new file mode 100644 index 0000000..150e9d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndnq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintn.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c new file mode 100644 index 0000000..d75ea35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndpq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c new file mode 100644 index 0000000..45de7fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndpq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c new file mode 100644 index 0000000..b3a9654 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintz.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c new file mode 100644 index 0000000..c8a723a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintz.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c new file mode 100644 index 0000000..aa364f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndxq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintx.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c new file mode 100644 index 0000000..99a7581 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndxq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintx.f32" } } */ -- cgit v1.1 From 5db0eb95c341d03d27b6893b22230ec8d4cb92e0 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 12:03:30 +0000 Subject: [ARM][GCC][2/1x]: MVE intrinsics with unary operand. This patch supports following MVE ACLE intrinsics with unary operand. vmvnq_n_s16, vmvnq_n_s32, vrev64q_s8, vrev64q_s16, vrev64q_s32, vcvtq_s16_f16, vcvtq_s32_f32, vrev64q_u8, vrev64q_u16, vrev64q_u32, vmvnq_n_u16, vmvnq_n_u32, vcvtq_u16_f16, vcvtq_u32_f32, vrev64q. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define. (UNOP_SNONE_NONE_QUALIFIERS): Likewise. (UNOP_SNONE_IMM_QUALIFIERS): Likewise. (UNOP_UNONE_NONE_QUALIFIERS): Likewise. (UNOP_UNONE_UNONE_QUALIFIERS): Likewise. (UNOP_UNONE_IMM_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vmvnq_n_s16): Define macro. (vmvnq_n_s32): Likewise. (vrev64q_s8): Likewise. (vrev64q_s16): Likewise. (vrev64q_s32): Likewise. (vcvtq_s16_f16): Likewise. (vcvtq_s32_f32): Likewise. (vrev64q_u8): Likewise. (vrev64q_u16): Likewise. (vrev64q_u32): Likewise. (vmvnq_n_u16): Likewise. (vmvnq_n_u32): Likewise. (vcvtq_u16_f16): Likewise. (vcvtq_u32_f32): Likewise. (__arm_vmvnq_n_s16): Define intrinsic. (__arm_vmvnq_n_s32): Likewise. (__arm_vrev64q_s8): Likewise. (__arm_vrev64q_s16): Likewise. (__arm_vrev64q_s32): Likewise. (__arm_vrev64q_u8): Likewise. (__arm_vrev64q_u16): Likewise. (__arm_vrev64q_u32): Likewise. (__arm_vmvnq_n_u16): Likewise. (__arm_vmvnq_n_u32): Likewise. (__arm_vcvtq_s16_f16): Likewise. (__arm_vcvtq_s32_f32): Likewise. (__arm_vcvtq_u16_f16): Likewise. (__arm_vcvtq_u32_f32): Likewise. (vrev64q): Define polymorphic variant. * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. (UNOP_SNONE_NONE): Likewise. (UNOP_SNONE_IMM): Likewise. (UNOP_UNONE_UNONE): Likewise. (UNOP_UNONE_NONE): Likewise. (UNOP_UNONE_IMM): Likewise. * config/arm/mve.md (mve_vrev64q_): Define RTL pattern. (mve_vcvtq_from_f_): Likewise. (mve_vmvnq_n_): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: New test. * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise. --- gcc/ChangeLog | 49 +++++++++ gcc/config/arm/arm-builtins.c | 36 ++++++ gcc/config/arm/arm_mve.h | 122 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 6 + gcc/config/arm/mve.md | 55 +++++++++- gcc/testsuite/ChangeLog | 19 ++++ .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 22 ++++ 20 files changed, 529 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 65b3645..ec3d190 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,55 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define. + (UNOP_SNONE_NONE_QUALIFIERS): Likewise. + (UNOP_SNONE_IMM_QUALIFIERS): Likewise. + (UNOP_UNONE_NONE_QUALIFIERS): Likewise. + (UNOP_UNONE_UNONE_QUALIFIERS): Likewise. + (UNOP_UNONE_IMM_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vmvnq_n_s16): Define macro. + (vmvnq_n_s32): Likewise. + (vrev64q_s8): Likewise. + (vrev64q_s16): Likewise. + (vrev64q_s32): Likewise. + (vcvtq_s16_f16): Likewise. + (vcvtq_s32_f32): Likewise. + (vrev64q_u8): Likewise. + (vrev64q_u16): Likewise. + (vrev64q_u32): Likewise. + (vmvnq_n_u16): Likewise. + (vmvnq_n_u32): Likewise. + (vcvtq_u16_f16): Likewise. + (vcvtq_u32_f32): Likewise. + (__arm_vmvnq_n_s16): Define intrinsic. + (__arm_vmvnq_n_s32): Likewise. + (__arm_vrev64q_s8): Likewise. + (__arm_vrev64q_s16): Likewise. + (__arm_vrev64q_s32): Likewise. + (__arm_vrev64q_u8): Likewise. + (__arm_vrev64q_u16): Likewise. + (__arm_vrev64q_u32): Likewise. + (__arm_vmvnq_n_u16): Likewise. + (__arm_vmvnq_n_u32): Likewise. + (__arm_vcvtq_s16_f16): Likewise. + (__arm_vcvtq_s32_f32): Likewise. + (__arm_vcvtq_u16_f16): Likewise. + (__arm_vcvtq_u32_f32): Likewise. + (vrev64q): Define polymorphic variant. + * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. + (UNOP_SNONE_NONE): Likewise. + (UNOP_SNONE_IMM): Likewise. + (UNOP_UNONE_UNONE): Likewise. + (UNOP_UNONE_NONE): Likewise. + (UNOP_UNONE_IMM): Likewise. + * config/arm/mve.md (mve_vrev64q_): Define RTL pattern. + (mve_vcvtq_from_f_): Likewise. + (mve_vmvnq_n_): Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. (UNOP_NONE_SNONE_QUALIFIERS): Likewise. (UNOP_NONE_UNONE_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 38bf82c..b8656b8 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -337,6 +337,42 @@ arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define UNOP_NONE_UNONE_QUALIFIERS \ (arm_unop_none_unone_qualifiers) +static enum arm_type_qualifiers +arm_unop_snone_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_SNONE_SNONE_QUALIFIERS \ + (arm_unop_snone_snone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_snone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_SNONE_NONE_QUALIFIERS \ + (arm_unop_snone_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_snone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_immediate }; +#define UNOP_SNONE_IMM_QUALIFIERS \ + (arm_unop_snone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_unop_unone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none }; +#define UNOP_UNONE_NONE_QUALIFIERS \ + (arm_unop_unone_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned }; +#define UNOP_UNONE_UNONE_QUALIFIERS \ + (arm_unop_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_immediate }; +#define UNOP_UNONE_IMM_QUALIFIERS \ + (arm_unop_unone_imm_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index e256c1e..14dd417 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -108,6 +108,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) +#define vmvnq_n_s16( __imm) __arm_vmvnq_n_s16( __imm) +#define vmvnq_n_s32( __imm) __arm_vmvnq_n_s32( __imm) +#define vrev64q_s8(__a) __arm_vrev64q_s8(__a) +#define vrev64q_s16(__a) __arm_vrev64q_s16(__a) +#define vrev64q_s32(__a) __arm_vrev64q_s32(__a) +#define vcvtq_s16_f16(__a) __arm_vcvtq_s16_f16(__a) +#define vcvtq_s32_f32(__a) __arm_vcvtq_s32_f32(__a) +#define vrev64q_u8(__a) __arm_vrev64q_u8(__a) +#define vrev64q_u16(__a) __arm_vrev64q_u16(__a) +#define vrev64q_u32(__a) __arm_vrev64q_u32(__a) +#define vmvnq_n_u16( __imm) __arm_vmvnq_n_u16( __imm) +#define vmvnq_n_u32( __imm) __arm_vmvnq_n_u32( __imm) +#define vcvtq_u16_f16(__a) __arm_vcvtq_u16_f16(__a) +#define vcvtq_u32_f32(__a) __arm_vcvtq_u32_f32(__a) #endif __extension__ extern __inline void @@ -164,6 +178,76 @@ __arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); } +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_n_s16 (const int16_t __imm) +{ + return __builtin_mve_vmvnq_n_sv8hi (__imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_n_s32 (const int32_t __imm) +{ + return __builtin_mve_vmvnq_n_sv4si (__imm); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_s8 (int8x16_t __a) +{ + return __builtin_mve_vrev64q_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_s16 (int16x8_t __a) +{ + return __builtin_mve_vrev64q_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_s32 (int32x4_t __a) +{ + return __builtin_mve_vrev64q_sv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_u8 (uint8x16_t __a) +{ + return __builtin_mve_vrev64q_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_u16 (uint16x8_t __a) +{ + return __builtin_mve_vrev64q_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_u32 (uint32x4_t __a) +{ + return __builtin_mve_vrev64q_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_n_u16 (const int __imm) +{ + return __builtin_mve_vmvnq_n_uv8hi (__imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_n_u32 (const int __imm) +{ + return __builtin_mve_vmvnq_n_uv4si (__imm); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -373,6 +457,34 @@ __arm_vcvtq_f32_u32 (uint32x4_t __a) return __builtin_mve_vcvtq_to_f_uv4sf (__a); } +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv4si (__a); +} + #endif enum { @@ -674,6 +786,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 78fe7c4e..d325f36 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -34,3 +34,9 @@ VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) +VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) +VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) +VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9f2c7f4..a58cfb2 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -22,17 +22,26 @@ (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) +(define_mode_iterator MVE_2 [V16QI V8HI V4SI]) +(define_mode_iterator MVE_5 [V8HI V4SI]) (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S - VCVTQ_TO_F_U]) + VCVTQ_TO_F_U VMVNQ_N_S VMVNQ_N_U VREV64Q_S VREV64Q_U + VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) -(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")]) +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VMVNQ_N_S "s") + (VMVNQ_N_U "u") (VREV64Q_U "u") (VREV64Q_S "s") + (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")]) + (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) +(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) +(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) +(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -325,3 +334,45 @@ "vcvt.f%#.%# %q0, %q1" [(set_attr "type" "mve_move") ]) + +;; +;; [vrev64q_u, vrev64q_s]) +;; +(define_insn "mve_vrev64q_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VREV64Q)) + ] + "TARGET_HAVE_MVE" + "vrev64.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_from_f_s, vcvtq_from_f_u]) +;; +(define_insn "mve_vcvtq_from_f_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTQ_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmvnq_n_u, vmvnq_n_s]) +;; +(define_insn "mve_vmvnq_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")] + VMVNQ_N)) + ] + "TARGET_HAVE_MVE" + "vmvn.i%# %q0, %1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6b836c1..d0d93e7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c new file mode 100644 index 0000000..c5cdd9d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c new file mode 100644 index 0000000..a0f8db2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c new file mode 100644 index 0000000..ab934ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c new file mode 100644 index 0000000..e802cac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c new file mode 100644 index 0000000..61a89bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo () +{ + return vmvnq_n_s16 (1); +} + +/* { dg-final { scan-assembler "vmvn.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c new file mode 100644 index 0000000..3700722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo () +{ + return vmvnq_n_s32 (2); +} + +/* { dg-final { scan-assembler "vmvn.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c new file mode 100644 index 0000000..b7e8734 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo () +{ + return vmvnq_n_u16 (1); +} + +/* { dg-final { scan-assembler "vmvn.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c new file mode 100644 index 0000000..235d672 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo () +{ + return vmvnq_n_u32 (2); +} + +/* { dg-final { scan-assembler "vmvn.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c new file mode 100644 index 0000000..35245ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vrev64q_s16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vrev64q_s16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c new file mode 100644 index 0000000..2344423 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vrev64q_s32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vrev64q_s32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c new file mode 100644 index 0000000..61a9725 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrev64q_s8 (a); +} + +/* { dg-final { scan-assembler "vrev64.8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrev64q (a); +} + +/* { dg-final { scan-assembler "vrev64.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c new file mode 100644 index 0000000..e42bd31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vrev64q_u16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vrev64q (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c new file mode 100644 index 0000000..af25b84 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vrev64q_u32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vrev64q (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c new file mode 100644 index 0000000..d9a194a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrev64q_u8 (a); +} + +/* { dg-final { scan-assembler "vrev64.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrev64q (a); +} + +/* { dg-final { scan-assembler "vrev64.8" } } */ -- cgit v1.1 From a9a437ffc4269650e34af92c4fb095b7ed98f94a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 13:36:41 +0100 Subject: tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] As I said already yesterday in another PR, I'm afraid the mixing of apples and oranges (what we are actually computing, whether what bytes are zero or non-zero in the native representation of EXP itself or what EXP points to) in a single function where it performs some handling which must be specific to one or the other case unconditionally and only from time to time determines something based on if nbytes is 0 or not will continue to bite us again and again. So, this patch performs at least a partial cleanup to separate those two cases into two functions. In addition to the separation, the patch uses e.g. ctor_for_folding so that it does handle volatile loads properly and various other checks instead of directly using DECL_INITIAL or does guard native_encode_expr call the way it is guarded elsewhere (that host and target byte sizes are expected). I've left other issues I found as is for now, like the *allnonnul being IMHO wrongly computed (if we don't know anything about the bytes, such as if _1 = MEM[s_2(D)]; MEM[whatever] = _1; where nothing really is known about strlen(s) etc., the code right now clears *nulterm and *allnul, but keeps *allnonnull set), but the callers seem to never use that value for anything (so the question is why is it computed and how exactly should it be defined). Another thing I find quite weird is the distinction between count_nonzero_bytes failing (return false) and when it succeeds, but sets values to a don't know state (the warning is only issued if it succeeds), plus what lenrange[2] is for. The size of the store should be visible already from the store statement. Also the looking at the type of the MEM_REF first operand to determine if it is is_char_store is really weird, because both in user code and through sccvn where pointer conversions are useless the type of the MEM_REF operand doesn't have to have anything to do with what the code actually does. 2020-03-17 Jakub Jelinek PR tree-optimization/94015 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the function where EXP is address of the bytes being stored rather than the bytes themselves into count_nonzero_bytes_addr. Punt on zero sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs. Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before calling native_encode_expr if host or target doesn't have 8-bit chars. Formatting fixes. (count_nonzero_bytes_addr): New function. * gcc.dg/pr94015.c: New test. --- gcc/ChangeLog | 12 +++ gcc/testsuite/ChangeLog | 5 + gcc/testsuite/gcc.dg/pr94015.c | 107 +++++++++++++++++++ gcc/tree-ssa-strlen.c | 234 +++++++++++++++++++++++------------------ 4 files changed, 254 insertions(+), 104 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94015.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ec3d190..c51606c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2020-03-17 Jakub Jelinek + + PR tree-optimization/94015 + * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the + function where EXP is address of the bytes being stored rather than + the bytes themselves into count_nonzero_bytes_addr. Punt on zero + sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs. + Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before + calling native_encode_expr if host or target doesn't have 8-bit + chars. Formatting fixes. + (count_nonzero_bytes_addr): New function. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d0d93e7..a389a6a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Jakub Jelinek + + PR tree-optimization/94015 + * gcc.dg/pr94015.c: New test. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.dg/pr94015.c b/gcc/testsuite/gcc.dg/pr94015.c new file mode 100644 index 0000000..2c91b23 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94015.c @@ -0,0 +1,107 @@ +/* PR tree-optimization/94015 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +char buf[10] = "AAAAAAAAA"; + +__attribute__((noipa)) char * +alloc (void) +{ + return buf; +} + +__attribute__((noipa)) void +f1 (void) +{ + char *s = alloc (); + *(char **)s = "1234567"; + s[7] = '\0'; +} + +__attribute__((noipa)) void +f2 (void) +{ + char *s = alloc (); + *(char **)s = "123456"; + s[6] = '\0'; +} + +__attribute__((noipa)) void +f3 (void) +{ + char *s = alloc (); + *(char **)s = "12345"; + s[5] = '\0'; +} + +__attribute__((noipa)) void +f4 (void) +{ + char *s = alloc (); + *(char **)s = "1234"; + s[4] = '\0'; +} + +__attribute__((noipa)) void +f5 (void) +{ + char *s = alloc (); + *(char **)s = "123"; + s[3] = '\0'; +} + +__attribute__((noipa)) void +f6 (void) +{ + char *s = alloc (); + *(char **)s = "12"; + s[2] = '\0'; +} + +__attribute__((noipa)) void +f7 (void) +{ + char *s = alloc (); + *(char **)s = "1"; + s[1] = '\0'; +} + +__attribute__((noipa)) void +f8 (void) +{ + char *s = alloc (); + *(char **)s = ""; + s[0] = '\0'; +} + +int +main () +{ + if (sizeof (char *) > 8) + return 0; + f1 (); + if (buf[7] != 0) + __builtin_abort (); + f2 (); + if (buf[6] != 0) + __builtin_abort (); + f3 (); + if (buf[5] != 0) + __builtin_abort (); + f4 (); + if (buf[4] != 0) + __builtin_abort (); + f5 (); + if (buf[3] != 0) + __builtin_abort (); + f6 (); + if (buf[2] != 0) + __builtin_abort (); + f7 (); + if (buf[1] != 0) + __builtin_abort (); + f8 (); + if (buf[0] != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index ec33d7c..7fcc610 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -4605,6 +4605,11 @@ int ssa_name_limit_t::next_ssa_name (tree ssa_name) return 0; } +static bool +count_nonzero_bytes_addr (tree, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, + unsigned [3], bool *, bool *, bool *, + const vr_values *, ssa_name_limit_t &); + /* Determines the minimum and maximum number of leading non-zero bytes in the representation of EXP and set LENRANGE[0] and LENRANGE[1] to each. @@ -4627,102 +4632,6 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, bool *allnul, bool *allnonnul, const vr_values *rvals, ssa_name_limit_t &snlim) { - int idx = get_stridx (exp); - if (idx > 0) - { - strinfo *si = get_strinfo (idx); - if (!si) - return false; - - /* Handle both constant lengths as well non-constant lengths - in some range. */ - unsigned HOST_WIDE_INT minlen, maxlen; - if (tree_fits_shwi_p (si->nonzero_chars)) - minlen = maxlen = tree_to_shwi (si->nonzero_chars); - else if (nbytes - && si->nonzero_chars - && TREE_CODE (si->nonzero_chars) == SSA_NAME) - { - const value_range_equiv *vr - = CONST_CAST (class vr_values *, rvals) - ->get_value_range (si->nonzero_chars); - if (vr->kind () != VR_RANGE - || !range_int_cst_p (vr)) - return false; - - minlen = tree_to_uhwi (vr->min ()); - maxlen = tree_to_uhwi (vr->max ()); - } - else - return false; - - if (maxlen < offset) - return false; - - minlen = minlen < offset ? 0 : minlen - offset; - maxlen -= offset; - if (maxlen + 1 < nbytes) - return false; - - if (!nbytes - && TREE_CODE (si->ptr) == SSA_NAME - && !POINTER_TYPE_P (TREE_TYPE (si->ptr))) - { - /* SI->PTR is an SSA_NAME with a DEF_STMT like - _1 = MEM [(char * {ref-all})s_4(D)]; */ - gimple *stmt = SSA_NAME_DEF_STMT (exp); - if (gimple_assign_single_p (stmt) - && gimple_assign_rhs_code (stmt) == MEM_REF) - { - tree rhs = gimple_assign_rhs1 (stmt); - if (tree refsize = TYPE_SIZE_UNIT (TREE_TYPE (rhs))) - if (tree_fits_uhwi_p (refsize)) - { - nbytes = tree_to_uhwi (refsize); - maxlen = nbytes; - } - } - - if (!nbytes) - return false; - } - - if (nbytes <= minlen) - *nulterm = false; - - if (nbytes < minlen) - { - minlen = nbytes; - if (nbytes < maxlen) - maxlen = nbytes; - } - - if (minlen < lenrange[0]) - lenrange[0] = minlen; - if (lenrange[1] < maxlen) - lenrange[1] = maxlen; - - if (lenrange[2] < nbytes) - lenrange[2] = nbytes; - - /* Since only the length of the string are known and not its contents, - clear ALLNUL and ALLNONNUL purely on the basis of the length. */ - *allnul = false; - if (minlen < nbytes) - *allnonnul = false; - - return true; - } - - if (TREE_CODE (exp) == ADDR_EXPR) - { - /* If the size of the access hasn't been determined yet it's that - of a pointer. */ - if (!nbytes) - nbytes = tree_to_uhwi (TYPE_SIZE_UNIT (TREE_TYPE (exp))); - exp = TREE_OPERAND (exp, 0); - } - if (TREE_CODE (exp) == SSA_NAME) { /* Handle non-zero single-character stores specially. */ @@ -4778,8 +4687,7 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, tree arg = TREE_OPERAND (exp, 0); tree off = TREE_OPERAND (exp, 1); - if (TREE_CODE (off) != INTEGER_CST - || !tree_fits_uhwi_p (off)) + if (TREE_CODE (off) != INTEGER_CST || !tree_fits_uhwi_p (off)) return false; unsigned HOST_WIDE_INT wioff = tree_to_uhwi (off); @@ -4796,15 +4704,17 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, if (!typesize || !tree_fits_uhwi_p (typesize)) return false; nbytes = tree_to_uhwi (typesize); + if (!nbytes) + return false; /* Handle MEM_REF = SSA_NAME types of assignments. */ - return count_nonzero_bytes (arg, offset, nbytes, lenrange, nulterm, - allnul, allnonnul, rvals, snlim); + return count_nonzero_bytes_addr (arg, offset, nbytes, lenrange, nulterm, + allnul, allnonnul, rvals, snlim); } - if (TREE_CODE (exp) == VAR_DECL && TREE_READONLY (exp)) + if (VAR_P (exp) || TREE_CODE (exp) == CONST_DECL) { - exp = DECL_INITIAL (exp); + exp = ctor_for_folding (exp); if (!exp) return false; } @@ -4831,6 +4741,8 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, unsigned char buf[256]; if (!prep) { + if (CHAR_BIT != 8 || BITS_PER_UNIT != 8) + return false; /* If the pointer to representation hasn't been set above for STRING_CST point it at the buffer. */ prep = reinterpret_cast (buf); @@ -4874,8 +4786,8 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, if (n) { /* When the initial number of non-zero bytes N is non-zero, reset - *ALLNUL; if N is less than that the size of the representation - also clear *ALLNONNUL. */ + *ALLNUL; if N is less than that the size of the representation + also clear *ALLNONNUL. */ *allnul = false; if (n < nbytes) *allnonnul = false; @@ -4901,6 +4813,120 @@ count_nonzero_bytes (tree exp, unsigned HOST_WIDE_INT offset, return true; } +/* Like count_nonzero_bytes, but instead of counting bytes in EXP, count + bytes that are pointed to by EXP, which should be a pointer. */ + +static bool +count_nonzero_bytes_addr (tree exp, unsigned HOST_WIDE_INT offset, + unsigned HOST_WIDE_INT nbytes, + unsigned lenrange[3], bool *nulterm, + bool *allnul, bool *allnonnul, + const vr_values *rvals, ssa_name_limit_t &snlim) +{ + int idx = get_stridx (exp); + if (idx > 0) + { + strinfo *si = get_strinfo (idx); + if (!si) + return false; + + /* Handle both constant lengths as well non-constant lengths + in some range. */ + unsigned HOST_WIDE_INT minlen, maxlen; + if (tree_fits_shwi_p (si->nonzero_chars)) + minlen = maxlen = tree_to_shwi (si->nonzero_chars); + else if (si->nonzero_chars + && TREE_CODE (si->nonzero_chars) == SSA_NAME) + { + vr_values *v = CONST_CAST (vr_values *, rvals); + const value_range_equiv *vr = v->get_value_range (si->nonzero_chars); + if (vr->kind () != VR_RANGE || !range_int_cst_p (vr)) + return false; + + minlen = tree_to_uhwi (vr->min ()); + maxlen = tree_to_uhwi (vr->max ()); + } + else + return false; + + if (maxlen < offset) + return false; + + minlen = minlen < offset ? 0 : minlen - offset; + maxlen -= offset; + if (maxlen + 1 < nbytes) + return false; + + if (nbytes <= minlen) + *nulterm = false; + + if (nbytes < minlen) + { + minlen = nbytes; + if (nbytes < maxlen) + maxlen = nbytes; + } + + if (minlen < lenrange[0]) + lenrange[0] = minlen; + if (lenrange[1] < maxlen) + lenrange[1] = maxlen; + + if (lenrange[2] < nbytes) + lenrange[2] = nbytes; + + /* Since only the length of the string are known and not its contents, + clear ALLNUL and ALLNONNUL purely on the basis of the length. */ + *allnul = false; + if (minlen < nbytes) + *allnonnul = false; + + return true; + } + + if (TREE_CODE (exp) == ADDR_EXPR) + return count_nonzero_bytes (TREE_OPERAND (exp, 0), offset, nbytes, + lenrange, nulterm, allnul, allnonnul, rvals, + snlim); + + if (TREE_CODE (exp) == SSA_NAME) + { + gimple *stmt = SSA_NAME_DEF_STMT (exp); + if (gimple_code (stmt) == GIMPLE_PHI) + { + /* Avoid processing an SSA_NAME that has already been visited + or if an SSA_NAME limit has been reached. Indicate success + if the former and failure if the latter. */ + if (int res = snlim.next_ssa_name (exp)) + return res > 0; + + /* Determine the minimum and maximum from the PHI arguments. */ + unsigned int n = gimple_phi_num_args (stmt); + for (unsigned i = 0; i != n; i++) + { + tree def = gimple_phi_arg_def (stmt, i); + if (!count_nonzero_bytes_addr (def, offset, nbytes, lenrange, + nulterm, allnul, allnonnul, rvals, + snlim)) + return false; + } + + return true; + } + } + + /* Otherwise we don't know anything. */ + lenrange[0] = 0; + if (lenrange[1] < nbytes) + lenrange[1] = nbytes; + if (lenrange[2] < nbytes) + lenrange[2] = nbytes; + *nulterm = false; + *allnul = false; + *allnonnul = false; + return true; +} + /* Same as above except with an implicit SSA_NAME limit. RVALS is used to determine ranges of dynamically computed string lengths (the results of strlen). */ -- cgit v1.1 From f582ca0fd70c5de7f1bcb532241d58f9e7f0090a Mon Sep 17 00:00:00 2001 From: Mihail Ionescu Date: Tue, 17 Mar 2020 12:39:39 +0000 Subject: [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE with -mfloat-abi=hard This patch adds a new multilib for armv8.1-m.main+mve with hard float abi. For armv8.1-m.main+mve soft and softfp, the v8-M multilibs will be reused. The following mappings are also updated: "-mfloat-abi=hard -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/hard" "-mfloat-abi=softfp -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/softfp" "-mfloat-abi=soft -march=armv8.1-m.main+mve.fp -> armv8-m.main/nofp" gcc/ChangeLog: 2020-03-17 Mihail Ionescu * config/arm/t-rmprofile: create new multilib for armv8.1-m.main+mve hard float and reuse v8-m.main ones for v8.1-m.main+mve . gcc/testsuite/ChangeLog: 2020-03-17 Mihail Ionescu * gcc.target/arm/multilib.exp: Add new v8.1-M entry. libgcc/ChangLog: 2020-03-17 Mihail Ionescu * config/arm/t-arm: Do not compile cmse_nonsecure_call.S for v8.1-m. --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/t-rmprofile | 13 +++++++------ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arm/multilib.exp | 3 +++ 4 files changed, 20 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c51606c..42bad0c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-17 Mihail Ionescu + + * config/arm/t-rmprofile: create new multilib for + armv8.1-m.main+mve hard float and reuse v8-m.main ones for + v8.1-m.main+mve. + 2020-03-17 Jakub Jelinek PR tree-optimization/94015 diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index 0fb3084..16e368f 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -27,8 +27,8 @@ # Arch and FPU variants to build libraries with -MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp -MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp +MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve +MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp v8.1-m.main+mve # Base M-profile (no fp) MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft @@ -48,8 +48,7 @@ MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=softfp MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp - - +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+mve/mfloat-abi=hard # Arch Matches MULTILIB_MATCHES += march?armv6s-m=march?armv6-m @@ -66,12 +65,14 @@ MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv7e-m armv8-m\.base armv8-m\.main, \ mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)/mfloat-abi.softfp) + # Map v8.1-M to v8-M. MULTILIB_MATCHES += march?armv8-m.main=march?armv8.1-m.main MULTILIB_MATCHES += march?armv8-m.main=march?armv8.1-m.main+dsp -MULTILIB_MATCHES += march?armv8-m.main=march?armv8.1-m.main+mve +MULTILIB_REUSE += mthumb/march.armv8-m\.main/mfloat-abi.soft=mthumb/march.armv8\.1-m\.main+mve/mfloat-abi.soft +MULTILIB_REUSE += mthumb/march.armv8-m\.main/mfloat-abi.soft=mthumb/march.armv8\.1-m\.main+mve/mfloat-abi.softfp -v8_1m_sp_variants = +fp +dsp+fp +mve.fp +v8_1m_sp_variants = +fp +dsp+fp +mve.fp +fp+mve v8_1m_dp_variants = +fp.dp +dsp+fp.dp +fp.dp+mve +fp.dp+mve.fp # Map all v8.1-m.main FP sp variants down to v8-m. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a389a6a..acf982f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-17 Mihail Ionescu + + * gcc.target/arm/multilib.exp: Add new v8.1-M entry. + 2020-03-17 Jakub Jelinek PR tree-optimization/94015 diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index 17111ee..f67a92a 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -814,6 +814,9 @@ if {[multilib_config "rmprofile"] } { {-march=armv8.1-m.main+mve.fp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8.1-m.main+mve -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" {-march=armv8.1-m.main+mve.fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8.1-m.main+mve -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+mve/hard" + {-march=armv8.1-m.main+mve+fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8.1-m.main+mve+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" {-march=armv8.1-m.main+mve.fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" {-march=armv8.1-m.main+mve+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8.1-m.main+mve.fp+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" -- cgit v1.1 From 700d4cb08c88aec37c13e21e63dd61fd698baabc Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 13:52:19 +0100 Subject: Fix up duplicated duplicated words mostly in comments In the r10-7197-gbae7b38cf8a21e068ad5c0bab089dedb78af3346 commit I've noticed duplicated word in a message, which lead me to grep for those and we have a tons of them. I've used grep -v 'long long\|optab optab\|template template\|double double' *.[chS] */*.[chS] *.def config/*/* 2>/dev/null | grep ' \([a-zA-Z]\+\) \1 ' Note, the command will not detect the doubled words at the start or end of line or when one of the words is at the end of line and the next one at the start of another one. Some of it is fairly obvious, e.g. all the "the the" cases which is something I've posted and committed patch for already e.g. in 2016, other cases are often valid, e.g. "that that" seems to look mostly ok to me. Some cases are quite hard to figure out, I've left out some of them from the patch (e.g. "and and" in some cases isn't talking about bitwise/logical and and so looks incorrect, but in other cases it is talking about those operations). In most cases the right solution seems to be to remove one of the duplicated words, but not always. I think most important are the ones with user visible messages (in the patch 3 of the first 4 hunks), the rest is just comments (and internal documentation; for that see the doc/tm.texi changes). 2020-03-17 Jakub Jelinek * lra-spills.c (remove_pseudos): Fix up duplicated word issue in a dump message. * tree-sra.c (create_access_replacement): Fix up duplicated word issue in a comment. * read-rtl-function.c (find_param_by_name, function_reader::parse_enum_value, function_reader::get_insn_by_uid): Likewise. * spellcheck.c (get_edit_distance_cutoff): Likewise. * tree-data-ref.c (create_ifn_alias_checks): Likewise. * tree.def (SWITCH_EXPR): Likewise. * selftest.c (assert_str_contains): Likewise. * ipa-param-manipulation.h (class ipa_param_body_adjustments): Likewise. * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. * langhooks.h (struct lang_hooks_for_decls): Likewise. * ipa-prop.h (struct ipa_param_descriptor): Likewise. * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): Likewise. * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. * tree-ssa-reassoc.c (reassociate_bb): Likewise. * tree.c (component_ref_size): Likewise. * hsa-common.c (hsa_init_compilation_unit_data): Likewise. * gimple-ssa-sprintf.c (get_string_length, format_string, format_directive): Likewise. * omp-grid.c (grid_process_kernel_body_copy): Likewise. * input.c (string_concat_db::get_string_concatenation, test_lexer_string_locations_ucn4): Likewise. * cfgexpand.c (pass_expand::execute): Likewise. * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, maybe_diag_overlap): Likewise. * rtl.c (RTX_CODE_HWINT_P_1): Likewise. * shrink-wrap.c (spread_components): Likewise. * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): Likewise. * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Likewise. * dwarf2out.c (dwarf2out_early_finish): Likewise. * gimple-ssa-store-merging.c: Likewise. * ira-costs.c (record_operand_costs): Likewise. * tree-vect-loop.c (vectorizable_reduction): Likewise. * target.def (dispatch): Likewise. (validate_dims, gen_ccmp_first): Fix up duplicated word issue in documentation text. * doc/tm.texi: Regenerated. * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up duplicated word issue in a comment. * config/i386/i386.c (ix86_test_loading_unspec): Likewise. * config/i386/i386-features.c (remove_partial_avx_dependency): Likewise. * config/msp430/msp430.c (msp430_select_section): Likewise. * config/gcn/gcn-run.c (load_image): Likewise. * config/aarch64/aarch64-sve.md (sve_ld1r): Likewise. * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. * config/aarch64/falkor-tag-collision-avoidance.c (single_dest_per_chain): Likewise. * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000-logue.c (rs6000_emit_probe_stack_range_stack_clash): Likewise. * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. Fix various other issues in the comment. c-family/ * c-common.c (resolve_overloaded_builtin): Fix up duplicated word issue in a diagnostic message. cp/ * pt.c (tsubst): Fix up duplicated word issue in a diagnostic message. (lookup_template_class_1, tsubst_expr): Fix up duplicated word issue in a comment. * parser.c (cp_parser_statement, cp_parser_linkage_specification, cp_parser_placeholder_type_specifier, cp_parser_constraint_requires_parens): Likewise. * name-lookup.c (suggest_alternative_in_explicit_scope): Likewise. fortran/ * array.c (gfc_check_iter_variable): Fix up duplicated word issue in a comment. * arith.c (gfc_arith_concat): Likewise. * resolve.c (gfc_resolve_ref): Likewise. * frontend-passes.c (matmul_lhs_realloc): Likewise. * module.c (gfc_match_submodule, load_needed): Likewise. * trans-expr.c (gfc_init_se): Likewise. --- gcc/ChangeLog | 70 ++++++++++++++++++++++ gcc/c-family/ChangeLog | 5 ++ gcc/c-family/c-common.c | 2 +- gcc/cfgexpand.c | 2 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 2 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386.c | 2 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 ++-- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/rs6000/rs6000-c.c | 2 +- gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 2 +- gcc/cp/ChangeLog | 10 ++++ gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 10 ++-- gcc/cp/pt.c | 6 +- gcc/doc/tm.texi | 4 +- gcc/dwarf2out.c | 2 +- gcc/fortran/ChangeLog | 10 ++++ gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/module.c | 4 +- gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-expr.c | 2 +- gcc/gimple-ssa-sprintf.c | 6 +- gcc/gimple-ssa-store-merging.c | 2 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/hsa-common.c | 2 +- gcc/input.c | 4 +- gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-prop.h | 2 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/lra-spills.c | 2 +- gcc/omp-grid.c | 2 +- gcc/read-rtl-function.c | 6 +- gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-data-ref.c | 2 +- gcc/tree-sra.c | 2 +- gcc/tree-ssa-dom.c | 2 +- gcc/tree-ssa-dse.c | 4 +- gcc/tree-ssa-loop-split.c | 2 +- gcc/tree-ssa-math-opts.c | 2 +- gcc/tree-ssa-reassoc.c | 2 +- gcc/tree-ssa-strlen.c | 4 +- gcc/tree-vect-loop.c | 2 +- gcc/tree.c | 2 +- gcc/tree.def | 2 +- 62 files changed, 176 insertions(+), 81 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42bad0c..98fc289 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,73 @@ +2020-03-17 Jakub Jelinek + + * lra-spills.c (remove_pseudos): Fix up duplicated word issue in + a dump message. + * tree-sra.c (create_access_replacement): Fix up duplicated word issue + in a comment. + * read-rtl-function.c (find_param_by_name, + function_reader::parse_enum_value, function_reader::get_insn_by_uid): + Likewise. + * spellcheck.c (get_edit_distance_cutoff): Likewise. + * tree-data-ref.c (create_ifn_alias_checks): Likewise. + * tree.def (SWITCH_EXPR): Likewise. + * selftest.c (assert_str_contains): Likewise. + * ipa-param-manipulation.h (class ipa_param_body_adjustments): + Likewise. + * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. + * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. + * langhooks.h (struct lang_hooks_for_decls): Likewise. + * ipa-prop.h (struct ipa_param_descriptor): Likewise. + * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): + Likewise. + * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. + * tree-ssa-reassoc.c (reassociate_bb): Likewise. + * tree.c (component_ref_size): Likewise. + * hsa-common.c (hsa_init_compilation_unit_data): Likewise. + * gimple-ssa-sprintf.c (get_string_length, format_string, + format_directive): Likewise. + * omp-grid.c (grid_process_kernel_body_copy): Likewise. + * input.c (string_concat_db::get_string_concatenation, + test_lexer_string_locations_ucn4): Likewise. + * cfgexpand.c (pass_expand::execute): Likewise. + * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, + maybe_diag_overlap): Likewise. + * rtl.c (RTX_CODE_HWINT_P_1): Likewise. + * shrink-wrap.c (spread_components): Likewise. + * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): + Likewise. + * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): + Likewise. + * dwarf2out.c (dwarf2out_early_finish): Likewise. + * gimple-ssa-store-merging.c: Likewise. + * ira-costs.c (record_operand_costs): Likewise. + * tree-vect-loop.c (vectorizable_reduction): Likewise. + * target.def (dispatch): Likewise. + (validate_dims, gen_ccmp_first): Fix up duplicated word issue + in documentation text. + * doc/tm.texi: Regenerated. + * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up + duplicated word issue in a comment. + * config/i386/i386.c (ix86_test_loading_unspec): Likewise. + * config/i386/i386-features.c (remove_partial_avx_dependency): + Likewise. + * config/msp430/msp430.c (msp430_select_section): Likewise. + * config/gcn/gcn-run.c (load_image): Likewise. + * config/aarch64/aarch64-sve.md (sve_ld1r): Likewise. + * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. + * config/aarch64/falkor-tag-collision-avoidance.c + (single_dest_per_chain): Likewise. + * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. + * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. + * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. + * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): + Likewise. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. + * config/rs6000/rs6000-logue.c + (rs6000_emit_probe_stack_range_stack_clash): Likewise. + * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. + Fix various other issues in the comment. + 2020-03-17 Mihail Ionescu * config/arm/t-rmprofile: create new multilib for diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index f03e44f..59661ef 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Jakub Jelinek + + * c-common.c (resolve_overloaded_builtin): Fix up duplicated word + issue in a diagnostic message. + 2020-03-15 Lewis Hyatt * c.opt: Avoid redundancy in the help text. diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 7e2dfb3..25020bf14 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -7427,7 +7427,7 @@ resolve_overloaded_builtin (location_t loc, tree function, warning_at (input_location, 0, "this target does not define a speculation barrier; " "your program will still execute correctly, " - "but incorrect speculation may not be be " + "but incorrect speculation may not be " "restricted"); /* If the optional second argument is present, handle any side diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index 9864e43..a7ec77d 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -6656,7 +6656,7 @@ pass_expand::execute (function *fun) if (crtl->tail_call_emit) fixup_tail_calls (); - /* BB subdivision may have created basic blocks that are are only reachable + /* BB subdivision may have created basic blocks that are only reachable from unlikely bbs but not marked as such in the profile. */ if (optimize) propagate_unlikely_bbs_forward (); diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index a661b25..f7a0893 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2477,7 +2477,7 @@ ) ;; This is used for vec_duplicates from memory, but can also -;; be used by combine to optimize selects of a a vec_duplicate +;; be used by combine to optimize selects of a vec_duplicate ;; with zero. (define_insn "sve_ld1r" [(set (match_operand:SVE_ALL 0 "register_operand" "=w") diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index b0cbb6e2..285341e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -21296,7 +21296,7 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, { base_off = 0x1000 - 1; /* We must still make sure that the base offset is aligned with respect - to the address. But it may may not be made any bigger. */ + to the address. But it may not be made any bigger. */ base_off -= (((base_off % msize) - (off_val_1 % msize)) + msize) % msize; } diff --git a/gcc/config/aarch64/falkor-tag-collision-avoidance.c b/gcc/config/aarch64/falkor-tag-collision-avoidance.c index b4e92a7..719df48 100644 --- a/gcc/config/aarch64/falkor-tag-collision-avoidance.c +++ b/gcc/config/aarch64/falkor-tag-collision-avoidance.c @@ -699,7 +699,7 @@ in_same_chain (rtx_insn *insn, rtx_insn *cand, unsigned regno) /* Callback function to traverse the tag map and drop loads that have the same - destination and and in the same chain of occurrence. Routine always returns + destination and are in the same chain of occurrence. Routine always returns true to allow traversal through all of TAG_MAP. */ bool single_dest_per_chain (const rtx &t ATTRIBUTE_UNUSED, insn_info_list_t *v, diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index 08411b4..ffbb921 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -781,7 +781,7 @@ fr30_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg) are sufficient argument registers available (or if no registers are needed because the parameter must be passed on the stack) then return zero, as this parameter does not require partial - register, partial stack stack space. */ + register, partial stack space. */ if (*cum + fr30_num_arg_regs (arg) <= FR30_NUM_ARG_REGS) return 0; diff --git a/gcc/config/gcn/gcn-run.c b/gcc/config/gcn/gcn-run.c index 7bec741..1e952e9 100644 --- a/gcc/config/gcn/gcn-run.c +++ b/gcc/config/gcn/gcn-run.c @@ -575,7 +575,7 @@ found_main:; break; case R_AMDGPU_REL64: /* FIXME - LLD seems to emit REL64 where the the assembler has ABS64. + LLD seems to emit REL64 where the assembler has ABS64. This is clearly wrong because it's not what the compiler is expecting. Let's assume, for now, that it's a bug. In any case, GCN kernels are always self contained and diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c index 6919c83..6528832 100644 --- a/gcc/config/i386/i386-features.c +++ b/gcc/config/i386/i386-features.c @@ -2224,7 +2224,7 @@ remove_partial_avx_dependency (void) loop_optimizer_init (AVOID_CFG_MODIFICATIONS); /* Generate a vxorps at entry of the nearest dominator for basic - blocks with conversions, which is in the the fake loop that + blocks with conversions, which is in the fake loop that contains the whole function, so that there is only a single vxorps in the whole function. */ bb = nearest_common_dominator_for_set (CDI_DOMINATORS, diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d1910b4..049ca4f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -22928,7 +22928,7 @@ ix86_test_loading_unspec () /* Verify that the two mems are thus treated as equal. */ ASSERT_TRUE (rtx_equal_p (dst, v0)); - /* Verify the the insn is recognized. */ + /* Verify that the insn is recognized. */ ASSERT_NE(-1, recog_memoized (insn)); /* Test of an UNSPEC_VOLATILE, which has its own enum values. */ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 41b3d52..1776aba 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -70,7 +70,7 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", upper part undefined. */ DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8) -/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of of flags +/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of flags set by instructions affecting just some flags (in particular shifts). This is because Core2 resolves dependencies on whole flags register and such sequences introduce false dependency on previous instruction diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index 25d1916..cde14c8 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1916,7 +1916,7 @@ msp430_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) case SECCAT_RODATA_MERGE_CONST: return default_elf_select_section (decl, reloc, align); - /* The sections listed below are are not supported for MSP430. + /* The sections listed below are not supported for MSP430. They should not be generated, but in case they are, we use default_select_section so they get placed in sections the msp430 assembler and linker understand. */ diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c index a9f930f..055a582 100644 --- a/gcc/config/nds32/nds32-md-auxiliary.c +++ b/gcc/config/nds32/nds32-md-auxiliary.c @@ -3304,12 +3304,12 @@ nds32_split_ashiftdi3 (rtx dst, rtx src, rtx shiftamount) ext_start = gen_reg_rtx (SImode); /* - # In fact, we want to check shift amonut is great than or equal 32, - # but in some corner case, the shift amount might be very large value, - # however we've defined SHIFT_COUNT_TRUNCATED, so GCC think we've - # handle that correctly without any truncate. - # so check the the condition of (shiftamount & 32) is most - # safe way to do. + # In fact, we want to check shift amount is greater than or equal to + # 32, but in some corner case, the shift amount might be very large + # value, however we've defined SHIFT_COUNT_TRUNCATED, so GCC thinks + # we've handled that correctly without any truncate. + # So checking the condition of (shiftamount & 32) is the safest + # way to do it. if (shiftamount & 32) dst_low_part = 0 dst_high_part = src_low_part << shiftamount & 0x1f diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index 690822a..e3e84df 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -975,7 +975,7 @@ write_fn_proto_from_insn (std::stringstream &s, const char *name, } /* DECL is an external FUNCTION_DECL, make sure its in the fndecl hash - table and and write a ptx prototype. These are emitted at end of + table and write a ptx prototype. These are emitted at end of compilation. */ static void diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 8c1fbbf..e59eff9 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -397,7 +397,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of the specific flags that are associated with each of the cpu choices that can be specified as the target of a -mcpu=target - compile option, or as the the target of a --with-cpu=target + compile option, or as the target of a --with-cpu=target configure option. Target flags that are specified in either of these two ways are considered "implicit" since the flags are not mentioned specifically by name. diff --git a/gcc/config/rs6000/rs6000-logue.c b/gcc/config/rs6000/rs6000-logue.c index fecc3e6..4cbf228 100644 --- a/gcc/config/rs6000/rs6000-logue.c +++ b/gcc/config/rs6000/rs6000-logue.c @@ -1547,7 +1547,7 @@ rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size, /* If explicitly requested, or the rounded size is not the same as the original size - or the the rounded size is greater than a page, + or the rounded size is greater than a page, then we will need a copy of the original stack pointer. */ if (rounded_size != orig_size || rounded_size > probe_interval diff --git a/gcc/config/rs6000/rs6000-p8swap.c b/gcc/config/rs6000/rs6000-p8swap.c index 067176d..3d5dc7d 100644 --- a/gcc/config/rs6000/rs6000-p8swap.c +++ b/gcc/config/rs6000/rs6000-p8swap.c @@ -1922,7 +1922,7 @@ replace_swapped_load_constant (swap_web_entry *insn_entry, rtx swap_insn) XEXP (new_mem, 0) = base_reg; /* Move the newly created insn ahead of the load insn. */ - /* The last insn is the the insn that forced new_mem into a register. */ + /* The last insn is the insn that forced new_mem into a register. */ rtx_insn *force_insn = get_last_insn (); /* Remove this insn from the end of the instruction sequence. */ remove_insn (force_insn); diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c index 9cfa684..fe7177f 100644 --- a/gcc/config/rs6000/rs6000-string.c +++ b/gcc/config/rs6000/rs6000-string.c @@ -679,7 +679,7 @@ expand_cmp_vec_sequence (unsigned HOST_WIDE_INT bytes_to_compare, bnl 6,.Lmismatch For the P8 LE case, we use lxvd2x and compare full 16 bytes - but then use use vgbbd and a shift to get two bytes with the + but then use vgbbd and a shift to get two bytes with the information we need in the correct order. VEC/VSX compare sequence if TARGET_P9_VECTOR: diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5798f92..2080c7d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3956,7 +3956,7 @@ rs6000_option_override_internal (bool global_init_p) } /* Enable the default support for IEEE 128-bit floating point on Linux VSX - sytems. In GCC 7, we would enable the the IEEE 128-bit floating point + sytems. In GCC 7, we would enable the IEEE 128-bit floating point infrastructure (-mfloat128-type) but not enable the actual __float128 type unless the user used the explicit -mfloat128. In GCC 8, we enable both the keyword as well as the type. */ diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 661ba2b..15b3ccc 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2020-03-17 Jakub Jelinek + + * pt.c (tsubst): Fix up duplicated word issue in a diagnostic message. + (lookup_template_class_1, tsubst_expr): Fix up duplicated word issue + in a comment. + * parser.c (cp_parser_statement, cp_parser_linkage_specification, + cp_parser_placeholder_type_specifier, + cp_parser_constraint_requires_parens): Likewise. + * name-lookup.c (suggest_alternative_in_explicit_scope): Likewise. + 2020-03-15 Iain Sandoe * coroutines.cc (co_await_expander): Fix indentation. diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c index e5638d2..d00bb5f 100644 --- a/gcc/cp/name-lookup.c +++ b/gcc/cp/name-lookup.c @@ -5938,7 +5938,7 @@ maybe_suggest_missing_header (location_t location, tree name, tree scope) /* Generate a name_hint at LOCATION for NAME, an IDENTIFIER_NODE for which name lookup failed within the explicitly provided SCOPE. - Suggest the the best meaningful candidates (if any), otherwise + Suggest the best meaningful candidates (if any), otherwise an empty name_hint is returned. */ name_hint diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 0c7db8b..58a1bea 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -11346,8 +11346,8 @@ cp_parser_statement (cp_parser* parser, tree in_statement_expr, /* This must be a namespace alias definition. */ if (std_attrs != NULL_TREE) { - /* Attributes should be parsed as part of the the - declaration, so let's un-parse them. */ + /* Attributes should be parsed as part of the + declaration, so let's un-parse them. */ saved_tokens.rollback(); std_attrs = NULL_TREE; } @@ -14554,7 +14554,7 @@ cp_parser_linkage_specification (cp_parser* parser) /* We're now using the new linkage. */ push_lang_context (linkage); - /* Preserve the location of the the innermost linkage specification, + /* Preserve the location of the innermost linkage specification, tracking the locations of nested specifications via a local. */ location_t saved_location = parser->innermost_linkage_specification_location; @@ -18316,7 +18316,7 @@ cp_parser_placeholder_type_specifier (cp_parser *parser, location_t loc, } /* A type constraint constrains a contextually determined type or type - parameter pack. However, the the Concepts TS does allow concepts + parameter pack. However, the Concepts TS does allow concepts to introduce non-type and template template parameters. */ if (TREE_CODE (proto) != TYPE_DECL) { @@ -27339,7 +27339,7 @@ cp_parser_constraint_requires_parens (cp_parser *parser, bool lambda_p) case CPP_EQ: { - /* An equal sign may be part of the the definition of a function, + /* An equal sign may be part of the definition of a function, and not an assignment operator, when parsing the expression for a trailing requires-clause. For example: diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 48ac486..c57d570 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -9682,7 +9682,7 @@ lookup_template_class_1 (tree d1, tree arglist, tree in_decl, tree context, if (entry) return entry->spec; - /* If the the template's constraints are not satisfied, + /* If the template's constraints are not satisfied, then we cannot form a valid type. Note that the check is deferred until after the hash @@ -15688,7 +15688,7 @@ tsubst (tree t, tree args, tsubst_flags_t complain, tree in_decl) else if (TYPENAME_IS_CLASS_P (t) && !CLASS_TYPE_P (f)) { if (complain & tf_error) - error ("%qT resolves to %qT, which is is not a class type", + error ("%qT resolves to %qT, which is not a class type", t, f); else return error_mark_node; @@ -17855,7 +17855,7 @@ tsubst_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl, case RANGE_FOR_STMT: { /* Construct another range_for, if this is not a final - substitution (for inside inside a generic lambda of a + substitution (for inside a generic lambda of a template). Otherwise convert to a regular for. */ tree decl, expr; stmt = (processing_template_decl diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 3560cfa..64e7b00 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -6157,7 +6157,7 @@ but might be present in another OpenMP context in the same TU. This hook should check the launch dimensions provided for an OpenACC compute region, or routine. Defaulted values are represented as -1 and non-constant values as 0. The @var{fn_level} is negative for the -function corresponding to the compute region. For a routine is is the +function corresponding to the compute region. For a routine it is the outermost level at which partitioned execution may be spawned. The hook should verify non-default values. If DECL is NULL, global defaults are being validated and unspecified defaults should be filled in. @@ -11858,7 +11858,7 @@ This function prepares to emit a comparison insn for the first compare in a with @code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}. The insns to prepare the compare are saved in @var{prep_seq} and the compare insns are saved in @var{gen_seq}. They will be emitted when all the - compares in the the conditional comparision are generated without error. + compares in the conditional comparision are generated without error. @var{code} is the @code{rtx_code} of the compare for @var{op0} and @var{op1}. @end deftypefn diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index bb45279..0c8606a 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -32152,7 +32152,7 @@ dwarf2out_early_finish (const char *filename) location related output removed and some LTO specific changes. Some refactoring might make both smaller and easier to match up. */ - /* Traverse the DIE's and add add sibling attributes to those DIE's + /* Traverse the DIE's and add sibling attributes to those DIE's that have children. */ add_sibling_attributes (comp_unit_die ()); for (limbo_die_node *node = limbo_die_list; node; node = node->next) diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index dd0487d..99b13db 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,13 @@ +2020-03-17 Jakub Jelinek + + * array.c (gfc_check_iter_variable): Fix up duplicated word issue + in a comment. + * arith.c (gfc_arith_concat): Likewise. + * resolve.c (gfc_resolve_ref): Likewise. + * frontend-passes.c (matmul_lhs_realloc): Likewise. + * module.c (gfc_match_submodule, load_needed): Likewise. + * trans-expr.c (gfc_init_se): Likewise. + 2020-03-15 Lewis Hyatt * lang.opt: Avoid redundancy in the help text. diff --git a/gcc/fortran/arith.c b/gcc/fortran/arith.c index 7325b28..7eb82d0 100644 --- a/gcc/fortran/arith.c +++ b/gcc/fortran/arith.c @@ -994,7 +994,7 @@ gfc_arith_concat (gfc_expr *op1, gfc_expr *op2, gfc_expr **resultp) gfc_expr *result; size_t len; - /* By cleverly playing around with constructors, is is possible + /* By cleverly playing around with constructors, it is possible to get mismaching types here. */ if (op1->ts.type != BT_CHARACTER || op2->ts.type != BT_CHARACTER || op1->ts.kind != op2->ts.kind) diff --git a/gcc/fortran/array.c b/gcc/fortran/array.c index 82b0eb3..57972bc 100644 --- a/gcc/fortran/array.c +++ b/gcc/fortran/array.c @@ -1475,7 +1475,7 @@ static cons_stack *base; static bool check_constructor (gfc_constructor_base, bool (*) (gfc_expr *)); /* Check an EXPR_VARIABLE expression in a constructor to make sure - that that variable is an iteration variables. */ + that that variable is an iteration variable. */ bool gfc_check_iter_variable (gfc_expr *expr) diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c index bbe34d6..d5d71b5 100644 --- a/gcc/fortran/frontend-passes.c +++ b/gcc/fortran/frontend-passes.c @@ -3190,7 +3190,7 @@ matmul_lhs_realloc (gfc_expr *c, gfc_expr *a, gfc_expr *b, gcc_assert (ar && ar->type == AR_FULL); /* c comes in as a full ref. Change it into a copy and make it into an - element ref so it has the right form for for ALLOCATE. In the same + element ref so it has the right form for ALLOCATE. In the same switch statement, also generate the size comparison for the secod IF statement. */ diff --git a/gcc/fortran/module.c b/gcc/fortran/module.c index b6a4e87..73a3f20 100644 --- a/gcc/fortran/module.c +++ b/gcc/fortran/module.c @@ -743,7 +743,7 @@ cleanup: ordered pair whose first element is the ancestor module name and whose second element is the submodule name. 'Submodule_name' is used for the submodule filename and uses '@' as a separator, whilst - the name of the symbol for the module uses '.' as a a separator. + the name of the symbol for the module uses '.' as a separator. The reasons for these choices are: (i) To follow another leading brand in the submodule filenames; (ii) Since '.' is not particularly visible in the filenames; and @@ -5044,7 +5044,7 @@ load_needed (pointer_info *p) sym->attr.use_assoc = 1; /* Unliked derived types, a STRUCTURE may share names with other symbols. - We greedily converted the the symbol name to lowercase before we knew its + We greedily converted the symbol name to lowercase before we knew its type, so now we must fix it. */ if (sym->attr.flavor == FL_STRUCT) sym->name = gfc_dt_upper_string (sym->name); diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c index b5813a7..23b5a2b 100644 --- a/gcc/fortran/resolve.c +++ b/gcc/fortran/resolve.c @@ -5318,7 +5318,7 @@ gfc_resolve_ref (gfc_expr *expr) { array_ref->u.ar.type = AR_ELEMENT; expr->rank = 0; - /* INQUIRY_LEN is not evaluated from the the rest of the expr + /* INQUIRY_LEN is not evaluated from the rest of the expr but directly from the string length. This means that setting the array indices to one does not matter but might trigger a runtime bounds error. Suppress the check. */ diff --git a/gcc/fortran/trans-expr.c b/gcc/fortran/trans-expr.c index 9d0921e..fdca9cc 100644 --- a/gcc/fortran/trans-expr.c +++ b/gcc/fortran/trans-expr.c @@ -1639,7 +1639,7 @@ gfc_copy_se_loopvars (gfc_se * dest, gfc_se * src) Care must be taken when multiple se are created with the same parent. The child se must be kept in sync. The easiest way is to delay creation - of a child se until after after the previous se has been translated. */ + of a child se until after the previous se has been translated. */ void gfc_init_se (gfc_se * se, gfc_se * parent) diff --git a/gcc/gimple-ssa-sprintf.c b/gcc/gimple-ssa-sprintf.c index a9d2504..13640e0 100644 --- a/gcc/gimple-ssa-sprintf.c +++ b/gcc/gimple-ssa-sprintf.c @@ -2098,7 +2098,7 @@ get_string_length (tree str, unsigned eltsize, const vr_values *vr) if (res.range.max < target_int_max ()) { res.knownrange = true; - /* When the the length of the longest string is known and not + /* When the length of the longest string is known and not excessive use it as the likely length of the string(s). */ res.range.likely = res.range.max; } @@ -2478,7 +2478,7 @@ format_string (const directive &dir, tree arg, const vr_values *vr_values) is bounded by MB_LEN_MAX * wcslen (S). */ res.range.max *= target_mb_len_max (); res.range.unlikely = res.range.max; - /* It's likely that the the total length is not more that + /* It's likely that the total length is not more that 2 * wcslen (S).*/ res.range.likely = res.range.min * 2; @@ -3337,7 +3337,7 @@ format_directive (const call_info &info, } else if (!info.is_string_func ()) { - /* If the warning is for a file function function like fprintf + /* If the warning is for a file function like fprintf of printf with no destination size just print the computed result. */ if (min == max) diff --git a/gcc/gimple-ssa-store-merging.c b/gcc/gimple-ssa-store-merging.c index c5dc1a8..4d4f549 100644 --- a/gcc/gimple-ssa-store-merging.c +++ b/gcc/gimple-ssa-store-merging.c @@ -61,7 +61,7 @@ record the surrounding bit region, i.e. bits that could be stored in a read-modify-write operation when storing the bit-field. Record store chains to different bases in a hash_map (m_stores) and make sure to - terminate such chains when appropriate (for example when when the stored + terminate such chains when appropriate (for example when the stored values get used subsequently). These stores can be a result of structure element initializers, array stores etc. A store_immediate_info object is recorded for every such store. diff --git a/gcc/gimple-ssa-warn-restrict.c b/gcc/gimple-ssa-warn-restrict.c index 5e7e5d4..a6a9635 100644 --- a/gcc/gimple-ssa-warn-restrict.c +++ b/gcc/gimple-ssa-warn-restrict.c @@ -577,7 +577,7 @@ builtin_memref::offset_out_of_bounds (int strict, offset_int ooboff[3]) const bool hib = wi::les_p (offrng[0], offrng[1]); bool lob = !hib; - /* Set to the size remaining in the object object after subtracting + /* Set to the size remaining in the object after subtracting REFOFF. It may become negative as a result of negative indices into the enclosing object, such as in: extern struct S { char a[4], b[3], c[1]; } *p; @@ -1430,7 +1430,7 @@ builtin_access::overlap () } /* Attempt to detect and diagnose an overlapping copy in a call expression - EXPR involving an an access ACS to a built-in memory or string function. + EXPR involving an access ACS to a built-in memory or string function. Return true when one has been detected, false otherwise. */ static bool diff --git a/gcc/hsa-common.c b/gcc/hsa-common.c index 6af5d0f..4b06791 100644 --- a/gcc/hsa-common.c +++ b/gcc/hsa-common.c @@ -95,7 +95,7 @@ hsa_callable_function_p (tree fndecl) && !lookup_attribute ("oacc function", DECL_ATTRIBUTES (fndecl))); } -/* Allocate HSA structures that are are used when dealing with different +/* Allocate HSA structures that are used when dealing with different functions. */ void diff --git a/gcc/input.c b/gcc/input.c index 8fe5d42..dd1d23d 100644 --- a/gcc/input.c +++ b/gcc/input.c @@ -1296,7 +1296,7 @@ string_concat_db::record_string_concatenation (int num, location_t *locs) m_table->put (key_loc, concat); } -/* Determine if LOC was the location of the the initial token of a +/* Determine if LOC was the location of the initial token of a concatenation of string literal tokens. If so, *OUT_NUM is written to with the number of tokens, and *OUT_LOCS with the location of an array of locations of the @@ -2701,7 +2701,7 @@ test_lexer_string_locations_ucn4 (const line_table_case &case_) /* Verify that cpp_interpret_string works. The string should be encoded in the execution character - set. Assuming that that is UTF-8, we should have the following: + set. Assuming that is UTF-8, we should have the following: ----------- ---- ----- ------- ---------------- Byte offset Byte Octal Unicode Source Column(s) ----------- ---- ----- ------- ---------------- diff --git a/gcc/ipa-param-manipulation.h b/gcc/ipa-param-manipulation.h index 098f8c1..0b038ea 100644 --- a/gcc/ipa-param-manipulation.h +++ b/gcc/ipa-param-manipulation.h @@ -406,7 +406,7 @@ private: auto_vec m_new_types; - /* Vector of structures telling how to replace old parameters in in the + /* Vector of structures telling how to replace old parameters in the function body. TODO: Even though there usually be only few, but should we use a hash? */ diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h index ea5043a..168c4c2 100644 --- a/gcc/ipa-prop.h +++ b/gcc/ipa-prop.h @@ -438,7 +438,7 @@ ipa_get_jf_ancestor_type_preserved (struct ipa_jump_func *jfunc) struct GTY(()) ipa_param_descriptor { /* In analysis and modification phase, this is the PARAM_DECL of this - parameter, in IPA LTO phase, this is the type of the the described + parameter, in IPA LTO phase, this is the type of the described parameter or NULL if not known. Do not read this field directly but through ipa_get_param and ipa_get_type as appropriate. */ tree decl_or_type; diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index d9e7105..6891156 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1319,7 +1319,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref) hard_reg_class = REGNO_REG_CLASS (other_regno); bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class]; /* Target code may return any cost for mode which does not - fit the the hard reg class (e.g. DImode for AREG on + fit the hard reg class (e.g. DImode for AREG on i386). Check this and use a bigger class to get the right cost. */ if (bigger_hard_reg_class != NO_REGS diff --git a/gcc/langhooks.h b/gcc/langhooks.h index f430759..83069a9 100644 --- a/gcc/langhooks.h +++ b/gcc/langhooks.h @@ -227,7 +227,7 @@ struct lang_hooks_for_decls bool (*ok_for_sibcall) (const_tree); /* Return a tree for the actual data of an array descriptor - or NULL_TREE - if original tree is not an array descriptor. If the the second argument + if original tree is not an array descriptor. If the second argument is true, only the TREE_TYPE is returned without generating a new tree. */ tree (*omp_array_data) (tree, bool); diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c index a4b955a..0caa4ac 100644 --- a/gcc/lra-spills.c +++ b/gcc/lra-spills.c @@ -434,7 +434,7 @@ remove_pseudos (rtx *loc, rtx_insn *insn) lra_get_insn_recog_data (insn)->used_insn_alternative = -1; if (lra_dump_file != NULL) fprintf (lra_dump_file, - "Memory subreg was simplified in in insn #%u\n", + "Memory subreg was simplified in insn #%u\n", INSN_UID (insn)); } } diff --git a/gcc/omp-grid.c b/gcc/omp-grid.c index 7c93f0b..b98e45d 100644 --- a/gcc/omp-grid.c +++ b/gcc/omp-grid.c @@ -1186,7 +1186,7 @@ grid_mark_tiling_parallels_and_loops (gimple_stmt_iterator *gsi, /* Given freshly copied top level kernel SEQ, identify the individual OMP components, mark them as part of kernel, copy assignment leading to them just before DST, remapping them using WI and adding new temporaries to - TGT_BIND, and and return the loop that will be used for kernel dispatch. */ + TGT_BIND, and return the loop that will be used for kernel dispatch. */ static gomp_for * grid_process_kernel_body_copy (grid_prop *grid, gimple_seq seq, diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c index 3cf5200..3379d64 100644 --- a/gcc/read-rtl-function.c +++ b/gcc/read-rtl-function.c @@ -532,7 +532,7 @@ function_reader::create_function () } -/* Look within the the params of FNDECL for a param named NAME. +/* Look within the params of FNDECL for a param named NAME. Return NULL_TREE if one isn't found. */ static tree @@ -969,7 +969,7 @@ function_reader::read_rtx_operand_u (rtx x, int idx) /* Read a name, looking for a match against a string found in array STRINGS of size NUM_VALUES. - Return the index of the the matched string, or emit an error. */ + Return the index of the matched string, or emit an error. */ int function_reader::parse_enum_value (int num_values, const char *const *strings) @@ -1611,7 +1611,7 @@ function_reader::apply_fixups () } /* Given a UID value, try to locate a pointer to the corresponding - rtx_insn *, or NULL if if can't be found. */ + rtx_insn *, or NULL if it can't be found. */ rtx_insn ** function_reader::get_insn_by_uid (int uid) diff --git a/gcc/rtl.c b/gcc/rtl.c index 4d527cf..4411e06 100644 --- a/gcc/rtl.c +++ b/gcc/rtl.c @@ -106,7 +106,7 @@ const enum rtx_class rtx_class[NUM_RTX_CODE] = { #undef DEF_RTL_EXPR }; -/* Whether rtxs with the given code code store data in the hwint field. */ +/* Whether rtxs with the given code store data in the hwint field. */ #define RTX_CODE_HWINT_P_1(ENUM) \ ((ENUM) == CONST_INT || (ENUM) == CONST_DOUBLE \ diff --git a/gcc/selftest.c b/gcc/selftest.c index 69d134e..f9368fa 100644 --- a/gcc/selftest.c +++ b/gcc/selftest.c @@ -95,7 +95,7 @@ assert_streq (const location &loc, } /* Implementation detail of ASSERT_STR_CONTAINS. - Use strstr to determine if val_needle is is within val_haystack. + Use strstr to determine if val_needle is within val_haystack. ::selftest::pass if it is found. ::selftest::fail if it is not found. */ diff --git a/gcc/shrink-wrap.c b/gcc/shrink-wrap.c index 21b37bf..775db9c 100644 --- a/gcc/shrink-wrap.c +++ b/gcc/shrink-wrap.c @@ -1380,7 +1380,7 @@ spread_components (sbitmap components) todo.release (); - /* Finally, mark everything not not needed both forwards and backwards. */ + /* Finally, mark everything not needed both forwards and backwards. */ bool did_changes = false; diff --git a/gcc/spellcheck.c b/gcc/spellcheck.c index 9b9bcdf..7891260 100644 --- a/gcc/spellcheck.c +++ b/gcc/spellcheck.c @@ -166,7 +166,7 @@ find_closest_string (const char *target, to be meaningful, given a goal of length GOAL_LEN and a candidate of length CANDIDATE_LEN. - This is a third of the the length of the candidate or of the goal, + This is a third of the length of the candidate or of the goal, whichever is bigger. */ edit_distance_t diff --git a/gcc/target.def b/gcc/target.def index b5e82ff..62e3d62 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -1519,7 +1519,7 @@ in its second parameter.", void, (rtx_insn *insn, int x), hook_void_rtx_insn_int) -/* The following member value is a a function that returns true is +/* The following member value is a function that returns true is dispatch schedling is supported in hardware and condition passed as the second parameter is true. */ DEFHOOK @@ -1694,7 +1694,7 @@ DEFHOOK "This hook should check the launch dimensions provided for an OpenACC\n\ compute region, or routine. Defaulted values are represented as -1\n\ and non-constant values as 0. The @var{fn_level} is negative for the\n\ -function corresponding to the compute region. For a routine is is the\n\ +function corresponding to the compute region. For a routine it is the\n\ outermost level at which partitioned execution may be spawned. The hook\n\ should verify non-default values. If DECL is NULL, global defaults\n\ are being validated and unspecified defaults should be filled in.\n\ @@ -2675,7 +2675,7 @@ DEFHOOK with @code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.\n\ The insns to prepare the compare are saved in @var{prep_seq} and the compare\n\ insns are saved in @var{gen_seq}. They will be emitted when all the\n\ - compares in the the conditional comparision are generated without error.\n\ + compares in the conditional comparision are generated without error.\n\ @var{code} is the @code{rtx_code} of the compare for @var{op0} and @var{op1}.", rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, int code, tree op0, tree op1), NULL) diff --git a/gcc/tree-call-cdce.c b/gcc/tree-call-cdce.c index 54b18a6..79237cc 100644 --- a/gcc/tree-call-cdce.c +++ b/gcc/tree-call-cdce.c @@ -832,7 +832,7 @@ shrink_wrap_one_built_in_call_with_conds (gcall *bi_call, vec conds, 4. [guard m]: [guard m+1] for 0 <= m <= n-2 5. [join]: [guard n-1] - We punt for the more complex case case of [join] being old and + We punt for the more complex case of [join] being old and simply free the dominance info. We also punt on postdominators, which aren't expected to be available at this point anyway. */ bi_call_bb = gimple_bb (bi_call); diff --git a/gcc/tree-data-ref.c b/gcc/tree-data-ref.c index e2ea5b8..851225e 100644 --- a/gcc/tree-data-ref.c +++ b/gcc/tree-data-ref.c @@ -1751,7 +1751,7 @@ create_ifn_alias_checks (tree *cond_expr, return false; /* Make sure that both DRs access the same pattern of bytes, - with a constant length and and step. */ + with a constant length and step. */ poly_uint64 seg_len; if (!operand_equal_p (dr_a.seg_len, dr_b.seg_len, 0) || !poly_int_tree_p (dr_a.seg_len, &seg_len) diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c index 5561ea6..afff0ec 100644 --- a/gcc/tree-sra.c +++ b/gcc/tree-sra.c @@ -2142,7 +2142,7 @@ sort_and_splice_var_accesses (tree var) /* Create a variable for the given ACCESS which determines the type, name and a few other properties. Return the variable declaration and store it also to ACCESS->replacement. REG_TREE is used when creating a declaration to base a - default-definition SSA name on on in order to facilitate an uninitialized + default-definition SSA name on in order to facilitate an uninitialized warning. It is used instead of the actual ACCESS type if that is not of a gimple register type. */ diff --git a/gcc/tree-ssa-dom.c b/gcc/tree-ssa-dom.c index eea494c..ee848fe 100644 --- a/gcc/tree-ssa-dom.c +++ b/gcc/tree-ssa-dom.c @@ -875,7 +875,7 @@ simplify_stmt_for_jump_threading (gimple *stmt, class avail_exprs_stack *avail_exprs_stack, basic_block bb ATTRIBUTE_UNUSED) { - /* First query our hash table to see if the the expression is available + /* First query our hash table to see if the expression is available there. A non-NULL return value will be either a constant or another SSA_NAME. */ tree cached_lhs = avail_exprs_stack->lookup_avail_expr (stmt, false, true); diff --git a/gcc/tree-ssa-dse.c b/gcc/tree-ssa-dse.c index 3ab15e2..cc93f55 100644 --- a/gcc/tree-ssa-dse.c +++ b/gcc/tree-ssa-dse.c @@ -88,7 +88,7 @@ static bitmap need_eh_cleanup; /* STMT is a statement that may write into memory. Analyze it and initialize WRITE to describe how STMT affects memory. - Return TRUE if the the statement was analyzed, FALSE otherwise. + Return TRUE if the statement was analyzed, FALSE otherwise. It is always safe to return FALSE. But typically better optimziation can be achieved by analyzing more statements. */ @@ -147,7 +147,7 @@ initialize_ao_ref_for_dse (gimple *stmt, ao_ref *write) return false; } -/* Given REF from the the alias oracle, return TRUE if it is a valid +/* Given REF from the alias oracle, return TRUE if it is a valid memory reference for dead store elimination, false otherwise. In particular, the reference must have a known base, known maximum diff --git a/gcc/tree-ssa-loop-split.c b/gcc/tree-ssa-loop-split.c index a74328c..7de95b5 100644 --- a/gcc/tree-ssa-loop-split.c +++ b/gcc/tree-ssa-loop-split.c @@ -770,7 +770,7 @@ find_vdef_in_loop (struct loop *loop) /* Non-pure call statement is conservatively assumed to impact all memory locations. So place call statements ahead of other memory - stores in the vector with an idea of of using them as shortcut + stores in the vector with an idea of using them as shortcut terminators to memory alias analysis. */ if (gimple_code (stmt) == GIMPLE_CALL) info->memory_stores.safe_push (stmt); diff --git a/gcc/tree-ssa-math-opts.c b/gcc/tree-ssa-math-opts.c index daefa64..54ba035 100644 --- a/gcc/tree-ssa-math-opts.c +++ b/gcc/tree-ssa-math-opts.c @@ -2477,7 +2477,7 @@ is_copysign_call_with_1 (gimple *call) } /* Try to expand the pattern x * copysign (1, y) into xorsign (x, y). - This only happens when the the xorsign optab is defined, if the + This only happens when the xorsign optab is defined, if the pattern is not a xorsign pattern or if expansion fails FALSE is returned, otherwise TRUE is returned. */ static bool diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c index 79871a8..14f9550 100644 --- a/gcc/tree-ssa-reassoc.c +++ b/gcc/tree-ssa-reassoc.c @@ -6373,7 +6373,7 @@ reassociate_bb (basic_block bb) int width; /* For binary bit operations, if there are at least 3 - operands and the last last operand in OPS is a constant, + operands and the last operand in OPS is a constant, move it to the front. This helps ensure that we generate (X & Y) & C rather than (X & C) & Y. The former will often match a canonical bit test when we get to RTL. */ diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index 7fcc610..df4c1b6 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -4381,7 +4381,7 @@ handle_builtin_string_cmp (gimple_stmt_iterator *gsi, const vr_values *rvals) int idx1 = get_stridx (arg1); int idx2 = get_stridx (arg2); - /* For strncmp set to the the value of the third argument if known. */ + /* For strncmp set to the value of the third argument if known. */ HOST_WIDE_INT bound = -1; tree len = NULL_TREE; /* Extract the strncmp bound. */ @@ -4965,7 +4965,7 @@ handle_store (gimple_stmt_iterator *gsi, bool *zero_write, tree ssaname = NULL_TREE, lhs = gimple_assign_lhs (stmt); tree rhs = gimple_assign_rhs1 (stmt); - /* The offset of the first byte in LHS modified by the the store. */ + /* The offset of the first byte in LHS modified by the store. */ unsigned HOST_WIDE_INT offset = 0; if (TREE_CODE (lhs) == MEM_REF diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index 53fccb7..73e092c 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -6541,7 +6541,7 @@ vectorizable_reduction (stmt_vec_info stmt_info, slp_tree slp_node, } /* The epilogue code relies on the number of elements being a multiple of the group size. The duplicate-and-interleave approach to setting - up the the initial vector does too. */ + up the initial vector does too. */ if (!multiple_p (nunits_out, group_size)) { if (dump_enabled_p ()) diff --git a/gcc/tree.c b/gcc/tree.c index 905563f..ee45193 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -13663,7 +13663,7 @@ component_ref_size (tree ref, bool *interior_zero_length /* = NULL */) } /* BASE is the declared object of which MEMBER is either a member - or that is is cast to REFTYPE (e.g., a char buffer used to store + or that is cast to REFTYPE (e.g., a char buffer used to store a REFTYPE object). */ tree reftype = TREE_TYPE (TREE_OPERAND (ref, 0)); tree basetype = TREE_TYPE (base); diff --git a/gcc/tree.def b/gcc/tree.def index 591b06b..6c53fe1 100644 --- a/gcc/tree.def +++ b/gcc/tree.def @@ -970,7 +970,7 @@ DEFTREECODE (SWITCH_EXPR, "switch_expr", tcc_statement, 2) is a 'default' label. Operand 1 is CASE_HIGH. If it is NULL_TREE, the label is a simple (one-value) case label. If it is non-NULL_TREE, the case is a range. - Operand 2 is CASE_LABEL, which is is the corresponding LABEL_DECL. + Operand 2 is CASE_LABEL, which has the corresponding LABEL_DECL. Operand 3 is CASE_CHAIN. This operand is only used in tree-cfg.c to speed up the lookup of case labels which use a particular edge in the control flow graph. */ -- cgit v1.1 From 6df4618cac91499f411673b33a516a5310cfbf79 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 12:23:42 +0000 Subject: [ARM][GCC][3/1x]: MVE intrinsics with unary operand. This patch supports following MVE ACLE intrinsics with unary operand. vdupq_n_s8, vdupq_n_s16, vdupq_n_s32, vabsq_s8, vabsq_s16, vabsq_s32, vclsq_s8, vclsq_s16, vclsq_s32, vclzq_s8, vclzq_s16, vclzq_s32, vnegq_s8, vnegq_s16, vnegq_s32, vaddlvq_s32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vmovlbq_s8, vmovlbq_s16, vmovltq_s8, vmovltq_s16, vmvnq_s8, vmvnq_s16, vmvnq_s32, vrev16q_s8, vrev32q_s8, vrev32q_s16, vqabsq_s8, vqabsq_s16, vqabsq_s32, vqnegq_s8, vqnegq_s16, vqnegq_s32, vcvtaq_s16_f16, vcvtaq_s32_f32, vcvtnq_s16_f16, vcvtnq_s32_f32, vcvtpq_s16_f16, vcvtpq_s32_f32, vcvtmq_s16_f16, vcvtmq_s32_f32, vmvnq_u8, vmvnq_u16, vmvnq_u32, vdupq_n_u8, vdupq_n_u16, vdupq_n_u32, vclzq_u8, vclzq_u16, vclzq_u32, vaddvq_u8, vaddvq_u16, vaddvq_u32, vrev32q_u8, vrev32q_u16, vmovltq_u8, vmovltq_u16, vmovlbq_u8, vmovlbq_u16, vrev16q_u8, vaddlvq_u32, vcvtpq_u16_f16, vcvtpq_u32_f32, vcvtnq_u16_f16, vcvtmq_u16_f16, vcvtmq_u32_f32, vcvtaq_u16_f16, vcvtaq_u32_f32, vdupq_n, vabsq, vclsq, vclzq, vnegq, vaddlvq, vaddvq, vmovlbq, vmovltq, vmvnq, vrev16q, vrev32q, vqabsq, vqnegq. A new register class "EVEN_REGS" which allows only even registers is added in this patch. The new constraint "e" allows only reigsters of EVEN_REGS class. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. * config/arm/arm_mve.h (vdupq_n_s8): Define macro. (vdupq_n_s16): Likewise. (vdupq_n_s32): Likewise. (vabsq_s8): Likewise. (vabsq_s16): Likewise. (vabsq_s32): Likewise. (vclsq_s8): Likewise. (vclsq_s16): Likewise. (vclsq_s32): Likewise. (vclzq_s8): Likewise. (vclzq_s16): Likewise. (vclzq_s32): Likewise. (vnegq_s8): Likewise. (vnegq_s16): Likewise. (vnegq_s32): Likewise. (vaddlvq_s32): Likewise. (vaddvq_s8): Likewise. (vaddvq_s16): Likewise. (vaddvq_s32): Likewise. (vmovlbq_s8): Likewise. (vmovlbq_s16): Likewise. (vmovltq_s8): Likewise. (vmovltq_s16): Likewise. (vmvnq_s8): Likewise. (vmvnq_s16): Likewise. (vmvnq_s32): Likewise. (vrev16q_s8): Likewise. (vrev32q_s8): Likewise. (vrev32q_s16): Likewise. (vqabsq_s8): Likewise. (vqabsq_s16): Likewise. (vqabsq_s32): Likewise. (vqnegq_s8): Likewise. (vqnegq_s16): Likewise. (vqnegq_s32): Likewise. (vcvtaq_s16_f16): Likewise. (vcvtaq_s32_f32): Likewise. (vcvtnq_s16_f16): Likewise. (vcvtnq_s32_f32): Likewise. (vcvtpq_s16_f16): Likewise. (vcvtpq_s32_f32): Likewise. (vcvtmq_s16_f16): Likewise. (vcvtmq_s32_f32): Likewise. (vmvnq_u8): Likewise. (vmvnq_u16): Likewise. (vmvnq_u32): Likewise. (vdupq_n_u8): Likewise. (vdupq_n_u16): Likewise. (vdupq_n_u32): Likewise. (vclzq_u8): Likewise. (vclzq_u16): Likewise. (vclzq_u32): Likewise. (vaddvq_u8): Likewise. (vaddvq_u16): Likewise. (vaddvq_u32): Likewise. (vrev32q_u8): Likewise. (vrev32q_u16): Likewise. (vmovltq_u8): Likewise. (vmovltq_u16): Likewise. (vmovlbq_u8): Likewise. (vmovlbq_u16): Likewise. (vrev16q_u8): Likewise. (vaddlvq_u32): Likewise. (vcvtpq_u16_f16): Likewise. (vcvtpq_u32_f32): Likewise. (vcvtnq_u16_f16): Likewise. (vcvtmq_u16_f16): Likewise. (vcvtmq_u32_f32): Likewise. (vcvtaq_u16_f16): Likewise. (vcvtaq_u32_f32): Likewise. (__arm_vdupq_n_s8): Define intrinsic. (__arm_vdupq_n_s16): Likewise. (__arm_vdupq_n_s32): Likewise. (__arm_vabsq_s8): Likewise. (__arm_vabsq_s16): Likewise. (__arm_vabsq_s32): Likewise. (__arm_vclsq_s8): Likewise. (__arm_vclsq_s16): Likewise. (__arm_vclsq_s32): Likewise. (__arm_vclzq_s8): Likewise. (__arm_vclzq_s16): Likewise. (__arm_vclzq_s32): Likewise. (__arm_vnegq_s8): Likewise. (__arm_vnegq_s16): Likewise. (__arm_vnegq_s32): Likewise. (__arm_vaddlvq_s32): Likewise. (__arm_vaddvq_s8): Likewise. (__arm_vaddvq_s16): Likewise. (__arm_vaddvq_s32): Likewise. (__arm_vmovlbq_s8): Likewise. (__arm_vmovlbq_s16): Likewise. (__arm_vmovltq_s8): Likewise. (__arm_vmovltq_s16): Likewise. (__arm_vmvnq_s8): Likewise. (__arm_vmvnq_s16): Likewise. (__arm_vmvnq_s32): Likewise. (__arm_vrev16q_s8): Likewise. (__arm_vrev32q_s8): Likewise. (__arm_vrev32q_s16): Likewise. (__arm_vqabsq_s8): Likewise. (__arm_vqabsq_s16): Likewise. (__arm_vqabsq_s32): Likewise. (__arm_vqnegq_s8): Likewise. (__arm_vqnegq_s16): Likewise. (__arm_vqnegq_s32): Likewise. (__arm_vmvnq_u8): Likewise. (__arm_vmvnq_u16): Likewise. (__arm_vmvnq_u32): Likewise. (__arm_vdupq_n_u8): Likewise. (__arm_vdupq_n_u16): Likewise. (__arm_vdupq_n_u32): Likewise. (__arm_vclzq_u8): Likewise. (__arm_vclzq_u16): Likewise. (__arm_vclzq_u32): Likewise. (__arm_vaddvq_u8): Likewise. (__arm_vaddvq_u16): Likewise. (__arm_vaddvq_u32): Likewise. (__arm_vrev32q_u8): Likewise. (__arm_vrev32q_u16): Likewise. (__arm_vmovltq_u8): Likewise. (__arm_vmovltq_u16): Likewise. (__arm_vmovlbq_u8): Likewise. (__arm_vmovlbq_u16): Likewise. (__arm_vrev16q_u8): Likewise. (__arm_vaddlvq_u32): Likewise. (__arm_vcvtpq_u16_f16): Likewise. (__arm_vcvtpq_u32_f32): Likewise. (__arm_vcvtnq_u16_f16): Likewise. (__arm_vcvtmq_u16_f16): Likewise. (__arm_vcvtmq_u32_f32): Likewise. (__arm_vcvtaq_u16_f16): Likewise. (__arm_vcvtaq_u32_f32): Likewise. (__arm_vcvtaq_s16_f16): Likewise. (__arm_vcvtaq_s32_f32): Likewise. (__arm_vcvtnq_s16_f16): Likewise. (__arm_vcvtnq_s32_f32): Likewise. (__arm_vcvtpq_s16_f16): Likewise. (__arm_vcvtpq_s32_f32): Likewise. (__arm_vcvtmq_s16_f16): Likewise. (__arm_vcvtmq_s32_f32): Likewise. (vdupq_n): Define polymorphic variant. (vabsq): Likewise. (vclsq): Likewise. (vclzq): Likewise. (vnegq): Likewise. (vaddlvq): Likewise. (vaddvq): Likewise. (vmovlbq): Likewise. (vmovltq): Likewise. (vmvnq): Likewise. (vrev16q): Likewise. (vrev32q): Likewise. (vqabsq): Likewise. (vqnegq): Likewise. * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. (UNOP_SNONE_NONE): Likewise. (UNOP_UNONE_UNONE): Likewise. (UNOP_UNONE_NONE): Likewise. * config/arm/constraints.md (e): Define new constriant to allow only even registers. * config/arm/mve.md (mve_vqabsq_s): Define RTL pattern. (mve_vnegq_s): Likewise. (mve_vmvnq_): Likewise. (mve_vdupq_n_): Likewise. (mve_vclzq_): Likewise. (mve_vclsq_s): Likewise. (mve_vaddvq_): Likewise. (mve_vabsq_s): Likewise. (mve_vrev32q_): Likewise. (mve_vmovltq_): Likewise. (mve_vmovlbq_): Likewise. (mve_vcvtpq_): Likewise. (mve_vcvtnq_): Likewise. (mve_vcvtmq_): Likewise. (mve_vcvtaq_): Likewise. (mve_vrev16q_v16qi): Likewise. (mve_vaddlvq_v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. --- gcc/ChangeLog | 183 +++++ gcc/config/arm/arm.h | 3 + gcc/config/arm/arm_mve.h | 740 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 31 + gcc/config/arm/constraints.md | 4 + gcc/config/arm/mve.md | 291 +++++++- gcc/testsuite/ChangeLog | 75 +++ .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 2 +- 79 files changed, 2695 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98fc289..8f7b261 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,186 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. + * config/arm/arm_mve.h (vdupq_n_s8): Define macro. + (vdupq_n_s16): Likewise. + (vdupq_n_s32): Likewise. + (vabsq_s8): Likewise. + (vabsq_s16): Likewise. + (vabsq_s32): Likewise. + (vclsq_s8): Likewise. + (vclsq_s16): Likewise. + (vclsq_s32): Likewise. + (vclzq_s8): Likewise. + (vclzq_s16): Likewise. + (vclzq_s32): Likewise. + (vnegq_s8): Likewise. + (vnegq_s16): Likewise. + (vnegq_s32): Likewise. + (vaddlvq_s32): Likewise. + (vaddvq_s8): Likewise. + (vaddvq_s16): Likewise. + (vaddvq_s32): Likewise. + (vmovlbq_s8): Likewise. + (vmovlbq_s16): Likewise. + (vmovltq_s8): Likewise. + (vmovltq_s16): Likewise. + (vmvnq_s8): Likewise. + (vmvnq_s16): Likewise. + (vmvnq_s32): Likewise. + (vrev16q_s8): Likewise. + (vrev32q_s8): Likewise. + (vrev32q_s16): Likewise. + (vqabsq_s8): Likewise. + (vqabsq_s16): Likewise. + (vqabsq_s32): Likewise. + (vqnegq_s8): Likewise. + (vqnegq_s16): Likewise. + (vqnegq_s32): Likewise. + (vcvtaq_s16_f16): Likewise. + (vcvtaq_s32_f32): Likewise. + (vcvtnq_s16_f16): Likewise. + (vcvtnq_s32_f32): Likewise. + (vcvtpq_s16_f16): Likewise. + (vcvtpq_s32_f32): Likewise. + (vcvtmq_s16_f16): Likewise. + (vcvtmq_s32_f32): Likewise. + (vmvnq_u8): Likewise. + (vmvnq_u16): Likewise. + (vmvnq_u32): Likewise. + (vdupq_n_u8): Likewise. + (vdupq_n_u16): Likewise. + (vdupq_n_u32): Likewise. + (vclzq_u8): Likewise. + (vclzq_u16): Likewise. + (vclzq_u32): Likewise. + (vaddvq_u8): Likewise. + (vaddvq_u16): Likewise. + (vaddvq_u32): Likewise. + (vrev32q_u8): Likewise. + (vrev32q_u16): Likewise. + (vmovltq_u8): Likewise. + (vmovltq_u16): Likewise. + (vmovlbq_u8): Likewise. + (vmovlbq_u16): Likewise. + (vrev16q_u8): Likewise. + (vaddlvq_u32): Likewise. + (vcvtpq_u16_f16): Likewise. + (vcvtpq_u32_f32): Likewise. + (vcvtnq_u16_f16): Likewise. + (vcvtmq_u16_f16): Likewise. + (vcvtmq_u32_f32): Likewise. + (vcvtaq_u16_f16): Likewise. + (vcvtaq_u32_f32): Likewise. + (__arm_vdupq_n_s8): Define intrinsic. + (__arm_vdupq_n_s16): Likewise. + (__arm_vdupq_n_s32): Likewise. + (__arm_vabsq_s8): Likewise. + (__arm_vabsq_s16): Likewise. + (__arm_vabsq_s32): Likewise. + (__arm_vclsq_s8): Likewise. + (__arm_vclsq_s16): Likewise. + (__arm_vclsq_s32): Likewise. + (__arm_vclzq_s8): Likewise. + (__arm_vclzq_s16): Likewise. + (__arm_vclzq_s32): Likewise. + (__arm_vnegq_s8): Likewise. + (__arm_vnegq_s16): Likewise. + (__arm_vnegq_s32): Likewise. + (__arm_vaddlvq_s32): Likewise. + (__arm_vaddvq_s8): Likewise. + (__arm_vaddvq_s16): Likewise. + (__arm_vaddvq_s32): Likewise. + (__arm_vmovlbq_s8): Likewise. + (__arm_vmovlbq_s16): Likewise. + (__arm_vmovltq_s8): Likewise. + (__arm_vmovltq_s16): Likewise. + (__arm_vmvnq_s8): Likewise. + (__arm_vmvnq_s16): Likewise. + (__arm_vmvnq_s32): Likewise. + (__arm_vrev16q_s8): Likewise. + (__arm_vrev32q_s8): Likewise. + (__arm_vrev32q_s16): Likewise. + (__arm_vqabsq_s8): Likewise. + (__arm_vqabsq_s16): Likewise. + (__arm_vqabsq_s32): Likewise. + (__arm_vqnegq_s8): Likewise. + (__arm_vqnegq_s16): Likewise. + (__arm_vqnegq_s32): Likewise. + (__arm_vmvnq_u8): Likewise. + (__arm_vmvnq_u16): Likewise. + (__arm_vmvnq_u32): Likewise. + (__arm_vdupq_n_u8): Likewise. + (__arm_vdupq_n_u16): Likewise. + (__arm_vdupq_n_u32): Likewise. + (__arm_vclzq_u8): Likewise. + (__arm_vclzq_u16): Likewise. + (__arm_vclzq_u32): Likewise. + (__arm_vaddvq_u8): Likewise. + (__arm_vaddvq_u16): Likewise. + (__arm_vaddvq_u32): Likewise. + (__arm_vrev32q_u8): Likewise. + (__arm_vrev32q_u16): Likewise. + (__arm_vmovltq_u8): Likewise. + (__arm_vmovltq_u16): Likewise. + (__arm_vmovlbq_u8): Likewise. + (__arm_vmovlbq_u16): Likewise. + (__arm_vrev16q_u8): Likewise. + (__arm_vaddlvq_u32): Likewise. + (__arm_vcvtpq_u16_f16): Likewise. + (__arm_vcvtpq_u32_f32): Likewise. + (__arm_vcvtnq_u16_f16): Likewise. + (__arm_vcvtmq_u16_f16): Likewise. + (__arm_vcvtmq_u32_f32): Likewise. + (__arm_vcvtaq_u16_f16): Likewise. + (__arm_vcvtaq_u32_f32): Likewise. + (__arm_vcvtaq_s16_f16): Likewise. + (__arm_vcvtaq_s32_f32): Likewise. + (__arm_vcvtnq_s16_f16): Likewise. + (__arm_vcvtnq_s32_f32): Likewise. + (__arm_vcvtpq_s16_f16): Likewise. + (__arm_vcvtpq_s32_f32): Likewise. + (__arm_vcvtmq_s16_f16): Likewise. + (__arm_vcvtmq_s32_f32): Likewise. + (vdupq_n): Define polymorphic variant. + (vabsq): Likewise. + (vclsq): Likewise. + (vclzq): Likewise. + (vnegq): Likewise. + (vaddlvq): Likewise. + (vaddvq): Likewise. + (vmovlbq): Likewise. + (vmovltq): Likewise. + (vmvnq): Likewise. + (vrev16q): Likewise. + (vrev32q): Likewise. + (vqabsq): Likewise. + (vqnegq): Likewise. + * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. + (UNOP_SNONE_NONE): Likewise. + (UNOP_UNONE_UNONE): Likewise. + (UNOP_UNONE_NONE): Likewise. + * config/arm/constraints.md (e): Define new constriant to allow only + even registers. + * config/arm/mve.md (mve_vqabsq_s): Define RTL pattern. + (mve_vnegq_s): Likewise. + (mve_vmvnq_): Likewise. + (mve_vdupq_n_): Likewise. + (mve_vclzq_): Likewise. + (mve_vclsq_s): Likewise. + (mve_vaddvq_): Likewise. + (mve_vabsq_s): Likewise. + (mve_vrev32q_): Likewise. + (mve_vmovltq_): Likewise. + (mve_vmovlbq_): Likewise. + (mve_vcvtpq_): Likewise. + (mve_vcvtnq_): Likewise. + (mve_vcvtmq_): Likewise. + (mve_vcvtaq_): Likewise. + (mve_vrev16q_v16qi): Likewise. + (mve_vaddlvq_v4si): Likewise. + 2020-03-17 Jakub Jelinek * lra-spills.c (remove_pseudos): Fix up duplicated word issue in diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c745341..fb55f73 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1167,6 +1167,7 @@ enum reg_class BASE_REGS, HI_REGS, CALLER_SAVE_REGS, + EVEN_REG, GENERAL_REGS, CORE_REGS, VFP_D0_D7_REGS, @@ -1195,6 +1196,7 @@ enum reg_class "BASE_REGS", \ "HI_REGS", \ "CALLER_SAVE_REGS", \ + "EVEN_REG", \ "GENERAL_REGS", \ "CORE_REGS", \ "VFP_D0_D7_REGS", \ @@ -1222,6 +1224,7 @@ enum reg_class { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 14dd417..912849f 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -108,20 +108,90 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) +#define vdupq_n_s8(__a) __arm_vdupq_n_s8(__a) +#define vdupq_n_s16(__a) __arm_vdupq_n_s16(__a) +#define vdupq_n_s32(__a) __arm_vdupq_n_s32(__a) +#define vabsq_s8(__a) __arm_vabsq_s8(__a) +#define vabsq_s16(__a) __arm_vabsq_s16(__a) +#define vabsq_s32(__a) __arm_vabsq_s32(__a) +#define vclsq_s8(__a) __arm_vclsq_s8(__a) +#define vclsq_s16(__a) __arm_vclsq_s16(__a) +#define vclsq_s32(__a) __arm_vclsq_s32(__a) +#define vclzq_s8(__a) __arm_vclzq_s8(__a) +#define vclzq_s16(__a) __arm_vclzq_s16(__a) +#define vclzq_s32(__a) __arm_vclzq_s32(__a) +#define vnegq_s8(__a) __arm_vnegq_s8(__a) +#define vnegq_s16(__a) __arm_vnegq_s16(__a) +#define vnegq_s32(__a) __arm_vnegq_s32(__a) +#define vaddlvq_s32(__a) __arm_vaddlvq_s32(__a) +#define vaddvq_s8(__a) __arm_vaddvq_s8(__a) +#define vaddvq_s16(__a) __arm_vaddvq_s16(__a) +#define vaddvq_s32(__a) __arm_vaddvq_s32(__a) +#define vmovlbq_s8(__a) __arm_vmovlbq_s8(__a) +#define vmovlbq_s16(__a) __arm_vmovlbq_s16(__a) +#define vmovltq_s8(__a) __arm_vmovltq_s8(__a) +#define vmovltq_s16(__a) __arm_vmovltq_s16(__a) +#define vmvnq_s8(__a) __arm_vmvnq_s8(__a) +#define vmvnq_s16(__a) __arm_vmvnq_s16(__a) +#define vmvnq_s32(__a) __arm_vmvnq_s32(__a) #define vmvnq_n_s16( __imm) __arm_vmvnq_n_s16( __imm) #define vmvnq_n_s32( __imm) __arm_vmvnq_n_s32( __imm) +#define vrev16q_s8(__a) __arm_vrev16q_s8(__a) +#define vrev32q_s8(__a) __arm_vrev32q_s8(__a) +#define vrev32q_s16(__a) __arm_vrev32q_s16(__a) #define vrev64q_s8(__a) __arm_vrev64q_s8(__a) #define vrev64q_s16(__a) __arm_vrev64q_s16(__a) #define vrev64q_s32(__a) __arm_vrev64q_s32(__a) +#define vqabsq_s8(__a) __arm_vqabsq_s8(__a) +#define vqabsq_s16(__a) __arm_vqabsq_s16(__a) +#define vqabsq_s32(__a) __arm_vqabsq_s32(__a) +#define vqnegq_s8(__a) __arm_vqnegq_s8(__a) +#define vqnegq_s16(__a) __arm_vqnegq_s16(__a) +#define vqnegq_s32(__a) __arm_vqnegq_s32(__a) +#define vcvtaq_s16_f16(__a) __arm_vcvtaq_s16_f16(__a) +#define vcvtaq_s32_f32(__a) __arm_vcvtaq_s32_f32(__a) +#define vcvtnq_s16_f16(__a) __arm_vcvtnq_s16_f16(__a) +#define vcvtnq_s32_f32(__a) __arm_vcvtnq_s32_f32(__a) +#define vcvtpq_s16_f16(__a) __arm_vcvtpq_s16_f16(__a) +#define vcvtpq_s32_f32(__a) __arm_vcvtpq_s32_f32(__a) +#define vcvtmq_s16_f16(__a) __arm_vcvtmq_s16_f16(__a) +#define vcvtmq_s32_f32(__a) __arm_vcvtmq_s32_f32(__a) #define vcvtq_s16_f16(__a) __arm_vcvtq_s16_f16(__a) #define vcvtq_s32_f32(__a) __arm_vcvtq_s32_f32(__a) #define vrev64q_u8(__a) __arm_vrev64q_u8(__a) #define vrev64q_u16(__a) __arm_vrev64q_u16(__a) #define vrev64q_u32(__a) __arm_vrev64q_u32(__a) +#define vmvnq_u8(__a) __arm_vmvnq_u8(__a) +#define vmvnq_u16(__a) __arm_vmvnq_u16(__a) +#define vmvnq_u32(__a) __arm_vmvnq_u32(__a) +#define vdupq_n_u8(__a) __arm_vdupq_n_u8(__a) +#define vdupq_n_u16(__a) __arm_vdupq_n_u16(__a) +#define vdupq_n_u32(__a) __arm_vdupq_n_u32(__a) +#define vclzq_u8(__a) __arm_vclzq_u8(__a) +#define vclzq_u16(__a) __arm_vclzq_u16(__a) +#define vclzq_u32(__a) __arm_vclzq_u32(__a) +#define vaddvq_u8(__a) __arm_vaddvq_u8(__a) +#define vaddvq_u16(__a) __arm_vaddvq_u16(__a) +#define vaddvq_u32(__a) __arm_vaddvq_u32(__a) +#define vrev32q_u8(__a) __arm_vrev32q_u8(__a) +#define vrev32q_u16(__a) __arm_vrev32q_u16(__a) +#define vmovltq_u8(__a) __arm_vmovltq_u8(__a) +#define vmovltq_u16(__a) __arm_vmovltq_u16(__a) +#define vmovlbq_u8(__a) __arm_vmovlbq_u8(__a) +#define vmovlbq_u16(__a) __arm_vmovlbq_u16(__a) #define vmvnq_n_u16( __imm) __arm_vmvnq_n_u16( __imm) #define vmvnq_n_u32( __imm) __arm_vmvnq_n_u32( __imm) +#define vrev16q_u8(__a) __arm_vrev16q_u8(__a) +#define vaddlvq_u32(__a) __arm_vaddlvq_u32(__a) #define vcvtq_u16_f16(__a) __arm_vcvtq_u16_f16(__a) #define vcvtq_u32_f32(__a) __arm_vcvtq_u32_f32(__a) +#define vcvtpq_u16_f16(__a) __arm_vcvtpq_u16_f16(__a) +#define vcvtpq_u32_f32(__a) __arm_vcvtpq_u32_f32(__a) +#define vcvtnq_u16_f16(__a) __arm_vcvtnq_u16_f16(__a) +#define vcvtmq_u16_f16(__a) __arm_vcvtmq_u16_f16(__a) +#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a) +#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a) +#define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a) #endif __extension__ extern __inline void @@ -178,6 +248,188 @@ __arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s8 (int8_t __a) +{ + return __builtin_mve_vdupq_n_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s16 (int16_t __a) +{ + return __builtin_mve_vdupq_n_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s32 (int32_t __a) +{ + return __builtin_mve_vdupq_n_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vabsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vabsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vabsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vclsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vclsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vclsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s8 (int8x16_t __a) +{ + return __builtin_mve_vclzq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s16 (int16x8_t __a) +{ + return __builtin_mve_vclzq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s32 (int32x4_t __a) +{ + return __builtin_mve_vclzq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s8 (int8x16_t __a) +{ + return __builtin_mve_vnegq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s16 (int16x8_t __a) +{ + return __builtin_mve_vnegq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s32 (int32x4_t __a) +{ + return __builtin_mve_vnegq_sv4si (__a); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_s32 (int32x4_t __a) +{ + return __builtin_mve_vaddlvq_sv4si (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s8 (int8x16_t __a) +{ + return __builtin_mve_vaddvq_sv16qi (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s16 (int16x8_t __a) +{ + return __builtin_mve_vaddvq_sv8hi (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s32 (int32x4_t __a) +{ + return __builtin_mve_vaddvq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmovlbq_sv16qi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmovlbq_sv8hi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmovltq_sv16qi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmovltq_sv8hi (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmvnq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmvnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s32 (int32x4_t __a) +{ + return __builtin_mve_vmvnq_sv4si (__a); +} + __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_n_s16 (const int16_t __imm) @@ -194,6 +446,27 @@ __arm_vmvnq_n_s32 (const int32_t __imm) __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev16q_s8 (int8x16_t __a) +{ + return __builtin_mve_vrev16q_sv16qi (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_s8 (int8x16_t __a) +{ + return __builtin_mve_vrev32q_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_s16 (int16x8_t __a) +{ + return __builtin_mve_vrev32q_sv8hi (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrev64q_s8 (int8x16_t __a) { return __builtin_mve_vrev64q_sv16qi (__a); @@ -213,6 +486,48 @@ __arm_vrev64q_s32 (int32x4_t __a) return __builtin_mve_vrev64q_sv4si (__a); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vqabsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vqabsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vqabsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s8 (int8x16_t __a) +{ + return __builtin_mve_vqnegq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s16 (int16x8_t __a) +{ + return __builtin_mve_vqnegq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s32 (int32x4_t __a) +{ + return __builtin_mve_vqnegq_sv4si (__a); +} + __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrev64q_u8 (uint8x16_t __a) @@ -234,6 +549,132 @@ __arm_vrev64q_u32 (uint32x4_t __a) return __builtin_mve_vrev64q_uv4si (__a); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmvnq_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmvnq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vmvnq_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u8 (uint8_t __a) +{ + return __builtin_mve_vdupq_n_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u16 (uint16_t __a) +{ + return __builtin_mve_vdupq_n_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u32 (uint32_t __a) +{ + return __builtin_mve_vdupq_n_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vclzq_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vclzq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vclzq_uv4si (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vaddvq_uv16qi (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vaddvq_uv8hi (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vaddvq_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_u8 (uint8x16_t __a) +{ + return __builtin_mve_vrev32q_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_u16 (uint16x8_t __a) +{ + return __builtin_mve_vrev32q_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmovltq_uv16qi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmovltq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmovlbq_uv16qi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmovlbq_uv8hi (__a); +} + __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_n_u16 (const int __imm) @@ -248,6 +689,20 @@ __arm_vmvnq_n_u32 (const int __imm) return __builtin_mve_vmvnq_n_uv4si (__imm); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev16q_u8 (uint8x16_t __a) +{ + return __builtin_mve_vrev16q_uv16qi (__a); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vaddlvq_uv4si (__a); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -485,6 +940,111 @@ __arm_vcvtq_u32_f32 (float32x4_t __a) return __builtin_mve_vcvtq_from_f_uv4si (__a); } +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_uv4si (__a); +} + + __extension__ extern __inline int16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtnq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_sv4si (__a); +} + #endif enum { @@ -735,24 +1295,40 @@ extern void *__ARM_undef; #define vrev64q(p0) __arm_vrev64q(p0) #define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vnegq(p0) __arm_vnegq(p0) #define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vabsq(p0) __arm_vabsq(p0) #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vrev32q(p0) __arm_vrev32q(p0) #define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) #define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) @@ -765,6 +1341,69 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + #define vcvtq(p0) __arm_vcvtq(p0) #define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -786,6 +1425,93 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vaddlvq(p0) __arm_vaddlvq(p0) +#define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddlvq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddlvq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vaddvq(p0) __arm_vaddvq(p0) +#define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vaddvq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vaddvq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddvq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vaddvq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vaddvq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddvq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + #define vrev64q(p0) __arm_vrev64q(p0) #define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -796,6 +1522,20 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index d325f36..44807d6 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -35,8 +35,39 @@ VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) +VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) +VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi) +VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si) VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) +VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) +VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) +VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index bf8f4ff..492dc96 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -49,6 +49,10 @@ (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS" "MVE FPCCR register") +(define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS" + "MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8}, + @code{r10}, @code{r12}, @code{r14}") + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index a58cfb2..dafdc1c 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -22,26 +22,55 @@ (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) +(define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F - VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S - VCVTQ_TO_F_U VMVNQ_N_S VMVNQ_N_U VREV64Q_S VREV64Q_U - VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S + VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S + VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U + VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S + VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S + VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S + VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S + VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U + VADDLVQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) -(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VMVNQ_N_S "s") - (VMVNQ_N_U "u") (VREV64Q_U "u") (VREV64Q_S "s") - (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")]) +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") + (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") + (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") + (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") + (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") + (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") + (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") + (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u") + (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s") + (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") + (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") + (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) +(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) +(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) +(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) +(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) +(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) +(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) +(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S]) +(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U]) +(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S]) +(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U]) +(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) +(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) +(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -362,6 +391,228 @@ "vcvt.%#.f%# %q0, %q1" [(set_attr "type" "mve_move") ]) +;; [vqnegq_s]) +;; +(define_insn "mve_vqnegq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VQNEGQ_S)) + ] + "TARGET_HAVE_MVE" + "vqneg.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqabsq_s]) +;; +(define_insn "mve_vqabsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VQABSQ_S)) + ] + "TARGET_HAVE_MVE" + "vqabs.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_s]) +;; +(define_insn "mve_vnegq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VNEGQ_S)) + ] + "TARGET_HAVE_MVE" + "vneg.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmvnq_u, vmvnq_s]) +;; +(define_insn "mve_vmvnq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VMVNQ)) + ] + "TARGET_HAVE_MVE" + "vmvn %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_u, vdupq_n_s]) +;; +(define_insn "mve_vdupq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand: 1 "s_register_operand" "r")] + VDUPQ_N)) + ] + "TARGET_HAVE_MVE" + "vdup.%# %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vclzq_u, vclzq_s]) +;; +(define_insn "mve_vclzq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VCLZQ)) + ] + "TARGET_HAVE_MVE" + "vclz.i%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vclsq_s]) +;; +(define_insn "mve_vclsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VCLSQ_S)) + ] + "TARGET_HAVE_MVE" + "vcls.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddvq_s, vaddvq_u]) +;; +(define_insn "mve_vaddvq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] + VADDVQ)) + ] + "TARGET_HAVE_MVE" + "vaddv.%#\t%0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_s]) +;; +(define_insn "mve_vabsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VABSQ_S)) + ] + "TARGET_HAVE_MVE" + "vabs.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_u, vrev32q_s]) +;; +(define_insn "mve_vrev32q_" + [ + (set (match_operand:MVE_3 0 "s_register_operand" "=w") + (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] + VREV32Q)) + ] + "TARGET_HAVE_MVE" + "vrev32.%#\t%q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovltq_u, vmovltq_s]) +;; +(define_insn "mve_vmovltq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")] + VMOVLTQ)) + ] + "TARGET_HAVE_MVE" + "vmovlt.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovlbq_s, vmovlbq_u]) +;; +(define_insn "mve_vmovlbq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")] + VMOVLBQ)) + ] + "TARGET_HAVE_MVE" + "vmovlb.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtpq_s, vcvtpq_u]) +;; +(define_insn "mve_vcvtpq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTPQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtp.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtnq_s, vcvtnq_u]) +;; +(define_insn "mve_vcvtnq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTNQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtn.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtmq_s, vcvtmq_u]) +;; +(define_insn "mve_vcvtmq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTMQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtm.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtaq_u, vcvtaq_s]) +;; +(define_insn "mve_vcvtaq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTAQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvta.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) ;; ;; [vmvnq_n_u, vmvnq_n_s]) @@ -376,3 +627,31 @@ "vmvn.i%# %q0, %1" [(set_attr "type" "mve_move") ]) + +;; +;; [vrev16q_u, vrev16q_s]) +;; +(define_insn "mve_vrev16q_v16qi" + [ + (set (match_operand:V16QI 0 "s_register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] + VREV16Q)) + ] + "TARGET_HAVE_MVE" + "vrev16.8 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddlvq_s vaddlvq_u]) +;; +(define_insn "mve_vaddlvq_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] + VADDLVQ)) + ] + "TARGET_HAVE_MVE" + "vaddlv.32 %Q0, %R0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index acf982f..b360cff 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,78 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. + 2020-03-17 Mihail Ionescu * gcc.target/arm/multilib.exp: Add new v8.1-M entry. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c new file mode 100644 index 0000000..e19f2a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vabsq_s16 (a); +} + +/* { dg-final { scan-assembler "vabs.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c new file mode 100644 index 0000000..b639df4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vabsq_s32 (a); +} + +/* { dg-final { scan-assembler "vabs.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c new file mode 100644 index 0000000..32a7a86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vabsq_s8 (a); +} + +/* { dg-final { scan-assembler "vabs.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c new file mode 100644 index 0000000..491034b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a) +{ + return vaddlvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.s32" } } */ + +int64_t +foo1 (int32x4_t a) +{ + return vaddlvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c new file mode 100644 index 0000000..40d064e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a) +{ + return vaddlvq_u32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.u32" } } */ + +uint64_t +foo1 (uint32x4_t a) +{ + return vaddlvq (a); +} + +/* { dg-final { scan-assembler "vaddlv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c new file mode 100644 index 0000000..3696e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a) +{ + return vaddvq_s16 (a); +} + +/* { dg-final { scan-assembler "vaddv.s16" } } */ + +int32_t +foo1 (int16x8_t a) +{ + return vaddvq_s16 (a); +} + +/* { dg-final { scan-assembler "vaddv.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c new file mode 100644 index 0000000..b41ec7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a) +{ + return vaddvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddv.s32" } } */ + +int32_t +foo1 (int32x4_t a) +{ + return vaddvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c new file mode 100644 index 0000000..4eeea53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a) +{ + return vaddvq_s8 (a); +} + +/* { dg-final { scan-assembler "vaddv.s8" } } */ + +int32_t +foo1 (int8x16_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c new file mode 100644 index 0000000..157e640 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint16x8_t a) +{ + return vaddvq_u16 (a); +} + +/* { dg-final { scan-assembler "vaddv.u16" } } */ + +uint32_t +foo1 (uint16x8_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c new file mode 100644 index 0000000..befca64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32x4_t a) +{ + return vaddvq_u32 (a); +} + +/* { dg-final { scan-assembler "vaddv.u32" } } */ + +uint32_t +foo1 (uint32x4_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c new file mode 100644 index 0000000..e6837f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint8x16_t a) +{ + return vaddvq_u8 (a); +} + +/* { dg-final { scan-assembler "vaddv.u8" } } */ + +uint32_t +foo1 (uint8x16_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c new file mode 100644 index 0000000..ab3981b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vclsq_s16 (a); +} + +/* { dg-final { scan-assembler "vcls.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c new file mode 100644 index 0000000..c02da23 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vclsq_s32 (a); +} + +/* { dg-final { scan-assembler "vcls.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c new file mode 100644 index 0000000..9f8d452 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vclsq_s8 (a); +} + +/* { dg-final { scan-assembler "vcls.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c new file mode 100644 index 0000000..4c9f64f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vclzq_s16 (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c new file mode 100644 index 0000000..9281b94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vclzq_s32 (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c new file mode 100644 index 0000000..4aa7d54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vclzq_s8 (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c new file mode 100644 index 0000000..e842b75 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vclzq_u16 (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c new file mode 100644 index 0000000..9178184 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vclzq_u32 (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c new file mode 100644 index 0000000..5726728 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vclzq_u8 (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c new file mode 100644 index 0000000..9fa6037 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtaq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvta.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c new file mode 100644 index 0000000..bdf00b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtaq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvta.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c new file mode 100644 index 0000000..ab27154 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtaq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvta.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c new file mode 100644 index 0000000..daf0ff0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtaq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvta.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c new file mode 100644 index 0000000..75134dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtmq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c new file mode 100644 index 0000000..b4066c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtmq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c new file mode 100644 index 0000000..a5842bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtmq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c new file mode 100644 index 0000000..03018e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtmq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c new file mode 100644 index 0000000..41b3157 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtnq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c new file mode 100644 index 0000000..db921d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtnq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c new file mode 100644 index 0000000..ac446cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtnq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c new file mode 100644 index 0000000..6c2c1fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtpq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c new file mode 100644 index 0000000..0b554b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtpq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c new file mode 100644 index 0000000..27dcb7d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtpq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c new file mode 100644 index 0000000..b3a75c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtpq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c new file mode 100644 index 0000000..8e5a3e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t a) +{ + return vdupq_n_s16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c new file mode 100644 index 0000000..71da142 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t a) +{ + return vdupq_n_s32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c new file mode 100644 index 0000000..d80138d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t a) +{ + return vdupq_n_s8 (a); +} + +/* { dg-final { scan-assembler "vdup.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c new file mode 100644 index 0000000..5fe7f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t a) +{ + return vdupq_n_u16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c new file mode 100644 index 0000000..65dab51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a) +{ + return vdupq_n_u32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c new file mode 100644 index 0000000..72e2009 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t a) +{ + return vdupq_n_u8 (a); +} + +/* { dg-final { scan-assembler "vdup.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c new file mode 100644 index 0000000..8c1a444 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vmovlbq_s16 (a); +} + +/* { dg-final { scan-assembler "vmovlb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c new file mode 100644 index 0000000..9ca36f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vmovlbq_s8 (a); +} + +/* { dg-final { scan-assembler "vmovlb.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c new file mode 100644 index 0000000..9b537bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vmovlbq_u16 (a); +} + +/* { dg-final { scan-assembler "vmovlb.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c new file mode 100644 index 0000000..ef9a6c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vmovlbq_u8 (a); +} + +/* { dg-final { scan-assembler "vmovlb.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c new file mode 100644 index 0000000..3bd5d37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vmovltq_s16 (a); +} + +/* { dg-final { scan-assembler "vmovlt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c new file mode 100644 index 0000000..2bd4b7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vmovltq_s8 (a); +} + +/* { dg-final { scan-assembler "vmovlt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c new file mode 100644 index 0000000..65eb459 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vmovltq_u16 (a); +} + +/* { dg-final { scan-assembler "vmovlt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c new file mode 100644 index 0000000..b4b9f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vmovltq_u8 (a); +} + +/* { dg-final { scan-assembler "vmovlt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c new file mode 100644 index 0000000..faa1258 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vmvnq_s16 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c new file mode 100644 index 0000000..739e919 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vmvnq_s32 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c new file mode 100644 index 0000000..51f0fbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vmvnq_s8 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c new file mode 100644 index 0000000..629d5df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vmvnq_u16 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c new file mode 100644 index 0000000..25573b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vmvnq_u32 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c new file mode 100644 index 0000000..5747d04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vmvnq_u8 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c new file mode 100644 index 0000000..75a8ded --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vnegq_s16 (a); +} + +/* { dg-final { scan-assembler "vneg.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c new file mode 100644 index 0000000..33c82c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vnegq_s32 (a); +} + +/* { dg-final { scan-assembler "vneg.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c new file mode 100644 index 0000000..21655a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vnegq_s8 (a); +} + +/* { dg-final { scan-assembler "vneg.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c new file mode 100644 index 0000000..2022ead --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vqabsq_s16 (a); +} + +/* { dg-final { scan-assembler "vqabs.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c new file mode 100644 index 0000000..a96bb0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vqabsq_s32 (a); +} + +/* { dg-final { scan-assembler "vqabs.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c new file mode 100644 index 0000000..7c2c4e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vqabsq_s8 (a); +} + +/* { dg-final { scan-assembler "vqabs.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c new file mode 100644 index 0000000..f0a8529 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vqnegq_s16 (a); +} + +/* { dg-final { scan-assembler "vqneg.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c new file mode 100644 index 0000000..76923a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vqnegq_s32 (a); +} + +/* { dg-final { scan-assembler "vqneg.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c new file mode 100644 index 0000000..7bdab5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vqnegq_s8 (a); +} + +/* { dg-final { scan-assembler "vqneg.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c new file mode 100644 index 0000000..ab62869 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrev16q_s8 (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrev16q (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c new file mode 100644 index 0000000..ea95db1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrev16q_u8 (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrev16q (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c new file mode 100644 index 0000000..1b339e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vrev32q_s16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c new file mode 100644 index 0000000..cb2f8a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrev32q_s8 (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c new file mode 100644 index 0000000..296482c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vrev32q_u16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c new file mode 100644 index 0000000..c70b278 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrev32q_u8 (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c index 35245ad..b2b6bd5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a) int16x8_t foo1 (int16x8_t a) { - return vrev64q_s16 (a); + return vrev64q (a); } /* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c index 2344423..e13f075 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a) int32x4_t foo1 (int32x4_t a) { - return vrev64q_s32 (a); + return vrev64q (a); } /* { dg-final { scan-assembler "vrev64.32" } } */ -- cgit v1.1 From a475f1534312a5672b5cc73356625b8dc42829df Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 14:21:50 +0000 Subject: [ARM][GCC][4/1x]: MVE intrinsics with unary operand. This patch supports following MVE ACLE intrinsics with unary operand. vctp16q, vctp32q, vctp64q, vctp8q, vpnot. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics There are few conflicts in defining the machine registers, resolved by re-ordering VPR_REGNUM, APSRQ_REGNUM and APSRGE_REGNUM. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (hi_UP): Define mode. * config/arm/arm.h (IS_VPR_REGNUM): Move. * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. (APSRQ_REGNUM): Modify. (APSRGE_REGNUM): Modify. * config/arm/arm_mve.h (vctp16q): Define macro. (vctp32q): Likewise. (vctp64q): Likewise. (vctp8q): Likewise. (vpnot): Likewise. (__arm_vctp16q): Define intrinsic. (__arm_vctp32q): Likewise. (__arm_vctp64q): Likewise. (__arm_vctp8q): Likewise. (__arm_vpnot): Likewise. * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin qualifier. * config/arm/mve.md (mve_vctpqhi): Define RTL pattern. (mve_vpnothi): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. --- gcc/ChangeLog | 24 +++++++++++++ gcc/config/arm/arm-builtins.c | 1 + gcc/config/arm/arm_mve.h | 40 ++++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 5 +++ gcc/config/arm/mve.md | 34 +++++++++++++++++- gcc/testsuite/ChangeLog | 10 ++++++ .../gcc.target/arm/mve/intrinsics/vctp16q.c | 22 ++++++++++++ .../gcc.target/arm/mve/intrinsics/vctp32q.c | 22 ++++++++++++ .../gcc.target/arm/mve/intrinsics/vctp64q.c | 22 ++++++++++++ .../gcc.target/arm/mve/intrinsics/vctp8q.c | 22 ++++++++++++ .../gcc.target/arm/mve/intrinsics/vpnot.c | 22 ++++++++++++ 11 files changed, 223 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f7b261..501484c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,30 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (hi_UP): Define mode. + * config/arm/arm.h (IS_VPR_REGNUM): Move. + * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. + (APSRQ_REGNUM): Modify. + (APSRGE_REGNUM): Modify. + * config/arm/arm_mve.h (vctp16q): Define macro. + (vctp32q): Likewise. + (vctp64q): Likewise. + (vctp8q): Likewise. + (vpnot): Likewise. + (__arm_vctp16q): Define intrinsic. + (__arm_vctp32q): Likewise. + (__arm_vctp64q): Likewise. + (__arm_vctp8q): Likewise. + (__arm_vpnot): Likewise. + * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin + qualifier. + * config/arm/mve.md (mve_vctpqhi): Define RTL pattern. + (mve_vpnothi): Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. * config/arm/arm_mve.h (vdupq_n_s8): Define macro. (vdupq_n_s16): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b8656b8..81d6546 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -415,6 +415,7 @@ arm_set_sat_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define hf_UP E_HFmode #define bf_UP E_BFmode #define si_UP E_SImode +#define hi_UP E_HImode #define void_UP E_VOIDmode #define sf_UP E_SFmode #define UP(X) X##_UP diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 912849f..7f94e11 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -192,6 +192,11 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a) #define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a) #define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a) +#define vctp16q(__a) __arm_vctp16q(__a) +#define vctp32q(__a) __arm_vctp32q(__a) +#define vctp64q(__a) __arm_vctp64q(__a) +#define vctp8q(__a) __arm_vctp8q(__a) +#define vpnot(__a) __arm_vpnot(__a) #endif __extension__ extern __inline void @@ -703,6 +708,41 @@ __arm_vaddlvq_u32 (uint32x4_t __a) return __builtin_mve_vaddlvq_uv4si (__a); } +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp16q (uint32_t __a) +{ + return __builtin_mve_vctp16qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp32q (uint32_t __a) +{ + return __builtin_mve_vctp32qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp64q (uint32_t __a) +{ + return __builtin_mve_vctp64qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp8q (uint32_t __a) +{ + return __builtin_mve_vctp8qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpnot (mve_pred16_t __a) +{ + return __builtin_mve_vpnothi (__a); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 44807d6..5d56969 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -71,3 +71,8 @@ VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) +VAR1 (UNOP_UNONE_UNONE, vctp16q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp32q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp64q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp8q, hi) +VAR1 (UNOP_UNONE_UNONE, vpnot, hi) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index dafdc1c..2f997e8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -36,7 +36,7 @@ VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U - VADDLVQ_U]) + VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -54,6 +54,9 @@ (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")]) +(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") + (VCTP64Q "64")]) + (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) @@ -71,6 +74,7 @@ (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) +(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -655,3 +659,31 @@ "vaddlv.32 %Q0, %R0, %q1" [(set_attr "type" "mve_move") ]) + +;; +;; [vctp8q vctp16q vctp32q vctp64q]) +;; +(define_insn "mve_vctpqhi" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")] + VCTPQ)) + ] + "TARGET_HAVE_MVE" + "vctp. %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vpnot]) +;; +(define_insn "mve_vpnothi" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")] + VPNOT)) + ] + "TARGET_HAVE_MVE" + "vpnot" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b360cff..de68c54 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,16 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. + * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c new file mode 100644 index 0000000..52a6b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp16q (a); +} + +/* { dg-final { scan-assembler "vctp.16" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp16q (a); +} + +/* { dg-final { scan-assembler "vctp.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c new file mode 100644 index 0000000..703518a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp32q (a); +} + +/* { dg-final { scan-assembler "vctp.32" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp32q (a); +} + +/* { dg-final { scan-assembler "vctp.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c new file mode 100644 index 0000000..2f83a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp64q (a); +} + +/* { dg-final { scan-assembler "vctp.64" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp64q (a); +} + +/* { dg-final { scan-assembler "vctp.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c new file mode 100644 index 0000000..ed696ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp8q (a); +} + +/* { dg-final { scan-assembler "vctp.8" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp8q (a); +} + +/* { dg-final { scan-assembler "vctp.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c new file mode 100644 index 0000000..7e08b1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (mve_pred16_t a) +{ + return vpnot (a); +} + +/* { dg-final { scan-assembler "vpnot" } } */ + +mve_pred16_t +foo1 (mve_pred16_t a) +{ + return vpnot (a); +} + +/* { dg-final { scan-assembler "vpnot" } } */ -- cgit v1.1 From 4be8cf77026b6cdcf9ab9cff6e70a75ea4bfaded Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 14:51:51 +0000 Subject: [ARM][GCC][1/2x]: MVE intrinsics with binary operands. This patch supports following MVE ACLE intrinsics with binary operand. vsubq_n_f16, vsubq_n_f32, vbrsrq_n_f16, vbrsrq_n_f32, vcvtq_n_f16_s16, vcvtq_n_f32_s32, vcvtq_n_f16_u16, vcvtq_n_f32_u32, vcreateq_f16, vcreateq_f32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch new constraint "Rd" is added, which checks the constant is with in the range of 1 to 16. Also a new predicate "mve_imm_16" is added, to check the the matching constraint Rd. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsubq_n_f16): Define macro. (vsubq_n_f32): Likewise. (vbrsrq_n_f16): Likewise. (vbrsrq_n_f32): Likewise. (vcvtq_n_f16_s16): Likewise. (vcvtq_n_f32_s32): Likewise. (vcvtq_n_f16_u16): Likewise. (vcvtq_n_f32_u32): Likewise. (vcreateq_f16): Likewise. (vcreateq_f32): Likewise. (__arm_vsubq_n_f16): Define intrinsic. (__arm_vsubq_n_f32): Likewise. (__arm_vbrsrq_n_f16): Likewise. (__arm_vbrsrq_n_f32): Likewise. (__arm_vcvtq_n_f16_s16): Likewise. (__arm_vcvtq_n_f32_s32): Likewise. (__arm_vcvtq_n_f16_u16): Likewise. (__arm_vcvtq_n_f32_u32): Likewise. (__arm_vcreateq_f16): Likewise. (__arm_vcreateq_f32): Likewise. (vsubq): Define polymorphic variant. (vbrsrq): Likewise. (vcvtq_n): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use it. (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. * config/arm/constraints.md (Rd): Define constraint to check constant is in the range of 1 to 16. * config/arm/mve.md (mve_vsubq_n_f): Define RTL pattern. mve_vbrsrq_n_f: Likewise. mve_vcvtq_n_to_f_: Likewise. mve_vcreateq_f: Likewise. * config/arm/predicates.md (mve_imm_16): Define predicate to check the matching constraint Rd. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test. * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. --- gcc/ChangeLog | 46 ++++++++++ gcc/config/arm/arm-builtins.c | 24 +++++ gcc/config/arm/arm_mve.h | 101 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 7 +- gcc/config/arm/constraints.md | 7 +- gcc/config/arm/mve.md | 67 +++++++++++++- gcc/config/arm/predicates.md | 4 + gcc/testsuite/ChangeLog | 15 +++ .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 22 +++++ .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 22 +++++ .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 14 +++ .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 22 +++++ .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 22 +++++ .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 22 +++++ .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 22 +++++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 22 +++++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 22 +++++ 18 files changed, 471 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 501484c..6cef738 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,52 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define + qualifier for binary operands. + (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. + (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vsubq_n_f16): Define macro. + (vsubq_n_f32): Likewise. + (vbrsrq_n_f16): Likewise. + (vbrsrq_n_f32): Likewise. + (vcvtq_n_f16_s16): Likewise. + (vcvtq_n_f32_s32): Likewise. + (vcvtq_n_f16_u16): Likewise. + (vcvtq_n_f32_u32): Likewise. + (vcreateq_f16): Likewise. + (vcreateq_f32): Likewise. + (__arm_vsubq_n_f16): Define intrinsic. + (__arm_vsubq_n_f32): Likewise. + (__arm_vbrsrq_n_f16): Likewise. + (__arm_vbrsrq_n_f32): Likewise. + (__arm_vcvtq_n_f16_s16): Likewise. + (__arm_vcvtq_n_f32_s32): Likewise. + (__arm_vcvtq_n_f16_u16): Likewise. + (__arm_vcvtq_n_f32_u32): Likewise. + (__arm_vcreateq_f16): Likewise. + (__arm_vcreateq_f32): Likewise. + (vsubq): Define polymorphic variant. + (vbrsrq): Likewise. + (vcvtq_n): Likewise. + * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use + it. + (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. + (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. + * config/arm/constraints.md (Rd): Define constraint to check constant is + in the range of 1 to 16. + * config/arm/mve.md (mve_vsubq_n_f): Define RTL pattern. + mve_vbrsrq_n_f: Likewise. + mve_vcvtq_n_to_f_: Likewise. + mve_vcreateq_f: Likewise. + * config/arm/predicates.md (mve_imm_16): Define predicate to check + the matching constraint Rd. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (hi_UP): Define mode. * config/arm/arm.h (IS_VPR_REGNUM): Move. * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 81d6546..00e81ac 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -373,6 +373,30 @@ arm_unop_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define UNOP_UNONE_IMM_QUALIFIERS \ (arm_unop_unone_imm_qualifiers) +static enum arm_type_qualifiers +arm_binop_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none }; +#define BINOP_NONE_NONE_NONE_QUALIFIERS \ + (arm_binop_none_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_binop_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_immediate }; +#define BINOP_NONE_NONE_IMM_QUALIFIERS \ + (arm_binop_none_none_imm_qualifiers) + +static enum arm_type_qualifiers +arm_binop_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_immediate }; +#define BINOP_NONE_UNONE_IMM_QUALIFIERS \ + (arm_binop_none_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_binop_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_unsigned }; +#define BINOP_NONE_UNONE_UNONE_QUALIFIERS \ + (arm_binop_none_unone_unone_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 7f94e11..acb71e4 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -197,6 +197,16 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vctp64q(__a) __arm_vctp64q(__a) #define vctp8q(__a) __arm_vctp8q(__a) #define vpnot(__a) __arm_vpnot(__a) +#define vsubq_n_f16(__a, __b) __arm_vsubq_n_f16(__a, __b) +#define vsubq_n_f32(__a, __b) __arm_vsubq_n_f32(__a, __b) +#define vbrsrq_n_f16(__a, __b) __arm_vbrsrq_n_f16(__a, __b) +#define vbrsrq_n_f32(__a, __b) __arm_vbrsrq_n_f32(__a, __b) +#define vcvtq_n_f16_s16(__a, __imm6) __arm_vcvtq_n_f16_s16(__a, __imm6) +#define vcvtq_n_f32_s32(__a, __imm6) __arm_vcvtq_n_f32_s32(__a, __imm6) +#define vcvtq_n_f16_u16(__a, __imm6) __arm_vcvtq_n_f16_u16(__a, __imm6) +#define vcvtq_n_f32_u32(__a, __imm6) __arm_vcvtq_n_f32_u32(__a, __imm6) +#define vcreateq_f16(__a, __b) __arm_vcreateq_f16(__a, __b) +#define vcreateq_f32(__a, __b) __arm_vcreateq_f32(__a, __b) #endif __extension__ extern __inline void @@ -1085,6 +1095,76 @@ __arm_vcvtmq_s32_f32 (float32x4_t __a) return __builtin_mve_vcvtmq_sv4si (__a); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vsubq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vsubq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv4sf (__a, __b); +} + #endif enum { @@ -1452,6 +1532,27 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vsubq(p0,p1) __arm_vsubq(p0,p1) +#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) +#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) + +#define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) +#define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_n_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_n_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 5d56969..1695fb2 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -6,7 +6,7 @@ GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your + by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT @@ -76,3 +76,8 @@ VAR1 (UNOP_UNONE_UNONE, vctp32q, hi) VAR1 (UNOP_UNONE_UNONE, vctp64q, hi) VAR1 (UNOP_UNONE_UNONE, vctp8q, hi) VAR1 (UNOP_UNONE_UNONE, vpnot, hi) +VAR2 (BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) +VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) +VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 492dc96..f92e4dc 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -34,7 +34,7 @@ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di, ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe -;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz +;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd ;; in all states: Pf, Pg ;; The following memory constraints have been used: @@ -53,6 +53,11 @@ "MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8}, @code{r10}, @code{r12}, @code{r14}") +(define_constraint "Rd" + "@internal In Thumb-2 state a constant in range 1 to 16" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16"))) + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 2f997e8..c0cd901 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -36,7 +36,9 @@ VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U - VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT]) + VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT + VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F + VSUBQ_N_F]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -52,7 +54,8 @@ (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s") (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") - (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")]) + (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") + (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64")]) @@ -75,6 +78,7 @@ (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) +(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -687,3 +691,62 @@ "vpnot" [(set_attr "type" "mve_move") ]) + +;; +;; [vsubq_n_f]) +;; +(define_insn "mve_vsubq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VSUBQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vsub.f %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vbrsrq_n_f]) +;; +(define_insn "mve_vbrsrq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:SI 2 "s_register_operand" "r")] + VBRSRQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vbrsr. %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) +;; +(define_insn "mve_vcvtq_n_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w") + (match_operand:SI 2 "mve_imm_16" "Rd")] + VCVTQ_N_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.f.\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; [vcreateq_f]) +;; +(define_insn "mve_vcreateq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") + (match_operand:DI 2 "s_register_operand" "r")] + VCREATEQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index fb12371..bb7462e 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -31,6 +31,10 @@ || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) +;; True for immediates in the range of 1 to 16 for MVE. +(define_predicate "mve_imm_16" + (match_test "satisfies_constraint_Rd (op)")) + ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns (define_predicate "guard_addr_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index de68c54..c3a4317 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,21 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c new file mode 100644 index 0000000..2be3c86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, int32_t b) +{ + return vbrsrq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ + +float16x8_t +foo1 (float16x8_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c new file mode 100644 index 0000000..3c00280 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, int32_t b) +{ + return vbrsrq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ + +float32x4_t +foo1 (float32x4_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c new file mode 100644 index 0000000..045f415 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c new file mode 100644 index 0000000..cc78738 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c new file mode 100644 index 0000000..7aea123 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a) +{ + return vcvtq_n_f16_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ + +float16x8_t +foo1 (int16x8_t a) +{ + return vcvtq_n (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c new file mode 100644 index 0000000..0985a60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a) +{ + return vcvtq_n_f16_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ + +float16x8_t +foo1 (uint16x8_t a) +{ + return vcvtq_n (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c new file mode 100644 index 0000000..8324e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a) +{ + return vcvtq_n_f32_s32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ + +float32x4_t +foo1 (int32x4_t a) +{ + return vcvtq_n (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c new file mode 100644 index 0000000..ea6125a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a) +{ + return vcvtq_n_f32_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ + +float32x4_t +foo1 (uint32x4_t a) +{ + return vcvtq_n (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c new file mode 100644 index 0000000..9ec4038 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b) +{ + return vsubq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c new file mode 100644 index 0000000..e5f8c64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b) +{ + return vsubq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.f32" } } */ -- cgit v1.1 From 887085be635101ae1fa16be8dcdbbe6b240b600b Mon Sep 17 00:00:00 2001 From: Ville Voutilainen Date: Tue, 17 Mar 2020 16:38:25 +0200 Subject: c++: Fix access checks for __is_assignable and __is_constructible gcc/ PR c++/94197 * cp/method.c (assignable_expr): Use cp_unevaluated. (is_xible_helper): Push a non-deferred access check for the stub objects created by assignable_expr and constructible_expr. testsuite/ PR c++/94197 * g++.dg/ext/pr94197.C: New. --- gcc/cp/ChangeLog | 14 ++++++++ gcc/cp/method.c | 4 +-- gcc/testsuite/g++.dg/ext/pr94197.C | 74 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ext/pr94197.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 15b3ccc..d2c062a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,17 @@ +2020-03-17 Ville Voutilainen + + gcc/ + + PR c++/94197 + * cp/method.c (assignable_expr): Use cp_unevaluated. + (is_xible_helper): Push a non-deferred access check for + the stub objects created by assignable_expr and constructible_expr. + + testsuite/ + + PR c++/94197 + * g++.dg/ext/pr94197.C: New. + 2020-03-17 Jakub Jelinek * pt.c (tsubst): Fix up duplicated word issue in a diagnostic message. diff --git a/gcc/cp/method.c b/gcc/cp/method.c index f10cfec..c131fd4 100644 --- a/gcc/cp/method.c +++ b/gcc/cp/method.c @@ -1739,11 +1739,10 @@ check_nontriv (tree *tp, int *, void *) static tree assignable_expr (tree to, tree from) { - ++cp_unevaluated_operand; + cp_unevaluated cp_uneval_guard; to = build_stub_object (to); from = build_stub_object (from); tree r = cp_build_modify_expr (input_location, to, NOP_EXPR, from, tf_none); - --cp_unevaluated_operand; return r; } @@ -1806,6 +1805,7 @@ constructible_expr (tree to, tree from) static tree is_xible_helper (enum tree_code code, tree to, tree from, bool trivial) { + deferring_access_check_sentinel acs (dk_no_deferred); if (VOID_TYPE_P (to) || ABSTRACT_CLASS_TYPE_P (to) || (from && FUNC_OR_METHOD_TYPE_P (from) && (TYPE_READONLY (from) || FUNCTION_REF_QUALIFIED (from)))) diff --git a/gcc/testsuite/g++.dg/ext/pr94197.C b/gcc/testsuite/g++.dg/ext/pr94197.C new file mode 100644 index 0000000..433a461 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/pr94197.C @@ -0,0 +1,74 @@ +// { dg-do compile { target c++11 } } + +template + T&& declval() noexcept; + +template +struct bool_constant +{ + static constexpr bool value = B; + using type = bool_constant; +}; + +using true_type = bool_constant; +using false_type = bool_constant; + +template + struct __is_nt_constructible_impl + : public false_type + { }; + +template + struct __is_nt_constructible_impl + : public bool_constant(declval()))> + { }; + +template + using __is_nothrow_constructible_impl + = __is_nt_constructible_impl<__is_constructible(T, Arg), T, Arg>; + +template + struct __is_nothrow_copy_constructible_impl + : public __is_nothrow_constructible_impl + { }; + +template + struct is_nothrow_copy_constructible + : public __is_nothrow_copy_constructible_impl::type + { }; + +template + struct __is_nt_assignable_impl + : public false_type + { }; + +template + struct __is_nt_assignable_impl + : public bool_constant() = declval())> + { }; + +template + using __is_nothrow_assignable_impl + = __is_nt_assignable_impl<__is_assignable(T, Arg), T, Arg>; + +template + struct __is_nothrow_copy_assignable_impl + : public __is_nothrow_assignable_impl + { }; + +template + struct is_nothrow_copy_assignable + : public __is_nothrow_copy_assignable_impl::type + { }; + +struct NType +{ + NType(); +private: + NType(const NType&); + NType& operator=(const NType&); +}; + + +static_assert( !is_nothrow_copy_constructible::value, "" ); +static_assert( !is_nothrow_copy_assignable::value, "" ); -- cgit v1.1 From f166a8cdf48bd0196cfcf91e5e8cd0e2b46409d8 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 15:08:47 +0000 Subject: [ARM][GCC][2/2x]: MVE intrinsics with binary operands. This patch supports following MVE ACLE intrinsics with binary operands. vcvtq_n_s16_f16, vcvtq_n_s32_f32, vcvtq_n_u16_f16, vcvtq_n_u32_f32, vcreateq_u8, vcreateq_u16, vcreateq_u32, vcreateq_u64, vcreateq_s8, vcreateq_s16, vcreateq_s32, vcreateq_s64, vshrq_n_s8, vshrq_n_s16, vshrq_n_s32, vshrq_n_u8, vshrq_n_u16, vshrq_n_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch new constraints "Rb" and "Rf" are added, which checks the constant is with in the range of 1 to 8 and 1 to 32 respectively. Also a new predicates "mve_imm_8" and "mve_imm_32" are added, to check the the matching constraint Rb and Rf respectively. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. (vcvtq_n_s32_f32): Likewise. (vcvtq_n_u16_f16): Likewise. (vcvtq_n_u32_f32): Likewise. (vcreateq_u8): Likewise. (vcreateq_u16): Likewise. (vcreateq_u32): Likewise. (vcreateq_u64): Likewise. (vcreateq_s8): Likewise. (vcreateq_s16): Likewise. (vcreateq_s32): Likewise. (vcreateq_s64): Likewise. (vshrq_n_s8): Likewise. (vshrq_n_s16): Likewise. (vshrq_n_s32): Likewise. (vshrq_n_u8): Likewise. (vshrq_n_u16): Likewise. (vshrq_n_u32): Likewise. (__arm_vcreateq_u8): Define intrinsic. (__arm_vcreateq_u16): Likewise. (__arm_vcreateq_u32): Likewise. (__arm_vcreateq_u64): Likewise. (__arm_vcreateq_s8): Likewise. (__arm_vcreateq_s16): Likewise. (__arm_vcreateq_s32): Likewise. (__arm_vcreateq_s64): Likewise. (__arm_vshrq_n_s8): Likewise. (__arm_vshrq_n_s16): Likewise. (__arm_vshrq_n_s32): Likewise. (__arm_vshrq_n_u8): Likewise. (__arm_vshrq_n_u16): Likewise. (__arm_vshrq_n_u32): Likewise. (__arm_vcvtq_n_s16_f16): Likewise. (__arm_vcvtq_n_s32_f32): Likewise. (__arm_vcvtq_n_u16_f16): Likewise. (__arm_vcvtq_n_u32_f32): Likewise. (vshrq_n): Define polymorphic variant. * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Use it. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/constraints.md (Rb): Define constraint to check constant is in the range of 1 to 8. (Rf): Define constraint to check constant is in the range of 1 to 32. * config/arm/mve.md (mve_vcreateq_): Define RTL pattern. (mve_vshrq_n_): Likewise. (mve_vcvtq_n_from_f_): Likewise. * config/arm/predicates.md (mve_imm_8): Define predicate to check the matching constraint Rb. (mve_imm_32): Define predicate to check the matching constraint Rf. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. --- gcc/ChangeLog | 59 ++++++++ gcc/config/arm/arm-builtins.c | 18 +++ gcc/config/arm/arm_mve.h | 154 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 8 +- gcc/config/arm/constraints.md | 12 +- gcc/config/arm/mve.md | 60 +++++++- gcc/config/arm/predicates.md | 8 ++ gcc/testsuite/ChangeLog | 23 +++ .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 14 ++ .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 14 ++ .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 14 ++ .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 14 ++ .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 22 +++ 26 files changed, 638 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6cef738..03312bd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,65 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define + qualifier for binary operands. + (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. + (vcvtq_n_s32_f32): Likewise. + (vcvtq_n_u16_f16): Likewise. + (vcvtq_n_u32_f32): Likewise. + (vcreateq_u8): Likewise. + (vcreateq_u16): Likewise. + (vcreateq_u32): Likewise. + (vcreateq_u64): Likewise. + (vcreateq_s8): Likewise. + (vcreateq_s16): Likewise. + (vcreateq_s32): Likewise. + (vcreateq_s64): Likewise. + (vshrq_n_s8): Likewise. + (vshrq_n_s16): Likewise. + (vshrq_n_s32): Likewise. + (vshrq_n_u8): Likewise. + (vshrq_n_u16): Likewise. + (vshrq_n_u32): Likewise. + (__arm_vcreateq_u8): Define intrinsic. + (__arm_vcreateq_u16): Likewise. + (__arm_vcreateq_u32): Likewise. + (__arm_vcreateq_u64): Likewise. + (__arm_vcreateq_s8): Likewise. + (__arm_vcreateq_s16): Likewise. + (__arm_vcreateq_s32): Likewise. + (__arm_vcreateq_s64): Likewise. + (__arm_vshrq_n_s8): Likewise. + (__arm_vshrq_n_s16): Likewise. + (__arm_vshrq_n_s32): Likewise. + (__arm_vshrq_n_u8): Likewise. + (__arm_vshrq_n_u16): Likewise. + (__arm_vshrq_n_u32): Likewise. + (__arm_vcvtq_n_s16_f16): Likewise. + (__arm_vcvtq_n_s32_f32): Likewise. + (__arm_vcvtq_n_u16_f16): Likewise. + (__arm_vcvtq_n_u32_f32): Likewise. + (vshrq_n): Define polymorphic variant. + * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): + Use it. + (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. + * config/arm/constraints.md (Rb): Define constraint to check constant is + in the range of 1 to 8. + (Rf): Define constraint to check constant is in the range of 1 to 32. + * config/arm/mve.md (mve_vcreateq_): Define RTL pattern. + (mve_vshrq_n_): Likewise. + (mve_vcvtq_n_from_f_): Likewise. + * config/arm/predicates.md (mve_imm_8): Define predicate to check + the matching constraint Rb. + (mve_imm_32): Define predicate to check the matching constraint Rf. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 00e81ac..066a046 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -397,6 +397,24 @@ arm_binop_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define BINOP_NONE_UNONE_UNONE_QUALIFIERS \ (arm_binop_none_unone_unone_qualifiers) +static enum arm_type_qualifiers +arm_binop_unone_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate }; +#define BINOP_UNONE_UNONE_IMM_QUALIFIERS \ + (arm_binop_unone_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned }; +#define BINOP_UNONE_UNONE_UNONE_QUALIFIERS \ + (arm_binop_unone_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none, qualifier_immediate }; +#define BINOP_UNONE_NONE_IMM_QUALIFIERS \ + (arm_binop_unone_none_imm_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index acb71e4..26787ba 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -207,6 +207,24 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtq_n_f32_u32(__a, __imm6) __arm_vcvtq_n_f32_u32(__a, __imm6) #define vcreateq_f16(__a, __b) __arm_vcreateq_f16(__a, __b) #define vcreateq_f32(__a, __b) __arm_vcreateq_f32(__a, __b) +#define vcvtq_n_s16_f16(__a, __imm6) __arm_vcvtq_n_s16_f16(__a, __imm6) +#define vcvtq_n_s32_f32(__a, __imm6) __arm_vcvtq_n_s32_f32(__a, __imm6) +#define vcvtq_n_u16_f16(__a, __imm6) __arm_vcvtq_n_u16_f16(__a, __imm6) +#define vcvtq_n_u32_f32(__a, __imm6) __arm_vcvtq_n_u32_f32(__a, __imm6) +#define vcreateq_u8(__a, __b) __arm_vcreateq_u8(__a, __b) +#define vcreateq_u16(__a, __b) __arm_vcreateq_u16(__a, __b) +#define vcreateq_u32(__a, __b) __arm_vcreateq_u32(__a, __b) +#define vcreateq_u64(__a, __b) __arm_vcreateq_u64(__a, __b) +#define vcreateq_s8(__a, __b) __arm_vcreateq_s8(__a, __b) +#define vcreateq_s16(__a, __b) __arm_vcreateq_s16(__a, __b) +#define vcreateq_s32(__a, __b) __arm_vcreateq_s32(__a, __b) +#define vcreateq_s64(__a, __b) __arm_vcreateq_s64(__a, __b) +#define vshrq_n_s8(__a, __imm) __arm_vshrq_n_s8(__a, __imm) +#define vshrq_n_s16(__a, __imm) __arm_vshrq_n_s16(__a, __imm) +#define vshrq_n_s32(__a, __imm) __arm_vshrq_n_s32(__a, __imm) +#define vshrq_n_u8(__a, __imm) __arm_vshrq_n_u8(__a, __imm) +#define vshrq_n_u16(__a, __imm) __arm_vshrq_n_u16(__a, __imm) +#define vshrq_n_u32(__a, __imm) __arm_vshrq_n_u32(__a, __imm) #endif __extension__ extern __inline void @@ -753,6 +771,104 @@ __arm_vpnot (mve_pred16_t __a) return __builtin_mve_vpnothi (__a); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u8 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv4si (__a, __b); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u64 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv2di (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s8 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv16qi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv4si (__a, __b); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s64 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv2di (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv4si (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u8 (uint8x16_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u16 (uint16x8_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u32 (uint32x4_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv4si (__a, __imm); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -1165,6 +1281,34 @@ __arm_vcreateq_f32 (uint64_t __a, uint64_t __b) return __builtin_mve_vcreateq_fv4sf (__a, __b); } +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); +} + #endif enum { @@ -1677,6 +1821,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vshrq(p0,p1) __arm_vshrq(p0,p1) +#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 1695fb2..b0a1e43 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -6,7 +6,7 @@ GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your + by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT @@ -81,3 +81,9 @@ VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) +VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) +VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) +VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index f92e4dc..e3e202c 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -34,7 +34,7 @@ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di, ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe -;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd +;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb ;; in all states: Pf, Pg ;; The following memory constraints have been used: @@ -58,6 +58,16 @@ (and (match_code "const_int") (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16"))) +(define_constraint "Rb" + "@internal In Thumb-2 state a constant in range 1 to 8" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8"))) + +(define_constraint "Rf" + "@internal In Thumb-2 state a constant in range 1 to 32" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32"))) + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index c0cd901..af8b654 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -22,6 +22,7 @@ (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) +(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI]) (define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) @@ -38,7 +39,8 @@ VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F - VSUBQ_N_F]) + VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U + VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -55,10 +57,16 @@ (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") - (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")]) + (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u") + (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") + (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") + (VCVTQ_N_FROM_F_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64")]) +(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") + (V4SI "mve_imm_32")]) +(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -79,6 +87,9 @@ (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) +(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) +(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) +(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -750,3 +761,48 @@ "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" [(set_attr "type" "mve_move") (set_attr "length""8")]) + +;; +;; [vcreateq_u, vcreateq_s]) +;; +(define_insn "mve_vcreateq_" + [ + (set (match_operand:MVE_1 0 "s_register_operand" "=w") + (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") + (match_operand:DI 2 "s_register_operand" "r")] + VCREATEQ)) + ] + "TARGET_HAVE_MVE" + "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshrq_n_s, vshrq_n_u]) +;; +(define_insn "mve_vshrq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "" "")] + VSHRQ_N)) + ] + "TARGET_HAVE_MVE" + "vshr.\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) +;; +(define_insn "mve_vcvtq_n_from_f_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w") + (match_operand:SI 2 "mve_imm_16" "Rd")] + VCVTQ_N_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt..f\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index bb7462e..2f5d5a7 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -35,6 +35,14 @@ (define_predicate "mve_imm_16" (match_test "satisfies_constraint_Rd (op)")) +;; True for immediates in the range of 1 to 8 for MVE. +(define_predicate "mve_imm_8" + (match_test "satisfies_constraint_Rb (op)")) + +;; True for immediates in the range of 1 to 32 for MVE. +(define_predicate "mve_imm_32" + (match_test "satisfies_constraint_Rf (op)")) + ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns (define_predicate "guard_addr_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c3a4317..fc581ef 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,29 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test. * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c new file mode 100644 index 0000000..e789a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c new file mode 100644 index 0000000..6983c7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c new file mode 100644 index 0000000..2016fad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s64 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c new file mode 100644 index 0000000..e6b36df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c new file mode 100644 index 0000000..bfb7f1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c new file mode 100644 index 0000000..2b1b193 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c new file mode 100644 index 0000000..e9b6dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u64 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c new file mode 100644 index 0000000..4a487a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c new file mode 100644 index 0000000..a220de3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtq_n_s16_f16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c new file mode 100644 index 0000000..4bb1525 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtq_n_s32_f32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c new file mode 100644 index 0000000..25d8b0d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtq_n_u16_f16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c new file mode 100644 index 0000000..7a35093 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtq_n_u32_f32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c new file mode 100644 index 0000000..8b4cfa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vshrq_n_s16 (a, 16); +} + +/* { dg-final { scan-assembler "vshr.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vshrq (a, 16); +} + +/* { dg-final { scan-assembler "vshr.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c new file mode 100644 index 0000000..bf421a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vshrq_n_s32 (a, 32); +} + +/* { dg-final { scan-assembler "vshr.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vshrq (a, 32); +} + +/* { dg-final { scan-assembler "vshr.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c new file mode 100644 index 0000000..a11218c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vshrq_n_s8 (a, 8); +} + +/* { dg-final { scan-assembler "vshr.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vshrq (a, 8); +} + +/* { dg-final { scan-assembler "vshr.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c new file mode 100644 index 0000000..a4a5439 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vshrq_n_u16 (a, 16); +} + +/* { dg-final { scan-assembler "vshr.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vshrq (a, 16); +} + +/* { dg-final { scan-assembler "vshr.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c new file mode 100644 index 0000000..d4630aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vshrq_n_u32 (a, 32); +} + +/* { dg-final { scan-assembler "vshr.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vshrq (a, 32); +} + +/* { dg-final { scan-assembler "vshr.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c new file mode 100644 index 0000000..3a3345d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vshrq_n_u8 (a, 8); +} + +/* { dg-final { scan-assembler "vshr.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vshrq (a, 8); +} + +/* { dg-final { scan-assembler "vshr.u8" } } */ -- cgit v1.1 From d71dba7b611f5e8404aa1b4361d319e856665a4a Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 15:22:25 +0000 Subject: [ARM][GCC][3/2x]: MVE intrinsics with binary operands. This patch supports following MVE ACLE intrinsics with binary operands. vaddlvq_p_s32, vaddlvq_p_u32, vcmpneq_s8, vcmpneq_s16, vcmpneq_s32, vcmpneq_u8, vcmpneq_u16, vcmpneq_u32, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_u8, vshlq_u16, vshlq_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro. (vaddlvq_p_u32): Likewise. (vcmpneq_s8): Likewise. (vcmpneq_s16): Likewise. (vcmpneq_s32): Likewise. (vcmpneq_u8): Likewise. (vcmpneq_u16): Likewise. (vcmpneq_u32): Likewise. (vshlq_s8): Likewise. (vshlq_s16): Likewise. (vshlq_s32): Likewise. (vshlq_u8): Likewise. (vshlq_u16): Likewise. (vshlq_u32): Likewise. (__arm_vaddlvq_p_s32): Define intrinsic. (__arm_vaddlvq_p_u32): Likewise. (__arm_vcmpneq_s8): Likewise. (__arm_vcmpneq_s16): Likewise. (__arm_vcmpneq_s32): Likewise. (__arm_vcmpneq_u8): Likewise. (__arm_vcmpneq_u16): Likewise. (__arm_vcmpneq_u32): Likewise. (__arm_vshlq_s8): Likewise. (__arm_vshlq_s16): Likewise. (__arm_vshlq_s32): Likewise. (__arm_vshlq_u8): Likewise. (__arm_vshlq_u16): Likewise. (__arm_vshlq_u32): Likewise. (vaddlvq_p): Define polymorphic variant. (vcmpneq): Likewise. (vshlq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS): Use it. (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vaddlvq_p_v4si): Define RTL pattern. (mve_vcmpneq_): Likewise. (mve_vshlq_): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: New test. * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise. --- gcc/ChangeLog | 47 ++++++ gcc/config/arm/arm-builtins.c | 18 +++ gcc/config/arm/arm_mve.h | 160 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 8 +- gcc/config/arm/mve.md | 56 +++++++- gcc/testsuite/ChangeLog | 19 +++ .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 22 +++ 20 files changed, 612 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 03312bd..c9e6530 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,53 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define + qualifier for binary operands. + (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. + (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro. + (vaddlvq_p_u32): Likewise. + (vcmpneq_s8): Likewise. + (vcmpneq_s16): Likewise. + (vcmpneq_s32): Likewise. + (vcmpneq_u8): Likewise. + (vcmpneq_u16): Likewise. + (vcmpneq_u32): Likewise. + (vshlq_s8): Likewise. + (vshlq_s16): Likewise. + (vshlq_s32): Likewise. + (vshlq_u8): Likewise. + (vshlq_u16): Likewise. + (vshlq_u32): Likewise. + (__arm_vaddlvq_p_s32): Define intrinsic. + (__arm_vaddlvq_p_u32): Likewise. + (__arm_vcmpneq_s8): Likewise. + (__arm_vcmpneq_s16): Likewise. + (__arm_vcmpneq_s32): Likewise. + (__arm_vcmpneq_u8): Likewise. + (__arm_vcmpneq_u16): Likewise. + (__arm_vcmpneq_u32): Likewise. + (__arm_vshlq_s8): Likewise. + (__arm_vshlq_s16): Likewise. + (__arm_vshlq_s32): Likewise. + (__arm_vshlq_u8): Likewise. + (__arm_vshlq_u16): Likewise. + (__arm_vshlq_u32): Likewise. + (vaddlvq_p): Define polymorphic variant. + (vcmpneq): Likewise. + (vshlq): Likewise. + * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS): + Use it. + (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. + (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. + * config/arm/mve.md (mve_vaddlvq_p_v4si): Define RTL pattern. + (mve_vcmpneq_): Likewise. + (mve_vshlq_): Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 066a046..afccac0 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -415,6 +415,24 @@ arm_binop_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define BINOP_UNONE_NONE_IMM_QUALIFIERS \ (arm_binop_unone_none_imm_qualifiers) +static enum arm_type_qualifiers +arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned }; +#define BINOP_NONE_NONE_UNONE_QUALIFIERS \ + (arm_binop_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none, qualifier_none }; +#define BINOP_UNONE_NONE_NONE_QUALIFIERS \ + (arm_binop_unone_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_unone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none }; +#define BINOP_UNONE_UNONE_NONE_QUALIFIERS \ + (arm_binop_unone_unone_none_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 26787ba..ef0d2ac 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -225,6 +225,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vshrq_n_u8(__a, __imm) __arm_vshrq_n_u8(__a, __imm) #define vshrq_n_u16(__a, __imm) __arm_vshrq_n_u16(__a, __imm) #define vshrq_n_u32(__a, __imm) __arm_vshrq_n_u32(__a, __imm) +#define vaddlvq_p_s32(__a, __p) __arm_vaddlvq_p_s32(__a, __p) +#define vaddlvq_p_u32(__a, __p) __arm_vaddlvq_p_u32(__a, __p) +#define vcmpneq_s8(__a, __b) __arm_vcmpneq_s8(__a, __b) +#define vcmpneq_s16(__a, __b) __arm_vcmpneq_s16(__a, __b) +#define vcmpneq_s32(__a, __b) __arm_vcmpneq_s32(__a, __b) +#define vcmpneq_u8(__a, __b) __arm_vcmpneq_u8(__a, __b) +#define vcmpneq_u16(__a, __b) __arm_vcmpneq_u16(__a, __b) +#define vcmpneq_u32(__a, __b) __arm_vcmpneq_u32(__a, __b) +#define vshlq_s8(__a, __b) __arm_vshlq_s8(__a, __b) +#define vshlq_s16(__a, __b) __arm_vshlq_s16(__a, __b) +#define vshlq_s32(__a, __b) __arm_vshlq_s32(__a, __b) +#define vshlq_u8(__a, __b) __arm_vshlq_u8(__a, __b) +#define vshlq_u16(__a, __b) __arm_vshlq_u16(__a, __b) +#define vshlq_u32(__a, __b) __arm_vshlq_u32(__a, __b) #endif __extension__ extern __inline void @@ -868,6 +882,103 @@ __arm_vshrq_n_u32 (uint32x4_t __a, const int __imm) { return __builtin_mve_vshrq_n_uv4si (__a, __imm); } +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_p_s32 (int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddlvq_p_sv4si (__a, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_p_u32 (uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddlvq_p_uv4si (__a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpneq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpneq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpneq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcmpneq_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcmpneq_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcmpneq_uv4si (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vshlq_sv16qi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vshlq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vshlq_sv4si (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vshlq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vshlq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vshlq_uv4si (__a, __b); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ @@ -1689,6 +1800,27 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) +#define vshlq(p0,p1) __arm_vshlq(p0,p1) +#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vshrq(p0,p1) __arm_vshrq(p0,p1) +#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + #define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) #define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -1831,6 +1963,34 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vaddlvq_p(p0,p1) __arm_vaddlvq_p(p0,p1) +#define __arm_vaddlvq_p(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddlvq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddlvq_p_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) +#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vshlq(p0,p1) __arm_vshlq(p0,p1) +#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index b0a1e43..05930c9 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -6,7 +6,7 @@ GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your + by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT @@ -87,3 +87,9 @@ VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) +VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index af8b654..4ae608b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -40,7 +40,8 @@ VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U - VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) + VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S + VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -59,8 +60,9 @@ (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u") (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") - (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") - (VCVTQ_N_FROM_F_U "u")]) + (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u") + (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s") + (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64")]) @@ -90,6 +92,9 @@ (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) +(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U]) +(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S]) +(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -806,3 +811,48 @@ "vcvt..f\t%q0, %q1, %2" [(set_attr "type" "mve_move") ]) + +;; +;; [vaddlvq_p_s]) +;; +(define_insn "mve_vaddlvq_p_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VADDLVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddlvt.32 %Q0, %R0, %q1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpneq_u, vcmpneq_s]) +;; +(define_insn "mve_vcmpneq_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPNEQ)) + ] + "TARGET_HAVE_MVE" + "vcmp.i%# ne, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshlq_s, vshlq_u]) +;; +(define_insn "mve_vshlq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VSHLQ)) + ] + "TARGET_HAVE_MVE" + "vshl.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fc581ef..83de77b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: New test. + * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c new file mode 100644 index 0000000..ccdebba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vaddlvq_p_s32 (a, p); +} + +/* { dg-final { scan-assembler "vaddlvt.s32" } } */ + +int64_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vaddlvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddlvt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c new file mode 100644 index 0000000..9bdff24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vaddlvq_p_u32 (a, p); +} + +/* { dg-final { scan-assembler "vaddlvt.u32" } } */ + +uint64_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vaddlvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddlvt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c new file mode 100644 index 0000000..001af00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpneq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c new file mode 100644 index 0000000..a49f8e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpneq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c new file mode 100644 index 0000000..e312b77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpneq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c new file mode 100644 index 0000000..c234f25 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcmpneq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c new file mode 100644 index 0000000..711d071 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcmpneq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c new file mode 100644 index 0000000..5fa8884 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcmpneq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c new file mode 100644 index 0000000..bcadf6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vshlq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c new file mode 100644 index 0000000..3f01c1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vshlq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c new file mode 100644 index 0000000..554f984 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vshlq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c new file mode 100644 index 0000000..9b6328b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vshlq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c new file mode 100644 index 0000000..d8a5b90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vshlq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c new file mode 100644 index 0000000..818b2f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vshlq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vshlq (a, b); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ -- cgit v1.1 From 33203b4c27d09b22b6cb4cc90970867eba2cda3f Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 15:32:36 +0000 Subject: [ARM][GCC][4/2x]: MVE intrinsics with binary operands. This patch supports following MVE ACLE intrinsics with binary operands. vsubq_u8, vsubq_n_u8, vrmulhq_u8, vrhaddq_u8, vqsubq_u8, vqsubq_n_u8, vqaddq_u8, vqaddq_n_u8, vorrq_u8, vornq_u8, vmulq_u8, vmulq_n_u8, vmulltq_int_u8, vmullbq_int_u8, vmulhq_u8, vmladavq_u8, vminvq_u8, vminq_u8, vmaxvq_u8, vmaxq_u8, vhsubq_u8, vhsubq_n_u8, vhaddq_u8, vhaddq_n_u8, veorq_u8, vcmpneq_n_u8, vcmphiq_u8, vcmphiq_n_u8, vcmpeqq_u8, vcmpeqq_n_u8, vcmpcsq_u8, vcmpcsq_n_u8, vcaddq_rot90_u8, vcaddq_rot270_u8, vbicq_u8, vandq_u8, vaddvq_p_u8, vaddvaq_u8, vaddq_n_u8, vabdq_u8, vshlq_r_u8, vrshlq_u8, vrshlq_n_u8, vqshlq_u8, vqshlq_r_u8, vqrshlq_u8, vqrshlq_n_u8, vminavq_s8, vminaq_s8, vmaxavq_s8, vmaxaq_s8, vbrsrq_n_u8, vshlq_n_u8, vrshrq_n_u8, vqshlq_n_u8, vcmpneq_n_s8, vcmpltq_s8, vcmpltq_n_s8, vcmpleq_s8, vcmpleq_n_s8, vcmpgtq_s8, vcmpgtq_n_s8, vcmpgeq_s8, vcmpgeq_n_s8, vcmpeqq_s8, vcmpeqq_n_s8, vqshluq_n_s8, vaddvq_p_s8, vsubq_s8, vsubq_n_s8, vshlq_r_s8, vrshlq_s8, vrshlq_n_s8, vrmulhq_s8, vrhaddq_s8, vqsubq_s8, vqsubq_n_s8, vqshlq_s8, vqshlq_r_s8, vqrshlq_s8, vqrshlq_n_s8, vqrdmulhq_s8, vqrdmulhq_n_s8, vqdmulhq_s8, vqdmulhq_n_s8, vqaddq_s8, vqaddq_n_s8, vorrq_s8, vornq_s8, vmulq_s8, vmulq_n_s8, vmulltq_int_s8, vmullbq_int_s8, vmulhq_s8, vmlsdavxq_s8, vmlsdavq_s8, vmladavxq_s8, vmladavq_s8, vminvq_s8, vminq_s8, vmaxvq_s8, vmaxq_s8, vhsubq_s8, vhsubq_n_s8, vhcaddq_rot90_s8, vhcaddq_rot270_s8, vhaddq_s8, vhaddq_n_s8, veorq_s8, vcaddq_rot90_s8, vcaddq_rot270_s8, vbrsrq_n_s8, vbicq_s8, vandq_s8, vaddvaq_s8, vaddq_n_s8, vabdq_s8, vshlq_n_s8, vrshrq_n_s8, vqshlq_n_s8, vsubq_u16, vsubq_n_u16, vrmulhq_u16, vrhaddq_u16, vqsubq_u16, vqsubq_n_u16, vqaddq_u16, vqaddq_n_u16, vorrq_u16, vornq_u16, vmulq_u16, vmulq_n_u16, vmulltq_int_u16, vmullbq_int_u16, vmulhq_u16, vmladavq_u16, vminvq_u16, vminq_u16, vmaxvq_u16, vmaxq_u16, vhsubq_u16, vhsubq_n_u16, vhaddq_u16, vhaddq_n_u16, veorq_u16, vcmpneq_n_u16, vcmphiq_u16, vcmphiq_n_u16, vcmpeqq_u16, vcmpeqq_n_u16, vcmpcsq_u16, vcmpcsq_n_u16, vcaddq_rot90_u16, vcaddq_rot270_u16, vbicq_u16, vandq_u16, vaddvq_p_u16, vaddvaq_u16, vaddq_n_u16, vabdq_u16, vshlq_r_u16, vrshlq_u16, vrshlq_n_u16, vqshlq_u16, vqshlq_r_u16, vqrshlq_u16, vqrshlq_n_u16, vminavq_s16, vminaq_s16, vmaxavq_s16, vmaxaq_s16, vbrsrq_n_u16, vshlq_n_u16, vrshrq_n_u16, vqshlq_n_u16, vcmpneq_n_s16, vcmpltq_s16, vcmpltq_n_s16, vcmpleq_s16, vcmpleq_n_s16, vcmpgtq_s16, vcmpgtq_n_s16, vcmpgeq_s16, vcmpgeq_n_s16, vcmpeqq_s16, vcmpeqq_n_s16, vqshluq_n_s16, vaddvq_p_s16, vsubq_s16, vsubq_n_s16, vshlq_r_s16, vrshlq_s16, vrshlq_n_s16, vrmulhq_s16, vrhaddq_s16, vqsubq_s16, vqsubq_n_s16, vqshlq_s16, vqshlq_r_s16, vqrshlq_s16, vqrshlq_n_s16, vqrdmulhq_s16, vqrdmulhq_n_s16, vqdmulhq_s16, vqdmulhq_n_s16, vqaddq_s16, vqaddq_n_s16, vorrq_s16, vornq_s16, vmulq_s16, vmulq_n_s16, vmulltq_int_s16, vmullbq_int_s16, vmulhq_s16, vmlsdavxq_s16, vmlsdavq_s16, vmladavxq_s16, vmladavq_s16, vminvq_s16, vminq_s16, vmaxvq_s16, vmaxq_s16, vhsubq_s16, vhsubq_n_s16, vhcaddq_rot90_s16, vhcaddq_rot270_s16, vhaddq_s16, vhaddq_n_s16, veorq_s16, vcaddq_rot90_s16, vcaddq_rot270_s16, vbrsrq_n_s16, vbicq_s16, vandq_s16, vaddvaq_s16, vaddq_n_s16, vabdq_s16, vshlq_n_s16, vrshrq_n_s16, vqshlq_n_s16, vsubq_u32, vsubq_n_u32, vrmulhq_u32, vrhaddq_u32, vqsubq_u32, vqsubq_n_u32, vqaddq_u32, vqaddq_n_u32, vorrq_u32, vornq_u32, vmulq_u32, vmulq_n_u32, vmulltq_int_u32, vmullbq_int_u32, vmulhq_u32, vmladavq_u32, vminvq_u32, vminq_u32, vmaxvq_u32, vmaxq_u32, vhsubq_u32, vhsubq_n_u32, vhaddq_u32, vhaddq_n_u32, veorq_u32, vcmpneq_n_u32, vcmphiq_u32, vcmphiq_n_u32, vcmpeqq_u32, vcmpeqq_n_u32, vcmpcsq_u32, vcmpcsq_n_u32, vcaddq_rot90_u32, vcaddq_rot270_u32, vbicq_u32, vandq_u32, vaddvq_p_u32, vaddvaq_u32, vaddq_n_u32, vabdq_u32, vshlq_r_u32, vrshlq_u32, vrshlq_n_u32, vqshlq_u32, vqshlq_r_u32, vqrshlq_u32, vqrshlq_n_u32, vminavq_s32, vminaq_s32, vmaxavq_s32, vmaxaq_s32, vbrsrq_n_u32, vshlq_n_u32, vrshrq_n_u32, vqshlq_n_u32, vcmpneq_n_s32, vcmpltq_s32, vcmpltq_n_s32, vcmpleq_s32, vcmpleq_n_s32, vcmpgtq_s32, vcmpgtq_n_s32, vcmpgeq_s32, vcmpgeq_n_s32, vcmpeqq_s32, vcmpeqq_n_s32, vqshluq_n_s32, vaddvq_p_s32, vsubq_s32, vsubq_n_s32, vshlq_r_s32, vrshlq_s32, vrshlq_n_s32, vrmulhq_s32, vrhaddq_s32, vqsubq_s32, vqsubq_n_s32, vqshlq_s32, vqshlq_r_s32, vqrshlq_s32, vqrshlq_n_s32, vqrdmulhq_s32, vqrdmulhq_n_s32, vqdmulhq_s32, vqdmulhq_n_s32, vqaddq_s32, vqaddq_n_s32, vorrq_s32, vornq_s32, vmulq_s32, vmulq_n_s32, vmulltq_int_s32, vmullbq_int_s32, vmulhq_s32, vmlsdavxq_s32, vmlsdavq_s32, vmladavxq_s32, vmladavq_s32, vminvq_s32, vminq_s32, vmaxvq_s32, vmaxq_s32, vhsubq_s32, vhsubq_n_s32, vhcaddq_rot90_s32, vhcaddq_rot270_s32, vhaddq_s32, vhaddq_n_s32, veorq_s32, vcaddq_rot90_s32, vcaddq_rot270_s32, vbrsrq_n_s32, vbicq_s32, vandq_s32, vaddvaq_s32, vaddq_n_s32, vabdq_s32, vshlq_n_s32, vrshrq_n_s32, vqshlq_n_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch new constraints "Ra" and "Rg" are added. Ra checks the constant is with in the range of 0 to 7 where as Rg checks that the constant is one among 1, 2, 4 and 8. Also a new predicates "mve_imm_7" and "mve_imm_selective_upto_8" are added, to check the the matching constraint Ra and Rg respectively. The above intrinsics are defined using the already defined builtin qualifiers BINOP_NONE_NONE_IMM, BINOP_NONE_NONE_NONE, BINOP_NONE_NONE_UNONE, BINOP_UNONE_NONE_IMM, BINOP_UNONE_NONE_NONE, BINOP_UNONE_UNONE_IMM, BINOP_UNONE_UNONE_NONE, BINOP_UNONE_UNONE_UNONE. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vsubq_u8): Define macro. (vsubq_n_u8): Likewise. (vrmulhq_u8): Likewise. (vrhaddq_u8): Likewise. (vqsubq_u8): Likewise. (vqsubq_n_u8): Likewise. (vqaddq_u8): Likewise. (vqaddq_n_u8): Likewise. (vorrq_u8): Likewise. (vornq_u8): Likewise. (vmulq_u8): Likewise. (vmulq_n_u8): Likewise. (vmulltq_int_u8): Likewise. (vmullbq_int_u8): Likewise. (vmulhq_u8): Likewise. (vmladavq_u8): Likewise. (vminvq_u8): Likewise. (vminq_u8): Likewise. (vmaxvq_u8): Likewise. (vmaxq_u8): Likewise. (vhsubq_u8): Likewise. (vhsubq_n_u8): Likewise. (vhaddq_u8): Likewise. (vhaddq_n_u8): Likewise. (veorq_u8): Likewise. (vcmpneq_n_u8): Likewise. (vcmphiq_u8): Likewise. (vcmphiq_n_u8): Likewise. (vcmpeqq_u8): Likewise. (vcmpeqq_n_u8): Likewise. (vcmpcsq_u8): Likewise. (vcmpcsq_n_u8): Likewise. (vcaddq_rot90_u8): Likewise. (vcaddq_rot270_u8): Likewise. (vbicq_u8): Likewise. (vandq_u8): Likewise. (vaddvq_p_u8): Likewise. (vaddvaq_u8): Likewise. (vaddq_n_u8): Likewise. (vabdq_u8): Likewise. (vshlq_r_u8): Likewise. (vrshlq_u8): Likewise. (vrshlq_n_u8): Likewise. (vqshlq_u8): Likewise. (vqshlq_r_u8): Likewise. (vqrshlq_u8): Likewise. (vqrshlq_n_u8): Likewise. (vminavq_s8): Likewise. (vminaq_s8): Likewise. (vmaxavq_s8): Likewise. (vmaxaq_s8): Likewise. (vbrsrq_n_u8): Likewise. (vshlq_n_u8): Likewise. (vrshrq_n_u8): Likewise. (vqshlq_n_u8): Likewise. (vcmpneq_n_s8): Likewise. (vcmpltq_s8): Likewise. (vcmpltq_n_s8): Likewise. (vcmpleq_s8): Likewise. (vcmpleq_n_s8): Likewise. (vcmpgtq_s8): Likewise. (vcmpgtq_n_s8): Likewise. (vcmpgeq_s8): Likewise. (vcmpgeq_n_s8): Likewise. (vcmpeqq_s8): Likewise. (vcmpeqq_n_s8): Likewise. (vqshluq_n_s8): Likewise. (vaddvq_p_s8): Likewise. (vsubq_s8): Likewise. (vsubq_n_s8): Likewise. (vshlq_r_s8): Likewise. (vrshlq_s8): Likewise. (vrshlq_n_s8): Likewise. (vrmulhq_s8): Likewise. (vrhaddq_s8): Likewise. (vqsubq_s8): Likewise. (vqsubq_n_s8): Likewise. (vqshlq_s8): Likewise. (vqshlq_r_s8): Likewise. (vqrshlq_s8): Likewise. (vqrshlq_n_s8): Likewise. (vqrdmulhq_s8): Likewise. (vqrdmulhq_n_s8): Likewise. (vqdmulhq_s8): Likewise. (vqdmulhq_n_s8): Likewise. (vqaddq_s8): Likewise. (vqaddq_n_s8): Likewise. (vorrq_s8): Likewise. (vornq_s8): Likewise. (vmulq_s8): Likewise. (vmulq_n_s8): Likewise. (vmulltq_int_s8): Likewise. (vmullbq_int_s8): Likewise. (vmulhq_s8): Likewise. (vmlsdavxq_s8): Likewise. (vmlsdavq_s8): Likewise. (vmladavxq_s8): Likewise. (vmladavq_s8): Likewise. (vminvq_s8): Likewise. (vminq_s8): Likewise. (vmaxvq_s8): Likewise. (vmaxq_s8): Likewise. (vhsubq_s8): Likewise. (vhsubq_n_s8): Likewise. (vhcaddq_rot90_s8): Likewise. (vhcaddq_rot270_s8): Likewise. (vhaddq_s8): Likewise. (vhaddq_n_s8): Likewise. (veorq_s8): Likewise. (vcaddq_rot90_s8): Likewise. (vcaddq_rot270_s8): Likewise. (vbrsrq_n_s8): Likewise. (vbicq_s8): Likewise. (vandq_s8): Likewise. (vaddvaq_s8): Likewise. (vaddq_n_s8): Likewise. (vabdq_s8): Likewise. (vshlq_n_s8): Likewise. (vrshrq_n_s8): Likewise. (vqshlq_n_s8): Likewise. (vsubq_u16): Likewise. (vsubq_n_u16): Likewise. (vrmulhq_u16): Likewise. (vrhaddq_u16): Likewise. (vqsubq_u16): Likewise. (vqsubq_n_u16): Likewise. (vqaddq_u16): Likewise. (vqaddq_n_u16): Likewise. (vorrq_u16): Likewise. (vornq_u16): Likewise. (vmulq_u16): Likewise. (vmulq_n_u16): Likewise. (vmulltq_int_u16): Likewise. (vmullbq_int_u16): Likewise. (vmulhq_u16): Likewise. (vmladavq_u16): Likewise. (vminvq_u16): Likewise. (vminq_u16): Likewise. (vmaxvq_u16): Likewise. (vmaxq_u16): Likewise. (vhsubq_u16): Likewise. (vhsubq_n_u16): Likewise. (vhaddq_u16): Likewise. (vhaddq_n_u16): Likewise. (veorq_u16): Likewise. (vcmpneq_n_u16): Likewise. (vcmphiq_u16): Likewise. (vcmphiq_n_u16): Likewise. (vcmpeqq_u16): Likewise. (vcmpeqq_n_u16): Likewise. (vcmpcsq_u16): Likewise. (vcmpcsq_n_u16): Likewise. (vcaddq_rot90_u16): Likewise. (vcaddq_rot270_u16): Likewise. (vbicq_u16): Likewise. (vandq_u16): Likewise. (vaddvq_p_u16): Likewise. (vaddvaq_u16): Likewise. (vaddq_n_u16): Likewise. (vabdq_u16): Likewise. (vshlq_r_u16): Likewise. (vrshlq_u16): Likewise. (vrshlq_n_u16): Likewise. (vqshlq_u16): Likewise. (vqshlq_r_u16): Likewise. (vqrshlq_u16): Likewise. (vqrshlq_n_u16): Likewise. (vminavq_s16): Likewise. (vminaq_s16): Likewise. (vmaxavq_s16): Likewise. (vmaxaq_s16): Likewise. (vbrsrq_n_u16): Likewise. (vshlq_n_u16): Likewise. (vrshrq_n_u16): Likewise. (vqshlq_n_u16): Likewise. (vcmpneq_n_s16): Likewise. (vcmpltq_s16): Likewise. (vcmpltq_n_s16): Likewise. (vcmpleq_s16): Likewise. (vcmpleq_n_s16): Likewise. (vcmpgtq_s16): Likewise. (vcmpgtq_n_s16): Likewise. (vcmpgeq_s16): Likewise. (vcmpgeq_n_s16): Likewise. (vcmpeqq_s16): Likewise. (vcmpeqq_n_s16): Likewise. (vqshluq_n_s16): Likewise. (vaddvq_p_s16): Likewise. (vsubq_s16): Likewise. (vsubq_n_s16): Likewise. (vshlq_r_s16): Likewise. (vrshlq_s16): Likewise. (vrshlq_n_s16): Likewise. (vrmulhq_s16): Likewise. (vrhaddq_s16): Likewise. (vqsubq_s16): Likewise. (vqsubq_n_s16): Likewise. (vqshlq_s16): Likewise. (vqshlq_r_s16): Likewise. (vqrshlq_s16): Likewise. (vqrshlq_n_s16): Likewise. (vqrdmulhq_s16): Likewise. (vqrdmulhq_n_s16): Likewise. (vqdmulhq_s16): Likewise. (vqdmulhq_n_s16): Likewise. (vqaddq_s16): Likewise. (vqaddq_n_s16): Likewise. (vorrq_s16): Likewise. (vornq_s16): Likewise. (vmulq_s16): Likewise. (vmulq_n_s16): Likewise. (vmulltq_int_s16): Likewise. (vmullbq_int_s16): Likewise. (vmulhq_s16): Likewise. (vmlsdavxq_s16): Likewise. (vmlsdavq_s16): Likewise. (vmladavxq_s16): Likewise. (vmladavq_s16): Likewise. (vminvq_s16): Likewise. (vminq_s16): Likewise. (vmaxvq_s16): Likewise. (vmaxq_s16): Likewise. (vhsubq_s16): Likewise. (vhsubq_n_s16): Likewise. (vhcaddq_rot90_s16): Likewise. (vhcaddq_rot270_s16): Likewise. (vhaddq_s16): Likewise. (vhaddq_n_s16): Likewise. (veorq_s16): Likewise. (vcaddq_rot90_s16): Likewise. (vcaddq_rot270_s16): Likewise. (vbrsrq_n_s16): Likewise. (vbicq_s16): Likewise. (vandq_s16): Likewise. (vaddvaq_s16): Likewise. (vaddq_n_s16): Likewise. (vabdq_s16): Likewise. (vshlq_n_s16): Likewise. (vrshrq_n_s16): Likewise. (vqshlq_n_s16): Likewise. (vsubq_u32): Likewise. (vsubq_n_u32): Likewise. (vrmulhq_u32): Likewise. (vrhaddq_u32): Likewise. (vqsubq_u32): Likewise. (vqsubq_n_u32): Likewise. (vqaddq_u32): Likewise. (vqaddq_n_u32): Likewise. (vorrq_u32): Likewise. (vornq_u32): Likewise. (vmulq_u32): Likewise. (vmulq_n_u32): Likewise. (vmulltq_int_u32): Likewise. (vmullbq_int_u32): Likewise. (vmulhq_u32): Likewise. (vmladavq_u32): Likewise. (vminvq_u32): Likewise. (vminq_u32): Likewise. (vmaxvq_u32): Likewise. (vmaxq_u32): Likewise. (vhsubq_u32): Likewise. (vhsubq_n_u32): Likewise. (vhaddq_u32): Likewise. (vhaddq_n_u32): Likewise. (veorq_u32): Likewise. (vcmpneq_n_u32): Likewise. (vcmphiq_u32): Likewise. (vcmphiq_n_u32): Likewise. (vcmpeqq_u32): Likewise. (vcmpeqq_n_u32): Likewise. (vcmpcsq_u32): Likewise. (vcmpcsq_n_u32): Likewise. (vcaddq_rot90_u32): Likewise. (vcaddq_rot270_u32): Likewise. (vbicq_u32): Likewise. (vandq_u32): Likewise. (vaddvq_p_u32): Likewise. (vaddvaq_u32): Likewise. (vaddq_n_u32): Likewise. (vabdq_u32): Likewise. (vshlq_r_u32): Likewise. (vrshlq_u32): Likewise. (vrshlq_n_u32): Likewise. (vqshlq_u32): Likewise. (vqshlq_r_u32): Likewise. (vqrshlq_u32): Likewise. (vqrshlq_n_u32): Likewise. (vminavq_s32): Likewise. (vminaq_s32): Likewise. (vmaxavq_s32): Likewise. (vmaxaq_s32): Likewise. (vbrsrq_n_u32): Likewise. (vshlq_n_u32): Likewise. (vrshrq_n_u32): Likewise. (vqshlq_n_u32): Likewise. (vcmpneq_n_s32): Likewise. (vcmpltq_s32): Likewise. (vcmpltq_n_s32): Likewise. (vcmpleq_s32): Likewise. (vcmpleq_n_s32): Likewise. (vcmpgtq_s32): Likewise. (vcmpgtq_n_s32): Likewise. (vcmpgeq_s32): Likewise. (vcmpgeq_n_s32): Likewise. (vcmpeqq_s32): Likewise. (vcmpeqq_n_s32): Likewise. (vqshluq_n_s32): Likewise. (vaddvq_p_s32): Likewise. (vsubq_s32): Likewise. (vsubq_n_s32): Likewise. (vshlq_r_s32): Likewise. (vrshlq_s32): Likewise. (vrshlq_n_s32): Likewise. (vrmulhq_s32): Likewise. (vrhaddq_s32): Likewise. (vqsubq_s32): Likewise. (vqsubq_n_s32): Likewise. (vqshlq_s32): Likewise. (vqshlq_r_s32): Likewise. (vqrshlq_s32): Likewise. (vqrshlq_n_s32): Likewise. (vqrdmulhq_s32): Likewise. (vqrdmulhq_n_s32): Likewise. (vqdmulhq_s32): Likewise. (vqdmulhq_n_s32): Likewise. (vqaddq_s32): Likewise. (vqaddq_n_s32): Likewise. (vorrq_s32): Likewise. (vornq_s32): Likewise. (vmulq_s32): Likewise. (vmulq_n_s32): Likewise. (vmulltq_int_s32): Likewise. (vmullbq_int_s32): Likewise. (vmulhq_s32): Likewise. (vmlsdavxq_s32): Likewise. (vmlsdavq_s32): Likewise. (vmladavxq_s32): Likewise. (vmladavq_s32): Likewise. (vminvq_s32): Likewise. (vminq_s32): Likewise. (vmaxvq_s32): Likewise. (vmaxq_s32): Likewise. (vhsubq_s32): Likewise. (vhsubq_n_s32): Likewise. (vhcaddq_rot90_s32): Likewise. (vhcaddq_rot270_s32): Likewise. (vhaddq_s32): Likewise. (vhaddq_n_s32): Likewise. (veorq_s32): Likewise. (vcaddq_rot90_s32): Likewise. (vcaddq_rot270_s32): Likewise. (vbrsrq_n_s32): Likewise. (vbicq_s32): Likewise. (vandq_s32): Likewise. (vaddvaq_s32): Likewise. (vaddq_n_s32): Likewise. (vabdq_s32): Likewise. (vshlq_n_s32): Likewise. (vrshrq_n_s32): Likewise. (vqshlq_n_s32): Likewise. (__arm_vsubq_u8): Define intrinsic. (__arm_vsubq_n_u8): Likewise. (__arm_vrmulhq_u8): Likewise. (__arm_vrhaddq_u8): Likewise. (__arm_vqsubq_u8): Likewise. (__arm_vqsubq_n_u8): Likewise. (__arm_vqaddq_u8): Likewise. (__arm_vqaddq_n_u8): Likewise. (__arm_vorrq_u8): Likewise. (__arm_vornq_u8): Likewise. (__arm_vmulq_u8): Likewise. (__arm_vmulq_n_u8): Likewise. (__arm_vmulltq_int_u8): Likewise. (__arm_vmullbq_int_u8): Likewise. (__arm_vmulhq_u8): Likewise. (__arm_vmladavq_u8): Likewise. (__arm_vminvq_u8): Likewise. (__arm_vminq_u8): Likewise. (__arm_vmaxvq_u8): Likewise. (__arm_vmaxq_u8): Likewise. (__arm_vhsubq_u8): Likewise. (__arm_vhsubq_n_u8): Likewise. (__arm_vhaddq_u8): Likewise. (__arm_vhaddq_n_u8): Likewise. (__arm_veorq_u8): Likewise. (__arm_vcmpneq_n_u8): Likewise. (__arm_vcmphiq_u8): Likewise. (__arm_vcmphiq_n_u8): Likewise. (__arm_vcmpeqq_u8): Likewise. (__arm_vcmpeqq_n_u8): Likewise. (__arm_vcmpcsq_u8): Likewise. (__arm_vcmpcsq_n_u8): Likewise. (__arm_vcaddq_rot90_u8): Likewise. (__arm_vcaddq_rot270_u8): Likewise. (__arm_vbicq_u8): Likewise. (__arm_vandq_u8): Likewise. (__arm_vaddvq_p_u8): Likewise. (__arm_vaddvaq_u8): Likewise. (__arm_vaddq_n_u8): Likewise. (__arm_vabdq_u8): Likewise. (__arm_vshlq_r_u8): Likewise. (__arm_vrshlq_u8): Likewise. (__arm_vrshlq_n_u8): Likewise. (__arm_vqshlq_u8): Likewise. (__arm_vqshlq_r_u8): Likewise. (__arm_vqrshlq_u8): Likewise. (__arm_vqrshlq_n_u8): Likewise. (__arm_vminavq_s8): Likewise. (__arm_vminaq_s8): Likewise. (__arm_vmaxavq_s8): Likewise. (__arm_vmaxaq_s8): Likewise. (__arm_vbrsrq_n_u8): Likewise. (__arm_vshlq_n_u8): Likewise. (__arm_vrshrq_n_u8): Likewise. (__arm_vqshlq_n_u8): Likewise. (__arm_vcmpneq_n_s8): Likewise. (__arm_vcmpltq_s8): Likewise. (__arm_vcmpltq_n_s8): Likewise. (__arm_vcmpleq_s8): Likewise. (__arm_vcmpleq_n_s8): Likewise. (__arm_vcmpgtq_s8): Likewise. (__arm_vcmpgtq_n_s8): Likewise. (__arm_vcmpgeq_s8): Likewise. (__arm_vcmpgeq_n_s8): Likewise. (__arm_vcmpeqq_s8): Likewise. (__arm_vcmpeqq_n_s8): Likewise. (__arm_vqshluq_n_s8): Likewise. (__arm_vaddvq_p_s8): Likewise. (__arm_vsubq_s8): Likewise. (__arm_vsubq_n_s8): Likewise. (__arm_vshlq_r_s8): Likewise. (__arm_vrshlq_s8): Likewise. (__arm_vrshlq_n_s8): Likewise. (__arm_vrmulhq_s8): Likewise. (__arm_vrhaddq_s8): Likewise. (__arm_vqsubq_s8): Likewise. (__arm_vqsubq_n_s8): Likewise. (__arm_vqshlq_s8): Likewise. (__arm_vqshlq_r_s8): Likewise. (__arm_vqrshlq_s8): Likewise. (__arm_vqrshlq_n_s8): Likewise. (__arm_vqrdmulhq_s8): Likewise. (__arm_vqrdmulhq_n_s8): Likewise. (__arm_vqdmulhq_s8): Likewise. (__arm_vqdmulhq_n_s8): Likewise. (__arm_vqaddq_s8): Likewise. (__arm_vqaddq_n_s8): Likewise. (__arm_vorrq_s8): Likewise. (__arm_vornq_s8): Likewise. (__arm_vmulq_s8): Likewise. (__arm_vmulq_n_s8): Likewise. (__arm_vmulltq_int_s8): Likewise. (__arm_vmullbq_int_s8): Likewise. (__arm_vmulhq_s8): Likewise. (__arm_vmlsdavxq_s8): Likewise. (__arm_vmlsdavq_s8): Likewise. (__arm_vmladavxq_s8): Likewise. (__arm_vmladavq_s8): Likewise. (__arm_vminvq_s8): Likewise. (__arm_vminq_s8): Likewise. (__arm_vmaxvq_s8): Likewise. (__arm_vmaxq_s8): Likewise. (__arm_vhsubq_s8): Likewise. (__arm_vhsubq_n_s8): Likewise. (__arm_vhcaddq_rot90_s8): Likewise. (__arm_vhcaddq_rot270_s8): Likewise. (__arm_vhaddq_s8): Likewise. (__arm_vhaddq_n_s8): Likewise. (__arm_veorq_s8): Likewise. (__arm_vcaddq_rot90_s8): Likewise. (__arm_vcaddq_rot270_s8): Likewise. (__arm_vbrsrq_n_s8): Likewise. (__arm_vbicq_s8): Likewise. (__arm_vandq_s8): Likewise. (__arm_vaddvaq_s8): Likewise. (__arm_vaddq_n_s8): Likewise. (__arm_vabdq_s8): Likewise. (__arm_vshlq_n_s8): Likewise. (__arm_vrshrq_n_s8): Likewise. (__arm_vqshlq_n_s8): Likewise. (__arm_vsubq_u16): Likewise. (__arm_vsubq_n_u16): Likewise. (__arm_vrmulhq_u16): Likewise. (__arm_vrhaddq_u16): Likewise. (__arm_vqsubq_u16): Likewise. (__arm_vqsubq_n_u16): Likewise. (__arm_vqaddq_u16): Likewise. (__arm_vqaddq_n_u16): Likewise. (__arm_vorrq_u16): Likewise. (__arm_vornq_u16): Likewise. (__arm_vmulq_u16): Likewise. (__arm_vmulq_n_u16): Likewise. (__arm_vmulltq_int_u16): Likewise. (__arm_vmullbq_int_u16): Likewise. (__arm_vmulhq_u16): Likewise. (__arm_vmladavq_u16): Likewise. (__arm_vminvq_u16): Likewise. (__arm_vminq_u16): Likewise. (__arm_vmaxvq_u16): Likewise. (__arm_vmaxq_u16): Likewise. (__arm_vhsubq_u16): Likewise. (__arm_vhsubq_n_u16): Likewise. (__arm_vhaddq_u16): Likewise. (__arm_vhaddq_n_u16): Likewise. (__arm_veorq_u16): Likewise. (__arm_vcmpneq_n_u16): Likewise. (__arm_vcmphiq_u16): Likewise. (__arm_vcmphiq_n_u16): Likewise. (__arm_vcmpeqq_u16): Likewise. (__arm_vcmpeqq_n_u16): Likewise. (__arm_vcmpcsq_u16): Likewise. (__arm_vcmpcsq_n_u16): Likewise. (__arm_vcaddq_rot90_u16): Likewise. (__arm_vcaddq_rot270_u16): Likewise. (__arm_vbicq_u16): Likewise. (__arm_vandq_u16): Likewise. (__arm_vaddvq_p_u16): Likewise. (__arm_vaddvaq_u16): Likewise. (__arm_vaddq_n_u16): Likewise. (__arm_vabdq_u16): Likewise. (__arm_vshlq_r_u16): Likewise. (__arm_vrshlq_u16): Likewise. (__arm_vrshlq_n_u16): Likewise. (__arm_vqshlq_u16): Likewise. (__arm_vqshlq_r_u16): Likewise. (__arm_vqrshlq_u16): Likewise. (__arm_vqrshlq_n_u16): Likewise. (__arm_vminavq_s16): Likewise. (__arm_vminaq_s16): Likewise. (__arm_vmaxavq_s16): Likewise. (__arm_vmaxaq_s16): Likewise. (__arm_vbrsrq_n_u16): Likewise. (__arm_vshlq_n_u16): Likewise. (__arm_vrshrq_n_u16): Likewise. (__arm_vqshlq_n_u16): Likewise. (__arm_vcmpneq_n_s16): Likewise. (__arm_vcmpltq_s16): Likewise. (__arm_vcmpltq_n_s16): Likewise. (__arm_vcmpleq_s16): Likewise. (__arm_vcmpleq_n_s16): Likewise. (__arm_vcmpgtq_s16): Likewise. (__arm_vcmpgtq_n_s16): Likewise. (__arm_vcmpgeq_s16): Likewise. (__arm_vcmpgeq_n_s16): Likewise. (__arm_vcmpeqq_s16): Likewise. (__arm_vcmpeqq_n_s16): Likewise. (__arm_vqshluq_n_s16): Likewise. (__arm_vaddvq_p_s16): Likewise. (__arm_vsubq_s16): Likewise. (__arm_vsubq_n_s16): Likewise. (__arm_vshlq_r_s16): Likewise. (__arm_vrshlq_s16): Likewise. (__arm_vrshlq_n_s16): Likewise. (__arm_vrmulhq_s16): Likewise. (__arm_vrhaddq_s16): Likewise. (__arm_vqsubq_s16): Likewise. (__arm_vqsubq_n_s16): Likewise. (__arm_vqshlq_s16): Likewise. (__arm_vqshlq_r_s16): Likewise. (__arm_vqrshlq_s16): Likewise. (__arm_vqrshlq_n_s16): Likewise. (__arm_vqrdmulhq_s16): Likewise. (__arm_vqrdmulhq_n_s16): Likewise. (__arm_vqdmulhq_s16): Likewise. (__arm_vqdmulhq_n_s16): Likewise. (__arm_vqaddq_s16): Likewise. (__arm_vqaddq_n_s16): Likewise. (__arm_vorrq_s16): Likewise. (__arm_vornq_s16): Likewise. (__arm_vmulq_s16): Likewise. (__arm_vmulq_n_s16): Likewise. (__arm_vmulltq_int_s16): Likewise. (__arm_vmullbq_int_s16): Likewise. (__arm_vmulhq_s16): Likewise. (__arm_vmlsdavxq_s16): Likewise. (__arm_vmlsdavq_s16): Likewise. (__arm_vmladavxq_s16): Likewise. (__arm_vmladavq_s16): Likewise. (__arm_vminvq_s16): Likewise. (__arm_vminq_s16): Likewise. (__arm_vmaxvq_s16): Likewise. (__arm_vmaxq_s16): Likewise. (__arm_vhsubq_s16): Likewise. (__arm_vhsubq_n_s16): Likewise. (__arm_vhcaddq_rot90_s16): Likewise. (__arm_vhcaddq_rot270_s16): Likewise. (__arm_vhaddq_s16): Likewise. (__arm_vhaddq_n_s16): Likewise. (__arm_veorq_s16): Likewise. (__arm_vcaddq_rot90_s16): Likewise. (__arm_vcaddq_rot270_s16): Likewise. (__arm_vbrsrq_n_s16): Likewise. (__arm_vbicq_s16): Likewise. (__arm_vandq_s16): Likewise. (__arm_vaddvaq_s16): Likewise. (__arm_vaddq_n_s16): Likewise. (__arm_vabdq_s16): Likewise. (__arm_vshlq_n_s16): Likewise. (__arm_vrshrq_n_s16): Likewise. (__arm_vqshlq_n_s16): Likewise. (__arm_vsubq_u32): Likewise. (__arm_vsubq_n_u32): Likewise. (__arm_vrmulhq_u32): Likewise. (__arm_vrhaddq_u32): Likewise. (__arm_vqsubq_u32): Likewise. (__arm_vqsubq_n_u32): Likewise. (__arm_vqaddq_u32): Likewise. (__arm_vqaddq_n_u32): Likewise. (__arm_vorrq_u32): Likewise. (__arm_vornq_u32): Likewise. (__arm_vmulq_u32): Likewise. (__arm_vmulq_n_u32): Likewise. (__arm_vmulltq_int_u32): Likewise. (__arm_vmullbq_int_u32): Likewise. (__arm_vmulhq_u32): Likewise. (__arm_vmladavq_u32): Likewise. (__arm_vminvq_u32): Likewise. (__arm_vminq_u32): Likewise. (__arm_vmaxvq_u32): Likewise. (__arm_vmaxq_u32): Likewise. (__arm_vhsubq_u32): Likewise. (__arm_vhsubq_n_u32): Likewise. (__arm_vhaddq_u32): Likewise. (__arm_vhaddq_n_u32): Likewise. (__arm_veorq_u32): Likewise. (__arm_vcmpneq_n_u32): Likewise. (__arm_vcmphiq_u32): Likewise. (__arm_vcmphiq_n_u32): Likewise. (__arm_vcmpeqq_u32): Likewise. (__arm_vcmpeqq_n_u32): Likewise. (__arm_vcmpcsq_u32): Likewise. (__arm_vcmpcsq_n_u32): Likewise. (__arm_vcaddq_rot90_u32): Likewise. (__arm_vcaddq_rot270_u32): Likewise. (__arm_vbicq_u32): Likewise. (__arm_vandq_u32): Likewise. (__arm_vaddvq_p_u32): Likewise. (__arm_vaddvaq_u32): Likewise. (__arm_vaddq_n_u32): Likewise. (__arm_vabdq_u32): Likewise. (__arm_vshlq_r_u32): Likewise. (__arm_vrshlq_u32): Likewise. (__arm_vrshlq_n_u32): Likewise. (__arm_vqshlq_u32): Likewise. (__arm_vqshlq_r_u32): Likewise. (__arm_vqrshlq_u32): Likewise. (__arm_vqrshlq_n_u32): Likewise. (__arm_vminavq_s32): Likewise. (__arm_vminaq_s32): Likewise. (__arm_vmaxavq_s32): Likewise. (__arm_vmaxaq_s32): Likewise. (__arm_vbrsrq_n_u32): Likewise. (__arm_vshlq_n_u32): Likewise. (__arm_vrshrq_n_u32): Likewise. (__arm_vqshlq_n_u32): Likewise. (__arm_vcmpneq_n_s32): Likewise. (__arm_vcmpltq_s32): Likewise. (__arm_vcmpltq_n_s32): Likewise. (__arm_vcmpleq_s32): Likewise. (__arm_vcmpleq_n_s32): Likewise. (__arm_vcmpgtq_s32): Likewise. (__arm_vcmpgtq_n_s32): Likewise. (__arm_vcmpgeq_s32): Likewise. (__arm_vcmpgeq_n_s32): Likewise. (__arm_vcmpeqq_s32): Likewise. (__arm_vcmpeqq_n_s32): Likewise. (__arm_vqshluq_n_s32): Likewise. (__arm_vaddvq_p_s32): Likewise. (__arm_vsubq_s32): Likewise. (__arm_vsubq_n_s32): Likewise. (__arm_vshlq_r_s32): Likewise. (__arm_vrshlq_s32): Likewise. (__arm_vrshlq_n_s32): Likewise. (__arm_vrmulhq_s32): Likewise. (__arm_vrhaddq_s32): Likewise. (__arm_vqsubq_s32): Likewise. (__arm_vqsubq_n_s32): Likewise. (__arm_vqshlq_s32): Likewise. (__arm_vqshlq_r_s32): Likewise. (__arm_vqrshlq_s32): Likewise. (__arm_vqrshlq_n_s32): Likewise. (__arm_vqrdmulhq_s32): Likewise. (__arm_vqrdmulhq_n_s32): Likewise. (__arm_vqdmulhq_s32): Likewise. (__arm_vqdmulhq_n_s32): Likewise. (__arm_vqaddq_s32): Likewise. (__arm_vqaddq_n_s32): Likewise. (__arm_vorrq_s32): Likewise. (__arm_vornq_s32): Likewise. (__arm_vmulq_s32): Likewise. (__arm_vmulq_n_s32): Likewise. (__arm_vmulltq_int_s32): Likewise. (__arm_vmullbq_int_s32): Likewise. (__arm_vmulhq_s32): Likewise. (__arm_vmlsdavxq_s32): Likewise. (__arm_vmlsdavq_s32): Likewise. (__arm_vmladavxq_s32): Likewise. (__arm_vmladavq_s32): Likewise. (__arm_vminvq_s32): Likewise. (__arm_vminq_s32): Likewise. (__arm_vmaxvq_s32): Likewise. (__arm_vmaxq_s32): Likewise. (__arm_vhsubq_s32): Likewise. (__arm_vhsubq_n_s32): Likewise. (__arm_vhcaddq_rot90_s32): Likewise. (__arm_vhcaddq_rot270_s32): Likewise. (__arm_vhaddq_s32): Likewise. (__arm_vhaddq_n_s32): Likewise. (__arm_veorq_s32): Likewise. (__arm_vcaddq_rot90_s32): Likewise. (__arm_vcaddq_rot270_s32): Likewise. (__arm_vbrsrq_n_s32): Likewise. (__arm_vbicq_s32): Likewise. (__arm_vandq_s32): Likewise. (__arm_vaddvaq_s32): Likewise. (__arm_vaddq_n_s32): Likewise. (__arm_vabdq_s32): Likewise. (__arm_vshlq_n_s32): Likewise. (__arm_vrshrq_n_s32): Likewise. (__arm_vqshlq_n_s32): Likewise. (vsubq): Define polymorphic variant. (vsubq_n): Likewise. (vshlq_r): Likewise. (vrshlq_n): Likewise. (vrshlq): Likewise. (vrmulhq): Likewise. (vrhaddq): Likewise. (vqsubq_n): Likewise. (vqsubq): Likewise. (vqshlq): Likewise. (vqshlq_r): Likewise. (vqshluq): Likewise. (vrshrq_n): Likewise. (vshlq_n): Likewise. (vqshluq_n): Likewise. (vqshlq_n): Likewise. (vqrshlq_n): Likewise. (vqrshlq): Likewise. (vqrdmulhq_n): Likewise. (vqrdmulhq): Likewise. (vqdmulhq_n): Likewise. (vqdmulhq): Likewise. (vqaddq_n): Likewise. (vqaddq): Likewise. (vorrq_n): Likewise. (vorrq): Likewise. (vornq): Likewise. (vmulq_n): Likewise. (vmulq): Likewise. (vmulltq_int): Likewise. (vmullbq_int): Likewise. (vmulhq): Likewise. (vminq): Likewise. (vminaq): Likewise. (vmaxq): Likewise. (vmaxaq): Likewise. (vhsubq_n): Likewise. (vhsubq): Likewise. (vhcaddq_rot90): Likewise. (vhcaddq_rot270): Likewise. (vhaddq_n): Likewise. (vhaddq): Likewise. (veorq): Likewise. (vcaddq_rot90): Likewise. (vcaddq_rot270): Likewise. (vbrsrq_n): Likewise. (vbicq_n): Likewise. (vbicq): Likewise. (vaddq): Likewise. (vaddq_n): Likewise. (vandq): Likewise. (vabdq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. (BINOP_NONE_NONE_NONE): Likewise. (BINOP_NONE_NONE_UNONE): Likewise. (BINOP_UNONE_NONE_IMM): Likewise. (BINOP_UNONE_NONE_NONE): Likewise. (BINOP_UNONE_UNONE_IMM): Likewise. (BINOP_UNONE_UNONE_NONE): Likewise. (BINOP_UNONE_UNONE_UNONE): Likewise. * config/arm/constraints.md (Ra): Define constraint to check constant is in the range of 0 to 7. (Rg): Define constriant to check the constant is one among 1, 2, 4 and 8. * config/arm/mve.md (mve_vabdq_): Define RTL pattern. (mve_vaddq_n_): Likewise. (mve_vaddvaq_): Likewise. (mve_vaddvq_p_): Likewise. (mve_vandq_): Likewise. (mve_vbicq_): Likewise. (mve_vbrsrq_n_): Likewise. (mve_vcaddq_rot270_): Likewise. (mve_vcaddq_rot90_): Likewise. (mve_vcmpcsq_n_u): Likewise. (mve_vcmpcsq_u): Likewise. (mve_vcmpeqq_n_): Likewise. (mve_vcmpeqq_): Likewise. (mve_vcmpgeq_n_s): Likewise. (mve_vcmpgeq_s): Likewise. (mve_vcmpgtq_n_s): Likewise. (mve_vcmpgtq_s): Likewise. (mve_vcmphiq_n_u): Likewise. (mve_vcmphiq_u): Likewise. (mve_vcmpleq_n_s): Likewise. (mve_vcmpleq_s): Likewise. (mve_vcmpltq_n_s): Likewise. (mve_vcmpltq_s): Likewise. (mve_vcmpneq_n_): Likewise. (mve_vddupq_n_u): Likewise. (mve_veorq_): Likewise. (mve_vhaddq_n_): Likewise. (mve_vhaddq_): Likewise. (mve_vhcaddq_rot270_s): Likewise. (mve_vhcaddq_rot90_s): Likewise. (mve_vhsubq_n_): Likewise. (mve_vhsubq_): Likewise. (mve_vidupq_n_u): Likewise. (mve_vmaxaq_s): Likewise. (mve_vmaxavq_s): Likewise. (mve_vmaxq_): Likewise. (mve_vmaxvq_): Likewise. (mve_vminaq_s): Likewise. (mve_vminavq_s): Likewise. (mve_vminq_): Likewise. (mve_vminvq_): Likewise. (mve_vmladavq_): Likewise. (mve_vmladavxq_s): Likewise. (mve_vmlsdavq_s): Likewise. (mve_vmlsdavxq_s): Likewise. (mve_vmulhq_): Likewise. (mve_vmullbq_int_): Likewise. (mve_vmulltq_int_): Likewise. (mve_vmulq_n_): Likewise. (mve_vmulq_): Likewise. (mve_vornq_): Likewise. (mve_vorrq_): Likewise. (mve_vqaddq_n_): Likewise. (mve_vqaddq_): Likewise. (mve_vqdmulhq_n_s): Likewise. (mve_vqdmulhq_s): Likewise. (mve_vqrdmulhq_n_s): Likewise. (mve_vqrdmulhq_s): Likewise. (mve_vqrshlq_n_): Likewise. (mve_vqrshlq_): Likewise. (mve_vqshlq_n_): Likewise. (mve_vqshlq_r_): Likewise. (mve_vqshlq_): Likewise. (mve_vqshluq_n_s): Likewise. (mve_vqsubq_n_): Likewise. (mve_vqsubq_): Likewise. (mve_vrhaddq_): Likewise. (mve_vrmulhq_): Likewise. (mve_vrshlq_n_): Likewise. (mve_vrshlq_): Likewise. (mve_vrshrq_n_): Likewise. (mve_vshlq_n_): Likewise. (mve_vshlq_r_): Likewise. (mve_vsubq_n_): Likewise. (mve_vsubq_): Likewise. * config/arm/predicates.md (mve_imm_7): Define predicate to check the matching constraint Ra. (mve_imm_selective_upto_8): Define predicate to check the matching constraint Rg. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. --- gcc/ChangeLog | 868 +++++ gcc/config/arm/arm_mve.h | 3657 +++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 120 + gcc/config/arm/constraints.md | 14 +- gcc/config/arm/mve.md | 1205 ++++++- gcc/config/arm/predicates.md | 8 + gcc/testsuite/ChangeLog | 365 ++ .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 22 + 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100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9e6530..feecf92 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,874 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vsubq_u8): Define macro. + (vsubq_n_u8): Likewise. + (vrmulhq_u8): Likewise. + (vrhaddq_u8): Likewise. + (vqsubq_u8): Likewise. + (vqsubq_n_u8): Likewise. + (vqaddq_u8): Likewise. + (vqaddq_n_u8): Likewise. + (vorrq_u8): Likewise. + (vornq_u8): Likewise. + (vmulq_u8): Likewise. + (vmulq_n_u8): Likewise. + (vmulltq_int_u8): Likewise. + (vmullbq_int_u8): Likewise. + (vmulhq_u8): Likewise. + (vmladavq_u8): Likewise. + (vminvq_u8): Likewise. + (vminq_u8): Likewise. + (vmaxvq_u8): Likewise. + (vmaxq_u8): Likewise. + (vhsubq_u8): Likewise. + (vhsubq_n_u8): Likewise. + (vhaddq_u8): Likewise. + (vhaddq_n_u8): Likewise. + (veorq_u8): Likewise. + (vcmpneq_n_u8): Likewise. + (vcmphiq_u8): Likewise. + (vcmphiq_n_u8): Likewise. + (vcmpeqq_u8): Likewise. + (vcmpeqq_n_u8): Likewise. + (vcmpcsq_u8): Likewise. + (vcmpcsq_n_u8): Likewise. + (vcaddq_rot90_u8): Likewise. + (vcaddq_rot270_u8): Likewise. + (vbicq_u8): Likewise. + (vandq_u8): Likewise. + (vaddvq_p_u8): Likewise. + (vaddvaq_u8): Likewise. + (vaddq_n_u8): Likewise. + (vabdq_u8): Likewise. + (vshlq_r_u8): Likewise. + (vrshlq_u8): Likewise. + (vrshlq_n_u8): Likewise. + (vqshlq_u8): Likewise. + (vqshlq_r_u8): Likewise. + (vqrshlq_u8): Likewise. + (vqrshlq_n_u8): Likewise. + (vminavq_s8): Likewise. + (vminaq_s8): Likewise. + (vmaxavq_s8): Likewise. + (vmaxaq_s8): Likewise. + (vbrsrq_n_u8): Likewise. + (vshlq_n_u8): Likewise. + (vrshrq_n_u8): Likewise. + (vqshlq_n_u8): Likewise. + (vcmpneq_n_s8): Likewise. + (vcmpltq_s8): Likewise. + (vcmpltq_n_s8): Likewise. + (vcmpleq_s8): Likewise. + (vcmpleq_n_s8): Likewise. + (vcmpgtq_s8): Likewise. + (vcmpgtq_n_s8): Likewise. + (vcmpgeq_s8): Likewise. + (vcmpgeq_n_s8): Likewise. + (vcmpeqq_s8): Likewise. + (vcmpeqq_n_s8): Likewise. + (vqshluq_n_s8): Likewise. + (vaddvq_p_s8): Likewise. + (vsubq_s8): Likewise. + (vsubq_n_s8): Likewise. + (vshlq_r_s8): Likewise. + (vrshlq_s8): Likewise. + (vrshlq_n_s8): Likewise. + (vrmulhq_s8): Likewise. + (vrhaddq_s8): Likewise. + (vqsubq_s8): Likewise. + (vqsubq_n_s8): Likewise. + (vqshlq_s8): Likewise. + (vqshlq_r_s8): Likewise. + (vqrshlq_s8): Likewise. + (vqrshlq_n_s8): Likewise. + (vqrdmulhq_s8): Likewise. + (vqrdmulhq_n_s8): Likewise. + (vqdmulhq_s8): Likewise. + (vqdmulhq_n_s8): Likewise. + (vqaddq_s8): Likewise. + (vqaddq_n_s8): Likewise. + (vorrq_s8): Likewise. + (vornq_s8): Likewise. + (vmulq_s8): Likewise. + (vmulq_n_s8): Likewise. + (vmulltq_int_s8): Likewise. + (vmullbq_int_s8): Likewise. + (vmulhq_s8): Likewise. + (vmlsdavxq_s8): Likewise. + (vmlsdavq_s8): Likewise. + (vmladavxq_s8): Likewise. + (vmladavq_s8): Likewise. + (vminvq_s8): Likewise. + (vminq_s8): Likewise. + (vmaxvq_s8): Likewise. + (vmaxq_s8): Likewise. + (vhsubq_s8): Likewise. + (vhsubq_n_s8): Likewise. + (vhcaddq_rot90_s8): Likewise. + (vhcaddq_rot270_s8): Likewise. + (vhaddq_s8): Likewise. + (vhaddq_n_s8): Likewise. + (veorq_s8): Likewise. + (vcaddq_rot90_s8): Likewise. + (vcaddq_rot270_s8): Likewise. + (vbrsrq_n_s8): Likewise. + (vbicq_s8): Likewise. + (vandq_s8): Likewise. + (vaddvaq_s8): Likewise. + (vaddq_n_s8): Likewise. + (vabdq_s8): Likewise. + (vshlq_n_s8): Likewise. + (vrshrq_n_s8): Likewise. + (vqshlq_n_s8): Likewise. + (vsubq_u16): Likewise. + (vsubq_n_u16): Likewise. + (vrmulhq_u16): Likewise. + (vrhaddq_u16): Likewise. + (vqsubq_u16): Likewise. + (vqsubq_n_u16): Likewise. + (vqaddq_u16): Likewise. + (vqaddq_n_u16): Likewise. + (vorrq_u16): Likewise. + (vornq_u16): Likewise. + (vmulq_u16): Likewise. + (vmulq_n_u16): Likewise. + (vmulltq_int_u16): Likewise. + (vmullbq_int_u16): Likewise. + (vmulhq_u16): Likewise. + (vmladavq_u16): Likewise. + (vminvq_u16): Likewise. + (vminq_u16): Likewise. + (vmaxvq_u16): Likewise. + (vmaxq_u16): Likewise. + (vhsubq_u16): Likewise. + (vhsubq_n_u16): Likewise. + (vhaddq_u16): Likewise. + (vhaddq_n_u16): Likewise. + (veorq_u16): Likewise. + (vcmpneq_n_u16): Likewise. + (vcmphiq_u16): Likewise. + (vcmphiq_n_u16): Likewise. + (vcmpeqq_u16): Likewise. + (vcmpeqq_n_u16): Likewise. + (vcmpcsq_u16): Likewise. + (vcmpcsq_n_u16): Likewise. + (vcaddq_rot90_u16): Likewise. + (vcaddq_rot270_u16): Likewise. + (vbicq_u16): Likewise. + (vandq_u16): Likewise. + (vaddvq_p_u16): Likewise. + (vaddvaq_u16): Likewise. + (vaddq_n_u16): Likewise. + (vabdq_u16): Likewise. + (vshlq_r_u16): Likewise. + (vrshlq_u16): Likewise. + (vrshlq_n_u16): Likewise. + (vqshlq_u16): Likewise. + (vqshlq_r_u16): Likewise. + (vqrshlq_u16): Likewise. + (vqrshlq_n_u16): Likewise. + (vminavq_s16): Likewise. + (vminaq_s16): Likewise. + (vmaxavq_s16): Likewise. + (vmaxaq_s16): Likewise. + (vbrsrq_n_u16): Likewise. + (vshlq_n_u16): Likewise. + (vrshrq_n_u16): Likewise. + (vqshlq_n_u16): Likewise. + (vcmpneq_n_s16): Likewise. + (vcmpltq_s16): Likewise. + (vcmpltq_n_s16): Likewise. + (vcmpleq_s16): Likewise. + (vcmpleq_n_s16): Likewise. + (vcmpgtq_s16): Likewise. + (vcmpgtq_n_s16): Likewise. + (vcmpgeq_s16): Likewise. + (vcmpgeq_n_s16): Likewise. + (vcmpeqq_s16): Likewise. + (vcmpeqq_n_s16): Likewise. + (vqshluq_n_s16): Likewise. + (vaddvq_p_s16): Likewise. + (vsubq_s16): Likewise. + (vsubq_n_s16): Likewise. + (vshlq_r_s16): Likewise. + (vrshlq_s16): Likewise. + (vrshlq_n_s16): Likewise. + (vrmulhq_s16): Likewise. + (vrhaddq_s16): Likewise. + (vqsubq_s16): Likewise. + (vqsubq_n_s16): Likewise. + (vqshlq_s16): Likewise. + (vqshlq_r_s16): Likewise. + (vqrshlq_s16): Likewise. + (vqrshlq_n_s16): Likewise. + (vqrdmulhq_s16): Likewise. + (vqrdmulhq_n_s16): Likewise. + (vqdmulhq_s16): Likewise. + (vqdmulhq_n_s16): Likewise. + (vqaddq_s16): Likewise. + (vqaddq_n_s16): Likewise. + (vorrq_s16): Likewise. + (vornq_s16): Likewise. + (vmulq_s16): Likewise. + (vmulq_n_s16): Likewise. + (vmulltq_int_s16): Likewise. + (vmullbq_int_s16): Likewise. + (vmulhq_s16): Likewise. + (vmlsdavxq_s16): Likewise. + (vmlsdavq_s16): Likewise. + (vmladavxq_s16): Likewise. + (vmladavq_s16): Likewise. + (vminvq_s16): Likewise. + (vminq_s16): Likewise. + (vmaxvq_s16): Likewise. + (vmaxq_s16): Likewise. + (vhsubq_s16): Likewise. + (vhsubq_n_s16): Likewise. + (vhcaddq_rot90_s16): Likewise. + (vhcaddq_rot270_s16): Likewise. + (vhaddq_s16): Likewise. + (vhaddq_n_s16): Likewise. + (veorq_s16): Likewise. + (vcaddq_rot90_s16): Likewise. + (vcaddq_rot270_s16): Likewise. + (vbrsrq_n_s16): Likewise. + (vbicq_s16): Likewise. + (vandq_s16): Likewise. + (vaddvaq_s16): Likewise. + (vaddq_n_s16): Likewise. + (vabdq_s16): Likewise. + (vshlq_n_s16): Likewise. + (vrshrq_n_s16): Likewise. + (vqshlq_n_s16): Likewise. + (vsubq_u32): Likewise. + (vsubq_n_u32): Likewise. + (vrmulhq_u32): Likewise. + (vrhaddq_u32): Likewise. + (vqsubq_u32): Likewise. + (vqsubq_n_u32): Likewise. + (vqaddq_u32): Likewise. + (vqaddq_n_u32): Likewise. + (vorrq_u32): Likewise. + (vornq_u32): Likewise. + (vmulq_u32): Likewise. + (vmulq_n_u32): Likewise. + (vmulltq_int_u32): Likewise. + (vmullbq_int_u32): Likewise. + (vmulhq_u32): Likewise. + (vmladavq_u32): Likewise. + (vminvq_u32): Likewise. + (vminq_u32): Likewise. + (vmaxvq_u32): Likewise. + (vmaxq_u32): Likewise. + (vhsubq_u32): Likewise. + (vhsubq_n_u32): Likewise. + (vhaddq_u32): Likewise. + (vhaddq_n_u32): Likewise. + (veorq_u32): Likewise. + (vcmpneq_n_u32): Likewise. + (vcmphiq_u32): Likewise. + (vcmphiq_n_u32): Likewise. + (vcmpeqq_u32): Likewise. + (vcmpeqq_n_u32): Likewise. + (vcmpcsq_u32): Likewise. + (vcmpcsq_n_u32): Likewise. + (vcaddq_rot90_u32): Likewise. + (vcaddq_rot270_u32): Likewise. + (vbicq_u32): Likewise. + (vandq_u32): Likewise. + (vaddvq_p_u32): Likewise. + (vaddvaq_u32): Likewise. + (vaddq_n_u32): Likewise. + (vabdq_u32): Likewise. + (vshlq_r_u32): Likewise. + (vrshlq_u32): Likewise. + (vrshlq_n_u32): Likewise. + (vqshlq_u32): Likewise. + (vqshlq_r_u32): Likewise. + (vqrshlq_u32): Likewise. + (vqrshlq_n_u32): Likewise. + (vminavq_s32): Likewise. + (vminaq_s32): Likewise. + (vmaxavq_s32): Likewise. + (vmaxaq_s32): Likewise. + (vbrsrq_n_u32): Likewise. + (vshlq_n_u32): Likewise. + (vrshrq_n_u32): Likewise. + (vqshlq_n_u32): Likewise. + (vcmpneq_n_s32): Likewise. + (vcmpltq_s32): Likewise. + (vcmpltq_n_s32): Likewise. + (vcmpleq_s32): Likewise. + (vcmpleq_n_s32): Likewise. + (vcmpgtq_s32): Likewise. + (vcmpgtq_n_s32): Likewise. + (vcmpgeq_s32): Likewise. + (vcmpgeq_n_s32): Likewise. + (vcmpeqq_s32): Likewise. + (vcmpeqq_n_s32): Likewise. + (vqshluq_n_s32): Likewise. + (vaddvq_p_s32): Likewise. + (vsubq_s32): Likewise. + (vsubq_n_s32): Likewise. + (vshlq_r_s32): Likewise. + (vrshlq_s32): Likewise. + (vrshlq_n_s32): Likewise. + (vrmulhq_s32): Likewise. + (vrhaddq_s32): Likewise. + (vqsubq_s32): Likewise. + (vqsubq_n_s32): Likewise. + (vqshlq_s32): Likewise. + (vqshlq_r_s32): Likewise. + (vqrshlq_s32): Likewise. + (vqrshlq_n_s32): Likewise. + (vqrdmulhq_s32): Likewise. + (vqrdmulhq_n_s32): Likewise. + (vqdmulhq_s32): Likewise. + (vqdmulhq_n_s32): Likewise. + (vqaddq_s32): Likewise. + (vqaddq_n_s32): Likewise. + (vorrq_s32): Likewise. + (vornq_s32): Likewise. + (vmulq_s32): Likewise. + (vmulq_n_s32): Likewise. + (vmulltq_int_s32): Likewise. + (vmullbq_int_s32): Likewise. + (vmulhq_s32): Likewise. + (vmlsdavxq_s32): Likewise. + (vmlsdavq_s32): Likewise. + (vmladavxq_s32): Likewise. + (vmladavq_s32): Likewise. + (vminvq_s32): Likewise. + (vminq_s32): Likewise. + (vmaxvq_s32): Likewise. + (vmaxq_s32): Likewise. + (vhsubq_s32): Likewise. + (vhsubq_n_s32): Likewise. + (vhcaddq_rot90_s32): Likewise. + (vhcaddq_rot270_s32): Likewise. + (vhaddq_s32): Likewise. + (vhaddq_n_s32): Likewise. + (veorq_s32): Likewise. + (vcaddq_rot90_s32): Likewise. + (vcaddq_rot270_s32): Likewise. + (vbrsrq_n_s32): Likewise. + (vbicq_s32): Likewise. + (vandq_s32): Likewise. + (vaddvaq_s32): Likewise. + (vaddq_n_s32): Likewise. + (vabdq_s32): Likewise. + (vshlq_n_s32): Likewise. + (vrshrq_n_s32): Likewise. + (vqshlq_n_s32): Likewise. + (__arm_vsubq_u8): Define intrinsic. + (__arm_vsubq_n_u8): Likewise. + (__arm_vrmulhq_u8): Likewise. + (__arm_vrhaddq_u8): Likewise. + (__arm_vqsubq_u8): Likewise. + (__arm_vqsubq_n_u8): Likewise. + (__arm_vqaddq_u8): Likewise. + (__arm_vqaddq_n_u8): Likewise. + (__arm_vorrq_u8): Likewise. + (__arm_vornq_u8): Likewise. + (__arm_vmulq_u8): Likewise. + (__arm_vmulq_n_u8): Likewise. + (__arm_vmulltq_int_u8): Likewise. + (__arm_vmullbq_int_u8): Likewise. + (__arm_vmulhq_u8): Likewise. + (__arm_vmladavq_u8): Likewise. + (__arm_vminvq_u8): Likewise. + (__arm_vminq_u8): Likewise. + (__arm_vmaxvq_u8): Likewise. + (__arm_vmaxq_u8): Likewise. + (__arm_vhsubq_u8): Likewise. + (__arm_vhsubq_n_u8): Likewise. + (__arm_vhaddq_u8): Likewise. + (__arm_vhaddq_n_u8): Likewise. + (__arm_veorq_u8): Likewise. + (__arm_vcmpneq_n_u8): Likewise. + (__arm_vcmphiq_u8): Likewise. + (__arm_vcmphiq_n_u8): Likewise. + (__arm_vcmpeqq_u8): Likewise. + (__arm_vcmpeqq_n_u8): Likewise. + (__arm_vcmpcsq_u8): Likewise. + (__arm_vcmpcsq_n_u8): Likewise. + (__arm_vcaddq_rot90_u8): Likewise. + (__arm_vcaddq_rot270_u8): Likewise. + (__arm_vbicq_u8): Likewise. + (__arm_vandq_u8): Likewise. + (__arm_vaddvq_p_u8): Likewise. + (__arm_vaddvaq_u8): Likewise. + (__arm_vaddq_n_u8): Likewise. + (__arm_vabdq_u8): Likewise. + (__arm_vshlq_r_u8): Likewise. + (__arm_vrshlq_u8): Likewise. + (__arm_vrshlq_n_u8): Likewise. + (__arm_vqshlq_u8): Likewise. + (__arm_vqshlq_r_u8): Likewise. + (__arm_vqrshlq_u8): Likewise. + (__arm_vqrshlq_n_u8): Likewise. + (__arm_vminavq_s8): Likewise. + (__arm_vminaq_s8): Likewise. + (__arm_vmaxavq_s8): Likewise. + (__arm_vmaxaq_s8): Likewise. + (__arm_vbrsrq_n_u8): Likewise. + (__arm_vshlq_n_u8): Likewise. + (__arm_vrshrq_n_u8): Likewise. + (__arm_vqshlq_n_u8): Likewise. + (__arm_vcmpneq_n_s8): Likewise. + (__arm_vcmpltq_s8): Likewise. + (__arm_vcmpltq_n_s8): Likewise. + (__arm_vcmpleq_s8): Likewise. + (__arm_vcmpleq_n_s8): Likewise. + (__arm_vcmpgtq_s8): Likewise. + (__arm_vcmpgtq_n_s8): Likewise. + (__arm_vcmpgeq_s8): Likewise. + (__arm_vcmpgeq_n_s8): Likewise. + (__arm_vcmpeqq_s8): Likewise. + (__arm_vcmpeqq_n_s8): Likewise. + (__arm_vqshluq_n_s8): Likewise. + (__arm_vaddvq_p_s8): Likewise. + (__arm_vsubq_s8): Likewise. + (__arm_vsubq_n_s8): Likewise. + (__arm_vshlq_r_s8): Likewise. + (__arm_vrshlq_s8): Likewise. + (__arm_vrshlq_n_s8): Likewise. + (__arm_vrmulhq_s8): Likewise. + (__arm_vrhaddq_s8): Likewise. + (__arm_vqsubq_s8): Likewise. + (__arm_vqsubq_n_s8): Likewise. + (__arm_vqshlq_s8): Likewise. + (__arm_vqshlq_r_s8): Likewise. + (__arm_vqrshlq_s8): Likewise. + (__arm_vqrshlq_n_s8): Likewise. + (__arm_vqrdmulhq_s8): Likewise. + (__arm_vqrdmulhq_n_s8): Likewise. + (__arm_vqdmulhq_s8): Likewise. + (__arm_vqdmulhq_n_s8): Likewise. + (__arm_vqaddq_s8): Likewise. + (__arm_vqaddq_n_s8): Likewise. + (__arm_vorrq_s8): Likewise. + (__arm_vornq_s8): Likewise. + (__arm_vmulq_s8): Likewise. + (__arm_vmulq_n_s8): Likewise. + (__arm_vmulltq_int_s8): Likewise. + (__arm_vmullbq_int_s8): Likewise. + (__arm_vmulhq_s8): Likewise. + (__arm_vmlsdavxq_s8): Likewise. + (__arm_vmlsdavq_s8): Likewise. + (__arm_vmladavxq_s8): Likewise. + (__arm_vmladavq_s8): Likewise. + (__arm_vminvq_s8): Likewise. + (__arm_vminq_s8): Likewise. + (__arm_vmaxvq_s8): Likewise. + (__arm_vmaxq_s8): Likewise. + (__arm_vhsubq_s8): Likewise. + (__arm_vhsubq_n_s8): Likewise. + (__arm_vhcaddq_rot90_s8): Likewise. + (__arm_vhcaddq_rot270_s8): Likewise. + (__arm_vhaddq_s8): Likewise. + (__arm_vhaddq_n_s8): Likewise. + (__arm_veorq_s8): Likewise. + (__arm_vcaddq_rot90_s8): Likewise. + (__arm_vcaddq_rot270_s8): Likewise. + (__arm_vbrsrq_n_s8): Likewise. + (__arm_vbicq_s8): Likewise. + (__arm_vandq_s8): Likewise. + (__arm_vaddvaq_s8): Likewise. + (__arm_vaddq_n_s8): Likewise. + (__arm_vabdq_s8): Likewise. + (__arm_vshlq_n_s8): Likewise. + (__arm_vrshrq_n_s8): Likewise. + (__arm_vqshlq_n_s8): Likewise. + (__arm_vsubq_u16): Likewise. + (__arm_vsubq_n_u16): Likewise. + (__arm_vrmulhq_u16): Likewise. + (__arm_vrhaddq_u16): Likewise. + (__arm_vqsubq_u16): Likewise. + (__arm_vqsubq_n_u16): Likewise. + (__arm_vqaddq_u16): Likewise. + (__arm_vqaddq_n_u16): Likewise. + (__arm_vorrq_u16): Likewise. + (__arm_vornq_u16): Likewise. + (__arm_vmulq_u16): Likewise. + (__arm_vmulq_n_u16): Likewise. + (__arm_vmulltq_int_u16): Likewise. + (__arm_vmullbq_int_u16): Likewise. + (__arm_vmulhq_u16): Likewise. + (__arm_vmladavq_u16): Likewise. + (__arm_vminvq_u16): Likewise. + (__arm_vminq_u16): Likewise. + (__arm_vmaxvq_u16): Likewise. + (__arm_vmaxq_u16): Likewise. + (__arm_vhsubq_u16): Likewise. + (__arm_vhsubq_n_u16): Likewise. + (__arm_vhaddq_u16): Likewise. + (__arm_vhaddq_n_u16): Likewise. + (__arm_veorq_u16): Likewise. + (__arm_vcmpneq_n_u16): Likewise. + (__arm_vcmphiq_u16): Likewise. + (__arm_vcmphiq_n_u16): Likewise. + (__arm_vcmpeqq_u16): Likewise. + (__arm_vcmpeqq_n_u16): Likewise. + (__arm_vcmpcsq_u16): Likewise. + (__arm_vcmpcsq_n_u16): Likewise. + (__arm_vcaddq_rot90_u16): Likewise. + (__arm_vcaddq_rot270_u16): Likewise. + (__arm_vbicq_u16): Likewise. + (__arm_vandq_u16): Likewise. + (__arm_vaddvq_p_u16): Likewise. + (__arm_vaddvaq_u16): Likewise. + (__arm_vaddq_n_u16): Likewise. + (__arm_vabdq_u16): Likewise. + (__arm_vshlq_r_u16): Likewise. + (__arm_vrshlq_u16): Likewise. + (__arm_vrshlq_n_u16): Likewise. + (__arm_vqshlq_u16): Likewise. + (__arm_vqshlq_r_u16): Likewise. + (__arm_vqrshlq_u16): Likewise. + (__arm_vqrshlq_n_u16): Likewise. + (__arm_vminavq_s16): Likewise. + (__arm_vminaq_s16): Likewise. + (__arm_vmaxavq_s16): Likewise. + (__arm_vmaxaq_s16): Likewise. + (__arm_vbrsrq_n_u16): Likewise. + (__arm_vshlq_n_u16): Likewise. + (__arm_vrshrq_n_u16): Likewise. + (__arm_vqshlq_n_u16): Likewise. + (__arm_vcmpneq_n_s16): Likewise. + (__arm_vcmpltq_s16): Likewise. + (__arm_vcmpltq_n_s16): Likewise. + (__arm_vcmpleq_s16): Likewise. + (__arm_vcmpleq_n_s16): Likewise. + (__arm_vcmpgtq_s16): Likewise. + (__arm_vcmpgtq_n_s16): Likewise. + (__arm_vcmpgeq_s16): Likewise. + (__arm_vcmpgeq_n_s16): Likewise. + (__arm_vcmpeqq_s16): Likewise. + (__arm_vcmpeqq_n_s16): Likewise. + (__arm_vqshluq_n_s16): Likewise. + (__arm_vaddvq_p_s16): Likewise. + (__arm_vsubq_s16): Likewise. + (__arm_vsubq_n_s16): Likewise. + (__arm_vshlq_r_s16): Likewise. + (__arm_vrshlq_s16): Likewise. + (__arm_vrshlq_n_s16): Likewise. + (__arm_vrmulhq_s16): Likewise. + (__arm_vrhaddq_s16): Likewise. + (__arm_vqsubq_s16): Likewise. + (__arm_vqsubq_n_s16): Likewise. + (__arm_vqshlq_s16): Likewise. + (__arm_vqshlq_r_s16): Likewise. + (__arm_vqrshlq_s16): Likewise. + (__arm_vqrshlq_n_s16): Likewise. + (__arm_vqrdmulhq_s16): Likewise. + (__arm_vqrdmulhq_n_s16): Likewise. + (__arm_vqdmulhq_s16): Likewise. + (__arm_vqdmulhq_n_s16): Likewise. + (__arm_vqaddq_s16): Likewise. + (__arm_vqaddq_n_s16): Likewise. + (__arm_vorrq_s16): Likewise. + (__arm_vornq_s16): Likewise. + (__arm_vmulq_s16): Likewise. + (__arm_vmulq_n_s16): Likewise. + (__arm_vmulltq_int_s16): Likewise. + (__arm_vmullbq_int_s16): Likewise. + (__arm_vmulhq_s16): Likewise. + (__arm_vmlsdavxq_s16): Likewise. + (__arm_vmlsdavq_s16): Likewise. + (__arm_vmladavxq_s16): Likewise. + (__arm_vmladavq_s16): Likewise. + (__arm_vminvq_s16): Likewise. + (__arm_vminq_s16): Likewise. + (__arm_vmaxvq_s16): Likewise. + (__arm_vmaxq_s16): Likewise. + (__arm_vhsubq_s16): Likewise. + (__arm_vhsubq_n_s16): Likewise. + (__arm_vhcaddq_rot90_s16): Likewise. + (__arm_vhcaddq_rot270_s16): Likewise. + (__arm_vhaddq_s16): Likewise. + (__arm_vhaddq_n_s16): Likewise. + (__arm_veorq_s16): Likewise. + (__arm_vcaddq_rot90_s16): Likewise. + (__arm_vcaddq_rot270_s16): Likewise. + (__arm_vbrsrq_n_s16): Likewise. + (__arm_vbicq_s16): Likewise. + (__arm_vandq_s16): Likewise. + (__arm_vaddvaq_s16): Likewise. + (__arm_vaddq_n_s16): Likewise. + (__arm_vabdq_s16): Likewise. + (__arm_vshlq_n_s16): Likewise. + (__arm_vrshrq_n_s16): Likewise. + (__arm_vqshlq_n_s16): Likewise. + (__arm_vsubq_u32): Likewise. + (__arm_vsubq_n_u32): Likewise. + (__arm_vrmulhq_u32): Likewise. + (__arm_vrhaddq_u32): Likewise. + (__arm_vqsubq_u32): Likewise. + (__arm_vqsubq_n_u32): Likewise. + (__arm_vqaddq_u32): Likewise. + (__arm_vqaddq_n_u32): Likewise. + (__arm_vorrq_u32): Likewise. + (__arm_vornq_u32): Likewise. + (__arm_vmulq_u32): Likewise. + (__arm_vmulq_n_u32): Likewise. + (__arm_vmulltq_int_u32): Likewise. + (__arm_vmullbq_int_u32): Likewise. + (__arm_vmulhq_u32): Likewise. + (__arm_vmladavq_u32): Likewise. + (__arm_vminvq_u32): Likewise. + (__arm_vminq_u32): Likewise. + (__arm_vmaxvq_u32): Likewise. + (__arm_vmaxq_u32): Likewise. + (__arm_vhsubq_u32): Likewise. + (__arm_vhsubq_n_u32): Likewise. + (__arm_vhaddq_u32): Likewise. + (__arm_vhaddq_n_u32): Likewise. + (__arm_veorq_u32): Likewise. + (__arm_vcmpneq_n_u32): Likewise. + (__arm_vcmphiq_u32): Likewise. + (__arm_vcmphiq_n_u32): Likewise. + (__arm_vcmpeqq_u32): Likewise. + (__arm_vcmpeqq_n_u32): Likewise. + (__arm_vcmpcsq_u32): Likewise. + (__arm_vcmpcsq_n_u32): Likewise. + (__arm_vcaddq_rot90_u32): Likewise. + (__arm_vcaddq_rot270_u32): Likewise. + (__arm_vbicq_u32): Likewise. + (__arm_vandq_u32): Likewise. + (__arm_vaddvq_p_u32): Likewise. + (__arm_vaddvaq_u32): Likewise. + (__arm_vaddq_n_u32): Likewise. + (__arm_vabdq_u32): Likewise. + (__arm_vshlq_r_u32): Likewise. + (__arm_vrshlq_u32): Likewise. + (__arm_vrshlq_n_u32): Likewise. + (__arm_vqshlq_u32): Likewise. + (__arm_vqshlq_r_u32): Likewise. + (__arm_vqrshlq_u32): Likewise. + (__arm_vqrshlq_n_u32): Likewise. + (__arm_vminavq_s32): Likewise. + (__arm_vminaq_s32): Likewise. + (__arm_vmaxavq_s32): Likewise. + (__arm_vmaxaq_s32): Likewise. + (__arm_vbrsrq_n_u32): Likewise. + (__arm_vshlq_n_u32): Likewise. + (__arm_vrshrq_n_u32): Likewise. + (__arm_vqshlq_n_u32): Likewise. + (__arm_vcmpneq_n_s32): Likewise. + (__arm_vcmpltq_s32): Likewise. + (__arm_vcmpltq_n_s32): Likewise. + (__arm_vcmpleq_s32): Likewise. + (__arm_vcmpleq_n_s32): Likewise. + (__arm_vcmpgtq_s32): Likewise. + (__arm_vcmpgtq_n_s32): Likewise. + (__arm_vcmpgeq_s32): Likewise. + (__arm_vcmpgeq_n_s32): Likewise. + (__arm_vcmpeqq_s32): Likewise. + (__arm_vcmpeqq_n_s32): Likewise. + (__arm_vqshluq_n_s32): Likewise. + (__arm_vaddvq_p_s32): Likewise. + (__arm_vsubq_s32): Likewise. + (__arm_vsubq_n_s32): Likewise. + (__arm_vshlq_r_s32): Likewise. + (__arm_vrshlq_s32): Likewise. + (__arm_vrshlq_n_s32): Likewise. + (__arm_vrmulhq_s32): Likewise. + (__arm_vrhaddq_s32): Likewise. + (__arm_vqsubq_s32): Likewise. + (__arm_vqsubq_n_s32): Likewise. + (__arm_vqshlq_s32): Likewise. + (__arm_vqshlq_r_s32): Likewise. + (__arm_vqrshlq_s32): Likewise. + (__arm_vqrshlq_n_s32): Likewise. + (__arm_vqrdmulhq_s32): Likewise. + (__arm_vqrdmulhq_n_s32): Likewise. + (__arm_vqdmulhq_s32): Likewise. + (__arm_vqdmulhq_n_s32): Likewise. + (__arm_vqaddq_s32): Likewise. + (__arm_vqaddq_n_s32): Likewise. + (__arm_vorrq_s32): Likewise. + (__arm_vornq_s32): Likewise. + (__arm_vmulq_s32): Likewise. + (__arm_vmulq_n_s32): Likewise. + (__arm_vmulltq_int_s32): Likewise. + (__arm_vmullbq_int_s32): Likewise. + (__arm_vmulhq_s32): Likewise. + (__arm_vmlsdavxq_s32): Likewise. + (__arm_vmlsdavq_s32): Likewise. + (__arm_vmladavxq_s32): Likewise. + (__arm_vmladavq_s32): Likewise. + (__arm_vminvq_s32): Likewise. + (__arm_vminq_s32): Likewise. + (__arm_vmaxvq_s32): Likewise. + (__arm_vmaxq_s32): Likewise. + (__arm_vhsubq_s32): Likewise. + (__arm_vhsubq_n_s32): Likewise. + (__arm_vhcaddq_rot90_s32): Likewise. + (__arm_vhcaddq_rot270_s32): Likewise. + (__arm_vhaddq_s32): Likewise. + (__arm_vhaddq_n_s32): Likewise. + (__arm_veorq_s32): Likewise. + (__arm_vcaddq_rot90_s32): Likewise. + (__arm_vcaddq_rot270_s32): Likewise. + (__arm_vbrsrq_n_s32): Likewise. + (__arm_vbicq_s32): Likewise. + (__arm_vandq_s32): Likewise. + (__arm_vaddvaq_s32): Likewise. + (__arm_vaddq_n_s32): Likewise. + (__arm_vabdq_s32): Likewise. + (__arm_vshlq_n_s32): Likewise. + (__arm_vrshrq_n_s32): Likewise. + (__arm_vqshlq_n_s32): Likewise. + (vsubq): Define polymorphic variant. + (vsubq_n): Likewise. + (vshlq_r): Likewise. + (vrshlq_n): Likewise. + (vrshlq): Likewise. + (vrmulhq): Likewise. + (vrhaddq): Likewise. + (vqsubq_n): Likewise. + (vqsubq): Likewise. + (vqshlq): Likewise. + (vqshlq_r): Likewise. + (vqshluq): Likewise. + (vrshrq_n): Likewise. + (vshlq_n): Likewise. + (vqshluq_n): Likewise. + (vqshlq_n): Likewise. + (vqrshlq_n): Likewise. + (vqrshlq): Likewise. + (vqrdmulhq_n): Likewise. + (vqrdmulhq): Likewise. + (vqdmulhq_n): Likewise. + (vqdmulhq): Likewise. + (vqaddq_n): Likewise. + (vqaddq): Likewise. + (vorrq_n): Likewise. + (vorrq): Likewise. + (vornq): Likewise. + (vmulq_n): Likewise. + (vmulq): Likewise. + (vmulltq_int): Likewise. + (vmullbq_int): Likewise. + (vmulhq): Likewise. + (vminq): Likewise. + (vminaq): Likewise. + (vmaxq): Likewise. + (vmaxaq): Likewise. + (vhsubq_n): Likewise. + (vhsubq): Likewise. + (vhcaddq_rot90): Likewise. + (vhcaddq_rot270): Likewise. + (vhaddq_n): Likewise. + (vhaddq): Likewise. + (veorq): Likewise. + (vcaddq_rot90): Likewise. + (vcaddq_rot270): Likewise. + (vbrsrq_n): Likewise. + (vbicq_n): Likewise. + (vbicq): Likewise. + (vaddq): Likewise. + (vaddq_n): Likewise. + (vandq): Likewise. + (vabdq): Likewise. + * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. + (BINOP_NONE_NONE_NONE): Likewise. + (BINOP_NONE_NONE_UNONE): Likewise. + (BINOP_UNONE_NONE_IMM): Likewise. + (BINOP_UNONE_NONE_NONE): Likewise. + (BINOP_UNONE_UNONE_IMM): Likewise. + (BINOP_UNONE_UNONE_NONE): Likewise. + (BINOP_UNONE_UNONE_UNONE): Likewise. + * config/arm/constraints.md (Ra): Define constraint to check constant is + in the range of 0 to 7. + (Rg): Define constriant to check the constant is one among 1, 2, 4 + and 8. + * config/arm/mve.md (mve_vabdq_): Define RTL pattern. + (mve_vaddq_n_): Likewise. + (mve_vaddvaq_): Likewise. + (mve_vaddvq_p_): Likewise. + (mve_vandq_): Likewise. + (mve_vbicq_): Likewise. + (mve_vbrsrq_n_): Likewise. + (mve_vcaddq_rot270_): Likewise. + (mve_vcaddq_rot90_): Likewise. + (mve_vcmpcsq_n_u): Likewise. + (mve_vcmpcsq_u): Likewise. + (mve_vcmpeqq_n_): Likewise. + (mve_vcmpeqq_): Likewise. + (mve_vcmpgeq_n_s): Likewise. + (mve_vcmpgeq_s): Likewise. + (mve_vcmpgtq_n_s): Likewise. + (mve_vcmpgtq_s): Likewise. + (mve_vcmphiq_n_u): Likewise. + (mve_vcmphiq_u): Likewise. + (mve_vcmpleq_n_s): Likewise. + (mve_vcmpleq_s): Likewise. + (mve_vcmpltq_n_s): Likewise. + (mve_vcmpltq_s): Likewise. + (mve_vcmpneq_n_): Likewise. + (mve_vddupq_n_u): Likewise. + (mve_veorq_): Likewise. + (mve_vhaddq_n_): Likewise. + (mve_vhaddq_): Likewise. + (mve_vhcaddq_rot270_s): Likewise. + (mve_vhcaddq_rot90_s): Likewise. + (mve_vhsubq_n_): Likewise. + (mve_vhsubq_): Likewise. + (mve_vidupq_n_u): Likewise. + (mve_vmaxaq_s): Likewise. + (mve_vmaxavq_s): Likewise. + (mve_vmaxq_): Likewise. + (mve_vmaxvq_): Likewise. + (mve_vminaq_s): Likewise. + (mve_vminavq_s): Likewise. + (mve_vminq_): Likewise. + (mve_vminvq_): Likewise. + (mve_vmladavq_): Likewise. + (mve_vmladavxq_s): Likewise. + (mve_vmlsdavq_s): Likewise. + (mve_vmlsdavxq_s): Likewise. + (mve_vmulhq_): Likewise. + (mve_vmullbq_int_): Likewise. + (mve_vmulltq_int_): Likewise. + (mve_vmulq_n_): Likewise. + (mve_vmulq_): Likewise. + (mve_vornq_): Likewise. + (mve_vorrq_): Likewise. + (mve_vqaddq_n_): Likewise. + (mve_vqaddq_): Likewise. + (mve_vqdmulhq_n_s): Likewise. + (mve_vqdmulhq_s): Likewise. + (mve_vqrdmulhq_n_s): Likewise. + (mve_vqrdmulhq_s): Likewise. + (mve_vqrshlq_n_): Likewise. + (mve_vqrshlq_): Likewise. + (mve_vqshlq_n_): Likewise. + (mve_vqshlq_r_): Likewise. + (mve_vqshlq_): Likewise. + (mve_vqshluq_n_s): Likewise. + (mve_vqsubq_n_): Likewise. + (mve_vqsubq_): Likewise. + (mve_vrhaddq_): Likewise. + (mve_vrmulhq_): Likewise. + (mve_vrshlq_n_): Likewise. + (mve_vrshlq_): Likewise. + (mve_vrshrq_n_): Likewise. + (mve_vshlq_n_): Likewise. + (mve_vshlq_r_): Likewise. + (mve_vsubq_n_): Likewise. + (mve_vsubq_): Likewise. + * config/arm/predicates.md (mve_imm_7): Define predicate to check + the matching constraint Ra. + (mve_imm_selective_upto_8): Define predicate to check the matching + constraint Rg. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index ef0d2ac..eb81a02 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -239,6 +239,366 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vshlq_u8(__a, __b) __arm_vshlq_u8(__a, __b) #define vshlq_u16(__a, __b) __arm_vshlq_u16(__a, __b) #define vshlq_u32(__a, __b) __arm_vshlq_u32(__a, __b) +#define vsubq_u8(__a, __b) __arm_vsubq_u8(__a, __b) +#define vsubq_n_u8(__a, __b) __arm_vsubq_n_u8(__a, __b) +#define vrmulhq_u8(__a, __b) __arm_vrmulhq_u8(__a, __b) +#define vrhaddq_u8(__a, __b) __arm_vrhaddq_u8(__a, __b) +#define vqsubq_u8(__a, __b) __arm_vqsubq_u8(__a, __b) +#define vqsubq_n_u8(__a, __b) __arm_vqsubq_n_u8(__a, __b) +#define vqaddq_u8(__a, __b) __arm_vqaddq_u8(__a, __b) +#define vqaddq_n_u8(__a, __b) __arm_vqaddq_n_u8(__a, __b) +#define vorrq_u8(__a, __b) __arm_vorrq_u8(__a, __b) +#define vornq_u8(__a, __b) __arm_vornq_u8(__a, __b) +#define vmulq_u8(__a, __b) __arm_vmulq_u8(__a, __b) +#define vmulq_n_u8(__a, __b) __arm_vmulq_n_u8(__a, __b) +#define vmulltq_int_u8(__a, __b) __arm_vmulltq_int_u8(__a, __b) +#define vmullbq_int_u8(__a, __b) __arm_vmullbq_int_u8(__a, __b) +#define vmulhq_u8(__a, __b) __arm_vmulhq_u8(__a, __b) +#define vmladavq_u8(__a, __b) __arm_vmladavq_u8(__a, __b) +#define vminvq_u8(__a, __b) __arm_vminvq_u8(__a, __b) +#define vminq_u8(__a, __b) __arm_vminq_u8(__a, __b) +#define vmaxvq_u8(__a, __b) __arm_vmaxvq_u8(__a, __b) +#define vmaxq_u8(__a, __b) __arm_vmaxq_u8(__a, __b) +#define vhsubq_u8(__a, __b) __arm_vhsubq_u8(__a, __b) +#define vhsubq_n_u8(__a, __b) __arm_vhsubq_n_u8(__a, __b) +#define vhaddq_u8(__a, __b) __arm_vhaddq_u8(__a, __b) +#define vhaddq_n_u8(__a, __b) __arm_vhaddq_n_u8(__a, __b) +#define veorq_u8(__a, __b) __arm_veorq_u8(__a, __b) +#define vcmpneq_n_u8(__a, __b) __arm_vcmpneq_n_u8(__a, __b) +#define vcmphiq_u8(__a, __b) __arm_vcmphiq_u8(__a, __b) +#define vcmphiq_n_u8(__a, __b) __arm_vcmphiq_n_u8(__a, __b) +#define vcmpeqq_u8(__a, __b) __arm_vcmpeqq_u8(__a, __b) +#define vcmpeqq_n_u8(__a, __b) __arm_vcmpeqq_n_u8(__a, __b) +#define vcmpcsq_u8(__a, __b) __arm_vcmpcsq_u8(__a, __b) +#define vcmpcsq_n_u8(__a, __b) __arm_vcmpcsq_n_u8(__a, __b) +#define vcaddq_rot90_u8(__a, __b) __arm_vcaddq_rot90_u8(__a, __b) +#define vcaddq_rot270_u8(__a, __b) __arm_vcaddq_rot270_u8(__a, __b) +#define vbicq_u8(__a, __b) __arm_vbicq_u8(__a, __b) +#define vandq_u8(__a, __b) __arm_vandq_u8(__a, __b) +#define vaddvq_p_u8(__a, __p) __arm_vaddvq_p_u8(__a, __p) +#define vaddvaq_u8(__a, __b) __arm_vaddvaq_u8(__a, __b) +#define vaddq_n_u8(__a, __b) __arm_vaddq_n_u8(__a, __b) +#define vabdq_u8(__a, __b) __arm_vabdq_u8(__a, __b) +#define vshlq_r_u8(__a, __b) __arm_vshlq_r_u8(__a, __b) +#define vrshlq_u8(__a, __b) __arm_vrshlq_u8(__a, __b) +#define vrshlq_n_u8(__a, __b) __arm_vrshlq_n_u8(__a, __b) +#define vqshlq_u8(__a, __b) __arm_vqshlq_u8(__a, __b) +#define vqshlq_r_u8(__a, __b) __arm_vqshlq_r_u8(__a, __b) +#define vqrshlq_u8(__a, __b) __arm_vqrshlq_u8(__a, __b) +#define vqrshlq_n_u8(__a, __b) __arm_vqrshlq_n_u8(__a, __b) +#define vminavq_s8(__a, __b) __arm_vminavq_s8(__a, __b) +#define vminaq_s8(__a, __b) __arm_vminaq_s8(__a, __b) +#define vmaxavq_s8(__a, __b) __arm_vmaxavq_s8(__a, __b) +#define vmaxaq_s8(__a, __b) __arm_vmaxaq_s8(__a, __b) +#define vbrsrq_n_u8(__a, __b) __arm_vbrsrq_n_u8(__a, __b) +#define vshlq_n_u8(__a, __imm) __arm_vshlq_n_u8(__a, __imm) +#define vrshrq_n_u8(__a, __imm) __arm_vrshrq_n_u8(__a, __imm) +#define vqshlq_n_u8(__a, __imm) __arm_vqshlq_n_u8(__a, __imm) +#define vcmpneq_n_s8(__a, __b) __arm_vcmpneq_n_s8(__a, __b) +#define vcmpltq_s8(__a, __b) __arm_vcmpltq_s8(__a, __b) +#define vcmpltq_n_s8(__a, __b) __arm_vcmpltq_n_s8(__a, __b) +#define vcmpleq_s8(__a, __b) __arm_vcmpleq_s8(__a, __b) +#define vcmpleq_n_s8(__a, __b) __arm_vcmpleq_n_s8(__a, __b) +#define vcmpgtq_s8(__a, __b) __arm_vcmpgtq_s8(__a, __b) +#define vcmpgtq_n_s8(__a, __b) __arm_vcmpgtq_n_s8(__a, __b) +#define vcmpgeq_s8(__a, __b) __arm_vcmpgeq_s8(__a, __b) +#define vcmpgeq_n_s8(__a, __b) __arm_vcmpgeq_n_s8(__a, __b) +#define vcmpeqq_s8(__a, __b) __arm_vcmpeqq_s8(__a, __b) +#define vcmpeqq_n_s8(__a, __b) __arm_vcmpeqq_n_s8(__a, __b) +#define vqshluq_n_s8(__a, __imm) __arm_vqshluq_n_s8(__a, __imm) +#define vaddvq_p_s8(__a, __p) __arm_vaddvq_p_s8(__a, __p) +#define vsubq_s8(__a, __b) __arm_vsubq_s8(__a, __b) +#define vsubq_n_s8(__a, __b) __arm_vsubq_n_s8(__a, __b) +#define vshlq_r_s8(__a, __b) __arm_vshlq_r_s8(__a, __b) +#define vrshlq_s8(__a, __b) __arm_vrshlq_s8(__a, __b) +#define vrshlq_n_s8(__a, __b) __arm_vrshlq_n_s8(__a, __b) +#define vrmulhq_s8(__a, __b) __arm_vrmulhq_s8(__a, __b) +#define vrhaddq_s8(__a, __b) __arm_vrhaddq_s8(__a, __b) +#define vqsubq_s8(__a, __b) __arm_vqsubq_s8(__a, __b) +#define vqsubq_n_s8(__a, __b) __arm_vqsubq_n_s8(__a, __b) +#define vqshlq_s8(__a, __b) __arm_vqshlq_s8(__a, __b) +#define vqshlq_r_s8(__a, __b) __arm_vqshlq_r_s8(__a, __b) +#define vqrshlq_s8(__a, __b) __arm_vqrshlq_s8(__a, __b) +#define vqrshlq_n_s8(__a, __b) __arm_vqrshlq_n_s8(__a, __b) +#define vqrdmulhq_s8(__a, __b) __arm_vqrdmulhq_s8(__a, __b) +#define vqrdmulhq_n_s8(__a, __b) __arm_vqrdmulhq_n_s8(__a, __b) +#define vqdmulhq_s8(__a, __b) __arm_vqdmulhq_s8(__a, __b) +#define vqdmulhq_n_s8(__a, __b) __arm_vqdmulhq_n_s8(__a, __b) +#define vqaddq_s8(__a, __b) __arm_vqaddq_s8(__a, __b) +#define vqaddq_n_s8(__a, __b) __arm_vqaddq_n_s8(__a, __b) +#define vorrq_s8(__a, __b) __arm_vorrq_s8(__a, __b) +#define vornq_s8(__a, __b) __arm_vornq_s8(__a, __b) +#define vmulq_s8(__a, __b) __arm_vmulq_s8(__a, __b) +#define vmulq_n_s8(__a, __b) __arm_vmulq_n_s8(__a, __b) +#define vmulltq_int_s8(__a, __b) __arm_vmulltq_int_s8(__a, __b) +#define vmullbq_int_s8(__a, __b) __arm_vmullbq_int_s8(__a, __b) +#define vmulhq_s8(__a, __b) __arm_vmulhq_s8(__a, __b) +#define vmlsdavxq_s8(__a, __b) __arm_vmlsdavxq_s8(__a, __b) +#define vmlsdavq_s8(__a, __b) __arm_vmlsdavq_s8(__a, __b) +#define vmladavxq_s8(__a, __b) __arm_vmladavxq_s8(__a, __b) +#define vmladavq_s8(__a, __b) __arm_vmladavq_s8(__a, __b) +#define vminvq_s8(__a, __b) __arm_vminvq_s8(__a, __b) +#define vminq_s8(__a, __b) __arm_vminq_s8(__a, __b) +#define vmaxvq_s8(__a, __b) __arm_vmaxvq_s8(__a, __b) +#define vmaxq_s8(__a, __b) __arm_vmaxq_s8(__a, __b) +#define vhsubq_s8(__a, __b) __arm_vhsubq_s8(__a, __b) +#define vhsubq_n_s8(__a, __b) __arm_vhsubq_n_s8(__a, __b) +#define vhcaddq_rot90_s8(__a, __b) __arm_vhcaddq_rot90_s8(__a, __b) +#define vhcaddq_rot270_s8(__a, __b) __arm_vhcaddq_rot270_s8(__a, __b) +#define vhaddq_s8(__a, __b) __arm_vhaddq_s8(__a, __b) +#define vhaddq_n_s8(__a, __b) __arm_vhaddq_n_s8(__a, __b) +#define veorq_s8(__a, __b) __arm_veorq_s8(__a, __b) +#define vcaddq_rot90_s8(__a, __b) __arm_vcaddq_rot90_s8(__a, __b) +#define vcaddq_rot270_s8(__a, __b) __arm_vcaddq_rot270_s8(__a, __b) +#define vbrsrq_n_s8(__a, __b) __arm_vbrsrq_n_s8(__a, __b) +#define vbicq_s8(__a, __b) __arm_vbicq_s8(__a, __b) +#define vandq_s8(__a, __b) __arm_vandq_s8(__a, __b) +#define vaddvaq_s8(__a, __b) __arm_vaddvaq_s8(__a, __b) +#define vaddq_n_s8(__a, __b) __arm_vaddq_n_s8(__a, __b) +#define vabdq_s8(__a, __b) __arm_vabdq_s8(__a, __b) +#define vshlq_n_s8(__a, __imm) __arm_vshlq_n_s8(__a, __imm) +#define vrshrq_n_s8(__a, __imm) __arm_vrshrq_n_s8(__a, __imm) +#define vqshlq_n_s8(__a, __imm) __arm_vqshlq_n_s8(__a, __imm) +#define vsubq_u16(__a, __b) __arm_vsubq_u16(__a, __b) +#define vsubq_n_u16(__a, __b) __arm_vsubq_n_u16(__a, __b) +#define vrmulhq_u16(__a, __b) __arm_vrmulhq_u16(__a, __b) +#define vrhaddq_u16(__a, __b) __arm_vrhaddq_u16(__a, __b) +#define vqsubq_u16(__a, __b) __arm_vqsubq_u16(__a, __b) +#define vqsubq_n_u16(__a, __b) __arm_vqsubq_n_u16(__a, __b) +#define vqaddq_u16(__a, __b) __arm_vqaddq_u16(__a, __b) +#define vqaddq_n_u16(__a, __b) __arm_vqaddq_n_u16(__a, __b) +#define vorrq_u16(__a, __b) __arm_vorrq_u16(__a, __b) +#define vornq_u16(__a, __b) __arm_vornq_u16(__a, __b) +#define vmulq_u16(__a, __b) __arm_vmulq_u16(__a, __b) +#define vmulq_n_u16(__a, __b) __arm_vmulq_n_u16(__a, __b) +#define vmulltq_int_u16(__a, __b) __arm_vmulltq_int_u16(__a, __b) +#define vmullbq_int_u16(__a, __b) __arm_vmullbq_int_u16(__a, __b) +#define vmulhq_u16(__a, __b) __arm_vmulhq_u16(__a, __b) +#define vmladavq_u16(__a, __b) __arm_vmladavq_u16(__a, __b) +#define vminvq_u16(__a, __b) __arm_vminvq_u16(__a, __b) +#define vminq_u16(__a, __b) __arm_vminq_u16(__a, __b) +#define vmaxvq_u16(__a, __b) __arm_vmaxvq_u16(__a, __b) +#define vmaxq_u16(__a, __b) __arm_vmaxq_u16(__a, __b) +#define vhsubq_u16(__a, __b) __arm_vhsubq_u16(__a, __b) +#define vhsubq_n_u16(__a, __b) __arm_vhsubq_n_u16(__a, __b) +#define vhaddq_u16(__a, __b) __arm_vhaddq_u16(__a, __b) +#define vhaddq_n_u16(__a, __b) __arm_vhaddq_n_u16(__a, __b) +#define veorq_u16(__a, __b) __arm_veorq_u16(__a, __b) +#define vcmpneq_n_u16(__a, __b) __arm_vcmpneq_n_u16(__a, __b) +#define vcmphiq_u16(__a, __b) __arm_vcmphiq_u16(__a, __b) +#define vcmphiq_n_u16(__a, __b) __arm_vcmphiq_n_u16(__a, __b) +#define vcmpeqq_u16(__a, __b) __arm_vcmpeqq_u16(__a, __b) +#define vcmpeqq_n_u16(__a, __b) __arm_vcmpeqq_n_u16(__a, __b) +#define vcmpcsq_u16(__a, __b) __arm_vcmpcsq_u16(__a, __b) +#define vcmpcsq_n_u16(__a, __b) __arm_vcmpcsq_n_u16(__a, __b) +#define vcaddq_rot90_u16(__a, __b) __arm_vcaddq_rot90_u16(__a, __b) +#define vcaddq_rot270_u16(__a, __b) __arm_vcaddq_rot270_u16(__a, __b) +#define vbicq_u16(__a, __b) __arm_vbicq_u16(__a, __b) +#define vandq_u16(__a, __b) __arm_vandq_u16(__a, __b) +#define vaddvq_p_u16(__a, __p) __arm_vaddvq_p_u16(__a, __p) +#define vaddvaq_u16(__a, __b) __arm_vaddvaq_u16(__a, __b) +#define vaddq_n_u16(__a, __b) __arm_vaddq_n_u16(__a, __b) +#define vabdq_u16(__a, __b) __arm_vabdq_u16(__a, __b) +#define vshlq_r_u16(__a, __b) __arm_vshlq_r_u16(__a, __b) +#define vrshlq_u16(__a, __b) __arm_vrshlq_u16(__a, __b) +#define vrshlq_n_u16(__a, __b) __arm_vrshlq_n_u16(__a, __b) +#define vqshlq_u16(__a, __b) __arm_vqshlq_u16(__a, __b) +#define vqshlq_r_u16(__a, __b) __arm_vqshlq_r_u16(__a, __b) +#define vqrshlq_u16(__a, __b) __arm_vqrshlq_u16(__a, __b) +#define vqrshlq_n_u16(__a, __b) __arm_vqrshlq_n_u16(__a, __b) +#define vminavq_s16(__a, __b) __arm_vminavq_s16(__a, __b) +#define vminaq_s16(__a, __b) __arm_vminaq_s16(__a, __b) +#define vmaxavq_s16(__a, __b) __arm_vmaxavq_s16(__a, __b) +#define vmaxaq_s16(__a, __b) __arm_vmaxaq_s16(__a, __b) +#define vbrsrq_n_u16(__a, __b) __arm_vbrsrq_n_u16(__a, __b) +#define vshlq_n_u16(__a, __imm) __arm_vshlq_n_u16(__a, __imm) +#define vrshrq_n_u16(__a, __imm) __arm_vrshrq_n_u16(__a, __imm) +#define vqshlq_n_u16(__a, __imm) __arm_vqshlq_n_u16(__a, __imm) +#define vcmpneq_n_s16(__a, __b) __arm_vcmpneq_n_s16(__a, __b) +#define vcmpltq_s16(__a, __b) __arm_vcmpltq_s16(__a, __b) +#define vcmpltq_n_s16(__a, __b) __arm_vcmpltq_n_s16(__a, __b) +#define vcmpleq_s16(__a, __b) __arm_vcmpleq_s16(__a, __b) +#define vcmpleq_n_s16(__a, __b) __arm_vcmpleq_n_s16(__a, __b) +#define vcmpgtq_s16(__a, __b) __arm_vcmpgtq_s16(__a, __b) +#define vcmpgtq_n_s16(__a, __b) __arm_vcmpgtq_n_s16(__a, __b) +#define vcmpgeq_s16(__a, __b) __arm_vcmpgeq_s16(__a, __b) +#define vcmpgeq_n_s16(__a, __b) __arm_vcmpgeq_n_s16(__a, __b) +#define vcmpeqq_s16(__a, __b) __arm_vcmpeqq_s16(__a, __b) +#define vcmpeqq_n_s16(__a, __b) __arm_vcmpeqq_n_s16(__a, __b) +#define vqshluq_n_s16(__a, __imm) __arm_vqshluq_n_s16(__a, __imm) +#define vaddvq_p_s16(__a, __p) __arm_vaddvq_p_s16(__a, __p) +#define vsubq_s16(__a, __b) __arm_vsubq_s16(__a, __b) +#define vsubq_n_s16(__a, __b) __arm_vsubq_n_s16(__a, __b) +#define vshlq_r_s16(__a, __b) __arm_vshlq_r_s16(__a, __b) +#define vrshlq_s16(__a, __b) __arm_vrshlq_s16(__a, __b) +#define vrshlq_n_s16(__a, __b) __arm_vrshlq_n_s16(__a, __b) +#define vrmulhq_s16(__a, __b) __arm_vrmulhq_s16(__a, __b) +#define vrhaddq_s16(__a, __b) __arm_vrhaddq_s16(__a, __b) +#define vqsubq_s16(__a, __b) __arm_vqsubq_s16(__a, __b) +#define vqsubq_n_s16(__a, __b) __arm_vqsubq_n_s16(__a, __b) +#define vqshlq_s16(__a, __b) __arm_vqshlq_s16(__a, __b) +#define vqshlq_r_s16(__a, __b) __arm_vqshlq_r_s16(__a, __b) +#define vqrshlq_s16(__a, __b) __arm_vqrshlq_s16(__a, __b) +#define vqrshlq_n_s16(__a, __b) __arm_vqrshlq_n_s16(__a, __b) +#define vqrdmulhq_s16(__a, __b) __arm_vqrdmulhq_s16(__a, __b) +#define vqrdmulhq_n_s16(__a, __b) __arm_vqrdmulhq_n_s16(__a, __b) +#define vqdmulhq_s16(__a, __b) __arm_vqdmulhq_s16(__a, __b) +#define vqdmulhq_n_s16(__a, __b) __arm_vqdmulhq_n_s16(__a, __b) +#define vqaddq_s16(__a, __b) __arm_vqaddq_s16(__a, __b) +#define vqaddq_n_s16(__a, __b) __arm_vqaddq_n_s16(__a, __b) +#define vorrq_s16(__a, __b) __arm_vorrq_s16(__a, __b) +#define vornq_s16(__a, __b) __arm_vornq_s16(__a, __b) +#define vmulq_s16(__a, __b) __arm_vmulq_s16(__a, __b) +#define vmulq_n_s16(__a, __b) __arm_vmulq_n_s16(__a, __b) +#define vmulltq_int_s16(__a, __b) __arm_vmulltq_int_s16(__a, __b) +#define vmullbq_int_s16(__a, __b) __arm_vmullbq_int_s16(__a, __b) +#define vmulhq_s16(__a, __b) __arm_vmulhq_s16(__a, __b) +#define vmlsdavxq_s16(__a, __b) __arm_vmlsdavxq_s16(__a, __b) +#define vmlsdavq_s16(__a, __b) __arm_vmlsdavq_s16(__a, __b) +#define vmladavxq_s16(__a, __b) __arm_vmladavxq_s16(__a, __b) +#define vmladavq_s16(__a, __b) __arm_vmladavq_s16(__a, __b) +#define vminvq_s16(__a, __b) __arm_vminvq_s16(__a, __b) +#define vminq_s16(__a, __b) __arm_vminq_s16(__a, __b) +#define vmaxvq_s16(__a, __b) __arm_vmaxvq_s16(__a, __b) +#define vmaxq_s16(__a, __b) __arm_vmaxq_s16(__a, __b) +#define vhsubq_s16(__a, __b) __arm_vhsubq_s16(__a, __b) +#define vhsubq_n_s16(__a, __b) __arm_vhsubq_n_s16(__a, __b) +#define vhcaddq_rot90_s16(__a, __b) __arm_vhcaddq_rot90_s16(__a, __b) +#define vhcaddq_rot270_s16(__a, __b) __arm_vhcaddq_rot270_s16(__a, __b) +#define vhaddq_s16(__a, __b) __arm_vhaddq_s16(__a, __b) +#define vhaddq_n_s16(__a, __b) __arm_vhaddq_n_s16(__a, __b) +#define veorq_s16(__a, __b) __arm_veorq_s16(__a, __b) +#define vcaddq_rot90_s16(__a, __b) __arm_vcaddq_rot90_s16(__a, __b) +#define vcaddq_rot270_s16(__a, __b) __arm_vcaddq_rot270_s16(__a, __b) +#define vbrsrq_n_s16(__a, __b) __arm_vbrsrq_n_s16(__a, __b) +#define vbicq_s16(__a, __b) __arm_vbicq_s16(__a, __b) +#define vandq_s16(__a, __b) __arm_vandq_s16(__a, __b) +#define vaddvaq_s16(__a, __b) __arm_vaddvaq_s16(__a, __b) +#define vaddq_n_s16(__a, __b) __arm_vaddq_n_s16(__a, __b) +#define vabdq_s16(__a, __b) __arm_vabdq_s16(__a, __b) +#define vshlq_n_s16(__a, __imm) __arm_vshlq_n_s16(__a, __imm) +#define vrshrq_n_s16(__a, __imm) __arm_vrshrq_n_s16(__a, __imm) +#define vqshlq_n_s16(__a, __imm) __arm_vqshlq_n_s16(__a, __imm) +#define vsubq_u32(__a, __b) __arm_vsubq_u32(__a, __b) +#define vsubq_n_u32(__a, __b) __arm_vsubq_n_u32(__a, __b) +#define vrmulhq_u32(__a, __b) __arm_vrmulhq_u32(__a, __b) +#define vrhaddq_u32(__a, __b) __arm_vrhaddq_u32(__a, __b) +#define vqsubq_u32(__a, __b) __arm_vqsubq_u32(__a, __b) +#define vqsubq_n_u32(__a, __b) __arm_vqsubq_n_u32(__a, __b) +#define vqaddq_u32(__a, __b) __arm_vqaddq_u32(__a, __b) +#define vqaddq_n_u32(__a, __b) __arm_vqaddq_n_u32(__a, __b) +#define vorrq_u32(__a, __b) __arm_vorrq_u32(__a, __b) +#define vornq_u32(__a, __b) __arm_vornq_u32(__a, __b) +#define vmulq_u32(__a, __b) __arm_vmulq_u32(__a, __b) +#define vmulq_n_u32(__a, __b) __arm_vmulq_n_u32(__a, __b) +#define vmulltq_int_u32(__a, __b) __arm_vmulltq_int_u32(__a, __b) +#define vmullbq_int_u32(__a, __b) __arm_vmullbq_int_u32(__a, __b) +#define vmulhq_u32(__a, __b) __arm_vmulhq_u32(__a, __b) +#define vmladavq_u32(__a, __b) __arm_vmladavq_u32(__a, __b) +#define vminvq_u32(__a, __b) __arm_vminvq_u32(__a, __b) +#define vminq_u32(__a, __b) __arm_vminq_u32(__a, __b) +#define vmaxvq_u32(__a, __b) __arm_vmaxvq_u32(__a, __b) +#define vmaxq_u32(__a, __b) __arm_vmaxq_u32(__a, __b) +#define vhsubq_u32(__a, __b) __arm_vhsubq_u32(__a, __b) +#define vhsubq_n_u32(__a, __b) __arm_vhsubq_n_u32(__a, __b) +#define vhaddq_u32(__a, __b) __arm_vhaddq_u32(__a, __b) +#define vhaddq_n_u32(__a, __b) __arm_vhaddq_n_u32(__a, __b) +#define veorq_u32(__a, __b) __arm_veorq_u32(__a, __b) +#define vcmpneq_n_u32(__a, __b) __arm_vcmpneq_n_u32(__a, __b) +#define vcmphiq_u32(__a, __b) __arm_vcmphiq_u32(__a, __b) +#define vcmphiq_n_u32(__a, __b) __arm_vcmphiq_n_u32(__a, __b) +#define vcmpeqq_u32(__a, __b) __arm_vcmpeqq_u32(__a, __b) +#define vcmpeqq_n_u32(__a, __b) __arm_vcmpeqq_n_u32(__a, __b) +#define vcmpcsq_u32(__a, __b) __arm_vcmpcsq_u32(__a, __b) +#define vcmpcsq_n_u32(__a, __b) __arm_vcmpcsq_n_u32(__a, __b) +#define vcaddq_rot90_u32(__a, __b) __arm_vcaddq_rot90_u32(__a, __b) +#define vcaddq_rot270_u32(__a, __b) __arm_vcaddq_rot270_u32(__a, __b) +#define vbicq_u32(__a, __b) __arm_vbicq_u32(__a, __b) +#define vandq_u32(__a, __b) __arm_vandq_u32(__a, __b) +#define vaddvq_p_u32(__a, __p) __arm_vaddvq_p_u32(__a, __p) +#define vaddvaq_u32(__a, __b) __arm_vaddvaq_u32(__a, __b) +#define vaddq_n_u32(__a, __b) __arm_vaddq_n_u32(__a, __b) +#define vabdq_u32(__a, __b) __arm_vabdq_u32(__a, __b) +#define vshlq_r_u32(__a, __b) __arm_vshlq_r_u32(__a, __b) +#define vrshlq_u32(__a, __b) __arm_vrshlq_u32(__a, __b) +#define vrshlq_n_u32(__a, __b) __arm_vrshlq_n_u32(__a, __b) +#define vqshlq_u32(__a, __b) __arm_vqshlq_u32(__a, __b) +#define vqshlq_r_u32(__a, __b) __arm_vqshlq_r_u32(__a, __b) +#define vqrshlq_u32(__a, __b) __arm_vqrshlq_u32(__a, __b) +#define vqrshlq_n_u32(__a, __b) __arm_vqrshlq_n_u32(__a, __b) +#define vminavq_s32(__a, __b) __arm_vminavq_s32(__a, __b) +#define vminaq_s32(__a, __b) __arm_vminaq_s32(__a, __b) +#define vmaxavq_s32(__a, __b) __arm_vmaxavq_s32(__a, __b) +#define vmaxaq_s32(__a, __b) __arm_vmaxaq_s32(__a, __b) +#define vbrsrq_n_u32(__a, __b) __arm_vbrsrq_n_u32(__a, __b) +#define vshlq_n_u32(__a, __imm) __arm_vshlq_n_u32(__a, __imm) +#define vrshrq_n_u32(__a, __imm) __arm_vrshrq_n_u32(__a, __imm) +#define vqshlq_n_u32(__a, __imm) __arm_vqshlq_n_u32(__a, __imm) +#define vcmpneq_n_s32(__a, __b) __arm_vcmpneq_n_s32(__a, __b) +#define vcmpltq_s32(__a, __b) __arm_vcmpltq_s32(__a, __b) +#define vcmpltq_n_s32(__a, __b) __arm_vcmpltq_n_s32(__a, __b) +#define vcmpleq_s32(__a, __b) __arm_vcmpleq_s32(__a, __b) +#define vcmpleq_n_s32(__a, __b) __arm_vcmpleq_n_s32(__a, __b) +#define vcmpgtq_s32(__a, __b) __arm_vcmpgtq_s32(__a, __b) +#define vcmpgtq_n_s32(__a, __b) __arm_vcmpgtq_n_s32(__a, __b) +#define vcmpgeq_s32(__a, __b) __arm_vcmpgeq_s32(__a, __b) +#define vcmpgeq_n_s32(__a, __b) __arm_vcmpgeq_n_s32(__a, __b) +#define vcmpeqq_s32(__a, __b) __arm_vcmpeqq_s32(__a, __b) +#define vcmpeqq_n_s32(__a, __b) __arm_vcmpeqq_n_s32(__a, __b) +#define vqshluq_n_s32(__a, __imm) __arm_vqshluq_n_s32(__a, __imm) +#define vaddvq_p_s32(__a, __p) __arm_vaddvq_p_s32(__a, __p) +#define vsubq_s32(__a, __b) __arm_vsubq_s32(__a, __b) +#define vsubq_n_s32(__a, __b) __arm_vsubq_n_s32(__a, __b) +#define vshlq_r_s32(__a, __b) __arm_vshlq_r_s32(__a, __b) +#define vrshlq_s32(__a, __b) __arm_vrshlq_s32(__a, __b) +#define vrshlq_n_s32(__a, __b) __arm_vrshlq_n_s32(__a, __b) +#define vrmulhq_s32(__a, __b) __arm_vrmulhq_s32(__a, __b) +#define vrhaddq_s32(__a, __b) __arm_vrhaddq_s32(__a, __b) +#define vqsubq_s32(__a, __b) __arm_vqsubq_s32(__a, __b) +#define vqsubq_n_s32(__a, __b) __arm_vqsubq_n_s32(__a, __b) +#define vqshlq_s32(__a, __b) __arm_vqshlq_s32(__a, __b) +#define vqshlq_r_s32(__a, __b) __arm_vqshlq_r_s32(__a, __b) +#define vqrshlq_s32(__a, __b) __arm_vqrshlq_s32(__a, __b) +#define vqrshlq_n_s32(__a, __b) __arm_vqrshlq_n_s32(__a, __b) +#define vqrdmulhq_s32(__a, __b) __arm_vqrdmulhq_s32(__a, __b) +#define vqrdmulhq_n_s32(__a, __b) __arm_vqrdmulhq_n_s32(__a, __b) +#define vqdmulhq_s32(__a, __b) __arm_vqdmulhq_s32(__a, __b) +#define vqdmulhq_n_s32(__a, __b) __arm_vqdmulhq_n_s32(__a, __b) +#define vqaddq_s32(__a, __b) __arm_vqaddq_s32(__a, __b) +#define vqaddq_n_s32(__a, __b) __arm_vqaddq_n_s32(__a, __b) +#define vorrq_s32(__a, __b) __arm_vorrq_s32(__a, __b) +#define vornq_s32(__a, __b) __arm_vornq_s32(__a, __b) +#define vmulq_s32(__a, __b) __arm_vmulq_s32(__a, __b) +#define vmulq_n_s32(__a, __b) __arm_vmulq_n_s32(__a, __b) +#define vmulltq_int_s32(__a, __b) __arm_vmulltq_int_s32(__a, __b) +#define vmullbq_int_s32(__a, __b) __arm_vmullbq_int_s32(__a, __b) +#define vmulhq_s32(__a, __b) __arm_vmulhq_s32(__a, __b) +#define vmlsdavxq_s32(__a, __b) __arm_vmlsdavxq_s32(__a, __b) +#define vmlsdavq_s32(__a, __b) __arm_vmlsdavq_s32(__a, __b) +#define vmladavxq_s32(__a, __b) __arm_vmladavxq_s32(__a, __b) +#define vmladavq_s32(__a, __b) __arm_vmladavq_s32(__a, __b) +#define vminvq_s32(__a, __b) __arm_vminvq_s32(__a, __b) +#define vminq_s32(__a, __b) __arm_vminq_s32(__a, __b) +#define vmaxvq_s32(__a, __b) __arm_vmaxvq_s32(__a, __b) +#define vmaxq_s32(__a, __b) __arm_vmaxq_s32(__a, __b) +#define vhsubq_s32(__a, __b) __arm_vhsubq_s32(__a, __b) +#define vhsubq_n_s32(__a, __b) __arm_vhsubq_n_s32(__a, __b) +#define vhcaddq_rot90_s32(__a, __b) __arm_vhcaddq_rot90_s32(__a, __b) +#define vhcaddq_rot270_s32(__a, __b) __arm_vhcaddq_rot270_s32(__a, __b) +#define vhaddq_s32(__a, __b) __arm_vhaddq_s32(__a, __b) +#define vhaddq_n_s32(__a, __b) __arm_vhaddq_n_s32(__a, __b) +#define veorq_s32(__a, __b) __arm_veorq_s32(__a, __b) +#define vcaddq_rot90_s32(__a, __b) __arm_vcaddq_rot90_s32(__a, __b) +#define vcaddq_rot270_s32(__a, __b) __arm_vcaddq_rot270_s32(__a, __b) +#define vbrsrq_n_s32(__a, __b) __arm_vbrsrq_n_s32(__a, __b) +#define vbicq_s32(__a, __b) __arm_vbicq_s32(__a, __b) +#define vandq_s32(__a, __b) __arm_vandq_s32(__a, __b) +#define vaddvaq_s32(__a, __b) __arm_vaddvaq_s32(__a, __b) +#define vaddq_n_s32(__a, __b) __arm_vaddq_n_s32(__a, __b) +#define vabdq_s32(__a, __b) __arm_vabdq_s32(__a, __b) +#define vshlq_n_s32(__a, __imm) __arm_vshlq_n_s32(__a, __imm) +#define vrshrq_n_s32(__a, __imm) __arm_vrshrq_n_s32(__a, __imm) +#define vqshlq_n_s32(__a, __imm) __arm_vqshlq_n_s32(__a, __imm) #endif __extension__ extern __inline void @@ -979,6 +1339,2525 @@ __arm_vshlq_u32 (uint32x4_t __a, int32x4_t __b) { return __builtin_mve_vshlq_uv4si (__a, __b); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vsubq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vsubq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vrmulhq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vrhaddq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vqsubq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vqsubq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vqaddq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vqaddq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vorrq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vornq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmulq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vmulq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmulltq_int_uv16qi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmullbq_int_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmulhq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmladavq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_u8 (uint8_t __a, uint8x16_t __b) +{ + return __builtin_mve_vminvq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vminq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_u8 (uint8_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmaxvq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vmaxq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vhsubq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vhsubq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vhaddq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vhaddq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_veorq_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vcmpneq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcmphiq_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vcmphiq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcmpeqq_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vcmpeqq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcmpcsq_uv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vcmpcsq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcaddq_rot90_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vcaddq_rot270_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vbicq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vandq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_u8 (uint8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_uv16qi (__a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_u8 (uint32_t __a, uint8x16_t __b) +{ + return __builtin_mve_vaddvaq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_u8 (uint8x16_t __a, uint8_t __b) +{ + return __builtin_mve_vaddq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __builtin_mve_vabdq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_u8 (uint8x16_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vrshlq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_u8 (uint8x16_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqshlq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_u8 (uint8x16_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_u8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrshlq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_u8 (uint8x16_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_s8 (uint8_t __a, int8x16_t __b) +{ + return __builtin_mve_vminavq_sv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_s8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vminaq_sv16qi (__a, __b); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_s8 (uint8_t __a, int8x16_t __b) +{ + return __builtin_mve_vmaxavq_sv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_s8 (uint8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmaxaq_sv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_u8 (uint8x16_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_uv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_u8 (uint8x16_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_u8 (uint8x16_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_u8 (uint8x16_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpneq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpltq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpltq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpleq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpleq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpgtq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpgtq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpgeq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpgeq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcmpeqq_sv16qi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vcmpeqq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vqshluq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_s8 (int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_sv16qi (__a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vsubq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vsubq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_s8 (int8x16_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vrshlq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_s8 (int8x16_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vrmulhq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vrhaddq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqsubq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vqsubq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqshlq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_s8 (int8x16_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrshlq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_s8 (int8x16_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrdmulhq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vqrdmulhq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqdmulhq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vqdmulhq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqaddq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vqaddq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vorrq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vornq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmulq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vmulq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmulltq_int_sv16qi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmullbq_int_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmulhq_sv16qi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmlsdavxq_sv16qi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmlsdavq_sv16qi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmladavxq_sv16qi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmladavq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_s8 (int8_t __a, int8x16_t __b) +{ + return __builtin_mve_vminvq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vminq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_s8 (int8_t __a, int8x16_t __b) +{ + return __builtin_mve_vmaxvq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vmaxq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vhsubq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vhsubq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vhcaddq_rot90_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vhcaddq_rot270_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vhaddq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vhaddq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_veorq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcaddq_rot90_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vcaddq_rot270_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_s8 (int8x16_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vbicq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vandq_sv16qi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_s8 (int32_t __a, int8x16_t __b) +{ + return __builtin_mve_vaddvaq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_s8 (int8x16_t __a, int8_t __b) +{ + return __builtin_mve_vaddq_n_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vabdq_sv16qi (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vsubq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vsubq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vrmulhq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vrhaddq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vqsubq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vqsubq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vqaddq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vqaddq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vorrq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vornq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmulq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vmulq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmulltq_int_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmullbq_int_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmulhq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmladavq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_u16 (uint16_t __a, uint16x8_t __b) +{ + return __builtin_mve_vminvq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vminq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_u16 (uint16_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmaxvq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vmaxq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vhsubq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vhsubq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vhaddq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vhaddq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_veorq_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vcmpneq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcmphiq_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vcmphiq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcmpeqq_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vcmpeqq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcmpcsq_uv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vcmpcsq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcaddq_rot90_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vcaddq_rot270_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vbicq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vandq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_u16 (uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_uv8hi (__a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_u16 (uint32_t __a, uint16x8_t __b) +{ + return __builtin_mve_vaddvaq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_u16 (uint16x8_t __a, uint16_t __b) +{ + return __builtin_mve_vaddq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __builtin_mve_vabdq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_u16 (uint16x8_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vrshlq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_u16 (uint16x8_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqshlq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_u16 (uint16x8_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_u16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrshlq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_u16 (uint16x8_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_s16 (uint16_t __a, int16x8_t __b) +{ + return __builtin_mve_vminavq_sv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_s16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vminaq_sv8hi (__a, __b); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_s16 (uint16_t __a, int16x8_t __b) +{ + return __builtin_mve_vmaxavq_sv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_s16 (uint16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmaxaq_sv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_u16 (uint16x8_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_uv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_u16 (uint16x8_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_u16 (uint16x8_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_u16 (uint16x8_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpneq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpltq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpltq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpleq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpleq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpgtq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpgtq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpgeq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpgeq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcmpeqq_sv8hi (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vcmpeqq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vqshluq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_s16 (int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_sv8hi (__a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vsubq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vsubq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_s16 (int16x8_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vrshlq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_s16 (int16x8_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vrmulhq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vrhaddq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqsubq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vqsubq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqshlq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_s16 (int16x8_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrshlq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_s16 (int16x8_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrdmulhq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vqrdmulhq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqdmulhq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vqdmulhq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqaddq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vqaddq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vorrq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vornq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmulq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vmulq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmulltq_int_sv8hi (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmullbq_int_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmulhq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmlsdavxq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmlsdavq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmladavxq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmladavq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_s16 (int16_t __a, int16x8_t __b) +{ + return __builtin_mve_vminvq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vminq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_s16 (int16_t __a, int16x8_t __b) +{ + return __builtin_mve_vmaxvq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vmaxq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vhsubq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vhsubq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vhcaddq_rot90_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vhcaddq_rot270_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vhaddq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vhaddq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_veorq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcaddq_rot90_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vcaddq_rot270_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_s16 (int16x8_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vbicq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vandq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_s16 (int32_t __a, int16x8_t __b) +{ + return __builtin_mve_vaddvaq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_s16 (int16x8_t __a, int16_t __b) +{ + return __builtin_mve_vaddq_n_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vabdq_sv8hi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vsubq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vsubq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vrmulhq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vrhaddq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vqsubq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vqsubq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vqaddq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vqaddq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vorrq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vornq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmulq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vmulq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmulltq_int_uv4si (__a, __b); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmullbq_int_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmulhq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmladavq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_u32 (uint32_t __a, uint32x4_t __b) +{ + return __builtin_mve_vminvq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vminq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_u32 (uint32_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmaxvq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmaxq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vhsubq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vhsubq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vhaddq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vhaddq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_veorq_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vcmpneq_n_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcmphiq_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vcmphiq_n_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcmpeqq_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vcmpeqq_n_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcmpcsq_uv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vcmpcsq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcaddq_rot90_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vcaddq_rot270_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vbicq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vandq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_u32 (uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_uv4si (__a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_u32 (uint32_t __a, uint32x4_t __b) +{ + return __builtin_mve_vaddvaq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_u32 (uint32x4_t __a, uint32_t __b) +{ + return __builtin_mve_vaddq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vabdq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_u32 (uint32x4_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrshlq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_u32 (uint32x4_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqshlq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_u32 (uint32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_u32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrshlq_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_u32 (uint32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_s32 (uint32_t __a, int32x4_t __b) +{ + return __builtin_mve_vminavq_sv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_s32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vminaq_sv4si (__a, __b); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_s32 (uint32_t __a, int32x4_t __b) +{ + return __builtin_mve_vmaxavq_sv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_s32 (uint32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmaxaq_sv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_u32 (uint32x4_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_uv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_u32 (uint32x4_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_uv4si (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_u32 (uint32x4_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_uv4si (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_u32 (uint32x4_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_uv4si (__a, __imm); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpneq_n_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpltq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpltq_n_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpleq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpleq_n_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpgtq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpgtq_n_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpgeq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpgeq_n_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcmpeqq_sv4si (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vcmpeqq_n_sv4si (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vqshluq_n_sv4si (__a, __imm); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_p_s32 (int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vaddvq_p_sv4si (__a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vsubq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vsubq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_r_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vshlq_r_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrshlq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vrshlq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrmulhq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrhaddq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqsubq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqsubq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqshlq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_r_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqshlq_r_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrshlq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqrshlq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrdmulhq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqrdmulhq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqdmulhq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqdmulhq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqaddq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqaddq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vorrq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vornq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmulq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vmulq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmulltq_int_sv4si (__a, __b); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmullbq_int_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmulhq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmlsdavxq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmlsdavq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmladavxq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmladavq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_s32 (int32_t __a, int32x4_t __b) +{ + return __builtin_mve_vminvq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vminq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_s32 (int32_t __a, int32x4_t __b) +{ + return __builtin_mve_vmaxvq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vmaxq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vhsubq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vhsubq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vhcaddq_rot90_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vhcaddq_rot270_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vhaddq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vhaddq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_veorq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcaddq_rot90_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vcaddq_rot270_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vbicq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vandq_sv4si (__a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_s32 (int32_t __a, int32x4_t __b) +{ + return __builtin_mve_vaddvaq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vaddq_n_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vabdq_sv4si (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vshlq_n_sv4si (__a, __imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vrshrq_n_sv4si (__a, __imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vqshlq_n_sv4si (__a, __imm); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ @@ -1792,7 +4671,13 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) #define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -1829,6 +4714,36 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -1991,6 +4906,746 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +#define vsubq(p0,p1) __arm_vsubq(p0,p1) +#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vsubq_n(p0,p1) __arm_vsubq_n(p0,p1) +#define __arm_vsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vshlq_r(p0,p1) __arm_vshlq_r(p0,p1) +#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vrshlq_n(p0,p1) __arm_vrshlq_n(p0,p1) +#define __arm_vrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) +#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vrshlq_n(p0,p1) __arm_vrshlq_n(p0,p1) +#define __arm_vrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) +#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vrmulhq(p0,p1) __arm_vrmulhq(p0,p1) +#define __arm_vrmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vrhaddq(p0,p1) __arm_vrhaddq(p0,p1) +#define __arm_vrhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqsubq_n(p0,p1) __arm_vqsubq_n(p0,p1) +#define __arm_vqsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) +#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqshlq(p0,p1) __arm_vqshlq(p0,p1) +#define __arm_vqshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqshlq_r(p0,p1) __arm_vqshlq_r(p0,p1) +#define __arm_vqshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vqshluq(p0,p1) __arm_vqshluq(p0,p1) +#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) + +#define vrshrq_n(p0,p1) __arm_vrshrq_n(p0,p1) +#define __arm_vrshrq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vshlq_n(p0,p1) __arm_vshlq_n(p0,p1) +#define __arm_vshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vqshluq_n(p0,p1) __arm_vqshluq_n(p0,p1) +#define __arm_vqshluq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) + +#define vqshlq_n(p0,p1) __arm_vqshlq_n(p0,p1) +#define __arm_vqshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vqrshlq_n(p0,p1) __arm_vqrshlq_n(p0,p1) +#define __arm_vqrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vqrshlq(p0,p1) __arm_vqrshlq(p0,p1) +#define __arm_vqrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqrdmulhq_n(p0,p1) __arm_vqrdmulhq_n(p0,p1) +#define __arm_vqrdmulhq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vqrdmulhq(p0,p1) __arm_vqrdmulhq(p0,p1) +#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqdmulhq_n(p0,p1) __arm_vqdmulhq_n(p0,p1) +#define __arm_vqdmulhq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vqdmulhq(p0,p1) __arm_vqdmulhq(p0,p1) +#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqaddq_n(p0,p1) __arm_vqaddq_n(p0,p1) +#define __arm_vqaddq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) +#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vorrq_n(p0,p1) __arm_vorrq_n(p0,p1) +#define __arm_vorrq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)));}) + +#define vorrq(p0,p1) __arm_vorrq(p0,p1) +#define __arm_vorrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vornq(p0,p1) __arm_vornq(p0,p1) +#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmulq_n(p0,p1) __arm_vmulq_n(p0,p1) +#define __arm_vmulq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vmulq(p0,p1) __arm_vmulq(p0,p1) +#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmulltq_int(p0,p1) __arm_vmulltq_int(p0,p1) +#define __arm_vmulltq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmullbq_int(p0,p1) __arm_vmullbq_int(p0,p1) +#define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmulhq(p0,p1) __arm_vmulhq(p0,p1) +#define __arm_vmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vminq(p0,p1) __arm_vminq(p0,p1) +#define __arm_vminq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vminaq(p0,p1) __arm_vminaq(p0,p1) +#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vmaxq(p0,p1) __arm_vmaxq(p0,p1) +#define __arm_vmaxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmaxaq(p0,p1) __arm_vmaxaq(p0,p1) +#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vhsubq_n(p0,p1) __arm_vhsubq_n(p0,p1) +#define __arm_vhsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) +#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vhcaddq_rot90(p0,p1) __arm_vhcaddq_rot90(p0,p1) +#define __arm_vhcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vhcaddq_rot270(p0,p1) __arm_vhcaddq_rot270(p0,p1) +#define __arm_vhcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vhaddq_n(p0,p1) __arm_vhaddq_n(p0,p1) +#define __arm_vhaddq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) +#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define veorq(p0,p1) __arm_veorq(p0,p1) +#define __arm_veorq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vcaddq_rot90(p0,p1) __arm_vcaddq_rot90(p0,p1) +#define __arm_vcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vcaddq_rot270(p0,p1) __arm_vcaddq_rot270(p0,p1) +#define __arm_vcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) +#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vbicq(p0,p1) __arm_vbicq(p0,p1) +#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vaddq(p0,p1) __arm_vaddq(p0,p1) +#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vaddq(p0,p1) __arm_vaddq(p0,p1) +#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vandq(p0,p1) __arm_vandq(p0,p1) +#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vabdq(p0,p1) __arm_vabdq(p0,p1) +#define __arm_vabdq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vaddvaq(p0,p1) __arm_vaddvaq(p0,p1) +#define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vaddvq_p(p0,p1) __arm_vaddvq_p(p0,p1) +#define __arm_vaddvq_p(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vaddvq_p_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vaddvq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddvq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vaddvq_p_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vaddvq_p_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddvq_p_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vcmpcsq(p0,p1) __arm_vcmpcsq(p0,p1) +#define __arm_vcmpcsq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vcmpeqq(p0,p1) __arm_vcmpeqq(p0,p1) +#define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vmlsdavxq(p0,p1) __arm_vmlsdavxq(p0,p1) +#define __arm_vmlsdavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vmlsdavq(p0,p1) __arm_vmlsdavq(p0,p1) +#define __arm_vmlsdavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vmladavxq(p0,p1) __arm_vmladavxq(p0,p1) +#define __arm_vmladavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavxq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavxq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavxq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmladavq(p0,p1) __arm_vmladavq(p0,p1) +#define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vminvq(p0,p1) __arm_vminvq(p0,p1) +#define __arm_vminvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t][__ARM_mve_type_int8x16_t]: __arm_vminvq_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t][__ARM_mve_type_int16x8_t]: __arm_vminvq_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vminvq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_uint8x16_t]: __arm_vminvq_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_uint16x8_t]: __arm_vminvq_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vminvq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vminavq(p0,p1) __arm_vminavq(p0,p1) +#define __arm_vminavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_int8x16_t]: __arm_vminavq_s8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_int16x8_t]: __arm_vminavq_s16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_int32x4_t]: __arm_vminavq_s32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vmaxvq(p0,p1) __arm_vmaxvq(p0,p1) +#define __arm_vmaxvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t][__ARM_mve_type_int8x16_t]: __arm_vmaxvq_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t][__ARM_mve_type_int16x8_t]: __arm_vmaxvq_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vmaxvq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxvq_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxvq_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxvq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmaxavq(p0,p1) __arm_vmaxavq(p0,p1) +#define __arm_vmaxavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_int8x16_t]: __arm_vmaxavq_s8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_int16x8_t]: __arm_vmaxavq_s16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_int32x4_t]: __arm_vmaxavq_s32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) +#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vcmphiq(p0,p1) __arm_vcmphiq(p0,p1) +#define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vcmpleq(p0,p1) __arm_vcmpleq(p0,p1) +#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + +#define vcmpltq(p0,p1) __arm_vcmpltq(p0,p1) +#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 05930c9..550a67f 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -93,3 +93,123 @@ VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index e3e202c..cdf75ab 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -34,7 +34,8 @@ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di, ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe -;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb +;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra, +;; Rg ;; in all states: Pf, Pg ;; The following memory constraints have been used: @@ -58,6 +59,11 @@ (and (match_code "const_int") (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16"))) +(define_constraint "Ra" + "@internal In Thumb-2 state a constant in range 0 to 7" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 7"))) + (define_constraint "Rb" "@internal In Thumb-2 state a constant in range 1 to 8" (and (match_code "const_int") @@ -68,6 +74,12 @@ (and (match_code "const_int") (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32"))) +(define_constraint "Rg" + "@internal In Thumb-2 state a constant is one among 1, 2, 4 and 8" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) + || (ival == 4) || (ival == 8))"))) + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4ae608b..8e817b8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -41,7 +41,32 @@ VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S - VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U]) + VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S + VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S + VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S + VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S + VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S + VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S + VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S + VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S + VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S + VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S + VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U + VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U + VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U + VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U + VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U + VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U + VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U + VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U + VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U + VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S + VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S + VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S + VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S + VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S + VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S + VABDQ_M_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -62,13 +87,46 @@ (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u") (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s") - (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")]) + (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s") + (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s") + (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u") + (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s") + (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u") + (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s") + (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") + (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") + (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") + (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") + (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") + (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") + (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") + (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u") + (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s") + (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u") + (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s") + (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u") + (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s") + (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s") + (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u") + (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s") + (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u") + (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s") + (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u") + (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s") + (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u") + (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s") + (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u") + (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s") + (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u") + (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") + (VADDVAQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64")]) (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") (V4SI "mve_imm_32")]) (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) +(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -95,6 +153,54 @@ (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U]) (define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S]) (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U]) +(define_int_iterator VABDQ [VABDQ_S VABDQ_U]) +(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U]) +(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U]) +(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S]) +(define_int_iterator VANDQ [VANDQ_U VANDQ_S]) +(define_int_iterator VBICQ [VBICQ_S VBICQ_U]) +(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S]) +(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U]) +(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) +(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) +(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) +(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) +(define_int_iterator VEORQ [VEORQ_U VEORQ_S]) +(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) +(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) +(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) +(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S]) +(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S]) +(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S]) +(define_int_iterator VMINQ [VMINQ_S VMINQ_U]) +(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S]) +(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S]) +(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U]) +(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S]) +(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S]) +(define_int_iterator VMULQ [VMULQ_U VMULQ_S]) +(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S]) +(define_int_iterator VORNQ [VORNQ_U VORNQ_S]) +(define_int_iterator VORRQ [VORRQ_S VORRQ_U]) +(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S]) +(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U]) +(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U]) +(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U]) +(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U]) +(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U]) +(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S]) +(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S]) +(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U]) +(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U]) +(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U]) +(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U]) +(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S]) +(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U]) +(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S]) +(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U]) +(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U]) +(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U]) + (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -856,3 +962,1098 @@ "vshl.%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) + +;; +;; [vabdq_s, vabdq_u]) +;; +(define_insn "mve_vabdq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VABDQ)) + ] + "TARGET_HAVE_MVE" + "vabd.%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddq_n_s, vaddq_n_u]) +;; +(define_insn "mve_vaddq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VADDQ_N)) + ] + "TARGET_HAVE_MVE" + "vadd.i%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddvaq_s, vaddvaq_u]) +;; +(define_insn "mve_vaddvaq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VADDVAQ)) + ] + "TARGET_HAVE_MVE" + "vaddva.%# %0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddvq_p_u, vaddvq_p_s]) +;; +(define_insn "mve_vaddvq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VADDVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddvt.%# %0, %q1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vandq_u, vandq_s]) +;; +(define_insn "mve_vandq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VANDQ)) + ] + "TARGET_HAVE_MVE" + "vand %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vbicq_s, vbicq_u]) +;; +(define_insn "mve_vbicq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VBICQ)) + ] + "TARGET_HAVE_MVE" + "vbic %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vbrsrq_n_u, vbrsrq_n_s]) +;; +(define_insn "mve_vbrsrq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "s_register_operand" "r")] + VBRSRQ_N)) + ] + "TARGET_HAVE_MVE" + "vbrsr.%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcaddq_rot270_s, vcaddq_rot270_u]) +;; +(define_insn "mve_vcaddq_rot270_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCADDQ_ROT270)) + ] + "TARGET_HAVE_MVE" + "vcadd.i%# %q0, %q1, %q2, #270" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcaddq_rot90_u, vcaddq_rot90_s]) +;; +(define_insn "mve_vcaddq_rot90_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCADDQ_ROT90)) + ] + "TARGET_HAVE_MVE" + "vcadd.i%# %q0, %q1, %q2, #90" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpcsq_n_u]) +;; +(define_insn "mve_vcmpcsq_n_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPCSQ_N_U)) + ] + "TARGET_HAVE_MVE" + "vcmp.u%# cs, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpcsq_u]) +;; +(define_insn "mve_vcmpcsq_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPCSQ_U)) + ] + "TARGET_HAVE_MVE" + "vcmp.u%# cs, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpeqq_n_s, vcmpeqq_n_u]) +;; +(define_insn "mve_vcmpeqq_n_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPEQQ_N)) + ] + "TARGET_HAVE_MVE" + "vcmp.i%# eq, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpeqq_u, vcmpeqq_s]) +;; +(define_insn "mve_vcmpeqq_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPEQQ)) + ] + "TARGET_HAVE_MVE" + "vcmp.i%# eq, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgeq_n_s]) +;; +(define_insn "mve_vcmpgeq_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPGEQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# ge, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgeq_s]) +;; +(define_insn "mve_vcmpgeq_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPGEQ_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# ge, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgtq_n_s]) +;; +(define_insn "mve_vcmpgtq_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPGTQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# gt, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgtq_s]) +;; +(define_insn "mve_vcmpgtq_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPGTQ_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# gt, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmphiq_n_u]) +;; +(define_insn "mve_vcmphiq_n_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPHIQ_N_U)) + ] + "TARGET_HAVE_MVE" + "vcmp.u%# hi, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmphiq_u]) +;; +(define_insn "mve_vcmphiq_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPHIQ_U)) + ] + "TARGET_HAVE_MVE" + "vcmp.u%# hi, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpleq_n_s]) +;; +(define_insn "mve_vcmpleq_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPLEQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# le, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpleq_s]) +;; +(define_insn "mve_vcmpleq_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPLEQ_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# le, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpltq_n_s]) +;; +(define_insn "mve_vcmpltq_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPLTQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# lt, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpltq_s]) +;; +(define_insn "mve_vcmpltq_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VCMPLTQ_S)) + ] + "TARGET_HAVE_MVE" + "vcmp.s%# lt, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpneq_n_u, vcmpneq_n_s]) +;; +(define_insn "mve_vcmpneq_n_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPNEQ_N)) + ] + "TARGET_HAVE_MVE" + "vcmp.i%# ne, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [veorq_u, veorq_s]) +;; +(define_insn "mve_veorq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VEORQ)) + ] + "TARGET_HAVE_MVE" + "veor %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhaddq_n_u, vhaddq_n_s]) +;; +(define_insn "mve_vhaddq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VHADDQ_N)) + ] + "TARGET_HAVE_MVE" + "vhadd.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhaddq_s, vhaddq_u]) +;; +(define_insn "mve_vhaddq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VHADDQ)) + ] + "TARGET_HAVE_MVE" + "vhadd.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhcaddq_rot270_s]) +;; +(define_insn "mve_vhcaddq_rot270_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VHCADDQ_ROT270_S)) + ] + "TARGET_HAVE_MVE" + "vhcadd.s%#\t%q0, %q1, %q2, #270" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhcaddq_rot90_s]) +;; +(define_insn "mve_vhcaddq_rot90_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VHCADDQ_ROT90_S)) + ] + "TARGET_HAVE_MVE" + "vhcadd.s%#\t%q0, %q1, %q2, #90" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhsubq_n_u, vhsubq_n_s]) +;; +(define_insn "mve_vhsubq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VHSUBQ_N)) + ] + "TARGET_HAVE_MVE" + "vhsub.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vhsubq_s, vhsubq_u]) +;; +(define_insn "mve_vhsubq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VHSUBQ)) + ] + "TARGET_HAVE_MVE" + "vhsub.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxaq_s]) +;; +(define_insn "mve_vmaxaq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMAXAQ_S)) + ] + "TARGET_HAVE_MVE" + "vmaxa.s%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxavq_s]) +;; +(define_insn "mve_vmaxavq_s" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMAXAVQ_S)) + ] + "TARGET_HAVE_MVE" + "vmaxav.s%#\t%0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxq_u, vmaxq_s]) +;; +(define_insn "mve_vmaxq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMAXQ)) + ] + "TARGET_HAVE_MVE" + "vmax.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxvq_u, vmaxvq_s]) +;; +(define_insn "mve_vmaxvq_" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMAXVQ)) + ] + "TARGET_HAVE_MVE" + "vmaxv.%#\t%0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminaq_s]) +;; +(define_insn "mve_vminaq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMINAQ_S)) + ] + "TARGET_HAVE_MVE" + "vmina.s%#\t%q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminavq_s]) +;; +(define_insn "mve_vminavq_s" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMINAVQ_S)) + ] + "TARGET_HAVE_MVE" + "vminav.s%#\t%0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminq_s, vminq_u]) +;; +(define_insn "mve_vminq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMINQ)) + ] + "TARGET_HAVE_MVE" + "vmin.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminvq_u, vminvq_s]) +;; +(define_insn "mve_vminvq_" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMINVQ)) + ] + "TARGET_HAVE_MVE" + "vminv.%#\t%0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmladavq_u, vmladavq_s]) +;; +(define_insn "mve_vmladavq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMLADAVQ)) + ] + "TARGET_HAVE_MVE" + "vmladav.%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmladavxq_s]) +;; +(define_insn "mve_vmladavxq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMLADAVXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmladavx.s%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsdavq_s]) +;; +(define_insn "mve_vmlsdavq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMLSDAVQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsdav.s%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsdavxq_s]) +;; +(define_insn "mve_vmlsdavxq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMLSDAVXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsdavx.s%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulhq_s, vmulhq_u]) +;; +(define_insn "mve_vmulhq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMULHQ)) + ] + "TARGET_HAVE_MVE" + "vmulh.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmullbq_int_u, vmullbq_int_s]) +;; +(define_insn "mve_vmullbq_int_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMULLBQ_INT)) + ] + "TARGET_HAVE_MVE" + "vmullb.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulltq_int_u, vmulltq_int_s]) +;; +(define_insn "mve_vmulltq_int_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMULLTQ_INT)) + ] + "TARGET_HAVE_MVE" + "vmullt.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulq_n_u, vmulq_n_s]) +;; +(define_insn "mve_vmulq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VMULQ_N)) + ] + "TARGET_HAVE_MVE" + "vmul.i%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulq_u, vmulq_s]) +;; +(define_insn "mve_vmulq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VMULQ)) + ] + "TARGET_HAVE_MVE" + "vmul.i%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vornq_u, vornq_s]) +;; +(define_insn "mve_vornq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VORNQ)) + ] + "TARGET_HAVE_MVE" + "vorn %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vorrq_s, vorrq_u]) +;; +(define_insn "mve_vorrq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VORRQ)) + ] + "TARGET_HAVE_MVE" + "vorr %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqaddq_n_s, vqaddq_n_u]) +;; +(define_insn "mve_vqaddq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQADDQ_N)) + ] + "TARGET_HAVE_MVE" + "vqadd.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqaddq_u, vqaddq_s]) +;; +(define_insn "mve_vqaddq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQADDQ)) + ] + "TARGET_HAVE_MVE" + "vqadd.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmulhq_n_s]) +;; +(define_insn "mve_vqdmulhq_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQDMULHQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqdmulh.s%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmulhq_s]) +;; +(define_insn "mve_vqdmulhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQDMULHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmulh.s%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmulhq_n_s]) +;; +(define_insn "mve_vqrdmulhq_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQRDMULHQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmulh.s%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmulhq_s]) +;; +(define_insn "mve_vqrdmulhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQRDMULHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmulh.s%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrshlq_n_s, vqrshlq_n_u]) +;; +(define_insn "mve_vqrshlq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r")] + VQRSHLQ_N)) + ] + "TARGET_HAVE_MVE" + "vqrshl.%#\t%q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrshlq_s, vqrshlq_u]) +;; +(define_insn "mve_vqrshlq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQRSHLQ)) + ] + "TARGET_HAVE_MVE" + "vqrshl.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshlq_n_s, vqshlq_n_u]) +;; +(define_insn "mve_vqshlq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VQSHLQ_N)) + ] + "TARGET_HAVE_MVE" + "vqshl.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshlq_r_u, vqshlq_r_s]) +;; +(define_insn "mve_vqshlq_r_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r")] + VQSHLQ_R)) + ] + "TARGET_HAVE_MVE" + "vqshl.%#\t%q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshlq_s, vqshlq_u]) +;; +(define_insn "mve_vqshlq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQSHLQ)) + ] + "TARGET_HAVE_MVE" + "vqshl.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshluq_n_s]) +;; +(define_insn "mve_vqshluq_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "mve_imm_7" "Ra")] + VQSHLUQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqshlu.s%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqsubq_n_s, vqsubq_n_u]) +;; +(define_insn "mve_vqsubq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQSUBQ_N)) + ] + "TARGET_HAVE_MVE" + "vqsub.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqsubq_u, vqsubq_s]) +;; +(define_insn "mve_vqsubq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VQSUBQ)) + ] + "TARGET_HAVE_MVE" + "vqsub.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrhaddq_s, vrhaddq_u]) +;; +(define_insn "mve_vrhaddq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VRHADDQ)) + ] + "TARGET_HAVE_MVE" + "vrhadd.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmulhq_s, vrmulhq_u]) +;; +(define_insn "mve_vrmulhq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VRMULHQ)) + ] + "TARGET_HAVE_MVE" + "vrmulh.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrshlq_n_u, vrshlq_n_s]) +;; +(define_insn "mve_vrshlq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r")] + VRSHLQ_N)) + ] + "TARGET_HAVE_MVE" + "vrshl.%#\t%q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrshlq_s, vrshlq_u]) +;; +(define_insn "mve_vrshlq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VRSHLQ)) + ] + "TARGET_HAVE_MVE" + "vrshl.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrshrq_n_s, vrshrq_n_u]) +;; +(define_insn "mve_vrshrq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "" "")] + VRSHRQ_N)) + ] + "TARGET_HAVE_MVE" + "vrshr.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshlq_n_u, vshlq_n_s]) +;; +(define_insn "mve_vshlq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VSHLQ_N)) + ] + "TARGET_HAVE_MVE" + "vshl.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshlq_r_s, vshlq_r_u]) +;; +(define_insn "mve_vshlq_r_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r")] + VSHLQ_R)) + ] + "TARGET_HAVE_MVE" + "vshl.%#\t%q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vsubq_n_s, vsubq_n_u]) +;; +(define_insn "mve_vsubq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VSUBQ_N)) + ] + "TARGET_HAVE_MVE" + "vsub.i%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vsubq_s, vsubq_u]) +;; +(define_insn "mve_vsubq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VSUBQ)) + ] + "TARGET_HAVE_MVE" + "vsub.i%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 2f5d5a7..9c9a84b 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -35,6 +35,10 @@ (define_predicate "mve_imm_16" (match_test "satisfies_constraint_Rd (op)")) +;; True for immediates in the range of 0 to 7 for MVE. +(define_predicate "mve_imm_7" + (match_test "satisfies_constraint_Ra (op)")) + ;; True for immediates in the range of 1 to 8 for MVE. (define_predicate "mve_imm_8" (match_test "satisfies_constraint_Rb (op)")) @@ -43,6 +47,10 @@ (define_predicate "mve_imm_32" (match_test "satisfies_constraint_Rf (op)")) +;; True if the immediate is one among 1, 2, 4 or 8 for MVE. +(define_predicate "mve_imm_selective_upto_8" + (match_test "satisfies_constraint_Rg (op)")) + ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns (define_predicate "guard_addr_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 83de77b..0635e97 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,371 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: New test. * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c new file mode 100644 index 0000000..17b45e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vabdq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vabd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c new file mode 100644 index 0000000..9776c7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vabdq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vabd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c new file mode 100644 index 0000000..9528a80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vabdq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vabd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c new file mode 100644 index 0000000..0005623 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vabdq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vabd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c new file mode 100644 index 0000000..a89bea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vabdq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vabd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c new file mode 100644 index 0000000..d724fee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vabdq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vabd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c new file mode 100644 index 0000000..55091b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vaddq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c new file mode 100644 index 0000000..0b83adf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vaddq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c new file mode 100644 index 0000000..250807e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vaddq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c new file mode 100644 index 0000000..c0af7e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vaddq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c new file mode 100644 index 0000000..9ad1da0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vaddq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c new file mode 100644 index 0000000..3a36041 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vaddq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c new file mode 100644 index 0000000..b4b0011 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b) +{ + return vaddvaq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c new file mode 100644 index 0000000..eba7167 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b) +{ + return vaddvaq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c new file mode 100644 index 0000000..2471c99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b) +{ + return vaddvaq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c new file mode 100644 index 0000000..0d97fd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b) +{ + return vaddvaq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c new file mode 100644 index 0000000..4e630c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b) +{ + return vaddvaq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c new file mode 100644 index 0000000..e7c5137 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b) +{ + return vaddvaq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b) +{ + return vaddvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddva.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c new file mode 100644 index 0000000..b84d0d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vaddvq_p_s16 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s16" } } */ + +int32_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c new file mode 100644 index 0000000..0983f4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vaddvq_p_s32 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s32" } } */ + +int32_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c new file mode 100644 index 0000000..aef7f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vaddvq_p_s8 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s8" } } */ + +int32_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c new file mode 100644 index 0000000..d4c214e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vaddvq_p_u16 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u16" } } */ + +uint32_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c new file mode 100644 index 0000000..604ca6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vaddvq_p_u32 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u32" } } */ + +uint32_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c new file mode 100644 index 0000000..9caeea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vaddvq_p_u8 (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u8" } } */ + +uint32_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vaddvq_p (a, p); +} + +/* { dg-final { scan-assembler "vaddvt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c new file mode 100644 index 0000000..ae989dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vandq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c new file mode 100644 index 0000000..4106cfb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vandq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c new file mode 100644 index 0000000..ed78186 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vandq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c new file mode 100644 index 0000000..842b829 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vandq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c new file mode 100644 index 0000000..3998cf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vandq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c new file mode 100644 index 0000000..45846bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vandq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c new file mode 100644 index 0000000..51daf20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vbicq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c new file mode 100644 index 0000000..2846494 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vbicq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c new file mode 100644 index 0000000..ac4753c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vbicq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c new file mode 100644 index 0000000..3bf72ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vbicq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c new file mode 100644 index 0000000..7a81637 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vbicq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c new file mode 100644 index 0000000..d834672 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vbicq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c new file mode 100644 index 0000000..f8f8263 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b) +{ + return vbrsrq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c new file mode 100644 index 0000000..3ad6933 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vbrsrq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c new file mode 100644 index 0000000..dd40854 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b) +{ + return vbrsrq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c new file mode 100644 index 0000000..227847a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b) +{ + return vbrsrq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c new file mode 100644 index 0000000..5ee194c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b) +{ + return vbrsrq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c new file mode 100644 index 0000000..3b828a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b) +{ + return vbrsrq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b) +{ + return vbrsrq (a, b); +} + +/* { dg-final { scan-assembler "vbrsr.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c new file mode 100644 index 0000000..c6490ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vcaddq_rot270_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c new file mode 100644 index 0000000..9a5a338 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vcaddq_rot270_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c new file mode 100644 index 0000000..d23a2aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcaddq_rot270_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c new file mode 100644 index 0000000..c73aff1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcaddq_rot270_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c new file mode 100644 index 0000000..b076c56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcaddq_rot270_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c new file mode 100644 index 0000000..7805b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcaddq_rot270_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c new file mode 100644 index 0000000..4386ca9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vcaddq_rot90_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c new file mode 100644 index 0000000..5255f4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vcaddq_rot90_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c new file mode 100644 index 0000000..c7f64ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcaddq_rot90_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c new file mode 100644 index 0000000..c1a06d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcaddq_rot90_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c new file mode 100644 index 0000000..9f612a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcaddq_rot90_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c new file mode 100644 index 0000000..e19076b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcaddq_rot90_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c new file mode 100644 index 0000000..caa2ce4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b) +{ + return vcmpcsq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c new file mode 100644 index 0000000..cc3f4d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b) +{ + return vcmpcsq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c new file mode 100644 index 0000000..768b60d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b) +{ + return vcmpcsq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c new file mode 100644 index 0000000..a474ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcmpcsq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c new file mode 100644 index 0000000..2a7fae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcmpcsq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c new file mode 100644 index 0000000..b370a91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcmpcsq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcmpcsq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c new file mode 100644 index 0000000..ec5ed4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpeqq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c new file mode 100644 index 0000000..02262e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpeqq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c new file mode 100644 index 0000000..ef91aac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpeqq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c new file mode 100644 index 0000000..4f776cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b) +{ + return vcmpeqq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c new file mode 100644 index 0000000..ba5ce37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b) +{ + return vcmpeqq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c new file mode 100644 index 0000000..b6ef1d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b) +{ + return vcmpeqq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c new file mode 100644 index 0000000..94f6e68 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpeqq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c new file mode 100644 index 0000000..20ebd7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpeqq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c new file mode 100644 index 0000000..a893103 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpeqq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c new file mode 100644 index 0000000..ad1c08f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcmpeqq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c new file mode 100644 index 0000000..2faa789 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcmpeqq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c new file mode 100644 index 0000000..742e24f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcmpeqq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c new file mode 100644 index 0000000..2b3bb69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpgeq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c new file mode 100644 index 0000000..1cfde96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpgeq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c new file mode 100644 index 0000000..269f2e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpgeq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c new file mode 100644 index 0000000..1423d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpgeq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c new file mode 100644 index 0000000..49b2143 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpgeq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c new file mode 100644 index 0000000..fe0f602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpgeq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c new file mode 100644 index 0000000..a6fdbf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpgtq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c new file mode 100644 index 0000000..24cb5ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpgtq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c new file mode 100644 index 0000000..a9fc907 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpgtq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c new file mode 100644 index 0000000..3e1f84f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpgtq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c new file mode 100644 index 0000000..70c8987 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpgtq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c new file mode 100644 index 0000000..a731716 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpgtq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c new file mode 100644 index 0000000..98fa9e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b) +{ + return vcmphiq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c new file mode 100644 index 0000000..f3dc573 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b) +{ + return vcmphiq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c new file mode 100644 index 0000000..84aefb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b) +{ + return vcmphiq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c new file mode 100644 index 0000000..fda860f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vcmphiq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c new file mode 100644 index 0000000..c0d0f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vcmphiq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c new file mode 100644 index 0000000..938abc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vcmphiq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vcmphiq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c new file mode 100644 index 0000000..8a38936 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpleq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c new file mode 100644 index 0000000..e8c489e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpleq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c new file mode 100644 index 0000000..0816bbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpleq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c new file mode 100644 index 0000000..80f270f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpleq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c new file mode 100644 index 0000000..5148d2a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpleq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c new file mode 100644 index 0000000..24f9f05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpleq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c new file mode 100644 index 0000000..a283416 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpltq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c new file mode 100644 index 0000000..cc2427c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpltq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c new file mode 100644 index 0000000..5f4859b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpltq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c new file mode 100644 index 0000000..c3e3f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b) +{ + return vcmpltq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c new file mode 100644 index 0000000..c8f82fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b) +{ + return vcmpltq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c new file mode 100644 index 0000000..5dbb4f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b) +{ + return vcmpltq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c new file mode 100644 index 0000000..e1d3b18 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b) +{ + return vcmpneq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c new file mode 100644 index 0000000..538b9d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b) +{ + return vcmpneq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c new file mode 100644 index 0000000..7417716 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b) +{ + return vcmpneq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c new file mode 100644 index 0000000..31eb156 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b) +{ + return vcmpneq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c new file mode 100644 index 0000000..10c328f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b) +{ + return vcmpneq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c new file mode 100644 index 0000000..2433f43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b) +{ + return vcmpneq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c new file mode 100644 index 0000000..30b7e3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return veorq_s16 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c new file mode 100644 index 0000000..ec14090 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return veorq_s32 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c new file mode 100644 index 0000000..b0e02b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return veorq_s8 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c new file mode 100644 index 0000000..2985db8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return veorq_u16 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c new file mode 100644 index 0000000..4c1dae1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return veorq_u32 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c new file mode 100644 index 0000000..cc64128 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return veorq_u8 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c new file mode 100644 index 0000000..75977c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vhaddq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c new file mode 100644 index 0000000..0bfe84d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vhaddq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c new file mode 100644 index 0000000..4901b91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vhaddq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c new file mode 100644 index 0000000..88b1e2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vhaddq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c new file mode 100644 index 0000000..ad492e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vhaddq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c new file mode 100644 index 0000000..328f09a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vhaddq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vhaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c new file mode 100644 index 0000000..fe7b305 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vhaddq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c new file mode 100644 index 0000000..ceda836 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vhaddq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c new file mode 100644 index 0000000..e117f0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vhaddq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c new file mode 100644 index 0000000..003e59b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vhaddq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c new file mode 100644 index 0000000..f91044d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vhaddq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c new file mode 100644 index 0000000..975ffa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vhaddq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vhaddq (a, b); +} + +/* { dg-final { scan-assembler "vhadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c new file mode 100644 index 0000000..cea5485 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vhcaddq_rot270_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vhcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c new file mode 100644 index 0000000..2e2e3d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vhcaddq_rot270_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vhcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c new file mode 100644 index 0000000..6788943 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vhcaddq_rot270_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vhcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c new file mode 100644 index 0000000..637b2cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vhcaddq_rot90_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vhcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c new file mode 100644 index 0000000..52358be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vhcaddq_rot90_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vhcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c new file mode 100644 index 0000000..5db1e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vhcaddq_rot90_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vhcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vhcadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c new file mode 100644 index 0000000..723c27a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vhsubq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c new file mode 100644 index 0000000..2d2b13d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vhsubq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c new file mode 100644 index 0000000..4180563 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vhsubq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c new file mode 100644 index 0000000..93e1395 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vhsubq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c new file mode 100644 index 0000000..06dddd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vhsubq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c new file mode 100644 index 0000000..ea81c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vhsubq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vhsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c new file mode 100644 index 0000000..89e6163 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vhsubq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c new file mode 100644 index 0000000..aac6752 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vhsubq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c new file mode 100644 index 0000000..e7008e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vhsubq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c new file mode 100644 index 0000000..c2a5e5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vhsubq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c new file mode 100644 index 0000000..634e2cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vhsubq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c new file mode 100644 index 0000000..9a95fb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vhsubq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vhsubq (a, b); +} + +/* { dg-final { scan-assembler "vhsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c new file mode 100644 index 0000000..36a6626 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vmaxaq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vmaxaq (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c new file mode 100644 index 0000000..935f848 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vmaxaq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vmaxaq (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c new file mode 100644 index 0000000..29a9297 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vmaxaq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vmaxaq (a, b); +} + +/* { dg-final { scan-assembler "vmaxa.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c new file mode 100644 index 0000000..acbf404 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, int16x8_t b) +{ + return vmaxavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s16" } } */ + +uint16_t +foo1 (uint16_t a, int16x8_t b) +{ + return vmaxavq (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c new file mode 100644 index 0000000..a98318b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b) +{ + return vmaxavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b) +{ + return vmaxavq (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c new file mode 100644 index 0000000..7007be2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, int8x16_t b) +{ + return vmaxavq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s8" } } */ + +uint8_t +foo1 (uint8_t a, int8x16_t b) +{ + return vmaxavq (a, b); +} + +/* { dg-final { scan-assembler "vmaxav.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c new file mode 100644 index 0000000..8e25328 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vmaxq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmax.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c new file mode 100644 index 0000000..732f68b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vmaxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmax.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c new file mode 100644 index 0000000..824b48d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vmaxq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmax.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c new file mode 100644 index 0000000..07cee0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmaxq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmax.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c new file mode 100644 index 0000000..d12df30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmaxq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmax.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c new file mode 100644 index 0000000..b78489c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmaxq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmax.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmaxq (a, b); +} + +/* { dg-final { scan-assembler "vmax.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c new file mode 100644 index 0000000..e529868 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16_t +foo (int16_t a, int16x8_t b) +{ + return vmaxvq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s16" } } */ + +int16_t +foo1 (int16_t a, int16x8_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c new file mode 100644 index 0000000..d4413e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b) +{ + return vmaxvq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c new file mode 100644 index 0000000..df0a452 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8_t +foo (int8_t a, int8x16_t b) +{ + return vmaxvq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s8" } } */ + +int8_t +foo1 (int8_t a, int8x16_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c new file mode 100644 index 0000000..9936b28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, uint16x8_t b) +{ + return vmaxvq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u16" } } */ + +uint16_t +foo1 (uint16_t a, uint16x8_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c new file mode 100644 index 0000000..3a93d1f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b) +{ + return vmaxvq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c new file mode 100644 index 0000000..208e2a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, uint8x16_t b) +{ + return vmaxvq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u8" } } */ + +uint8_t +foo1 (uint8_t a, uint8x16_t b) +{ + return vmaxvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxv.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c new file mode 100644 index 0000000..d63314e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vminaq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmina.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vminaq (a, b); +} + +/* { dg-final { scan-assembler "vmina.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c new file mode 100644 index 0000000..9c0da84 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vminaq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmina.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vminaq (a, b); +} + +/* { dg-final { scan-assembler "vmina.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c new file mode 100644 index 0000000..7754688 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vminaq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmina.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vminaq (a, b); +} + +/* { dg-final { scan-assembler "vmina.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c new file mode 100644 index 0000000..3fde0f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, int16x8_t b) +{ + return vminavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vminav.s16" } } */ + +uint16_t +foo1 (uint16_t a, int16x8_t b) +{ + return vminavq (a, b); +} + +/* { dg-final { scan-assembler "vminav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c new file mode 100644 index 0000000..d11604f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b) +{ + return vminavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vminav.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b) +{ + return vminavq (a, b); +} + +/* { dg-final { scan-assembler "vminav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c new file mode 100644 index 0000000..be4485d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, int8x16_t b) +{ + return vminavq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vminav.s8" } } */ + +uint8_t +foo1 (uint8_t a, int8x16_t b) +{ + return vminavq (a, b); +} + +/* { dg-final { scan-assembler "vminav.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c new file mode 100644 index 0000000..c3a6d1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vminq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmin.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c new file mode 100644 index 0000000..9f53f04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vminq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmin.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c new file mode 100644 index 0000000..7b0a077 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vminq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmin.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c new file mode 100644 index 0000000..82ace41 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vminq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmin.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c new file mode 100644 index 0000000..7649470 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vminq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmin.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c new file mode 100644 index 0000000..e2e27c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vminq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmin.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vminq (a, b); +} + +/* { dg-final { scan-assembler "vmin.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c new file mode 100644 index 0000000..3c3ccd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16_t +foo (int16_t a, int16x8_t b) +{ + return vminvq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vminv.s16" } } */ + +int16_t +foo1 (int16_t a, int16x8_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c new file mode 100644 index 0000000..0d32820 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b) +{ + return vminvq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vminv.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c new file mode 100644 index 0000000..bad7e3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8_t +foo (int8_t a, int8x16_t b) +{ + return vminvq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vminv.s8" } } */ + +int8_t +foo1 (int8_t a, int8x16_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c new file mode 100644 index 0000000..bae99af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, uint16x8_t b) +{ + return vminvq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vminv.u16" } } */ + +uint16_t +foo1 (uint16_t a, uint16x8_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c new file mode 100644 index 0000000..b706203 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b) +{ + return vminvq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vminv.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c new file mode 100644 index 0000000..f25d324 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, uint8x16_t b) +{ + return vminvq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vminv.u8" } } */ + +uint8_t +foo1 (uint8_t a, uint8x16_t b) +{ + return vminvq (a, b); +} + +/* { dg-final { scan-assembler "vminv.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c new file mode 100644 index 0000000..9e7a8ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b) +{ + return vmladavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c new file mode 100644 index 0000000..a7b0c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b) +{ + return vmladavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c new file mode 100644 index 0000000..17ccc3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b) +{ + return vmladavq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c new file mode 100644 index 0000000..cf7e011 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmladavq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u16" } } */ + +uint32_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c new file mode 100644 index 0000000..0fd673f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmladavq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u32" } } */ + +uint32_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c new file mode 100644 index 0000000..267d8ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmladavq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u8" } } */ + +uint32_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmladavq (a, b); +} + +/* { dg-final { scan-assembler "vmladav.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c new file mode 100644 index 0000000..26c4978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b) +{ + return vmladavxq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmladavxq (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c new file mode 100644 index 0000000..c27689e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b) +{ + return vmladavxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmladavxq (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c new file mode 100644 index 0000000..c586530 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b) +{ + return vmladavxq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmladavxq (a, b); +} + +/* { dg-final { scan-assembler "vmladavx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c new file mode 100644 index 0000000..17712c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlsdavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlsdavq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c new file mode 100644 index 0000000..e8d3797 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlsdavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlsdavq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c new file mode 100644 index 0000000..6d42b89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b) +{ + return vmlsdavq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmlsdavq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdav.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c new file mode 100644 index 0000000..8fa2995 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlsdavxq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlsdavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c new file mode 100644 index 0000000..d284075 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlsdavxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlsdavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c new file mode 100644 index 0000000..8dcaa94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b) +{ + return vmlsdavxq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmlsdavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c new file mode 100644 index 0000000..4fd4d09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vmulhq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c new file mode 100644 index 0000000..636e90e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vmulhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c new file mode 100644 index 0000000..b894e6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vmulhq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c new file mode 100644 index 0000000..d985f55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmulhq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c new file mode 100644 index 0000000..ab81b7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmulhq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c new file mode 100644 index 0000000..b193f69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmulhq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmulhq (a, b); +} + +/* { dg-final { scan-assembler "vmulh.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c new file mode 100644 index 0000000..f08143c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b) +{ + return vmullbq_int_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c new file mode 100644 index 0000000..be3e424 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b) +{ + return vmullbq_int_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c new file mode 100644 index 0000000..3c9f38c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, int8x16_t b) +{ + return vmullbq_int_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c new file mode 100644 index 0000000..1af9ae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmullbq_int_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c new file mode 100644 index 0000000..938d000 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmullbq_int_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u32" } } */ + +uint64x2_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c new file mode 100644 index 0000000..5ea19ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmullbq_int_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmullbq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c new file mode 100644 index 0000000..19033a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b) +{ + return vmulltq_int_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c new file mode 100644 index 0000000..f7d6fa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b) +{ + return vmulltq_int_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c new file mode 100644 index 0000000..dab3ef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, int8x16_t b) +{ + return vmulltq_int_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c new file mode 100644 index 0000000..1f0d587 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmulltq_int_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c new file mode 100644 index 0000000..71fa3be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmulltq_int_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u32" } } */ + +uint64x2_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c new file mode 100644 index 0000000..8ca4abe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmulltq_int_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmulltq_int (a, b); +} + +/* { dg-final { scan-assembler "vmullt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c new file mode 100644 index 0000000..b83d7fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vmulq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c new file mode 100644 index 0000000..5324c16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vmulq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c new file mode 100644 index 0000000..b0c6a31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vmulq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c new file mode 100644 index 0000000..8b4848d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vmulq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c new file mode 100644 index 0000000..ff1754c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vmulq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c new file mode 100644 index 0000000..f68b208 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vmulq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c new file mode 100644 index 0000000..6fd2651 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vmulq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c new file mode 100644 index 0000000..e286ed5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vmulq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c new file mode 100644 index 0000000..7c87b3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vmulq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c new file mode 100644 index 0000000..1cdbbd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmulq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c new file mode 100644 index 0000000..d042781 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmulq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c new file mode 100644 index 0000000..33df8f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmulq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c new file mode 100644 index 0000000..c291a8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vornq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c new file mode 100644 index 0000000..066958d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vornq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c new file mode 100644 index 0000000..4a773a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vornq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c new file mode 100644 index 0000000..ebcf3dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vornq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c new file mode 100644 index 0000000..742b7ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vornq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c new file mode 100644 index 0000000..ccd699a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vornq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c new file mode 100644 index 0000000..60b2700 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vorrq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c new file mode 100644 index 0000000..d8053ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vorrq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c new file mode 100644 index 0000000..4e7a69a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vorrq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c new file mode 100644 index 0000000..73225bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vorrq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c new file mode 100644 index 0000000..98753e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vorrq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c new file mode 100644 index 0000000..e2e1cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vorrq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c new file mode 100644 index 0000000..1bf77bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vqaddq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c new file mode 100644 index 0000000..8dd6542 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqaddq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c new file mode 100644 index 0000000..67cc654 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vqaddq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c new file mode 100644 index 0000000..0ab0065 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vqaddq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c new file mode 100644 index 0000000..35ce4eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vqaddq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c new file mode 100644 index 0000000..f747a7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vqaddq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vqaddq_n (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c new file mode 100644 index 0000000..64efd37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqaddq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c new file mode 100644 index 0000000..bd1c1bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqaddq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c new file mode 100644 index 0000000..9e5e4c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqaddq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c new file mode 100644 index 0000000..3ee5ff1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vqaddq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c new file mode 100644 index 0000000..571433f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vqaddq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c new file mode 100644 index 0000000..cba127e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vqaddq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vqaddq (a, b); +} + +/* { dg-final { scan-assembler "vqadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c new file mode 100644 index 0000000..e5adac2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vqdmulhq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vqdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c new file mode 100644 index 0000000..965bbd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqdmulhq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c new file mode 100644 index 0000000..60d3517 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vqdmulhq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vqdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c new file mode 100644 index 0000000..1a24bfd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqdmulhq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c new file mode 100644 index 0000000..83b74af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqdmulhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c new file mode 100644 index 0000000..62170b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqdmulhq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c new file mode 100644 index 0000000..fdeb2c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vqrdmulhq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vqrdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c new file mode 100644 index 0000000..825ef08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqrdmulhq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqrdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c new file mode 100644 index 0000000..43c2932 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vqrdmulhq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vqrdmulhq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c new file mode 100644 index 0000000..7a7d5e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqrdmulhq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqrdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c new file mode 100644 index 0000000..16a2001 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqrdmulhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqrdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c new file mode 100644 index 0000000..3350abd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqrdmulhq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqrdmulhq (a, b); +} + +/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c new file mode 100644 index 0000000..c4f7a2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b) +{ + return vqrshlq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c new file mode 100644 index 0000000..8478efa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqrshlq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c new file mode 100644 index 0000000..af40991 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b) +{ + return vqrshlq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c new file mode 100644 index 0000000..20fd1bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b) +{ + return vqrshlq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c new file mode 100644 index 0000000..e235c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b) +{ + return vqrshlq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c new file mode 100644 index 0000000..ecd4a5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b) +{ + return vqrshlq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b) +{ + return vqrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c new file mode 100644 index 0000000..03e9bbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqrshlq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c new file mode 100644 index 0000000..6f0cf54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqrshlq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c new file mode 100644 index 0000000..451607e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqrshlq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c new file mode 100644 index 0000000..f59823f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vqrshlq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c new file mode 100644 index 0000000..d3744db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vqrshlq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c new file mode 100644 index 0000000..a3e8da3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vqrshlq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vqrshlq (a, b); +} + +/* { dg-final { scan-assembler "vqrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c new file mode 100644 index 0000000..0880cb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vqshlq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c new file mode 100644 index 0000000..3a56f35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vqshlq_n_s32 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c new file mode 100644 index 0000000..28f384c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vqshlq_n_s8 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c new file mode 100644 index 0000000..8beb722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vqshlq_n_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c new file mode 100644 index 0000000..ef616dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vqshlq_n_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c new file mode 100644 index 0000000..a85ef65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vqshlq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vqshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c new file mode 100644 index 0000000..46a02f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b) +{ + return vqshlq_r_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c new file mode 100644 index 0000000..e53f613 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqshlq_r_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c new file mode 100644 index 0000000..1cbd5d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b) +{ + return vqshlq_r_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c new file mode 100644 index 0000000..3503245 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b) +{ + return vqshlq_r_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c new file mode 100644 index 0000000..9d3dbcd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b) +{ + return vqshlq_r_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c new file mode 100644 index 0000000..4466e9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b) +{ + return vqshlq_r_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b) +{ + return vqshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c new file mode 100644 index 0000000..867e7e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqshlq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c new file mode 100644 index 0000000..121debf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqshlq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c new file mode 100644 index 0000000..cfcb38f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqshlq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c new file mode 100644 index 0000000..43b53d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vqshlq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c new file mode 100644 index 0000000..af63eeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vqshlq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c new file mode 100644 index 0000000..691e7be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vqshlq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vqshlq (a, b); +} + +/* { dg-final { scan-assembler "vqshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c new file mode 100644 index 0000000..79418d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (int16x8_t a) +{ + return vqshluq_n_s16 (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s16" } } */ + +uint16x8_t +foo1 (int16x8_t a) +{ + return vqshluq_n (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c new file mode 100644 index 0000000..10e8fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (int32x4_t a) +{ + return vqshluq_n_s32 (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s32" } } */ + +uint32x4_t +foo1 (int32x4_t a) +{ + return vqshluq_n (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c new file mode 100644 index 0000000..920b1b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (int8x16_t a) +{ + return vqshluq_n_s8 (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s8" } } */ + +uint8x16_t +foo1 (int8x16_t a) +{ + return vqshluq_n (a, 7); +} + +/* { dg-final { scan-assembler "vqshlu.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c new file mode 100644 index 0000000..0da54b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vqsubq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c new file mode 100644 index 0000000..5db6fee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vqsubq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c new file mode 100644 index 0000000..96519ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vqsubq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c new file mode 100644 index 0000000..c735629 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vqsubq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c new file mode 100644 index 0000000..a196593a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vqsubq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c new file mode 100644 index 0000000..981d623 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vqsubq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vqsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c new file mode 100644 index 0000000..26be587 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vqsubq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c new file mode 100644 index 0000000..9739a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vqsubq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c new file mode 100644 index 0000000..1bdf354 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vqsubq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c new file mode 100644 index 0000000..1f29987 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vqsubq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c new file mode 100644 index 0000000..6ff6121 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vqsubq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c new file mode 100644 index 0000000..daa3e87 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vqsubq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vqsubq (a, b); +} + +/* { dg-final { scan-assembler "vqsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c new file mode 100644 index 0000000..5bb7897 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vrhaddq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c new file mode 100644 index 0000000..33a145c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vrhaddq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c new file mode 100644 index 0000000..9e7fe95f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vrhaddq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c new file mode 100644 index 0000000..ff0b5a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vrhaddq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c new file mode 100644 index 0000000..ba16e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vrhaddq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c new file mode 100644 index 0000000..a3fadd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vrhaddq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vrhaddq (a, b); +} + +/* { dg-final { scan-assembler "vrhadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c new file mode 100644 index 0000000..44b3885 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vrmulhq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c new file mode 100644 index 0000000..174a60a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vrmulhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c new file mode 100644 index 0000000..89dbd6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vrmulhq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c new file mode 100644 index 0000000..4fb76f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vrmulhq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c new file mode 100644 index 0000000..7b52833 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vrmulhq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c new file mode 100644 index 0000000..a151828 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vrmulhq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vrmulhq (a, b); +} + +/* { dg-final { scan-assembler "vrmulh.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c new file mode 100644 index 0000000..bd380f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b) +{ + return vrshlq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c new file mode 100644 index 0000000..9f7051d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vrshlq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c new file mode 100644 index 0000000..04e3321 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b) +{ + return vrshlq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c new file mode 100644 index 0000000..fc3c87d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b) +{ + return vrshlq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c new file mode 100644 index 0000000..937f145 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b) +{ + return vrshlq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c new file mode 100644 index 0000000..68c967f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b) +{ + return vrshlq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b) +{ + return vrshlq_n (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c new file mode 100644 index 0000000..9cc6bce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vrshlq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c new file mode 100644 index 0000000..cbc68db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vrshlq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c new file mode 100644 index 0000000..08fbc16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vrshlq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c new file mode 100644 index 0000000..db530b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b) +{ + return vrshlq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c new file mode 100644 index 0000000..ecb5ea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b) +{ + return vrshlq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c new file mode 100644 index 0000000..09ffca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b) +{ + return vrshlq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b) +{ + return vrshlq (a, b); +} + +/* { dg-final { scan-assembler "vrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c new file mode 100644 index 0000000..04147e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vrshrq_n_s16 (a, 16); +} + +/* { dg-final { scan-assembler "vrshr.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vrshrq_n (a, 16); +} + +/* { dg-final { scan-assembler "vrshr.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c new file mode 100644 index 0000000..4c68cf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vrshrq_n_s32 (a, 32); +} + +/* { dg-final { scan-assembler "vrshr.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vrshrq_n (a, 32); +} + +/* { dg-final { scan-assembler "vrshr.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c new file mode 100644 index 0000000..5263272 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrshrq_n_s8 (a, 8); +} + +/* { dg-final { scan-assembler "vrshr.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrshrq_n (a, 8); +} + +/* { dg-final { scan-assembler "vrshr.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c new file mode 100644 index 0000000..5952a48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vrshrq_n_u16 (a, 16); +} + +/* { dg-final { scan-assembler "vrshr.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vrshrq_n (a, 16); +} + +/* { dg-final { scan-assembler "vrshr.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c new file mode 100644 index 0000000..507f2dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vrshrq_n_u32 (a, 32); +} + +/* { dg-final { scan-assembler "vrshr.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vrshrq_n (a, 32); +} + +/* { dg-final { scan-assembler "vrshr.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c new file mode 100644 index 0000000..ec882da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrshrq_n_u8 (a, 8); +} + +/* { dg-final { scan-assembler "vrshr.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrshrq_n (a, 8); +} + +/* { dg-final { scan-assembler "vrshr.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c new file mode 100644 index 0000000..12bde64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vshlq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c new file mode 100644 index 0000000..64b797b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vshlq_n_s32 (a, 16); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vshlq_n (a, 16); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c new file mode 100644 index 0000000..df495c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vshlq_n_s8 (a, 1); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c new file mode 100644 index 0000000..d2c1a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vshlq_n_u16 (a, 11); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vshlq_n (a, 11); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c new file mode 100644 index 0000000..17c4697 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vshlq_n_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c new file mode 100644 index 0000000..dbbfee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vshlq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vshlq_n (a, 1); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c new file mode 100644 index 0000000..1a571da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b) +{ + return vshlq_r_s16 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c new file mode 100644 index 0000000..0402912 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vshlq_r_s32 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c new file mode 100644 index 0000000..c75ab26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b) +{ + return vshlq_r_s8 (a, b); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c new file mode 100644 index 0000000..7f1f83c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b) +{ + return vshlq_r_u16 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c new file mode 100644 index 0000000..bfed41d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b) +{ + return vshlq_r_u32 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c new file mode 100644 index 0000000..add49f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b) +{ + return vshlq_r_u8 (a, b); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b) +{ + return vshlq_r (a, b); +} + +/* { dg-final { scan-assembler "vshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c new file mode 100644 index 0000000..49153b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b) +{ + return vsubq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c new file mode 100644 index 0000000..c337a48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b) +{ + return vsubq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c new file mode 100644 index 0000000..f3652b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b) +{ + return vsubq_n_s8 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c new file mode 100644 index 0000000..c2f67d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b) +{ + return vsubq_n_u16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c new file mode 100644 index 0000000..c5b5975 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b) +{ + return vsubq_n_u32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c new file mode 100644 index 0000000..8088ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b) +{ + return vsubq_n_u8 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b) +{ + return vsubq_n (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c new file mode 100644 index 0000000..2b98e4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vsubq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c new file mode 100644 index 0000000..847d56b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vsubq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c new file mode 100644 index 0000000..bbf40ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vsubq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c new file mode 100644 index 0000000..a57093c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vsubq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c new file mode 100644 index 0000000..964fbfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vsubq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c new file mode 100644 index 0000000..f900ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vsubq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.i8" } } */ -- cgit v1.1 From f9355dee93fce833b307c4e8e7eb6d9a7d831333 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 15:44:52 +0000 Subject: [ARM][GCC][5/2x]: MVE intrinsics with binary operands. This patch supports following MVE ACLE intrinsics with binary operands. vqmovntq_u16, vqmovnbq_u16, vmulltq_poly_p8, vmullbq_poly_p8, vmovntq_u16, vmovnbq_u16, vmlaldavxq_u16, vmlaldavq_u16, vqmovuntq_s16, vqmovunbq_s16, vshlltq_n_u8, vshllbq_n_u8, vorrq_n_u16, vbicq_n_u16, vcmpneq_n_f16, vcmpneq_f16, vcmpltq_n_f16, vcmpltq_f16, vcmpleq_n_f16, vcmpleq_f16, vcmpgtq_n_f16, vcmpgtq_f16, vcmpgeq_n_f16, vcmpgeq_f16, vcmpeqq_n_f16, vcmpeqq_f16, vsubq_f16, vqmovntq_s16, vqmovnbq_s16, vqdmulltq_s16, vqdmulltq_n_s16, vqdmullbq_s16, vqdmullbq_n_s16, vorrq_f16, vornq_f16, vmulq_n_f16, vmulq_f16, vmovntq_s16, vmovnbq_s16, vmlsldavxq_s16, vmlsldavq_s16, vmlaldavxq_s16, vmlaldavq_s16, vminnmvq_f16, vminnmq_f16, vminnmavq_f16, vminnmaq_f16, vmaxnmvq_f16, vmaxnmq_f16, vmaxnmavq_f16, vmaxnmaq_f16, veorq_f16, vcmulq_rot90_f16, vcmulq_rot270_f16, vcmulq_rot180_f16, vcmulq_f16, vcaddq_rot90_f16, vcaddq_rot270_f16, vbicq_f16, vandq_f16, vaddq_n_f16, vabdq_f16, vshlltq_n_s8, vshllbq_n_s8, vorrq_n_s16, vbicq_n_s16, vqmovntq_u32, vqmovnbq_u32, vmulltq_poly_p16, vmullbq_poly_p16, vmovntq_u32, vmovnbq_u32, vmlaldavxq_u32, vmlaldavq_u32, vqmovuntq_s32, vqmovunbq_s32, vshlltq_n_u16, vshllbq_n_u16, vorrq_n_u32, vbicq_n_u32, vcmpneq_n_f32, vcmpneq_f32, vcmpltq_n_f32, vcmpltq_f32, vcmpleq_n_f32, vcmpleq_f32, vcmpgtq_n_f32, vcmpgtq_f32, vcmpgeq_n_f32, vcmpgeq_f32, vcmpeqq_n_f32, vcmpeqq_f32, vsubq_f32, vqmovntq_s32, vqmovnbq_s32, vqdmulltq_s32, vqdmulltq_n_s32, vqdmullbq_s32, vqdmullbq_n_s32, vorrq_f32, vornq_f32, vmulq_n_f32, vmulq_f32, vmovntq_s32, vmovnbq_s32, vmlsldavxq_s32, vmlsldavq_s32, vmlaldavxq_s32, vmlaldavq_s32, vminnmvq_f32, vminnmq_f32, vminnmavq_f32, vminnmaq_f32, vmaxnmvq_f32, vmaxnmq_f32, vmaxnmavq_f32, vmaxnmaq_f32, veorq_f32, vcmulq_rot90_f32, vcmulq_rot270_f32, vcmulq_rot180_f32, vcmulq_f32, vcaddq_rot90_f32, vcaddq_rot270_f32, vbicq_f32, vandq_f32, vaddq_n_f32, vabdq_f32, vshlltq_n_s16, vshllbq_n_s16, vorrq_n_s32, vbicq_n_s32, vrmlaldavhq_u32, vctp8q_m, vctp64q_m, vctp32q_m, vctp16q_m, vaddlvaq_u32, vrmlsldavhxq_s32, vrmlsldavhq_s32, vrmlaldavhxq_s32, vrmlaldavhq_s32, vcvttq_f16_f32, vcvtbq_f16_f32, vaddlvaq_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics The above intrinsics are defined using the already defined builtin qualifiers BINOP_NONE_NONE_IMM, BINOP_NONE_NONE_NONE, BINOP_UNONE_NONE_NONE, BINOP_UNONE_UNONE_IMM, BINOP_UNONE_UNONE_NONE, BINOP_UNONE_UNONE_UNONE. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vqmovntq_u16): Define macro. (vqmovnbq_u16): Likewise. (vmulltq_poly_p8): Likewise. (vmullbq_poly_p8): Likewise. (vmovntq_u16): Likewise. (vmovnbq_u16): Likewise. (vmlaldavxq_u16): Likewise. (vmlaldavq_u16): Likewise. (vqmovuntq_s16): Likewise. (vqmovunbq_s16): Likewise. (vshlltq_n_u8): Likewise. (vshllbq_n_u8): Likewise. (vorrq_n_u16): Likewise. (vbicq_n_u16): Likewise. (vcmpneq_n_f16): Likewise. (vcmpneq_f16): Likewise. (vcmpltq_n_f16): Likewise. (vcmpltq_f16): Likewise. (vcmpleq_n_f16): Likewise. (vcmpleq_f16): Likewise. (vcmpgtq_n_f16): Likewise. (vcmpgtq_f16): Likewise. (vcmpgeq_n_f16): Likewise. (vcmpgeq_f16): Likewise. (vcmpeqq_n_f16): Likewise. (vcmpeqq_f16): Likewise. (vsubq_f16): Likewise. (vqmovntq_s16): Likewise. (vqmovnbq_s16): Likewise. (vqdmulltq_s16): Likewise. (vqdmulltq_n_s16): Likewise. (vqdmullbq_s16): Likewise. (vqdmullbq_n_s16): Likewise. (vorrq_f16): Likewise. (vornq_f16): Likewise. (vmulq_n_f16): Likewise. (vmulq_f16): Likewise. (vmovntq_s16): Likewise. (vmovnbq_s16): Likewise. (vmlsldavxq_s16): Likewise. (vmlsldavq_s16): Likewise. (vmlaldavxq_s16): Likewise. (vmlaldavq_s16): Likewise. (vminnmvq_f16): Likewise. (vminnmq_f16): Likewise. (vminnmavq_f16): Likewise. (vminnmaq_f16): Likewise. (vmaxnmvq_f16): Likewise. (vmaxnmq_f16): Likewise. (vmaxnmavq_f16): Likewise. (vmaxnmaq_f16): Likewise. (veorq_f16): Likewise. (vcmulq_rot90_f16): Likewise. (vcmulq_rot270_f16): Likewise. (vcmulq_rot180_f16): Likewise. (vcmulq_f16): Likewise. (vcaddq_rot90_f16): Likewise. (vcaddq_rot270_f16): Likewise. (vbicq_f16): Likewise. (vandq_f16): Likewise. (vaddq_n_f16): Likewise. (vabdq_f16): Likewise. (vshlltq_n_s8): Likewise. (vshllbq_n_s8): Likewise. (vorrq_n_s16): Likewise. (vbicq_n_s16): Likewise. (vqmovntq_u32): Likewise. (vqmovnbq_u32): Likewise. (vmulltq_poly_p16): Likewise. (vmullbq_poly_p16): Likewise. (vmovntq_u32): Likewise. (vmovnbq_u32): Likewise. (vmlaldavxq_u32): Likewise. (vmlaldavq_u32): Likewise. (vqmovuntq_s32): Likewise. (vqmovunbq_s32): Likewise. (vshlltq_n_u16): Likewise. (vshllbq_n_u16): Likewise. (vorrq_n_u32): Likewise. (vbicq_n_u32): Likewise. (vcmpneq_n_f32): Likewise. (vcmpneq_f32): Likewise. (vcmpltq_n_f32): Likewise. (vcmpltq_f32): Likewise. (vcmpleq_n_f32): Likewise. (vcmpleq_f32): Likewise. (vcmpgtq_n_f32): Likewise. (vcmpgtq_f32): Likewise. (vcmpgeq_n_f32): Likewise. (vcmpgeq_f32): Likewise. (vcmpeqq_n_f32): Likewise. (vcmpeqq_f32): Likewise. (vsubq_f32): Likewise. (vqmovntq_s32): Likewise. (vqmovnbq_s32): Likewise. (vqdmulltq_s32): Likewise. (vqdmulltq_n_s32): Likewise. (vqdmullbq_s32): Likewise. (vqdmullbq_n_s32): Likewise. (vorrq_f32): Likewise. (vornq_f32): Likewise. (vmulq_n_f32): Likewise. (vmulq_f32): Likewise. (vmovntq_s32): Likewise. (vmovnbq_s32): Likewise. (vmlsldavxq_s32): Likewise. (vmlsldavq_s32): Likewise. (vmlaldavxq_s32): Likewise. (vmlaldavq_s32): Likewise. (vminnmvq_f32): Likewise. (vminnmq_f32): Likewise. (vminnmavq_f32): Likewise. (vminnmaq_f32): Likewise. (vmaxnmvq_f32): Likewise. (vmaxnmq_f32): Likewise. (vmaxnmavq_f32): Likewise. (vmaxnmaq_f32): Likewise. (veorq_f32): Likewise. (vcmulq_rot90_f32): Likewise. (vcmulq_rot270_f32): Likewise. (vcmulq_rot180_f32): Likewise. (vcmulq_f32): Likewise. (vcaddq_rot90_f32): Likewise. (vcaddq_rot270_f32): Likewise. (vbicq_f32): Likewise. (vandq_f32): Likewise. (vaddq_n_f32): Likewise. (vabdq_f32): Likewise. (vshlltq_n_s16): Likewise. (vshllbq_n_s16): Likewise. (vorrq_n_s32): Likewise. (vbicq_n_s32): Likewise. (vrmlaldavhq_u32): Likewise. (vctp8q_m): Likewise. (vctp64q_m): Likewise. (vctp32q_m): Likewise. (vctp16q_m): Likewise. (vaddlvaq_u32): Likewise. (vrmlsldavhxq_s32): Likewise. (vrmlsldavhq_s32): Likewise. (vrmlaldavhxq_s32): Likewise. (vrmlaldavhq_s32): Likewise. (vcvttq_f16_f32): Likewise. (vcvtbq_f16_f32): Likewise. (vaddlvaq_s32): Likewise. (__arm_vqmovntq_u16): Define intrinsic. (__arm_vqmovnbq_u16): Likewise. (__arm_vmulltq_poly_p8): Likewise. (__arm_vmullbq_poly_p8): Likewise. (__arm_vmovntq_u16): Likewise. (__arm_vmovnbq_u16): Likewise. (__arm_vmlaldavxq_u16): Likewise. (__arm_vmlaldavq_u16): Likewise. (__arm_vqmovuntq_s16): Likewise. (__arm_vqmovunbq_s16): Likewise. (__arm_vshlltq_n_u8): Likewise. (__arm_vshllbq_n_u8): Likewise. (__arm_vorrq_n_u16): Likewise. (__arm_vbicq_n_u16): Likewise. (__arm_vcmpneq_n_f16): Likewise. (__arm_vcmpneq_f16): Likewise. (__arm_vcmpltq_n_f16): Likewise. (__arm_vcmpltq_f16): Likewise. (__arm_vcmpleq_n_f16): Likewise. (__arm_vcmpleq_f16): Likewise. (__arm_vcmpgtq_n_f16): Likewise. (__arm_vcmpgtq_f16): Likewise. (__arm_vcmpgeq_n_f16): Likewise. (__arm_vcmpgeq_f16): Likewise. (__arm_vcmpeqq_n_f16): Likewise. (__arm_vcmpeqq_f16): Likewise. (__arm_vsubq_f16): Likewise. (__arm_vqmovntq_s16): Likewise. (__arm_vqmovnbq_s16): Likewise. (__arm_vqdmulltq_s16): Likewise. (__arm_vqdmulltq_n_s16): Likewise. (__arm_vqdmullbq_s16): Likewise. (__arm_vqdmullbq_n_s16): Likewise. (__arm_vorrq_f16): Likewise. (__arm_vornq_f16): Likewise. (__arm_vmulq_n_f16): Likewise. (__arm_vmulq_f16): Likewise. (__arm_vmovntq_s16): Likewise. (__arm_vmovnbq_s16): Likewise. (__arm_vmlsldavxq_s16): Likewise. (__arm_vmlsldavq_s16): Likewise. (__arm_vmlaldavxq_s16): Likewise. (__arm_vmlaldavq_s16): Likewise. (__arm_vminnmvq_f16): Likewise. (__arm_vminnmq_f16): Likewise. (__arm_vminnmavq_f16): Likewise. (__arm_vminnmaq_f16): Likewise. (__arm_vmaxnmvq_f16): Likewise. (__arm_vmaxnmq_f16): Likewise. (__arm_vmaxnmavq_f16): Likewise. (__arm_vmaxnmaq_f16): Likewise. (__arm_veorq_f16): Likewise. (__arm_vcmulq_rot90_f16): Likewise. (__arm_vcmulq_rot270_f16): Likewise. (__arm_vcmulq_rot180_f16): Likewise. (__arm_vcmulq_f16): Likewise. (__arm_vcaddq_rot90_f16): Likewise. (__arm_vcaddq_rot270_f16): Likewise. (__arm_vbicq_f16): Likewise. (__arm_vandq_f16): Likewise. (__arm_vaddq_n_f16): Likewise. (__arm_vabdq_f16): Likewise. (__arm_vshlltq_n_s8): Likewise. (__arm_vshllbq_n_s8): Likewise. (__arm_vorrq_n_s16): Likewise. (__arm_vbicq_n_s16): Likewise. (__arm_vqmovntq_u32): Likewise. (__arm_vqmovnbq_u32): Likewise. (__arm_vmulltq_poly_p16): Likewise. (__arm_vmullbq_poly_p16): Likewise. (__arm_vmovntq_u32): Likewise. (__arm_vmovnbq_u32): Likewise. (__arm_vmlaldavxq_u32): Likewise. (__arm_vmlaldavq_u32): Likewise. (__arm_vqmovuntq_s32): Likewise. (__arm_vqmovunbq_s32): Likewise. (__arm_vshlltq_n_u16): Likewise. (__arm_vshllbq_n_u16): Likewise. (__arm_vorrq_n_u32): Likewise. (__arm_vbicq_n_u32): Likewise. (__arm_vcmpneq_n_f32): Likewise. (__arm_vcmpneq_f32): Likewise. (__arm_vcmpltq_n_f32): Likewise. (__arm_vcmpltq_f32): Likewise. (__arm_vcmpleq_n_f32): Likewise. (__arm_vcmpleq_f32): Likewise. (__arm_vcmpgtq_n_f32): Likewise. (__arm_vcmpgtq_f32): Likewise. (__arm_vcmpgeq_n_f32): Likewise. (__arm_vcmpgeq_f32): Likewise. (__arm_vcmpeqq_n_f32): Likewise. (__arm_vcmpeqq_f32): Likewise. (__arm_vsubq_f32): Likewise. (__arm_vqmovntq_s32): Likewise. (__arm_vqmovnbq_s32): Likewise. (__arm_vqdmulltq_s32): Likewise. (__arm_vqdmulltq_n_s32): Likewise. (__arm_vqdmullbq_s32): Likewise. (__arm_vqdmullbq_n_s32): Likewise. (__arm_vorrq_f32): Likewise. (__arm_vornq_f32): Likewise. (__arm_vmulq_n_f32): Likewise. (__arm_vmulq_f32): Likewise. (__arm_vmovntq_s32): Likewise. (__arm_vmovnbq_s32): Likewise. (__arm_vmlsldavxq_s32): Likewise. (__arm_vmlsldavq_s32): Likewise. (__arm_vmlaldavxq_s32): Likewise. (__arm_vmlaldavq_s32): Likewise. (__arm_vminnmvq_f32): Likewise. (__arm_vminnmq_f32): Likewise. (__arm_vminnmavq_f32): Likewise. (__arm_vminnmaq_f32): Likewise. (__arm_vmaxnmvq_f32): Likewise. (__arm_vmaxnmq_f32): Likewise. (__arm_vmaxnmavq_f32): Likewise. (__arm_vmaxnmaq_f32): Likewise. (__arm_veorq_f32): Likewise. (__arm_vcmulq_rot90_f32): Likewise. (__arm_vcmulq_rot270_f32): Likewise. (__arm_vcmulq_rot180_f32): Likewise. (__arm_vcmulq_f32): Likewise. (__arm_vcaddq_rot90_f32): Likewise. (__arm_vcaddq_rot270_f32): Likewise. (__arm_vbicq_f32): Likewise. (__arm_vandq_f32): Likewise. (__arm_vaddq_n_f32): Likewise. (__arm_vabdq_f32): Likewise. (__arm_vshlltq_n_s16): Likewise. (__arm_vshllbq_n_s16): Likewise. (__arm_vorrq_n_s32): Likewise. (__arm_vbicq_n_s32): Likewise. (__arm_vrmlaldavhq_u32): Likewise. (__arm_vctp8q_m): Likewise. (__arm_vctp64q_m): Likewise. (__arm_vctp32q_m): Likewise. (__arm_vctp16q_m): Likewise. (__arm_vaddlvaq_u32): Likewise. (__arm_vrmlsldavhxq_s32): Likewise. (__arm_vrmlsldavhq_s32): Likewise. (__arm_vrmlaldavhxq_s32): Likewise. (__arm_vrmlaldavhq_s32): Likewise. (__arm_vcvttq_f16_f32): Likewise. (__arm_vcvtbq_f16_f32): Likewise. (__arm_vaddlvaq_s32): Likewise. (vst4q): Define polymorphic variant. (vrndxq): Likewise. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vdupq_n): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. (vsubq_n): Likewise. (vbrsrq_n): Likewise. (vcvtq_n): Likewise. (vsubq): Likewise. (vorrq): Likewise. (vabdq): Likewise. (vaddq_n): Likewise. (vandq): Likewise. (vbicq): Likewise. (vornq): Likewise. (vmulq_n): Likewise. (vmulq): Likewise. (vcaddq_rot270): Likewise. (vcmpeqq_n): Likewise. (vcmpeqq): Likewise. (vcaddq_rot90): Likewise. (vcmpgeq_n): Likewise. (vcmpgeq): Likewise. (vcmpgtq_n): Likewise. (vcmpgtq): Likewise. (vcmpgtq): Likewise. (vcmpleq_n): Likewise. (vcmpleq_n): Likewise. (vcmpleq): Likewise. (vcmpleq): Likewise. (vcmpltq_n): Likewise. (vcmpltq_n): Likewise. (vcmpltq): Likewise. (vcmpltq): Likewise. (vcmpneq_n): Likewise. (vcmpneq_n): Likewise. (vcmpneq): Likewise. (vcmpneq): Likewise. (vcmulq): Likewise. (vcmulq): Likewise. (vcmulq_rot180): Likewise. (vcmulq_rot180): Likewise. (vcmulq_rot270): Likewise. (vcmulq_rot270): Likewise. (vcmulq_rot90): Likewise. (vcmulq_rot90): Likewise. (veorq): Likewise. (veorq): Likewise. (vmaxnmaq): Likewise. (vmaxnmaq): Likewise. (vmaxnmavq): Likewise. (vmaxnmavq): Likewise. (vmaxnmq): Likewise. (vmaxnmq): Likewise. (vmaxnmvq): Likewise. (vmaxnmvq): Likewise. (vminnmaq): Likewise. (vminnmaq): Likewise. (vminnmavq): Likewise. (vminnmavq): Likewise. (vminnmq): Likewise. (vminnmq): Likewise. (vminnmvq): Likewise. (vminnmvq): Likewise. (vbicq_n): Likewise. (vqmovntq): Likewise. (vqmovntq): Likewise. (vqmovnbq): Likewise. (vqmovnbq): Likewise. (vmulltq_poly): Likewise. (vmulltq_poly): Likewise. (vmullbq_poly): Likewise. (vmullbq_poly): Likewise. (vmovntq): Likewise. (vmovntq): Likewise. (vmovnbq): Likewise. (vmovnbq): Likewise. (vmlaldavxq): Likewise. (vmlaldavxq): Likewise. (vqmovuntq): Likewise. (vqmovuntq): Likewise. (vshlltq_n): Likewise. (vshlltq_n): Likewise. (vshllbq_n): Likewise. (vshllbq_n): Likewise. (vorrq_n): Likewise. (vorrq_n): Likewise. (vmlaldavq): Likewise. (vmlaldavq): Likewise. (vqmovunbq): Likewise. (vqmovunbq): Likewise. (vqdmulltq_n): Likewise. (vqdmulltq_n): Likewise. (vqdmulltq): Likewise. (vqdmulltq): Likewise. (vqdmullbq_n): Likewise. (vqdmullbq_n): Likewise. (vqdmullbq): Likewise. (vqdmullbq): Likewise. (vaddlvaq): Likewise. (vaddlvaq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhxq): Likewise. (vrmlaldavhxq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhxq): Likewise. (vrmlsldavhxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavq): Likewise. (vmlsldavq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. (BINOP_NONE_NONE_NONE): Likewise. (BINOP_UNONE_NONE_NONE): Likewise. (BINOP_UNONE_UNONE_IMM): Likewise. (BINOP_UNONE_UNONE_NONE): Likewise. (BINOP_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (mve_vabdq_f): Define RTL pattern. (mve_vaddlvaq_v4si): Likewise. (mve_vaddq_n_f): Likewise. (mve_vandq_f): Likewise. (mve_vbicq_f): Likewise. (mve_vbicq_n_): Likewise. (mve_vcaddq_rot270_f): Likewise. (mve_vcaddq_rot90_f): Likewise. (mve_vcmpeqq_f): Likewise. (mve_vcmpeqq_n_f): Likewise. (mve_vcmpgeq_f): Likewise. (mve_vcmpgeq_n_f): Likewise. (mve_vcmpgtq_f): Likewise. (mve_vcmpgtq_n_f): Likewise. (mve_vcmpleq_f): Likewise. (mve_vcmpleq_n_f): Likewise. (mve_vcmpltq_f): Likewise. (mve_vcmpltq_n_f): Likewise. (mve_vcmpneq_f): Likewise. (mve_vcmpneq_n_f): Likewise. (mve_vcmulq_f): Likewise. (mve_vcmulq_rot180_f): Likewise. (mve_vcmulq_rot270_f): Likewise. (mve_vcmulq_rot90_f): Likewise. (mve_vctpq_mhi): Likewise. (mve_vcvtbq_f16_f32v8hf): Likewise. (mve_vcvttq_f16_f32v8hf): Likewise. (mve_veorq_f): Likewise. (mve_vmaxnmaq_f): Likewise. (mve_vmaxnmavq_f): Likewise. (mve_vmaxnmq_f): Likewise. (mve_vmaxnmvq_f): Likewise. (mve_vminnmaq_f): Likewise. (mve_vminnmavq_f): Likewise. (mve_vminnmq_f): Likewise. (mve_vminnmvq_f): Likewise. (mve_vmlaldavq_): Likewise. (mve_vmlaldavxq_): Likewise. (mve_vmlsldavq_s): Likewise. (mve_vmlsldavxq_s): Likewise. (mve_vmovnbq_): Likewise. (mve_vmovntq_): Likewise. (mve_vmulq_f): Likewise. (mve_vmulq_n_f): Likewise. (mve_vornq_f): Likewise. (mve_vorrq_f): Likewise. (mve_vorrq_n_): Likewise. (mve_vqdmullbq_n_s): Likewise. (mve_vqdmullbq_s): Likewise. (mve_vqdmulltq_n_s): Likewise. (mve_vqdmulltq_s): Likewise. (mve_vqmovnbq_): Likewise. (mve_vqmovntq_): Likewise. (mve_vqmovunbq_s): Likewise. (mve_vqmovuntq_s): Likewise. (mve_vrmlaldavhxq_sv4si): Likewise. (mve_vrmlsldavhq_sv4si): Likewise. (mve_vrmlsldavhxq_sv4si): Likewise. (mve_vshllbq_n_): Likewise. (mve_vshlltq_n_): Likewise. (mve_vsubq_f): Likewise. (mve_vmulltq_poly_p): Likewise. (mve_vmullbq_poly_p): Likewise. (mve_vrmlaldavhq_v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. --- gcc/ChangeLog | 488 +++ gcc/config/arm/arm_mve.h | 3279 ++++++++++++++++---- gcc/config/arm/arm_mve_builtins.def | 468 +-- gcc/config/arm/mve.md | 1008 +++++- gcc/testsuite/ChangeLog | 150 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 14 + .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 22 + 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100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index feecf92..af2a867 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,494 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vqmovntq_u16): Define macro. + (vqmovnbq_u16): Likewise. + (vmulltq_poly_p8): Likewise. + (vmullbq_poly_p8): Likewise. + (vmovntq_u16): Likewise. + (vmovnbq_u16): Likewise. + (vmlaldavxq_u16): Likewise. + (vmlaldavq_u16): Likewise. + (vqmovuntq_s16): Likewise. + (vqmovunbq_s16): Likewise. + (vshlltq_n_u8): Likewise. + (vshllbq_n_u8): Likewise. + (vorrq_n_u16): Likewise. + (vbicq_n_u16): Likewise. + (vcmpneq_n_f16): Likewise. + (vcmpneq_f16): Likewise. + (vcmpltq_n_f16): Likewise. + (vcmpltq_f16): Likewise. + (vcmpleq_n_f16): Likewise. + (vcmpleq_f16): Likewise. + (vcmpgtq_n_f16): Likewise. + (vcmpgtq_f16): Likewise. + (vcmpgeq_n_f16): Likewise. + (vcmpgeq_f16): Likewise. + (vcmpeqq_n_f16): Likewise. + (vcmpeqq_f16): Likewise. + (vsubq_f16): Likewise. + (vqmovntq_s16): Likewise. + (vqmovnbq_s16): Likewise. + (vqdmulltq_s16): Likewise. + (vqdmulltq_n_s16): Likewise. + (vqdmullbq_s16): Likewise. + (vqdmullbq_n_s16): Likewise. + (vorrq_f16): Likewise. + (vornq_f16): Likewise. + (vmulq_n_f16): Likewise. + (vmulq_f16): Likewise. + (vmovntq_s16): Likewise. + (vmovnbq_s16): Likewise. + (vmlsldavxq_s16): Likewise. + (vmlsldavq_s16): Likewise. + (vmlaldavxq_s16): Likewise. + (vmlaldavq_s16): Likewise. + (vminnmvq_f16): Likewise. + (vminnmq_f16): Likewise. + (vminnmavq_f16): Likewise. + (vminnmaq_f16): Likewise. + (vmaxnmvq_f16): Likewise. + (vmaxnmq_f16): Likewise. + (vmaxnmavq_f16): Likewise. + (vmaxnmaq_f16): Likewise. + (veorq_f16): Likewise. + (vcmulq_rot90_f16): Likewise. + (vcmulq_rot270_f16): Likewise. + (vcmulq_rot180_f16): Likewise. + (vcmulq_f16): Likewise. + (vcaddq_rot90_f16): Likewise. + (vcaddq_rot270_f16): Likewise. + (vbicq_f16): Likewise. + (vandq_f16): Likewise. + (vaddq_n_f16): Likewise. + (vabdq_f16): Likewise. + (vshlltq_n_s8): Likewise. + (vshllbq_n_s8): Likewise. + (vorrq_n_s16): Likewise. + (vbicq_n_s16): Likewise. + (vqmovntq_u32): Likewise. + (vqmovnbq_u32): Likewise. + (vmulltq_poly_p16): Likewise. + (vmullbq_poly_p16): Likewise. + (vmovntq_u32): Likewise. + (vmovnbq_u32): Likewise. + (vmlaldavxq_u32): Likewise. + (vmlaldavq_u32): Likewise. + (vqmovuntq_s32): Likewise. + (vqmovunbq_s32): Likewise. + (vshlltq_n_u16): Likewise. + (vshllbq_n_u16): Likewise. + (vorrq_n_u32): Likewise. + (vbicq_n_u32): Likewise. + (vcmpneq_n_f32): Likewise. + (vcmpneq_f32): Likewise. + (vcmpltq_n_f32): Likewise. + (vcmpltq_f32): Likewise. + (vcmpleq_n_f32): Likewise. + (vcmpleq_f32): Likewise. + (vcmpgtq_n_f32): Likewise. + (vcmpgtq_f32): Likewise. + (vcmpgeq_n_f32): Likewise. + (vcmpgeq_f32): Likewise. + (vcmpeqq_n_f32): Likewise. + (vcmpeqq_f32): Likewise. + (vsubq_f32): Likewise. + (vqmovntq_s32): Likewise. + (vqmovnbq_s32): Likewise. + (vqdmulltq_s32): Likewise. + (vqdmulltq_n_s32): Likewise. + (vqdmullbq_s32): Likewise. + (vqdmullbq_n_s32): Likewise. + (vorrq_f32): Likewise. + (vornq_f32): Likewise. + (vmulq_n_f32): Likewise. + (vmulq_f32): Likewise. + (vmovntq_s32): Likewise. + (vmovnbq_s32): Likewise. + (vmlsldavxq_s32): Likewise. + (vmlsldavq_s32): Likewise. + (vmlaldavxq_s32): Likewise. + (vmlaldavq_s32): Likewise. + (vminnmvq_f32): Likewise. + (vminnmq_f32): Likewise. + (vminnmavq_f32): Likewise. + (vminnmaq_f32): Likewise. + (vmaxnmvq_f32): Likewise. + (vmaxnmq_f32): Likewise. + (vmaxnmavq_f32): Likewise. + (vmaxnmaq_f32): Likewise. + (veorq_f32): Likewise. + (vcmulq_rot90_f32): Likewise. + (vcmulq_rot270_f32): Likewise. + (vcmulq_rot180_f32): Likewise. + (vcmulq_f32): Likewise. + (vcaddq_rot90_f32): Likewise. + (vcaddq_rot270_f32): Likewise. + (vbicq_f32): Likewise. + (vandq_f32): Likewise. + (vaddq_n_f32): Likewise. + (vabdq_f32): Likewise. + (vshlltq_n_s16): Likewise. + (vshllbq_n_s16): Likewise. + (vorrq_n_s32): Likewise. + (vbicq_n_s32): Likewise. + (vrmlaldavhq_u32): Likewise. + (vctp8q_m): Likewise. + (vctp64q_m): Likewise. + (vctp32q_m): Likewise. + (vctp16q_m): Likewise. + (vaddlvaq_u32): Likewise. + (vrmlsldavhxq_s32): Likewise. + (vrmlsldavhq_s32): Likewise. + (vrmlaldavhxq_s32): Likewise. + (vrmlaldavhq_s32): Likewise. + (vcvttq_f16_f32): Likewise. + (vcvtbq_f16_f32): Likewise. + (vaddlvaq_s32): Likewise. + (__arm_vqmovntq_u16): Define intrinsic. + (__arm_vqmovnbq_u16): Likewise. + (__arm_vmulltq_poly_p8): Likewise. + (__arm_vmullbq_poly_p8): Likewise. + (__arm_vmovntq_u16): Likewise. + (__arm_vmovnbq_u16): Likewise. + (__arm_vmlaldavxq_u16): Likewise. + (__arm_vmlaldavq_u16): Likewise. + (__arm_vqmovuntq_s16): Likewise. + (__arm_vqmovunbq_s16): Likewise. + (__arm_vshlltq_n_u8): Likewise. + (__arm_vshllbq_n_u8): Likewise. + (__arm_vorrq_n_u16): Likewise. + (__arm_vbicq_n_u16): Likewise. + (__arm_vcmpneq_n_f16): Likewise. + (__arm_vcmpneq_f16): Likewise. + (__arm_vcmpltq_n_f16): Likewise. + (__arm_vcmpltq_f16): Likewise. + (__arm_vcmpleq_n_f16): Likewise. + (__arm_vcmpleq_f16): Likewise. + (__arm_vcmpgtq_n_f16): Likewise. + (__arm_vcmpgtq_f16): Likewise. + (__arm_vcmpgeq_n_f16): Likewise. + (__arm_vcmpgeq_f16): Likewise. + (__arm_vcmpeqq_n_f16): Likewise. + (__arm_vcmpeqq_f16): Likewise. + (__arm_vsubq_f16): Likewise. + (__arm_vqmovntq_s16): Likewise. + (__arm_vqmovnbq_s16): Likewise. + (__arm_vqdmulltq_s16): Likewise. + (__arm_vqdmulltq_n_s16): Likewise. + (__arm_vqdmullbq_s16): Likewise. + (__arm_vqdmullbq_n_s16): Likewise. + (__arm_vorrq_f16): Likewise. + (__arm_vornq_f16): Likewise. + (__arm_vmulq_n_f16): Likewise. + (__arm_vmulq_f16): Likewise. + (__arm_vmovntq_s16): Likewise. + (__arm_vmovnbq_s16): Likewise. + (__arm_vmlsldavxq_s16): Likewise. + (__arm_vmlsldavq_s16): Likewise. + (__arm_vmlaldavxq_s16): Likewise. + (__arm_vmlaldavq_s16): Likewise. + (__arm_vminnmvq_f16): Likewise. + (__arm_vminnmq_f16): Likewise. + (__arm_vminnmavq_f16): Likewise. + (__arm_vminnmaq_f16): Likewise. + (__arm_vmaxnmvq_f16): Likewise. + (__arm_vmaxnmq_f16): Likewise. + (__arm_vmaxnmavq_f16): Likewise. + (__arm_vmaxnmaq_f16): Likewise. + (__arm_veorq_f16): Likewise. + (__arm_vcmulq_rot90_f16): Likewise. + (__arm_vcmulq_rot270_f16): Likewise. + (__arm_vcmulq_rot180_f16): Likewise. + (__arm_vcmulq_f16): Likewise. + (__arm_vcaddq_rot90_f16): Likewise. + (__arm_vcaddq_rot270_f16): Likewise. + (__arm_vbicq_f16): Likewise. + (__arm_vandq_f16): Likewise. + (__arm_vaddq_n_f16): Likewise. + (__arm_vabdq_f16): Likewise. + (__arm_vshlltq_n_s8): Likewise. + (__arm_vshllbq_n_s8): Likewise. + (__arm_vorrq_n_s16): Likewise. + (__arm_vbicq_n_s16): Likewise. + (__arm_vqmovntq_u32): Likewise. + (__arm_vqmovnbq_u32): Likewise. + (__arm_vmulltq_poly_p16): Likewise. + (__arm_vmullbq_poly_p16): Likewise. + (__arm_vmovntq_u32): Likewise. + (__arm_vmovnbq_u32): Likewise. + (__arm_vmlaldavxq_u32): Likewise. + (__arm_vmlaldavq_u32): Likewise. + (__arm_vqmovuntq_s32): Likewise. + (__arm_vqmovunbq_s32): Likewise. + (__arm_vshlltq_n_u16): Likewise. + (__arm_vshllbq_n_u16): Likewise. + (__arm_vorrq_n_u32): Likewise. + (__arm_vbicq_n_u32): Likewise. + (__arm_vcmpneq_n_f32): Likewise. + (__arm_vcmpneq_f32): Likewise. + (__arm_vcmpltq_n_f32): Likewise. + (__arm_vcmpltq_f32): Likewise. + (__arm_vcmpleq_n_f32): Likewise. + (__arm_vcmpleq_f32): Likewise. + (__arm_vcmpgtq_n_f32): Likewise. + (__arm_vcmpgtq_f32): Likewise. + (__arm_vcmpgeq_n_f32): Likewise. + (__arm_vcmpgeq_f32): Likewise. + (__arm_vcmpeqq_n_f32): Likewise. + (__arm_vcmpeqq_f32): Likewise. + (__arm_vsubq_f32): Likewise. + (__arm_vqmovntq_s32): Likewise. + (__arm_vqmovnbq_s32): Likewise. + (__arm_vqdmulltq_s32): Likewise. + (__arm_vqdmulltq_n_s32): Likewise. + (__arm_vqdmullbq_s32): Likewise. + (__arm_vqdmullbq_n_s32): Likewise. + (__arm_vorrq_f32): Likewise. + (__arm_vornq_f32): Likewise. + (__arm_vmulq_n_f32): Likewise. + (__arm_vmulq_f32): Likewise. + (__arm_vmovntq_s32): Likewise. + (__arm_vmovnbq_s32): Likewise. + (__arm_vmlsldavxq_s32): Likewise. + (__arm_vmlsldavq_s32): Likewise. + (__arm_vmlaldavxq_s32): Likewise. + (__arm_vmlaldavq_s32): Likewise. + (__arm_vminnmvq_f32): Likewise. + (__arm_vminnmq_f32): Likewise. + (__arm_vminnmavq_f32): Likewise. + (__arm_vminnmaq_f32): Likewise. + (__arm_vmaxnmvq_f32): Likewise. + (__arm_vmaxnmq_f32): Likewise. + (__arm_vmaxnmavq_f32): Likewise. + (__arm_vmaxnmaq_f32): Likewise. + (__arm_veorq_f32): Likewise. + (__arm_vcmulq_rot90_f32): Likewise. + (__arm_vcmulq_rot270_f32): Likewise. + (__arm_vcmulq_rot180_f32): Likewise. + (__arm_vcmulq_f32): Likewise. + (__arm_vcaddq_rot90_f32): Likewise. + (__arm_vcaddq_rot270_f32): Likewise. + (__arm_vbicq_f32): Likewise. + (__arm_vandq_f32): Likewise. + (__arm_vaddq_n_f32): Likewise. + (__arm_vabdq_f32): Likewise. + (__arm_vshlltq_n_s16): Likewise. + (__arm_vshllbq_n_s16): Likewise. + (__arm_vorrq_n_s32): Likewise. + (__arm_vbicq_n_s32): Likewise. + (__arm_vrmlaldavhq_u32): Likewise. + (__arm_vctp8q_m): Likewise. + (__arm_vctp64q_m): Likewise. + (__arm_vctp32q_m): Likewise. + (__arm_vctp16q_m): Likewise. + (__arm_vaddlvaq_u32): Likewise. + (__arm_vrmlsldavhxq_s32): Likewise. + (__arm_vrmlsldavhq_s32): Likewise. + (__arm_vrmlaldavhxq_s32): Likewise. + (__arm_vrmlaldavhq_s32): Likewise. + (__arm_vcvttq_f16_f32): Likewise. + (__arm_vcvtbq_f16_f32): Likewise. + (__arm_vaddlvaq_s32): Likewise. + (vst4q): Define polymorphic variant. + (vrndxq): Likewise. + (vrndq): Likewise. + (vrndpq): Likewise. + (vrndnq): Likewise. + (vrndmq): Likewise. + (vrndaq): Likewise. + (vrev64q): Likewise. + (vnegq): Likewise. + (vdupq_n): Likewise. + (vabsq): Likewise. + (vrev32q): Likewise. + (vcvtbq_f32): Likewise. + (vcvttq_f32): Likewise. + (vcvtq): Likewise. + (vsubq_n): Likewise. + (vbrsrq_n): Likewise. + (vcvtq_n): Likewise. + (vsubq): Likewise. + (vorrq): Likewise. + (vabdq): Likewise. + (vaddq_n): Likewise. + (vandq): Likewise. + (vbicq): Likewise. + (vornq): Likewise. + (vmulq_n): Likewise. + (vmulq): Likewise. + (vcaddq_rot270): Likewise. + (vcmpeqq_n): Likewise. + (vcmpeqq): Likewise. + (vcaddq_rot90): Likewise. + (vcmpgeq_n): Likewise. + (vcmpgeq): Likewise. + (vcmpgtq_n): Likewise. + (vcmpgtq): Likewise. + (vcmpgtq): Likewise. + (vcmpleq_n): Likewise. + (vcmpleq_n): Likewise. + (vcmpleq): Likewise. + (vcmpleq): Likewise. + (vcmpltq_n): Likewise. + (vcmpltq_n): Likewise. + (vcmpltq): Likewise. + (vcmpltq): Likewise. + (vcmpneq_n): Likewise. + (vcmpneq_n): Likewise. + (vcmpneq): Likewise. + (vcmpneq): Likewise. + (vcmulq): Likewise. + (vcmulq): Likewise. + (vcmulq_rot180): Likewise. + (vcmulq_rot180): Likewise. + (vcmulq_rot270): Likewise. + (vcmulq_rot270): Likewise. + (vcmulq_rot90): Likewise. + (vcmulq_rot90): Likewise. + (veorq): Likewise. + (veorq): Likewise. + (vmaxnmaq): Likewise. + (vmaxnmaq): Likewise. + (vmaxnmavq): Likewise. + (vmaxnmavq): Likewise. + (vmaxnmq): Likewise. + (vmaxnmq): Likewise. + (vmaxnmvq): Likewise. + (vmaxnmvq): Likewise. + (vminnmaq): Likewise. + (vminnmaq): Likewise. + (vminnmavq): Likewise. + (vminnmavq): Likewise. + (vminnmq): Likewise. + (vminnmq): Likewise. + (vminnmvq): Likewise. + (vminnmvq): Likewise. + (vbicq_n): Likewise. + (vqmovntq): Likewise. + (vqmovntq): Likewise. + (vqmovnbq): Likewise. + (vqmovnbq): Likewise. + (vmulltq_poly): Likewise. + (vmulltq_poly): Likewise. + (vmullbq_poly): Likewise. + (vmullbq_poly): Likewise. + (vmovntq): Likewise. + (vmovntq): Likewise. + (vmovnbq): Likewise. + (vmovnbq): Likewise. + (vmlaldavxq): Likewise. + (vmlaldavxq): Likewise. + (vqmovuntq): Likewise. + (vqmovuntq): Likewise. + (vshlltq_n): Likewise. + (vshlltq_n): Likewise. + (vshllbq_n): Likewise. + (vshllbq_n): Likewise. + (vorrq_n): Likewise. + (vorrq_n): Likewise. + (vmlaldavq): Likewise. + (vmlaldavq): Likewise. + (vqmovunbq): Likewise. + (vqmovunbq): Likewise. + (vqdmulltq_n): Likewise. + (vqdmulltq_n): Likewise. + (vqdmulltq): Likewise. + (vqdmulltq): Likewise. + (vqdmullbq_n): Likewise. + (vqdmullbq_n): Likewise. + (vqdmullbq): Likewise. + (vqdmullbq): Likewise. + (vaddlvaq): Likewise. + (vaddlvaq): Likewise. + (vrmlaldavhq): Likewise. + (vrmlaldavhq): Likewise. + (vrmlaldavhxq): Likewise. + (vrmlaldavhxq): Likewise. + (vrmlsldavhq): Likewise. + (vrmlsldavhq): Likewise. + (vrmlsldavhxq): Likewise. + (vrmlsldavhxq): Likewise. + (vmlsldavxq): Likewise. + (vmlsldavxq): Likewise. + (vmlsldavq): Likewise. + (vmlsldavq): Likewise. + * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. + (BINOP_NONE_NONE_NONE): Likewise. + (BINOP_UNONE_NONE_NONE): Likewise. + (BINOP_UNONE_UNONE_IMM): Likewise. + (BINOP_UNONE_UNONE_NONE): Likewise. + (BINOP_UNONE_UNONE_UNONE): Likewise. + * config/arm/mve.md (mve_vabdq_f): Define RTL pattern. + (mve_vaddlvaq_v4si): Likewise. + (mve_vaddq_n_f): Likewise. + (mve_vandq_f): Likewise. + (mve_vbicq_f): Likewise. + (mve_vbicq_n_): Likewise. + (mve_vcaddq_rot270_f): Likewise. + (mve_vcaddq_rot90_f): Likewise. + (mve_vcmpeqq_f): Likewise. + (mve_vcmpeqq_n_f): Likewise. + (mve_vcmpgeq_f): Likewise. + (mve_vcmpgeq_n_f): Likewise. + (mve_vcmpgtq_f): Likewise. + (mve_vcmpgtq_n_f): Likewise. + (mve_vcmpleq_f): Likewise. + (mve_vcmpleq_n_f): Likewise. + (mve_vcmpltq_f): Likewise. + (mve_vcmpltq_n_f): Likewise. + (mve_vcmpneq_f): Likewise. + (mve_vcmpneq_n_f): Likewise. + (mve_vcmulq_f): Likewise. + (mve_vcmulq_rot180_f): Likewise. + (mve_vcmulq_rot270_f): Likewise. + (mve_vcmulq_rot90_f): Likewise. + (mve_vctpq_mhi): Likewise. + (mve_vcvtbq_f16_f32v8hf): Likewise. + (mve_vcvttq_f16_f32v8hf): Likewise. + (mve_veorq_f): Likewise. + (mve_vmaxnmaq_f): Likewise. + (mve_vmaxnmavq_f): Likewise. + (mve_vmaxnmq_f): Likewise. + (mve_vmaxnmvq_f): Likewise. + (mve_vminnmaq_f): Likewise. + (mve_vminnmavq_f): Likewise. + (mve_vminnmq_f): Likewise. + (mve_vminnmvq_f): Likewise. + (mve_vmlaldavq_): Likewise. + (mve_vmlaldavxq_): Likewise. + (mve_vmlsldavq_s): Likewise. + (mve_vmlsldavxq_s): Likewise. + (mve_vmovnbq_): Likewise. + (mve_vmovntq_): Likewise. + (mve_vmulq_f): Likewise. + (mve_vmulq_n_f): Likewise. + (mve_vornq_f): Likewise. + (mve_vorrq_f): Likewise. + (mve_vorrq_n_): Likewise. + (mve_vqdmullbq_n_s): Likewise. + (mve_vqdmullbq_s): Likewise. + (mve_vqdmulltq_n_s): Likewise. + (mve_vqdmulltq_s): Likewise. + (mve_vqmovnbq_): Likewise. + (mve_vqmovntq_): Likewise. + (mve_vqmovunbq_s): Likewise. + (mve_vqmovuntq_s): Likewise. + (mve_vrmlaldavhxq_sv4si): Likewise. + (mve_vrmlsldavhq_sv4si): Likewise. + (mve_vrmlsldavhxq_sv4si): Likewise. + (mve_vshllbq_n_): Likewise. + (mve_vshlltq_n_): Likewise. + (mve_vsubq_f): Likewise. + (mve_vmulltq_poly_p): Likewise. + (mve_vmullbq_poly_p): Likewise. + (mve_vrmlaldavhq_v4si): Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vsubq_u8): Define macro. (vsubq_n_u8): Likewise. (vrmulhq_u8): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index eb81a02..db5e472 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -599,6 +599,149 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vshlq_n_s32(__a, __imm) __arm_vshlq_n_s32(__a, __imm) #define vrshrq_n_s32(__a, __imm) __arm_vrshrq_n_s32(__a, __imm) #define vqshlq_n_s32(__a, __imm) __arm_vqshlq_n_s32(__a, __imm) +#define vqmovntq_u16(__a, __b) __arm_vqmovntq_u16(__a, __b) +#define vqmovnbq_u16(__a, __b) __arm_vqmovnbq_u16(__a, __b) +#define vmulltq_poly_p8(__a, __b) __arm_vmulltq_poly_p8(__a, __b) +#define vmullbq_poly_p8(__a, __b) __arm_vmullbq_poly_p8(__a, __b) +#define vmovntq_u16(__a, __b) __arm_vmovntq_u16(__a, __b) +#define vmovnbq_u16(__a, __b) __arm_vmovnbq_u16(__a, __b) +#define vmlaldavq_u16(__a, __b) __arm_vmlaldavq_u16(__a, __b) +#define vqmovuntq_s16(__a, __b) __arm_vqmovuntq_s16(__a, __b) +#define vqmovunbq_s16(__a, __b) __arm_vqmovunbq_s16(__a, __b) +#define vshlltq_n_u8(__a, __imm) __arm_vshlltq_n_u8(__a, __imm) +#define vshllbq_n_u8(__a, __imm) __arm_vshllbq_n_u8(__a, __imm) +#define vorrq_n_u16(__a, __imm) __arm_vorrq_n_u16(__a, __imm) +#define vbicq_n_u16(__a, __imm) __arm_vbicq_n_u16(__a, __imm) +#define vcmpneq_n_f16(__a, __b) __arm_vcmpneq_n_f16(__a, __b) +#define vcmpneq_f16(__a, __b) __arm_vcmpneq_f16(__a, __b) +#define vcmpltq_n_f16(__a, __b) __arm_vcmpltq_n_f16(__a, __b) +#define vcmpltq_f16(__a, __b) __arm_vcmpltq_f16(__a, __b) +#define vcmpleq_n_f16(__a, __b) __arm_vcmpleq_n_f16(__a, __b) +#define vcmpleq_f16(__a, __b) __arm_vcmpleq_f16(__a, __b) +#define vcmpgtq_n_f16(__a, __b) __arm_vcmpgtq_n_f16(__a, __b) +#define vcmpgtq_f16(__a, __b) __arm_vcmpgtq_f16(__a, __b) +#define vcmpgeq_n_f16(__a, __b) __arm_vcmpgeq_n_f16(__a, __b) +#define vcmpgeq_f16(__a, __b) __arm_vcmpgeq_f16(__a, __b) +#define vcmpeqq_n_f16(__a, __b) __arm_vcmpeqq_n_f16(__a, __b) +#define vcmpeqq_f16(__a, __b) __arm_vcmpeqq_f16(__a, __b) +#define vsubq_f16(__a, __b) __arm_vsubq_f16(__a, __b) +#define vqmovntq_s16(__a, __b) __arm_vqmovntq_s16(__a, __b) +#define vqmovnbq_s16(__a, __b) __arm_vqmovnbq_s16(__a, __b) +#define vqdmulltq_s16(__a, __b) __arm_vqdmulltq_s16(__a, __b) +#define vqdmulltq_n_s16(__a, __b) __arm_vqdmulltq_n_s16(__a, __b) +#define vqdmullbq_s16(__a, __b) __arm_vqdmullbq_s16(__a, __b) +#define vqdmullbq_n_s16(__a, __b) __arm_vqdmullbq_n_s16(__a, __b) +#define vorrq_f16(__a, __b) __arm_vorrq_f16(__a, __b) +#define vornq_f16(__a, __b) __arm_vornq_f16(__a, __b) +#define vmulq_n_f16(__a, __b) __arm_vmulq_n_f16(__a, __b) +#define vmulq_f16(__a, __b) __arm_vmulq_f16(__a, __b) +#define vmovntq_s16(__a, __b) __arm_vmovntq_s16(__a, __b) +#define vmovnbq_s16(__a, __b) __arm_vmovnbq_s16(__a, __b) +#define vmlsldavxq_s16(__a, __b) __arm_vmlsldavxq_s16(__a, __b) +#define vmlsldavq_s16(__a, __b) __arm_vmlsldavq_s16(__a, __b) +#define vmlaldavxq_s16(__a, __b) __arm_vmlaldavxq_s16(__a, __b) +#define vmlaldavq_s16(__a, __b) __arm_vmlaldavq_s16(__a, __b) +#define vminnmvq_f16(__a, __b) __arm_vminnmvq_f16(__a, __b) +#define vminnmq_f16(__a, __b) __arm_vminnmq_f16(__a, __b) +#define vminnmavq_f16(__a, __b) __arm_vminnmavq_f16(__a, __b) +#define vminnmaq_f16(__a, __b) __arm_vminnmaq_f16(__a, __b) +#define vmaxnmvq_f16(__a, __b) __arm_vmaxnmvq_f16(__a, __b) +#define vmaxnmq_f16(__a, __b) __arm_vmaxnmq_f16(__a, __b) +#define vmaxnmavq_f16(__a, __b) __arm_vmaxnmavq_f16(__a, __b) +#define vmaxnmaq_f16(__a, __b) __arm_vmaxnmaq_f16(__a, __b) +#define veorq_f16(__a, __b) __arm_veorq_f16(__a, __b) +#define vcmulq_rot90_f16(__a, __b) __arm_vcmulq_rot90_f16(__a, __b) +#define vcmulq_rot270_f16(__a, __b) __arm_vcmulq_rot270_f16(__a, __b) +#define vcmulq_rot180_f16(__a, __b) __arm_vcmulq_rot180_f16(__a, __b) +#define vcmulq_f16(__a, __b) __arm_vcmulq_f16(__a, __b) +#define vcaddq_rot90_f16(__a, __b) __arm_vcaddq_rot90_f16(__a, __b) +#define vcaddq_rot270_f16(__a, __b) __arm_vcaddq_rot270_f16(__a, __b) +#define vbicq_f16(__a, __b) __arm_vbicq_f16(__a, __b) +#define vandq_f16(__a, __b) __arm_vandq_f16(__a, __b) +#define vaddq_n_f16(__a, __b) __arm_vaddq_n_f16(__a, __b) +#define vabdq_f16(__a, __b) __arm_vabdq_f16(__a, __b) +#define vshlltq_n_s8(__a, __imm) __arm_vshlltq_n_s8(__a, __imm) +#define vshllbq_n_s8(__a, __imm) __arm_vshllbq_n_s8(__a, __imm) +#define vorrq_n_s16(__a, __imm) __arm_vorrq_n_s16(__a, __imm) +#define vbicq_n_s16(__a, __imm) __arm_vbicq_n_s16(__a, __imm) +#define vqmovntq_u32(__a, __b) __arm_vqmovntq_u32(__a, __b) +#define vqmovnbq_u32(__a, __b) __arm_vqmovnbq_u32(__a, __b) +#define vmulltq_poly_p16(__a, __b) __arm_vmulltq_poly_p16(__a, __b) +#define vmullbq_poly_p16(__a, __b) __arm_vmullbq_poly_p16(__a, __b) +#define vmovntq_u32(__a, __b) __arm_vmovntq_u32(__a, __b) +#define vmovnbq_u32(__a, __b) __arm_vmovnbq_u32(__a, __b) +#define vmlaldavq_u32(__a, __b) __arm_vmlaldavq_u32(__a, __b) +#define vqmovuntq_s32(__a, __b) __arm_vqmovuntq_s32(__a, __b) +#define vqmovunbq_s32(__a, __b) __arm_vqmovunbq_s32(__a, __b) +#define vshlltq_n_u16(__a, __imm) __arm_vshlltq_n_u16(__a, __imm) +#define vshllbq_n_u16(__a, __imm) __arm_vshllbq_n_u16(__a, __imm) +#define vorrq_n_u32(__a, __imm) __arm_vorrq_n_u32(__a, __imm) +#define vbicq_n_u32(__a, __imm) __arm_vbicq_n_u32(__a, __imm) +#define vcmpneq_n_f32(__a, __b) __arm_vcmpneq_n_f32(__a, __b) +#define vcmpneq_f32(__a, __b) __arm_vcmpneq_f32(__a, __b) +#define vcmpltq_n_f32(__a, __b) __arm_vcmpltq_n_f32(__a, __b) +#define vcmpltq_f32(__a, __b) __arm_vcmpltq_f32(__a, __b) +#define vcmpleq_n_f32(__a, __b) __arm_vcmpleq_n_f32(__a, __b) +#define vcmpleq_f32(__a, __b) __arm_vcmpleq_f32(__a, __b) +#define vcmpgtq_n_f32(__a, __b) __arm_vcmpgtq_n_f32(__a, __b) +#define vcmpgtq_f32(__a, __b) __arm_vcmpgtq_f32(__a, __b) +#define vcmpgeq_n_f32(__a, __b) __arm_vcmpgeq_n_f32(__a, __b) +#define vcmpgeq_f32(__a, __b) __arm_vcmpgeq_f32(__a, __b) +#define vcmpeqq_n_f32(__a, __b) __arm_vcmpeqq_n_f32(__a, __b) +#define vcmpeqq_f32(__a, __b) __arm_vcmpeqq_f32(__a, __b) +#define vsubq_f32(__a, __b) __arm_vsubq_f32(__a, __b) +#define vqmovntq_s32(__a, __b) __arm_vqmovntq_s32(__a, __b) +#define vqmovnbq_s32(__a, __b) __arm_vqmovnbq_s32(__a, __b) +#define vqdmulltq_s32(__a, __b) __arm_vqdmulltq_s32(__a, __b) +#define vqdmulltq_n_s32(__a, __b) __arm_vqdmulltq_n_s32(__a, __b) +#define vqdmullbq_s32(__a, __b) __arm_vqdmullbq_s32(__a, __b) +#define vqdmullbq_n_s32(__a, __b) __arm_vqdmullbq_n_s32(__a, __b) +#define vorrq_f32(__a, __b) __arm_vorrq_f32(__a, __b) +#define vornq_f32(__a, __b) __arm_vornq_f32(__a, __b) +#define vmulq_n_f32(__a, __b) __arm_vmulq_n_f32(__a, __b) +#define vmulq_f32(__a, __b) __arm_vmulq_f32(__a, __b) +#define vmovntq_s32(__a, __b) __arm_vmovntq_s32(__a, __b) +#define vmovnbq_s32(__a, __b) __arm_vmovnbq_s32(__a, __b) +#define vmlsldavxq_s32(__a, __b) __arm_vmlsldavxq_s32(__a, __b) +#define vmlsldavq_s32(__a, __b) __arm_vmlsldavq_s32(__a, __b) +#define vmlaldavxq_s32(__a, __b) __arm_vmlaldavxq_s32(__a, __b) +#define vmlaldavq_s32(__a, __b) __arm_vmlaldavq_s32(__a, __b) +#define vminnmvq_f32(__a, __b) __arm_vminnmvq_f32(__a, __b) +#define vminnmq_f32(__a, __b) __arm_vminnmq_f32(__a, __b) +#define vminnmavq_f32(__a, __b) __arm_vminnmavq_f32(__a, __b) +#define vminnmaq_f32(__a, __b) __arm_vminnmaq_f32(__a, __b) +#define vmaxnmvq_f32(__a, __b) __arm_vmaxnmvq_f32(__a, __b) +#define vmaxnmq_f32(__a, __b) __arm_vmaxnmq_f32(__a, __b) +#define vmaxnmavq_f32(__a, __b) __arm_vmaxnmavq_f32(__a, __b) +#define vmaxnmaq_f32(__a, __b) __arm_vmaxnmaq_f32(__a, __b) +#define veorq_f32(__a, __b) __arm_veorq_f32(__a, __b) +#define vcmulq_rot90_f32(__a, __b) __arm_vcmulq_rot90_f32(__a, __b) +#define vcmulq_rot270_f32(__a, __b) __arm_vcmulq_rot270_f32(__a, __b) +#define vcmulq_rot180_f32(__a, __b) __arm_vcmulq_rot180_f32(__a, __b) +#define vcmulq_f32(__a, __b) __arm_vcmulq_f32(__a, __b) +#define vcaddq_rot90_f32(__a, __b) __arm_vcaddq_rot90_f32(__a, __b) +#define vcaddq_rot270_f32(__a, __b) __arm_vcaddq_rot270_f32(__a, __b) +#define vbicq_f32(__a, __b) __arm_vbicq_f32(__a, __b) +#define vandq_f32(__a, __b) __arm_vandq_f32(__a, __b) +#define vaddq_n_f32(__a, __b) __arm_vaddq_n_f32(__a, __b) +#define vabdq_f32(__a, __b) __arm_vabdq_f32(__a, __b) +#define vshlltq_n_s16(__a, __imm) __arm_vshlltq_n_s16(__a, __imm) +#define vshllbq_n_s16(__a, __imm) __arm_vshllbq_n_s16(__a, __imm) +#define vorrq_n_s32(__a, __imm) __arm_vorrq_n_s32(__a, __imm) +#define vbicq_n_s32(__a, __imm) __arm_vbicq_n_s32(__a, __imm) +#define vrmlaldavhq_u32(__a, __b) __arm_vrmlaldavhq_u32(__a, __b) +#define vctp8q_m(__a, __p) __arm_vctp8q_m(__a, __p) +#define vctp64q_m(__a, __p) __arm_vctp64q_m(__a, __p) +#define vctp32q_m(__a, __p) __arm_vctp32q_m(__a, __p) +#define vctp16q_m(__a, __p) __arm_vctp16q_m(__a, __p) +#define vaddlvaq_u32(__a, __b) __arm_vaddlvaq_u32(__a, __b) +#define vrmlsldavhxq_s32(__a, __b) __arm_vrmlsldavhxq_s32(__a, __b) +#define vrmlsldavhq_s32(__a, __b) __arm_vrmlsldavhq_s32(__a, __b) +#define vrmlaldavhxq_s32(__a, __b) __arm_vrmlaldavhxq_s32(__a, __b) +#define vrmlaldavhq_s32(__a, __b) __arm_vrmlaldavhq_s32(__a, __b) +#define vcvttq_f16_f32(__a, __b) __arm_vcvttq_f16_f32(__a, __b) +#define vcvtbq_f16_f32(__a, __b) __arm_vcvtbq_f16_f32(__a, __b) +#define vaddlvaq_s32(__a, __b) __arm_vaddlvaq_s32(__a, __b) #endif __extension__ extern __inline void @@ -3859,451 +4002,1452 @@ __arm_vqshlq_n_s32 (int32x4_t __a, const int __imm) return __builtin_mve_vqshlq_n_sv4si (__a, __imm); } -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ - -__extension__ extern __inline void +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +__arm_vqmovntq_u16 (uint8x16_t __a, uint16x8_t __b) { - union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv8hf (__addr, __rv.__o); + return __builtin_mve_vqmovntq_uv8hi (__a, __b); } -__extension__ extern __inline void +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +__arm_vqmovnbq_u16 (uint8x16_t __a, uint16x8_t __b) { - union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv4sf (__addr, __rv.__o); + return __builtin_mve_vqmovnbq_uv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f16 (float16x8_t __a) +__arm_vmulltq_poly_p8 (uint8x16_t __a, uint8x16_t __b) { - return __builtin_mve_vrndxq_fv8hf (__a); + return __builtin_mve_vmulltq_poly_pv16qi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f32 (float32x4_t __a) +__arm_vmullbq_poly_p8 (uint8x16_t __a, uint8x16_t __b) { - return __builtin_mve_vrndxq_fv4sf (__a); + return __builtin_mve_vmullbq_poly_pv16qi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f16 (float16x8_t __a) +__arm_vmovntq_u16 (uint8x16_t __a, uint16x8_t __b) { - return __builtin_mve_vrndq_fv8hf (__a); + return __builtin_mve_vmovntq_uv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f32 (float32x4_t __a) +__arm_vmovnbq_u16 (uint8x16_t __a, uint16x8_t __b) { - return __builtin_mve_vrndq_fv4sf (__a); + return __builtin_mve_vmovnbq_uv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f16 (float16x8_t __a) +__arm_vmlaldavq_u16 (uint16x8_t __a, uint16x8_t __b) { - return __builtin_mve_vrndpq_fv8hf (__a); + return __builtin_mve_vmlaldavq_uv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f32 (float32x4_t __a) +__arm_vqmovuntq_s16 (uint8x16_t __a, int16x8_t __b) { - return __builtin_mve_vrndpq_fv4sf (__a); + return __builtin_mve_vqmovuntq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f16 (float16x8_t __a) +__arm_vqmovunbq_s16 (uint8x16_t __a, int16x8_t __b) { - return __builtin_mve_vrndnq_fv8hf (__a); + return __builtin_mve_vqmovunbq_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f32 (float32x4_t __a) +__arm_vshlltq_n_u8 (uint8x16_t __a, const int __imm) { - return __builtin_mve_vrndnq_fv4sf (__a); + return __builtin_mve_vshlltq_n_uv16qi (__a, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f16 (float16x8_t __a) +__arm_vshllbq_n_u8 (uint8x16_t __a, const int __imm) { - return __builtin_mve_vrndmq_fv8hf (__a); + return __builtin_mve_vshllbq_n_uv16qi (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f32 (float32x4_t __a) +__arm_vorrq_n_u16 (uint16x8_t __a, const int __imm) { - return __builtin_mve_vrndmq_fv4sf (__a); + return __builtin_mve_vorrq_n_uv8hi (__a, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f16 (float16x8_t __a) +__arm_vbicq_n_u16 (uint16x8_t __a, const int __imm) { - return __builtin_mve_vrndaq_fv8hf (__a); + return __builtin_mve_vbicq_n_uv8hi (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f32 (float32x4_t __a) +__arm_vqmovntq_s16 (int8x16_t __a, int16x8_t __b) { - return __builtin_mve_vrndaq_fv4sf (__a); + return __builtin_mve_vqmovntq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f16 (float16x8_t __a) +__arm_vqmovnbq_s16 (int8x16_t __a, int16x8_t __b) { - return __builtin_mve_vrev64q_fv8hf (__a); + return __builtin_mve_vqmovnbq_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f32 (float32x4_t __a) +__arm_vqdmulltq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vrev64q_fv4sf (__a); + return __builtin_mve_vqdmulltq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f16 (float16x8_t __a) +__arm_vqdmulltq_n_s16 (int16x8_t __a, int16_t __b) { - return __builtin_mve_vnegq_fv8hf (__a); + return __builtin_mve_vqdmulltq_n_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f32 (float32x4_t __a) +__arm_vqdmullbq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vnegq_fv4sf (__a); + return __builtin_mve_vqdmullbq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f16 (float16_t __a) +__arm_vqdmullbq_n_s16 (int16x8_t __a, int16_t __b) { - return __builtin_mve_vdupq_n_fv8hf (__a); + return __builtin_mve_vqdmullbq_n_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f32 (float32_t __a) +__arm_vmovntq_s16 (int8x16_t __a, int16x8_t __b) { - return __builtin_mve_vdupq_n_fv4sf (__a); + return __builtin_mve_vmovntq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f16 (float16x8_t __a) +__arm_vmovnbq_s16 (int8x16_t __a, int16x8_t __b) { - return __builtin_mve_vabsq_fv8hf (__a); + return __builtin_mve_vmovnbq_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f32 (float32x4_t __a) +__arm_vmlsldavxq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vabsq_fv4sf (__a); + return __builtin_mve_vmlsldavxq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_f16 (float16x8_t __a) +__arm_vmlsldavq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vrev32q_fv8hf (__a); + return __builtin_mve_vmlsldavq_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_f32_f16 (float16x8_t __a) +__arm_vmlaldavxq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vcvttq_f32_f16v4sf (__a); + return __builtin_mve_vmlaldavxq_sv8hi (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_f32_f16 (float16x8_t __a) +__arm_vmlaldavq_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vcvtbq_f32_f16v4sf (__a); + return __builtin_mve_vmlaldavq_sv8hi (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_s16 (int16x8_t __a) +__arm_vshlltq_n_s8 (int8x16_t __a, const int __imm) { - return __builtin_mve_vcvtq_to_f_sv8hf (__a); + return __builtin_mve_vshlltq_n_sv16qi (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_s32 (int32x4_t __a) +__arm_vshllbq_n_s8 (int8x16_t __a, const int __imm) { - return __builtin_mve_vcvtq_to_f_sv4sf (__a); + return __builtin_mve_vshllbq_n_sv16qi (__a, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_u16 (uint16x8_t __a) +__arm_vorrq_n_s16 (int16x8_t __a, const int __imm) { - return __builtin_mve_vcvtq_to_f_uv8hf (__a); + return __builtin_mve_vorrq_n_sv8hi (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_u32 (uint32x4_t __a) +__arm_vbicq_n_s16 (int16x8_t __a, const int __imm) { - return __builtin_mve_vcvtq_to_f_uv4sf (__a); + return __builtin_mve_vbicq_n_sv8hi (__a, __imm); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s16_f16 (float16x8_t __a) +__arm_vqmovntq_u32 (uint16x8_t __a, uint32x4_t __b) { - return __builtin_mve_vcvtq_from_f_sv8hi (__a); + return __builtin_mve_vqmovntq_uv4si (__a, __b); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s32_f32 (float32x4_t __a) +__arm_vqmovnbq_u32 (uint16x8_t __a, uint32x4_t __b) { - return __builtin_mve_vcvtq_from_f_sv4si (__a); + return __builtin_mve_vqmovnbq_uv4si (__a, __b); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u16_f16 (float16x8_t __a) +__arm_vmulltq_poly_p16 (uint16x8_t __a, uint16x8_t __b) { - return __builtin_mve_vcvtq_from_f_uv8hi (__a); + return __builtin_mve_vmulltq_poly_pv8hi (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u32_f32 (float32x4_t __a) +__arm_vmullbq_poly_p16 (uint16x8_t __a, uint16x8_t __b) { - return __builtin_mve_vcvtq_from_f_uv4si (__a); + return __builtin_mve_vmullbq_poly_pv8hi (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u16_f16 (float16x8_t __a) +__arm_vmovntq_u32 (uint16x8_t __a, uint32x4_t __b) { - return __builtin_mve_vcvtpq_uv8hi (__a); + return __builtin_mve_vmovntq_uv4si (__a, __b); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u32_f32 (float32x4_t __a) +__arm_vmovnbq_u32 (uint16x8_t __a, uint32x4_t __b) { - return __builtin_mve_vcvtpq_uv4si (__a); + return __builtin_mve_vmovnbq_uv4si (__a, __b); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __builtin_mve_vmlaldavq_uv4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_u16_f16 (float16x8_t __a) +__arm_vqmovuntq_s32 (uint16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtnq_uv8hi (__a); + return __builtin_mve_vqmovuntq_sv4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u16_f16 (float16x8_t __a) +__arm_vqmovunbq_s32 (uint16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtmq_uv8hi (__a); + return __builtin_mve_vqmovunbq_sv4si (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u32_f32 (float32x4_t __a) +__arm_vshlltq_n_u16 (uint16x8_t __a, const int __imm) { - return __builtin_mve_vcvtmq_uv4si (__a); + return __builtin_mve_vshlltq_n_uv8hi (__a, __imm); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u16_f16 (float16x8_t __a) +__arm_vshllbq_n_u16 (uint16x8_t __a, const int __imm) { - return __builtin_mve_vcvtaq_uv8hi (__a); + return __builtin_mve_vshllbq_n_uv8hi (__a, __imm); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u32_f32 (float32x4_t __a) +__arm_vorrq_n_u32 (uint32x4_t __a, const int __imm) { - return __builtin_mve_vcvtaq_uv4si (__a); + return __builtin_mve_vorrq_n_uv4si (__a, __imm); } - __extension__ extern __inline int16x8_t - __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s16_f16 (float16x8_t __a) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_n_u32 (uint32x4_t __a, const int __imm) { - return __builtin_mve_vcvtaq_sv8hi (__a); + return __builtin_mve_vbicq_n_uv4si (__a, __imm); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s32_f32 (float32x4_t __a) +__arm_vqmovntq_s32 (int16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtaq_sv4si (__a); + return __builtin_mve_vqmovntq_sv4si (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s16_f16 (float16x8_t __a) +__arm_vqmovnbq_s32 (int16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtnq_sv8hi (__a); + return __builtin_mve_vqmovnbq_sv4si (__a, __b); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s32_f32 (float32x4_t __a) +__arm_vqdmulltq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vcvtnq_sv4si (__a); + return __builtin_mve_vqdmulltq_sv4si (__a, __b); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s16_f16 (float16x8_t __a) +__arm_vqdmulltq_n_s32 (int32x4_t __a, int32_t __b) { - return __builtin_mve_vcvtpq_sv8hi (__a); + return __builtin_mve_vqdmulltq_n_sv4si (__a, __b); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s32_f32 (float32x4_t __a) +__arm_vqdmullbq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vcvtpq_sv4si (__a); + return __builtin_mve_vqdmullbq_sv4si (__a, __b); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmullbq_n_s32 (int32x4_t __a, int32_t __b) +{ + return __builtin_mve_vqdmullbq_n_sv4si (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s16_f16 (float16x8_t __a) +__arm_vmovntq_s32 (int16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtmq_sv8hi (__a); + return __builtin_mve_vmovntq_sv4si (__a, __b); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s32_f32 (float32x4_t __a) +__arm_vmovnbq_s32 (int16x8_t __a, int32x4_t __b) { - return __builtin_mve_vcvtmq_sv4si (__a); + return __builtin_mve_vmovnbq_sv4si (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmlsldavxq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vsubq_n_fv8hf (__a, __b); + return __builtin_mve_vmlsldavxq_sv4si (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmlsldavq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vsubq_n_fv4sf (__a, __b); + return __builtin_mve_vmlsldavq_sv4si (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +__arm_vmlaldavxq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); + return __builtin_mve_vmlaldavxq_sv4si (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +__arm_vmlaldavq_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); + return __builtin_mve_vmlaldavq_sv4si (__a, __b); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +__arm_vshlltq_n_s16 (int16x8_t __a, const int __imm) { - return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); + return __builtin_mve_vshlltq_n_sv8hi (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +__arm_vshllbq_n_s16 (int16x8_t __a, const int __imm) { - return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); + return __builtin_mve_vshllbq_n_sv8hi (__a, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +__arm_vorrq_n_s32 (int32x4_t __a, const int __imm) { - return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); + return __builtin_mve_vorrq_n_sv4si (__a, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +__arm_vbicq_n_s32 (int32x4_t __a, const int __imm) { - return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); + return __builtin_mve_vbicq_n_sv4si (__a, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +__arm_vrmlaldavhq_u32 (uint32x4_t __a, uint32x4_t __b) { - return __builtin_mve_vcreateq_fv8hf (__a, __b); + return __builtin_mve_vrmlaldavhq_uv4si (__a, __b); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +__arm_vctp8q_m (uint32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcreateq_fv4sf (__a, __b); + return __builtin_mve_vctp8q_mhi (__a, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +__arm_vctp64q_m (uint32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); + return __builtin_mve_vctp64q_mhi (__a, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +__arm_vctp32q_m (uint32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); + return __builtin_mve_vctp32q_mhi (__a, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +__arm_vctp16q_m (uint32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); + return __builtin_mve_vctp16q_mhi (__a, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +__arm_vaddlvaq_u32 (uint64_t __a, uint32x4_t __b) { - return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); + return __builtin_mve_vaddlvaq_uv4si (__a, __b); } -#endif +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlsldavhxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrmlsldavhxq_sv4si (__a, __b); +} -enum { - __ARM_mve_type_float16_t = 1, - __ARM_mve_type_float16_t_ptr, +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlsldavhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrmlsldavhq_sv4si (__a, __b); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhxq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrmlaldavhxq_sv4si (__a, __b); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vrmlaldavhq_sv4si (__a, __b); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvaq_s32 (int64_t __a, int32x4_t __b) +{ + return __builtin_mve_vaddlvaq_sv4si (__a, __b); +} + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4sf (__addr, __rv.__o); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndxq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndpq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndpq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndnq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndnq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndmq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndmq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndaq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndaq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev64q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f32 (float32x4_t __a) +{ + return __builtin_mve_vrev64q_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f16 (float16x8_t __a) +{ + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_uv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtnq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_sv4si (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vsubq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vsubq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv4sf (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpneq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpneq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpltq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpltq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpleq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpleq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgtq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgeq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpeqq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vsubq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vorrq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vornq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vmulq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_veorq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vbicq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vandq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vaddq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vabdq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpneq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpneq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpltq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpltq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpleq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpleq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgtq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgeq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpeqq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vsubq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vorrq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vornq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vmulq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_veorq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vbicq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vandq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vaddq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vabdq_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); +} + +#endif + +enum { + __ARM_mve_type_float16_t = 1, + __ARM_mve_type_float16_t_ptr, __ARM_mve_type_float16_t_const_ptr, __ARM_mve_type_float16x8_t, __ARM_mve_type_float16x8x2_t, @@ -4361,373 +5505,1161 @@ enum { __ARM_mve_unsupported_type }; -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -#define __ARM_mve_typeid(x) _Generic(x, \ - float16_t: __ARM_mve_type_float16_t, \ - float16_t *: __ARM_mve_type_float16_t_ptr, \ - float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ - float16x8_t: __ARM_mve_type_float16x8_t, \ - float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ - float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ - float32_t: __ARM_mve_type_float32_t, \ - float32_t *: __ARM_mve_type_float32_t_ptr, \ - float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ - float32x4_t: __ARM_mve_type_float32x4_t, \ - float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ - float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ - int16_t: __ARM_mve_type_int16_t, \ - int16_t *: __ARM_mve_type_int16_t_ptr, \ - int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ - int16x8_t: __ARM_mve_type_int16x8_t, \ - int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ - int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ - int32_t: __ARM_mve_type_int32_t, \ - int32_t *: __ARM_mve_type_int32_t_ptr, \ - int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ - int32x4_t: __ARM_mve_type_int32x4_t, \ - int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ - int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ - int64_t: __ARM_mve_type_int64_t, \ - int64_t *: __ARM_mve_type_int64_t_ptr, \ - int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ - int64x2_t: __ARM_mve_type_int64x2_t, \ - int8_t: __ARM_mve_type_int8_t, \ - int8_t *: __ARM_mve_type_int8_t_ptr, \ - int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ - int8x16_t: __ARM_mve_type_int8x16_t, \ - int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ - int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ - uint16_t: __ARM_mve_type_uint16_t, \ - uint16_t *: __ARM_mve_type_uint16_t_ptr, \ - uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ - uint16x8_t: __ARM_mve_type_uint16x8_t, \ - uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ - uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ - uint32_t: __ARM_mve_type_uint32_t, \ - uint32_t *: __ARM_mve_type_uint32_t_ptr, \ - uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ - uint32x4_t: __ARM_mve_type_uint32x4_t, \ - uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ - uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ - uint64_t: __ARM_mve_type_uint64_t, \ - uint64_t *: __ARM_mve_type_uint64_t_ptr, \ - uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ - uint64x2_t: __ARM_mve_type_uint64x2_t, \ - uint8_t: __ARM_mve_type_uint8_t, \ - uint8_t *: __ARM_mve_type_uint8_t_ptr, \ - uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ - uint8x16_t: __ARM_mve_type_uint8x16_t, \ - uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ - uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ - default: _Generic(x, \ - signed char: __ARM_mve_type_int8_t, \ - short: __ARM_mve_type_int16_t, \ - int: __ARM_mve_type_int32_t, \ - long: __ARM_mve_type_int32_t, \ - long long: __ARM_mve_type_int64_t, \ - unsigned char: __ARM_mve_type_uint8_t, \ - unsigned short: __ARM_mve_type_uint16_t, \ - unsigned int: __ARM_mve_type_uint32_t, \ - unsigned long: __ARM_mve_type_uint32_t, \ - unsigned long long: __ARM_mve_type_uint64_t, \ - default: __ARM_mve_unsupported_type)) -#else -#define __ARM_mve_typeid(x) _Generic(x, \ - int16_t: __ARM_mve_type_int16_t, \ - int16_t *: __ARM_mve_type_int16_t_ptr, \ - int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ - int16x8_t: __ARM_mve_type_int16x8_t, \ - int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ - int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ - int32_t: __ARM_mve_type_int32_t, \ - int32_t *: __ARM_mve_type_int32_t_ptr, \ - int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ - int32x4_t: __ARM_mve_type_int32x4_t, \ - int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ - int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ - int64_t: __ARM_mve_type_int64_t, \ - int64_t *: __ARM_mve_type_int64_t_ptr, \ - int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ - int64x2_t: __ARM_mve_type_int64x2_t, \ - int8_t: __ARM_mve_type_int8_t, \ - int8_t *: __ARM_mve_type_int8_t_ptr, \ - int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ - int8x16_t: __ARM_mve_type_int8x16_t, \ - int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ - int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ - uint16_t: __ARM_mve_type_uint16_t, \ - uint16_t *: __ARM_mve_type_uint16_t_ptr, \ - uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ - uint16x8_t: __ARM_mve_type_uint16x8_t, \ - uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ - uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ - uint32_t: __ARM_mve_type_uint32_t, \ - uint32_t *: __ARM_mve_type_uint32_t_ptr, \ - uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ - uint32x4_t: __ARM_mve_type_uint32x4_t, \ - uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ - uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ - uint64_t: __ARM_mve_type_uint64_t, \ - uint64_t *: __ARM_mve_type_uint64_t_ptr, \ - uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ - uint64x2_t: __ARM_mve_type_uint64x2_t, \ - uint8_t: __ARM_mve_type_uint8_t, \ - uint8_t *: __ARM_mve_type_uint8_t_ptr, \ - uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ - uint8x16_t: __ARM_mve_type_uint8x16_t, \ - uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ - uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ - default: _Generic(x, \ - signed char: __ARM_mve_type_int8_t, \ - short: __ARM_mve_type_int16_t, \ - int: __ARM_mve_type_int32_t, \ - long: __ARM_mve_type_int32_t, \ - long long: __ARM_mve_type_int64_t, \ - unsigned char: __ARM_mve_type_uint8_t, \ - unsigned short: __ARM_mve_type_uint16_t, \ - unsigned int: __ARM_mve_type_uint32_t, \ - unsigned long: __ARM_mve_type_uint32_t, \ - unsigned long long: __ARM_mve_type_uint64_t, \ - default: __ARM_mve_unsupported_type)) -#endif /* MVE Floating point. */ +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define __ARM_mve_typeid(x) _Generic(x, \ + float16_t: __ARM_mve_type_float16_t, \ + float16_t *: __ARM_mve_type_float16_t_ptr, \ + float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ + float16x8_t: __ARM_mve_type_float16x8_t, \ + float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ + float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ + float32_t: __ARM_mve_type_float32_t, \ + float32_t *: __ARM_mve_type_float32_t_ptr, \ + float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ + float32x4_t: __ARM_mve_type_float32x4_t, \ + float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ + float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#else +#define __ARM_mve_typeid(x) _Generic(x, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#endif /* MVE Floating point. */ + +extern void *__ARM_undef; +#define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vdupq_n(p0) __arm_vdupq_n(p0) +#define __arm_vdupq_n(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vdupq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vdupq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vsubq(p0,p1) __arm_vsubq(p0,p1) +#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vshlq(p0,p1) __arm_vshlq(p0,p1) +#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vshrq(p0,p1) __arm_vshrq(p0,p1) +#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) +#define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_n_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_n_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vorrq(p0,p1) __arm_vorrq(p0,p1) +#define __arm_vorrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vabdq(p0,p1) __arm_vabdq(p0,p1) +#define __arm_vabdq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vaddq(p0,p1) __arm_vaddq(p0,p1) +#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vandq(p0,p1) __arm_vandq(p0,p1) +#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vbicq(p0,p1) __arm_vbicq(p0,p1) +#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vornq(p0,p1) __arm_vornq(p0,p1) +#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmulq_n(p0,p1) __arm_vmulq_n(p0,p1) +#define __arm_vmulq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vmulq(p0,p1) __arm_vmulq(p0,p1) +#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcaddq_rot270(p0,p1) __arm_vcaddq_rot270(p0,p1) +#define __arm_vcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpeqq(p0,p1) __arm_vcmpeqq(p0,p1) +#define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcaddq_rot90(p0,p1) __arm_vcaddq_rot90(p0,p1) +#define __arm_vcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpgeq_n(p0,p1) __arm_vcmpgeq_n(p0,p1) +#define __arm_vcmpgeq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpgtq_n(p0,p1) __arm_vcmpgtq_n(p0,p1) +#define __arm_vcmpgtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpleq(p0,p1) __arm_vcmpleq(p0,p1) +#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpltq(p0,p1) __arm_vcmpltq(p0,p1) +#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) +#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq(p0,p1) __arm_vcmulq(p0,p1) +#define __arm_vcmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq_rot180(p0,p1) __arm_vcmulq_rot180(p0,p1) +#define __arm_vcmulq_rot180(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq_rot270(p0,p1) __arm_vcmulq_rot270(p0,p1) +#define __arm_vcmulq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq_rot90(p0,p1) __arm_vcmulq_rot90(p0,p1) +#define __arm_vcmulq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define veorq(p0,p1) __arm_veorq(p0,p1) +#define __arm_veorq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmaxnmaq(p0,p1) __arm_vmaxnmaq(p0,p1) +#define __arm_vmaxnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmaxnmavq(p0,p1) __arm_vmaxnmavq(p0,p1) +#define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmaxnmq(p0,p1) __arm_vmaxnmq(p0,p1) +#define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) +#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) +#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vminnmaq(p0,p1) __arm_vminnmaq(p0,p1) +#define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vminnmavq(p0,p1) __arm_vminnmavq(p0,p1) +#define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) +#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) + +#define vminnmq(p0,p1) __arm_vminnmq(p0,p1) +#define __arm_vminnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vminnmvq(p0,p1) __arm_vminnmvq(p0,p1) +#define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vshlq_r(p0,p1) __arm_vshlq_r(p0,p1) +#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vshlq_n(p0,p1) __arm_vshlq_n(p0,p1) +#define __arm_vshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vshlltq(p0,p1) __arm_vshlltq(p0,p1) +#define __arm_vshlltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) -extern void *__ARM_undef; -#define __ARM_mve_coerce(param, type) \ - _Generic(param, type: param, default: *(type *)__ARM_undef) +#define vshllbq(p0,p1) __arm_vshllbq(p0,p1) +#define __arm_vshllbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) +#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vst4q(p0,p1) __arm_vst4q(p0,p1) -#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) +#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) +#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vrndxq(p0) __arm_vrndxq(p0) -#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vrmulhq(p0,p1) __arm_vrmulhq(p0,p1) +#define __arm_vrmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vrhaddq(p0,p1) __arm_vrhaddq(p0,p1) +#define __arm_vrhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) +#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqshluq(p0,p1) __arm_vqshluq(p0,p1) +#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) -#define vrndq(p0) __arm_vrndq(p0) -#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vqshlq(p0,p1) __arm_vqshlq(p0,p1) +#define __arm_vqshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqshlq_r(p0,p1) __arm_vqshlq_r(p0,p1) +#define __arm_vqshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vqshlq_n(p0,p1) __arm_vqshlq_n(p0,p1) +#define __arm_vqshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vrndpq(p0) __arm_vrndpq(p0) -#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqrshlq(p0,p1) __arm_vqrshlq(p0,p1) +#define __arm_vqrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) -#define vrndnq(p0) __arm_vrndnq(p0) -#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqrdmulhq(p0,p1) __arm_vqrdmulhq(p0,p1) +#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) -#define vrndmq(p0) __arm_vrndmq(p0) -#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmlaldavxq(p0,p1) __arm_vmlaldavxq(p0,p1) +#define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vrndaq(p0) __arm_vrndaq(p0) -#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqmovuntq(p0,p1) __arm_vqmovuntq(p0,p1) +#define __arm_vqmovuntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vrev64q(p0) __arm_vrev64q(p0) -#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqmovntq(p0,p1) __arm_vqmovntq(p0,p1) +#define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vnegq(p0) __arm_vnegq(p0) -#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqmovnbq(p0,p1) __arm_vqmovnbq(p0,p1) +#define __arm_vqmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vabsq(p0) __arm_vabsq(p0) -#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vqdmulltq(p0,p1) __arm_vqdmulltq(p0,p1) +#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vrev32q(p0) __arm_vrev32q(p0) -#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vqmovunbq(p0,p1) __arm_vqmovunbq(p0,p1) +#define __arm_vqmovunbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) -#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vqdmullbq(p0,p1) __arm_vqdmullbq(p0,p1) +#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) -#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vqdmulhq(p0,p1) __arm_vqdmulhq(p0,p1) +#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vrev16q(p0) __arm_vrev16q(p0) -#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) +#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) +#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vqabsq(p0) __arm_vqabsq(p0) -#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vmulltq_poly(p0,p1) __arm_vmulltq_poly(p0,p1) +#define __arm_vmulltq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) -#define vqnegq(p0) __arm_vqnegq(p0) -#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vmullbq_poly(p0,p1) __arm_vmullbq_poly(p0,p1) +#define __arm_vmullbq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) -#define vmvnq(p0) __arm_vmvnq(p0) -#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vmulltq_int(p0,p1) __arm_vmulltq_int(p0,p1) +#define __arm_vmulltq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vmovlbq(p0) __arm_vmovlbq(p0) -#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) +#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) +#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vmovltq(p0) __arm_vmovltq(p0) -#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) +#define vhcaddq_rot270(p0,p1) __arm_vhcaddq_rot270(p0,p1) +#define __arm_vhcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vclzq(p0) __arm_vclzq(p0) -#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vhcaddq_rot90(p0,p1) __arm_vhcaddq_rot90(p0,p1) +#define __arm_vhcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vclsq(p0) __arm_vclsq(p0) -#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) +#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcvtq(p0) __arm_vcvtq(p0) -#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vminq(p0,p1) __arm_vminq(p0,p1) +#define __arm_vminq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vsubq(p0,p1) __arm_vsubq(p0,p1) -#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vminaq(p0,p1) __arm_vminaq(p0,p1) +#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) -#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) +#define vmaxq(p0,p1) __arm_vmaxq(p0,p1) +#define __arm_vmaxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vshlq(p0,p1) __arm_vshlq(p0,p1) -#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxaq(p0,p1) __arm_vmaxaq(p0,p1) +#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vshrq(p0,p1) __arm_vshrq(p0,p1) -#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vmovntq(p0,p1) __arm_vmovntq(p0,p1) +#define __arm_vmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) -#define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_n_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_n_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vmovnbq(p0,p1) __arm_vmovnbq(p0,p1) +#define __arm_vmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) -#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmulhq(p0,p1) __arm_vmulhq(p0,p1) +#define __arm_vmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmullbq_int(p0,p1) __arm_vmullbq_int(p0,p1) +#define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) #define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -4744,7 +6676,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#else /* MVE Interger. */ +#else /* MVE Interger. srinath*/ #define vst4q(p0,p1) __arm_vst4q(p0,p1) #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -4915,12 +6847,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) - -#define vsubq_n(p0,p1) __arm_vsubq_n(p0,p1) -#define __arm_vsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ @@ -4938,43 +6865,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vrshlq_n(p0,p1) __arm_vrshlq_n(p0,p1) -#define __arm_vrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) - #define vrshlq(p0,p1) __arm_vrshlq(p0,p1) #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) - -#define vrshlq_n(p0,p1) __arm_vrshlq_n(p0,p1) -#define __arm_vrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) - -#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) -#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -5004,8 +6904,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vqsubq_n(p0,p1) __arm_vqsubq_n(p0,p1) -#define __arm_vqsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) +#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ @@ -5013,12 +6913,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) - -#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) -#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -5054,8 +6949,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) -#define vrshrq_n(p0,p1) __arm_vrshrq_n(p0,p1) -#define __arm_vrshrq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) +#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ @@ -5074,13 +6969,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vqshluq_n(p0,p1) __arm_vqshluq_n(p0,p1) -#define __arm_vqshluq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) - #define vqshlq_n(p0,p1) __arm_vqshlq_n(p0,p1) #define __arm_vqshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -5091,17 +6979,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vqrshlq_n(p0,p1) __arm_vqrshlq_n(p0,p1) -#define __arm_vqrshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) - #define vqrshlq(p0,p1) __arm_vqrshlq(p0,p1) #define __arm_vqrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -5111,15 +6988,13 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) - -#define vqrdmulhq_n(p0,p1) __arm_vqrdmulhq_n(p0,p1) -#define __arm_vqrdmulhq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) #define vqrdmulhq(p0,p1) __arm_vqrdmulhq(p0,p1) #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -5127,26 +7002,24 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) - -#define vqdmulhq_n(p0,p1) __arm_vqdmulhq_n(p0,p1) -#define __arm_vqdmulhq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) #define vqdmulhq(p0,p1) __arm_vqdmulhq(p0,p1) #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vqaddq_n(p0,p1) __arm_vqaddq_n(p0,p1) -#define __arm_vqaddq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) +#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ @@ -5154,12 +7027,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) - -#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) -#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -5167,15 +7035,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vorrq_n(p0,p1) __arm_vorrq_n(p0,p1) -#define __arm_vorrq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)));}) - #define vorrq(p0,p1) __arm_vorrq(p0,p1) #define __arm_vorrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -5291,8 +7150,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vhsubq_n(p0,p1) __arm_vhsubq_n(p0,p1) -#define __arm_vhsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) +#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ @@ -5300,12 +7159,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) - -#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) -#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -5329,8 +7183,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vhaddq_n(p0,p1) __arm_vhaddq_n(p0,p1) -#define __arm_vhaddq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) +#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ @@ -5338,12 +7192,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) - -#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) -#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -5414,12 +7263,7 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) - -#define vaddq(p0,p1) __arm_vaddq(p0,p1) -#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ @@ -5591,6 +7435,129 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vqmovntq(p0,p1) __arm_vqmovntq(p0,p1) +#define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqmovnbq(p0,p1) __arm_vqmovnbq(p0,p1) +#define __arm_vqmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmulltq_poly(p0,p1) __arm_vmulltq_poly(p0,p1) +#define __arm_vmulltq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) + +#define vmullbq_poly(p0,p1) __arm_vmullbq_poly(p0,p1) +#define __arm_vmullbq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) + +#define vmovntq(p0,p1) __arm_vmovntq(p0,p1) +#define __arm_vmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmovnbq(p0,p1) __arm_vmovnbq(p0,p1) +#define __arm_vmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vmlaldavxq(p0,p1) __arm_vmlaldavxq(p0,p1) +#define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqmovuntq(p0,p1) __arm_vqmovuntq(p0,p1) +#define __arm_vqmovuntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vshlltq(p0,p1) __arm_vshlltq(p0,p1) +#define __arm_vshlltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) + +#define vshllbq(p0,p1) __arm_vshllbq(p0,p1) +#define __arm_vshllbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) + +#define vmlaldavq(p0,p1) __arm_vmlaldavq(p0,p1) +#define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqmovunbq(p0,p1) __arm_vqmovunbq(p0,p1) +#define __arm_vqmovunbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqdmulltq(p0,p1) __arm_vqdmulltq(p0,p1) +#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqdmullbq(p0,p1) __arm_vqdmullbq(p0,p1) +#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vcmpgeq_n(p0,p1) __arm_vcmpgeq_n(p0,p1) +#define __arm_vcmpgeq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + #define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) #define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -5646,6 +7613,46 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) +#define vaddlvaq(p0,p1) __arm_vaddlvaq(p0,p1) +#define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vrmlaldavhq(p0,p1) __arm_vrmlaldavhq(p0,p1) +#define __arm_vrmlaldavhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vrmlaldavhxq(p0,p1) __arm_vrmlaldavhxq(p0,p1) +#define __arm_vrmlaldavhxq(p0,p1) __arm_vrmlaldavhxq_s32(p0,p1) + +#define vrmlsldavhq(p0,p1) __arm_vrmlsldavhq(p0,p1) +#define __arm_vrmlsldavhq(p0,p1) __arm_vrmlsldavhq_s32(p0,p1) + +#define vrmlsldavhq(p0,p1) __arm_vrmlsldavhq(p0,p1) +#define __arm_vrmlsldavhq(p0,p1) __arm_vrmlsldavhq_s32(p0,p1) + +#define vrmlsldavhxq(p0,p1) __arm_vrmlsldavhxq(p0,p1) +#define __arm_vrmlsldavhxq(p0,p1) __arm_vrmlsldavhxq_s32(p0,p1) + +#define vmlsldavxq(p0,p1) __arm_vmlsldavxq(p0,p1) +#define __arm_vmlsldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vmlsldavq(p0,p1) __arm_vmlsldavq(p0,p1) +#define __arm_vmlsldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 550a67f..7129b99 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -18,198 +18,276 @@ along with GCC; see the file COPYING3. If not see . */ -VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) -VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) -VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) -VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) -VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) -VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) -VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) -VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) -VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) -VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) -VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) -VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) -VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) -VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) -VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) -VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) -VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) -VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) -VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi) -VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si) -VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) -VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) -VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) -VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) -VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) -VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) -VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) -VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) -VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) -VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) -VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) -VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) -VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) -VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) -VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) -VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) -VAR1 (UNOP_UNONE_UNONE, vctp16q, hi) -VAR1 (UNOP_UNONE_UNONE, vctp32q, hi) -VAR1 (UNOP_UNONE_UNONE, vctp64q, hi) -VAR1 (UNOP_UNONE_UNONE, vctp8q, hi) -VAR1 (UNOP_UNONE_UNONE, vpnot, hi) -VAR2 (BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) -VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) -VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) -VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) -VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) -VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) -VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) -VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) -VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si) +VAR5(STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2(UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1(UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1(UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1(UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2(UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2(UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) +VAR3(UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) +VAR3(UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) +VAR2(UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) +VAR2(UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) +VAR2(UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) +VAR2(UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) +VAR2(UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) +VAR2(UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) +VAR2(UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) +VAR2(UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) +VAR2(UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) +VAR1(UNOP_SNONE_SNONE, vrev16q_s, v16qi) +VAR1(UNOP_SNONE_SNONE, vaddlvq_s, v4si) +VAR3(UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) +VAR3(UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) +VAR3(UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) +VAR3(UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) +VAR3(UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) +VAR2(UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) +VAR2(UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) +VAR2(UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) +VAR2(UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) +VAR2(UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) +VAR2(UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) +VAR2(UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) +VAR2(UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) +VAR2(UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) +VAR1(UNOP_UNONE_UNONE, vrev16q_u, v16qi) +VAR1(UNOP_UNONE_UNONE, vaddlvq_u, v4si) +VAR1(UNOP_UNONE_UNONE, vctp16q, hi) +VAR1(UNOP_UNONE_UNONE, vctp32q, hi) +VAR1(UNOP_UNONE_UNONE, vctp64q, hi) +VAR1(UNOP_UNONE_UNONE, vctp8q, hi) +VAR1(UNOP_UNONE_UNONE, vpnot, hi) +VAR2(BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) +VAR2(BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) +VAR2(BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) +VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) +VAR4(BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) +VAR4(BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) +VAR3(BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) +VAR1(BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) +VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si) +VAR3(BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_UNONE, vqmovntq_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_UNONE, vqmovnbq_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_UNONE, vmulltq_poly_p, v16qi, v8hi) +VAR2(BINOP_UNONE_UNONE_UNONE, vmullbq_poly_p, v16qi, v8hi) +VAR2(BINOP_UNONE_UNONE_UNONE, vmovntq_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_UNONE, vmovnbq_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_UNONE, vmlaldavq_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_NONE, vqmovuntq_s, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_NONE, vqmovunbq_s, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) +VAR2(BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) +VAR2(BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) +VAR2(BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) +VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) +VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vqmovnbq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_n_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_n_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vorrq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vornq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmulq_n_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmulq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmovntq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vmovnbq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vmlsldavxq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vmlsldavq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vmlaldavxq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vmlaldavq_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_NONE, vminnmvq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vminnmq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vminnmavq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vminnmaq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmaxnmvq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmaxnmq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmaxnmavq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vmaxnmaq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, veorq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vbicq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vandq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vaddq_n_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_NONE, vabdq_f, v8hf, v4sf) +VAR2(BINOP_NONE_NONE_IMM, vshlltq_n_s, v16qi, v8hi) +VAR2(BINOP_NONE_NONE_IMM, vshllbq_n_s, v16qi, v8hi) +VAR2(BINOP_NONE_NONE_IMM, vorrq_n_s, v8hi, v4si) +VAR2(BINOP_NONE_NONE_IMM, vbicq_n_s, v8hi, v4si) +VAR1(BINOP_UNONE_UNONE_UNONE, vrmlaldavhq_u, v4si) +VAR1(BINOP_UNONE_UNONE_UNONE, vctp8q_m, hi) +VAR1(BINOP_UNONE_UNONE_UNONE, vctp64q_m, hi) +VAR1(BINOP_UNONE_UNONE_UNONE, vctp32q_m, hi) +VAR1(BINOP_UNONE_UNONE_UNONE, vctp16q_m, hi) +VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvaq_u, v4si) +VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhxq_s, v4si) +VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhq_s, v4si) +VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhxq_s, v4si) +VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si) +VAR1(BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf) +VAR1(BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf) +VAR1(BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 8e817b8..24fb816 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -66,7 +66,26 @@ VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S - VABDQ_M_U]) + VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F + VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F + VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F + VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F + VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F + VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F + VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F + VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U + VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M + VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32 + VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S + VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S + VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S + VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U + VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S + VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S + VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S + VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S + VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P + VMULLBQ_POLY_P]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -119,10 +138,19 @@ (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s") (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u") (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") - (VADDVAQ_U "u")]) + (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u") + (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u") + (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s") + (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u") + (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u") + (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") + (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s") + (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u") + (VRMLALDAVHQ_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") - (VCTP64Q "64")]) + (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") + (VCTP32Q_M "32") (VCTP64Q_M "64")]) (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") (V4SI "mve_imm_32")]) (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) @@ -146,6 +174,7 @@ (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) +(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M]) (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) @@ -200,7 +229,18 @@ (define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U]) (define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U]) (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U]) - +(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U]) +(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U]) +(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S]) +(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S]) +(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S]) +(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) +(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) +(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S]) +(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S]) +(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U]) +(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S]) +(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -2057,3 +2097,963 @@ "vsub.i%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) + +;; +;; [vabdq_f]) +;; +(define_insn "mve_vabdq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VABDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vabd.f%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddlvaq_s vaddlvaq_u]) +;; +(define_insn "mve_vaddlvaq_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w")] + VADDLVAQ)) + ] + "TARGET_HAVE_MVE" + "vaddlva.32 %Q0, %R0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddq_n_f]) +;; +(define_insn "mve_vaddq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VADDQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vadd.f%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vandq_f]) +;; +(define_insn "mve_vandq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VANDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vand %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vbicq_f]) +;; +(define_insn "mve_vbicq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VBICQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vbic %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vbicq_n_s, vbicq_n_u]) +;; +(define_insn "mve_vbicq_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")] + VBICQ_N)) + ] + "TARGET_HAVE_MVE" + "vbic.i%# %q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcaddq_rot270_f]) +;; +(define_insn "mve_vcaddq_rot270_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCADDQ_ROT270_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcadd.f%# %q0, %q1, %q2, #270" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcaddq_rot90_f]) +;; +(define_insn "mve_vcaddq_rot90_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCADDQ_ROT90_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcadd.f%# %q0, %q1, %q2, #90" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpeqq_f]) +;; +(define_insn "mve_vcmpeqq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPEQQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# eq, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpeqq_n_f]) +;; +(define_insn "mve_vcmpeqq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPEQQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# eq, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgeq_f]) +;; +(define_insn "mve_vcmpgeq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPGEQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# ge, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgeq_n_f]) +;; +(define_insn "mve_vcmpgeq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPGEQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# ge, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgtq_f]) +;; +(define_insn "mve_vcmpgtq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPGTQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# gt, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpgtq_n_f]) +;; +(define_insn "mve_vcmpgtq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPGTQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# gt, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpleq_f]) +;; +(define_insn "mve_vcmpleq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPLEQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# le, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpleq_n_f]) +;; +(define_insn "mve_vcmpleq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPLEQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# le, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpltq_f]) +;; +(define_insn "mve_vcmpltq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPLTQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# lt, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpltq_n_f]) +;; +(define_insn "mve_vcmpltq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPLTQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# lt, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpneq_f]) +;; +(define_insn "mve_vcmpneq_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMPNEQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# ne, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpneq_n_f]) +;; +(define_insn "mve_vcmpneq_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VCMPNEQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmp.f%# ne, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmulq_f]) +;; +(define_insn "mve_vcmulq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMULQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmul.f%# %q0, %q1, %q2, #0" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmulq_rot180_f]) +;; +(define_insn "mve_vcmulq_rot180_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMULQ_ROT180_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmul.f%# %q0, %q1, %q2, #180" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmulq_rot270_f]) +;; +(define_insn "mve_vcmulq_rot270_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMULQ_ROT270_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmul.f%# %q0, %q1, %q2, #270" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmulq_rot90_f]) +;; +(define_insn "mve_vcmulq_rot90_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VCMULQ_ROT90_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmul.f%# %q0, %q1, %q2, #90" + [(set_attr "type" "mve_move") +]) + +;; +;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) +;; +(define_insn "mve_vctpq_mhi" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VCTPQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vctpt. %1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtbq_f16_f32]) +;; +(define_insn "mve_vcvtbq_f16_f32v8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") + (match_operand:V4SF 2 "s_register_operand" "w")] + VCVTBQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtb.f16.f32 %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvttq_f16_f32]) +;; +(define_insn "mve_vcvttq_f16_f32v8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") + (match_operand:V4SF 2 "s_register_operand" "w")] + VCVTTQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtt.f16.f32 %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [veorq_f]) +;; +(define_insn "mve_veorq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VEORQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "veor %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxnmaq_f]) +;; +(define_insn "mve_vmaxnmaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMAXNMAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmaxnma.f%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxnmavq_f]) +;; +(define_insn "mve_vmaxnmavq_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMAXNMAVQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmaxnmav.f%# %0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxnmq_f]) +;; +(define_insn "mve_vmaxnmq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMAXNMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmaxnm.f%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxnmvq_f]) +;; +(define_insn "mve_vmaxnmvq_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMAXNMVQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmaxnmv.f%# %0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminnmaq_f]) +;; +(define_insn "mve_vminnmaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMINNMAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vminnma.f%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminnmavq_f]) +;; +(define_insn "mve_vminnmavq_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMINNMAVQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vminnmav.f%# %0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminnmq_f]) +;; +(define_insn "mve_vminnmq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMINNMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vminnm.f%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vminnmvq_f]) +;; +(define_insn "mve_vminnmvq_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMINNMVQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vminnmv.f%# %0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlaldavq_u, vmlaldavq_s]) +;; +(define_insn "mve_vmlaldavq_" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMLALDAVQ)) + ] + "TARGET_HAVE_MVE" + "vmlaldav.%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlaldavxq_s]) +;; +(define_insn "mve_vmlaldavxq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMLALDAVXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlaldavx.s%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsldavq_s]) +;; +(define_insn "mve_vmlsldavq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMLSLDAVQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsldav.s%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsldavxq_s]) +;; +(define_insn "mve_vmlsldavxq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMLSLDAVXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsldavx.s%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovnbq_u, vmovnbq_s]) +;; +(define_insn "mve_vmovnbq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMOVNBQ)) + ] + "TARGET_HAVE_MVE" + "vmovnb.i%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovntq_s, vmovntq_u]) +;; +(define_insn "mve_vmovntq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VMOVNTQ)) + ] + "TARGET_HAVE_MVE" + "vmovnt.i%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulq_f]) +;; +(define_insn "mve_vmulq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VMULQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmul.f%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulq_n_f]) +;; +(define_insn "mve_vmulq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VMULQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vmul.f%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vornq_f]) +;; +(define_insn "mve_vornq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VORNQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vorn %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vorrq_f]) +;; +(define_insn "mve_vorrq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VORRQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vorr %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vorrq_n_u, vorrq_n_s]) +;; +(define_insn "mve_vorrq_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")] + VORRQ_N)) + ] + "TARGET_HAVE_MVE" + "vorr.i%# %q0, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmullbq_n_s]) +;; +(define_insn "mve_vqdmullbq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQDMULLBQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqdmullb.s%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmullbq_s]) +;; +(define_insn "mve_vqdmullbq_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQDMULLBQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmullb.s%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmulltq_n_s]) +;; +(define_insn "mve_vqdmulltq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r")] + VQDMULLTQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqdmullt.s%# %q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmulltq_s]) +;; +(define_insn "mve_vqdmulltq_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQDMULLTQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmullt.s%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqmovnbq_u, vqmovnbq_s]) +;; +(define_insn "mve_vqmovnbq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQMOVNBQ)) + ] + "TARGET_HAVE_MVE" + "vqmovnb.%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqmovntq_u, vqmovntq_s]) +;; +(define_insn "mve_vqmovntq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQMOVNTQ)) + ] + "TARGET_HAVE_MVE" + "vqmovnt.%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqmovunbq_s]) +;; +(define_insn "mve_vqmovunbq_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQMOVUNBQ_S)) + ] + "TARGET_HAVE_MVE" + "vqmovunb.s%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqmovuntq_s]) +;; +(define_insn "mve_vqmovuntq_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w")] + VQMOVUNTQ_S)) + ] + "TARGET_HAVE_MVE" + "vqmovunt.s%# %q0, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlaldavhxq_s]) +;; +(define_insn "mve_vrmlaldavhxq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VRMLALDAVHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlsldavhq_s]) +;; +(define_insn "mve_vrmlsldavhq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VRMLSLDAVHQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlsldavhxq_s]) +;; +(define_insn "mve_vrmlsldavhxq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VRMLSLDAVHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshllbq_n_s, vshllbq_n_u]) +;; +(define_insn "mve_vshllbq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VSHLLBQ_N)) + ] + "TARGET_HAVE_MVE" + "vshllb.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshlltq_n_u, vshlltq_n_s]) +;; +(define_insn "mve_vshlltq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VSHLLTQ_N)) + ] + "TARGET_HAVE_MVE" + "vshllt.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vsubq_f]) +;; +(define_insn "mve_vsubq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w")] + VSUBQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vsub.f%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmulltq_poly_p]) +;; +(define_insn "mve_vmulltq_poly_p" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") + (match_operand:MVE_3 2 "s_register_operand" "w")] + VMULLTQ_POLY_P)) + ] + "TARGET_HAVE_MVE" + "vmullt.p%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmullbq_poly_p]) +;; +(define_insn "mve_vmullbq_poly_p" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w") + (match_operand:MVE_3 2 "s_register_operand" "w")] + VMULLBQ_POLY_P)) + ] + "TARGET_HAVE_MVE" + "vmullb.p%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlaldavhq_u vrmlaldavhq_s]) +;; +(define_insn "mve_vrmlaldavhq_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VRMLALDAVHQ)) + ] + "TARGET_HAVE_MVE" + "vrmlaldavh.32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0635e97..5cc2c04 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,156 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c new file mode 100644 index 0000000..b653833 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vabdq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vabd.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c new file mode 100644 index 0000000..c62cbc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vabdq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vabd.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vabdq (a, b); +} + +/* { dg-final { scan-assembler "vabd.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c new file mode 100644 index 0000000..af890f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b) +{ + return vaddlvaq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vaddlva.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b) +{ + return vaddlvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddlva.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c new file mode 100644 index 0000000..6dd14bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b) +{ + return vaddlvaq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vaddlva.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b) +{ + return vaddlvaq (a, b); +} + +/* { dg-final { scan-assembler "vaddlva.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c new file mode 100644 index 0000000..f0783c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b) +{ + return vaddq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c new file mode 100644 index 0000000..80ea7a42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b) +{ + return vaddq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c new file mode 100644 index 0000000..39feba4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vandq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c new file mode 100644 index 0000000..41e9168 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vandq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vandq (a, b); +} + +/* { dg-final { scan-assembler "vand" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c new file mode 100644 index 0000000..7f62d4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vbicq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c new file mode 100644 index 0000000..022278e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vbicq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vbicq (a, b); +} + +/* { dg-final { scan-assembler "vbic" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c new file mode 100644 index 0000000..00d7ad9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vbicq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vbic.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c new file mode 100644 index 0000000..747675d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vbicq_n_s32 (a, 1); +} + +/* { dg-final { scan-assembler "vbic.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c new file mode 100644 index 0000000..ac542fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vbicq_n_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vbic.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c new file mode 100644 index 0000000..3326e7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vbicq_n_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vbic.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c new file mode 100644 index 0000000..b53fda7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcaddq_rot270_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c new file mode 100644 index 0000000..6410ee6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcaddq_rot270_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcaddq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c new file mode 100644 index 0000000..d3b7a90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcaddq_rot90_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c new file mode 100644 index 0000000..b588b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcaddq_rot90_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcaddq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcadd.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c new file mode 100644 index 0000000..fcc4549 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpeqq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c new file mode 100644 index 0000000..b90bdf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpeqq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpeqq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c new file mode 100644 index 0000000..8a35c01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpeqq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpeqq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c new file mode 100644 index 0000000..28b0fbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpeqq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpeqq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c new file mode 100644 index 0000000..a71993a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpgeq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c new file mode 100644 index 0000000..0499b4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpgeq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpgeq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c new file mode 100644 index 0000000..98e0e610 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpgeq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpgeq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c new file mode 100644 index 0000000..1e522a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpgeq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpgeq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c new file mode 100644 index 0000000..76baa4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpgtq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c new file mode 100644 index 0000000..593babb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpgtq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpgtq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c new file mode 100644 index 0000000..57d3838 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpgtq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpgtq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c new file mode 100644 index 0000000..305972e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpgtq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpgtq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c new file mode 100644 index 0000000..30e9fc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpleq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c new file mode 100644 index 0000000..0be1ac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpleq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpleq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c new file mode 100644 index 0000000..7ec4e0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpleq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpleq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c new file mode 100644 index 0000000..274dc7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpleq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpleq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c new file mode 100644 index 0000000..00800f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpltq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c new file mode 100644 index 0000000..3aeeea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpltq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpltq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c new file mode 100644 index 0000000..0e51876 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpltq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpltq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c new file mode 100644 index 0000000..5f7cf8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpltq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpltq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c new file mode 100644 index 0000000..f34e236 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmpneq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c new file mode 100644 index 0000000..697b312 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmpneq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmpneq (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c new file mode 100644 index 0000000..dfa0af7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b) +{ + return vcmpneq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b) +{ + return vcmpneq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c new file mode 100644 index 0000000..806546c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b) +{ + return vcmpneq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b) +{ + return vcmpneq_n (a, b); +} + +/* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c new file mode 100644 index 0000000..c2628eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmulq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmulq (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c new file mode 100644 index 0000000..86601e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmulq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmulq (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c new file mode 100644 index 0000000..621a5c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot180_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot180 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c new file mode 100644 index 0000000..1984f8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot180_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot180 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c new file mode 100644 index 0000000..f1b52d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot270_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c new file mode 100644 index 0000000..ab1c8ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot270_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot270 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c new file mode 100644 index 0000000..5ea6c4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot90_f16 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vcmulq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c new file mode 100644 index 0000000..5765076 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot90_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vcmulq_rot90 (a, b); +} + +/* { dg-final { scan-assembler "vcmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c new file mode 100644 index 0000000..f332577 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vctp16q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vctpt.16" } } */ + +mve_pred16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vctp16q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c new file mode 100644 index 0000000..f1260f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vctp32q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vctpt.32" } } */ + +mve_pred16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vctp32q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c new file mode 100644 index 0000000..976289c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vctp64q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vctpt.64" } } */ + +mve_pred16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vctp64q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c new file mode 100644 index 0000000..56b48f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vctp8q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vctpt.8" } } */ + +mve_pred16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vctp8q_m (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c new file mode 100644 index 0000000..cc63222 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float32x4_t b) +{ + return vcvtbq_f16_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c new file mode 100644 index 0000000..8d34e7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float32x4_t b) +{ + return vcvttq_f16_f32 (a, b); +} + +/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c new file mode 100644 index 0000000..e9398d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return veorq_f16 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c new file mode 100644 index 0000000..0a7ca68 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return veorq_f32 (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return veorq (a, b); +} + +/* { dg-final { scan-assembler "veor" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c index 75977c4..3e63f18 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c index 0bfe84d..1ca4a6f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c index 4901b91..721b3c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c index 88b1e2e..50ca937e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b) uint16x8_t foo1 (uint16x8_t a, uint16_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c index ad492e5..f522f94 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b) uint32x4_t foo1 (uint32x4_t a, uint32_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c index 328f09a..8367bde 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b) uint8x16_t foo1 (uint8x16_t a, uint8_t b) { - return vhaddq_n (a, b); + return vhaddq (a, b); } /* { dg-final { scan-assembler "vhadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c index 723c27a..654e4e5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c index 2d2b13d..bea8367 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c index 4180563..35209c3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c index 93e1395..0d79078 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b) uint16x8_t foo1 (uint16x8_t a, uint16_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c index 06dddd4..95797d3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b) uint32x4_t foo1 (uint32x4_t a, uint32_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c index ea81c02..2965a31 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b) uint8x16_t foo1 (uint8x16_t a, uint8_t b) { - return vhsubq_n (a, b); + return vhsubq (a, b); } /* { dg-final { scan-assembler "vhsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c new file mode 100644 index 0000000..424e9e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vmaxnmaq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnma.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vmaxnmaq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnma.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c new file mode 100644 index 0000000..35b960c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vmaxnmaq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnma.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vmaxnmaq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnma.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c new file mode 100644 index 0000000..bcbf659 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b) +{ + return vmaxnmavq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmav.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b) +{ + return vmaxnmavq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmav.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c new file mode 100644 index 0000000..dc88ef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b) +{ + return vmaxnmavq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmav.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b) +{ + return vmaxnmavq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmav.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c new file mode 100644 index 0000000..9c136b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vmaxnmq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnm.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vmaxnmq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c new file mode 100644 index 0000000..86222d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vmaxnmq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnm.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vmaxnmq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c new file mode 100644 index 0000000..4f6ce2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b) +{ + return vmaxnmvq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmv.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b) +{ + return vmaxnmvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmv.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c new file mode 100644 index 0000000..5206bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b) +{ + return vmaxnmvq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmv.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b) +{ + return vmaxnmvq (a, b); +} + +/* { dg-final { scan-assembler "vmaxnmv.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c new file mode 100644 index 0000000..ea2ab72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vminnmaq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vminnma.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vminnmaq (a, b); +} + +/* { dg-final { scan-assembler "vminnma.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c new file mode 100644 index 0000000..14ed06e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vminnmaq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vminnma.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vminnmaq (a, b); +} + +/* { dg-final { scan-assembler "vminnma.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c new file mode 100644 index 0000000..e89076e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b) +{ + return vminnmavq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vminnmav.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b) +{ + return vminnmavq (a, b); +} + +/* { dg-final { scan-assembler "vminnmav.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c new file mode 100644 index 0000000..d06c1a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b) +{ + return vminnmavq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vminnmav.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b) +{ + return vminnmavq (a, b); +} + +/* { dg-final { scan-assembler "vminnmav.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c new file mode 100644 index 0000000..f7c051e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vminnmq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vminnm.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vminnmq (a, b); +} + +/* { dg-final { scan-assembler "vminnm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c new file mode 100644 index 0000000..7f1d843 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vminnmq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vminnm.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vminnmq (a, b); +} + +/* { dg-final { scan-assembler "vminnm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c new file mode 100644 index 0000000..c0307b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b) +{ + return vminnmvq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vminnmv.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b) +{ + return vminnmvq (a, b); +} + +/* { dg-final { scan-assembler "vminnmv.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c new file mode 100644 index 0000000..da7a861 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b) +{ + return vminnmvq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vminnmv.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b) +{ + return vminnmvq (a, b); +} + +/* { dg-final { scan-assembler "vminnmv.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c new file mode 100644 index 0000000..f456d3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlaldavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlaldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c new file mode 100644 index 0000000..8453d9d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlaldavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlaldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c new file mode 100644 index 0000000..e4c1f32 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmlaldavq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.u16" } } */ + +uint64_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmlaldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c new file mode 100644 index 0000000..3c4ff64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vmlaldavq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.u32" } } */ + +uint64_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vmlaldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldav.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c new file mode 100644 index 0000000..a7268d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlaldavxq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlaldavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c new file mode 100644 index 0000000..fe0a178 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlaldavxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlaldavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c new file mode 100644 index 0000000..1215b36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlsldavq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlsldav.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlsldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlsldav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c new file mode 100644 index 0000000..e42a8a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlsldavq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlsldav.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlsldavq (a, b); +} + +/* { dg-final { scan-assembler "vmlsldav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c new file mode 100644 index 0000000..5a18fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b) +{ + return vmlsldavxq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vmlsldavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c new file mode 100644 index 0000000..5d807a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vmlsldavxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vmlsldavxq (a, b); +} + +/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c new file mode 100644 index 0000000..01aa74a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vmovnbq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c new file mode 100644 index 0000000..c7e2c23 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vmovnbq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c new file mode 100644 index 0000000..198b211 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vmovnbq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c new file mode 100644 index 0000000..d5b3162 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vmovnbq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vmovnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c new file mode 100644 index 0000000..07ab334 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vmovntq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vmovntq (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c new file mode 100644 index 0000000..4d2cc31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vmovntq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vmovntq (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c new file mode 100644 index 0000000..d3da582 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vmovntq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vmovntq (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c new file mode 100644 index 0000000..e62154b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vmovntq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vmovntq (a, b); +} + +/* { dg-final { scan-assembler "vmovnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c new file mode 100644 index 0000000..0918063 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmullbq_poly_p16 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.p16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmullbq_poly (a, b); +} + +/* { dg-final { scan-assembler "vmullb.p16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c new file mode 100644 index 0000000..088b319 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmullbq_poly_p8 (a, b); +} + +/* { dg-final { scan-assembler "vmullb.p8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmullbq_poly (a, b); +} + +/* { dg-final { scan-assembler "vmullb.p8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c new file mode 100644 index 0000000..368b73a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vmulltq_poly_p16 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.p16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vmulltq_poly (a, b); +} + +/* { dg-final { scan-assembler "vmullt.p16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c new file mode 100644 index 0000000..861b7cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vmulltq_poly_p8 (a, b); +} + +/* { dg-final { scan-assembler "vmullt.p8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vmulltq_poly (a, b); +} + +/* { dg-final { scan-assembler "vmullt.p8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c new file mode 100644 index 0000000..845dd82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vmulq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c new file mode 100644 index 0000000..515a30d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vmulq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vmulq (a, b); +} + +/* { dg-final { scan-assembler "vmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c new file mode 100644 index 0000000..1d98916 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b) +{ + return vmulq_n_f16 (a, b); +} + +/* { dg-final { scan-assembler "vmul.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c new file mode 100644 index 0000000..dd75efc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b) +{ + return vmulq_n_f32 (a, b); +} + +/* { dg-final { scan-assembler "vmul.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32_t b) +{ + return vmulq_n (a, b); +} + +/* { dg-final { scan-assembler "vmul.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c new file mode 100644 index 0000000..50d34e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vornq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c new file mode 100644 index 0000000..70e998a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vornq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vornq (a, b); +} + +/* { dg-final { scan-assembler "vorn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c new file mode 100644 index 0000000..c19d622 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vorrq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c new file mode 100644 index 0000000..f547583 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vorrq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vorrq (a, b); +} + +/* { dg-final { scan-assembler "vorr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c new file mode 100644 index 0000000..4eca757 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vorrq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vorr.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c new file mode 100644 index 0000000..037c719 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vorrq_n_s32 (a, 1); +} + +/* { dg-final { scan-assembler "vorr.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c new file mode 100644 index 0000000..2384e62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vorrq_n_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vorr.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c new file mode 100644 index 0000000..0468657 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vorrq_n_u32 (a, 44); +} + +/* { dg-final { scan-assembler "vorr.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c index 1bf77bc..5203f35 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c index 8dd6542..e55608a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c index 67cc654..c894da2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c index 0ab0065..39b1254 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b) uint16x8_t foo1 (uint16x8_t a, uint16_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c index 35ce4eb..ec622cd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b) uint32x4_t foo1 (uint32x4_t a, uint32_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c index f747a7c..723c14b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b) uint8x16_t foo1 (uint8x16_t a, uint8_t b) { - return vqaddq_n (a, b); + return vqaddq (a, b); } /* { dg-final { scan-assembler "vqadd.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c index e5adac2..fa27947 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vqdmulhq_n (a, b); + return vqdmulhq (a, b); } /* { dg-final { scan-assembler "vqdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c index 965bbd8..58dc566 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vqdmulhq_n (a, b); + return vqdmulhq (a, b); } /* { dg-final { scan-assembler "vqdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c index 60d3517..73ea78d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vqdmulhq_n (a, b); + return vqdmulhq (a, b); } /* { dg-final { scan-assembler "vqdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c new file mode 100644 index 0000000..4f61311 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16_t b) +{ + return vqdmullbq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16_t b) +{ + return vqdmullbq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c new file mode 100644 index 0000000..478b84d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32_t b) +{ + return vqdmullbq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32_t b) +{ + return vqdmullbq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c new file mode 100644 index 0000000..f988616 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b) +{ + return vqdmullbq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqdmullbq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c new file mode 100644 index 0000000..06baf2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b) +{ + return vqdmullbq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqdmullbq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c new file mode 100644 index 0000000..143bd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16_t b) +{ + return vqdmulltq_n_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16_t b) +{ + return vqdmulltq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c new file mode 100644 index 0000000..6013021 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32_t b) +{ + return vqdmulltq_n_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32_t b) +{ + return vqdmulltq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c new file mode 100644 index 0000000..f8ad242 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b) +{ + return vqdmulltq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vqdmulltq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c new file mode 100644 index 0000000..c50a9dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b) +{ + return vqdmulltq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vqdmulltq (a, b); +} + +/* { dg-final { scan-assembler "vqdmullt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c new file mode 100644 index 0000000..0d9b25a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqmovnbq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c new file mode 100644 index 0000000..91eedba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqmovnbq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c new file mode 100644 index 0000000..86aed4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqmovnbq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c new file mode 100644 index 0000000..a1e92e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqmovnbq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqmovnbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c new file mode 100644 index 0000000..cb8549b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqmovntq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqmovntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c new file mode 100644 index 0000000..476000d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqmovntq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqmovntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c new file mode 100644 index 0000000..ec98d99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqmovntq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqmovntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c new file mode 100644 index 0000000..20a4fa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqmovntq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqmovntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovnt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c new file mode 100644 index 0000000..2486c5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqmovunbq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovunb.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqmovunbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovunb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c new file mode 100644 index 0000000..aa72dca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqmovunbq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovunb.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqmovunbq (a, b); +} + +/* { dg-final { scan-assembler "vqmovunb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c new file mode 100644 index 0000000..27a60f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqmovuntq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vqmovunt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqmovuntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovunt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c new file mode 100644 index 0000000..8abc08a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqmovuntq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vqmovunt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqmovuntq (a, b); +} + +/* { dg-final { scan-assembler "vqmovunt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c index fdeb2c8..edfc03b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vqrdmulhq_n (a, b); + return vqrdmulhq (a, b); } /* { dg-final { scan-assembler "vqrdmulh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c index 825ef08..7bd8f8d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vqrdmulhq_n (a, b); + return vqrdmulhq (a, b); } /* { dg-final { scan-assembler "vqrdmulh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c index 43c2932..f62ad06 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vqrdmulhq_n (a, b); + return vqrdmulhq (a, b); } /* { dg-final { scan-assembler "vqrdmulh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c index c4f7a2d..4f07c30 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int32_t b) int16x8_t foo1 (int16x8_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c index 8478efa..8eb13a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c index af40991..efbd2d7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int32_t b) int8x16_t foo1 (int8x16_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c index 20fd1bc..74a7a3b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, int32_t b) uint16x8_t foo1 (uint16x8_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c index e235c18..f6a714b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, int32_t b) uint32x4_t foo1 (uint32x4_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c index ecd4a5a..5a71f4c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, int32_t b) uint8x16_t foo1 (uint8x16_t a, int32_t b) { - return vqrshlq_n (a, b); + return vqrshlq (a, b); } /* { dg-final { scan-assembler "vqrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c index 79418d9..1b84675 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a) uint16x8_t foo1 (int16x8_t a) { - return vqshluq_n (a, 7); + return vqshluq (a, 7); } /* { dg-final { scan-assembler "vqshlu.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c index 10e8fa4..8721546 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a) uint32x4_t foo1 (int32x4_t a) { - return vqshluq_n (a, 7); + return vqshluq (a, 7); } /* { dg-final { scan-assembler "vqshlu.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c index 920b1b7..f9e28be 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a) uint8x16_t foo1 (int8x16_t a) { - return vqshluq_n (a, 7); + return vqshluq (a, 7); } /* { dg-final { scan-assembler "vqshlu.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c index 0da54b6..cf66a17 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c index 5db6fee..bab7c54 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c index 96519ae..62cbb96 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c index c735629..f38fe6c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b) uint16x8_t foo1 (uint16x8_t a, uint16_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c index a196593a2..e40bb8a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b) uint32x4_t foo1 (uint32x4_t a, uint32_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c index 981d623..02305b4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b) uint8x16_t foo1 (uint8x16_t a, uint8_t b) { - return vqsubq_n (a, b); + return vqsubq (a, b); } /* { dg-final { scan-assembler "vqsub.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c new file mode 100644 index 0000000..bdcc4ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vrmlaldavhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrmlaldavhq (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c new file mode 100644 index 0000000..5decdf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vrmlaldavhq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ + +uint64_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vrmlaldavhq (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c new file mode 100644 index 0000000..c9e84a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vrmlaldavhxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrmlaldavhxq (a, b); +} + +/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c new file mode 100644 index 0000000..ffcc1a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vrmlsldavhq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrmlsldavhq (a, b); +} + +/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c new file mode 100644 index 0000000..c6abc90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b) +{ + return vrmlsldavhxq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vrmlsldavhxq (a, b); +} + +/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c index bd380f8..a81e2ba 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int32_t b) int16x8_t foo1 (int16x8_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c index 9f7051d..82a77db 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c index 04e3321..63bc48e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int32_t b) int8x16_t foo1 (int8x16_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c index fc3c87d..3c6b3b7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, int32_t b) uint16x8_t foo1 (uint16x8_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c index 937f145..9bbab4e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, int32_t b) uint32x4_t foo1 (uint32x4_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c index 68c967f..aa0cfc9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, int32_t b) uint8x16_t foo1 (uint8x16_t a, int32_t b) { - return vrshlq_n (a, b); + return vrshlq (a, b); } /* { dg-final { scan-assembler "vrshl.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c index 04147e2..f7874c0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a) int16x8_t foo1 (int16x8_t a) { - return vrshrq_n (a, 16); + return vrshrq (a, 16); } /* { dg-final { scan-assembler "vrshr.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c index 4c68cf8..3a1258a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a) int32x4_t foo1 (int32x4_t a) { - return vrshrq_n (a, 32); + return vrshrq (a, 32); } /* { dg-final { scan-assembler "vrshr.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c index 5263272..ecb766c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a) int8x16_t foo1 (int8x16_t a) { - return vrshrq_n (a, 8); + return vrshrq (a, 8); } /* { dg-final { scan-assembler "vrshr.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c index 5952a48..d77ea96 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a) uint16x8_t foo1 (uint16x8_t a) { - return vrshrq_n (a, 16); + return vrshrq (a, 16); } /* { dg-final { scan-assembler "vrshr.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c index 507f2dd..c0c41eb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a) uint32x4_t foo1 (uint32x4_t a) { - return vrshrq_n (a, 32); + return vrshrq (a, 32); } /* { dg-final { scan-assembler "vrshr.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c index ec882da..2e3cf7b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a) uint8x16_t foo1 (uint8x16_t a) { - return vrshrq_n (a, 8); + return vrshrq (a, 8); } /* { dg-final { scan-assembler "vrshr.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c new file mode 100644 index 0000000..8797de0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vshllbq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vshllbq (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c new file mode 100644 index 0000000..9d0b57e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vshllbq_n_s8 (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vshllbq (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c new file mode 100644 index 0000000..24f4f7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vshllbq_n_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vshllbq (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c new file mode 100644 index 0000000..153da94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vshllbq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vshllbq (a, 1); +} + +/* { dg-final { scan-assembler "vshllb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c new file mode 100644 index 0000000..6db513a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vshlltq_n_s16 (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vshlltq (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c new file mode 100644 index 0000000..aec31c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vshlltq_n_s8 (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vshlltq (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c new file mode 100644 index 0000000..df633d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vshlltq_n_u16 (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vshlltq (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c new file mode 100644 index 0000000..ed6dd28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vshlltq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vshlltq (a, 1); +} + +/* { dg-final { scan-assembler "vshllt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c new file mode 100644 index 0000000..646690c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vsubq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vsub.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c new file mode 100644 index 0000000..f011a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vsubq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vsub.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vsubq (a, b); +} + +/* { dg-final { scan-assembler "vsub.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c index 49153b2..ae32f24 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (int16x8_t a, int16_t b) int16x8_t foo1 (int16x8_t a, int16_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c index c337a48..1114b02 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (int32x4_t a, int32_t b) int32x4_t foo1 (int32x4_t a, int32_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c index f3652b1..6cc8aab 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (int8x16_t a, int8_t b) int8x16_t foo1 (int8x16_t a, int8_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c index c2f67d6..449fe23 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (uint16x8_t a, uint16_t b) uint16x8_t foo1 (uint16x8_t a, uint16_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c index c5b5975..842a0df 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (uint32x4_t a, uint32_t b) uint32x4_t foo1 (uint32x4_t a, uint32_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c index 8088ab1..48067f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" @@ -16,7 +17,7 @@ foo (uint8x16_t a, uint8_t b) uint8x16_t foo1 (uint8x16_t a, uint8_t b) { - return vsubq_n (a, b); + return vsubq (a, b); } /* { dg-final { scan-assembler "vsub.i8" } } */ -- cgit v1.1 From 0dad5b336874338fcad2ae0509bbf520a01e353a Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 15:56:35 +0000 Subject: [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. This patch supports following MVE ACLE intrinsics with ternary operands. vabavq_s8, vabavq_s16, vabavq_s32, vbicq_m_n_s16, vbicq_m_n_s32, vbicq_m_n_u16, vbicq_m_n_u32, vcmpeqq_m_f16, vcmpeqq_m_f32, vcvtaq_m_s16_f16, vcvtaq_m_u16_f16, vcvtaq_m_s32_f32, vcvtaq_m_u32_f32, vcvtq_m_f16_s16, vcvtq_m_f16_u16, vcvtq_m_f32_s32, vcvtq_m_f32_u32, vqrshrnbq_n_s16, vqrshrnbq_n_u16, vqrshrnbq_n_s32, vqrshrnbq_n_u32, vqrshrunbq_n_s16, vqrshrunbq_n_s32, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vshlcq_s8, vshlcq_u8, vshlcq_s16, vshlcq_u16, vshlcq_s32, vshlcq_u32, vabavq_s8, vabavq_s16, vabavq_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for ternary operands. (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vabavq_s8): Define macro. (vabavq_s16): Likewise. (vabavq_s32): Likewise. (vbicq_m_n_s16): Likewise. (vbicq_m_n_s32): Likewise. (vbicq_m_n_u16): Likewise. (vbicq_m_n_u32): Likewise. (vcmpeqq_m_f16): Likewise. (vcmpeqq_m_f32): Likewise. (vcvtaq_m_s16_f16): Likewise. (vcvtaq_m_u16_f16): Likewise. (vcvtaq_m_s32_f32): Likewise. (vcvtaq_m_u32_f32): Likewise. (vcvtq_m_f16_s16): Likewise. (vcvtq_m_f16_u16): Likewise. (vcvtq_m_f32_s32): Likewise. (vcvtq_m_f32_u32): Likewise. (vqrshrnbq_n_s16): Likewise. (vqrshrnbq_n_u16): Likewise. (vqrshrnbq_n_s32): Likewise. (vqrshrnbq_n_u32): Likewise. (vqrshrunbq_n_s16): Likewise. (vqrshrunbq_n_s32): Likewise. (vrmlaldavhaq_s32): Likewise. (vrmlaldavhaq_u32): Likewise. (vshlcq_s8): Likewise. (vshlcq_u8): Likewise. (vshlcq_s16): Likewise. (vshlcq_u16): Likewise. (vshlcq_s32): Likewise. (vshlcq_u32): Likewise. (vabavq_u8): Likewise. (vabavq_u16): Likewise. (vabavq_u32): Likewise. (__arm_vabavq_s8): Define intrinsic. (__arm_vabavq_s16): Likewise. (__arm_vabavq_s32): Likewise. (__arm_vabavq_u8): Likewise. (__arm_vabavq_u16): Likewise. (__arm_vabavq_u32): Likewise. (__arm_vbicq_m_n_s16): Likewise. (__arm_vbicq_m_n_s32): Likewise. (__arm_vbicq_m_n_u16): Likewise. (__arm_vbicq_m_n_u32): Likewise. (__arm_vqrshrnbq_n_s16): Likewise. (__arm_vqrshrnbq_n_u16): Likewise. (__arm_vqrshrnbq_n_s32): Likewise. (__arm_vqrshrnbq_n_u32): Likewise. (__arm_vqrshrunbq_n_s16): Likewise. (__arm_vqrshrunbq_n_s32): Likewise. (__arm_vrmlaldavhaq_s32): Likewise. (__arm_vrmlaldavhaq_u32): Likewise. (__arm_vshlcq_s8): Likewise. (__arm_vshlcq_u8): Likewise. (__arm_vshlcq_s16): Likewise. (__arm_vshlcq_u16): Likewise. (__arm_vshlcq_s32): Likewise. (__arm_vshlcq_u32): Likewise. (__arm_vcmpeqq_m_f16): Likewise. (__arm_vcmpeqq_m_f32): Likewise. (__arm_vcvtaq_m_s16_f16): Likewise. (__arm_vcvtaq_m_u16_f16): Likewise. (__arm_vcvtaq_m_s32_f32): Likewise. (__arm_vcvtaq_m_u32_f32): Likewise. (__arm_vcvtq_m_f16_s16): Likewise. (__arm_vcvtq_m_f16_u16): Likewise. (__arm_vcvtq_m_f32_s32): Likewise. (__arm_vcvtq_m_f32_u32): Likewise. (vcvtaq_m): Define polymorphic variant. (vcvtq_m): Likewise. (vabavq): Likewise. (vshlcq): Likewise. (vbicq_m_n): Likewise. (vqrshrnbq_n): Likewise. (vqrshrunbq_n): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer. (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. * config/arm/mve.md (VBICQ_M_N): Define iterator. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (mve_vbicq_m_n_): Define RTL pattern. (mve_vcmpeqq_m_f): Likewise. (mve_vcvtaq_m_): Likewise. (mve_vcvtq_m_to_f_): Likewise. (mve_vqrshrnbq_n_): Likewise. (mve_vqrshrunbq_n_s): Likewise. (mve_vrmlaldavhaq_v4si): Likewise. (mve_vabavq_): Likewise. (mve_vshlcq_): Likewise. (mve_vshlcq_): Likewise. (mve_vshlcq_vec_): Define RTL expand. (mve_vshlcq_carry_): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise. --- gcc/ChangeLog | 129 +++++ gcc/config/arm/arm-builtins.c | 90 ++++ gcc/config/arm/arm_mve.h | 449 +++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 564 +++++++++++---------- gcc/config/arm/mve.md | 187 ++++++- gcc/testsuite/ChangeLog | 39 ++ .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + 40 files changed, 1925 insertions(+), 295 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index af2a867..508b104 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,135 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): + Define qualifier for ternary operands. + (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vabavq_s8): Define macro. + (vabavq_s16): Likewise. + (vabavq_s32): Likewise. + (vbicq_m_n_s16): Likewise. + (vbicq_m_n_s32): Likewise. + (vbicq_m_n_u16): Likewise. + (vbicq_m_n_u32): Likewise. + (vcmpeqq_m_f16): Likewise. + (vcmpeqq_m_f32): Likewise. + (vcvtaq_m_s16_f16): Likewise. + (vcvtaq_m_u16_f16): Likewise. + (vcvtaq_m_s32_f32): Likewise. + (vcvtaq_m_u32_f32): Likewise. + (vcvtq_m_f16_s16): Likewise. + (vcvtq_m_f16_u16): Likewise. + (vcvtq_m_f32_s32): Likewise. + (vcvtq_m_f32_u32): Likewise. + (vqrshrnbq_n_s16): Likewise. + (vqrshrnbq_n_u16): Likewise. + (vqrshrnbq_n_s32): Likewise. + (vqrshrnbq_n_u32): Likewise. + (vqrshrunbq_n_s16): Likewise. + (vqrshrunbq_n_s32): Likewise. + (vrmlaldavhaq_s32): Likewise. + (vrmlaldavhaq_u32): Likewise. + (vshlcq_s8): Likewise. + (vshlcq_u8): Likewise. + (vshlcq_s16): Likewise. + (vshlcq_u16): Likewise. + (vshlcq_s32): Likewise. + (vshlcq_u32): Likewise. + (vabavq_u8): Likewise. + (vabavq_u16): Likewise. + (vabavq_u32): Likewise. + (__arm_vabavq_s8): Define intrinsic. + (__arm_vabavq_s16): Likewise. + (__arm_vabavq_s32): Likewise. + (__arm_vabavq_u8): Likewise. + (__arm_vabavq_u16): Likewise. + (__arm_vabavq_u32): Likewise. + (__arm_vbicq_m_n_s16): Likewise. + (__arm_vbicq_m_n_s32): Likewise. + (__arm_vbicq_m_n_u16): Likewise. + (__arm_vbicq_m_n_u32): Likewise. + (__arm_vqrshrnbq_n_s16): Likewise. + (__arm_vqrshrnbq_n_u16): Likewise. + (__arm_vqrshrnbq_n_s32): Likewise. + (__arm_vqrshrnbq_n_u32): Likewise. + (__arm_vqrshrunbq_n_s16): Likewise. + (__arm_vqrshrunbq_n_s32): Likewise. + (__arm_vrmlaldavhaq_s32): Likewise. + (__arm_vrmlaldavhaq_u32): Likewise. + (__arm_vshlcq_s8): Likewise. + (__arm_vshlcq_u8): Likewise. + (__arm_vshlcq_s16): Likewise. + (__arm_vshlcq_u16): Likewise. + (__arm_vshlcq_s32): Likewise. + (__arm_vshlcq_u32): Likewise. + (__arm_vcmpeqq_m_f16): Likewise. + (__arm_vcmpeqq_m_f32): Likewise. + (__arm_vcvtaq_m_s16_f16): Likewise. + (__arm_vcvtaq_m_u16_f16): Likewise. + (__arm_vcvtaq_m_s32_f32): Likewise. + (__arm_vcvtaq_m_u32_f32): Likewise. + (__arm_vcvtq_m_f16_s16): Likewise. + (__arm_vcvtq_m_f16_u16): Likewise. + (__arm_vcvtq_m_f32_s32): Likewise. + (__arm_vcvtq_m_f32_u32): Likewise. + (vcvtaq_m): Define polymorphic variant. + (vcvtq_m): Likewise. + (vabavq): Likewise. + (vshlcq): Likewise. + (vbicq_m_n): Likewise. + (vqrshrnbq_n): Likewise. + (vqrshrunbq_n): Likewise. + * config/arm/arm_mve_builtins.def + (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer. + (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. + * config/arm/mve.md (VBICQ_M_N): Define iterator. + (VCVTAQ_M): Likewise. + (VCVTQ_M_TO_F): Likewise. + (VQRSHRNBQ_N): Likewise. + (VABAVQ): Likewise. + (VSHLCQ): Likewise. + (VRMLALDAVHAQ): Likewise. + (mve_vbicq_m_n_): Define RTL pattern. + (mve_vcmpeqq_m_f): Likewise. + (mve_vcvtaq_m_): Likewise. + (mve_vcvtq_m_to_f_): Likewise. + (mve_vqrshrnbq_n_): Likewise. + (mve_vqrshrunbq_n_s): Likewise. + (mve_vrmlaldavhaq_v4si): Likewise. + (mve_vabavq_): Likewise. + (mve_vshlcq_): Likewise. + (mve_vshlcq_): Likewise. + (mve_vshlcq_vec_): Define RTL expand. + (mve_vshlcq_carry_): Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vqmovntq_u16): Define macro. (vqmovnbq_u16): Likewise. (vmulltq_poly_p8): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index afccac0..af4f3b6 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -433,6 +433,96 @@ arm_binop_unone_unone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define BINOP_UNONE_UNONE_NONE_QUALIFIERS \ (arm_binop_unone_unone_none_qualifiers) +static enum arm_type_qualifiers +arm_ternop_unone_unone_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_immediate }; +#define TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS \ + (arm_ternop_unone_unone_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none }; +#define TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS \ + (arm_ternop_unone_unone_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none, qualifier_unsigned, + qualifier_immediate }; +#define TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS \ + (arm_ternop_unone_none_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate }; +#define TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS \ + (arm_ternop_none_none_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, + qualifier_immediate }; +#define TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS \ + (arm_ternop_unone_unone_none_imm_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, + qualifier_unsigned }; +#define TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ + (arm_ternop_unone_unone_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned }; +#define TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_ternop_unone_unone_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned }; +#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_ternop_unone_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate }; +#define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \ + (arm_ternop_none_none_none_imm_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned }; +#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_ternop_none_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_immediate, qualifier_unsigned }; +#define TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS \ + (arm_ternop_none_none_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_unsigned }; +#define TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS \ + (arm_ternop_none_none_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned }; +#define TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ + (arm_ternop_unone_unone_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; +#define TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS \ + (arm_ternop_none_none_none_none_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index db5e472..c15bb8b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -742,6 +742,40 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvttq_f16_f32(__a, __b) __arm_vcvttq_f16_f32(__a, __b) #define vcvtbq_f16_f32(__a, __b) __arm_vcvtbq_f16_f32(__a, __b) #define vaddlvaq_s32(__a, __b) __arm_vaddlvaq_s32(__a, __b) +#define vabavq_s8(__a, __b, __c) __arm_vabavq_s8(__a, __b, __c) +#define vabavq_s16(__a, __b, __c) __arm_vabavq_s16(__a, __b, __c) +#define vabavq_s32(__a, __b, __c) __arm_vabavq_s32(__a, __b, __c) +#define vbicq_m_n_s16(__a, __imm, __p) __arm_vbicq_m_n_s16(__a, __imm, __p) +#define vbicq_m_n_s32(__a, __imm, __p) __arm_vbicq_m_n_s32(__a, __imm, __p) +#define vbicq_m_n_u16(__a, __imm, __p) __arm_vbicq_m_n_u16(__a, __imm, __p) +#define vbicq_m_n_u32(__a, __imm, __p) __arm_vbicq_m_n_u32(__a, __imm, __p) +#define vcmpeqq_m_f16(__a, __b, __p) __arm_vcmpeqq_m_f16(__a, __b, __p) +#define vcmpeqq_m_f32(__a, __b, __p) __arm_vcmpeqq_m_f32(__a, __b, __p) +#define vcvtaq_m_s16_f16(__inactive, __a, __p) __arm_vcvtaq_m_s16_f16(__inactive, __a, __p) +#define vcvtaq_m_u16_f16(__inactive, __a, __p) __arm_vcvtaq_m_u16_f16(__inactive, __a, __p) +#define vcvtaq_m_s32_f32(__inactive, __a, __p) __arm_vcvtaq_m_s32_f32(__inactive, __a, __p) +#define vcvtaq_m_u32_f32(__inactive, __a, __p) __arm_vcvtaq_m_u32_f32(__inactive, __a, __p) +#define vcvtq_m_f16_s16(__inactive, __a, __p) __arm_vcvtq_m_f16_s16(__inactive, __a, __p) +#define vcvtq_m_f16_u16(__inactive, __a, __p) __arm_vcvtq_m_f16_u16(__inactive, __a, __p) +#define vcvtq_m_f32_s32(__inactive, __a, __p) __arm_vcvtq_m_f32_s32(__inactive, __a, __p) +#define vcvtq_m_f32_u32(__inactive, __a, __p) __arm_vcvtq_m_f32_u32(__inactive, __a, __p) +#define vqrshrnbq_n_s16(__a, __b, __imm) __arm_vqrshrnbq_n_s16(__a, __b, __imm) +#define vqrshrnbq_n_u16(__a, __b, __imm) __arm_vqrshrnbq_n_u16(__a, __b, __imm) +#define vqrshrnbq_n_s32(__a, __b, __imm) __arm_vqrshrnbq_n_s32(__a, __b, __imm) +#define vqrshrnbq_n_u32(__a, __b, __imm) __arm_vqrshrnbq_n_u32(__a, __b, __imm) +#define vqrshrunbq_n_s16(__a, __b, __imm) __arm_vqrshrunbq_n_s16(__a, __b, __imm) +#define vqrshrunbq_n_s32(__a, __b, __imm) __arm_vqrshrunbq_n_s32(__a, __b, __imm) +#define vrmlaldavhaq_s32(__a, __b, __c) __arm_vrmlaldavhaq_s32(__a, __b, __c) +#define vrmlaldavhaq_u32(__a, __b, __c) __arm_vrmlaldavhaq_u32(__a, __b, __c) +#define vshlcq_s8(__a, __b, __imm) __arm_vshlcq_s8(__a, __b, __imm) +#define vshlcq_u8(__a, __b, __imm) __arm_vshlcq_u8(__a, __b, __imm) +#define vshlcq_s16(__a, __b, __imm) __arm_vshlcq_s16(__a, __b, __imm) +#define vshlcq_u16(__a, __b, __imm) __arm_vshlcq_u16(__a, __b, __imm) +#define vshlcq_s32(__a, __b, __imm) __arm_vshlcq_s32(__a, __b, __imm) +#define vshlcq_u32(__a, __b, __imm) __arm_vshlcq_u32(__a, __b, __imm) +#define vabavq_u8(__a, __b, __c) __arm_vabavq_u8(__a, __b, __c) +#define vabavq_u16(__a, __b, __c) __arm_vabavq_u16(__a, __b, __c) +#define vabavq_u32(__a, __b, __c) __arm_vabavq_u32(__a, __b, __c) #endif __extension__ extern __inline void @@ -4485,6 +4519,186 @@ __arm_vaddlvaq_s32 (int64_t __a, int32x4_t __b) return __builtin_mve_vaddlvaq_sv4si (__a, __b); } +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_s8 (uint32_t __a, int8x16_t __b, int8x16_t __c) +{ + return __builtin_mve_vabavq_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_s16 (uint32_t __a, int16x8_t __b, int16x8_t __c) +{ + return __builtin_mve_vabavq_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_s32 (uint32_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vabavq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return __builtin_mve_vabavq_uv16qi(__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return __builtin_mve_vabavq_uv8hi(__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return __builtin_mve_vabavq_uv4si(__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_n_sv8hi (__a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_n_sv4si (__a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_n_uv8hi (__a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_n_uv4si (__a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) +{ + return __builtin_mve_vqrshrnbq_n_sv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) +{ + return __builtin_mve_vqrshrnbq_n_uv8hi (__a, __b, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) +{ + return __builtin_mve_vqrshrnbq_n_sv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) +{ + return __builtin_mve_vqrshrnbq_n_uv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) +{ + return __builtin_mve_vqrshrunbq_n_sv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) +{ + return __builtin_mve_vqrshrunbq_n_sv4si (__a, __b, __imm); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vrmlaldavhaq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhaq_u32 (uint64_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return __builtin_mve_vrmlaldavhaq_uv4si (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_s8 (int8x16_t __a, uint32_t * __b, const int __imm) +{ + int8x16_t __res = __builtin_mve_vshlcq_vec_sv16qi (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_sv16qi (__a, *__b, __imm); + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_u8 (uint8x16_t __a, uint32_t * __b, const int __imm) +{ + uint8x16_t __res = __builtin_mve_vshlcq_vec_uv16qi (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_uv16qi (__a, *__b, __imm); + return __res; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_s16 (int16x8_t __a, uint32_t * __b, const int __imm) +{ + int16x8_t __res = __builtin_mve_vshlcq_vec_sv8hi (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_sv8hi (__a, *__b, __imm); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_u16 (uint16x8_t __a, uint32_t * __b, const int __imm) +{ + uint16x8_t __res = __builtin_mve_vshlcq_vec_uv8hi (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_uv8hi (__a, *__b, __imm); + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_s32 (int32x4_t __a, uint32_t * __b, const int __imm) +{ + int32x4_t __res = __builtin_mve_vshlcq_vec_sv4si (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_sv4si (__a, *__b, __imm); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_u32 (uint32x4_t __a, uint32_t * __b, const int __imm) +{ + uint32x4_t __res = __builtin_mve_vshlcq_vec_uv4si (__a, *__b, __imm); + *__b = __builtin_mve_vshlcq_carry_uv4si (__a, *__b, __imm); + return __res; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -5443,6 +5657,76 @@ __arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); } +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p); +} + #endif enum { @@ -6033,25 +6317,26 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) -#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) - -#define vcmpgtq_n(p0,p1) __arm_vcmpgtq_n(p0,p1) -#define __arm_vcmpgtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) +#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) +#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) #define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -6676,7 +6961,60 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#else /* MVE Interger. srinath*/ +#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) +#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) +#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) +#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) +#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vcvtaq_m(p0,p1,p2) __arm_vcvtaq_m(p0,p1,p2) +#define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vcvtq_m(p0,p1,p2) __arm_vcvtq_m(p0,p1,p2) +#define __arm_vcvtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcvtq_m_f32_u32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -7653,6 +7991,77 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +#define vabavq(p0,p1,p2) __arm_vabavq(p0,p1,p2) +#define __arm_vabavq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabavq_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabavq_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabavq_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabavq_u8 (__p0, __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabavq_u16 (__p0, __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabavq_u32 (__p0, __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) +#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vrmlaldavhaq(p0,p1,p2) __arm_vrmlaldavhaq(p0,p1,p2) +#define __arm_vrmlaldavhaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) +#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + +#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) +#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) +#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) +#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 7129b99..3ac9630 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -18,276 +18,294 @@ along with GCC; see the file COPYING3. If not see . */ -VAR5(STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) -VAR2(UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) -VAR1(UNOP_NONE_NONE, vrev32q_f, v8hf) -VAR1(UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) -VAR1(UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) -VAR2(UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) -VAR2(UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) -VAR3(UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) -VAR3(UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) -VAR2(UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) -VAR2(UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) -VAR2(UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) -VAR2(UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) -VAR2(UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) -VAR2(UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) -VAR2(UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) -VAR2(UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) -VAR2(UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) -VAR1(UNOP_SNONE_SNONE, vrev16q_s, v16qi) -VAR1(UNOP_SNONE_SNONE, vaddlvq_s, v4si) -VAR3(UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) -VAR3(UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) -VAR3(UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) -VAR3(UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) -VAR3(UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) -VAR2(UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) -VAR2(UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) -VAR2(UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) -VAR2(UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) -VAR2(UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) -VAR2(UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) -VAR2(UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) -VAR2(UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) -VAR2(UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) -VAR1(UNOP_UNONE_UNONE, vrev16q_u, v16qi) -VAR1(UNOP_UNONE_UNONE, vaddlvq_u, v4si) -VAR1(UNOP_UNONE_UNONE, vctp16q, hi) -VAR1(UNOP_UNONE_UNONE, vctp32q, hi) -VAR1(UNOP_UNONE_UNONE, vctp64q, hi) -VAR1(UNOP_UNONE_UNONE, vctp8q, hi) -VAR1(UNOP_UNONE_UNONE, vpnot, hi) -VAR2(BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) -VAR2(BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) -VAR2(BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) -VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) -VAR4(BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) -VAR4(BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) -VAR3(BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) -VAR1(BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) -VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si) -VAR3(BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_UNONE, vqmovntq_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_UNONE, vqmovnbq_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_UNONE, vmulltq_poly_p, v16qi, v8hi) -VAR2(BINOP_UNONE_UNONE_UNONE, vmullbq_poly_p, v16qi, v8hi) -VAR2(BINOP_UNONE_UNONE_UNONE, vmovntq_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_UNONE, vmovnbq_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_UNONE, vmlaldavq_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_NONE, vqmovuntq_s, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_NONE, vqmovunbq_s, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) -VAR2(BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) -VAR2(BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) -VAR2(BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) -VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) -VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vqmovnbq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_n_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_n_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vorrq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vornq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmulq_n_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmulq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmovntq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vmovnbq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vmlsldavxq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vmlsldavq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vmlaldavxq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vmlaldavq_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_NONE, vminnmvq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vminnmq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vminnmavq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vminnmaq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmaxnmvq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmaxnmq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmaxnmavq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vmaxnmaq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, veorq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vbicq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vandq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vaddq_n_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_NONE, vabdq_f, v8hf, v4sf) -VAR2(BINOP_NONE_NONE_IMM, vshlltq_n_s, v16qi, v8hi) -VAR2(BINOP_NONE_NONE_IMM, vshllbq_n_s, v16qi, v8hi) -VAR2(BINOP_NONE_NONE_IMM, vorrq_n_s, v8hi, v4si) -VAR2(BINOP_NONE_NONE_IMM, vbicq_n_s, v8hi, v4si) -VAR1(BINOP_UNONE_UNONE_UNONE, vrmlaldavhq_u, v4si) -VAR1(BINOP_UNONE_UNONE_UNONE, vctp8q_m, hi) -VAR1(BINOP_UNONE_UNONE_UNONE, vctp64q_m, hi) -VAR1(BINOP_UNONE_UNONE_UNONE, vctp32q_m, hi) -VAR1(BINOP_UNONE_UNONE_UNONE, vctp16q_m, hi) -VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvaq_u, v4si) -VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhxq_s, v4si) -VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhq_s, v4si) -VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhxq_s, v4si) -VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si) -VAR1(BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf) -VAR1(BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf) -VAR1(BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si) +VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) +VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) +VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) +VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi) +VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si) +VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) +VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) +VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) +VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) +VAR1 (UNOP_UNONE_UNONE, vctp16q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp32q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp64q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp8q, hi) +VAR1 (UNOP_UNONE_UNONE, vpnot, hi) +VAR2 (BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) +VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) +VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) +VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) +VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) +VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) +VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_UNONE, vqmovntq_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_UNONE, vqmovnbq_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_UNONE, vmulltq_poly_p, v16qi, v8hi) +VAR2 (BINOP_UNONE_UNONE_UNONE, vmullbq_poly_p, v16qi, v8hi) +VAR2 (BINOP_UNONE_UNONE_UNONE, vmovntq_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_UNONE, vmovnbq_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_UNONE, vmlaldavq_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_NONE, vqmovuntq_s, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_NONE, vqmovunbq_s, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) +VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) +VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) +VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vqmovnbq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vqdmulltq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vqdmulltq_n_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vqdmullbq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vqdmullbq_n_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vorrq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vornq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmulq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmulq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmovntq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vmovnbq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vmlsldavxq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vmlsldavq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vmlaldavxq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vmlaldavq_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_NONE, vminnmvq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vminnmq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vminnmavq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vminnmaq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmaxnmvq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmaxnmq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmaxnmavq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vmaxnmaq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, veorq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vbicq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vandq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vaddq_n_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vabdq_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_IMM, vshlltq_n_s, v16qi, v8hi) +VAR2 (BINOP_NONE_NONE_IMM, vshllbq_n_s, v16qi, v8hi) +VAR2 (BINOP_NONE_NONE_IMM, vorrq_n_s, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_IMM, vbicq_n_s, v8hi, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vrmlaldavhq_u, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vctp8q_m, hi) +VAR1 (BINOP_UNONE_UNONE_UNONE, vctp64q_m, hi) +VAR1 (BINOP_UNONE_UNONE_UNONE, vctp32q_m, hi) +VAR1 (BINOP_UNONE_UNONE_UNONE, vctp16q_m, hi) +VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvaq_u, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vrmlsldavhxq_s, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vrmlsldavhq_s, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vrmlaldavhxq_s, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf) +VAR1 (BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf) +VAR1 (BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vbicq_m_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vbicq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrnbq_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrnbq_n_u, v8hi, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) +VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) +VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf) +VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_NONE, vabavq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vabavq_u, v16qi, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtaq_m_u, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtaq_m_s, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 24fb816..3cdb2e7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -85,7 +85,11 @@ VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P - VMULLBQ_POLY_P]) + VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F + VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U + VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S + VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U + VRMLALDAVHAQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -146,7 +150,12 @@ (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s") (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u") - (VRMLALDAVHQ_S "s")]) + (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u") + (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s") + (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s") + (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u") + (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s") + (VSHLCQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -241,6 +250,13 @@ (define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U]) (define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S]) (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) +(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U]) +(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U]) +(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U]) +(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S]) +(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U]) +(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U]) +(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -3057,3 +3073,170 @@ "vrmlaldavh.32 %Q0, %R0, %q1, %q2" [(set_attr "type" "mve_move") ]) + +;; +;; [vbicq_m_n_s, vbicq_m_n_u]) +;; +(define_insn "mve_vbicq_m_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VBICQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vbict.i%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vcmpeqq_m_f]) +;; +(define_insn "mve_vcmpeqq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPEQQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# eq, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vcvtaq_m_u, vcvtaq_m_s]) +;; +(define_insn "mve_vcvtaq_m_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTAQ_M)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtat.%#.f%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) +;; +(define_insn "mve_vcvtq_m_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTQ_M_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtt.f%#.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vqrshrnbq_n_u, vqrshrnbq_n_s]) +;; +(define_insn "mve_vqrshrnbq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQRSHRNBQ_N)) + ] + "TARGET_HAVE_MVE" + "vqrshrnb.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) +;; +;; [vqrshrunbq_n_s]) +;; +(define_insn "mve_vqrshrunbq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQRSHRUNBQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqrshrunb.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) +;; +;; [vrmlaldavhaq_s vrmlaldavhaq_u]) +;; +(define_insn "mve_vrmlaldavhaq_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w")] + VRMLALDAVHAQ)) + ] + "TARGET_HAVE_MVE" + "vrmlaldavha.32 %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabavq_s, vabavq_u]) +;; +(define_insn "mve_vabavq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VABAVQ)) + ] + "TARGET_HAVE_MVE" + "vabav.%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshlcq_u vshlcq_s] +;; +(define_expand "mve_vshlcq_vec_" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_32") + (unspec:MVE_2 [(const_int 0)] VSHLCQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (SImode); + emit_insn(gen_mve_vshlcq_(operands[0], ignore_wb, operands[1], + operands[2], operands[3])); + DONE; +}) + +(define_expand "mve_vshlcq_carry_" + [(match_operand:SI 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_32") + (unspec:MVE_2 [(const_int 0)] VSHLCQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (mode); + emit_insn(gen_mve_vshlcq_(ignore_vec, operands[0], operands[1], + operands[2], operands[3])); + DONE; +}) + +(define_insn "mve_vshlcq_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") + (match_operand:SI 3 "s_register_operand" "1") + (match_operand:SI 4 "mve_imm_32" "Rf")] + VSHLCQ)) + (set (match_operand:SI 1 "s_register_operand" "=r") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4)] + VSHLCQ))] + "TARGET_HAVE_MVE" + "vshlc %q0, %1, %4") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5cc2c04..15e7d6d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,45 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise. + +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c new file mode 100644 index 0000000..0898103 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int16x8_t b, int16x8_t c) +{ + return vabavq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s16" } } */ + +uint32_t +foo1 (uint32_t a, int16x8_t b, int16x8_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c new file mode 100644 index 0000000..5d92016 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b, int32x4_t c) +{ + return vabavq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b, int32x4_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c new file mode 100644 index 0000000..0cfcbc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int8x16_t b, int8x16_t c) +{ + return vabavq_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s8" } } */ + +uint32_t +foo1 (uint32_t a, int8x16_t b, int8x16_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c new file mode 100644 index 0000000..08b75d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, uint16x8_t c) +{ + return vabavq_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, uint16x8_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c new file mode 100644 index 0000000..d6099b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, uint32x4_t c) +{ + return vabavq_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, uint32x4_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c new file mode 100644 index 0000000..948ffbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, uint8x16_t c) +{ + return vabavq_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, uint8x16_t c) +{ + return vabavq (a, b, c); +} + +/* { dg-final { scan-assembler "vabav.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c new file mode 100644 index 0000000..f70e5a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vbicq_m_n_s16 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vbicq_m_n (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c new file mode 100644 index 0000000..f41169d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vbicq_m_n_s32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vbicq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c new file mode 100644 index 0000000..add8a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vbicq_m_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vbicq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c new file mode 100644 index 0000000..fa53e33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vbicq_m_n_u32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vbicq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c new file mode 100644 index 0000000..dbe2a5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c new file mode 100644 index 0000000..8947375 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c new file mode 100644 index 0000000..e9aa0e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_m_s16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c new file mode 100644 index 0000000..fb5b8c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_m_s32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c new file mode 100644 index 0000000..0193a09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_m_u16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c new file mode 100644 index 0000000..4233fc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_m_u32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c new file mode 100644 index 0000000..b013a77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_f16_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c new file mode 100644 index 0000000..75aa4c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_f16_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c new file mode 100644 index 0000000..df44944 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_f32_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c new file mode 100644 index 0000000..bea45f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_f32_u32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c new file mode 100644 index 0000000..64dff62 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqrshrnbq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c new file mode 100644 index 0000000..371b476 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqrshrnbq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c new file mode 100644 index 0000000..c0849b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqrshrnbq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c new file mode 100644 index 0000000..e70c1dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqrshrnbq_n_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c new file mode 100644 index 0000000..97e2570 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqrshrunbq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqrshrunbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c new file mode 100644 index 0000000..fe9a42c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqrshrunbq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqrshrunbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c new file mode 100644 index 0000000..d86dbb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlaldavhaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlaldavhaq (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c new file mode 100644 index 0000000..776d860 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, uint32x4_t c) +{ + return vrmlaldavhaq_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, uint32x4_t c) +{ + return vrmlaldavhaq (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c new file mode 100644 index 0000000..27dbcce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, uint32_t * b) +{ + return vshlcq_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +int16x8_t +foo1 (int16x8_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c new file mode 100644 index 0000000..3cd034d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, uint32_t * b) +{ + return vshlcq_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +int32x4_t +foo1 (int32x4_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c new file mode 100644 index 0000000..5e8e92d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, uint32_t * b) +{ + return vshlcq_s8 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +int8x16_t +foo1 (int8x16_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c new file mode 100644 index 0000000..dbb486a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32_t * b) +{ + return vshlcq_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c new file mode 100644 index 0000000..7581bbb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t * b) +{ + return vshlcq_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c new file mode 100644 index 0000000..fa10d06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint32_t * b) +{ + return vshlcq_u8 (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint32_t * b) +{ + return vshlcq (a, b, 1); +} + +/* { dg-final { scan-assembler "vshlc" } } */ -- cgit v1.1 From e4596b66710d398cbddb62499b30c147ebd4696d Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Tue, 17 Mar 2020 14:12:54 +0000 Subject: coroutines, testsuite: Fix single test execution. Invocations of the coro-torture.exp like 'coro-torture.exp=some-test.C' were failing because DEFAULT_CXXFLAGS was undefined. Fixed by defining this locally, if it has no pre-existing global value. --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/coroutines/torture/coro-torture.exp | 14 ++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 15e7d6d..ad4fcb5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Iain Sandoe + + * g++.dg/coroutines/torture/coro-torture.exp: Ensure that + DEFAULT_CXXFLAGS has a value, even if unset by a higher level. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/g++.dg/coroutines/torture/coro-torture.exp b/gcc/testsuite/g++.dg/coroutines/torture/coro-torture.exp index d2463b2..2246f71 100644 --- a/gcc/testsuite/g++.dg/coroutines/torture/coro-torture.exp +++ b/gcc/testsuite/g++.dg/coroutines/torture/coro-torture.exp @@ -3,13 +3,19 @@ load_lib g++-dg.exp load_lib torture-options.exp -global DG_TORTURE_OPTIONS LTO_TORTURE_OPTIONS +global DG_TORTURE_OPTIONS LTO_TORTURE_OPTIONS -dg-init -torture-init +# If a testcase doesn't have special options, use these. +global DEFAULT_CXXFLAGS +if ![info exists DEFAULT_CXXFLAGS] then { + set DEFAULT_CXXFLAGS " -pedantic-errors -Wno-long-long" +} set DEFAULT_COROFLAGS $DEFAULT_CXXFLAGS -lappend DEFAULT_COROFLAGS "-std=c++17" "-fcoroutines" +lappend DEFAULT_COROFLAGS "-fcoroutines" "-std=c++17" + +dg-init +torture-init set-torture-options [concat $DG_TORTURE_OPTIONS $LTO_TORTURE_OPTIONS] -- cgit v1.1 From 1fef0148be4b40660446d79a2b2dc73e89bfbeff Mon Sep 17 00:00:00 2001 From: Ville Voutilainen Date: Tue, 17 Mar 2020 18:43:21 +0200 Subject: Fix the ChangeLog after the __is_assignable/__is_constructible fix --- gcc/cp/ChangeLog | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index d2c062a..0cdbd02 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,17 +1,10 @@ 2020-03-17 Ville Voutilainen - gcc/ - PR c++/94197 - * cp/method.c (assignable_expr): Use cp_unevaluated. + * method.c (assignable_expr): Use cp_unevaluated. (is_xible_helper): Push a non-deferred access check for the stub objects created by assignable_expr and constructible_expr. - testsuite/ - - PR c++/94197 - * g++.dg/ext/pr94197.C: New. - 2020-03-17 Jakub Jelinek * pt.c (tsubst): Fix up duplicated word issue in a diagnostic message. -- cgit v1.1 From cf9c3bff39cf973c5c8621ff44199dcb831193a7 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 17 Mar 2020 15:36:37 +0000 Subject: aarch64: Fix bf16_v(ld|st)n.c failures for big-endian gcc.target/aarch64/advsimd-intrinsics/bf16_vldn.c and gcc.target/aarch64/advsimd-intrinsics/bf16_vstn.c were failing for big-endian targets because the in aarch64_be_ld1 and aarch64_be_st1 had no expansion for the bfloat16 modes. 2020-03-17 Richard Sandiford gcc/ * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. --- gcc/ChangeLog | 4 ++++ gcc/config/aarch64/iterators.md | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 508b104..642954d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-03-17 Richard Sandiford + + * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 95fa3e4..8e43438 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1000,7 +1000,8 @@ (V4HI ".4h") (V8HI ".8h") (V2SI ".2s") (V4SI ".4s") (V2DI ".2d") (V4HF ".4h") - (V8HF ".8h") (V2SF ".2s") + (V8HF ".8h") (V4BF ".4h") + (V8BF ".8h") (V2SF ".2s") (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") -- cgit v1.1 From 58a703f0726b3bb6c5ac8b600369106985906590 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 17 Mar 2020 15:39:42 +0000 Subject: testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c 2020-03-17 Richard Sandiford gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Skip for -fno-fat-lto-objects. Use tabs rather than spaces in the check-function-bodies code. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ad4fcb5..484eef5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-17 Richard Sandiford + + * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Skip for + -fno-fat-lto-objects. Use tabs rather than spaces in the + check-function-bodies code. + 2020-03-17 Iain Sandoe * g++.dg/coroutines/torture/coro-torture.exp: Ensure that diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c index 05c3058..a914680 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { aarch64*-*-* } } } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ /* { dg-require-effective-target aarch64_asm_bf16_ok } */ /* { dg-additional-options "-save-temps -march=armv8.2-a+bf16+nosimd" } */ /* { dg-final { check-function-bodies "**" "" {-O[^0]} } } */ @@ -7,8 +8,8 @@ /* **test_bfcvt: -** bfcvt h0, s0 -** ret +** bfcvt h0, s0 +** ret */ bfloat16_t test_bfcvt (float32_t a) { -- cgit v1.1 From cd0b71242738a1901405f421b352e4f6c30ff7c5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 21:21:16 +0100 Subject: c++: Fix parsing of invalid enum specifiers [PR90995] The testcase shows some accepts-invalid (the ones without alignas) and ice-on-invalid-code (the ones with alignas) cases. If the enum doesn't have an underlying type and is not a definition, the caller retries to parse it as elaborated type specifier. E.g. for enum struct S s it will then pedwarn that elaborated type specifier shouldn't have the struct/class keywords. The problem is if the enum specifier is not followed by { when it has underlying type. In that case we have already called cp_parser_parse_definitely to end the tentative parsing started at the beginning of cp_parser_enum_specifier. But the cp_parser_error (parser, "expected %<;%> or %<{%>"); doesn't emit any error because the whole function is called from yet another tentative parse and the caller starts parsing the elaborated type specifier where the cp_parser_enum_specifier stopped (i.e. after the underlying type token(s)). The ultimate caller than commits the tentative parsing (and even if it wouldn't, it wouldn't know what kind of error to report). I think after seeing enum {,struct,class} : type not being followed by { or ;, there is no reason not to report it right away, as it can't be valid C++, which is what the patch does. Not sure if we shouldn't also return error_mark_node instead of NULL_TREE, so that the caller doesn't try to parse it as elaborated type specifier (the patch doesn't do that right now). Furthermore, while reading the code, I've noticed that parser->colon_corrects_to_scope_p is saved and set to false at the start of the function, but not restored back in some cases. Don't have a testcase where this would be a problem, but it just seems wrong. Either we can in the two spots replace return NULL_TREE; with { type = NULL_TREE; goto out; } or we could perhaps abuse warning_sentinel or create a special class with dtor to clean the flag up. And lastly, I've fixed some formatting issues in the function while reading it. 2020-03-17 Jakub Jelinek PR c++/90995 * parser.c (cp_parser_enum_specifier): Use temp_override for parser->colon_corrects_to_scope_p, replace goto out with return. If scoped enum or enum with underlying type is not followed by { or ;, call cp_parser_commit_to_tentative_parse before calling cp_parser_error and make sure to return error_mark_node instead of NULL_TREE. Formatting fixes. * g++.dg/cpp0x/enum40.C: New test. --- gcc/cp/ChangeLog | 10 +++++++ gcc/cp/parser.c | 52 +++++++++++++++---------------------- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 +++++++++++++++++++ 4 files changed, 62 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 0cdbd02..1db1e09 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2020-03-17 Jakub Jelinek + + PR c++/90995 + * parser.c (cp_parser_enum_specifier): Use temp_override for + parser->colon_corrects_to_scope_p, replace goto out with return. + If scoped enum or enum with underlying type is not followed by + { or ;, call cp_parser_commit_to_tentative_parse before calling + cp_parser_error and make sure to return error_mark_node instead of + NULL_TREE. Formatting fixes. + 2020-03-17 Ville Voutilainen PR c++/94197 diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 58a1bea..26e0236 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -19001,9 +19001,7 @@ cp_parser_enum_specifier (cp_parser* parser) bool is_unnamed = false; tree underlying_type = NULL_TREE; cp_token *type_start_token = NULL; - bool saved_colon_corrects_to_scope_p = parser->colon_corrects_to_scope_p; - - parser->colon_corrects_to_scope_p = false; + temp_override cleanup (parser->colon_corrects_to_scope_p, false); /* Parse tentatively so that we can back up if we don't find a enum-specifier. */ @@ -19043,24 +19041,24 @@ cp_parser_enum_specifier (cp_parser* parser) push_deferring_access_checks (dk_no_check); nested_name_specifier - = cp_parser_nested_name_specifier_opt (parser, - /*typename_keyword_p=*/true, - /*check_dependency_p=*/false, - /*type_p=*/false, - /*is_declaration=*/false); + = cp_parser_nested_name_specifier_opt (parser, + /*typename_keyword_p=*/true, + /*check_dependency_p=*/false, + /*type_p=*/false, + /*is_declaration=*/false); if (nested_name_specifier) { tree name; identifier = cp_parser_identifier (parser); - name = cp_parser_lookup_name (parser, identifier, - enum_type, - /*is_template=*/false, - /*is_namespace=*/false, - /*check_dependency=*/true, - /*ambiguous_decls=*/NULL, - input_location); + name = cp_parser_lookup_name (parser, identifier, + enum_type, + /*is_template=*/false, + /*is_namespace=*/false, + /*check_dependency=*/true, + /*ambiguous_decls=*/NULL, + input_location); if (name && name != error_mark_node) { type = TREE_TYPE (name); @@ -19140,23 +19138,21 @@ cp_parser_enum_specifier (cp_parser* parser) { if (cxx_dialect < cxx11 || (!scoped_enum_p && !underlying_type)) { + if (has_underlying_type) + cp_parser_commit_to_tentative_parse (parser); cp_parser_error (parser, "expected %<{%>"); if (has_underlying_type) - { - type = NULL_TREE; - goto out; - } + return error_mark_node; } /* An opaque-enum-specifier must have a ';' here. */ if ((scoped_enum_p || underlying_type) && cp_lexer_next_token_is_not (parser->lexer, CPP_SEMICOLON)) { + if (has_underlying_type) + cp_parser_commit_to_tentative_parse (parser); cp_parser_error (parser, "expected %<;%> or %<{%>"); if (has_underlying_type) - { - type = NULL_TREE; - goto out; - } + return error_mark_node; } } @@ -19172,9 +19168,7 @@ cp_parser_enum_specifier (cp_parser* parser) push_scope (nested_name_specifier); } else if (TREE_CODE (nested_name_specifier) == NAMESPACE_DECL) - { - push_nested_namespace (nested_name_specifier); - } + push_nested_namespace (nested_name_specifier); } /* Issue an error message if type-definitions are forbidden here. */ @@ -19334,12 +19328,8 @@ cp_parser_enum_specifier (cp_parser* parser) pop_scope (nested_name_specifier); } else if (TREE_CODE (nested_name_specifier) == NAMESPACE_DECL) - { - pop_nested_namespace (nested_name_specifier); - } + pop_nested_namespace (nested_name_specifier); } - out: - parser->colon_corrects_to_scope_p = saved_colon_corrects_to_scope_p; return type; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 484eef5..45fb829 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-17 Jakub Jelinek + + PR c++/90995 + * g++.dg/cpp0x/enum40.C: New test. + 2020-03-17 Richard Sandiford * gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Skip for diff --git a/gcc/testsuite/g++.dg/cpp0x/enum40.C b/gcc/testsuite/g++.dg/cpp0x/enum40.C new file mode 100644 index 0000000..cfdf2a4 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/enum40.C @@ -0,0 +1,26 @@ +// PR c++/90995 +// { dg-do compile { target c++11 } } + +void +foo () +{ + enum : int a alignas; // { dg-error "expected" } +} + +void +bar () +{ + enum : int a; // { dg-error "expected" } +} + +void +baz () +{ + enum class a : int b alignas; // { dg-error "expected" } +} + +void +qux () +{ + enum class a : int b; // { dg-error "expected" } +} -- cgit v1.1 From 046c58907ec85884042d9937ea9c25ef9fe57b1d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 17 Mar 2020 22:32:34 +0100 Subject: c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] The following testcases ICE, because they contain extern variable declarations with incomplete enum types that is later completed and after that those variables are accessed. The ICEs are because the vars then may have incorrect DECL_MODE etc., e.g. in the first case the var has SImode DECL_MODE (the guessed mode for the enum), but the enum then actually has DImode because its enumerators don't fit into unsigned int. The following patch fixes it by using C_TYPE_INCOMPLETE_VARS not just on incomplete struct/union types, but also incomplete enum types. TYPE_VFIELD can't be used as it is TYPE_MIN_VALUE on ENUMERAL_TYPE, thankfully TYPE_LANG_SLOT_1 has been used in the C FE only on FUNCTION_TYPEs. 2020-03-17 Jakub Jelinek PR c/94172 * c-tree.h (C_TYPE_INCOMPLETE_VARS): Define to TYPE_LANG_SLOT_1 instead of TYPE_VFIELD, and support it on {RECORD,UNION,ENUMERAL}_TYPE. (TYPE_ACTUAL_ARG_TYPES): Check that it is only used on FUNCTION_TYPEs. * c-decl.c (pushdecl): Push C_TYPE_INCOMPLETE_VARS also to ENUMERAL_TYPEs. (finish_incomplete_vars): New function, moved from finish_struct. Use relayout_decl instead of layout_decl. (finish_struct): Remove obsolete comment about C_TYPE_INCOMPLETE_VARS being TYPE_VFIELD. Use finish_incomplete_vars. (finish_enum): Clear C_TYPE_INCOMPLETE_VARS. Call finish_incomplete_vars. * c-typeck.c (c_build_qualified_type): Clear C_TYPE_INCOMPLETE_VARS also on ENUMERAL_TYPEs. * gcc.dg/pr94172-1.c: New test. * gcc.dg/pr94172-2.c: New test. --- gcc/c/ChangeLog | 17 ++++++++++++++ gcc/c/c-decl.c | 50 ++++++++++++++++++++++------------------ gcc/c/c-tree.h | 12 ++++++---- gcc/c/c-typeck.c | 3 ++- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/pr94172-1.c | 12 ++++++++++ gcc/testsuite/gcc.dg/pr94172-2.c | 19 +++++++++++++++ 7 files changed, 89 insertions(+), 28 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c (limited to 'gcc') diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 240859e..25f8f5b 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,20 @@ +2020-03-17 Jakub Jelinek + + PR c/94172 + * c-tree.h (C_TYPE_INCOMPLETE_VARS): Define to TYPE_LANG_SLOT_1 + instead of TYPE_VFIELD, and support it on {RECORD,UNION,ENUMERAL}_TYPE. + (TYPE_ACTUAL_ARG_TYPES): Check that it is only used on FUNCTION_TYPEs. + * c-decl.c (pushdecl): Push C_TYPE_INCOMPLETE_VARS also to + ENUMERAL_TYPEs. + (finish_incomplete_vars): New function, moved from finish_struct. Use + relayout_decl instead of layout_decl. + (finish_struct): Remove obsolete comment about C_TYPE_INCOMPLETE_VARS + being TYPE_VFIELD. Use finish_incomplete_vars. + (finish_enum): Clear C_TYPE_INCOMPLETE_VARS. Call + finish_incomplete_vars. + * c-typeck.c (c_build_qualified_type): Clear C_TYPE_INCOMPLETE_VARS + also on ENUMERAL_TYPEs. + 2020-03-16 Jakub Jelinek PR c/94179 diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c index 87a0734..ed5163d 100644 --- a/gcc/c/c-decl.c +++ b/gcc/c/c-decl.c @@ -3312,7 +3312,8 @@ pushdecl (tree x) element = TREE_TYPE (element); element = TYPE_MAIN_VARIANT (element); - if (RECORD_OR_UNION_TYPE_P (element) + if ((RECORD_OR_UNION_TYPE_P (element) + || TREE_CODE (element) == ENUMERAL_TYPE) && (TREE_CODE (x) != TYPE_DECL || TREE_CODE (TREE_TYPE (x)) == ARRAY_TYPE) && !COMPLETE_TYPE_P (element)) @@ -8354,6 +8355,26 @@ field_decl_cmp (const void *x_p, const void *y_p) return 1; } +/* If this structure or union completes the type of any previous + variable declaration, lay it out and output its rtl. */ +static void +finish_incomplete_vars (tree incomplete_vars, bool toplevel) +{ + for (tree x = incomplete_vars; x; x = TREE_CHAIN (x)) + { + tree decl = TREE_VALUE (x); + if (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE) + layout_array_type (TREE_TYPE (decl)); + if (TREE_CODE (decl) != TYPE_DECL) + { + relayout_decl (decl); + if (c_dialect_objc ()) + objc_check_decl (decl); + rest_of_decl_compilation (decl, toplevel, 0); + } + } +} + /* Fill in the fields of a RECORD_TYPE or UNION_TYPE node, T. LOC is the location of the RECORD_TYPE or UNION_TYPE's definition. FIELDLIST is a chain of FIELD_DECL nodes for the fields. @@ -8612,13 +8633,6 @@ finish_struct (location_t loc, tree t, tree fieldlist, tree attributes, warning_at (loc, 0, "union cannot be made transparent"); } - /* Note: C_TYPE_INCOMPLETE_VARS overloads TYPE_VFIELD which is used - in dwarf2out via rest_of_decl_compilation below and means - something totally different. Since we will be clearing - C_TYPE_INCOMPLETE_VARS shortly after we iterate through them, - clear it ahead of time and avoid problems in dwarf2out. Ideally, - C_TYPE_INCOMPLETE_VARS should use some language specific - node. */ tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (t)); for (x = TYPE_MAIN_VARIANT (t); x; x = TYPE_NEXT_VARIANT (x)) { @@ -8639,21 +8653,7 @@ finish_struct (location_t loc, tree t, tree fieldlist, tree attributes, /* Finish debugging output for this type. */ rest_of_type_compilation (t, toplevel); - /* If this structure or union completes the type of any previous - variable declaration, lay it out and output its rtl. */ - for (x = incomplete_vars; x; x = TREE_CHAIN (x)) - { - tree decl = TREE_VALUE (x); - if (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE) - layout_array_type (TREE_TYPE (decl)); - if (TREE_CODE (decl) != TYPE_DECL) - { - layout_decl (decl, 0); - if (c_dialect_objc ()) - objc_check_decl (decl); - rest_of_decl_compilation (decl, toplevel, 0); - } - } + finish_incomplete_vars (incomplete_vars, toplevel); /* If we're inside a function proper, i.e. not file-scope and not still parsing parameters, then arrange for the size of a variable sized type @@ -8932,8 +8932,10 @@ finish_enum (tree enumtype, tree values, tree attributes) TYPE_LANG_SPECIFIC (enumtype) = lt; /* Fix up all variant types of this enum type. */ + tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (enumtype)); for (tem = TYPE_MAIN_VARIANT (enumtype); tem; tem = TYPE_NEXT_VARIANT (tem)) { + C_TYPE_INCOMPLETE_VARS (tem) = NULL_TREE; if (tem == enumtype) continue; TYPE_VALUES (tem) = TYPE_VALUES (enumtype); @@ -8952,6 +8954,8 @@ finish_enum (tree enumtype, tree values, tree attributes) /* Finish debugging output for this type. */ rest_of_type_compilation (enumtype, toplevel); + finish_incomplete_vars (incomplete_vars, toplevel); + /* If this enum is defined inside a struct, add it to struct_types. */ if (warn_cxx_compat diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h index 7122992..364d7e0 100644 --- a/gcc/c/c-tree.h +++ b/gcc/c/c-tree.h @@ -38,9 +38,12 @@ along with GCC; see the file COPYING3. If not see nonzero if the definition of the type has already started. */ #define C_TYPE_BEING_DEFINED(TYPE) TYPE_LANG_FLAG_0 (TYPE) -/* In an incomplete RECORD_TYPE or UNION_TYPE, a list of variable - declarations whose type would be completed by completing that type. */ -#define C_TYPE_INCOMPLETE_VARS(TYPE) TYPE_VFIELD (TYPE) +/* In an incomplete RECORD_TYPE, UNION_TYPE or ENUMERAL_TYPE, a list of + variable declarations whose type would be completed by completing + that type. */ +#define C_TYPE_INCOMPLETE_VARS(TYPE) \ + TYPE_LANG_SLOT_1 (TREE_CHECK4 (TYPE, RECORD_TYPE, UNION_TYPE, \ + QUAL_UNION_TYPE, ENUMERAL_TYPE)) /* In an IDENTIFIER_NODE, nonzero if this identifier is actually a keyword. C_RID_CODE (node) is then the RID_* value of the keyword. */ @@ -108,7 +111,8 @@ along with GCC; see the file COPYING3. If not see /* For FUNCTION_TYPE, a hidden list of types of arguments. The same as TYPE_ARG_TYPES for functions with prototypes, but created for functions without prototypes. */ -#define TYPE_ACTUAL_ARG_TYPES(NODE) TYPE_LANG_SLOT_1 (NODE) +#define TYPE_ACTUAL_ARG_TYPES(NODE) \ + TYPE_LANG_SLOT_1 (FUNCTION_TYPE_CHECK (NODE)) /* For a CONSTRUCTOR, whether some initializer contains a subexpression meaning it is not a constant expression. */ diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index 490d8fc..385bf3a 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -15207,7 +15207,8 @@ c_build_qualified_type (tree type, int type_quals, tree orig_qual_type, : build_qualified_type (type, type_quals)); /* A variant type does not inherit the list of incomplete vars from the type main variant. */ - if (RECORD_OR_UNION_TYPE_P (var_type) + if ((RECORD_OR_UNION_TYPE_P (var_type) + || TREE_CODE (var_type) == ENUMERAL_TYPE) && TYPE_MAIN_VARIANT (var_type) != var_type) C_TYPE_INCOMPLETE_VARS (var_type) = 0; return var_type; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 45fb829..dae22c2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2020-03-17 Jakub Jelinek + PR c/94172 + * gcc.dg/pr94172-1.c: New test. + * gcc.dg/pr94172-2.c: New test. + PR c++/90995 * g++.dg/cpp0x/enum40.C: New test. diff --git a/gcc/testsuite/gcc.dg/pr94172-1.c b/gcc/testsuite/gcc.dg/pr94172-1.c new file mode 100644 index 0000000..12f84af --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94172-1.c @@ -0,0 +1,12 @@ +/* PR c/94172 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern enum E e; +enum E { l = 0x100000000ULL }; + +unsigned long long +foo (void) +{ + return e; +} diff --git a/gcc/testsuite/gcc.dg/pr94172-2.c b/gcc/testsuite/gcc.dg/pr94172-2.c new file mode 100644 index 0000000..bb7b060 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94172-2.c @@ -0,0 +1,19 @@ +/* PR c/94172 */ +/* { dg-do compile } */ +/* { dg-options "-Os -g -fshort-enums" } */ + +extern enum E e; +extern void bar (int a); +enum E { F }; + +void +foo (int a) +{ + int l = e; + if (a) + { + __asm volatile ("nop"); + l = 0; + } + bar (l); +} -- cgit v1.1 From 2e30d3e3e88b6a544074ff89de4974bc5e200e89 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 17 Mar 2020 23:01:04 +0100 Subject: testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector * g++.dg/debug/dwarf2/const2b.C (dg-do): Fix target selector. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dae22c2..775837d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-17 Uroš Bizjak + + * g++.dg/debug/dwarf2/const2b.C (dg-do): Fix target selector. + 2020-03-17 Jakub Jelinek PR c/94172 diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C b/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C index 3ad1c08..681ad72 100644 --- a/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C +++ b/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target i386*-*-* x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-O -gdwarf-2 -dA -msse" } */ /* { dg-require-effective-target sse } */ /* { dg-final { scan-assembler "DW_AT_const_value" } } */ -- cgit v1.1 From 3b2cc34369ae1a774f0c910454999613c320bfe6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 18 Mar 2020 00:16:17 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index c73081a..584bf4b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200317 +20200318 -- cgit v1.1 From 80616e5b7a5caf6f41210c9451a32de2fd64528e Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 17 Mar 2020 05:45:02 -0400 Subject: c++: Fix comment typo. --- gcc/cp/constraint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc index 697ed67..2176978 100644 --- a/gcc/cp/constraint.cc +++ b/gcc/cp/constraint.cc @@ -2536,7 +2536,7 @@ satisfy_atom (tree t, tree args, subst_info info) location_t loc = cp_expr_loc_or_input_loc (expr); - /* [17.4.1.2] ... lvalue-to-value conversion is performed as necessary, + /* [17.4.1.2] ... lvalue-to-rvalue conversion is performed as necessary, and EXPR shall be a constant expression of type bool. */ result = force_rvalue (result, info.complain); if (result == error_mark_node) -- cgit v1.1 From 52b3aa8be18938486065f5f2a23553b134a10a81 Mon Sep 17 00:00:00 2001 From: Alexey Neyman Date: Sat, 14 Mar 2020 17:05:36 -0700 Subject: dwarf: Generate DIEs for external variables with -g1 [93751] -g1 is described in the manual to generate debug info for functions and external variables. It does that for older debugging formats but not for DWARF. This change brings DWARF in line with the rest of the debugging formats and with the manual. gcc/ChangeLog 2020-03-17 Alexey Neyman PR debug/93751 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if the debug level is terse and the declaration is public. Do not generate type info. (dwarf2out_decl): Same. (add_type_attribute): Return immediately if debug level is terse. Signed-off-by: Alexey Neyman --- gcc/ChangeLog | 10 ++++ gcc/dwarf2out.c | 70 +++++++++++++++------------ gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 +++ gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 +++ 4 files changed, 62 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 642954d..e1c4da2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2020-03-17 Alexey Neyman + + PR debug/93751 + * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if + the debug level is terse and the declaration is public. Do not + generate type info. + (dwarf2out_decl): Same. + (add_type_attribute): Return immediately if debug level is + terse. + 2020-03-17 Richard Sandiford * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 0c8606a..b1fa6f5 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -21563,6 +21563,9 @@ add_type_attribute (dw_die_ref object_die, tree type, int cv_quals, enum tree_code code = TREE_CODE (type); dw_die_ref type_die = NULL; + if (debug_info_level <= DINFO_LEVEL_TERSE) + return; + /* ??? If this type is an unnamed subrange type of an integral, floating-point or fixed-point type, use the inner type. This is because we have no support for unnamed types in base_type_die. This can happen if this is @@ -26355,39 +26358,44 @@ gen_decl_die (tree decl, tree origin, struct vlr_context *ctx, case VAR_DECL: case RESULT_DECL: /* If we are in terse mode, don't generate any DIEs to represent any - variable declarations or definitions. */ - if (debug_info_level <= DINFO_LEVEL_TERSE) + variable declarations or definitions unless it is external. */ + if (debug_info_level < DINFO_LEVEL_TERSE + || (debug_info_level == DINFO_LEVEL_TERSE + && !TREE_PUBLIC (decl_or_origin))) break; - /* Avoid generating stray type DIEs during late dwarf dumping. - All types have been dumped early. */ - if (early_dwarf - /* ??? But in LTRANS we cannot annotate early created variably - modified type DIEs without copying them and adjusting all - references to them. Dump them again as happens for inlining - which copies both the decl and the types. */ - /* ??? And even non-LTO needs to re-visit type DIEs to fill - in VLA bound information for example. */ - || (decl && variably_modified_type_p (TREE_TYPE (decl), - current_function_decl))) + if (debug_info_level > DINFO_LEVEL_TERSE) { - /* Output any DIEs that are needed to specify the type of this data - object. */ - if (decl_by_reference_p (decl_or_origin)) - gen_type_die (TREE_TYPE (TREE_TYPE (decl_or_origin)), context_die); - else - gen_type_die (TREE_TYPE (decl_or_origin), context_die); - } + /* Avoid generating stray type DIEs during late dwarf dumping. + All types have been dumped early. */ + if (early_dwarf + /* ??? But in LTRANS we cannot annotate early created variably + modified type DIEs without copying them and adjusting all + references to them. Dump them again as happens for inlining + which copies both the decl and the types. */ + /* ??? And even non-LTO needs to re-visit type DIEs to fill + in VLA bound information for example. */ + || (decl && variably_modified_type_p (TREE_TYPE (decl), + current_function_decl))) + { + /* Output any DIEs that are needed to specify the type of this data + object. */ + if (decl_by_reference_p (decl_or_origin)) + gen_type_die (TREE_TYPE (TREE_TYPE (decl_or_origin)), context_die); + else + gen_type_die (TREE_TYPE (decl_or_origin), context_die); + } - if (early_dwarf) - { - /* And its containing type. */ - class_origin = decl_class_context (decl_or_origin); - if (class_origin != NULL_TREE) - gen_type_die_for_member (class_origin, decl_or_origin, context_die); + if (early_dwarf) + { + /* And its containing type. */ + class_origin = decl_class_context (decl_or_origin); + if (class_origin != NULL_TREE) + gen_type_die_for_member (class_origin, decl_or_origin, context_die); - /* And its containing namespace. */ - context_die = declare_in_namespace (decl_or_origin, context_die); + /* And its containing namespace. */ + context_die = declare_in_namespace (decl_or_origin, context_die); + } } /* Now output the DIE to represent the data object itself. This gets @@ -26832,8 +26840,10 @@ dwarf2out_decl (tree decl) context_die = lookup_decl_die (DECL_CONTEXT (decl)); /* If we are in terse mode, don't generate any DIEs to represent any - variable declarations or definitions. */ - if (debug_info_level <= DINFO_LEVEL_TERSE) + variable declarations or definitions unless it is external. */ + if (debug_info_level < DINFO_LEVEL_TERSE + || (debug_info_level == DINFO_LEVEL_TERSE + && !TREE_PUBLIC (decl))) return; break; diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c b/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c new file mode 100644 index 0000000..4be170c --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c @@ -0,0 +1,6 @@ +// { dg-do compile } +// { dg-options "-O -gdwarf-2 -g1 -dA" } +static int bar; + +// Verify that with -g1 we still do not generate DIEs for static variables. +// { dg-final { scan-assembler-not " DW_TAG_variable" } } diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c b/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c new file mode 100644 index 0000000..3ee369b --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c @@ -0,0 +1,6 @@ +// { dg-do compile } +// { dg-options "-O -gdwarf-2 -g1 -dA" } +int foo; + +// Verify that with -g1 we generate DIEs for external variables. +// { dg-final { scan-assembler " DW_TAG_variable" } } -- cgit v1.1 From af8656be8df68ac26840f7844430fd595255ebd2 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 18 Mar 2020 08:53:23 +0100 Subject: c++: Diagnose a deduction guide in a wrong scope [PR91759] The following testcase is accepts-invalid since r7-6608-ga56c0ac08242269b. Before that change we had this "deduction guide %qD must be declared in the same scope as %qT" diagnostics for it, after the change it is expected to be diagnosed in set_decl_namespace at the not_found: label in there. On this testcase nothing is diagnosed though, because set_decl_namespace isn't called at all, as in_namespace is NULL. The following patch restores the old warning but does it only in case we don't call set_decl_namespace. 2020-03-18 Jakub Jelinek PR c++/91759 * decl.c (grokfndecl): Restore old diagnostics about deduction guide declared in different scope if in_namespace is NULL_TREE. * g++.dg/cpp1z/class-deduction72.C: New test. --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/decl.c | 9 +++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 1db1e09..9aaa81a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2020-03-18 Jakub Jelinek + + PR c++/91759 + * decl.c (grokfndecl): Restore old diagnostics about deduction + guide declared in different scope if in_namespace is NULL_TREE. + 2020-03-17 Jakub Jelinek PR c++/90995 diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index d240436..319b7ee 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -9644,6 +9644,15 @@ grokfndecl (tree ctype, "namespace scope", decl); return NULL_TREE; } + tree type = TREE_TYPE (DECL_NAME (decl)); + if (in_namespace == NULL_TREE + && CP_DECL_CONTEXT (decl) != CP_TYPE_CONTEXT (type)) + { + error_at (location, "deduction guide %qD must be declared in the " + "same scope as %qT", decl, type); + inform (location_of (type), " declared here"); + return NULL_TREE; + } if (funcdef_flag) error_at (location, "deduction guide %qD must not have a function body", decl); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 775837d..8efb773 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Jakub Jelinek + + PR c++/91759 + * g++.dg/cpp1z/class-deduction72.C: New test. + 2020-03-17 Uroš Bizjak * g++.dg/debug/dwarf2/const2b.C (dg-do): Fix target selector. diff --git a/gcc/testsuite/g++.dg/cpp1z/class-deduction72.C b/gcc/testsuite/g++.dg/cpp1z/class-deduction72.C new file mode 100644 index 0000000..60c5599 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/class-deduction72.C @@ -0,0 +1,11 @@ +// PR c++/91759 +// { dg-do compile { target c++17 } } + +namespace N { + template + struct X{ X(int); }; // { dg-message "declared here" } +} + +using N::X; + +X(int) -> X; // { dg-error "must be declared in the same scope as" } -- cgit v1.1 From 4e3d3e40726e1b68bf52fa205c68495124ea60b8 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 18 Mar 2020 09:13:17 +0100 Subject: middle-end/94188 fix fold of addr expression generation This adds a missing type conversion to build_fold_addr_expr and adjusts fallout - build_fold_addr_expr was used as a convenience to build an ADDR_EXPR but some callers do not expect the result to be simplified to something else. 2020-03-18 Richard Biener PR middle-end/94188 * fold-const.c (build_fold_addr_expr): Convert address to correct type. * asan.c (maybe_create_ssa_name): Strip useless type conversions. * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1 to build the ADDR_EXPR which we don't really want to simplify. * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise. * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise. * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise. (simplify_builtin_call): Strip useless type conversions. * tree-ssa-strlen.c (new_strinfo): Likewise. * gcc.dg/pr94188.c: New testcase. --- gcc/ChangeLog | 14 ++++++++++++++ gcc/asan.c | 5 +++-- gcc/fold-const.c | 7 ++++++- gcc/gimple-fold.c | 4 ++-- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr94188.c | 10 ++++++++++ gcc/tree-ssa-dom.c | 9 ++++----- gcc/tree-ssa-forwprop.c | 11 ++++++----- gcc/tree-ssa-loop-im.c | 3 ++- gcc/tree-ssa-strlen.c | 3 ++- 10 files changed, 54 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94188.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e1c4da2..b4d7946 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2020-03-18 Richard Biener + + PR middle-end/94188 + * fold-const.c (build_fold_addr_expr): Convert address to + correct type. + * asan.c (maybe_create_ssa_name): Strip useless type conversions. + * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1 + to build the ADDR_EXPR which we don't really want to simplify. + * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise. + * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise. + * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise. + (simplify_builtin_call): Strip useless type conversions. + * tree-ssa-strlen.c (new_strinfo): Likewise. + 2020-03-17 Alexey Neyman PR debug/93751 diff --git a/gcc/asan.c b/gcc/asan.c index 05f8b63..00d0e67 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -62,6 +62,7 @@ along with GCC; see the file COPYING3. If not see #include "builtins.h" #include "fnmatch.h" #include "tree-inline.h" +#include "tree-ssa.h" /* AddressSanitizer finds out-of-bounds and use-after-free bugs with <2x slowdown on average. @@ -2061,10 +2062,10 @@ static tree maybe_create_ssa_name (location_t loc, tree base, gimple_stmt_iterator *iter, bool before_p) { + STRIP_USELESS_TYPE_CONVERSION (base); if (TREE_CODE (base) == SSA_NAME) return base; - gimple *g = gimple_build_assign (make_ssa_name (TREE_TYPE (base)), - TREE_CODE (base), base); + gimple *g = gimple_build_assign (make_ssa_name (TREE_TYPE (base)), base); gimple_set_location (g, loc); if (before_p) gsi_insert_before (iter, g, GSI_SAME_STMT); diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 71a1d3e..3ab1a9a 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -8523,7 +8523,12 @@ build_fold_addr_expr_with_type_loc (location_t loc, tree t, tree ptrtype) } else if (TREE_CODE (t) == MEM_REF && integer_zerop (TREE_OPERAND (t, 1))) - return TREE_OPERAND (t, 0); + { + t = TREE_OPERAND (t, 0); + + if (TREE_TYPE (t) != ptrtype) + t = fold_convert_loc (loc, ptrtype, t); + } else if (TREE_CODE (t) == MEM_REF && TREE_CODE (TREE_OPERAND (t, 0)) == INTEGER_CST) return fold_binary (POINTER_PLUS_EXPR, ptrtype, diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index 9e45cc5..3f17de9 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -6413,8 +6413,8 @@ gimple_fold_stmt_to_constant_1 (gimple *stmt, tree (*valueize) (tree), && TREE_CODE (op1) == INTEGER_CST) { tree off = fold_convert (ptr_type_node, op1); - return build_fold_addr_expr_loc - (loc, + return build1_loc + (loc, ADDR_EXPR, TREE_TYPE (op0), fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (op0)), unshare_expr (op0), off)); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8efb773..2c7f350 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Richard Biener + + PR middle-end/94188 + * gcc.dg/pr94188.c: New testcase. + 2020-03-18 Jakub Jelinek PR c++/91759 diff --git a/gcc/testsuite/gcc.dg/pr94188.c b/gcc/testsuite/gcc.dg/pr94188.c new file mode 100644 index 0000000..7a73c1b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94188.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ + +struct dm_tree_link { + int list; + int node; +}; +void fn1(void *p) +{ + 0 ? ((struct dm_tree_link *)((char *)p - (char *)&((struct dm_tree_link *)0)->list))->node : 0; +} diff --git a/gcc/tree-ssa-dom.c b/gcc/tree-ssa-dom.c index ee848fe..864c984 100644 --- a/gcc/tree-ssa-dom.c +++ b/gcc/tree-ssa-dom.c @@ -1725,11 +1725,10 @@ record_equivalences_from_stmt (gimple *stmt, int may_optimize_p, tree op0 = gimple_assign_rhs1 (stmt); tree op1 = gimple_assign_rhs2 (stmt); tree new_rhs - = build_fold_addr_expr (fold_build2 (MEM_REF, - TREE_TYPE (TREE_TYPE (op0)), - unshare_expr (op0), - fold_convert (ptr_type_node, - op1))); + = build1 (ADDR_EXPR, TREE_TYPE (op0), + fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (op0)), + unshare_expr (op0), fold_convert (ptr_type_node, + op1))); if (dump_file && (dump_flags & TDF_DETAILS)) { fprintf (dump_file, "==== ASGN "); diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index f65216d..61b4eec 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -50,6 +50,7 @@ along with GCC; see the file COPYING3. If not see #include "vec-perm-indices.h" #include "internal-fn.h" #include "cgraph.h" +#include "tree-ssa.h" /* This pass propagates the RHS of assignment statements into use sites of the LHS of the assignment. It's basically a specialized @@ -732,16 +733,15 @@ forward_propagate_addr_expr_1 (tree name, tree def_rhs, if (TREE_CODE (new_def_rhs) == MEM_REF && !is_gimple_mem_ref_addr (TREE_OPERAND (new_def_rhs, 0))) return false; - new_def_rhs = build_fold_addr_expr_with_type (new_def_rhs, - TREE_TYPE (rhs)); + new_def_rhs = build1 (ADDR_EXPR, TREE_TYPE (rhs), new_def_rhs); /* Recurse. If we could propagate into all uses of lhs do not bother to replace into the current use but just pretend we did. */ - if (TREE_CODE (new_def_rhs) == ADDR_EXPR - && forward_propagate_addr_expr (lhs, new_def_rhs, single_use_p)) + if (forward_propagate_addr_expr (lhs, new_def_rhs, single_use_p)) return true; - if (useless_type_conversion_p (TREE_TYPE (lhs), TREE_TYPE (new_def_rhs))) + if (useless_type_conversion_p (TREE_TYPE (lhs), + TREE_TYPE (new_def_rhs))) gimple_assign_set_rhs_with_ops (use_stmt_gsi, TREE_CODE (new_def_rhs), new_def_rhs); else if (is_gimple_min_invariant (new_def_rhs)) @@ -1319,6 +1319,7 @@ simplify_builtin_call (gimple_stmt_iterator *gsi_p, tree callee2) || !tree_fits_shwi_p (src1)) break; ptr1 = build_fold_addr_expr (ptr1); + STRIP_USELESS_TYPE_CONVERSION (ptr1); callee1 = NULL_TREE; len1 = size_one_node; lhs1 = NULL_TREE; diff --git a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c index 3e64ae7..273a580 100644 --- a/gcc/tree-ssa-loop-im.c +++ b/gcc/tree-ssa-loop-im.c @@ -1527,7 +1527,8 @@ gather_mem_refs_stmt (class loop *loop, gimple *stmt) tree ref_alias_type = reference_alias_ptr_type (*mem); unsigned int ref_align = get_object_alignment (*mem); tree ref_type = TREE_TYPE (*mem); - tree tmp = build_fold_addr_expr (unshare_expr (mem_base)); + tree tmp = build1 (ADDR_EXPR, ptr_type_node, + unshare_expr (mem_base)); if (TYPE_ALIGN (ref_type) != ref_align) ref_type = build_aligned_type (ref_type, ref_align); (*slot)->mem.ref diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index df4c1b6..f883a1f 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -57,9 +57,9 @@ along with GCC; see the file COPYING3. If not see #include "cfgloop.h" #include "tree-ssa-loop.h" #include "tree-scalar-evolution.h" - #include "vr-values.h" #include "gimple-ssa-evrp-analyze.h" +#include "tree-ssa.h" /* A vector indexed by SSA_NAME_VERSION. 0 means unknown, positive value is an index into strinfo vector, negative value stands for @@ -679,6 +679,7 @@ new_strinfo (tree ptr, int idx, tree nonzero_chars, bool full_string_p) { strinfo *si = strinfo_pool.allocate (); si->nonzero_chars = nonzero_chars; + STRIP_USELESS_TYPE_CONVERSION (ptr); si->ptr = ptr; si->stmt = NULL; si->alloc = NULL; -- cgit v1.1 From 4da9288745d8f9c0d6918b685522e89c277020c7 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Wed, 18 Mar 2020 12:07:54 +0100 Subject: libgomp testsuite - disable long double for AMDGCN * testsuite/libgomp.oacc-c++/firstprivate-mappings-1.C: Add #define DO_LONG_DOUBLE; set to 1, except for nvidia + gcn. * libgomp.oacc-c-c++-common/firstprivate-mappings-1.c: Likewise. * g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if not defined; update comments. * c-c++-common/goacc/firstprivate-mappings-1.c: Likewise. --- gcc/testsuite/ChangeLog | 56 ++++++++++++---------- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 ++--- .../g++.dg/goacc/firstprivate-mappings-1.C | 12 ++--- 3 files changed, 39 insertions(+), 41 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2c7f350..0b2e4b8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-18 Tobias Burnus + + * g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if + not defined; update comments. + * c-c++-common/goacc/firstprivate-mappings-1.c: Likewise. + 2020-03-18 Richard Biener PR middle-end/94188 @@ -33,8 +39,8 @@ DEFAULT_CXXFLAGS has a value, even if unset by a higher level. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. @@ -72,8 +78,8 @@ * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. @@ -222,8 +228,8 @@ * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. @@ -587,8 +593,8 @@ * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: New test. * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. @@ -606,8 +612,8 @@ * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. @@ -629,8 +635,8 @@ * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test. * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. @@ -644,8 +650,8 @@ * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. @@ -654,8 +660,8 @@ * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. @@ -738,8 +744,8 @@ * gcc.dg/pr94015.c: New test. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: New test. * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise. @@ -757,8 +763,8 @@ * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise. 2020-03-17 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. @@ -789,8 +795,8 @@ * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. 2020-03-16 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vst4q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. @@ -866,8 +872,8 @@ 2020-03-16 Andre Vieira - Mihail Ionescu - Srinath Parvathaneni + Mihail Ionescu + Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test. * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. @@ -1296,7 +1302,7 @@ 2020-03-04 Martin Sebor PR tree-optimization/93986 - * gcc.dg/pr93986.c: New test. + * gcc.dg/pr93986.c: New test. 2020-03-04 David Malcolm diff --git a/gcc/testsuite/c-c++-common/goacc/firstprivate-mappings-1.c b/gcc/testsuite/c-c++-common/goacc/firstprivate-mappings-1.c index 33576c5..7987bea 100644 --- a/gcc/testsuite/c-c++-common/goacc/firstprivate-mappings-1.c +++ b/gcc/testsuite/c-c++-common/goacc/firstprivate-mappings-1.c @@ -2,7 +2,9 @@ /* This file is also sourced from '../../../../libgomp/testsuite/libgomp.oacc-c-c++-common/firstprivate-mappings-1.c' - as an execution test. */ + as an execution test. + + 'long double' tests are compiled/used unless DO_LONG_DOUBLE is set to 0. */ /* See also '../../g++.dg/goacc/firstprivate-mappings-1.C'. */ @@ -24,13 +26,7 @@ # define HAVE_INT128 0 #endif - -/* The one is only relevant for offloading compilation; will always be enabled - when doing tree scanning. */ -#ifdef ACC_DEVICE_TYPE_nvidia -/* PR71064. */ -# define DO_LONG_DOUBLE 0 -#else +#ifndef DO_LONG_DOUBLE # define DO_LONG_DOUBLE 1 #endif diff --git a/gcc/testsuite/g++.dg/goacc/firstprivate-mappings-1.C b/gcc/testsuite/g++.dg/goacc/firstprivate-mappings-1.C index 639bf3f..1b1badb 100644 --- a/gcc/testsuite/g++.dg/goacc/firstprivate-mappings-1.C +++ b/gcc/testsuite/g++.dg/goacc/firstprivate-mappings-1.C @@ -2,7 +2,9 @@ /* This file is also sourced from '../../../../libgomp/testsuite/libgomp.oacc-c++/firstprivate-mappings-1.C' - as an execution test. */ + as an execution test. + + 'long double' tests are compiled/used unless DO_LONG_DOUBLE is set to 0. */ /* See also '../../c-c++-common/goacc/firstprivate-mappings-1.c'. */ @@ -21,13 +23,7 @@ # define HAVE_INT128 0 #endif - -/* The one is only relevant for offloading compilation; will always be enabled - when doing tree scanning. */ -#ifdef ACC_DEVICE_TYPE_nvidia -/* PR71064. */ -# define DO_LONG_DOUBLE 0 -#else +#ifndef DO_LONG_DOUBLE # define DO_LONG_DOUBLE 1 #endif -- cgit v1.1 From cb26919c857f002fc17f7c478e7c8f0eb2a7c9b2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 16 Mar 2020 15:26:35 +0000 Subject: aarch64: Treat p12-p15 as call-preserved in SVE PCS functions Due to a stupid mistake that I can't really explain, I'd got the treatment of p12-p15 mixed up when adding support for the SVE PCS. The registers are supposed to be call-preserved rather than call-clobbered. The fix is simple, but it has quite a big effect on the PCS tests (as it should!). 2020-03-18 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as call-preserved for SVE PCS functions. (aarch64_layout_frame): Cope with up to 12 predicate save slots. Optimize the case in which there are no following vector save slots. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the check-function-bodies patterns for p15 to be saved. * gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two predicates to be saved. * gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15 to be saved and restored. * gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise. * gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. * gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 16 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect p12-p15 to be saved and restored. (test_2): Remove p12-p15 from the clobber list. (test_4): Expect only 32 bytes of stack to be allocated for the predicate save slot. * gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather than p4 to create a vector-sized save slot. * gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise. --- gcc/ChangeLog | 7 + gcc/config/aarch64/aarch64.c | 31 ++- gcc/testsuite/ChangeLog | 58 ++++ .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 ++++++++++++--------- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 ++++++++++++--------- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 ++++++++++++--------- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 ++++++++++++--------- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +++--- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +++--- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +++--- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +++--- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +++--- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +++--- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +++--- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +++--- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +++--- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 ++--- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 ++--- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 ++--- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 ++--- 27 files changed, 1511 insertions(+), 1180 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b4d7946..1fa2911 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-18 Richard Sandiford + + * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as + call-preserved for SVE PCS functions. + (aarch64_layout_frame): Cope with up to 12 predicate save slots. + Optimize the case in which there are no following vector save slots. + 2020-03-18 Richard Biener PR middle-end/94188 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 285341e..26c0096 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1425,7 +1425,7 @@ aarch64_sve_abi (void) = default_function_abi.full_reg_clobbers (); for (int regno = V8_REGNUM; regno <= V23_REGNUM; ++regno) CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); - for (int regno = P4_REGNUM; regno <= P11_REGNUM; ++regno) + for (int regno = P4_REGNUM; regno <= P15_REGNUM; ++regno) CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); sve_abi.initialize (ARM_PCS_SVE, full_reg_clobbers); } @@ -6008,14 +6008,31 @@ aarch64_layout_frame (void) offset += BYTES_PER_SVE_PRED; } - /* We save a maximum of 8 predicate registers, and since vector - registers are 8 times the size of a predicate register, all the - saved predicates fit within a single vector. Doing this also - rounds the offset to a 128-bit boundary. */ if (maybe_ne (offset, 0)) { - gcc_assert (known_le (offset, vector_save_size)); - offset = vector_save_size; + /* If we have any vector registers to save above the predicate registers, + the offset of the vector register save slots need to be a multiple + of the vector size. This lets us use the immediate forms of LDR/STR + (or LD1/ST1 for big-endian). + + A vector register is 8 times the size of a predicate register, + and we need to save a maximum of 12 predicate registers, so the + first vector register will be at either #1, MUL VL or #2, MUL VL. + + If we don't have any vector registers to save, and we know how + big the predicate save area is, we can just round it up to the + next 16-byte boundary. */ + if (last_fp_reg == (int) INVALID_REGNUM && offset.is_constant ()) + offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); + else + { + if (known_le (offset, vector_save_size)) + offset = vector_save_size; + else if (known_le (offset, vector_save_size * 2)) + offset = vector_save_size * 2; + else + gcc_unreachable (); + } } /* If we need to save any SVE vector registers, add them next. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0b2e4b8..3c70254 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,61 @@ +2020-03-18 Richard Sandiford + + * gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the + check-function-bodies patterns for p15 to be saved. + * gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two + predicates to be saved. + * gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15 + to be saved and restored. + * gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise. + * gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + * gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 16 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect + p12-p15 to be saved and restored. + (test_2): Remove p12-p15 from the clobber list. + (test_4): Expect only 32 bytes of stack to be allocated for the + predicate save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather + than p4 to create a vector-sized save slot. + * gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise. + * gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise. + 2020-03-18 Tobias Burnus * g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c index 1d8f429..57b56a7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c @@ -10,9 +10,11 @@ extern "C" { /* ** dup_x0_m: +** ... ** add (x[0-9]+), x0, #?1 ** mov (p[0-7])\.b, p15\.b ** mov z0\.d, \2/m, \1 +** ... ** ret */ svuint64_t @@ -25,8 +27,10 @@ dup_x0_m (svuint64_t z0, uint64_t x0) /* ** dup_d1_z: +** ... ** mov (p[0-7])\.b, p15\.b ** mov z0\.d, \1/m, d1 +** ... ** ret */ svfloat64_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c index fd9932e..ab7c4a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c @@ -6,11 +6,17 @@ /* ** callee_pred: +** addvl sp, sp, #-1 +** str p[0-9]+, \[sp\] +** str p[0-9]+, \[sp, #1, mul vl\] ** ldr (p[0-9]+), \[x0\] ** ldr (p[0-9]+), \[x1\] ** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b ** brkpb (p[0-7])\.b, \3/z, p3\.b, \1\.b ** brka p0\.b, \4/z, \2\.b +** ldr p[0-9]+, \[sp\] +** ldr p[0-9]+, \[sp, #1, mul vl\] +** addvl sp, sp, #1 ** ret */ __SVBool_t __attribute__((noipa)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c index 4eee042..d94e26e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,43 +15,47 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p1\.b, all -** st1d z8\.d, p1, \[sp, #1, mul vl\] -** st1d z9\.d, p1, \[sp, #2, mul vl\] -** st1d z10\.d, p1, \[sp, #3, mul vl\] -** st1d z11\.d, p1, \[sp, #4, mul vl\] -** st1d z12\.d, p1, \[sp, #5, mul vl\] -** st1d z13\.d, p1, \[sp, #6, mul vl\] -** st1d z14\.d, p1, \[sp, #7, mul vl\] +** st1d z8\.d, p1, \[sp, #2, mul vl\] +** st1d z9\.d, p1, \[sp, #3, mul vl\] +** st1d z10\.d, p1, \[sp, #4, mul vl\] +** st1d z11\.d, p1, \[sp, #5, mul vl\] +** st1d z12\.d, p1, \[sp, #6, mul vl\] +** st1d z13\.d, p1, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p1, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p1, \[x11, #-8, mul vl\] +** st1d z15\.d, p1, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all ** ptrue p1\.b, all -** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p1/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p1/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p1/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p1/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p1/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p1/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p1/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -60,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -87,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c index e88a3dd..a895272 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,43 +15,47 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p1\.b, all -** st1d z8\.d, p1, \[sp, #1, mul vl\] -** st1d z9\.d, p1, \[sp, #2, mul vl\] -** st1d z10\.d, p1, \[sp, #3, mul vl\] -** st1d z11\.d, p1, \[sp, #4, mul vl\] -** st1d z12\.d, p1, \[sp, #5, mul vl\] -** st1d z13\.d, p1, \[sp, #6, mul vl\] -** st1d z14\.d, p1, \[sp, #7, mul vl\] +** st1d z8\.d, p1, \[sp, #2, mul vl\] +** st1d z9\.d, p1, \[sp, #3, mul vl\] +** st1d z10\.d, p1, \[sp, #4, mul vl\] +** st1d z11\.d, p1, \[sp, #5, mul vl\] +** st1d z12\.d, p1, \[sp, #6, mul vl\] +** st1d z13\.d, p1, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p1, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p1, \[x11, #-8, mul vl\] +** st1d z15\.d, p1, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all ** ptrue p1\.b, all -** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p1/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p1/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p1/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p1/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p1/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p1/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p1/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -60,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -87,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c index d14cd79..72267dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c index d81dd8e..3188078 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c @@ -6,7 +6,7 @@ /* ** test_1: -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c index 05aa18b..7c4884d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,43 +18,47 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,7 +67,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -73,7 +81,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -82,43 +90,47 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -127,7 +139,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -137,7 +153,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -146,43 +162,47 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -191,7 +211,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -205,7 +229,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -214,43 +238,47 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -259,7 +287,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c index 85b7794..872364f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,43 +18,47 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,7 +67,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -73,7 +81,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -82,43 +90,47 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -127,7 +139,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -137,7 +153,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -146,43 +162,47 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -191,7 +211,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -205,7 +229,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -214,43 +238,47 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -259,7 +287,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c index 0fcd357..4ba71c0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,39 +18,43 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -59,7 +63,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -69,7 +77,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -78,39 +86,43 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -119,7 +131,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -129,7 +145,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -138,39 +154,43 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -179,7 +199,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -193,7 +217,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -202,39 +226,43 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -243,7 +271,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c index e81194c..c3acd40 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c @@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -18,39 +18,43 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -59,7 +63,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -69,7 +77,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** calls_vpcs: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -78,39 +86,43 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** bl vpcs_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -119,7 +131,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -129,7 +145,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** calls_standard_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -138,39 +154,43 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -179,7 +199,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); } ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ @@ -193,7 +217,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** calls_vpcs_ptr: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -202,39 +226,43 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** blr x0 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -243,7 +271,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void)) ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c index c42699d..aa67bee 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c @@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ** stp x29, x30, \[sp\] ** ) ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -23,45 +23,49 @@ void standard_callee (__SVInt8_t *); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] -** addvl x0, sp, #17 +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] +** addvl x0, sp, #18 ** add x0, x0, #?16 ** bl standard_callee ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -70,7 +74,11 @@ void standard_callee (__SVInt8_t *); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ( ** ldp x29, x30, \[sp\], 16 ** addvl sp, sp, #1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c index 49fe968..ab232d7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c @@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ** stp x29, x30, \[sp\] ** ) ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -23,41 +23,45 @@ void standard_callee (__SVInt8_t *); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] -** addvl x0, sp, #17 +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] +** addvl x0, sp, #18 ** add x0, x0, #?16 ** bl standard_callee -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -66,7 +70,11 @@ void standard_callee (__SVInt8_t *); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ( ** ldp x29, x30, \[sp\], 16 ** addvl sp, sp, #1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c index dc3282e..cce9cd8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c @@ -8,40 +8,40 @@ void standard_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 +** addvl sp, sp, #-18 ** ptrue p0\.b, all -** st1d z8\.d, p0, \[sp, #1, mul vl\] -** st1d z9\.d, p0, \[sp, #2, mul vl\] -** st1d z10\.d, p0, \[sp, #3, mul vl\] -** st1d z11\.d, p0, \[sp, #4, mul vl\] -** st1d z12\.d, p0, \[sp, #5, mul vl\] -** st1d z13\.d, p0, \[sp, #6, mul vl\] -** st1d z14\.d, p0, \[sp, #7, mul vl\] +** st1d z8\.d, p0, \[sp, #2, mul vl\] +** st1d z9\.d, p0, \[sp, #3, mul vl\] +** st1d z10\.d, p0, \[sp, #4, mul vl\] +** st1d z11\.d, p0, \[sp, #5, mul vl\] +** st1d z12\.d, p0, \[sp, #6, mul vl\] +** st1d z13\.d, p0, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** st1d z15\.d, p0, \[x11, #-8, mul vl\] +** st1d z14\.d, p0, \[x11, #-8, mul vl\] +** st1d z15\.d, p0, \[x11, #-7, mul vl\] ** cbnz w0, \.L[0-9]+ ** ptrue p0\.b, all -** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] -** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] -** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] -** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] -** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] -** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] -** ld1d z14\.d, p0/z, \[sp, #7, mul vl\] +** ld1d z8\.d, p0/z, \[sp, #2, mul vl\] +** ld1d z9\.d, p0/z, \[sp, #3, mul vl\] +** ld1d z10\.d, p0/z, \[sp, #4, mul vl\] +** ld1d z11\.d, p0/z, \[sp, #5, mul vl\] +** ld1d z12\.d, p0/z, \[sp, #6, mul vl\] +** ld1d z13\.d, p0/z, \[sp, #7, mul vl\] ** addvl x11, sp, #16 -** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] -** addvl sp, sp, #17 +** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\] +** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret ** ... -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -50,15 +50,19 @@ void standard_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** bl standard_callee -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -67,6 +71,10 @@ void standard_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** b \.L[0-9]+ */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c index 0d29ff2..0c4fff8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c @@ -8,29 +8,29 @@ void standard_callee (void); ** calls_standard: ** stp x29, x30, \[sp, -16\]! ** mov x29, sp -** addvl sp, sp, #-17 -** str z8, \[sp, #1, mul vl\] +** addvl sp, sp, #-18 +** str z8, \[sp, #2, mul vl\] ** cbnz w0, \.L[0-9]+ -** ldr z8, \[sp, #1, mul vl\] -** addvl sp, sp, #17 +** ldr z8, \[sp, #2, mul vl\] +** addvl sp, sp, #18 ** ldp x29, x30, \[sp\], 16 ** ret ** ... -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -39,22 +39,26 @@ void standard_callee (void); ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] ** bl standard_callee -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -63,6 +67,10 @@ void standard_callee (void); ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** b \.L[0-9]+ */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c index 485d018..110947a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c @@ -6,9 +6,8 @@ /* ** test_1: -** cntb x12 -** mov x13, #?17 -** mul x12, x12, x13 +** cntd x12, all, mul #9 +** lsl x12, x12, #?4 ** mov x11, sp ** ... ** sub sp, sp, x12 @@ -20,39 +19,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, all -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -61,7 +64,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** addvl sp, sp, #17 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** addvl sp, sp, #18 ** ret */ svbool_t @@ -88,7 +95,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c index 087e8db..6590e4a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #2176 +** sub sp, sp, #2304 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl128 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?2176 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?2304 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #128 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl128 ** ldr p4, \[sp\] -** add sp, sp, #?128 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c index 0eb7d10..404301d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #272 +** sub sp, sp, #288 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl16 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?272 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?288 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c index e8dc5d5..113ccc1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c @@ -6,7 +6,7 @@ /* ** test_1: -** mov x12, #?4352 +** mov x12, #?4608 ** sub sp, sp, x12 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] @@ -16,39 +16,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl256 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -57,6 +61,10 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] ** add sp, sp, x12 ** ret */ @@ -84,7 +92,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -122,11 +130,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #256 +** sub sp, sp, #32 ** str p4, \[sp\] ** ptrue p0\.b, vl256 ** ldr p4, \[sp\] -** add sp, sp, #?256 +** add sp, sp, #?32 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c index 73c49e4..0f71cec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #544 +** sub sp, sp, #576 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl32 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?544 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?576 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #32 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl32 ** ldr p4, \[sp\] -** add sp, sp, #?32 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c index d4b5241..8edbd04 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c @@ -6,7 +6,7 @@ /* ** test_1: -** sub sp, sp, #1088 +** sub sp, sp, #1152 ** str p4, \[sp\] ** str p5, \[sp, #1, mul vl\] ** str p6, \[sp, #2, mul vl\] @@ -15,39 +15,43 @@ ** str p9, \[sp, #5, mul vl\] ** str p10, \[sp, #6, mul vl\] ** str p11, \[sp, #7, mul vl\] -** str z8, \[sp, #1, mul vl\] -** str z9, \[sp, #2, mul vl\] -** str z10, \[sp, #3, mul vl\] -** str z11, \[sp, #4, mul vl\] -** str z12, \[sp, #5, mul vl\] -** str z13, \[sp, #6, mul vl\] -** str z14, \[sp, #7, mul vl\] -** str z15, \[sp, #8, mul vl\] -** str z16, \[sp, #9, mul vl\] -** str z17, \[sp, #10, mul vl\] -** str z18, \[sp, #11, mul vl\] -** str z19, \[sp, #12, mul vl\] -** str z20, \[sp, #13, mul vl\] -** str z21, \[sp, #14, mul vl\] -** str z22, \[sp, #15, mul vl\] -** str z23, \[sp, #16, mul vl\] +** str p12, \[sp, #8, mul vl\] +** str p13, \[sp, #9, mul vl\] +** str p14, \[sp, #10, mul vl\] +** str p15, \[sp, #11, mul vl\] +** str z8, \[sp, #2, mul vl\] +** str z9, \[sp, #3, mul vl\] +** str z10, \[sp, #4, mul vl\] +** str z11, \[sp, #5, mul vl\] +** str z12, \[sp, #6, mul vl\] +** str z13, \[sp, #7, mul vl\] +** str z14, \[sp, #8, mul vl\] +** str z15, \[sp, #9, mul vl\] +** str z16, \[sp, #10, mul vl\] +** str z17, \[sp, #11, mul vl\] +** str z18, \[sp, #12, mul vl\] +** str z19, \[sp, #13, mul vl\] +** str z20, \[sp, #14, mul vl\] +** str z21, \[sp, #15, mul vl\] +** str z22, \[sp, #16, mul vl\] +** str z23, \[sp, #17, mul vl\] ** ptrue p0\.b, vl64 -** ldr z8, \[sp, #1, mul vl\] -** ldr z9, \[sp, #2, mul vl\] -** ldr z10, \[sp, #3, mul vl\] -** ldr z11, \[sp, #4, mul vl\] -** ldr z12, \[sp, #5, mul vl\] -** ldr z13, \[sp, #6, mul vl\] -** ldr z14, \[sp, #7, mul vl\] -** ldr z15, \[sp, #8, mul vl\] -** ldr z16, \[sp, #9, mul vl\] -** ldr z17, \[sp, #10, mul vl\] -** ldr z18, \[sp, #11, mul vl\] -** ldr z19, \[sp, #12, mul vl\] -** ldr z20, \[sp, #13, mul vl\] -** ldr z21, \[sp, #14, mul vl\] -** ldr z22, \[sp, #15, mul vl\] -** ldr z23, \[sp, #16, mul vl\] +** ldr z8, \[sp, #2, mul vl\] +** ldr z9, \[sp, #3, mul vl\] +** ldr z10, \[sp, #4, mul vl\] +** ldr z11, \[sp, #5, mul vl\] +** ldr z12, \[sp, #6, mul vl\] +** ldr z13, \[sp, #7, mul vl\] +** ldr z14, \[sp, #8, mul vl\] +** ldr z15, \[sp, #9, mul vl\] +** ldr z16, \[sp, #10, mul vl\] +** ldr z17, \[sp, #11, mul vl\] +** ldr z18, \[sp, #12, mul vl\] +** ldr z19, \[sp, #13, mul vl\] +** ldr z20, \[sp, #14, mul vl\] +** ldr z21, \[sp, #15, mul vl\] +** ldr z22, \[sp, #16, mul vl\] +** ldr z23, \[sp, #17, mul vl\] ** ldr p4, \[sp\] ** ldr p5, \[sp, #1, mul vl\] ** ldr p6, \[sp, #2, mul vl\] @@ -56,7 +60,11 @@ ** ldr p9, \[sp, #5, mul vl\] ** ldr p10, \[sp, #6, mul vl\] ** ldr p11, \[sp, #7, mul vl\] -** add sp, sp, #?1088 +** ldr p12, \[sp, #8, mul vl\] +** ldr p13, \[sp, #9, mul vl\] +** ldr p14, \[sp, #10, mul vl\] +** ldr p15, \[sp, #11, mul vl\] +** add sp, sp, #?1152 ** ret */ svbool_t @@ -83,7 +91,7 @@ test_2 (void) asm volatile ("" ::: "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", - "p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); + "p0", "p1", "p2", "p3"); return svptrue_b8 (); } @@ -121,11 +129,11 @@ test_3 (void) /* ** test_4: -** sub sp, sp, #64 +** sub sp, sp, #16 ** str p4, \[sp\] ** ptrue p0\.b, vl64 ** ldr p4, \[sp\] -** add sp, sp, #?64 +** add sp, sp, #?16 ** ret */ svbool_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c index d5a9d44..e31200f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #144 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?144 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #176 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, #?176 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #256 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #288 ** stp x24, x25, \[sp, 128\] ** str x26, \[sp, 144\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 128\] ** ldr x26, \[sp, 144\] ** add sp, sp, #?288 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #128 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 128\] ** add x29, sp, #?128 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 128\] ** add x29, sp, #?128 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?128 ** stp x24, x25, \[sp, 144\] ** str x26, \[sp, 160\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl128 ** sub sp, x29, #128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c index c185e2e..f637516 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #272 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?272 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #304 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, #?304 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #512 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?512 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #544 ** stp x24, x25, \[sp, 256\] ** str x26, \[sp, 272\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl128 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 256\] ** ldr x26, \[sp, 272\] ** add sp, sp, #?544 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #256 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 256\] ** add x29, sp, #?256 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 256\] ** add x29, sp, #?256 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?256 ** stp x24, x25, \[sp, 272\] ** str x26, \[sp, 288\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl256 ** sub sp, x29, #256 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?256 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c index f8318b3..6bcbb57 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #48 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?48 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #80 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, #?80 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #64 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #96 ** stp x24, x25, \[sp, 32\] ** str x26, \[sp, 48\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 32\] ** ldr x26, \[sp, 48\] ** add sp, sp, #?96 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #32 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 32\] ** add x29, sp, #?32 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 32\] ** add x29, sp, #?32 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -260,12 +260,12 @@ test_10 (int n) ** add x29, sp, #?32 ** stp x24, x25, \[sp, 48\] ** str x26, \[sp, 64\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl32 ** sub sp, x29, #32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?32 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -279,6 +279,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c index 45a23ad..dc7df8e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c @@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, /* ** test_1: ** sub sp, sp, #80 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?80 ** ret */ @@ -21,7 +21,7 @@ svbool_t test_1 (void) { volatile int x = 1; - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -30,10 +30,10 @@ test_1 (void) ** sub sp, sp, #112 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, #?112 @@ -43,7 +43,7 @@ svbool_t test_2 (void) { volatile int x = 1; - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -53,10 +53,10 @@ test_2 (void) ** sub sp, sp, x12 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, x12 @@ -66,17 +66,17 @@ svbool_t test_3 (void) { volatile int x[1024]; - asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); + asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26"); return svptrue_b8 (); } /* ** test_4: ** sub sp, sp, #128 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?128 ** ret */ @@ -85,7 +85,7 @@ test_4 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b16 (); } @@ -94,10 +94,10 @@ test_4 (void) ** sub sp, sp, #160 ** stp x24, x25, \[sp, 64\] ** str x26, \[sp, 80\] -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.h, vl32 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** ldp x24, x25, \[sp, 64\] ** ldr x26, \[sp, 80\] ** add sp, sp, #?160 @@ -108,7 +108,7 @@ test_5 (void) { volatile svint32_t b; b = svdup_s32 (1); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b16 (); } @@ -117,11 +117,11 @@ test_5 (void) ** stp x29, x30, \[sp, -16\]! ** mov x29, sp ** sub sp, sp, #64 -** str p4, \[sp\] +** str z16, \[sp\] ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\], 16 ** ret @@ -130,7 +130,7 @@ svbool_t test_6 (void) { take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -140,12 +140,12 @@ test_6 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 64\] ** add x29, sp, #?64 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -157,7 +157,7 @@ test_7 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -169,12 +169,12 @@ test_7 (void) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** add sp, sp, #?16 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -188,7 +188,7 @@ test_8 (void) { volatile int x[1024]; take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -198,12 +198,12 @@ test_8 (void) ** sub sp, sp, x12 ** stp x29, x30, \[sp, 64\] ** add x29, sp, #?64 -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x29, x30, \[sp\] ** mov x12, #?4112 @@ -215,7 +215,7 @@ test_9 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4"); + asm volatile ("" ::: "z16"); return svptrue_b8 (); } @@ -227,12 +227,12 @@ test_9 (int n) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -246,7 +246,7 @@ test_10 (int n) { volatile int x[1024]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } @@ -261,12 +261,12 @@ test_10 (int n) ** add x29, sp, #?64 ** stp x24, x25, \[sp, 80\] ** str x26, \[sp, 96\] -** str p4, \[sp\] +** str z16, \[sp\] ** sub sp, sp, #16 ** ... ** ptrue p0\.b, vl64 ** sub sp, x29, #64 -** ldr p4, \[sp\] +** ldr z16, \[sp\] ** add sp, sp, #?64 ** ldp x24, x25, \[sp, 16\] ** ldr x26, \[sp, 32\] @@ -280,6 +280,6 @@ test_11 (int n) { volatile int x[0x7ee4]; take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); - asm volatile ("" ::: "p4", "x24", "x25", "x26"); + asm volatile ("" ::: "z16", "x24", "x25", "x26"); return svptrue_b8 (); } -- cgit v1.1 From d91480dee934478063fe5945b73ff3c108e40a91 Mon Sep 17 00:00:00 2001 From: Duan bo Date: Wed, 18 Mar 2020 10:18:39 +0000 Subject: aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SYMBOL_TINY_GOT case in aarch64_load_symref_appropriately was missing support for ILP32. This caused an ICE on the testcase. 2020-03-18 Duan bo gcc/ PR target/94201 * config/aarch64/aarch64.md (ldr_got_tiny): Delete. (@ldr_got_tiny_): New pattern. (ldr_got_tiny_sidi): Likewise. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use them to handle SYMBOL_TINY_GOT for ILP32. gcc/testsuite/ PR target/94201 * gcc.target/aarch64/pr94201.c:New test. --- gcc/ChangeLog | 9 +++++++++ gcc/config/aarch64/aarch64.c | 17 +++++++++++++++-- gcc/config/aarch64/aarch64.md | 22 ++++++++++++++++------ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 +++++++++++++ 5 files changed, 58 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94201.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fa2911..5eb23b5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2020-03-18 Duan bo + + PR target/94201 + * config/aarch64/aarch64.md (ldr_got_tiny): Delete. + (@ldr_got_tiny_): New pattern. + (ldr_got_tiny_sidi): Likewise. + * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use + them to handle SYMBOL_TINY_GOT for ILP32. + 2020-03-18 Richard Sandiford * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 26c0096..c90de65 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2739,8 +2739,21 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm, } case SYMBOL_TINY_GOT: - emit_insn (gen_ldr_got_tiny (dest, imm)); - return; + { + rtx insn; + machine_mode mode = GET_MODE (dest); + + if (mode == ptr_mode) + insn = gen_ldr_got_tiny (mode, dest, imm); + else + { + gcc_assert (mode == Pmode); + insn = gen_ldr_got_tiny_sidi (dest, imm); + } + + emit_insn (insn); + return; + } case SYMBOL_TINY_TLSIE: { diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7ad4e91..c7c4d1d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6766,13 +6766,23 @@ [(set_attr "type" "load_4")] ) -(define_insn "ldr_got_tiny" - [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] - UNSPEC_GOTTINYPIC))] +(define_insn "@ldr_got_tiny_" + [(set (match_operand:PTR 0 "register_operand" "=r") + (unspec:PTR [(match_operand:PTR 1 "aarch64_valid_symref" "S")] + UNSPEC_GOTTINYPIC))] "" - "ldr\\t%0, %L1" - [(set_attr "type" "load_8")] + "ldr\t%0, %L1" + [(set_attr "type" "load_")] +) + +(define_insn "ldr_got_tiny_sidi" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI [(match_operand:DI 1 "aarch64_valid_symref" "S")] + UNSPEC_GOTTINYPIC)))] + "TARGET_ILP32" + "ldr\t%w0, %L1" + [(set_attr "type" "load_4")] ) (define_insn "aarch64_load_tp_hard" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3c70254..e8b78df 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Duan bo + + PR target/94201 + * gcc.target/aarch64/pr94201.c:New test. + 2020-03-18 Richard Sandiford * gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the diff --git a/gcc/testsuite/gcc.target/aarch64/pr94201.c b/gcc/testsuite/gcc.target/aarch64/pr94201.c new file mode 100644 index 0000000..6917616 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr94201.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mcmodel=tiny -mabi=ilp32 -fPIC" } */ + +extern int bar (void *); +extern long long a; + +int +foo (void) +{ + a = 1; + return bar ((void *)bar); +} + -- cgit v1.1 From d5029d45940e8c12b425b4d1a23081b4155caa61 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 18 Mar 2020 12:56:26 +0100 Subject: Fix up duplicated duplicated words in comments Another set of duplicated word fixes for things I've missed last time. These include e.g. *.cc files I forgot about, or duplicated words at the start or end of line. 2020-03-18 Jakub Jelinek * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue in a comment. * config/arc/arc.c (frame_stack_add): Likewise. * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): Likewise. * ipa-predicate.c (predicate::remap_after_inlining): Likewise. * tree-ssa-strlen.h (handle_printf_call): Likewise. * tree-ssa-strlen.c (is_strlen_related_p): Likewise. * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. analyzer/ * sm-malloc.cc (malloc_state_machine::on_stmt): Fix up duplicated word issue in a comment. * region-model.cc (region_model::make_region_for_unexpected_tree_code, region_model::delete_region_and_descendents): Likewise. * engine.cc (class exploded_cluster): Likewise. * diagnostic-manager.cc (class path_builder): Likewise. cp/ * constraint.cc (resolve_function_concept_check, subsumes_constraints, strictly_subsumes): Fix up duplicated word issue in a comment. * coroutines.cc (build_init_or_final_await, captures_temporary): Likewise. * logic.cc (dnf_size_r, cnf_size_r): Likewise. * pt.c (append_type_to_template_for_access_check): Likewise. d/ * expr.cc (ExprVisitor::visit (CatAssignExp *)): Fix up duplicated word issue in a comment. * d-target.cc (Target::FPTypeProperties::max): Likewise. fortran/ * class.c (generate_finalization_wrapper): Fix up duplicated word issue in a comment. * trans-types.c (gfc_get_nodesc_array_type): Likewise. --- gcc/ChangeLog | 12 ++++++++++++ gcc/analyzer/ChangeLog | 9 +++++++++ gcc/analyzer/diagnostic-manager.cc | 2 +- gcc/analyzer/engine.cc | 2 +- gcc/analyzer/region-model.cc | 4 ++-- gcc/analyzer/sm-malloc.cc | 2 +- gcc/asan.c | 2 +- gcc/config/arc/arc.c | 2 +- gcc/cp/ChangeLog | 7 +++++++ gcc/cp/constraint.cc | 6 +++--- gcc/cp/coroutines.cc | 4 ++-- gcc/cp/logic.cc | 8 ++++---- gcc/cp/pt.c | 2 +- gcc/d/ChangeLog | 6 ++++++ gcc/d/d-target.cc | 2 +- gcc/d/expr.cc | 2 +- gcc/fortran/ChangeLog | 6 ++++++ gcc/fortran/class.c | 2 +- gcc/fortran/trans-types.c | 2 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/ipa-predicate.c | 2 +- gcc/optinfo-emit-json.cc | 2 +- gcc/tree-ssa-strlen.c | 2 +- gcc/tree-ssa-strlen.h | 2 +- 24 files changed, 66 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5eb23b5..283ad1d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2020-03-18 Jakub Jelinek + + * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue + in a comment. + * config/arc/arc.c (frame_stack_add): Likewise. + * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): + Likewise. + * ipa-predicate.c (predicate::remap_after_inlining): Likewise. + * tree-ssa-strlen.h (handle_printf_call): Likewise. + * tree-ssa-strlen.c (is_strlen_related_p): Likewise. + * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. + 2020-03-18 Duan bo PR target/94201 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 8fc5dc4..a5c8b27 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,12 @@ +2020-03-18 Jakub Jelinek + + * sm-malloc.cc (malloc_state_machine::on_stmt): Fix up duplicated word + issue in a comment. + * region-model.cc (region_model::make_region_for_unexpected_tree_code, + region_model::delete_region_and_descendents): Likewise. + * engine.cc (class exploded_cluster): Likewise. + * diagnostic-manager.cc (class path_builder): Likewise. + 2020-03-13 David Malcolm PR analyzer/94099 diff --git a/gcc/analyzer/diagnostic-manager.cc b/gcc/analyzer/diagnostic-manager.cc index bea566d..9bd018a 100644 --- a/gcc/analyzer/diagnostic-manager.cc +++ b/gcc/analyzer/diagnostic-manager.cc @@ -110,7 +110,7 @@ saved_diagnostic::operator== (const saved_diagnostic &other) const /* State for building a checker_path from a particular exploded_path. In particular, this precomputes reachability information: the set of - source enodes for which a a path be found to the diagnostic enode. */ + source enodes for which a path be found to the diagnostic enode. */ class path_builder { diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc index 2431ae3..a8037c6 100644 --- a/gcc/analyzer/engine.cc +++ b/gcc/analyzer/engine.cc @@ -2988,7 +2988,7 @@ exploded_path::dump () const cluster, each supernode gets its own cluster. Hence all enodes relating to a particular function with a particular - callstring will be be in a cluster together; all enodes for the same + callstring will be in a cluster together; all enodes for the same function but with a different callstring will be in a different cluster. */ diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 45a1902..9cc6560 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -4871,7 +4871,7 @@ region_model::get_lvalue_1 (path_var pv, region_model_context *ctxt) } } -/* If we see a tree code we we don't know how to handle, rather than +/* If we see a tree code we don't know how to handle, rather than ICE or generate bogus results, create a dummy region, and notify CTXT so that it can mark the new state as being not properly modelled. The exploded graph can then stop exploring that path, @@ -6607,7 +6607,7 @@ region_model::get_descendents (region_id rid, region_id_set *out, } /* Delete RID and all descendent regions. - Find any pointers to such regions; convert convert them to + Find any pointers to such regions; convert them to poisoned values of kind PKIND. Accumulate stats on purged entities into STATS. */ diff --git a/gcc/analyzer/sm-malloc.cc b/gcc/analyzer/sm-malloc.cc index aaef695..38a2f1e 100644 --- a/gcc/analyzer/sm-malloc.cc +++ b/gcc/analyzer/sm-malloc.cc @@ -655,7 +655,7 @@ malloc_state_machine::on_stmt (sm_context *sm_ctxt, sm_ctxt->on_transition (node, stmt, arg, m_nonnull, m_freed); /* Keep state "null" as-is, rather than transitioning to "free"; - we don't want want to complain about double-free of NULL. */ + we don't want to complain about double-free of NULL. */ /* freed -> stop, with warning. */ sm_ctxt->warn_for_state (node, stmt, arg, m_freed, diff --git a/gcc/asan.c b/gcc/asan.c index 00d0e67..cc8f912 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -795,7 +795,7 @@ get_mem_refs_of_builtin_call (gcall *call, handle_builtin_alloca (call, iter); break; /* And now the __atomic* and __sync builtins. - These are handled differently from the classical memory memory + These are handled differently from the classical memory access builtins above. */ case BUILT_IN_ATOMIC_LOAD_1: diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 537af79..922ccc5 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -2607,7 +2607,7 @@ frame_stack_add (HOST_WIDE_INT offset) register. During compilation of a function the frame size is evaluated - multiple times, it is not until the reload pass is complete the the + multiple times, it is not until the reload pass is complete the frame size is considered fixed (it is at this point that space for all spills has been allocated). However the frame_pointer_needed variable is not set true until the register allocation pass, as a diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 9aaa81a..938504b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,12 @@ 2020-03-18 Jakub Jelinek + * constraint.cc (resolve_function_concept_check, subsumes_constraints, + strictly_subsumes): Fix up duplicated word issue in a comment. + * coroutines.cc (build_init_or_final_await, captures_temporary): + Likewise. + * logic.cc (dnf_size_r, cnf_size_r): Likewise. + * pt.c (append_type_to_template_for_access_check): Likewise. + PR c++/91759 * decl.c (grokfndecl): Restore old diagnostics about deduction guide declared in different scope if in_namespace is NULL_TREE. diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc index 2176978..5e434be 100644 --- a/gcc/cp/constraint.cc +++ b/gcc/cp/constraint.cc @@ -316,7 +316,7 @@ resolve_function_concept_overload (tree ovl, tree args) return cands; } -/* Determine if the the call expression CALL is a constraint check, and +/* Determine if the call expression CALL is a constraint check, and return the concept declaration and arguments being checked. If CALL does not denote a constraint check, return NULL. */ @@ -2958,7 +2958,7 @@ equivalently_constrained (tree d1, tree d2) Partial ordering of constraints ---------------------------------------------------------------------------*/ -/* Returns true when the the constraints in A subsume those in B. */ +/* Returns true when the constraints in A subsume those in B. */ bool subsumes_constraints (tree a, tree b) @@ -2968,7 +2968,7 @@ subsumes_constraints (tree a, tree b) return subsumes (a, b); } -/* Returns true when the the constraints in CI (with arguments +/* Returns true when the constraints in CI (with arguments ARGS) strictly subsume the associated constraints of TMPL. */ bool diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc index f70b3ab..a943ba0 100644 --- a/gcc/cp/coroutines.cc +++ b/gcc/cp/coroutines.cc @@ -2466,7 +2466,7 @@ build_init_or_final_await (location_t loc, bool is_final) return error_mark_node; /* So build the co_await for this */ - /* For initial/final suspends the call is is "a" per [expr.await] 3.2. */ + /* For initial/final suspends the call is "a" per [expr.await] 3.2. */ return build_co_await (loc, setup_call, (is_final ? FINAL_SUSPEND_POINT : INITIAL_SUSPEND_POINT)); } @@ -2547,7 +2547,7 @@ static tree captures_temporary (tree *stmt, int *do_subtree, void *d) { /* Stop recursing if we see an await expression, the subtrees - of that will be handled when it it processed. */ + of that will be handled when it is processed. */ if (TREE_CODE (*stmt) == CO_AWAIT_EXPR || TREE_CODE (*stmt) == CO_YIELD_EXPR) { *do_subtree = 0; diff --git a/gcc/cp/logic.cc b/gcc/cp/logic.cc index 4e376fd..194b743 100644 --- a/gcc/cp/logic.cc +++ b/gcc/cp/logic.cc @@ -355,7 +355,7 @@ atomic_p (tree t) /* Recursively count the number of clauses produced when converting T to DNF. Returns a pair containing the number of clauses and a bool - value signifying that the the tree would be rewritten as a result of + value signifying that the tree would be rewritten as a result of distributing. In general, a conjunction for which this flag is set is considered a disjunction for the purpose of counting. */ @@ -421,7 +421,7 @@ dnf_size_r (tree t) /* Matches constraints of the form P /\ Q, possibly resulting in the distribution of one side over the other. When both P and Q are disjunctions, the number of clauses are multiplied. - When only one of P and Q is a disjunction, the the number of + When only one of P and Q is a disjunction, the number of clauses are added. Otherwise, neither side is a disjunction and no clauses are created. */ if (disjunction_p (lhs)) @@ -463,7 +463,7 @@ dnf_size_r (tree t) /* Recursively count the number of clauses produced when converting T to CNF. Returns a pair containing the number of clauses and a bool - value signifying that the the tree would be rewritten as a result of + value signifying that the tree would be rewritten as a result of distributing. In general, a disjunction for which this flag is set is considered a conjunction for the purpose of counting. */ @@ -488,7 +488,7 @@ cnf_size_r (tree t) /* Matches constraints of the form P \/ Q, possibly resulting in the distribution of one side over the other. When both P and Q are conjunctions, the number of clauses are multiplied. - When only one of P and Q is a conjunction, the the number of + When only one of P and Q is a conjunction, the number of clauses are added. Otherwise, neither side is a conjunction and no clauses are created. */ if (disjunction_p (lhs)) diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index c57d570..03a8dfb 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -29078,7 +29078,7 @@ append_type_to_template_for_access_check_1 (tree t, } /* Append TYPE_DECL to the template TEMPL. - TEMPL is either a class type, a FUNCTION_DECL or a a TEMPLATE_DECL. + TEMPL is either a class type, a FUNCTION_DECL or a TEMPLATE_DECL. At TEMPL instanciation time, TYPE_DECL will be checked to see if it can be accessed through SCOPE. LOCATION is the location of the usage point of TYPE_DECL. diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index ea43e3e..32856f1 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,9 @@ +2020-03-18 Jakub Jelinek + + * expr.cc (ExprVisitor::visit (CatAssignExp *)): Fix up duplicated + word issue in a comment. + * d-target.cc (Target::FPTypeProperties::max): Likewise. + 2020-03-16 Iain Buclaw PR d/92309 diff --git a/gcc/d/d-target.cc b/gcc/d/d-target.cc index 4c51b43..7e11bd6 100644 --- a/gcc/d/d-target.cc +++ b/gcc/d/d-target.cc @@ -53,7 +53,7 @@ bool Target::cppExceptions; int Target::classinfosize; unsigned long long Target::maxStaticDataSize; -/* Floating-point constants for for .max, .min, and other properties. */ +/* Floating-point constants for .max, .min, and other properties. */ template real_t Target::FPTypeProperties::max; template real_t Target::FPTypeProperties::min_normal; template real_t Target::FPTypeProperties::nan; diff --git a/gcc/d/expr.cc b/gcc/d/expr.cc index 59777e2..fcf9bc5 100644 --- a/gcc/d/expr.cc +++ b/gcc/d/expr.cc @@ -836,7 +836,7 @@ public: } /* Build a concat assignment expression. The right operand is appended - to the the left operand. */ + to the left operand. */ void visit (CatAssignExp *e) { diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 99b13db..db79f05 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2020-03-18 Jakub Jelinek + + * class.c (generate_finalization_wrapper): Fix up duplicated word + issue in a comment. + * trans-types.c (gfc_get_nodesc_array_type): Likewise. + 2020-03-17 Jakub Jelinek * array.c (gfc_check_iter_variable): Fix up duplicated word issue diff --git a/gcc/fortran/class.c b/gcc/fortran/class.c index 45fd5cb..9aa3eb7 100644 --- a/gcc/fortran/class.c +++ b/gcc/fortran/class.c @@ -1574,7 +1574,7 @@ generate_finalization_wrapper (gfc_symbol *derived, gfc_namespace *ns, } /* No wrapper of the ancestor and no own FINAL subroutines and allocatable - components: Return a NULL() expression; we defer this a bit to have have + components: Return a NULL() expression; we defer this a bit to have an interface declaration. */ if ((!ancestor_wrapper || ancestor_wrapper->expr_type == EXPR_NULL) && !derived->attr.alloc_comp diff --git a/gcc/fortran/trans-types.c b/gcc/fortran/trans-types.c index 8a4c8ee..b7712dc 100644 --- a/gcc/fortran/trans-types.c +++ b/gcc/fortran/trans-types.c @@ -1595,7 +1595,7 @@ gfc_get_nodesc_array_type (tree etype, gfc_array_spec * as, gfc_packed packed, mpz_init_set_ui (stride, 1); mpz_init (delta); - /* We don't use build_array_type because this does not include include + /* We don't use build_array_type because this does not include lang-specific information (i.e. the bounds of the array) when checking for duplicates. */ if (as->rank) diff --git a/gcc/gimple-loop-versioning.cc b/gcc/gimple-loop-versioning.cc index c424b3a..ff6c561 100644 --- a/gcc/gimple-loop-versioning.cc +++ b/gcc/gimple-loop-versioning.cc @@ -1070,7 +1070,7 @@ loop_versioning::analyze_arbitrary_term (address_info &address, where nothing in the way "x" and "y" are set gives a hint as to whether "i" iterates over the innermost dimension of the array. - In these situations it seems reasonable to assume the the + In these situations it seems reasonable to assume the programmer has nested the loops appropriately (although of course there are examples like GEMM in which this assumption doesn't hold for all accesses in the loop). diff --git a/gcc/ipa-predicate.c b/gcc/ipa-predicate.c index 367baf7..27dabf2 100644 --- a/gcc/ipa-predicate.c +++ b/gcc/ipa-predicate.c @@ -497,7 +497,7 @@ predicate::remap_after_duplication (clause_t possible_truths) is summary of function predicate P is from. OPERAND_MAP is array giving callee formal IDs the caller formal IDs. POSSSIBLE_TRUTHS is clause of all callee conditions that may be true in caller context. TOPLEV_PREDICATE is - predicate under which callee is executed. OFFSET_MAP is an array of of + predicate under which callee is executed. OFFSET_MAP is an array of offsets that need to be added to conditions, negative offset means that conditions relying on values passed by reference have to be discarded because they might not be preserved (and should be considered offset zero diff --git a/gcc/optinfo-emit-json.cc b/gcc/optinfo-emit-json.cc index 68762c2..6765c7d 100644 --- a/gcc/optinfo-emit-json.cc +++ b/gcc/optinfo-emit-json.cc @@ -153,7 +153,7 @@ optrecord_json_writer::add_record (const optinfo *optinfo) /* Private methods of optrecord_json_writer. */ -/* Add record OBJ to the the innermost scope. */ +/* Add record OBJ to the innermost scope. */ void optrecord_json_writer::add_record (json::object *obj) diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index f883a1f..6dd37fb 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -2911,7 +2911,7 @@ handle_builtin_strncat (built_in_function, gimple_stmt_iterator *gsi) /* Return true if LEN depends on a call to strlen(SRC) in an interesting way. LEN can either be an integer expression, or a pointer (to char). - When it is the latter (such as in recursive calls to self) is is + When it is the latter (such as in recursive calls to self) it is assumed to be the argument in some call to strlen() whose relationship to SRC is being ascertained. */ diff --git a/gcc/tree-ssa-strlen.h b/gcc/tree-ssa-strlen.h index 12b7df0..a11c4d5 100644 --- a/gcc/tree-ssa-strlen.h +++ b/gcc/tree-ssa-strlen.h @@ -31,7 +31,7 @@ extern tree get_range (tree, wide_int[2], const vr_values * = NULL); struct c_strlen_data; extern void get_range_strlen_dynamic (tree , c_strlen_data *, const vr_values *); -/* APIs internal to strlen pass. Defined in in gimple-ssa-sprintf.c. */ +/* APIs internal to strlen pass. Defined in gimple-ssa-sprintf.c. */ extern bool handle_printf_call (gimple_stmt_iterator *, const vr_values *); #endif // GCC_TREE_SSA_STRLEN_H -- cgit v1.1 From 1ba9acb11e3589b96ed945ed2a3af6acd6377018 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 18 Mar 2020 13:11:30 +0100 Subject: middle-end/94206 fix memset folding to avoid types with padding This makes sure that the store a memset is folded to uses a type covering all bits. 2020-03-18 Richard Biener PR middle-end/94206 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using partial int modes or not mode-precision integer types for the store. * gcc.dg/torture/pr94206.c: New testcase. --- gcc/ChangeLog | 7 +++++++ gcc/gimple-fold.c | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/torture/pr94206.c | 17 +++++++++++++++++ 4 files changed, 35 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 283ad1d..114d299 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-18 Richard Biener + + PR middle-end/94206 + * gimple-fold.c (gimple_fold_builtin_memset): Avoid using + partial int modes or not mode-precision integer types for + the store. + 2020-03-18 Jakub Jelinek * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index 3f17de9..c5939f1 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -1235,12 +1235,18 @@ gimple_fold_builtin_memset (gimple_stmt_iterator *gsi, tree c, tree len) length = tree_to_uhwi (len); if (GET_MODE_SIZE (SCALAR_INT_TYPE_MODE (etype)) != length + || (GET_MODE_PRECISION (SCALAR_INT_TYPE_MODE (etype)) + != GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE (etype))) || get_pointer_alignment (dest) / BITS_PER_UNIT < length) return NULL_TREE; if (length > HOST_BITS_PER_WIDE_INT / BITS_PER_UNIT) return NULL_TREE; + if (!type_has_mode_precision_p (etype)) + etype = lang_hooks.types.type_for_mode (SCALAR_INT_TYPE_MODE (etype), + TYPE_UNSIGNED (etype)); + if (integer_zerop (c)) cval = 0; else diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e8b78df..4aa798f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Richard Biener + + PR middle-end/94206 + * gcc.dg/torture/pr94206.c: New testcase. + 2020-03-18 Duan bo PR target/94201 diff --git a/gcc/testsuite/gcc.dg/torture/pr94206.c b/gcc/testsuite/gcc.dg/torture/pr94206.c new file mode 100644 index 0000000..9e54bba --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr94206.c @@ -0,0 +1,17 @@ +/* { dg-do run { target lp64 } } */ + +struct { + unsigned long x:33; +} s; +typedef __typeof__(s.x + 0) uint33; + +int main() +{ + uint33 x; + __builtin_memset(&x, -1, sizeof x); + unsigned long u; + __builtin_memcpy(&u, &x, sizeof u); + if (u != -1ul) + __builtin_abort (); + return 0; +} -- cgit v1.1 From 11cf25c40e3f586d19474108c78a2dfad7925902 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Wed, 18 Mar 2020 05:16:28 -0700 Subject: PR c++/94147 - mangling of lambdas assigned to globals This patch implements Jason's suggestion of pushing a lambda scope when parsing a global variable initializer. That bit worked fine, but happened to cause g++.dg/opt/dump1.C to not give any used-but-not-defined warnings. The reason was no_linkage_check, which considers any lambda that has an extra-scope to have linkage. Which is technically correct. Except that we think that all types that have linkage have external linkage. Our representation of linkage and visibility is somewhat inaccurate, particularly when it comes to types. We have TREE_PUBLIC, DECL_EXTERNAL, DECL_VISIBILITY, DECL_COMDAT, DECL_NOT_REALLY_EXTERN. It could really do with a through cleanup, but that won't be a simple task. The best I could come up with was seeing if the extra scope was a VAR_DECL, and if that was TREE_PUBLIC and the var was inline (its COMDATness is sadly not set at that point) or a template instantiation, then the lambda had linkage. Otherwise it's as-if it has no-linkage from the POV of compiler internals. This is an ABI change (so we should document it), but it's changing mangling from an unpredictable (in practice) counter, to something the ABI defines. So I'm not concerned about mangling-changed warnings, or preserving the broken mangling under some ABI selection flag. Code that did this worked by accident within a single TU. It'll continue to work by design there, and across TUs. * parser.c (cp_parser_init_declarator): Namespace-scope variables provide a lambda scope. * tree.c (no_linkage_check): Lambdas with a variable for extra scope have a linkage from the variable. --- gcc/cp/ChangeLog | 8 ++++++++ gcc/cp/parser.c | 20 ++++++++++++++------ gcc/cp/tree.c | 20 +++++++++++++++++--- gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 +++++++++++++++++++++++ gcc/testsuite/g++.dg/abi/mangle74.C | 30 ++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 938504b..bb5f77f 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2020-03-18 Nathan Sidwell + + PR c++/94147 - mangling of lambdas assigned to globals + * parser.c (cp_parser_init_declarator): Namespace-scope variables + provide a lambda scope. + * tree.c (no_linkage_check): Lambdas with a variable for extra + scope have a linkage from the variable. + 2020-03-18 Jakub Jelinek * constraint.cc (resolve_function_concept_check, subsumes_constraints, diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 26e0236..198ab97 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -20761,16 +20761,24 @@ cp_parser_init_declarator (cp_parser* parser, else { /* We want to record the extra mangling scope for in-class - initializers of class members and initializers of static data - member templates. The former involves deferring - parsing of the initializer until end of class as with default - arguments. So right here we only handle the latter. */ - if (!member_p && processing_template_decl && decl != error_mark_node) + initializers of class members and initializers of static + data member templates and namespace-scope initializers. + The former involves deferring parsing of the initializer + until end of class as with default arguments. So right + here we only handle the latter two. */ + bool has_lambda_scope = false; + + if (decl != error_mark_node + && !member_p + && (processing_template_decl || DECL_NAMESPACE_SCOPE_P (decl))) + has_lambda_scope = true; + + if (has_lambda_scope) start_lambda_scope (decl); initializer = cp_parser_initializer (parser, &is_direct_init, &is_non_constant_init); - if (!member_p && processing_template_decl && decl != error_mark_node) + if (has_lambda_scope) finish_lambda_scope (); if (initializer == error_mark_node) cp_parser_skip_to_end_of_statement (parser); diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c index a412345..da2e7fd 100644 --- a/gcc/cp/tree.c +++ b/gcc/cp/tree.c @@ -2794,9 +2794,23 @@ no_linkage_check (tree t, bool relaxed_p) fix it up later if not. We need to check this even in templates so that we properly handle a lambda-expression in the signature. */ if (LAMBDA_TYPE_P (t) - && CLASSTYPE_LAMBDA_EXPR (t) != error_mark_node - && LAMBDA_TYPE_EXTRA_SCOPE (t) == NULL_TREE) - return t; + && CLASSTYPE_LAMBDA_EXPR (t) != error_mark_node) + { + tree extra = LAMBDA_TYPE_EXTRA_SCOPE (t); + if (!extra) + return t; + + /* If the mangling scope is internal-linkage or not repeatable + elsewhere, the lambda effectively has no linkage. (Sadly + we're not very careful with the linkages of types.) */ + if (TREE_CODE (extra) == VAR_DECL + && !(TREE_PUBLIC (extra) + && (processing_template_decl + || (DECL_LANG_SPECIFIC (extra) && DECL_USE_TEMPLATE (extra)) + /* DECL_COMDAT is set too late for us to check. */ + || DECL_VAR_DECLARED_INLINE_P (extra)))) + return t; + } /* Otherwise there's no point in checking linkage on template functions; we can't know their complete types. */ diff --git a/gcc/testsuite/g++.dg/abi/lambda-vis.C b/gcc/testsuite/g++.dg/abi/lambda-vis.C new file mode 100644 index 0000000..c3eb157 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/lambda-vis.C @@ -0,0 +1,23 @@ +// { dg-do compile { target c++17 } } +// { dg-options "-fno-inline" } + +template int sfoo (T); // { dg-warning "used but never defined" } +template int gfoo (T); // { dg-warning "used but never defined" } +template int ifoo (T); // OK +template struct Wrapper {}; +template Wrapper capture (T &&) {return Wrapper ();} + +static int svar = sfoo (capture ([]{})); + +int gvar = gfoo (capture ([]{})); + +inline int ivar = ifoo (capture ([]{})); + +// { dg-final { scan-assembler {_Z7captureINL4svarMUlvE_EE7WrapperIT_EOS2_:} } } +// { dg-final { scan-assembler {_Z7captureIN4gvarMUlvE_EE7WrapperIT_EOS2_:} } } +// { dg-final { scan-assembler {_Z7captureIN4ivarMUlvE_EE7WrapperIT_EOS2_:} } } + +// Calls to the foos are emitted. +// { dg-final { scan-assembler {call[ \t]*_Z4sfooI7WrapperINL4svarMUlvE_EEEiT_} { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler {call[ \t]*_Z4gfooI7WrapperIN4gvarMUlvE_EEEiT_} { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler {call[ \t]*_Z4ifooI7WrapperIN4ivarMUlvE_EEEiT_} { target { i?86-*-* x86_64-*-* } } } } diff --git a/gcc/testsuite/g++.dg/abi/mangle74.C b/gcc/testsuite/g++.dg/abi/mangle74.C new file mode 100644 index 0000000..4e1c632 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/mangle74.C @@ -0,0 +1,30 @@ +// { dg-do compile { target c++17 } } +// { dg-options "-fno-inline -O0" } + +inline auto var = [] () {return 2;}; + +int bob () +{ +return var (); +} + +struct Foo +{ + static inline auto bar = [] () {return 4;}; +}; + +int bill () +{ + return Foo::bar (); +} + +// this one should have internal linkage (from svar) +static auto svar = [] () {return 8;}; +int thorn () +{ + return svar (); +} + +// { dg-final { scan-assembler "_ZNK3varMUlvE_clEv:" } } +// { dg-final { scan-assembler "_ZNK3Foo3barMUlvE_clEv:" { xfail *-*-* } } } +// { dg-final { scan-assembler-not "_ZNK3FooUlvE_clEv:" { xfail *-*-* } } } -- cgit v1.1 From 5a80a6c3e5f800de63a2eadd8ae3e6822172a718 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Tue, 3 Mar 2020 17:36:49 +0000 Subject: amdgcn: Add cond_add/sub/and/ior/xor for all vector modes 2020-03-18 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". (cond_): Use VEC_ALLREG_MODE. (cond_): Use VEC_ALLREG_INT_MODE. --- gcc/ChangeLog | 8 ++++++++ gcc/config/gcn/gcn-valu.md | 27 ++++++++++++--------------- 2 files changed, 20 insertions(+), 15 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 114d299..dac1d41 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-18 Andrew Stubbs + + * config/gcn/gcn-valu.md (COND_MODE): Delete. + (COND_INT_MODE): Delete. + (cond_op): Add "mult". + (cond_): Use VEC_ALLREG_MODE. + (cond_): Use VEC_ALLREG_INT_MODE. + 2020-03-18 Richard Biener PR middle-end/94206 diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index a8034f7..68d89fa 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2903,19 +2903,15 @@ DONE; }) -; FIXME this should be VEC_REG_MODE, but not all dependencies are implemented. -(define_mode_iterator COND_MODE [V64SI V64DI V64SF V64DF]) -(define_mode_iterator COND_INT_MODE [V64SI V64DI]) - -(define_code_iterator cond_op [plus minus]) +(define_code_iterator cond_op [plus minus mult]) (define_expand "cond_" - [(match_operand:COND_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_op:COND_MODE - (match_operand:COND_MODE 2 "gcn_alu_operand") - (match_operand:COND_MODE 3 "gcn_alu_operand")) - (match_operand:COND_MODE 4 "register_operand")] + (cond_op:VEC_ALLREG_MODE + (match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]); @@ -2927,15 +2923,16 @@ DONE; }) +;; TODO smin umin smax umax (define_code_iterator cond_bitop [and ior xor]) (define_expand "cond_" - [(match_operand:COND_INT_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_INT_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_bitop:COND_INT_MODE - (match_operand:COND_INT_MODE 2 "gcn_alu_operand") - (match_operand:COND_INT_MODE 3 "gcn_alu_operand")) - (match_operand:COND_INT_MODE 4 "register_operand")] + (cond_bitop:VEC_ALLREG_INT_MODE + (match_operand:VEC_ALLREG_INT_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_INT_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_INT_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]); -- cgit v1.1 From dbde9e2d5952ff1c50c4aeaaabb23cebafb50759 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Tue, 17 Mar 2020 12:49:19 +0000 Subject: amdgcn: Fix vector compare modes The GCN VCC register has 64 CC values in one registers, one bit for each vector lane. Previously we avoided problems with invalid optimizations by not declaring a mode for the comparison operators, but it turns out that causes other problems (and build warnings). Instead, the optimization issues can be avoided by setting STORE_REGISTER_VALUE to -1, meaning that all the bits are significant. (It would be better if we could set STORE_REGISTER_VALUE according to the known mask or vector size, but we can't.) 2020-03-18 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (vec_cmpdi): Set operand 1 to DImode. (vec_cmpdi_dup): Likewise. * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. --- gcc/ChangeLog | 6 ++++++ gcc/config/gcn/gcn-valu.md | 4 ++-- gcc/config/gcn/gcn.h | 4 ++++ 3 files changed, 12 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dac1d41..fcd0272 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2020-03-18 Andrew Stubbs + * config/gcn/gcn-valu.md (vec_cmpdi): Set operand 1 to DImode. + (vec_cmpdi_dup): Likewise. + * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. + +2020-03-18 Andrew Stubbs + * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 68d89fa..d362068 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2549,7 +2549,7 @@ (define_insn "vec_cmpdi" [(set (match_operand:DI 0 "register_operand" "=cV,cV, e, e,Sg,Sg") - (match_operator 1 "gcn_fp_compare_operator" + (match_operator:DI 1 "gcn_fp_compare_operator" [(match_operand:VCMP_MODE 2 "gcn_alu_operand" "vSv, B,vSv, B, v,vA") (match_operand:VCMP_MODE 3 "gcn_vop3_operand" @@ -2658,7 +2658,7 @@ (define_insn "vec_cmpdi_dup" [(set (match_operand:DI 0 "register_operand" "=cV,cV, e,e,Sg") - (match_operator 1 "gcn_fp_compare_operator" + (match_operator:DI 1 "gcn_fp_compare_operator" [(vec_duplicate:VCMP_MODE (match_operand: 2 "gcn_alu_operand" " Sv, B,Sv,B, A")) diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index 0efa99f..9993a99 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -607,6 +607,10 @@ enum gcn_builtin_codes #define SLOW_BYTE_ACCESS 0 #define WORD_REGISTER_OPERATIONS 1 +/* Flag values are either BImode or DImode, but either way the compiler + should assume that all the bits are live. */ +#define STORE_FLAG_VALUE -1 + /* Definitions for register eliminations. This is an array of structures. Each structure initializes one pair -- cgit v1.1 From 0db2cd177020920e187ef47791d52cf689133a25 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 17 Mar 2020 10:25:14 -0400 Subject: analyzer: tweaks to exploded_node ctor I have followup work that touches this, so it's easiest to get this cleanup in first. gcc/analyzer/ChangeLog: * engine.cc (exploded_node::exploded_node): Move implementation here from header; accept point_and_state by const reference rather than by value. * exploded-graph.h (exploded_node::exploded_node): Pass point_and_state by const reference rather than by value. Move body to engine.cc. --- gcc/analyzer/ChangeLog | 9 +++++++++ gcc/analyzer/engine.cc | 11 +++++++++++ gcc/analyzer/exploded-graph.h | 7 +------ 3 files changed, 21 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index a5c8b27..ace456c 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,12 @@ +2020-03-18 David Malcolm + + * engine.cc (exploded_node::exploded_node): Move implementation + here from header; accept point_and_state by const reference rather + than by value. + * exploded-graph.h (exploded_node::exploded_node): Pass + point_and_state by const reference rather than by value. Move + body to engine.cc. + 2020-03-18 Jakub Jelinek * sm-malloc.cc (malloc_state_machine::on_stmt): Fix up duplicated word diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc index a8037c6..369110b 100644 --- a/gcc/analyzer/engine.cc +++ b/gcc/analyzer/engine.cc @@ -795,6 +795,17 @@ print_enode_indices (pretty_printer *pp, } } +/* class exploded_node : public dnode. */ + +/* exploded_node's ctor. */ + +exploded_node::exploded_node (const point_and_state &ps, + int index) +: m_ps (ps), m_status (STATUS_WORKLIST), m_index (index) +{ + gcc_checking_assert (ps.get_state ().m_region_model->canonicalized_p ()); +} + /* For use by dump_dot, get a value for the .dot "fillcolor" attribute. Colorize by sm-state, to make it easier to see how sm-state propagates through the exploded_graph. */ diff --git a/gcc/analyzer/exploded-graph.h b/gcc/analyzer/exploded-graph.h index c0a520a..b9a5618 100644 --- a/gcc/analyzer/exploded-graph.h +++ b/gcc/analyzer/exploded-graph.h @@ -175,12 +175,7 @@ class exploded_node : public dnode STATUS_MERGER }; - exploded_node (point_and_state ps, - int index) - : m_ps (ps), m_status (STATUS_WORKLIST), m_index (index) - { - gcc_checking_assert (ps.get_state ().m_region_model->canonicalized_p ()); - } + exploded_node (const point_and_state &ps, int index); hashval_t hash () const { return m_ps.hash (); } -- cgit v1.1 From 7d9c107ab1eab331e7011513b11e26b78850d614 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 17 Mar 2020 14:43:43 -0400 Subject: analyzer: introduce noop_region_model_context tentative_region_model_context and test_region_model_context are both forced to implement numerous pure virtual vfuncs of the abstract region_model_context. This patch adds a noop_region_model_context which provides empty implementations of all of region_model_context's pure virtual functions, and subclasses the above classes from that, rather than from region_model_context directly. gcc/analyzer/ChangeLog: * region-model.h (class noop_region_model_context): New subclass of region_model_context. (class tentative_region_model_context): Inherit from noop_region_model_context rather than from region_model_context; drop redundant vfunc implementations. (class test_region_model_context): Likewise. --- gcc/analyzer/ChangeLog | 9 +++++ gcc/analyzer/region-model.h | 84 +++++++++++++-------------------------------- 2 files changed, 32 insertions(+), 61 deletions(-) (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index ace456c..110a845 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,5 +1,14 @@ 2020-03-18 David Malcolm + * region-model.h (class noop_region_model_context): New subclass + of region_model_context. + (class tentative_region_model_context): Inherit from + noop_region_model_context rather than from region_model_context; + drop redundant vfunc implementations. + (class test_region_model_context): Likewise. + +2020-03-18 David Malcolm + * engine.cc (exploded_node::exploded_node): Move implementation here from header; accept point_and_state by const reference rather than by value. diff --git a/gcc/analyzer/region-model.h b/gcc/analyzer/region-model.h index c1fe592..035b611 100644 --- a/gcc/analyzer/region-model.h +++ b/gcc/analyzer/region-model.h @@ -1972,42 +1972,50 @@ class region_model_context const dump_location_t &loc) = 0; }; -/* A subclass of region_model_context for determining if operations fail - e.g. "can we generate a region for the lvalue of EXPR?". */ +/* A "do nothing" subclass of region_model_context. */ -class tentative_region_model_context : public region_model_context +class noop_region_model_context : public region_model_context { public: - tentative_region_model_context () : m_num_unexpected_codes (0) {} - - void warn (pending_diagnostic *) FINAL OVERRIDE {} - void remap_svalue_ids (const svalue_id_map &) FINAL OVERRIDE {} - int on_svalue_purge (svalue_id, const svalue_id_map &) FINAL OVERRIDE + void warn (pending_diagnostic *) OVERRIDE {} + void remap_svalue_ids (const svalue_id_map &) OVERRIDE {} + int on_svalue_purge (svalue_id, const svalue_id_map &) OVERRIDE { return 0; } - logger *get_logger () FINAL OVERRIDE { return NULL; } + logger *get_logger () OVERRIDE { return NULL; } void on_inherited_svalue (svalue_id parent_sid ATTRIBUTE_UNUSED, svalue_id child_sid ATTRIBUTE_UNUSED) - FINAL OVERRIDE + OVERRIDE { } void on_cast (svalue_id src_sid ATTRIBUTE_UNUSED, - svalue_id dst_sid ATTRIBUTE_UNUSED) FINAL OVERRIDE + svalue_id dst_sid ATTRIBUTE_UNUSED) OVERRIDE { } void on_condition (tree lhs ATTRIBUTE_UNUSED, enum tree_code op ATTRIBUTE_UNUSED, - tree rhs ATTRIBUTE_UNUSED) FINAL OVERRIDE + tree rhs ATTRIBUTE_UNUSED) OVERRIDE { } - void on_unknown_change (svalue_id sid ATTRIBUTE_UNUSED) FINAL OVERRIDE + void on_unknown_change (svalue_id sid ATTRIBUTE_UNUSED) OVERRIDE { } void on_phi (const gphi *phi ATTRIBUTE_UNUSED, - tree rhs ATTRIBUTE_UNUSED) FINAL OVERRIDE + tree rhs ATTRIBUTE_UNUSED) OVERRIDE { } + void on_unexpected_tree_code (tree, const dump_location_t &) OVERRIDE {} +}; + +/* A subclass of region_model_context for determining if operations fail + e.g. "can we generate a region for the lvalue of EXPR?". */ + +class tentative_region_model_context : public noop_region_model_context +{ +public: + tentative_region_model_context () : m_num_unexpected_codes (0) {} + void on_unexpected_tree_code (tree, const dump_location_t &) FINAL OVERRIDE { @@ -2143,7 +2151,7 @@ using namespace ::selftest; /* An implementation of region_model_context for use in selftests, which stores any pending_diagnostic instances passed to it. */ -class test_region_model_context : public region_model_context +class test_region_model_context : public noop_region_model_context { public: void warn (pending_diagnostic *d) FINAL OVERRIDE @@ -2151,54 +2159,8 @@ public: m_diagnostics.safe_push (d); } - void remap_svalue_ids (const svalue_id_map &) FINAL OVERRIDE - { - /* Empty. */ - } - -#if 0 - bool can_purge_p (svalue_id) FINAL OVERRIDE - { - return true; - } -#endif - - int on_svalue_purge (svalue_id, const svalue_id_map &) FINAL OVERRIDE - { - /* Empty. */ - return 0; - } - - logger *get_logger () FINAL OVERRIDE { return NULL; } - - void on_inherited_svalue (svalue_id parent_sid ATTRIBUTE_UNUSED, - svalue_id child_sid ATTRIBUTE_UNUSED) - FINAL OVERRIDE - { - } - - void on_cast (svalue_id src_sid ATTRIBUTE_UNUSED, - svalue_id dst_sid ATTRIBUTE_UNUSED) FINAL OVERRIDE - { - } - unsigned get_num_diagnostics () const { return m_diagnostics.length (); } - void on_condition (tree lhs ATTRIBUTE_UNUSED, - enum tree_code op ATTRIBUTE_UNUSED, - tree rhs ATTRIBUTE_UNUSED) FINAL OVERRIDE - { - } - - void on_unknown_change (svalue_id sid ATTRIBUTE_UNUSED) FINAL OVERRIDE - { - } - - void on_phi (const gphi *phi ATTRIBUTE_UNUSED, - tree rhs ATTRIBUTE_UNUSED) FINAL OVERRIDE - { - } - void on_unexpected_tree_code (tree t, const dump_location_t &) FINAL OVERRIDE { -- cgit v1.1 From f665beeba625490bd96a593d23e00726d969cf98 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 10 Mar 2020 18:50:03 -0400 Subject: analyzer: add test coverage for fixed ICE [PR94047] PR analyzer/94047 reports an ICE, which turned out to be caused by the erroneous use of TREE_TYPE on the view region's type in region_model::get_representative_path_var that I introduced in r10-7024-ge516294a1acb28aaaad44cfd583cc6a80354044e and fixed in g:787477a226033e36be3f6d16b71be13dd917e982. This patch adds a regression test for the ICE. gcc/testsuite/ChangeLog: PR analyzer/94047 * gcc.dg/analyzer/pr94047.c: New test. --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4aa798f..a91d737 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 David Malcolm + + PR analyzer/94047 + * gcc.dg/analyzer/pr94047.c: New test. + 2020-03-18 Richard Biener PR middle-end/94206 diff --git a/gcc/testsuite/gcc.dg/analyzer/pr94047.c b/gcc/testsuite/gcc.dg/analyzer/pr94047.c new file mode 100644 index 0000000..d989a25 --- /dev/null +++ b/gcc/testsuite/gcc.dg/analyzer/pr94047.c @@ -0,0 +1,23 @@ +/* { dg-additional-options "-Wno-analyzer-too-complex" } */ +/* TODO: the above ought not to be necessary, but currently is due to a + state explosion within the for loop. */ + +typedef struct list +{ + struct list *next; +} tlist; + +void +bar (struct list *l) +{ + l->next = l->next->next; +} + +void +foo (void) +{ + struct list l; + tlist t = l; + for (;;) + bar (&t); +} -- cgit v1.1 From 884d914111228eed977d794f38e4cc88bf132a58 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Wed, 11 Mar 2020 17:06:41 -0400 Subject: analyzer: make summarized dumps more comprehensive The previous implementation of summarized dumps within region_model::dump_to_pp showed only the "top-level" keys within the current frame and for globals, and thus didn't e.g. show the values of fields of structs, or elements of arrays. This patch rewrites it to gather a vec of representative path_vars for all regions, using this to generate the dump, so that all expressible lvalues ought to make it to the summarized dump. gcc/analyzer/ChangeLog: * region-model.cc: Include "stor-layout.h". (region_model::dump_to_pp): Rather than calling dump_summary_of_map on each of the current frame and the globals, instead get a vec of representative path_vars for all regions, and then dump a summary of all of them. (region_model::dump_summary_of_map): Delete, rewriting into... (region_model::dump_summary_of_rep_path_vars): ...this new function, working on a vec of path_vars. (region_model::set_value): New overload. (region_model::get_representative_path_var): Rename "parent_region" local to "parent_reg" and consolidate with other local. Guard test for grandparent being stack on parent_reg being non-NULL. Move handling for parent being an array_region to within guard for parent_reg being non-NULL. (selftest::make_test_compound_type): New function. (selftest::test_dump_2): New selftest. (selftest::test_dump_3): New selftest. (selftest::test_stack_frames): Update expected output from simplified dump to show "a" and "b" from parent frame and "y" in child frame. (selftest::analyzer_region_model_cc_tests): Call test_dump_2 and test_dump_3. * region-model.h (region_model::set_value): New overload decl. (region_model::dump_summary_of_map): Delete. (region_model::dump_summary_of_rep_path_vars): New. --- gcc/analyzer/ChangeLog | 28 +++++ gcc/analyzer/region-model.cc | 261 ++++++++++++++++++++++++++++++++----------- gcc/analyzer/region-model.h | 6 +- 3 files changed, 227 insertions(+), 68 deletions(-) (limited to 'gcc') diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 110a845..0219cb3 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,5 +1,33 @@ 2020-03-18 David Malcolm + * region-model.cc: Include "stor-layout.h". + (region_model::dump_to_pp): Rather than calling + dump_summary_of_map on each of the current frame and the globals, + instead get a vec of representative path_vars for all regions, + and then dump a summary of all of them. + (region_model::dump_summary_of_map): Delete, rewriting into... + (region_model::dump_summary_of_rep_path_vars): ...this new + function, working on a vec of path_vars. + (region_model::set_value): New overload. + (region_model::get_representative_path_var): Rename + "parent_region" local to "parent_reg" and consolidate with other + local. Guard test for grandparent being stack on parent_reg being + non-NULL. Move handling for parent being an array_region to + within guard for parent_reg being non-NULL. + (selftest::make_test_compound_type): New function. + (selftest::test_dump_2): New selftest. + (selftest::test_dump_3): New selftest. + (selftest::test_stack_frames): Update expected output from + simplified dump to show "a" and "b" from parent frame and "y" in + child frame. + (selftest::analyzer_region_model_cc_tests): Call test_dump_2 and + test_dump_3. + * region-model.h (region_model::set_value): New overload decl. + (region_model::dump_summary_of_map): Delete. + (region_model::dump_summary_of_rep_path_vars): New. + +2020-03-18 David Malcolm + * region-model.h (class noop_region_model_context): New subclass of region_model_context. (class tentative_region_model_context): Inherit from diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 9cc6560..a71d3de 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -59,6 +59,7 @@ along with GCC; see the file COPYING3. If not see #include "analyzer/sm.h" #include "analyzer/pending-diagnostic.h" #include "analyzer/analyzer-selftests.h" +#include "stor-layout.h" #if ENABLE_ANALYZER @@ -3538,7 +3539,7 @@ region_model::dump_dot (const char *path) const /* Dump a multiline representation of this model to PP, showing the region hierarchy, the svalues, and any constraints. - If SUMMARIZE is true, show only the most pertient information, + If SUMMARIZE is true, show only the most pertinent information, in a form that attempts to be less verbose. Otherwise, show all information. */ @@ -3547,18 +3548,23 @@ region_model::dump_to_pp (pretty_printer *pp, bool summarize) const { if (summarize) { - bool is_first = true; - region_id frame_id = get_current_frame_id (); - frame_region *frame = get_region (frame_id); - if (frame) - dump_summary_of_map (pp, frame, &is_first); - - region_id globals_id = get_globals_region_id (); - map_region *globals = get_region (globals_id); - if (globals) - dump_summary_of_map (pp, globals, &is_first); + auto_vec rep_path_vars; unsigned i; + region *reg; + FOR_EACH_VEC_ELT (m_regions, i, reg) + { + region_id rid = region_id::from_int (i); + path_var pv = get_representative_path_var (rid); + if (pv.m_tree) + rep_path_vars.safe_push (pv); + } + bool is_first = true; + + /* Work with a copy in case the get_lvalue calls change anything + (they shouldn't). */ + region_model copy (*this); + copy.dump_summary_of_rep_path_vars (pp, &rep_path_vars, &is_first); equiv_class *ec; FOR_EACH_VEC_ELT (m_constraints->m_equiv_classes, i, ec) @@ -3680,37 +3686,28 @@ dump_vec_of_tree (pretty_printer *pp, pp_printf (pp, "}: %s", label); } -/* Dump *MAP_REGION to PP in compact form, updating *IS_FIRST. - Subroutine of region_model::dump_to_pp for use on stack frames and for - the "globals" region. */ +/* Dump all *REP_PATH_VARS to PP in compact form, updating *IS_FIRST. + Subroutine of region_model::dump_to_pp. */ void -region_model::dump_summary_of_map (pretty_printer *pp, - map_region *map_region, - bool *is_first) const -{ - /* Get the keys, sorted by tree_cmp. In particular, this ought - to alphabetize any decls. */ - auto_vec keys (map_region->elements ()); - for (map_region::iterator_t iter = map_region->begin (); - iter != map_region->end (); - ++iter) - { - tree key_a = (*iter).first; - keys.quick_push (key_a); - } - keys.qsort (tree_cmp); - +region_model::dump_summary_of_rep_path_vars (pretty_printer *pp, + auto_vec *rep_path_vars, + bool *is_first) +{ /* Print pointers, constants, and poisoned values that aren't "uninit"; gather keys for unknown and uninit values. */ unsigned i; - tree key; - auto_vec unknown_keys; - auto_vec uninit_keys; - FOR_EACH_VEC_ELT (keys, i, key) + path_var *pv; + auto_vec unknown_trees; + auto_vec uninit_trees; + FOR_EACH_VEC_ELT (*rep_path_vars, i, pv) { - region_id child_rid = *map_region->get (key); - + if (TREE_CODE (pv->m_tree) == STRING_CST) + continue; + tentative_region_model_context ctxt; + region_id child_rid = get_lvalue (*pv, &ctxt); + if (ctxt.had_errors_p ()) + continue; region *child_region = get_region (child_rid); if (!child_region) continue; @@ -3729,7 +3726,7 @@ region_model::dump_summary_of_map (pretty_printer *pp, gcc_assert (!pointee_rid.null_p ()); tree pointee = get_representative_path_var (pointee_rid).m_tree; dump_separator (pp, is_first); - dump_tree (pp, key); + dump_tree (pp, pv->m_tree); pp_string (pp, ": "); pp_character (pp, '&'); if (pointee) @@ -3740,23 +3737,23 @@ region_model::dump_summary_of_map (pretty_printer *pp, break; case SK_CONSTANT: dump_separator (pp, is_first); - dump_tree (pp, key); + dump_tree (pp, pv->m_tree); pp_string (pp, ": "); dump_tree (pp, sval->dyn_cast_constant_svalue ()->get_constant ()); break; case SK_UNKNOWN: - unknown_keys.safe_push (key); + unknown_trees.safe_push (pv->m_tree); break; case SK_POISONED: { poisoned_svalue *poisoned_sval = as_a (sval); enum poison_kind pkind = poisoned_sval->get_poison_kind (); if (pkind == POISON_KIND_UNINIT) - uninit_keys.safe_push (key); + uninit_trees.safe_push (pv->m_tree); else { dump_separator (pp, is_first); - dump_tree (pp, key); + dump_tree (pp, pv->m_tree); pp_printf (pp, ": %s", poison_kind_to_str (pkind)); } } @@ -3770,8 +3767,8 @@ region_model::dump_summary_of_map (pretty_printer *pp, } /* Print unknown and uninitialized values in consolidated form. */ - dump_vec_of_tree (pp, is_first, unknown_keys, "unknown"); - dump_vec_of_tree (pp, is_first, uninit_keys, "uninit"); + dump_vec_of_tree (pp, is_first, unknown_trees, "unknown"); + dump_vec_of_tree (pp, is_first, uninit_trees, "uninit"); } /* Assert that this object is valid. */ @@ -5355,6 +5352,19 @@ region_model::set_value (region_id lhs_rid, svalue_id rhs_sid, get_region (lhs_rid)->set_value (*this, lhs_rid, rhs_sid, ctxt); } +/* Set the value of the region given by LHS to the value given + by RHS. */ + +void +region_model::set_value (tree lhs, tree rhs, region_model_context *ctxt) +{ + region_id lhs_rid = get_lvalue (lhs, ctxt); + svalue_id rhs_sid = get_rvalue (rhs, ctxt); + gcc_assert (!lhs_rid.null_p ()); + gcc_assert (!rhs_sid.null_p ()); + set_value (lhs_rid, rhs_sid, ctxt); +} + /* Determine what is known about the condition "LHS_SID OP RHS_SID" within this model. */ @@ -5735,12 +5745,12 @@ path_var region_model::get_representative_path_var (region_id rid) const { region *reg = get_region (rid); - region *parent_region = get_region (reg->get_parent ()); + region *parent_reg = get_region (reg->get_parent ()); region_id stack_rid = get_stack_region_id (); if (!stack_rid.null_p ()) - if (parent_region->get_parent () == stack_rid) + if (parent_reg && parent_reg->get_parent () == stack_rid) { - frame_region *parent_frame = (frame_region *)parent_region; + frame_region *parent_frame = (frame_region *)parent_reg; tree t = parent_frame->get_tree_for_child_region (rid); return path_var (t, parent_frame->get_depth ()); } @@ -5753,7 +5763,6 @@ region_model::get_representative_path_var (region_id rid) const /* Handle e.g. fields of a local by recursing. */ region_id parent_rid = reg->get_parent (); - region *parent_reg = get_region (parent_rid); if (parent_reg) { if (reg->is_view_p ()) @@ -5782,25 +5791,25 @@ region_model::get_representative_path_var (region_id rid) const parent_pv.m_stack_depth); } } - } - /* Handle elements within an array. */ - if (array_region *array_reg = parent_region->dyn_cast_array_region ()) - { - array_region::key_t key; - if (array_reg->get_key_for_child_region (rid, &key)) - { - path_var parent_pv = get_representative_path_var (parent_rid); - if (parent_pv.m_tree && reg->get_type ()) - { - tree index = array_reg->constant_from_key (key); - return path_var (build4 (ARRAY_REF, - reg->get_type (), - parent_pv.m_tree, index, - NULL_TREE, NULL_TREE), - parent_pv.m_stack_depth); - } - } + /* Handle elements within an array. */ + if (array_region *array_reg = parent_reg->dyn_cast_array_region ()) + { + array_region::key_t key; + if (array_reg->get_key_for_child_region (rid, &key)) + { + path_var parent_pv = get_representative_path_var (parent_rid); + if (parent_pv.m_tree && reg->get_type ()) + { + tree index = array_reg->constant_from_key (key); + return path_var (build4 (ARRAY_REF, + reg->get_type (), + parent_pv.m_tree, index, + NULL_TREE, NULL_TREE), + parent_pv.m_stack_depth); + } + } + } } /* Handle string literals. */ @@ -7400,6 +7409,124 @@ test_dump () ASSERT_DUMP_EQ (model, true, ""); } +/* Helper function for selftests. Create a struct or union type named NAME, + with the fields given by the FIELD_DECLS in FIELDS. + If IS_STRUCT is true create a RECORD_TYPE (aka a struct), otherwise + create a UNION_TYPE. */ + +static tree +make_test_compound_type (const char *name, bool is_struct, + const auto_vec *fields) +{ + tree t = make_node (is_struct ? RECORD_TYPE : UNION_TYPE); + TYPE_NAME (t) = get_identifier (name); + TYPE_SIZE (t) = 0; + + tree fieldlist = NULL; + int i; + tree field; + FOR_EACH_VEC_ELT (*fields, i, field) + { + gcc_assert (TREE_CODE (field) == FIELD_DECL); + DECL_CONTEXT (field) = t; + fieldlist = chainon (field, fieldlist); + } + fieldlist = nreverse (fieldlist); + TYPE_FIELDS (t) = fieldlist; + + layout_type (t); + return t; +} + +/* Verify that dumps can show struct fields. */ + +static void +test_dump_2 () +{ + auto_vec fields; + tree x_field = build_decl (UNKNOWN_LOCATION, FIELD_DECL, + get_identifier ("x"), integer_type_node); + fields.safe_push (x_field); + tree y_field = build_decl (UNKNOWN_LOCATION, FIELD_DECL, + get_identifier ("y"), integer_type_node); + fields.safe_push (y_field); + tree coord_type = make_test_compound_type ("coord", true, &fields); + + tree c = build_global_decl ("c", coord_type); + tree c_x = build3 (COMPONENT_REF, TREE_TYPE (x_field), + c, x_field, NULL_TREE); + tree c_y = build3 (COMPONENT_REF, TREE_TYPE (y_field), + c, y_field, NULL_TREE); + + tree int_17 = build_int_cst (integer_type_node, 17); + tree int_m3 = build_int_cst (integer_type_node, -3); + + region_model model; + model.set_value (c_x, int_17, NULL); + model.set_value (c_y, int_m3, NULL); + + /* Simplified dump. */ + ASSERT_DUMP_EQ (model, true, "c.x: 17, c.y: -3"); + + /* Full dump. */ + ASSERT_DUMP_EQ + (model, false, + "r0: {kind: `root', parent: null, sval: null}\n" + "`-globals: r1: {kind: `globals', parent: r0, sval: null, map: {`c': r2}}\n" + " `-`c': r2: {kind: `struct', parent: r1, sval: null, type: `struct coord', map: {`x': r3, `y': r4}}\n" + " |: type: `struct coord'\n" + " |-`x': r3: {kind: `primitive', parent: r2, sval: sv0, type: `int'}\n" + " | |: sval: sv0: {type: `int', `17'}\n" + " | |: type: `int'\n" + " `-`y': r4: {kind: `primitive', parent: r2, sval: sv1, type: `int'}\n" + " |: sval: sv1: {type: `int', `-3'}\n" + " |: type: `int'\n" + "svalues:\n" + " sv0: {type: `int', `17'}\n" + " sv1: {type: `int', `-3'}\n" + "constraint manager:\n" + " equiv classes:\n" + " constraints:\n"); +} + +/* Verify that dumps can show array elements. */ + +static void +test_dump_3 () +{ + tree tlen = size_int (10); + tree arr_type = build_array_type (char_type_node, build_index_type (tlen)); + + tree a = build_global_decl ("a", arr_type); + + region_model model; + tree int_0 = build_int_cst (integer_type_node, 0); + tree a_0 = build4 (ARRAY_REF, char_type_node, + a, int_0, NULL_TREE, NULL_TREE); + tree char_A = build_int_cst (char_type_node, 'A'); + model.set_value (a_0, char_A, NULL); + + /* Simplified dump. */ + ASSERT_DUMP_EQ (model, true, "a[0]: 65"); + + /* Full dump. */ + ASSERT_DUMP_EQ + (model, false, + "r0: {kind: `root', parent: null, sval: null}\n" + "`-globals: r1: {kind: `globals', parent: r0, sval: null, map: {`a': r2}}\n" + " `-`a': r2: {kind: `array', parent: r1, sval: null, type: `char[11]', array: {[0]: r3}}\n" + " |: type: `char[11]'\n" + " `-[0]: r3: {kind: `primitive', parent: r2, sval: sv1, type: `char'}\n" + " |: sval: sv1: {type: `char', `65'}\n" + " |: type: `char'\n" + "svalues:\n" + " sv0: {type: `int', `0'}\n" + " sv1: {type: `char', `65'}\n" + "constraint manager:\n" + " equiv classes:\n" + " constraints:\n"); +} + /* Verify that region_model::get_representative_tree works as expected. */ static void @@ -7834,7 +7961,7 @@ test_stack_frames () #endif ASSERT_DUMP_EQ (model, true, - "x: 0, {y}: unknown, p: &x, q: &p, b < 10, y != 5"); + "a: 42, x: 0, p: &x, q: &p, {b, y}: unknown, b < 10, y != 5"); /* Pop the "child_fn" frame from the stack. */ purge_stats purged; @@ -8475,6 +8602,8 @@ analyzer_region_model_cc_tests () { test_tree_cmp_on_constants (); test_dump (); + test_dump_2 (); + test_dump_3 (); test_get_representative_tree (); test_unique_constants (); test_svalue_equality (); diff --git a/gcc/analyzer/region-model.h b/gcc/analyzer/region-model.h index 035b611..65e6600 100644 --- a/gcc/analyzer/region-model.h +++ b/gcc/analyzer/region-model.h @@ -1771,6 +1771,7 @@ class region_model void set_value (region_id lhs_rid, svalue_id rhs_sid, region_model_context *ctxt); + void set_value (tree lhs, tree rhs, region_model_context *ctxt); svalue_id set_to_new_unknown_value (region_id dst_rid, tree type, region_model_context *ctxt); @@ -1884,8 +1885,9 @@ class region_model void poison_any_pointers_to_bad_regions (const region_id_set &bad_regions, enum poison_kind pkind); - void dump_summary_of_map (pretty_printer *pp, map_region *map_region, - bool *is_first) const; + void dump_summary_of_rep_path_vars (pretty_printer *pp, + auto_vec *rep_path_vars, + bool *is_first); auto_delete_vec m_svalues; auto_delete_vec m_regions; -- cgit v1.1 From 8165795c1555c83c0c6c68650321540f9253d461 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 16:26:53 +0000 Subject: [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. This patch supports following MVE ACLE intrinsics with ternary operands. vpselq_u8, vpselq_s8, vrev64q_m_u8, vqrdmlashq_n_u8, vqrdmlahq_n_u8, vqdmlahq_n_u8, vmvnq_m_u8, vmlasq_n_u8, vmlaq_n_u8, vmladavq_p_u8, vmladavaq_u8, vminvq_p_u8, vmaxvq_p_u8, vdupq_m_n_u8, vcmpneq_m_u8, vcmpneq_m_n_u8, vcmphiq_m_u8, vcmphiq_m_n_u8, vcmpeqq_m_u8, vcmpeqq_m_n_u8, vcmpcsq_m_u8, vcmpcsq_m_n_u8, vclzq_m_u8, vaddvaq_p_u8, vsriq_n_u8, vsliq_n_u8, vshlq_m_r_u8, vrshlq_m_n_u8, vqshlq_m_r_u8, vqrshlq_m_n_u8, vminavq_p_s8, vminaq_m_s8, vmaxavq_p_s8, vmaxaq_m_s8, vcmpneq_m_s8, vcmpneq_m_n_s8, vcmpltq_m_s8, vcmpltq_m_n_s8, vcmpleq_m_s8, vcmpleq_m_n_s8, vcmpgtq_m_s8, vcmpgtq_m_n_s8, vcmpgeq_m_s8, vcmpgeq_m_n_s8, vcmpeqq_m_s8, vcmpeqq_m_n_s8, vshlq_m_r_s8, vrshlq_m_n_s8, vrev64q_m_s8, vqshlq_m_r_s8, vqrshlq_m_n_s8, vqnegq_m_s8, vqabsq_m_s8, vnegq_m_s8, vmvnq_m_s8, vmlsdavxq_p_s8, vmlsdavq_p_s8, vmladavxq_p_s8, vmladavq_p_s8, vminvq_p_s8, vmaxvq_p_s8, vdupq_m_n_s8, vclzq_m_s8, vclsq_m_s8, vaddvaq_p_s8, vabsq_m_s8, vqrdmlsdhxq_s8, vqrdmlsdhq_s8, vqrdmlashq_n_s8, vqrdmlahq_n_s8, vqrdmladhxq_s8, vqrdmladhq_s8, vqdmlsdhxq_s8, vqdmlsdhq_s8, vqdmlahq_n_s8, vqdmladhxq_s8, vqdmladhq_s8, vmlsdavaxq_s8, vmlsdavaq_s8, vmlasq_n_s8, vmlaq_n_s8, vmladavaxq_s8, vmladavaq_s8, vsriq_n_s8, vsliq_n_s8, vpselq_u16, vpselq_s16, vrev64q_m_u16, vqrdmlashq_n_u16, vqrdmlahq_n_u16, vqdmlahq_n_u16, vmvnq_m_u16, vmlasq_n_u16, vmlaq_n_u16, vmladavq_p_u16, vmladavaq_u16, vminvq_p_u16, vmaxvq_p_u16, vdupq_m_n_u16, vcmpneq_m_u16, vcmpneq_m_n_u16, vcmphiq_m_u16, vcmphiq_m_n_u16, vcmpeqq_m_u16, vcmpeqq_m_n_u16, vcmpcsq_m_u16, vcmpcsq_m_n_u16, vclzq_m_u16, vaddvaq_p_u16, vsriq_n_u16, vsliq_n_u16, vshlq_m_r_u16, vrshlq_m_n_u16, vqshlq_m_r_u16, vqrshlq_m_n_u16, vminavq_p_s16, vminaq_m_s16, vmaxavq_p_s16, vmaxaq_m_s16, vcmpneq_m_s16, vcmpneq_m_n_s16, vcmpltq_m_s16, vcmpltq_m_n_s16, vcmpleq_m_s16, vcmpleq_m_n_s16, vcmpgtq_m_s16, vcmpgtq_m_n_s16, vcmpgeq_m_s16, vcmpgeq_m_n_s16, vcmpeqq_m_s16, vcmpeqq_m_n_s16, vshlq_m_r_s16, vrshlq_m_n_s16, vrev64q_m_s16, vqshlq_m_r_s16, vqrshlq_m_n_s16, vqnegq_m_s16, vqabsq_m_s16, vnegq_m_s16, vmvnq_m_s16, vmlsdavxq_p_s16, vmlsdavq_p_s16, vmladavxq_p_s16, vmladavq_p_s16, vminvq_p_s16, vmaxvq_p_s16, vdupq_m_n_s16, vclzq_m_s16, vclsq_m_s16, vaddvaq_p_s16, vabsq_m_s16, vqrdmlsdhxq_s16, vqrdmlsdhq_s16, vqrdmlashq_n_s16, vqrdmlahq_n_s16, vqrdmladhxq_s16, vqrdmladhq_s16, vqdmlsdhxq_s16, vqdmlsdhq_s16, vqdmlahq_n_s16, vqdmladhxq_s16, vqdmladhq_s16, vmlsdavaxq_s16, vmlsdavaq_s16, vmlasq_n_s16, vmlaq_n_s16, vmladavaxq_s16, vmladavaq_s16, vsriq_n_s16, vsliq_n_s16, vpselq_u32, vpselq_s32, vrev64q_m_u32, vqrdmlashq_n_u32, vqrdmlahq_n_u32, vqdmlahq_n_u32, vmvnq_m_u32, vmlasq_n_u32, vmlaq_n_u32, vmladavq_p_u32, vmladavaq_u32, vminvq_p_u32, vmaxvq_p_u32, vdupq_m_n_u32, vcmpneq_m_u32, vcmpneq_m_n_u32, vcmphiq_m_u32, vcmphiq_m_n_u32, vcmpeqq_m_u32, vcmpeqq_m_n_u32, vcmpcsq_m_u32, vcmpcsq_m_n_u32, vclzq_m_u32, vaddvaq_p_u32, vsriq_n_u32, vsliq_n_u32, vshlq_m_r_u32, vrshlq_m_n_u32, vqshlq_m_r_u32, vqrshlq_m_n_u32, vminavq_p_s32, vminaq_m_s32, vmaxavq_p_s32, vmaxaq_m_s32, vcmpneq_m_s32, vcmpneq_m_n_s32, vcmpltq_m_s32, vcmpltq_m_n_s32, vcmpleq_m_s32, vcmpleq_m_n_s32, vcmpgtq_m_s32, vcmpgtq_m_n_s32, vcmpgeq_m_s32, vcmpgeq_m_n_s32, vcmpeqq_m_s32, vcmpeqq_m_n_s32, vshlq_m_r_s32, vrshlq_m_n_s32, vrev64q_m_s32, vqshlq_m_r_s32, vqrshlq_m_n_s32, vqnegq_m_s32, vqabsq_m_s32, vnegq_m_s32, vmvnq_m_s32, vmlsdavxq_p_s32, vmlsdavq_p_s32, vmladavxq_p_s32, vmladavq_p_s32, vminvq_p_s32, vmaxvq_p_s32, vdupq_m_n_s32, vclzq_m_s32, vclsq_m_s32, vaddvaq_p_s32, vabsq_m_s32, vqrdmlsdhxq_s32, vqrdmlsdhq_s32, vqrdmlashq_n_s32, vqrdmlahq_n_s32, vqrdmladhxq_s32, vqrdmladhq_s32, vqdmlsdhxq_s32, vqdmlsdhq_s32, vqdmlahq_n_s32, vqdmladhxq_s32, vqdmladhq_s32, vmlsdavaxq_s32, vmlsdavaq_s32, vmlasq_n_s32, vmlaq_n_s32, vmladavaxq_s32, vmladavaq_s32, vsriq_n_s32, vsliq_n_s32, vpselq_u64, vpselq_s64. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch new constraints "Rc" and "Re" are added, which checks the constant is with in the range of 0 to 15 and 0 to 31 respectively. Also a new predicates "mve_imm_15" and "mve_imm_31" are added, to check the the matching constraint Rc and Re respectively. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vpselq_u8): Define macro. (vpselq_s8): Likewise. (vrev64q_m_u8): Likewise. (vqrdmlashq_n_u8): Likewise. (vqrdmlahq_n_u8): Likewise. (vqdmlahq_n_u8): Likewise. (vmvnq_m_u8): Likewise. (vmlasq_n_u8): Likewise. (vmlaq_n_u8): Likewise. (vmladavq_p_u8): Likewise. (vmladavaq_u8): Likewise. (vminvq_p_u8): Likewise. (vmaxvq_p_u8): Likewise. (vdupq_m_n_u8): Likewise. (vcmpneq_m_u8): Likewise. (vcmpneq_m_n_u8): Likewise. (vcmphiq_m_u8): Likewise. (vcmphiq_m_n_u8): Likewise. (vcmpeqq_m_u8): Likewise. (vcmpeqq_m_n_u8): Likewise. (vcmpcsq_m_u8): Likewise. (vcmpcsq_m_n_u8): Likewise. (vclzq_m_u8): Likewise. (vaddvaq_p_u8): Likewise. (vsriq_n_u8): Likewise. (vsliq_n_u8): Likewise. (vshlq_m_r_u8): Likewise. (vrshlq_m_n_u8): Likewise. (vqshlq_m_r_u8): Likewise. (vqrshlq_m_n_u8): Likewise. (vminavq_p_s8): Likewise. (vminaq_m_s8): Likewise. (vmaxavq_p_s8): Likewise. (vmaxaq_m_s8): Likewise. (vcmpneq_m_s8): Likewise. (vcmpneq_m_n_s8): Likewise. (vcmpltq_m_s8): Likewise. (vcmpltq_m_n_s8): Likewise. (vcmpleq_m_s8): Likewise. (vcmpleq_m_n_s8): Likewise. (vcmpgtq_m_s8): Likewise. (vcmpgtq_m_n_s8): Likewise. (vcmpgeq_m_s8): Likewise. (vcmpgeq_m_n_s8): Likewise. (vcmpeqq_m_s8): Likewise. (vcmpeqq_m_n_s8): Likewise. (vshlq_m_r_s8): Likewise. (vrshlq_m_n_s8): Likewise. (vrev64q_m_s8): Likewise. (vqshlq_m_r_s8): Likewise. (vqrshlq_m_n_s8): Likewise. (vqnegq_m_s8): Likewise. (vqabsq_m_s8): Likewise. (vnegq_m_s8): Likewise. (vmvnq_m_s8): Likewise. (vmlsdavxq_p_s8): Likewise. (vmlsdavq_p_s8): Likewise. (vmladavxq_p_s8): Likewise. (vmladavq_p_s8): Likewise. (vminvq_p_s8): Likewise. (vmaxvq_p_s8): Likewise. (vdupq_m_n_s8): Likewise. (vclzq_m_s8): Likewise. (vclsq_m_s8): Likewise. (vaddvaq_p_s8): Likewise. (vabsq_m_s8): Likewise. (vqrdmlsdhxq_s8): Likewise. (vqrdmlsdhq_s8): Likewise. (vqrdmlashq_n_s8): Likewise. (vqrdmlahq_n_s8): Likewise. (vqrdmladhxq_s8): Likewise. (vqrdmladhq_s8): Likewise. (vqdmlsdhxq_s8): Likewise. (vqdmlsdhq_s8): Likewise. (vqdmlahq_n_s8): Likewise. (vqdmladhxq_s8): Likewise. (vqdmladhq_s8): Likewise. (vmlsdavaxq_s8): Likewise. (vmlsdavaq_s8): Likewise. (vmlasq_n_s8): Likewise. (vmlaq_n_s8): Likewise. (vmladavaxq_s8): Likewise. (vmladavaq_s8): Likewise. (vsriq_n_s8): Likewise. (vsliq_n_s8): Likewise. (vpselq_u16): Likewise. (vpselq_s16): Likewise. (vrev64q_m_u16): Likewise. (vqrdmlashq_n_u16): Likewise. (vqrdmlahq_n_u16): Likewise. (vqdmlahq_n_u16): Likewise. (vmvnq_m_u16): Likewise. (vmlasq_n_u16): Likewise. (vmlaq_n_u16): Likewise. (vmladavq_p_u16): Likewise. (vmladavaq_u16): Likewise. (vminvq_p_u16): Likewise. (vmaxvq_p_u16): Likewise. (vdupq_m_n_u16): Likewise. (vcmpneq_m_u16): Likewise. (vcmpneq_m_n_u16): Likewise. (vcmphiq_m_u16): Likewise. (vcmphiq_m_n_u16): Likewise. (vcmpeqq_m_u16): Likewise. (vcmpeqq_m_n_u16): Likewise. (vcmpcsq_m_u16): Likewise. (vcmpcsq_m_n_u16): Likewise. (vclzq_m_u16): Likewise. (vaddvaq_p_u16): Likewise. (vsriq_n_u16): Likewise. (vsliq_n_u16): Likewise. (vshlq_m_r_u16): Likewise. (vrshlq_m_n_u16): Likewise. (vqshlq_m_r_u16): Likewise. (vqrshlq_m_n_u16): Likewise. (vminavq_p_s16): Likewise. (vminaq_m_s16): Likewise. (vmaxavq_p_s16): Likewise. (vmaxaq_m_s16): Likewise. (vcmpneq_m_s16): Likewise. (vcmpneq_m_n_s16): Likewise. (vcmpltq_m_s16): Likewise. (vcmpltq_m_n_s16): Likewise. (vcmpleq_m_s16): Likewise. (vcmpleq_m_n_s16): Likewise. (vcmpgtq_m_s16): Likewise. (vcmpgtq_m_n_s16): Likewise. (vcmpgeq_m_s16): Likewise. (vcmpgeq_m_n_s16): Likewise. (vcmpeqq_m_s16): Likewise. (vcmpeqq_m_n_s16): Likewise. (vshlq_m_r_s16): Likewise. (vrshlq_m_n_s16): Likewise. (vrev64q_m_s16): Likewise. (vqshlq_m_r_s16): Likewise. (vqrshlq_m_n_s16): Likewise. (vqnegq_m_s16): Likewise. (vqabsq_m_s16): Likewise. (vnegq_m_s16): Likewise. (vmvnq_m_s16): Likewise. (vmlsdavxq_p_s16): Likewise. (vmlsdavq_p_s16): Likewise. (vmladavxq_p_s16): Likewise. (vmladavq_p_s16): Likewise. (vminvq_p_s16): Likewise. (vmaxvq_p_s16): Likewise. (vdupq_m_n_s16): Likewise. (vclzq_m_s16): Likewise. (vclsq_m_s16): Likewise. (vaddvaq_p_s16): Likewise. (vabsq_m_s16): Likewise. (vqrdmlsdhxq_s16): Likewise. (vqrdmlsdhq_s16): Likewise. (vqrdmlashq_n_s16): Likewise. (vqrdmlahq_n_s16): Likewise. (vqrdmladhxq_s16): Likewise. (vqrdmladhq_s16): Likewise. (vqdmlsdhxq_s16): Likewise. (vqdmlsdhq_s16): Likewise. (vqdmlahq_n_s16): Likewise. (vqdmladhxq_s16): Likewise. (vqdmladhq_s16): Likewise. (vmlsdavaxq_s16): Likewise. (vmlsdavaq_s16): Likewise. (vmlasq_n_s16): Likewise. (vmlaq_n_s16): Likewise. (vmladavaxq_s16): Likewise. (vmladavaq_s16): Likewise. (vsriq_n_s16): Likewise. (vsliq_n_s16): Likewise. (vpselq_u32): Likewise. (vpselq_s32): Likewise. (vrev64q_m_u32): Likewise. (vqrdmlashq_n_u32): Likewise. (vqrdmlahq_n_u32): Likewise. (vqdmlahq_n_u32): Likewise. (vmvnq_m_u32): Likewise. (vmlasq_n_u32): Likewise. (vmlaq_n_u32): Likewise. (vmladavq_p_u32): Likewise. (vmladavaq_u32): Likewise. (vminvq_p_u32): Likewise. (vmaxvq_p_u32): Likewise. (vdupq_m_n_u32): Likewise. (vcmpneq_m_u32): Likewise. (vcmpneq_m_n_u32): Likewise. (vcmphiq_m_u32): Likewise. (vcmphiq_m_n_u32): Likewise. (vcmpeqq_m_u32): Likewise. (vcmpeqq_m_n_u32): Likewise. (vcmpcsq_m_u32): Likewise. (vcmpcsq_m_n_u32): Likewise. (vclzq_m_u32): Likewise. (vaddvaq_p_u32): Likewise. (vsriq_n_u32): Likewise. (vsliq_n_u32): Likewise. (vshlq_m_r_u32): Likewise. (vrshlq_m_n_u32): Likewise. (vqshlq_m_r_u32): Likewise. (vqrshlq_m_n_u32): Likewise. (vminavq_p_s32): Likewise. (vminaq_m_s32): Likewise. (vmaxavq_p_s32): Likewise. (vmaxaq_m_s32): Likewise. (vcmpneq_m_s32): Likewise. (vcmpneq_m_n_s32): Likewise. (vcmpltq_m_s32): Likewise. (vcmpltq_m_n_s32): Likewise. (vcmpleq_m_s32): Likewise. (vcmpleq_m_n_s32): Likewise. (vcmpgtq_m_s32): Likewise. (vcmpgtq_m_n_s32): Likewise. (vcmpgeq_m_s32): Likewise. (vcmpgeq_m_n_s32): Likewise. (vcmpeqq_m_s32): Likewise. (vcmpeqq_m_n_s32): Likewise. (vshlq_m_r_s32): Likewise. (vrshlq_m_n_s32): Likewise. (vrev64q_m_s32): Likewise. (vqshlq_m_r_s32): Likewise. (vqrshlq_m_n_s32): Likewise. (vqnegq_m_s32): Likewise. (vqabsq_m_s32): Likewise. (vnegq_m_s32): Likewise. (vmvnq_m_s32): Likewise. (vmlsdavxq_p_s32): Likewise. (vmlsdavq_p_s32): Likewise. (vmladavxq_p_s32): Likewise. (vmladavq_p_s32): Likewise. (vminvq_p_s32): Likewise. (vmaxvq_p_s32): Likewise. (vdupq_m_n_s32): Likewise. (vclzq_m_s32): Likewise. (vclsq_m_s32): Likewise. (vaddvaq_p_s32): Likewise. (vabsq_m_s32): Likewise. (vqrdmlsdhxq_s32): Likewise. (vqrdmlsdhq_s32): Likewise. (vqrdmlashq_n_s32): Likewise. (vqrdmlahq_n_s32): Likewise. (vqrdmladhxq_s32): Likewise. (vqrdmladhq_s32): Likewise. (vqdmlsdhxq_s32): Likewise. (vqdmlsdhq_s32): Likewise. (vqdmlahq_n_s32): Likewise. (vqdmladhxq_s32): Likewise. (vqdmladhq_s32): Likewise. (vmlsdavaxq_s32): Likewise. (vmlsdavaq_s32): Likewise. (vmlasq_n_s32): Likewise. (vmlaq_n_s32): Likewise. (vmladavaxq_s32): Likewise. (vmladavaq_s32): Likewise. (vsriq_n_s32): Likewise. (vsliq_n_s32): Likewise. (vpselq_u64): Likewise. (vpselq_s64): Likewise. (__arm_vpselq_u8): Define intrinsic. (__arm_vpselq_s8): Likewise. (__arm_vrev64q_m_u8): Likewise. (__arm_vqrdmlashq_n_u8): Likewise. (__arm_vqrdmlahq_n_u8): Likewise. (__arm_vqdmlahq_n_u8): Likewise. (__arm_vmvnq_m_u8): Likewise. (__arm_vmlasq_n_u8): Likewise. (__arm_vmlaq_n_u8): Likewise. (__arm_vmladavq_p_u8): Likewise. (__arm_vmladavaq_u8): Likewise. (__arm_vminvq_p_u8): Likewise. (__arm_vmaxvq_p_u8): Likewise. (__arm_vdupq_m_n_u8): Likewise. (__arm_vcmpneq_m_u8): Likewise. (__arm_vcmpneq_m_n_u8): Likewise. (__arm_vcmphiq_m_u8): Likewise. (__arm_vcmphiq_m_n_u8): Likewise. (__arm_vcmpeqq_m_u8): Likewise. (__arm_vcmpeqq_m_n_u8): Likewise. (__arm_vcmpcsq_m_u8): Likewise. (__arm_vcmpcsq_m_n_u8): Likewise. (__arm_vclzq_m_u8): Likewise. (__arm_vaddvaq_p_u8): Likewise. (__arm_vsriq_n_u8): Likewise. (__arm_vsliq_n_u8): Likewise. (__arm_vshlq_m_r_u8): Likewise. (__arm_vrshlq_m_n_u8): Likewise. (__arm_vqshlq_m_r_u8): Likewise. (__arm_vqrshlq_m_n_u8): Likewise. (__arm_vminavq_p_s8): Likewise. (__arm_vminaq_m_s8): Likewise. (__arm_vmaxavq_p_s8): Likewise. (__arm_vmaxaq_m_s8): Likewise. (__arm_vcmpneq_m_s8): Likewise. (__arm_vcmpneq_m_n_s8): Likewise. (__arm_vcmpltq_m_s8): Likewise. (__arm_vcmpltq_m_n_s8): Likewise. (__arm_vcmpleq_m_s8): Likewise. (__arm_vcmpleq_m_n_s8): Likewise. (__arm_vcmpgtq_m_s8): Likewise. (__arm_vcmpgtq_m_n_s8): Likewise. (__arm_vcmpgeq_m_s8): Likewise. (__arm_vcmpgeq_m_n_s8): Likewise. (__arm_vcmpeqq_m_s8): Likewise. (__arm_vcmpeqq_m_n_s8): Likewise. (__arm_vshlq_m_r_s8): Likewise. (__arm_vrshlq_m_n_s8): Likewise. (__arm_vrev64q_m_s8): Likewise. (__arm_vqshlq_m_r_s8): Likewise. (__arm_vqrshlq_m_n_s8): Likewise. (__arm_vqnegq_m_s8): Likewise. (__arm_vqabsq_m_s8): Likewise. (__arm_vnegq_m_s8): Likewise. (__arm_vmvnq_m_s8): Likewise. (__arm_vmlsdavxq_p_s8): Likewise. (__arm_vmlsdavq_p_s8): Likewise. (__arm_vmladavxq_p_s8): Likewise. (__arm_vmladavq_p_s8): Likewise. (__arm_vminvq_p_s8): Likewise. (__arm_vmaxvq_p_s8): Likewise. (__arm_vdupq_m_n_s8): Likewise. (__arm_vclzq_m_s8): Likewise. (__arm_vclsq_m_s8): Likewise. (__arm_vaddvaq_p_s8): Likewise. (__arm_vabsq_m_s8): Likewise. (__arm_vqrdmlsdhxq_s8): Likewise. (__arm_vqrdmlsdhq_s8): Likewise. (__arm_vqrdmlashq_n_s8): Likewise. (__arm_vqrdmlahq_n_s8): Likewise. (__arm_vqrdmladhxq_s8): Likewise. (__arm_vqrdmladhq_s8): Likewise. (__arm_vqdmlsdhxq_s8): Likewise. (__arm_vqdmlsdhq_s8): Likewise. (__arm_vqdmlahq_n_s8): Likewise. (__arm_vqdmladhxq_s8): Likewise. (__arm_vqdmladhq_s8): Likewise. (__arm_vmlsdavaxq_s8): Likewise. (__arm_vmlsdavaq_s8): Likewise. (__arm_vmlasq_n_s8): Likewise. (__arm_vmlaq_n_s8): Likewise. (__arm_vmladavaxq_s8): Likewise. (__arm_vmladavaq_s8): Likewise. (__arm_vsriq_n_s8): Likewise. (__arm_vsliq_n_s8): Likewise. (__arm_vpselq_u16): Likewise. (__arm_vpselq_s16): Likewise. (__arm_vrev64q_m_u16): Likewise. (__arm_vqrdmlashq_n_u16): Likewise. (__arm_vqrdmlahq_n_u16): Likewise. (__arm_vqdmlahq_n_u16): Likewise. (__arm_vmvnq_m_u16): Likewise. (__arm_vmlasq_n_u16): Likewise. (__arm_vmlaq_n_u16): Likewise. (__arm_vmladavq_p_u16): Likewise. (__arm_vmladavaq_u16): Likewise. (__arm_vminvq_p_u16): Likewise. (__arm_vmaxvq_p_u16): Likewise. (__arm_vdupq_m_n_u16): Likewise. (__arm_vcmpneq_m_u16): Likewise. (__arm_vcmpneq_m_n_u16): Likewise. (__arm_vcmphiq_m_u16): Likewise. (__arm_vcmphiq_m_n_u16): Likewise. (__arm_vcmpeqq_m_u16): Likewise. (__arm_vcmpeqq_m_n_u16): Likewise. (__arm_vcmpcsq_m_u16): Likewise. (__arm_vcmpcsq_m_n_u16): Likewise. (__arm_vclzq_m_u16): Likewise. (__arm_vaddvaq_p_u16): Likewise. (__arm_vsriq_n_u16): Likewise. (__arm_vsliq_n_u16): Likewise. (__arm_vshlq_m_r_u16): Likewise. (__arm_vrshlq_m_n_u16): Likewise. (__arm_vqshlq_m_r_u16): Likewise. (__arm_vqrshlq_m_n_u16): Likewise. (__arm_vminavq_p_s16): Likewise. (__arm_vminaq_m_s16): Likewise. (__arm_vmaxavq_p_s16): Likewise. (__arm_vmaxaq_m_s16): Likewise. (__arm_vcmpneq_m_s16): Likewise. (__arm_vcmpneq_m_n_s16): Likewise. (__arm_vcmpltq_m_s16): Likewise. (__arm_vcmpltq_m_n_s16): Likewise. (__arm_vcmpleq_m_s16): Likewise. (__arm_vcmpleq_m_n_s16): Likewise. (__arm_vcmpgtq_m_s16): Likewise. (__arm_vcmpgtq_m_n_s16): Likewise. (__arm_vcmpgeq_m_s16): Likewise. (__arm_vcmpgeq_m_n_s16): Likewise. (__arm_vcmpeqq_m_s16): Likewise. (__arm_vcmpeqq_m_n_s16): Likewise. (__arm_vshlq_m_r_s16): Likewise. (__arm_vrshlq_m_n_s16): Likewise. (__arm_vrev64q_m_s16): Likewise. (__arm_vqshlq_m_r_s16): Likewise. (__arm_vqrshlq_m_n_s16): Likewise. (__arm_vqnegq_m_s16): Likewise. (__arm_vqabsq_m_s16): Likewise. (__arm_vnegq_m_s16): Likewise. (__arm_vmvnq_m_s16): Likewise. (__arm_vmlsdavxq_p_s16): Likewise. (__arm_vmlsdavq_p_s16): Likewise. (__arm_vmladavxq_p_s16): Likewise. (__arm_vmladavq_p_s16): Likewise. (__arm_vminvq_p_s16): Likewise. (__arm_vmaxvq_p_s16): Likewise. (__arm_vdupq_m_n_s16): Likewise. (__arm_vclzq_m_s16): Likewise. (__arm_vclsq_m_s16): Likewise. (__arm_vaddvaq_p_s16): Likewise. (__arm_vabsq_m_s16): Likewise. (__arm_vqrdmlsdhxq_s16): Likewise. (__arm_vqrdmlsdhq_s16): Likewise. (__arm_vqrdmlashq_n_s16): Likewise. (__arm_vqrdmlahq_n_s16): Likewise. (__arm_vqrdmladhxq_s16): Likewise. (__arm_vqrdmladhq_s16): Likewise. (__arm_vqdmlsdhxq_s16): Likewise. (__arm_vqdmlsdhq_s16): Likewise. (__arm_vqdmlahq_n_s16): Likewise. (__arm_vqdmladhxq_s16): Likewise. (__arm_vqdmladhq_s16): Likewise. (__arm_vmlsdavaxq_s16): Likewise. (__arm_vmlsdavaq_s16): Likewise. (__arm_vmlasq_n_s16): Likewise. (__arm_vmlaq_n_s16): Likewise. (__arm_vmladavaxq_s16): Likewise. (__arm_vmladavaq_s16): Likewise. (__arm_vsriq_n_s16): Likewise. (__arm_vsliq_n_s16): Likewise. (__arm_vpselq_u32): Likewise. (__arm_vpselq_s32): Likewise. (__arm_vrev64q_m_u32): Likewise. (__arm_vqrdmlashq_n_u32): Likewise. (__arm_vqrdmlahq_n_u32): Likewise. (__arm_vqdmlahq_n_u32): Likewise. (__arm_vmvnq_m_u32): Likewise. (__arm_vmlasq_n_u32): Likewise. (__arm_vmlaq_n_u32): Likewise. (__arm_vmladavq_p_u32): Likewise. (__arm_vmladavaq_u32): Likewise. (__arm_vminvq_p_u32): Likewise. (__arm_vmaxvq_p_u32): Likewise. (__arm_vdupq_m_n_u32): Likewise. (__arm_vcmpneq_m_u32): Likewise. (__arm_vcmpneq_m_n_u32): Likewise. (__arm_vcmphiq_m_u32): Likewise. (__arm_vcmphiq_m_n_u32): Likewise. (__arm_vcmpeqq_m_u32): Likewise. (__arm_vcmpeqq_m_n_u32): Likewise. (__arm_vcmpcsq_m_u32): Likewise. (__arm_vcmpcsq_m_n_u32): Likewise. (__arm_vclzq_m_u32): Likewise. (__arm_vaddvaq_p_u32): Likewise. (__arm_vsriq_n_u32): Likewise. (__arm_vsliq_n_u32): Likewise. (__arm_vshlq_m_r_u32): Likewise. (__arm_vrshlq_m_n_u32): Likewise. (__arm_vqshlq_m_r_u32): Likewise. (__arm_vqrshlq_m_n_u32): Likewise. (__arm_vminavq_p_s32): Likewise. (__arm_vminaq_m_s32): Likewise. (__arm_vmaxavq_p_s32): Likewise. (__arm_vmaxaq_m_s32): Likewise. (__arm_vcmpneq_m_s32): Likewise. (__arm_vcmpneq_m_n_s32): Likewise. (__arm_vcmpltq_m_s32): Likewise. (__arm_vcmpltq_m_n_s32): Likewise. (__arm_vcmpleq_m_s32): Likewise. (__arm_vcmpleq_m_n_s32): Likewise. (__arm_vcmpgtq_m_s32): Likewise. (__arm_vcmpgtq_m_n_s32): Likewise. (__arm_vcmpgeq_m_s32): Likewise. (__arm_vcmpgeq_m_n_s32): Likewise. (__arm_vcmpeqq_m_s32): Likewise. (__arm_vcmpeqq_m_n_s32): Likewise. (__arm_vshlq_m_r_s32): Likewise. (__arm_vrshlq_m_n_s32): Likewise. (__arm_vrev64q_m_s32): Likewise. (__arm_vqshlq_m_r_s32): Likewise. (__arm_vqrshlq_m_n_s32): Likewise. (__arm_vqnegq_m_s32): Likewise. (__arm_vqabsq_m_s32): Likewise. (__arm_vnegq_m_s32): Likewise. (__arm_vmvnq_m_s32): Likewise. (__arm_vmlsdavxq_p_s32): Likewise. (__arm_vmlsdavq_p_s32): Likewise. (__arm_vmladavxq_p_s32): Likewise. (__arm_vmladavq_p_s32): Likewise. (__arm_vminvq_p_s32): Likewise. (__arm_vmaxvq_p_s32): Likewise. (__arm_vdupq_m_n_s32): Likewise. (__arm_vclzq_m_s32): Likewise. (__arm_vclsq_m_s32): Likewise. (__arm_vaddvaq_p_s32): Likewise. (__arm_vabsq_m_s32): Likewise. (__arm_vqrdmlsdhxq_s32): Likewise. (__arm_vqrdmlsdhq_s32): Likewise. (__arm_vqrdmlashq_n_s32): Likewise. (__arm_vqrdmlahq_n_s32): Likewise. (__arm_vqrdmladhxq_s32): Likewise. (__arm_vqrdmladhq_s32): Likewise. (__arm_vqdmlsdhxq_s32): Likewise. (__arm_vqdmlsdhq_s32): Likewise. (__arm_vqdmlahq_n_s32): Likewise. (__arm_vqdmladhxq_s32): Likewise. (__arm_vqdmladhq_s32): Likewise. (__arm_vmlsdavaxq_s32): Likewise. (__arm_vmlsdavaq_s32): Likewise. (__arm_vmlasq_n_s32): Likewise. (__arm_vmlaq_n_s32): Likewise. (__arm_vmladavaxq_s32): Likewise. (__arm_vmladavaq_s32): Likewise. (__arm_vsriq_n_s32): Likewise. (__arm_vsliq_n_s32): Likewise. (__arm_vpselq_u64): Likewise. (__arm_vpselq_s64): Likewise. (vcmpneq_m_n): Define polymorphic variant. (vcmpneq_m): Likewise. (vqrdmlsdhq): Likewise. (vqrdmlsdhxq): Likewise. (vqrshlq_m_n): Likewise. (vqshlq_m_r): Likewise. (vrev64q_m): Likewise. (vrshlq_m_n): Likewise. (vshlq_m_r): Likewise. (vsliq_n): Likewise. (vsriq_n): Likewise. (vqrdmlashq_n): Likewise. (vqrdmlahq): Likewise. (vqrdmladhxq): Likewise. (vqrdmladhq): Likewise. (vqnegq_m): Likewise. (vqdmlsdhxq): Likewise. (vabsq_m): Likewise. (vclsq_m): Likewise. (vclzq_m): Likewise. (vcmpgeq_m): Likewise. (vcmpgeq_m_n): Likewise. (vdupq_m_n): Likewise. (vmaxaq_m): Likewise. (vmlaq_n): Likewise. (vmlasq_n): Likewise. (vmvnq_m): Likewise. (vnegq_m): Likewise. (vpselq): Likewise. (vqdmlahq_n): Likewise. (vqrdmlahq_n): Likewise. (vqdmlsdhq): Likewise. (vqdmladhq): Likewise. (vqabsq_m): Likewise. (vminaq_m): Likewise. (vrmlaldavhaq): Likewise. (vmlsdavxq_p): Likewise. (vmlsdavq_p): Likewise. (vmlsdavaxq): Likewise. (vmlsdavaq): Likewise. (vaddvaq_p): Likewise. (vcmpcsq_m_n): Likewise. (vcmpcsq_m): Likewise. (vcmpeqq_m_n): Likewise. (vcmpeqq_m): Likewise. (vmladavxq_p): Likewise. (vmladavq_p): Likewise. (vmladavaxq): Likewise. (vmladavaq): Likewise. (vminvq_p): Likewise. (vminavq_p): Likewise. (vmaxvq_p): Likewise. (vmaxavq_p): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmphiq_m_n): Likewise. (vcmphiq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/constraints.md (Rc): Define constraint to check constant is in the range of 0 to 15. (Re): Define constraint to check constant is in the range of 0 to 31. * config/arm/mve.md (VADDVAQ_P): Define iterator. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (mve_vabsq_m_s): Define RTL pattern. (mve_vaddvaq_p_): Likewise. (mve_vclsq_m_s): Likewise. (mve_vclzq_m_): Likewise. (mve_vcmpcsq_m_n_u): Likewise. (mve_vcmpcsq_m_u): Likewise. (mve_vcmpeqq_m_n_): Likewise. (mve_vcmpeqq_m_): Likewise. (mve_vcmpgeq_m_n_s): Likewise. (mve_vcmpgeq_m_s): Likewise. (mve_vcmpgtq_m_n_s): Likewise. (mve_vcmpgtq_m_s): Likewise. (mve_vcmphiq_m_n_u): Likewise. (mve_vcmphiq_m_u): Likewise. (mve_vcmpleq_m_n_s): Likewise. (mve_vcmpleq_m_s): Likewise. (mve_vcmpltq_m_n_s): Likewise. (mve_vcmpltq_m_s): Likewise. (mve_vcmpneq_m_n_): Likewise. (mve_vcmpneq_m_): Likewise. (mve_vdupq_m_n_): Likewise. (mve_vmaxaq_m_s): Likewise. (mve_vmaxavq_p_s): Likewise. (mve_vmaxvq_p_): Likewise. (mve_vminaq_m_s): Likewise. (mve_vminavq_p_s): Likewise. (mve_vminvq_p_): Likewise. (mve_vmladavaq_): Likewise. (mve_vmladavq_p_): Likewise. (mve_vmladavxq_p_s): Likewise. (mve_vmlaq_n_): Likewise. (mve_vmlasq_n_): Likewise. (mve_vmlsdavq_p_s): Likewise. (mve_vmlsdavxq_p_s): Likewise. (mve_vmvnq_m_): Likewise. (mve_vnegq_m_s): Likewise. (mve_vpselq_): Likewise. (mve_vqabsq_m_s): Likewise. (mve_vqdmlahq_n_): Likewise. (mve_vqnegq_m_s): Likewise. (mve_vqrdmladhq_s): Likewise. (mve_vqrdmladhxq_s): Likewise. (mve_vqrdmlahq_n_): Likewise. (mve_vqrdmlashq_n_): Likewise. (mve_vqrdmlsdhq_s): Likewise. (mve_vqrdmlsdhxq_s): Likewise. (mve_vqrshlq_m_n_): Likewise. (mve_vqshlq_m_r_): Likewise. (mve_vrev64q_m_): Likewise. (mve_vrshlq_m_n_): Likewise. (mve_vshlq_m_r_): Likewise. (mve_vsliq_n_): Likewise. (mve_vsriq_n_): Likewise. (mve_vqdmlsdhxq_s): Likewise. (mve_vqdmlsdhq_s): Likewise. (mve_vqdmladhxq_s): Likewise. (mve_vqdmladhq_s): Likewise. (mve_vmlsdavaxq_s): Likewise. (mve_vmlsdavaq_s): Likewise. (mve_vmladavaxq_s): Likewise. * config/arm/predicates.md (mve_imm_15):Define predicate to check the matching constraint Rc. (mve_imm_31): Define predicate to check the matching constraint Re. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise. --- gcc/ChangeLog | 679 +++++ gcc/config/arm/arm_mve.h | 2966 +++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 85 + gcc/config/arm/constraints.md | 10 + gcc/config/arm/mve.md | 1032 ++++++- gcc/config/arm/predicates.md | 8 + gcc/testsuite/ChangeLog | 262 ++ .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 22 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fcd0272..ebbdb8e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,682 @@ +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm_mve.h (vpselq_u8): Define macro. + (vpselq_s8): Likewise. + (vrev64q_m_u8): Likewise. + (vqrdmlashq_n_u8): Likewise. + (vqrdmlahq_n_u8): Likewise. + (vqdmlahq_n_u8): Likewise. + (vmvnq_m_u8): Likewise. + (vmlasq_n_u8): Likewise. + (vmlaq_n_u8): Likewise. + (vmladavq_p_u8): Likewise. + (vmladavaq_u8): Likewise. + (vminvq_p_u8): Likewise. + (vmaxvq_p_u8): Likewise. + (vdupq_m_n_u8): Likewise. + (vcmpneq_m_u8): Likewise. + (vcmpneq_m_n_u8): Likewise. + (vcmphiq_m_u8): Likewise. + (vcmphiq_m_n_u8): Likewise. + (vcmpeqq_m_u8): Likewise. + (vcmpeqq_m_n_u8): Likewise. + (vcmpcsq_m_u8): Likewise. + (vcmpcsq_m_n_u8): Likewise. + (vclzq_m_u8): Likewise. + (vaddvaq_p_u8): Likewise. + (vsriq_n_u8): Likewise. + (vsliq_n_u8): Likewise. + (vshlq_m_r_u8): Likewise. + (vrshlq_m_n_u8): Likewise. + (vqshlq_m_r_u8): Likewise. + (vqrshlq_m_n_u8): Likewise. + (vminavq_p_s8): Likewise. + (vminaq_m_s8): Likewise. + (vmaxavq_p_s8): Likewise. + (vmaxaq_m_s8): Likewise. + (vcmpneq_m_s8): Likewise. + (vcmpneq_m_n_s8): Likewise. + (vcmpltq_m_s8): Likewise. + (vcmpltq_m_n_s8): Likewise. + (vcmpleq_m_s8): Likewise. + (vcmpleq_m_n_s8): Likewise. + (vcmpgtq_m_s8): Likewise. + (vcmpgtq_m_n_s8): Likewise. + (vcmpgeq_m_s8): Likewise. + (vcmpgeq_m_n_s8): Likewise. + (vcmpeqq_m_s8): Likewise. + (vcmpeqq_m_n_s8): Likewise. + (vshlq_m_r_s8): Likewise. + (vrshlq_m_n_s8): Likewise. + (vrev64q_m_s8): Likewise. + (vqshlq_m_r_s8): Likewise. + (vqrshlq_m_n_s8): Likewise. + (vqnegq_m_s8): Likewise. + (vqabsq_m_s8): Likewise. + (vnegq_m_s8): Likewise. + (vmvnq_m_s8): Likewise. + (vmlsdavxq_p_s8): Likewise. + (vmlsdavq_p_s8): Likewise. + (vmladavxq_p_s8): Likewise. + (vmladavq_p_s8): Likewise. + (vminvq_p_s8): Likewise. + (vmaxvq_p_s8): Likewise. + (vdupq_m_n_s8): Likewise. + (vclzq_m_s8): Likewise. + (vclsq_m_s8): Likewise. + (vaddvaq_p_s8): Likewise. + (vabsq_m_s8): Likewise. + (vqrdmlsdhxq_s8): Likewise. + (vqrdmlsdhq_s8): Likewise. + (vqrdmlashq_n_s8): Likewise. + (vqrdmlahq_n_s8): Likewise. + (vqrdmladhxq_s8): Likewise. + (vqrdmladhq_s8): Likewise. + (vqdmlsdhxq_s8): Likewise. + (vqdmlsdhq_s8): Likewise. + (vqdmlahq_n_s8): Likewise. + (vqdmladhxq_s8): Likewise. + (vqdmladhq_s8): Likewise. + (vmlsdavaxq_s8): Likewise. + (vmlsdavaq_s8): Likewise. + (vmlasq_n_s8): Likewise. + (vmlaq_n_s8): Likewise. + (vmladavaxq_s8): Likewise. + (vmladavaq_s8): Likewise. + (vsriq_n_s8): Likewise. + (vsliq_n_s8): Likewise. + (vpselq_u16): Likewise. + (vpselq_s16): Likewise. + (vrev64q_m_u16): Likewise. + (vqrdmlashq_n_u16): Likewise. + (vqrdmlahq_n_u16): Likewise. + (vqdmlahq_n_u16): Likewise. + (vmvnq_m_u16): Likewise. + (vmlasq_n_u16): Likewise. + (vmlaq_n_u16): Likewise. + (vmladavq_p_u16): Likewise. + (vmladavaq_u16): Likewise. + (vminvq_p_u16): Likewise. + (vmaxvq_p_u16): Likewise. + (vdupq_m_n_u16): Likewise. + (vcmpneq_m_u16): Likewise. + (vcmpneq_m_n_u16): Likewise. + (vcmphiq_m_u16): Likewise. + (vcmphiq_m_n_u16): Likewise. + (vcmpeqq_m_u16): Likewise. + (vcmpeqq_m_n_u16): Likewise. + (vcmpcsq_m_u16): Likewise. + (vcmpcsq_m_n_u16): Likewise. + (vclzq_m_u16): Likewise. + (vaddvaq_p_u16): Likewise. + (vsriq_n_u16): Likewise. + (vsliq_n_u16): Likewise. + (vshlq_m_r_u16): Likewise. + (vrshlq_m_n_u16): Likewise. + (vqshlq_m_r_u16): Likewise. + (vqrshlq_m_n_u16): Likewise. + (vminavq_p_s16): Likewise. + (vminaq_m_s16): Likewise. + (vmaxavq_p_s16): Likewise. + (vmaxaq_m_s16): Likewise. + (vcmpneq_m_s16): Likewise. + (vcmpneq_m_n_s16): Likewise. + (vcmpltq_m_s16): Likewise. + (vcmpltq_m_n_s16): Likewise. + (vcmpleq_m_s16): Likewise. + (vcmpleq_m_n_s16): Likewise. + (vcmpgtq_m_s16): Likewise. + (vcmpgtq_m_n_s16): Likewise. + (vcmpgeq_m_s16): Likewise. + (vcmpgeq_m_n_s16): Likewise. + (vcmpeqq_m_s16): Likewise. + (vcmpeqq_m_n_s16): Likewise. + (vshlq_m_r_s16): Likewise. + (vrshlq_m_n_s16): Likewise. + (vrev64q_m_s16): Likewise. + (vqshlq_m_r_s16): Likewise. + (vqrshlq_m_n_s16): Likewise. + (vqnegq_m_s16): Likewise. + (vqabsq_m_s16): Likewise. + (vnegq_m_s16): Likewise. + (vmvnq_m_s16): Likewise. + (vmlsdavxq_p_s16): Likewise. + (vmlsdavq_p_s16): Likewise. + (vmladavxq_p_s16): Likewise. + (vmladavq_p_s16): Likewise. + (vminvq_p_s16): Likewise. + (vmaxvq_p_s16): Likewise. + (vdupq_m_n_s16): Likewise. + (vclzq_m_s16): Likewise. + (vclsq_m_s16): Likewise. + (vaddvaq_p_s16): Likewise. + (vabsq_m_s16): Likewise. + (vqrdmlsdhxq_s16): Likewise. + (vqrdmlsdhq_s16): Likewise. + (vqrdmlashq_n_s16): Likewise. + (vqrdmlahq_n_s16): Likewise. + (vqrdmladhxq_s16): Likewise. + (vqrdmladhq_s16): Likewise. + (vqdmlsdhxq_s16): Likewise. + (vqdmlsdhq_s16): Likewise. + (vqdmlahq_n_s16): Likewise. + (vqdmladhxq_s16): Likewise. + (vqdmladhq_s16): Likewise. + (vmlsdavaxq_s16): Likewise. + (vmlsdavaq_s16): Likewise. + (vmlasq_n_s16): Likewise. + (vmlaq_n_s16): Likewise. + (vmladavaxq_s16): Likewise. + (vmladavaq_s16): Likewise. + (vsriq_n_s16): Likewise. + (vsliq_n_s16): Likewise. + (vpselq_u32): Likewise. + (vpselq_s32): Likewise. + (vrev64q_m_u32): Likewise. + (vqrdmlashq_n_u32): Likewise. + (vqrdmlahq_n_u32): Likewise. + (vqdmlahq_n_u32): Likewise. + (vmvnq_m_u32): Likewise. + (vmlasq_n_u32): Likewise. + (vmlaq_n_u32): Likewise. + (vmladavq_p_u32): Likewise. + (vmladavaq_u32): Likewise. + (vminvq_p_u32): Likewise. + (vmaxvq_p_u32): Likewise. + (vdupq_m_n_u32): Likewise. + (vcmpneq_m_u32): Likewise. + (vcmpneq_m_n_u32): Likewise. + (vcmphiq_m_u32): Likewise. + (vcmphiq_m_n_u32): Likewise. + (vcmpeqq_m_u32): Likewise. + (vcmpeqq_m_n_u32): Likewise. + (vcmpcsq_m_u32): Likewise. + (vcmpcsq_m_n_u32): Likewise. + (vclzq_m_u32): Likewise. + (vaddvaq_p_u32): Likewise. + (vsriq_n_u32): Likewise. + (vsliq_n_u32): Likewise. + (vshlq_m_r_u32): Likewise. + (vrshlq_m_n_u32): Likewise. + (vqshlq_m_r_u32): Likewise. + (vqrshlq_m_n_u32): Likewise. + (vminavq_p_s32): Likewise. + (vminaq_m_s32): Likewise. + (vmaxavq_p_s32): Likewise. + (vmaxaq_m_s32): Likewise. + (vcmpneq_m_s32): Likewise. + (vcmpneq_m_n_s32): Likewise. + (vcmpltq_m_s32): Likewise. + (vcmpltq_m_n_s32): Likewise. + (vcmpleq_m_s32): Likewise. + (vcmpleq_m_n_s32): Likewise. + (vcmpgtq_m_s32): Likewise. + (vcmpgtq_m_n_s32): Likewise. + (vcmpgeq_m_s32): Likewise. + (vcmpgeq_m_n_s32): Likewise. + (vcmpeqq_m_s32): Likewise. + (vcmpeqq_m_n_s32): Likewise. + (vshlq_m_r_s32): Likewise. + (vrshlq_m_n_s32): Likewise. + (vrev64q_m_s32): Likewise. + (vqshlq_m_r_s32): Likewise. + (vqrshlq_m_n_s32): Likewise. + (vqnegq_m_s32): Likewise. + (vqabsq_m_s32): Likewise. + (vnegq_m_s32): Likewise. + (vmvnq_m_s32): Likewise. + (vmlsdavxq_p_s32): Likewise. + (vmlsdavq_p_s32): Likewise. + (vmladavxq_p_s32): Likewise. + (vmladavq_p_s32): Likewise. + (vminvq_p_s32): Likewise. + (vmaxvq_p_s32): Likewise. + (vdupq_m_n_s32): Likewise. + (vclzq_m_s32): Likewise. + (vclsq_m_s32): Likewise. + (vaddvaq_p_s32): Likewise. + (vabsq_m_s32): Likewise. + (vqrdmlsdhxq_s32): Likewise. + (vqrdmlsdhq_s32): Likewise. + (vqrdmlashq_n_s32): Likewise. + (vqrdmlahq_n_s32): Likewise. + (vqrdmladhxq_s32): Likewise. + (vqrdmladhq_s32): Likewise. + (vqdmlsdhxq_s32): Likewise. + (vqdmlsdhq_s32): Likewise. + (vqdmlahq_n_s32): Likewise. + (vqdmladhxq_s32): Likewise. + (vqdmladhq_s32): Likewise. + (vmlsdavaxq_s32): Likewise. + (vmlsdavaq_s32): Likewise. + (vmlasq_n_s32): Likewise. + (vmlaq_n_s32): Likewise. + (vmladavaxq_s32): Likewise. + (vmladavaq_s32): Likewise. + (vsriq_n_s32): Likewise. + (vsliq_n_s32): Likewise. + (vpselq_u64): Likewise. + (vpselq_s64): Likewise. + (__arm_vpselq_u8): Define intrinsic. + (__arm_vpselq_s8): Likewise. + (__arm_vrev64q_m_u8): Likewise. + (__arm_vqrdmlashq_n_u8): Likewise. + (__arm_vqrdmlahq_n_u8): Likewise. + (__arm_vqdmlahq_n_u8): Likewise. + (__arm_vmvnq_m_u8): Likewise. + (__arm_vmlasq_n_u8): Likewise. + (__arm_vmlaq_n_u8): Likewise. + (__arm_vmladavq_p_u8): Likewise. + (__arm_vmladavaq_u8): Likewise. + (__arm_vminvq_p_u8): Likewise. + (__arm_vmaxvq_p_u8): Likewise. + (__arm_vdupq_m_n_u8): Likewise. + (__arm_vcmpneq_m_u8): Likewise. + (__arm_vcmpneq_m_n_u8): Likewise. + (__arm_vcmphiq_m_u8): Likewise. + (__arm_vcmphiq_m_n_u8): Likewise. + (__arm_vcmpeqq_m_u8): Likewise. + (__arm_vcmpeqq_m_n_u8): Likewise. + (__arm_vcmpcsq_m_u8): Likewise. + (__arm_vcmpcsq_m_n_u8): Likewise. + (__arm_vclzq_m_u8): Likewise. + (__arm_vaddvaq_p_u8): Likewise. + (__arm_vsriq_n_u8): Likewise. + (__arm_vsliq_n_u8): Likewise. + (__arm_vshlq_m_r_u8): Likewise. + (__arm_vrshlq_m_n_u8): Likewise. + (__arm_vqshlq_m_r_u8): Likewise. + (__arm_vqrshlq_m_n_u8): Likewise. + (__arm_vminavq_p_s8): Likewise. + (__arm_vminaq_m_s8): Likewise. + (__arm_vmaxavq_p_s8): Likewise. + (__arm_vmaxaq_m_s8): Likewise. + (__arm_vcmpneq_m_s8): Likewise. + (__arm_vcmpneq_m_n_s8): Likewise. + (__arm_vcmpltq_m_s8): Likewise. + (__arm_vcmpltq_m_n_s8): Likewise. + (__arm_vcmpleq_m_s8): Likewise. + (__arm_vcmpleq_m_n_s8): Likewise. + (__arm_vcmpgtq_m_s8): Likewise. + (__arm_vcmpgtq_m_n_s8): Likewise. + (__arm_vcmpgeq_m_s8): Likewise. + (__arm_vcmpgeq_m_n_s8): Likewise. + (__arm_vcmpeqq_m_s8): Likewise. + (__arm_vcmpeqq_m_n_s8): Likewise. + (__arm_vshlq_m_r_s8): Likewise. + (__arm_vrshlq_m_n_s8): Likewise. + (__arm_vrev64q_m_s8): Likewise. + (__arm_vqshlq_m_r_s8): Likewise. + (__arm_vqrshlq_m_n_s8): Likewise. + (__arm_vqnegq_m_s8): Likewise. + (__arm_vqabsq_m_s8): Likewise. + (__arm_vnegq_m_s8): Likewise. + (__arm_vmvnq_m_s8): Likewise. + (__arm_vmlsdavxq_p_s8): Likewise. + (__arm_vmlsdavq_p_s8): Likewise. + (__arm_vmladavxq_p_s8): Likewise. + (__arm_vmladavq_p_s8): Likewise. + (__arm_vminvq_p_s8): Likewise. + (__arm_vmaxvq_p_s8): Likewise. + (__arm_vdupq_m_n_s8): Likewise. + (__arm_vclzq_m_s8): Likewise. + (__arm_vclsq_m_s8): Likewise. + (__arm_vaddvaq_p_s8): Likewise. + (__arm_vabsq_m_s8): Likewise. + (__arm_vqrdmlsdhxq_s8): Likewise. + (__arm_vqrdmlsdhq_s8): Likewise. + (__arm_vqrdmlashq_n_s8): Likewise. + (__arm_vqrdmlahq_n_s8): Likewise. + (__arm_vqrdmladhxq_s8): Likewise. + (__arm_vqrdmladhq_s8): Likewise. + (__arm_vqdmlsdhxq_s8): Likewise. + (__arm_vqdmlsdhq_s8): Likewise. + (__arm_vqdmlahq_n_s8): Likewise. + (__arm_vqdmladhxq_s8): Likewise. + (__arm_vqdmladhq_s8): Likewise. + (__arm_vmlsdavaxq_s8): Likewise. + (__arm_vmlsdavaq_s8): Likewise. + (__arm_vmlasq_n_s8): Likewise. + (__arm_vmlaq_n_s8): Likewise. + (__arm_vmladavaxq_s8): Likewise. + (__arm_vmladavaq_s8): Likewise. + (__arm_vsriq_n_s8): Likewise. + (__arm_vsliq_n_s8): Likewise. + (__arm_vpselq_u16): Likewise. + (__arm_vpselq_s16): Likewise. + (__arm_vrev64q_m_u16): Likewise. + (__arm_vqrdmlashq_n_u16): Likewise. + (__arm_vqrdmlahq_n_u16): Likewise. + (__arm_vqdmlahq_n_u16): Likewise. + (__arm_vmvnq_m_u16): Likewise. + (__arm_vmlasq_n_u16): Likewise. + (__arm_vmlaq_n_u16): Likewise. + (__arm_vmladavq_p_u16): Likewise. + (__arm_vmladavaq_u16): Likewise. + (__arm_vminvq_p_u16): Likewise. + (__arm_vmaxvq_p_u16): Likewise. + (__arm_vdupq_m_n_u16): Likewise. + (__arm_vcmpneq_m_u16): Likewise. + (__arm_vcmpneq_m_n_u16): Likewise. + (__arm_vcmphiq_m_u16): Likewise. + (__arm_vcmphiq_m_n_u16): Likewise. + (__arm_vcmpeqq_m_u16): Likewise. + (__arm_vcmpeqq_m_n_u16): Likewise. + (__arm_vcmpcsq_m_u16): Likewise. + (__arm_vcmpcsq_m_n_u16): Likewise. + (__arm_vclzq_m_u16): Likewise. + (__arm_vaddvaq_p_u16): Likewise. + (__arm_vsriq_n_u16): Likewise. + (__arm_vsliq_n_u16): Likewise. + (__arm_vshlq_m_r_u16): Likewise. + (__arm_vrshlq_m_n_u16): Likewise. + (__arm_vqshlq_m_r_u16): Likewise. + (__arm_vqrshlq_m_n_u16): Likewise. + (__arm_vminavq_p_s16): Likewise. + (__arm_vminaq_m_s16): Likewise. + (__arm_vmaxavq_p_s16): Likewise. + (__arm_vmaxaq_m_s16): Likewise. + (__arm_vcmpneq_m_s16): Likewise. + (__arm_vcmpneq_m_n_s16): Likewise. + (__arm_vcmpltq_m_s16): Likewise. + (__arm_vcmpltq_m_n_s16): Likewise. + (__arm_vcmpleq_m_s16): Likewise. + (__arm_vcmpleq_m_n_s16): Likewise. + (__arm_vcmpgtq_m_s16): Likewise. + (__arm_vcmpgtq_m_n_s16): Likewise. + (__arm_vcmpgeq_m_s16): Likewise. + (__arm_vcmpgeq_m_n_s16): Likewise. + (__arm_vcmpeqq_m_s16): Likewise. + (__arm_vcmpeqq_m_n_s16): Likewise. + (__arm_vshlq_m_r_s16): Likewise. + (__arm_vrshlq_m_n_s16): Likewise. + (__arm_vrev64q_m_s16): Likewise. + (__arm_vqshlq_m_r_s16): Likewise. + (__arm_vqrshlq_m_n_s16): Likewise. + (__arm_vqnegq_m_s16): Likewise. + (__arm_vqabsq_m_s16): Likewise. + (__arm_vnegq_m_s16): Likewise. + (__arm_vmvnq_m_s16): Likewise. + (__arm_vmlsdavxq_p_s16): Likewise. + (__arm_vmlsdavq_p_s16): Likewise. + (__arm_vmladavxq_p_s16): Likewise. + (__arm_vmladavq_p_s16): Likewise. + (__arm_vminvq_p_s16): Likewise. + (__arm_vmaxvq_p_s16): Likewise. + (__arm_vdupq_m_n_s16): Likewise. + (__arm_vclzq_m_s16): Likewise. + (__arm_vclsq_m_s16): Likewise. + (__arm_vaddvaq_p_s16): Likewise. + (__arm_vabsq_m_s16): Likewise. + (__arm_vqrdmlsdhxq_s16): Likewise. + (__arm_vqrdmlsdhq_s16): Likewise. + (__arm_vqrdmlashq_n_s16): Likewise. + (__arm_vqrdmlahq_n_s16): Likewise. + (__arm_vqrdmladhxq_s16): Likewise. + (__arm_vqrdmladhq_s16): Likewise. + (__arm_vqdmlsdhxq_s16): Likewise. + (__arm_vqdmlsdhq_s16): Likewise. + (__arm_vqdmlahq_n_s16): Likewise. + (__arm_vqdmladhxq_s16): Likewise. + (__arm_vqdmladhq_s16): Likewise. + (__arm_vmlsdavaxq_s16): Likewise. + (__arm_vmlsdavaq_s16): Likewise. + (__arm_vmlasq_n_s16): Likewise. + (__arm_vmlaq_n_s16): Likewise. + (__arm_vmladavaxq_s16): Likewise. + (__arm_vmladavaq_s16): Likewise. + (__arm_vsriq_n_s16): Likewise. + (__arm_vsliq_n_s16): Likewise. + (__arm_vpselq_u32): Likewise. + (__arm_vpselq_s32): Likewise. + (__arm_vrev64q_m_u32): Likewise. + (__arm_vqrdmlashq_n_u32): Likewise. + (__arm_vqrdmlahq_n_u32): Likewise. + (__arm_vqdmlahq_n_u32): Likewise. + (__arm_vmvnq_m_u32): Likewise. + (__arm_vmlasq_n_u32): Likewise. + (__arm_vmlaq_n_u32): Likewise. + (__arm_vmladavq_p_u32): Likewise. + (__arm_vmladavaq_u32): Likewise. + (__arm_vminvq_p_u32): Likewise. + (__arm_vmaxvq_p_u32): Likewise. + (__arm_vdupq_m_n_u32): Likewise. + (__arm_vcmpneq_m_u32): Likewise. + (__arm_vcmpneq_m_n_u32): Likewise. + (__arm_vcmphiq_m_u32): Likewise. + (__arm_vcmphiq_m_n_u32): Likewise. + (__arm_vcmpeqq_m_u32): Likewise. + (__arm_vcmpeqq_m_n_u32): Likewise. + (__arm_vcmpcsq_m_u32): Likewise. + (__arm_vcmpcsq_m_n_u32): Likewise. + (__arm_vclzq_m_u32): Likewise. + (__arm_vaddvaq_p_u32): Likewise. + (__arm_vsriq_n_u32): Likewise. + (__arm_vsliq_n_u32): Likewise. + (__arm_vshlq_m_r_u32): Likewise. + (__arm_vrshlq_m_n_u32): Likewise. + (__arm_vqshlq_m_r_u32): Likewise. + (__arm_vqrshlq_m_n_u32): Likewise. + (__arm_vminavq_p_s32): Likewise. + (__arm_vminaq_m_s32): Likewise. + (__arm_vmaxavq_p_s32): Likewise. + (__arm_vmaxaq_m_s32): Likewise. + (__arm_vcmpneq_m_s32): Likewise. + (__arm_vcmpneq_m_n_s32): Likewise. + (__arm_vcmpltq_m_s32): Likewise. + (__arm_vcmpltq_m_n_s32): Likewise. + (__arm_vcmpleq_m_s32): Likewise. + (__arm_vcmpleq_m_n_s32): Likewise. + (__arm_vcmpgtq_m_s32): Likewise. + (__arm_vcmpgtq_m_n_s32): Likewise. + (__arm_vcmpgeq_m_s32): Likewise. + (__arm_vcmpgeq_m_n_s32): Likewise. + (__arm_vcmpeqq_m_s32): Likewise. + (__arm_vcmpeqq_m_n_s32): Likewise. + (__arm_vshlq_m_r_s32): Likewise. + (__arm_vrshlq_m_n_s32): Likewise. + (__arm_vrev64q_m_s32): Likewise. + (__arm_vqshlq_m_r_s32): Likewise. + (__arm_vqrshlq_m_n_s32): Likewise. + (__arm_vqnegq_m_s32): Likewise. + (__arm_vqabsq_m_s32): Likewise. + (__arm_vnegq_m_s32): Likewise. + (__arm_vmvnq_m_s32): Likewise. + (__arm_vmlsdavxq_p_s32): Likewise. + (__arm_vmlsdavq_p_s32): Likewise. + (__arm_vmladavxq_p_s32): Likewise. + (__arm_vmladavq_p_s32): Likewise. + (__arm_vminvq_p_s32): Likewise. + (__arm_vmaxvq_p_s32): Likewise. + (__arm_vdupq_m_n_s32): Likewise. + (__arm_vclzq_m_s32): Likewise. + (__arm_vclsq_m_s32): Likewise. + (__arm_vaddvaq_p_s32): Likewise. + (__arm_vabsq_m_s32): Likewise. + (__arm_vqrdmlsdhxq_s32): Likewise. + (__arm_vqrdmlsdhq_s32): Likewise. + (__arm_vqrdmlashq_n_s32): Likewise. + (__arm_vqrdmlahq_n_s32): Likewise. + (__arm_vqrdmladhxq_s32): Likewise. + (__arm_vqrdmladhq_s32): Likewise. + (__arm_vqdmlsdhxq_s32): Likewise. + (__arm_vqdmlsdhq_s32): Likewise. + (__arm_vqdmlahq_n_s32): Likewise. + (__arm_vqdmladhxq_s32): Likewise. + (__arm_vqdmladhq_s32): Likewise. + (__arm_vmlsdavaxq_s32): Likewise. + (__arm_vmlsdavaq_s32): Likewise. + (__arm_vmlasq_n_s32): Likewise. + (__arm_vmlaq_n_s32): Likewise. + (__arm_vmladavaxq_s32): Likewise. + (__arm_vmladavaq_s32): Likewise. + (__arm_vsriq_n_s32): Likewise. + (__arm_vsliq_n_s32): Likewise. + (__arm_vpselq_u64): Likewise. + (__arm_vpselq_s64): Likewise. + (vcmpneq_m_n): Define polymorphic variant. + (vcmpneq_m): Likewise. + (vqrdmlsdhq): Likewise. + (vqrdmlsdhxq): Likewise. + (vqrshlq_m_n): Likewise. + (vqshlq_m_r): Likewise. + (vrev64q_m): Likewise. + (vrshlq_m_n): Likewise. + (vshlq_m_r): Likewise. + (vsliq_n): Likewise. + (vsriq_n): Likewise. + (vqrdmlashq_n): Likewise. + (vqrdmlahq): Likewise. + (vqrdmladhxq): Likewise. + (vqrdmladhq): Likewise. + (vqnegq_m): Likewise. + (vqdmlsdhxq): Likewise. + (vabsq_m): Likewise. + (vclsq_m): Likewise. + (vclzq_m): Likewise. + (vcmpgeq_m): Likewise. + (vcmpgeq_m_n): Likewise. + (vdupq_m_n): Likewise. + (vmaxaq_m): Likewise. + (vmlaq_n): Likewise. + (vmlasq_n): Likewise. + (vmvnq_m): Likewise. + (vnegq_m): Likewise. + (vpselq): Likewise. + (vqdmlahq_n): Likewise. + (vqrdmlahq_n): Likewise. + (vqdmlsdhq): Likewise. + (vqdmladhq): Likewise. + (vqabsq_m): Likewise. + (vminaq_m): Likewise. + (vrmlaldavhaq): Likewise. + (vmlsdavxq_p): Likewise. + (vmlsdavq_p): Likewise. + (vmlsdavaxq): Likewise. + (vmlsdavaq): Likewise. + (vaddvaq_p): Likewise. + (vcmpcsq_m_n): Likewise. + (vcmpcsq_m): Likewise. + (vcmpeqq_m_n): Likewise. + (vcmpeqq_m): Likewise. + (vmladavxq_p): Likewise. + (vmladavq_p): Likewise. + (vmladavaxq): Likewise. + (vmladavaq): Likewise. + (vminvq_p): Likewise. + (vminavq_p): Likewise. + (vmaxvq_p): Likewise. + (vmaxavq_p): Likewise. + (vcmpltq_m_n): Likewise. + (vcmpltq_m): Likewise. + (vcmpleq_m): Likewise. + (vcmpleq_m_n): Likewise. + (vcmphiq_m_n): Likewise. + (vcmphiq_m): Likewise. + (vcmpgtq_m_n): Likewise. + (vcmpgtq_m): Likewise. + * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use + builtin qualifier. + (TERNOP_NONE_NONE_NONE_NONE): Likewise. + (TERNOP_NONE_NONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. + (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. + * config/arm/constraints.md (Rc): Define constraint to check constant is + in the range of 0 to 15. + (Re): Define constraint to check constant is in the range of 0 to 31. + * config/arm/mve.md (VADDVAQ_P): Define iterator. + (VCLZQ_M): Likewise. + (VCMPEQQ_M_N): Likewise. + (VCMPEQQ_M): Likewise. + (VCMPNEQ_M_N): Likewise. + (VCMPNEQ_M): Likewise. + (VDUPQ_M_N): Likewise. + (VMAXVQ_P): Likewise. + (VMINVQ_P): Likewise. + (VMLADAVAQ): Likewise. + (VMLADAVQ_P): Likewise. + (VMLAQ_N): Likewise. + (VMLASQ_N): Likewise. + (VMVNQ_M): Likewise. + (VPSELQ): Likewise. + (VQDMLAHQ_N): Likewise. + (VQRDMLAHQ_N): Likewise. + (VQRDMLASHQ_N): Likewise. + (VQRSHLQ_M_N): Likewise. + (VQSHLQ_M_R): Likewise. + (VREV64Q_M): Likewise. + (VRSHLQ_M_N): Likewise. + (VSHLQ_M_R): Likewise. + (VSLIQ_N): Likewise. + (VSRIQ_N): Likewise. + (mve_vabsq_m_s): Define RTL pattern. + (mve_vaddvaq_p_): Likewise. + (mve_vclsq_m_s): Likewise. + (mve_vclzq_m_): Likewise. + (mve_vcmpcsq_m_n_u): Likewise. + (mve_vcmpcsq_m_u): Likewise. + (mve_vcmpeqq_m_n_): Likewise. + (mve_vcmpeqq_m_): Likewise. + (mve_vcmpgeq_m_n_s): Likewise. + (mve_vcmpgeq_m_s): Likewise. + (mve_vcmpgtq_m_n_s): Likewise. + (mve_vcmpgtq_m_s): Likewise. + (mve_vcmphiq_m_n_u): Likewise. + (mve_vcmphiq_m_u): Likewise. + (mve_vcmpleq_m_n_s): Likewise. + (mve_vcmpleq_m_s): Likewise. + (mve_vcmpltq_m_n_s): Likewise. + (mve_vcmpltq_m_s): Likewise. + (mve_vcmpneq_m_n_): Likewise. + (mve_vcmpneq_m_): Likewise. + (mve_vdupq_m_n_): Likewise. + (mve_vmaxaq_m_s): Likewise. + (mve_vmaxavq_p_s): Likewise. + (mve_vmaxvq_p_): Likewise. + (mve_vminaq_m_s): Likewise. + (mve_vminavq_p_s): Likewise. + (mve_vminvq_p_): Likewise. + (mve_vmladavaq_): Likewise. + (mve_vmladavq_p_): Likewise. + (mve_vmladavxq_p_s): Likewise. + (mve_vmlaq_n_): Likewise. + (mve_vmlasq_n_): Likewise. + (mve_vmlsdavq_p_s): Likewise. + (mve_vmlsdavxq_p_s): Likewise. + (mve_vmvnq_m_): Likewise. + (mve_vnegq_m_s): Likewise. + (mve_vpselq_): Likewise. + (mve_vqabsq_m_s): Likewise. + (mve_vqdmlahq_n_): Likewise. + (mve_vqnegq_m_s): Likewise. + (mve_vqrdmladhq_s): Likewise. + (mve_vqrdmladhxq_s): Likewise. + (mve_vqrdmlahq_n_): Likewise. + (mve_vqrdmlashq_n_): Likewise. + (mve_vqrdmlsdhq_s): Likewise. + (mve_vqrdmlsdhxq_s): Likewise. + (mve_vqrshlq_m_n_): Likewise. + (mve_vqshlq_m_r_): Likewise. + (mve_vrev64q_m_): Likewise. + (mve_vrshlq_m_n_): Likewise. + (mve_vshlq_m_r_): Likewise. + (mve_vsliq_n_): Likewise. + (mve_vsriq_n_): Likewise. + (mve_vqdmlsdhxq_s): Likewise. + (mve_vqdmlsdhq_s): Likewise. + (mve_vqdmladhxq_s): Likewise. + (mve_vqdmladhq_s): Likewise. + (mve_vmlsdavaxq_s): Likewise. + (mve_vmlsdavaq_s): Likewise. + (mve_vmladavaxq_s): Likewise. + * config/arm/predicates.md (mve_imm_15):Define predicate to check the + matching constraint Rc. + (mve_imm_31): Define predicate to check the matching constraint Re. + 2020-03-18 Andrew Stubbs * config/gcn/gcn-valu.md (vec_cmpdi): Set operand 1 to DImode. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index c15bb8b..f852c68 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -776,6 +776,263 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vabavq_u8(__a, __b, __c) __arm_vabavq_u8(__a, __b, __c) #define vabavq_u16(__a, __b, __c) __arm_vabavq_u16(__a, __b, __c) #define vabavq_u32(__a, __b, __c) __arm_vabavq_u32(__a, __b, __c) +#define vpselq_u8(__a, __b, __p) __arm_vpselq_u8(__a, __b, __p) +#define vpselq_s8(__a, __b, __p) __arm_vpselq_s8(__a, __b, __p) +#define vrev64q_m_u8(__inactive, __a, __p) __arm_vrev64q_m_u8(__inactive, __a, __p) +#define vqrdmlashq_n_u8(__a, __b, __c) __arm_vqrdmlashq_n_u8(__a, __b, __c) +#define vqrdmlahq_n_u8(__a, __b, __c) __arm_vqrdmlahq_n_u8(__a, __b, __c) +#define vqdmlahq_n_u8(__a, __b, __c) __arm_vqdmlahq_n_u8(__a, __b, __c) +#define vmvnq_m_u8(__inactive, __a, __p) __arm_vmvnq_m_u8(__inactive, __a, __p) +#define vmlasq_n_u8(__a, __b, __c) __arm_vmlasq_n_u8(__a, __b, __c) +#define vmlaq_n_u8(__a, __b, __c) __arm_vmlaq_n_u8(__a, __b, __c) +#define vmladavq_p_u8(__a, __b, __p) __arm_vmladavq_p_u8(__a, __b, __p) +#define vmladavaq_u8(__a, __b, __c) __arm_vmladavaq_u8(__a, __b, __c) +#define vminvq_p_u8(__a, __b, __p) __arm_vminvq_p_u8(__a, __b, __p) +#define vmaxvq_p_u8(__a, __b, __p) __arm_vmaxvq_p_u8(__a, __b, __p) +#define vdupq_m_n_u8(__inactive, __a, __p) __arm_vdupq_m_n_u8(__inactive, __a, __p) +#define vcmpneq_m_u8(__a, __b, __p) __arm_vcmpneq_m_u8(__a, __b, __p) +#define vcmpneq_m_n_u8(__a, __b, __p) __arm_vcmpneq_m_n_u8(__a, __b, __p) +#define vcmphiq_m_u8(__a, __b, __p) __arm_vcmphiq_m_u8(__a, __b, __p) +#define vcmphiq_m_n_u8(__a, __b, __p) __arm_vcmphiq_m_n_u8(__a, __b, __p) +#define vcmpeqq_m_u8(__a, __b, __p) __arm_vcmpeqq_m_u8(__a, __b, __p) +#define vcmpeqq_m_n_u8(__a, __b, __p) __arm_vcmpeqq_m_n_u8(__a, __b, __p) +#define vcmpcsq_m_u8(__a, __b, __p) __arm_vcmpcsq_m_u8(__a, __b, __p) +#define vcmpcsq_m_n_u8(__a, __b, __p) __arm_vcmpcsq_m_n_u8(__a, __b, __p) +#define vclzq_m_u8(__inactive, __a, __p) __arm_vclzq_m_u8(__inactive, __a, __p) +#define vaddvaq_p_u8(__a, __b, __p) __arm_vaddvaq_p_u8(__a, __b, __p) +#define vsriq_n_u8(__a, __b, __imm) __arm_vsriq_n_u8(__a, __b, __imm) +#define vsliq_n_u8(__a, __b, __imm) __arm_vsliq_n_u8(__a, __b, __imm) +#define vshlq_m_r_u8(__a, __b, __p) __arm_vshlq_m_r_u8(__a, __b, __p) +#define vrshlq_m_n_u8(__a, __b, __p) __arm_vrshlq_m_n_u8(__a, __b, __p) +#define vqshlq_m_r_u8(__a, __b, __p) __arm_vqshlq_m_r_u8(__a, __b, __p) +#define vqrshlq_m_n_u8(__a, __b, __p) __arm_vqrshlq_m_n_u8(__a, __b, __p) +#define vminavq_p_s8(__a, __b, __p) __arm_vminavq_p_s8(__a, __b, __p) +#define vminaq_m_s8(__a, __b, __p) __arm_vminaq_m_s8(__a, __b, __p) +#define vmaxavq_p_s8(__a, __b, __p) __arm_vmaxavq_p_s8(__a, __b, __p) +#define vmaxaq_m_s8(__a, __b, __p) __arm_vmaxaq_m_s8(__a, __b, __p) +#define vcmpneq_m_s8(__a, __b, __p) __arm_vcmpneq_m_s8(__a, __b, __p) +#define vcmpneq_m_n_s8(__a, __b, __p) __arm_vcmpneq_m_n_s8(__a, __b, __p) +#define vcmpltq_m_s8(__a, __b, __p) __arm_vcmpltq_m_s8(__a, __b, __p) +#define vcmpltq_m_n_s8(__a, __b, __p) __arm_vcmpltq_m_n_s8(__a, __b, __p) +#define vcmpleq_m_s8(__a, __b, __p) __arm_vcmpleq_m_s8(__a, __b, __p) +#define vcmpleq_m_n_s8(__a, __b, __p) __arm_vcmpleq_m_n_s8(__a, __b, __p) +#define vcmpgtq_m_s8(__a, __b, __p) __arm_vcmpgtq_m_s8(__a, __b, __p) +#define vcmpgtq_m_n_s8(__a, __b, __p) __arm_vcmpgtq_m_n_s8(__a, __b, __p) +#define vcmpgeq_m_s8(__a, __b, __p) __arm_vcmpgeq_m_s8(__a, __b, __p) +#define vcmpgeq_m_n_s8(__a, __b, __p) __arm_vcmpgeq_m_n_s8(__a, __b, __p) +#define vcmpeqq_m_s8(__a, __b, __p) __arm_vcmpeqq_m_s8(__a, __b, __p) +#define vcmpeqq_m_n_s8(__a, __b, __p) __arm_vcmpeqq_m_n_s8(__a, __b, __p) +#define vshlq_m_r_s8(__a, __b, __p) __arm_vshlq_m_r_s8(__a, __b, __p) +#define vrshlq_m_n_s8(__a, __b, __p) __arm_vrshlq_m_n_s8(__a, __b, __p) +#define vrev64q_m_s8(__inactive, __a, __p) __arm_vrev64q_m_s8(__inactive, __a, __p) +#define vqshlq_m_r_s8(__a, __b, __p) __arm_vqshlq_m_r_s8(__a, __b, __p) +#define vqrshlq_m_n_s8(__a, __b, __p) __arm_vqrshlq_m_n_s8(__a, __b, __p) +#define vqnegq_m_s8(__inactive, __a, __p) __arm_vqnegq_m_s8(__inactive, __a, __p) +#define vqabsq_m_s8(__inactive, __a, __p) __arm_vqabsq_m_s8(__inactive, __a, __p) +#define vnegq_m_s8(__inactive, __a, __p) __arm_vnegq_m_s8(__inactive, __a, __p) +#define vmvnq_m_s8(__inactive, __a, __p) __arm_vmvnq_m_s8(__inactive, __a, __p) +#define vmlsdavxq_p_s8(__a, __b, __p) __arm_vmlsdavxq_p_s8(__a, __b, __p) +#define vmlsdavq_p_s8(__a, __b, __p) __arm_vmlsdavq_p_s8(__a, __b, __p) +#define vmladavxq_p_s8(__a, __b, __p) __arm_vmladavxq_p_s8(__a, __b, __p) +#define vmladavq_p_s8(__a, __b, __p) __arm_vmladavq_p_s8(__a, __b, __p) +#define vminvq_p_s8(__a, __b, __p) __arm_vminvq_p_s8(__a, __b, __p) +#define vmaxvq_p_s8(__a, __b, __p) __arm_vmaxvq_p_s8(__a, __b, __p) +#define vdupq_m_n_s8(__inactive, __a, __p) __arm_vdupq_m_n_s8(__inactive, __a, __p) +#define vclzq_m_s8(__inactive, __a, __p) __arm_vclzq_m_s8(__inactive, __a, __p) +#define vclsq_m_s8(__inactive, __a, __p) __arm_vclsq_m_s8(__inactive, __a, __p) +#define vaddvaq_p_s8(__a, __b, __p) __arm_vaddvaq_p_s8(__a, __b, __p) +#define vabsq_m_s8(__inactive, __a, __p) __arm_vabsq_m_s8(__inactive, __a, __p) +#define vqrdmlsdhxq_s8(__inactive, __a, __b) __arm_vqrdmlsdhxq_s8(__inactive, __a, __b) +#define vqrdmlsdhq_s8(__inactive, __a, __b) __arm_vqrdmlsdhq_s8(__inactive, __a, __b) +#define vqrdmlashq_n_s8(__a, __b, __c) __arm_vqrdmlashq_n_s8(__a, __b, __c) +#define vqrdmlahq_n_s8(__a, __b, __c) __arm_vqrdmlahq_n_s8(__a, __b, __c) +#define vqrdmladhxq_s8(__inactive, __a, __b) __arm_vqrdmladhxq_s8(__inactive, __a, __b) +#define vqrdmladhq_s8(__inactive, __a, __b) __arm_vqrdmladhq_s8(__inactive, __a, __b) +#define vqdmlsdhxq_s8(__inactive, __a, __b) __arm_vqdmlsdhxq_s8(__inactive, __a, __b) +#define vqdmlsdhq_s8(__inactive, __a, __b) __arm_vqdmlsdhq_s8(__inactive, __a, __b) +#define vqdmlahq_n_s8(__a, __b, __c) __arm_vqdmlahq_n_s8(__a, __b, __c) +#define vqdmladhxq_s8(__inactive, __a, __b) __arm_vqdmladhxq_s8(__inactive, __a, __b) +#define vqdmladhq_s8(__inactive, __a, __b) __arm_vqdmladhq_s8(__inactive, __a, __b) +#define vmlsdavaxq_s8(__a, __b, __c) __arm_vmlsdavaxq_s8(__a, __b, __c) +#define vmlsdavaq_s8(__a, __b, __c) __arm_vmlsdavaq_s8(__a, __b, __c) +#define vmlasq_n_s8(__a, __b, __c) __arm_vmlasq_n_s8(__a, __b, __c) +#define vmlaq_n_s8(__a, __b, __c) __arm_vmlaq_n_s8(__a, __b, __c) +#define vmladavaxq_s8(__a, __b, __c) __arm_vmladavaxq_s8(__a, __b, __c) +#define vmladavaq_s8(__a, __b, __c) __arm_vmladavaq_s8(__a, __b, __c) +#define vsriq_n_s8(__a, __b, __imm) __arm_vsriq_n_s8(__a, __b, __imm) +#define vsliq_n_s8(__a, __b, __imm) __arm_vsliq_n_s8(__a, __b, __imm) +#define vpselq_u16(__a, __b, __p) __arm_vpselq_u16(__a, __b, __p) +#define vpselq_s16(__a, __b, __p) __arm_vpselq_s16(__a, __b, __p) +#define vrev64q_m_u16(__inactive, __a, __p) __arm_vrev64q_m_u16(__inactive, __a, __p) +#define vqrdmlashq_n_u16(__a, __b, __c) __arm_vqrdmlashq_n_u16(__a, __b, __c) +#define vqrdmlahq_n_u16(__a, __b, __c) __arm_vqrdmlahq_n_u16(__a, __b, __c) +#define vqdmlahq_n_u16(__a, __b, __c) __arm_vqdmlahq_n_u16(__a, __b, __c) +#define vmvnq_m_u16(__inactive, __a, __p) __arm_vmvnq_m_u16(__inactive, __a, __p) +#define vmlasq_n_u16(__a, __b, __c) __arm_vmlasq_n_u16(__a, __b, __c) +#define vmlaq_n_u16(__a, __b, __c) __arm_vmlaq_n_u16(__a, __b, __c) +#define vmladavq_p_u16(__a, __b, __p) __arm_vmladavq_p_u16(__a, __b, __p) +#define vmladavaq_u16(__a, __b, __c) __arm_vmladavaq_u16(__a, __b, __c) +#define vminvq_p_u16(__a, __b, __p) __arm_vminvq_p_u16(__a, __b, __p) +#define vmaxvq_p_u16(__a, __b, __p) __arm_vmaxvq_p_u16(__a, __b, __p) +#define vdupq_m_n_u16(__inactive, __a, __p) __arm_vdupq_m_n_u16(__inactive, __a, __p) +#define vcmpneq_m_u16(__a, __b, __p) __arm_vcmpneq_m_u16(__a, __b, __p) +#define vcmpneq_m_n_u16(__a, __b, __p) __arm_vcmpneq_m_n_u16(__a, __b, __p) +#define vcmphiq_m_u16(__a, __b, __p) __arm_vcmphiq_m_u16(__a, __b, __p) +#define vcmphiq_m_n_u16(__a, __b, __p) __arm_vcmphiq_m_n_u16(__a, __b, __p) +#define vcmpeqq_m_u16(__a, __b, __p) __arm_vcmpeqq_m_u16(__a, __b, __p) +#define vcmpeqq_m_n_u16(__a, __b, __p) __arm_vcmpeqq_m_n_u16(__a, __b, __p) +#define vcmpcsq_m_u16(__a, __b, __p) __arm_vcmpcsq_m_u16(__a, __b, __p) +#define vcmpcsq_m_n_u16(__a, __b, __p) __arm_vcmpcsq_m_n_u16(__a, __b, __p) +#define vclzq_m_u16(__inactive, __a, __p) __arm_vclzq_m_u16(__inactive, __a, __p) +#define vaddvaq_p_u16(__a, __b, __p) __arm_vaddvaq_p_u16(__a, __b, __p) +#define vsriq_n_u16(__a, __b, __imm) __arm_vsriq_n_u16(__a, __b, __imm) +#define vsliq_n_u16(__a, __b, __imm) __arm_vsliq_n_u16(__a, __b, __imm) +#define vshlq_m_r_u16(__a, __b, __p) __arm_vshlq_m_r_u16(__a, __b, __p) +#define vrshlq_m_n_u16(__a, __b, __p) __arm_vrshlq_m_n_u16(__a, __b, __p) +#define vqshlq_m_r_u16(__a, __b, __p) __arm_vqshlq_m_r_u16(__a, __b, __p) +#define vqrshlq_m_n_u16(__a, __b, __p) __arm_vqrshlq_m_n_u16(__a, __b, __p) +#define vminavq_p_s16(__a, __b, __p) __arm_vminavq_p_s16(__a, __b, __p) +#define vminaq_m_s16(__a, __b, __p) __arm_vminaq_m_s16(__a, __b, __p) +#define vmaxavq_p_s16(__a, __b, __p) __arm_vmaxavq_p_s16(__a, __b, __p) +#define vmaxaq_m_s16(__a, __b, __p) __arm_vmaxaq_m_s16(__a, __b, __p) +#define vcmpneq_m_s16(__a, __b, __p) __arm_vcmpneq_m_s16(__a, __b, __p) +#define vcmpneq_m_n_s16(__a, __b, __p) __arm_vcmpneq_m_n_s16(__a, __b, __p) +#define vcmpltq_m_s16(__a, __b, __p) __arm_vcmpltq_m_s16(__a, __b, __p) +#define vcmpltq_m_n_s16(__a, __b, __p) __arm_vcmpltq_m_n_s16(__a, __b, __p) +#define vcmpleq_m_s16(__a, __b, __p) __arm_vcmpleq_m_s16(__a, __b, __p) +#define vcmpleq_m_n_s16(__a, __b, __p) __arm_vcmpleq_m_n_s16(__a, __b, __p) +#define vcmpgtq_m_s16(__a, __b, __p) __arm_vcmpgtq_m_s16(__a, __b, __p) +#define vcmpgtq_m_n_s16(__a, __b, __p) __arm_vcmpgtq_m_n_s16(__a, __b, __p) +#define vcmpgeq_m_s16(__a, __b, __p) __arm_vcmpgeq_m_s16(__a, __b, __p) +#define vcmpgeq_m_n_s16(__a, __b, __p) __arm_vcmpgeq_m_n_s16(__a, __b, __p) +#define vcmpeqq_m_s16(__a, __b, __p) __arm_vcmpeqq_m_s16(__a, __b, __p) +#define vcmpeqq_m_n_s16(__a, __b, __p) __arm_vcmpeqq_m_n_s16(__a, __b, __p) +#define vshlq_m_r_s16(__a, __b, __p) __arm_vshlq_m_r_s16(__a, __b, __p) +#define vrshlq_m_n_s16(__a, __b, __p) __arm_vrshlq_m_n_s16(__a, __b, __p) +#define vrev64q_m_s16(__inactive, __a, __p) __arm_vrev64q_m_s16(__inactive, __a, __p) +#define vqshlq_m_r_s16(__a, __b, __p) __arm_vqshlq_m_r_s16(__a, __b, __p) +#define vqrshlq_m_n_s16(__a, __b, __p) __arm_vqrshlq_m_n_s16(__a, __b, __p) +#define vqnegq_m_s16(__inactive, __a, __p) __arm_vqnegq_m_s16(__inactive, __a, __p) +#define vqabsq_m_s16(__inactive, __a, __p) __arm_vqabsq_m_s16(__inactive, __a, __p) +#define vnegq_m_s16(__inactive, __a, __p) __arm_vnegq_m_s16(__inactive, __a, __p) +#define vmvnq_m_s16(__inactive, __a, __p) __arm_vmvnq_m_s16(__inactive, __a, __p) +#define vmlsdavxq_p_s16(__a, __b, __p) __arm_vmlsdavxq_p_s16(__a, __b, __p) +#define vmlsdavq_p_s16(__a, __b, __p) __arm_vmlsdavq_p_s16(__a, __b, __p) +#define vmladavxq_p_s16(__a, __b, __p) __arm_vmladavxq_p_s16(__a, __b, __p) +#define vmladavq_p_s16(__a, __b, __p) __arm_vmladavq_p_s16(__a, __b, __p) +#define vminvq_p_s16(__a, __b, __p) __arm_vminvq_p_s16(__a, __b, __p) +#define vmaxvq_p_s16(__a, __b, __p) __arm_vmaxvq_p_s16(__a, __b, __p) +#define vdupq_m_n_s16(__inactive, __a, __p) __arm_vdupq_m_n_s16(__inactive, __a, __p) +#define vclzq_m_s16(__inactive, __a, __p) __arm_vclzq_m_s16(__inactive, __a, __p) +#define vclsq_m_s16(__inactive, __a, __p) __arm_vclsq_m_s16(__inactive, __a, __p) +#define vaddvaq_p_s16(__a, __b, __p) __arm_vaddvaq_p_s16(__a, __b, __p) +#define vabsq_m_s16(__inactive, __a, __p) __arm_vabsq_m_s16(__inactive, __a, __p) +#define vqrdmlsdhxq_s16(__inactive, __a, __b) __arm_vqrdmlsdhxq_s16(__inactive, __a, __b) +#define vqrdmlsdhq_s16(__inactive, __a, __b) __arm_vqrdmlsdhq_s16(__inactive, __a, __b) +#define vqrdmlashq_n_s16(__a, __b, __c) __arm_vqrdmlashq_n_s16(__a, __b, __c) +#define vqrdmlahq_n_s16(__a, __b, __c) __arm_vqrdmlahq_n_s16(__a, __b, __c) +#define vqrdmladhxq_s16(__inactive, __a, __b) __arm_vqrdmladhxq_s16(__inactive, __a, __b) +#define vqrdmladhq_s16(__inactive, __a, __b) __arm_vqrdmladhq_s16(__inactive, __a, __b) +#define vqdmlsdhxq_s16(__inactive, __a, __b) __arm_vqdmlsdhxq_s16(__inactive, __a, __b) +#define vqdmlsdhq_s16(__inactive, __a, __b) __arm_vqdmlsdhq_s16(__inactive, __a, __b) +#define vqdmlahq_n_s16(__a, __b, __c) __arm_vqdmlahq_n_s16(__a, __b, __c) +#define vqdmladhxq_s16(__inactive, __a, __b) __arm_vqdmladhxq_s16(__inactive, __a, __b) +#define vqdmladhq_s16(__inactive, __a, __b) __arm_vqdmladhq_s16(__inactive, __a, __b) +#define vmlsdavaxq_s16(__a, __b, __c) __arm_vmlsdavaxq_s16(__a, __b, __c) +#define vmlsdavaq_s16(__a, __b, __c) __arm_vmlsdavaq_s16(__a, __b, __c) +#define vmlasq_n_s16(__a, __b, __c) __arm_vmlasq_n_s16(__a, __b, __c) +#define vmlaq_n_s16(__a, __b, __c) __arm_vmlaq_n_s16(__a, __b, __c) +#define vmladavaxq_s16(__a, __b, __c) __arm_vmladavaxq_s16(__a, __b, __c) +#define vmladavaq_s16(__a, __b, __c) __arm_vmladavaq_s16(__a, __b, __c) +#define vsriq_n_s16(__a, __b, __imm) __arm_vsriq_n_s16(__a, __b, __imm) +#define vsliq_n_s16(__a, __b, __imm) __arm_vsliq_n_s16(__a, __b, __imm) +#define vpselq_u32(__a, __b, __p) __arm_vpselq_u32(__a, __b, __p) +#define vpselq_s32(__a, __b, __p) __arm_vpselq_s32(__a, __b, __p) +#define vrev64q_m_u32(__inactive, __a, __p) __arm_vrev64q_m_u32(__inactive, __a, __p) +#define vqrdmlashq_n_u32(__a, __b, __c) __arm_vqrdmlashq_n_u32(__a, __b, __c) +#define vqrdmlahq_n_u32(__a, __b, __c) __arm_vqrdmlahq_n_u32(__a, __b, __c) +#define vqdmlahq_n_u32(__a, __b, __c) __arm_vqdmlahq_n_u32(__a, __b, __c) +#define vmvnq_m_u32(__inactive, __a, __p) __arm_vmvnq_m_u32(__inactive, __a, __p) +#define vmlasq_n_u32(__a, __b, __c) __arm_vmlasq_n_u32(__a, __b, __c) +#define vmlaq_n_u32(__a, __b, __c) __arm_vmlaq_n_u32(__a, __b, __c) +#define vmladavq_p_u32(__a, __b, __p) __arm_vmladavq_p_u32(__a, __b, __p) +#define vmladavaq_u32(__a, __b, __c) __arm_vmladavaq_u32(__a, __b, __c) +#define vminvq_p_u32(__a, __b, __p) __arm_vminvq_p_u32(__a, __b, __p) +#define vmaxvq_p_u32(__a, __b, __p) __arm_vmaxvq_p_u32(__a, __b, __p) +#define vdupq_m_n_u32(__inactive, __a, __p) __arm_vdupq_m_n_u32(__inactive, __a, __p) +#define vcmpneq_m_u32(__a, __b, __p) __arm_vcmpneq_m_u32(__a, __b, __p) +#define vcmpneq_m_n_u32(__a, __b, __p) __arm_vcmpneq_m_n_u32(__a, __b, __p) +#define vcmphiq_m_u32(__a, __b, __p) __arm_vcmphiq_m_u32(__a, __b, __p) +#define vcmphiq_m_n_u32(__a, __b, __p) __arm_vcmphiq_m_n_u32(__a, __b, __p) +#define vcmpeqq_m_u32(__a, __b, __p) __arm_vcmpeqq_m_u32(__a, __b, __p) +#define vcmpeqq_m_n_u32(__a, __b, __p) __arm_vcmpeqq_m_n_u32(__a, __b, __p) +#define vcmpcsq_m_u32(__a, __b, __p) __arm_vcmpcsq_m_u32(__a, __b, __p) +#define vcmpcsq_m_n_u32(__a, __b, __p) __arm_vcmpcsq_m_n_u32(__a, __b, __p) +#define vclzq_m_u32(__inactive, __a, __p) __arm_vclzq_m_u32(__inactive, __a, __p) +#define vaddvaq_p_u32(__a, __b, __p) __arm_vaddvaq_p_u32(__a, __b, __p) +#define vsriq_n_u32(__a, __b, __imm) __arm_vsriq_n_u32(__a, __b, __imm) +#define vsliq_n_u32(__a, __b, __imm) __arm_vsliq_n_u32(__a, __b, __imm) +#define vshlq_m_r_u32(__a, __b, __p) __arm_vshlq_m_r_u32(__a, __b, __p) +#define vrshlq_m_n_u32(__a, __b, __p) __arm_vrshlq_m_n_u32(__a, __b, __p) +#define vqshlq_m_r_u32(__a, __b, __p) __arm_vqshlq_m_r_u32(__a, __b, __p) +#define vqrshlq_m_n_u32(__a, __b, __p) __arm_vqrshlq_m_n_u32(__a, __b, __p) +#define vminavq_p_s32(__a, __b, __p) __arm_vminavq_p_s32(__a, __b, __p) +#define vminaq_m_s32(__a, __b, __p) __arm_vminaq_m_s32(__a, __b, __p) +#define vmaxavq_p_s32(__a, __b, __p) __arm_vmaxavq_p_s32(__a, __b, __p) +#define vmaxaq_m_s32(__a, __b, __p) __arm_vmaxaq_m_s32(__a, __b, __p) +#define vcmpneq_m_s32(__a, __b, __p) __arm_vcmpneq_m_s32(__a, __b, __p) +#define vcmpneq_m_n_s32(__a, __b, __p) __arm_vcmpneq_m_n_s32(__a, __b, __p) +#define vcmpltq_m_s32(__a, __b, __p) __arm_vcmpltq_m_s32(__a, __b, __p) +#define vcmpltq_m_n_s32(__a, __b, __p) __arm_vcmpltq_m_n_s32(__a, __b, __p) +#define vcmpleq_m_s32(__a, __b, __p) __arm_vcmpleq_m_s32(__a, __b, __p) +#define vcmpleq_m_n_s32(__a, __b, __p) __arm_vcmpleq_m_n_s32(__a, __b, __p) +#define vcmpgtq_m_s32(__a, __b, __p) __arm_vcmpgtq_m_s32(__a, __b, __p) +#define vcmpgtq_m_n_s32(__a, __b, __p) __arm_vcmpgtq_m_n_s32(__a, __b, __p) +#define vcmpgeq_m_s32(__a, __b, __p) __arm_vcmpgeq_m_s32(__a, __b, __p) +#define vcmpgeq_m_n_s32(__a, __b, __p) __arm_vcmpgeq_m_n_s32(__a, __b, __p) +#define vcmpeqq_m_s32(__a, __b, __p) __arm_vcmpeqq_m_s32(__a, __b, __p) +#define vcmpeqq_m_n_s32(__a, __b, __p) __arm_vcmpeqq_m_n_s32(__a, __b, __p) +#define vshlq_m_r_s32(__a, __b, __p) __arm_vshlq_m_r_s32(__a, __b, __p) +#define vrshlq_m_n_s32(__a, __b, __p) __arm_vrshlq_m_n_s32(__a, __b, __p) +#define vrev64q_m_s32(__inactive, __a, __p) __arm_vrev64q_m_s32(__inactive, __a, __p) +#define vqshlq_m_r_s32(__a, __b, __p) __arm_vqshlq_m_r_s32(__a, __b, __p) +#define vqrshlq_m_n_s32(__a, __b, __p) __arm_vqrshlq_m_n_s32(__a, __b, __p) +#define vqnegq_m_s32(__inactive, __a, __p) __arm_vqnegq_m_s32(__inactive, __a, __p) +#define vqabsq_m_s32(__inactive, __a, __p) __arm_vqabsq_m_s32(__inactive, __a, __p) +#define vnegq_m_s32(__inactive, __a, __p) __arm_vnegq_m_s32(__inactive, __a, __p) +#define vmvnq_m_s32(__inactive, __a, __p) __arm_vmvnq_m_s32(__inactive, __a, __p) +#define vmlsdavxq_p_s32(__a, __b, __p) __arm_vmlsdavxq_p_s32(__a, __b, __p) +#define vmlsdavq_p_s32(__a, __b, __p) __arm_vmlsdavq_p_s32(__a, __b, __p) +#define vmladavxq_p_s32(__a, __b, __p) __arm_vmladavxq_p_s32(__a, __b, __p) +#define vmladavq_p_s32(__a, __b, __p) __arm_vmladavq_p_s32(__a, __b, __p) +#define vminvq_p_s32(__a, __b, __p) __arm_vminvq_p_s32(__a, __b, __p) +#define vmaxvq_p_s32(__a, __b, __p) __arm_vmaxvq_p_s32(__a, __b, __p) +#define vdupq_m_n_s32(__inactive, __a, __p) __arm_vdupq_m_n_s32(__inactive, __a, __p) +#define vclzq_m_s32(__inactive, __a, __p) __arm_vclzq_m_s32(__inactive, __a, __p) +#define vclsq_m_s32(__inactive, __a, __p) __arm_vclsq_m_s32(__inactive, __a, __p) +#define vaddvaq_p_s32(__a, __b, __p) __arm_vaddvaq_p_s32(__a, __b, __p) +#define vabsq_m_s32(__inactive, __a, __p) __arm_vabsq_m_s32(__inactive, __a, __p) +#define vqrdmlsdhxq_s32(__inactive, __a, __b) __arm_vqrdmlsdhxq_s32(__inactive, __a, __b) +#define vqrdmlsdhq_s32(__inactive, __a, __b) __arm_vqrdmlsdhq_s32(__inactive, __a, __b) +#define vqrdmlashq_n_s32(__a, __b, __c) __arm_vqrdmlashq_n_s32(__a, __b, __c) +#define vqrdmlahq_n_s32(__a, __b, __c) __arm_vqrdmlahq_n_s32(__a, __b, __c) +#define vqrdmladhxq_s32(__inactive, __a, __b) __arm_vqrdmladhxq_s32(__inactive, __a, __b) +#define vqrdmladhq_s32(__inactive, __a, __b) __arm_vqrdmladhq_s32(__inactive, __a, __b) +#define vqdmlsdhxq_s32(__inactive, __a, __b) __arm_vqdmlsdhxq_s32(__inactive, __a, __b) +#define vqdmlsdhq_s32(__inactive, __a, __b) __arm_vqdmlsdhq_s32(__inactive, __a, __b) +#define vqdmlahq_n_s32(__a, __b, __c) __arm_vqdmlahq_n_s32(__a, __b, __c) +#define vqdmladhxq_s32(__inactive, __a, __b) __arm_vqdmladhxq_s32(__inactive, __a, __b) +#define vqdmladhq_s32(__inactive, __a, __b) __arm_vqdmladhq_s32(__inactive, __a, __b) +#define vmlsdavaxq_s32(__a, __b, __c) __arm_vmlsdavaxq_s32(__a, __b, __c) +#define vmlsdavaq_s32(__a, __b, __c) __arm_vmlsdavaq_s32(__a, __b, __c) +#define vmlasq_n_s32(__a, __b, __c) __arm_vmlasq_n_s32(__a, __b, __c) +#define vmlaq_n_s32(__a, __b, __c) __arm_vmlaq_n_s32(__a, __b, __c) +#define vmladavaxq_s32(__a, __b, __c) __arm_vmladavaxq_s32(__a, __b, __c) +#define vmladavaq_s32(__a, __b, __c) __arm_vmladavaq_s32(__a, __b, __c) +#define vsriq_n_s32(__a, __b, __imm) __arm_vsriq_n_s32(__a, __b, __imm) +#define vsliq_n_s32(__a, __b, __imm) __arm_vsliq_n_s32(__a, __b, __imm) +#define vpselq_u64(__a, __b, __p) __arm_vpselq_u64(__a, __b, __p) +#define vpselq_s64(__a, __b, __p) __arm_vpselq_s64(__a, __b, __p) #endif __extension__ extern __inline void @@ -4699,6 +4956,1805 @@ __arm_vshlcq_u32 (uint32x4_t __a, uint32_t * __b, const int __imm) return __res; } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_uv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c) +{ + return __builtin_mve_vqrdmlashq_n_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c) +{ + return __builtin_mve_vqrdmlahq_n_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c) +{ + return __builtin_mve_vqdmlahq_n_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_uv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c) +{ + return __builtin_mve_vmlasq_n_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c) +{ + return __builtin_mve_vmlaq_n_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c) +{ + return __builtin_mve_vmladavaq_uv16qi (__a, __b, __c); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_u8 (uint8_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_u8 (uint8_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_u8 (uint8x16_t __inactive, uint8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_uv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_uv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_u8 (uint32_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_uv16qi (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_uv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_p_s8 (uint8_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminavq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminaq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_p_s8 (uint8_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxavq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxaq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqnegq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqabsq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_sv16qi (__inactive, __a, __p); +} + + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_p_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavxq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_p_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_p_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavxq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_s8 (int8_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_s8 (int8_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_s8 (int8x16_t __inactive, int8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclsq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_s8 (int32_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_sv16qi (__a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_sv16qi (__inactive, __a, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrdmlsdhxq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrdmlsdhq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c) +{ + return __builtin_mve_vqrdmlashq_n_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c) +{ + return __builtin_mve_vqrdmlahq_n_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrdmladhxq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqrdmladhq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqdmlsdhxq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqdmlsdhq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c) +{ + return __builtin_mve_vqdmlahq_n_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqdmladhxq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b) +{ + return __builtin_mve_vqdmladhq_sv16qi (__inactive, __a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_s8 (int32_t __a, int8x16_t __b, int8x16_t __c) +{ + return __builtin_mve_vmlsdavaxq_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_s8 (int32_t __a, int8x16_t __b, int8x16_t __c) +{ + return __builtin_mve_vmlsdavaq_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c) +{ + return __builtin_mve_vmlasq_n_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c) +{ + return __builtin_mve_vmlaq_n_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_s8 (int32_t __a, int8x16_t __b, int8x16_t __c) +{ + return __builtin_mve_vmladavaxq_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_s8 (int32_t __a, int8x16_t __b, int8x16_t __c) +{ + return __builtin_mve_vmladavaq_sv16qi (__a, __b, __c); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_sv16qi (__a, __b, __imm); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_sv16qi (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return __builtin_mve_vqrdmlashq_n_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return __builtin_mve_vqrdmlahq_n_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return __builtin_mve_vqdmlahq_n_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return __builtin_mve_vmlasq_n_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) +{ + return __builtin_mve_vmlaq_n_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c) +{ + return __builtin_mve_vmladavaq_uv8hi (__a, __b, __c); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_u16 (uint16_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_u16 (uint16_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_u16 (uint16x8_t __inactive, uint16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_u16 (uint32_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_uv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_uv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_p_s16 (uint16_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminavq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminaq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_p_s16 (uint16_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxavq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxaq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqnegq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqabsq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavxq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavxq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_s16 (int16_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_s16 (int16_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_s16 (int16x8_t __inactive, int16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclsq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_s16 (int32_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_sv8hi (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrdmlsdhxq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrdmlsdhq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return __builtin_mve_vqrdmlashq_n_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return __builtin_mve_vqrdmlahq_n_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrdmladhxq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqrdmladhq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqdmlsdhxq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqdmlsdhq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return __builtin_mve_vqdmlahq_n_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqdmladhxq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b) +{ + return __builtin_mve_vqdmladhq_sv8hi (__inactive, __a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_s16 (int32_t __a, int16x8_t __b, int16x8_t __c) +{ + return __builtin_mve_vmlsdavaxq_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_s16 (int32_t __a, int16x8_t __b, int16x8_t __c) +{ + return __builtin_mve_vmlsdavaq_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return __builtin_mve_vmlasq_n_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) +{ + return __builtin_mve_vmlaq_n_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_s16 (int32_t __a, int16x8_t __b, int16x8_t __c) +{ + return __builtin_mve_vmladavaxq_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_s16 (int32_t __a, int16x8_t __b, int16x8_t __c) +{ + return __builtin_mve_vmladavaq_sv8hi (__a, __b, __c); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_sv8hi (__a, __b, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_sv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_uv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_sv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return __builtin_mve_vqrdmlashq_n_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return __builtin_mve_vqrdmlahq_n_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return __builtin_mve_vqdmlahq_n_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return __builtin_mve_vmlasq_n_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) +{ + return __builtin_mve_vmlaq_n_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c) +{ + return __builtin_mve_vmladavaq_uv4si (__a, __b, __c); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_u32 (uint32_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_u32 (uint32_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmphiq_m_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmphiq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_uv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpcsq_m_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpcsq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_u32 (uint32_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_uv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_uv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminavq_p_s32 (uint32_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminavq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminaq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxavq_p_s32 (uint32_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxavq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxaq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_sv4si (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_r_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_r_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_r_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_r_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_n_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqnegq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vqabsq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vmvnq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavxq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavxq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmladavq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminvq_p_s32 (int32_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminvq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxvq_p_s32 (int32_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxvq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_s32 (int32x4_t __inactive, int32_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclzq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vclsq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvaq_p_s32 (int32_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddvaq_p_sv4si (__a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_s32 (int32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrdmlsdhxq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrdmlsdhq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return __builtin_mve_vqrdmlashq_n_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return __builtin_mve_vqrdmlahq_n_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrdmladhxq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqrdmladhq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqdmlsdhxq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqdmlsdhq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return __builtin_mve_vqdmlahq_n_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqdmladhxq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b) +{ + return __builtin_mve_vqdmladhq_sv4si (__inactive, __a, __b); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_s32 (int32_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vmlsdavaxq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_s32 (int32_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vmlsdavaq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return __builtin_mve_vmlasq_n_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) +{ + return __builtin_mve_vmlaq_n_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_s32 (int32_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vmladavaxq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_s32 (int32_t __a, int32x4_t __b, int32x4_t __c) +{ + return __builtin_mve_vmladavaq_sv4si (__a, __b, __c); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) +{ + return __builtin_mve_vsriq_n_sv4si (__a, __b, __imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) +{ + return __builtin_mve_vsliq_n_sv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_u64 (uint64x2_t __a, uint64x2_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_uv2di (__a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_s64 (int64x2_t __a, int64x2_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_sv2di (__a, __b, __p); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -6939,61 +8995,326 @@ extern void *__ARM_undef; #define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) +#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) +#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) +#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) +#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vclsq_m(p0,p1,p2) __arm_vclsq_m(p0,p1,p2) +#define __arm_vclsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vclzq_m(p0,p1,p2) __arm_vclzq_m(p0,p1,p2) +#define __arm_vclzq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclzq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclzq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclzq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vclzq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vclzq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vclzq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmaxaq_m(p0,p1,p2) __arm_vmaxaq_m(p0,p1,p2) +#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vminaq_m(p0,p1,p2) __arm_vminaq_m(p0,p1,p2) +#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlaq(p0,p1,p2) __arm_vmlaq(p0,p1,p2) +#define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vsriq(p0,p1,p2) __arm_vsriq(p0,p1,p2) +#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vsliq(p0,p1,p2) __arm_vsliq(p0,p1,p2) +#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) +#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vrshlq_m_n(p0,p1,p2) __arm_vrshlq_m_n(p0,p1,p2) +#define __arm_vrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __p1, p2));}) + +#define vqshlq_m_r(p0,p1,p2) __arm_vqshlq_m_r(p0,p1,p2) +#define __arm_vqshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrshlq_m_n(p0,p1,p2) __arm_vqrshlq_m_n(p0,p1,p2) +#define __arm_vqrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrdmlsdhxq(p0,p1,p2) __arm_vqrdmlsdhxq(p0,p1,p2) +#define __arm_vqrdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrdmlsdhq(p0,p1,p2) __arm_vqrdmlsdhq(p0,p1,p2) +#define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrdmlashq(p0,p1,p2) __arm_vqrdmlashq(p0,p1,p2) +#define __arm_vqrdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlashq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlashq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlashq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqrdmlahq(p0,p1,p2) __arm_vqrdmlahq(p0,p1,p2) +#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vmlasq(p0,p1,p2) __arm_vmlasq(p0,p1,p2) +#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqdmlahq(p0,p1,p2) __arm_vqdmlahq(p0,p1,p2) +#define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqrdmladhxq(p0,p1,p2) __arm_vqrdmladhxq(p0,p1,p2) +#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrdmladhq(p0,p1,p2) __arm_vqrdmladhq(p0,p1,p2) +#define __arm_vqrdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqnegq_m(p0,p1,p2) __arm_vqnegq_m(p0,p1,p2) +#define __arm_vqnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) -#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmlsdhxq(p0,p1,p2) __arm_vqdmlsdhxq(p0,p1,p2) +#define __arm_vqdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) -#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) +#define vqdmlsdhq(p0,p1,p2) __arm_vqdmlsdhq(p0,p1,p2) +#define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) -#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmladhxq(p0,p1,p2) __arm_vqdmladhxq(p0,p1,p2) +#define __arm_vqdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmladhq(p0,p1,p2) __arm_vqdmladhq(p0,p1,p2) +#define __arm_vqdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) +#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) +#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) -#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) +#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) +#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) #define vcvtaq_m(p0,p1,p2) __arm_vcvtaq_m(p0,p1,p2) #define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ @@ -7951,6 +10272,40 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) +#define vcmpneq_m(p0,p1,p2) __arm_vcmpneq_m(p0,p1,p2) +#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) +#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + #define vaddlvaq(p0,p1) __arm_vaddlvaq(p0,p1) #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -8062,6 +10417,527 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) +#define vqrdmlsdhq(p0,p1,p2) __arm_vqrdmlsdhq(p0,p1,p2) +#define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrdmlsdhxq(p0,p1,p2) __arm_vqrdmlsdhxq(p0,p1,p2) +#define __arm_vqrdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrshlq_m_n(p0,p1,p2) __arm_vqrshlq_m_n(p0,p1,p2) +#define __arm_vqrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqshlq_m_r(p0,p1,p2) __arm_vqshlq_m_r(p0,p1,p2) +#define __arm_vqshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vrev64q_m(p0,p1,p2) __arm_vrev64q_m(p0,p1,p2) +#define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev64q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev64q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrev64q_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev64q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev64q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrev64q_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrshlq_m_n(p0,p1,p2) __arm_vrshlq_m_n(p0,p1,p2) +#define __arm_vrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __p1, p2));}) + +#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) +#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vsliq(p0,p1,p2) __arm_vsliq(p0,p1,p2) +#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vsriq(p0,p1,p2) __arm_vsriq(p0,p1,p2) +#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrdmlashq(p0,p1,p2) __arm_vqrdmlashq(p0,p1,p2) +#define __arm_vqrdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlashq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlashq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlashq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqrdmlahq(p0,p1,p2) __arm_vqrdmlahq(p0,p1,p2) +#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqrdmladhxq(p0,p1,p2) __arm_vqrdmladhxq(p0,p1,p2) +#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqrdmladhq(p0,p1,p2) __arm_vqrdmladhq(p0,p1,p2) +#define __arm_vqrdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqnegq_m(p0,p1,p2) __arm_vqnegq_m(p0,p1,p2) +#define __arm_vqnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqdmlsdhxq(p0,p1,p2) __arm_vqdmlsdhxq(p0,p1,p2) +#define __arm_vqdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vabsq_m(p0,p1,p2) __arm_vabsq_m(p0,p1,p2) +#define __arm_vabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vclsq_m(p0,p1,p2) __arm_vclsq_m(p0,p1,p2) +#define __arm_vclsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vclzq_m(p0,p1,p2) __arm_vclzq_m(p0,p1,p2) +#define __arm_vclzq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclzq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclzq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclzq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vclzq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vclzq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vclzq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vcmpgeq_m(p0,p1,p2) __arm_vcmpgeq_m(p0,p1,p2) +#define __arm_vcmpgeq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vcmpgeq_m_n(p0,p1,p2) __arm_vcmpgeq_m_n(p0,p1,p2) +#define __arm_vcmpgeq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define vdupq_m(p0,p1,p2) __arm_vdupq_m(p0,p1,p2) +#define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vdupq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vdupq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vdupq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + +#define vmaxaq_m(p0,p1,p2) __arm_vmaxaq_m(p0,p1,p2) +#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlaq(p0,p1,p2) __arm_vmlaq(p0,p1,p2) +#define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vmlasq(p0,p1,p2) __arm_vmlasq(p0,p1,p2) +#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) +#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vnegq_m(p0,p1,p2) __arm_vnegq_m(p0,p1,p2) +#define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vpselq(p0,p1,p2) __arm_vpselq(p0,p1,p2) +#define __arm_vpselq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vpselq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vpselq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vpselq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int64x2_t]: __arm_vpselq_s64 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vpselq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vpselq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vpselq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint64x2_t]: __arm_vpselq_u64 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) + +#define vqdmlahq(p0,p1,p2) __arm_vqdmlahq(p0,p1,p2) +#define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + +#define vqdmlsdhq(p0,p1,p2) __arm_vqdmlsdhq(p0,p1,p2) +#define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmladhxq(p0,p1,p2) __arm_vqdmladhxq(p0,p1,p2) +#define __arm_vqdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmladhq(p0,p1,p2) __arm_vqdmladhq(p0,p1,p2) +#define __arm_vqdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) +#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vminaq_m(p0,p1,p2) __arm_vminaq_m(p0,p1,p2) +#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vrmlaldavhaq(p0,p1,p2) __arm_vrmlaldavhaq(p0,p1,p2) +#define __arm_vrmlaldavhaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vmlsdavxq_p(p0,p1,p2) __arm_vmlsdavxq_p(p0,p1,p2) +#define __arm_vmlsdavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavxq_p_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavxq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavxq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlsdavq_p(p0,p1,p2) __arm_vmlsdavq_p(p0,p1,p2) +#define __arm_vmlsdavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavq_p_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlsdavaxq(p0,p1,p2) __arm_vmlsdavaxq(p0,p1,p2) +#define __arm_vmlsdavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaxq_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaxq_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaxq_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vmlsdavaq(p0,p1,p2) __arm_vmlsdavaq(p0,p1,p2) +#define __arm_vmlsdavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaq_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaq_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaq_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vaddvaq_p(p0,p1,p2) __arm_vaddvaq_p(p0,p1,p2) +#define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vcmpcsq_m_n(p0,p1,p2) __arm_vcmpcsq_m_n(p0,p1,p2) +#define __arm_vcmpcsq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + +#define vcmpcsq_m(p0,p1,p2) __arm_vcmpcsq_m(p0,p1,p2) +#define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmladavxq_p(p0,p1,p2) __arm_vmladavxq_p(p0,p1,p2) +#define __arm_vmladavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavxq_p_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavxq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavxq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmladavq_p(p0,p1,p2) __arm_vmladavq_p(p0,p1,p2) +#define __arm_vmladavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavq_p_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavq_p_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavq_p_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavq_p_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmladavaxq(p0,p1,p2) __arm_vmladavaxq(p0,p1,p2) +#define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vmladavaq(p0,p1,p2) __arm_vmladavaq(p0,p1,p2) +#define __arm_vmladavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vminvq_p(p0,p1,p2) __arm_vminvq_p(p0,p1,p2) +#define __arm_vminvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t][__ARM_mve_type_int8x16_t]: __arm_vminvq_p_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t][__ARM_mve_type_int16x8_t]: __arm_vminvq_p_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vminvq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_uint8x16_t]: __arm_vminvq_p_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_uint16x8_t]: __arm_vminvq_p_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vminvq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vminavq_p(p0,p1,p2) __arm_vminavq_p(p0,p1,p2) +#define __arm_vminavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_int8x16_t]: __arm_vminavq_p_s8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_int16x8_t]: __arm_vminavq_p_s16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_int32x4_t]: __arm_vminavq_p_s32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmaxvq_p(p0,p1,p2) __arm_vmaxvq_p(p0,p1,p2) +#define __arm_vmaxvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t][__ARM_mve_type_int8x16_t]: __arm_vmaxvq_p_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t][__ARM_mve_type_int16x8_t]: __arm_vmaxvq_p_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t]: __arm_vmaxvq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxvq_p_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxvq_p_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxvq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmaxavq_p(p0,p1,p2) __arm_vmaxavq_p(p0,p1,p2) +#define __arm_vmaxavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8_t][__ARM_mve_type_int8x16_t]: __arm_vmaxavq_p_s8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t][__ARM_mve_type_int16x8_t]: __arm_vmaxavq_p_s16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_int32x4_t]: __arm_vmaxavq_p_s32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vcmpltq_m(p0,p1,p2) __arm_vcmpltq_m(p0,p1,p2) +#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define vcmpleq_m(p0,p1,p2) __arm_vcmpleq_m(p0,p1,p2) +#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define vcmphiq_m(p0,p1,p2) __arm_vcmphiq_m(p0,p1,p2) +#define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vcmpgtq_m(p0,p1,p2) __arm_vcmpgtq_m(p0,p1,p2) +#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 3ac9630..25badfb 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -309,3 +309,88 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtaq_m_u, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtaq_m_s, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) +VAR4 (TERNOP_UNONE_UNONE_UNONE_UNONE, vpselq_u, v16qi, v8hi, v4si, v2di) +VAR4 (TERNOP_NONE_NONE_NONE_UNONE, vpselq_s, v16qi, v8hi, v4si, v2di) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev64q_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqrdmlashq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqrdmlahq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqdmlahq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmvnq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlasq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsliq_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vshlq_m_r_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vrshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqshlq_m_r_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqrshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqshlq_m_r_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqrshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqnegq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqabsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmvnq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavxq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavxq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vminvq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmaxvq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclzq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vaddvaq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlashq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlahq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmladhxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmladhq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqdmlsdhxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqdmlsdhq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqdmlahq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqdmladhxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqdmladhq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlsdavaxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlsdavaq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlasq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlaq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index cdf75ab..2641669 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -69,6 +69,16 @@ (and (match_code "const_int") (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8"))) +(define_constraint "Rc" + "@internal In Thumb-2 state a constant in range 0 to 15" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 15"))) + +(define_constraint "Re" + "@internal In Thumb-2 state a constant in range 0 to 31" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 31"))) + (define_constraint "Rf" "@internal In Thumb-2 state a constant in range 1 to 32" (and (match_code "const_int") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3cdb2e7..b9985a0 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -89,7 +89,28 @@ VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U - VRMLALDAVHAQ_U]) + VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U + VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U + VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S + VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S + VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S + VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S + VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S + VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U + VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S + VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U + VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U + VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U + VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U + VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S + VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S + VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S + VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S + VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S + VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S + VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U + VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S + VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -155,7 +176,24 @@ (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u") (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s") - (VSHLCQ_U "u")]) + (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u") + (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s") + (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u") + (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s") + (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u") + (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s") + (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u") + (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s") + (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u") + (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s") + (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u") + (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u") + (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u") + (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u") + (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s") + (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u") + (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s") + (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -164,6 +202,9 @@ (V4SI "mve_imm_32")]) (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) (define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")]) +(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")]) +(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15") + (V4SI "mve_imm_31")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -257,6 +298,31 @@ (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U]) (define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U]) (define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U]) +(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U]) +(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U]) +(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U]) +(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U]) +(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U]) +(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U]) +(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U]) +(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U]) +(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U]) +(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U]) +(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U]) +(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U]) +(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U]) +(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U]) +(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U]) +(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U]) +(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U]) +(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U]) +(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U]) +(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U]) +(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U]) +(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U]) +(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U]) +(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U]) +(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -3209,7 +3275,7 @@ { rtx ignore_wb = gen_reg_rtx (SImode); emit_insn(gen_mve_vshlcq_(operands[0], ignore_wb, operands[1], - operands[2], operands[3])); + operands[2], operands[3])); DONE; }) @@ -3240,3 +3306,963 @@ VSHLCQ))] "TARGET_HAVE_MVE" "vshlc %q0, %1, %4") + +;; +;; [vabsq_m_s]) +;; +(define_insn "mve_vabsq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VABSQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vabst.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddvaq_p_u, vaddvaq_p_s]) +;; +(define_insn "mve_vaddvaq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VADDVAQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddvat.%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vclsq_m_s]) +;; +(define_insn "mve_vclsq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCLSQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vclst.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vclzq_m_s, vclzq_m_u]) +;; +(define_insn "mve_vclzq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCLZQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vclzt.i%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpcsq_m_n_u]) +;; +(define_insn "mve_vcmpcsq_m_n_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPCSQ_M_N_U)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.u%# cs, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpcsq_m_u]) +;; +(define_insn "mve_vcmpcsq_m_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPCSQ_M_U)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.u%# cs, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s]) +;; +(define_insn "mve_vcmpeqq_m_n_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPEQQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.i%# eq, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpeqq_m_u, vcmpeqq_m_s]) +;; +(define_insn "mve_vcmpeqq_m_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPEQQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.i%# eq, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgeq_m_n_s]) +;; +(define_insn "mve_vcmpgeq_m_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGEQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# ge, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgeq_m_s]) +;; +(define_insn "mve_vcmpgeq_m_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGEQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# ge, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgtq_m_n_s]) +;; +(define_insn "mve_vcmpgtq_m_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGTQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# gt, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgtq_m_s]) +;; +(define_insn "mve_vcmpgtq_m_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGTQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# gt, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmphiq_m_n_u]) +;; +(define_insn "mve_vcmphiq_m_n_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPHIQ_M_N_U)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.u%# hi, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmphiq_m_u]) +;; +(define_insn "mve_vcmphiq_m_u" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPHIQ_M_U)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.u%# hi, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpleq_m_n_s]) +;; +(define_insn "mve_vcmpleq_m_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLEQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# le, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpleq_m_s]) +;; +(define_insn "mve_vcmpleq_m_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLEQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# le, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpltq_m_n_s]) +;; +(define_insn "mve_vcmpltq_m_n_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLTQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# lt, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpltq_m_s]) +;; +(define_insn "mve_vcmpltq_m_s" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLTQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.s%# lt, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpneq_m_n_u, vcmpneq_m_n_s]) +;; +(define_insn "mve_vcmpneq_m_n_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPNEQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.i%# ne, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpneq_m_s, vcmpneq_m_u]) +;; +(define_insn "mve_vcmpneq_m_" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPNEQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcmpt.i%# ne, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vdupq_m_n_s, vdupq_m_n_u]) +;; +(define_insn "mve_vdupq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VDUPQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vdupt.%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxaq_m_s]) +;; +(define_insn "mve_vmaxaq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXAQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmaxat.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxavq_p_s]) +;; +(define_insn "mve_vmaxavq_p_s" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXAVQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmaxavt.s%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxvq_p_u, vmaxvq_p_s]) +;; +(define_insn "mve_vmaxvq_p_" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmaxvt.%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminaq_m_s]) +;; +(define_insn "mve_vminaq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINAQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vminat.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminavq_p_s]) +;; +(define_insn "mve_vminavq_p_s" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINAVQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vminavt.s%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminvq_p_s, vminvq_p_u]) +;; +(define_insn "mve_vminvq_p_" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vminvt.%#\t%0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmladavaq_u, vmladavaq_s]) +;; +(define_insn "mve_vmladavaq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VMLADAVAQ)) + ] + "TARGET_HAVE_MVE" + "vmladava.%# %0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmladavq_p_u, vmladavq_p_s]) +;; +(define_insn "mve_vmladavq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLADAVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmladavt.%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmladavxq_p_s]) +;; +(define_insn "mve_vmladavxq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLADAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmladavxt.s%#\t%0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlaq_n_u, vmlaq_n_s]) +;; +(define_insn "mve_vmlaq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VMLAQ_N)) + ] + "TARGET_HAVE_MVE" + "vmla.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlasq_n_u, vmlasq_n_s]) +;; +(define_insn "mve_vmlasq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VMLASQ_N)) + ] + "TARGET_HAVE_MVE" + "vmlas.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsdavq_p_s]) +;; +(define_insn "mve_vmlsdavq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLSDAVQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsdavt.s%# %0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsdavxq_p_s]) +;; +(define_insn "mve_vmlsdavxq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLSDAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsdavxt.s%# %0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmvnq_m_s, vmvnq_m_u]) +;; +(define_insn "mve_vmvnq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMVNQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmvnt %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vnegq_m_s]) +;; +(define_insn "mve_vnegq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VNEGQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vnegt.s%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vpselq_u, vpselq_s]) +;; +(define_insn "mve_vpselq_" + [ + (set (match_operand:MVE_1 0 "s_register_operand" "=w") + (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") + (match_operand:MVE_1 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VPSELQ)) + ] + "TARGET_HAVE_MVE" + "vpsel %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqabsq_m_s]) +;; +(define_insn "mve_vqabsq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQABSQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqabst.s%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmlahq_n_s, vqdmlahq_n_u]) +;; +(define_insn "mve_vqdmlahq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VQDMLAHQ_N)) + ] + "TARGET_HAVE_MVE" + "vqdmlah.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqnegq_m_s]) +;; +(define_insn "mve_vqnegq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQNEGQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqnegt.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmladhq_s]) +;; +(define_insn "mve_vqrdmladhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQRDMLADHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmladh.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmladhxq_s]) +;; +(define_insn "mve_vqrdmladhxq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQRDMLADHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmladhx.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmlahq_n_s, vqrdmlahq_n_u]) +;; +(define_insn "mve_vqrdmlahq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VQRDMLAHQ_N)) + ] + "TARGET_HAVE_MVE" + "vqrdmlah.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmlashq_n_s, vqrdmlashq_n_u]) +;; +(define_insn "mve_vqrdmlashq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VQRDMLASHQ_N)) + ] + "TARGET_HAVE_MVE" + "vqrdmlash.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmlsdhq_s]) +;; +(define_insn "mve_vqrdmlsdhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQRDMLSDHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmlsdh.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrdmlsdhxq_s]) +;; +(define_insn "mve_vqrdmlsdhxq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQRDMLSDHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vqrdmlsdhx.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrshlq_m_n_s, vqrshlq_m_n_u]) +;; +(define_insn "mve_vqrshlq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQRSHLQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshlt.%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshlq_m_r_u, vqshlq_m_r_s]) +;; +(define_insn "mve_vqshlq_m_r_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQSHLQ_M_R)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshlt.%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrev64q_m_u, vrev64q_m_s]) +;; +(define_insn "mve_vrev64q_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VREV64Q_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrev64t.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshlq_m_n_s, vrshlq_m_n_u]) +;; +(define_insn "mve_vrshlq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRSHLQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrshlt.%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshlq_m_r_u, vshlq_m_r_s]) +;; +(define_insn "mve_vshlq_m_r_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSHLQ_M_R)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlt.%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vsliq_n_u, vsliq_n_s]) +;; +(define_insn "mve_vsliq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "" "")] + VSLIQ_N)) + ] + "TARGET_HAVE_MVE" + "vsli.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vsriq_n_u, vsriq_n_s]) +;; +(define_insn "mve_vsriq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] + VSRIQ_N)) + ] + "TARGET_HAVE_MVE" + "vsri.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmlsdhxq_s]) +;; +(define_insn "mve_vqdmlsdhxq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQDMLSDHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmlsdhx.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmlsdhq_s]) +;; +(define_insn "mve_vqdmlsdhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQDMLSDHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmlsdh.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmladhxq_s]) +;; +(define_insn "mve_vqdmladhxq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQDMLADHXQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmladhx.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqdmladhq_s]) +;; +(define_insn "mve_vqdmladhq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VQDMLADHQ_S)) + ] + "TARGET_HAVE_MVE" + "vqdmladh.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsdavaxq_s]) +;; +(define_insn "mve_vmlsdavaxq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VMLSDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsdavax.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsdavaq_s]) +;; +(define_insn "mve_vmlsdavaq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VMLSDAVAQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsdava.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmladavaxq_s]) +;; +(define_insn "mve_vmladavaxq_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w")] + VMLADAVAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmladavax.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 9c9a84b..2b65e64 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -43,6 +43,14 @@ (define_predicate "mve_imm_8" (match_test "satisfies_constraint_Rb (op)")) +;; True for immediates in the range of 0 to 15 for MVE. +(define_predicate "mve_imm_15" + (match_test "satisfies_constraint_Rc (op)")) + +;; True for immediates in the range of 0 to 31 for MVE. +(define_predicate "mve_imm_31" + (match_test "satisfies_constraint_Re (op)")) + ;; True for immediates in the range of 1 to 32 for MVE. (define_predicate "mve_imm_32" (match_test "satisfies_constraint_Rf (op)")) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a91d737..6cae249 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,265 @@ +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise. + 2020-03-18 David Malcolm PR analyzer/94047 diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c new file mode 100644 index 0000000..4c07ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vabsq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c new file mode 100644 index 0000000..0566786 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vabsq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c new file mode 100644 index 0000000..f16bf7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vabsq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c new file mode 100644 index 0000000..6799c80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddvaq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c new file mode 100644 index 0000000..fde29428 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddvaq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c new file mode 100644 index 0000000..53a6fe0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddvaq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c new file mode 100644 index 0000000..9dc39da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddvaq_p_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c new file mode 100644 index 0000000..445accb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddvaq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c new file mode 100644 index 0000000..774ee9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddvaq_p_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddvat.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c new file mode 100644 index 0000000..8277577 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vclsq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vclsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c new file mode 100644 index 0000000..88b94db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vclsq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vclsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c new file mode 100644 index 0000000..2fbc10c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vclsq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vclsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c new file mode 100644 index 0000000..6f1acc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vclzq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c new file mode 100644 index 0000000..d5f6f19 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vclzq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c new file mode 100644 index 0000000..db7df73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vclzq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c new file mode 100644 index 0000000..a59409a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vclzq_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c new file mode 100644 index 0000000..0290642 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vclzq_m_u32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c new file mode 100644 index 0000000..ee29433 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vclzq_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vclzq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c new file mode 100644 index 0000000..8682715 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c new file mode 100644 index 0000000..9909279 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c new file mode 100644 index 0000000..0350934 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpcsq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c new file mode 100644 index 0000000..85accf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpcsq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpcsq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c new file mode 100644 index 0000000..9018c71 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpcsq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpcsq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c new file mode 100644 index 0000000..9f73e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpcsq_m_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpcsq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c new file mode 100644 index 0000000..751b95e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c new file mode 100644 index 0000000..b26993b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c new file mode 100644 index 0000000..105002b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c new file mode 100644 index 0000000..97d5cfb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c new file mode 100644 index 0000000..aa99be6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c new file mode 100644 index 0000000..f61acc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c new file mode 100644 index 0000000..c027744 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c new file mode 100644 index 0000000..0eab804 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c new file mode 100644 index 0000000..6830040 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpeqq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c new file mode 100644 index 0000000..3484f3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c new file mode 100644 index 0000000..efec6cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c new file mode 100644 index 0000000..34942fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpeqq_m_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c new file mode 100644 index 0000000..f755e77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c new file mode 100644 index 0000000..a12de37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c new file mode 100644 index 0000000..dacc7bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c new file mode 100644 index 0000000..9763eea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpgeq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c new file mode 100644 index 0000000..0fd2c61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpgeq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c new file mode 100644 index 0000000..589d9c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpgeq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c new file mode 100644 index 0000000..49462ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c new file mode 100644 index 0000000..d601100 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c new file mode 100644 index 0000000..0bf9c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c new file mode 100644 index 0000000..4f10cf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpgtq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c new file mode 100644 index 0000000..600dbc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpgtq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c new file mode 100644 index 0000000..8ff848d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpgtq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c new file mode 100644 index 0000000..428d3e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmphiq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c new file mode 100644 index 0000000..c5d5b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmphiq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c new file mode 100644 index 0000000..34dba3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmphiq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c new file mode 100644 index 0000000..8bf9bfe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmphiq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c new file mode 100644 index 0000000..3d1a35a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmphiq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c new file mode 100644 index 0000000..0c66a82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmphiq_m_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.u8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmphiq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c new file mode 100644 index 0000000..e5e48fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpleq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c new file mode 100644 index 0000000..b18a1e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpleq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c new file mode 100644 index 0000000..a846f43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpleq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c new file mode 100644 index 0000000..2f2a8d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpleq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c new file mode 100644 index 0000000..67eb5b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpleq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c new file mode 100644 index 0000000..c0e3c3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpleq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c new file mode 100644 index 0000000..f90a4ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpltq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c new file mode 100644 index 0000000..e199f65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpltq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c new file mode 100644 index 0000000..8333830 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpltq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c new file mode 100644 index 0000000..ea2696f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpltq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c new file mode 100644 index 0000000..a682259 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpltq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c new file mode 100644 index 0000000..3d4ab77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpltq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.s8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c index 0e51876..50cacad 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c @@ -16,7 +16,7 @@ foo (float16x8_t a, float16_t b) mve_pred16_t foo1 (float16x8_t a, float16_t b) { - return vcmpltq_n (a, b); + return vcmpltq (a, b); } /* { dg-final { scan-assembler "vcmp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c index 5f7cf8a..dc65787 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c @@ -16,7 +16,7 @@ foo (float32x4_t a, float32_t b) mve_pred16_t foo1 (float32x4_t a, float32_t b) { - return vcmpltq_n (a, b); + return vcmpltq (a, b); } /* { dg-final { scan-assembler "vcmp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c new file mode 100644 index 0000000..832fec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c new file mode 100644 index 0000000..c351cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c new file mode 100644 index 0000000..40e38e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c new file mode 100644 index 0000000..a287f33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c new file mode 100644 index 0000000..cb81ec4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c new file mode 100644 index 0000000..21ed443 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c new file mode 100644 index 0000000..e98c854 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c new file mode 100644 index 0000000..240dd63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c new file mode 100644 index 0000000..a941bac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpneq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c new file mode 100644 index 0000000..1f4bdb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i16" } } */ + +mve_pred16_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c new file mode 100644 index 0000000..eaeb6a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i32" } } */ + +mve_pred16_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c new file mode 100644 index 0000000..4a31aa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpneq_m_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.i8" } } */ + +mve_pred16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c new file mode 100644 index 0000000..d24d636 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16_t a, mve_pred16_t p) +{ + return vdupq_m_n_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c new file mode 100644 index 0000000..d685fcf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32_t a, mve_pred16_t p) +{ + return vdupq_m_n_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c new file mode 100644 index 0000000..28fb048 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8_t a, mve_pred16_t p) +{ + return vdupq_m_n_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c new file mode 100644 index 0000000..e0c101a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p) +{ + return vdupq_m_n_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c new file mode 100644 index 0000000..b1f0ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vdupq_m_n_u32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c new file mode 100644 index 0000000..be23f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p) +{ + return vdupq_m_n_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c new file mode 100644 index 0000000..6f967e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxaq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxat.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c new file mode 100644 index 0000000..ef2daa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxaq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxat.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c new file mode 100644 index 0000000..a6ef4f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxaq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxat.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c new file mode 100644 index 0000000..d4996c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s16" } } */ + +uint16_t +foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c new file mode 100644 index 0000000..3d45852 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c new file mode 100644 index 0000000..cc65137 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxavq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s8" } } */ + +uint8_t +foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c new file mode 100644 index 0000000..4c1e2ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16_t +foo (int16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxvq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s16" } } */ + +int16_t +foo1 (int16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c new file mode 100644 index 0000000..2ed9fcfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxvq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c new file mode 100644 index 0000000..25c1ef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8_t +foo (int8_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxvq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s8" } } */ + +int8_t +foo1 (int8_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c new file mode 100644 index 0000000..3539036 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxvq_p_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u16" } } */ + +uint16_t +foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c new file mode 100644 index 0000000..464c05a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxvq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c new file mode 100644 index 0000000..26c6d24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxvq_p_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u8" } } */ + +uint8_t +foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxvt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c new file mode 100644 index 0000000..8342abc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminaq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminat.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c new file mode 100644 index 0000000..5527d17 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminaq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminat.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c new file mode 100644 index 0000000..48d1022 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminaq_m_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminat.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c new file mode 100644 index 0000000..e754069 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, int16x8_t b, mve_pred16_t p) +{ + return vminavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s16" } } */ + +uint16_t +foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) +{ + return vminavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c new file mode 100644 index 0000000..758547b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b, mve_pred16_t p) +{ + return vminavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) +{ + return vminavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c new file mode 100644 index 0000000..d59b8e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, int8x16_t b, mve_pred16_t p) +{ + return vminavq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s8" } } */ + +uint8_t +foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) +{ + return vminavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c new file mode 100644 index 0000000..872fc98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16_t +foo (int16_t a, int16x8_t b, mve_pred16_t p) +{ + return vminvq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s16" } } */ + +int16_t +foo1 (int16_t a, int16x8_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c new file mode 100644 index 0000000..47c6a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vminvq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c new file mode 100644 index 0000000..a2e3307 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8_t +foo (int8_t a, int8x16_t b, mve_pred16_t p) +{ + return vminvq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s8" } } */ + +int8_t +foo1 (int8_t a, int8x16_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c new file mode 100644 index 0000000..0100340 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16_t +foo (uint16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminvq_p_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u16" } } */ + +uint16_t +foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c new file mode 100644 index 0000000..964455f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminvq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c new file mode 100644 index 0000000..dfae14d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8_t +foo (uint8_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminvq_p_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u8" } } */ + +uint8_t +foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminvt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c new file mode 100644 index 0000000..6d7bbce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmladavaq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c new file mode 100644 index 0000000..5c0b9e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmladavaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c new file mode 100644 index 0000000..5620ba4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmladavaq_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c new file mode 100644 index 0000000..34e0129 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, uint16x8_t c) +{ + return vmladavaq_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, uint16x8_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c new file mode 100644 index 0000000..5518565 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, uint32x4_t c) +{ + return vmladavaq_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, uint32x4_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c new file mode 100644 index 0000000..1d5af5e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, uint8x16_t c) +{ + return vmladavaq_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, uint8x16_t c) +{ + return vmladavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladava.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c new file mode 100644 index 0000000..e74b07e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmladavaxq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmladavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c new file mode 100644 index 0000000..5bf679d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmladavaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmladavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c new file mode 100644 index 0000000..67dd10b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmladavaxq_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmladavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmladavax.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c new file mode 100644 index 0000000..20638fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmladavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c new file mode 100644 index 0000000..be64018 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmladavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c new file mode 100644 index 0000000..20cbcdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmladavq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c new file mode 100644 index 0000000..9573d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmladavq_p_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u16" } } */ + +uint32_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c new file mode 100644 index 0000000..52d5adb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmladavq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u32" } } */ + +uint32_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c new file mode 100644 index 0000000..d51d02b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmladavq_p_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u8" } } */ + +uint32_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmladavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c new file mode 100644 index 0000000..2a86612 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmladavxq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmladavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c new file mode 100644 index 0000000..7f28113 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmladavxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmladavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c new file mode 100644 index 0000000..2765be8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmladavxq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmladavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmladavxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c new file mode 100644 index 0000000..e14adfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c) +{ + return vmlaq_n_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c new file mode 100644 index 0000000..e68fecb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c) +{ + return vmlaq_n_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c new file mode 100644 index 0000000..ca4446c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c) +{ + return vmlaq_n_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c new file mode 100644 index 0000000..81219f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vmlaq_n_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c new file mode 100644 index 0000000..871c7fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vmlaq_n_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c new file mode 100644 index 0000000..bb0412f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vmlaq_n_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmla.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c new file mode 100644 index 0000000..abe9e1d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c) +{ + return vmlasq_n_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c new file mode 100644 index 0000000..d18178c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c) +{ + return vmlasq_n_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c new file mode 100644 index 0000000..a67f624 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c) +{ + return vmlasq_n_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c new file mode 100644 index 0000000..d86a35d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vmlasq_n_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c new file mode 100644 index 0000000..bd9280d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vmlasq_n_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c new file mode 100644 index 0000000..22d6344 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vmlasq_n_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vmlasq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlas.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c new file mode 100644 index 0000000..2e1ba82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmlsdavaq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmlsdavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c new file mode 100644 index 0000000..0a4a4cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmlsdavaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmlsdavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c new file mode 100644 index 0000000..3151a59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmlsdavaq_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmlsdavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdava.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c new file mode 100644 index 0000000..fcd0f39 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmlsdavaxq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c) +{ + return vmlsdavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c new file mode 100644 index 0000000..36b5c54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmlsdavaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c) +{ + return vmlsdavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c new file mode 100644 index 0000000..7170a57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmlsdavaxq_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c) +{ + return vmlsdavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c new file mode 100644 index 0000000..41cc553 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsdavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsdavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c new file mode 100644 index 0000000..b74d602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsdavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsdavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c new file mode 100644 index 0000000..5457e2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmlsdavq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmlsdavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c new file mode 100644 index 0000000..cb900bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsdavxq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ + +int32_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsdavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c new file mode 100644 index 0000000..682d62a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsdavxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ + +int32_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsdavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c new file mode 100644 index 0000000..96b81d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmlsdavxq_p_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ + +int32_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmlsdavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c new file mode 100644 index 0000000..24317ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmvnq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c new file mode 100644 index 0000000..ac6caa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vmvnq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c new file mode 100644 index 0000000..95be493 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmvnq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c new file mode 100644 index 0000000..6d85ba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmvnq_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c new file mode 100644 index 0000000..e08d1fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vmvnq_m_u32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c new file mode 100644 index 0000000..73edc54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmvnq_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmvnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c new file mode 100644 index 0000000..3226161 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vnegq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c new file mode 100644 index 0000000..1c54ff7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vnegq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c new file mode 100644 index 0000000..2e828b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vnegq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c new file mode 100644 index 0000000..379972a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vpselq_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c new file mode 100644 index 0000000..8b79e31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vpselq_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c new file mode 100644 index 0000000..daf67f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t a, int64x2_t b, mve_pred16_t p) +{ + return vpselq_s64 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +int64x2_t +foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c new file mode 100644 index 0000000..def4758 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vpselq_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c new file mode 100644 index 0000000..c559afd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vpselq_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c new file mode 100644 index 0000000..ac7c11a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vpselq_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c new file mode 100644 index 0000000..09303ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p) +{ + return vpselq_u64 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +uint64x2_t +foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c new file mode 100644 index 0000000..a592d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vpselq_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c new file mode 100644 index 0000000..2047818 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqabsq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqabst.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c new file mode 100644 index 0000000..95af462 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqabsq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqabst.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c new file mode 100644 index 0000000..cde5328 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqabsq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqabst.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c new file mode 100644 index 0000000..fa5bcc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmladhq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c new file mode 100644 index 0000000..ba37ad5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmladhq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c new file mode 100644 index 0000000..32d2eb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmladhq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c new file mode 100644 index 0000000..ff95d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmladhxq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c new file mode 100644 index 0000000..d8f08ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmladhxq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c new file mode 100644 index 0000000..6ffbfb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmladhxq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmladhx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c new file mode 100644 index 0000000..7b90c71 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqdmlahq_n_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c new file mode 100644 index 0000000..6c2e487 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqdmlahq_n_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c new file mode 100644 index 0000000..7a62762e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqdmlahq_n_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c new file mode 100644 index 0000000..926a2fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqdmlahq_n_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c new file mode 100644 index 0000000..9f59e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqdmlahq_n_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c new file mode 100644 index 0000000..9a578fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqdmlahq_n_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqdmlah.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c new file mode 100644 index 0000000..3084c6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmlsdhq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c new file mode 100644 index 0000000..243b545 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmlsdhq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c new file mode 100644 index 0000000..6b31a59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmlsdhq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c new file mode 100644 index 0000000..99efed1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmlsdhxq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c new file mode 100644 index 0000000..e654b64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmlsdhxq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c new file mode 100644 index 0000000..653732c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmlsdhxq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqdmlsdhx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c new file mode 100644 index 0000000..0faae49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqnegq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqnegt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c new file mode 100644 index 0000000..a4b9b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqnegq_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqnegt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c new file mode 100644 index 0000000..5b6b8d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqnegq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqnegt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c new file mode 100644 index 0000000..68814a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmladhq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c new file mode 100644 index 0000000..b76abef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmladhq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c new file mode 100644 index 0000000..af692a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmladhq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmladhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c new file mode 100644 index 0000000..9a26501 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmladhxq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c new file mode 100644 index 0000000..7b79fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmladhxq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c new file mode 100644 index 0000000..0e6cc19 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmladhxq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmladhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmladhx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c new file mode 100644 index 0000000..bea0038 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqrdmlahq_n_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c new file mode 100644 index 0000000..50878ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqrdmlahq_n_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c new file mode 100644 index 0000000..8d75b1a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqrdmlahq_n_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c new file mode 100644 index 0000000..aecc0f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqrdmlahq_n_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c new file mode 100644 index 0000000..bef2b3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqrdmlahq_n_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c new file mode 100644 index 0000000..69aab30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqrdmlahq_n_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqrdmlahq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c new file mode 100644 index 0000000..b02cb58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqrdmlashq_n_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c new file mode 100644 index 0000000..0b2e2aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqrdmlashq_n_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c new file mode 100644 index 0000000..fe0c7b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqrdmlashq_n_s8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c new file mode 100644 index 0000000..5390e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqrdmlashq_n_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c new file mode 100644 index 0000000..716ead2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqrdmlashq_n_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c new file mode 100644 index 0000000..5ec79f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqrdmlashq_n_u8 (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) +{ + return vqrdmlashq (a, b, c); +} + +/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c new file mode 100644 index 0000000..ca0a8d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmlsdhq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c new file mode 100644 index 0000000..9c16270 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmlsdhq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c new file mode 100644 index 0000000..2a04793 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmlsdhq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmlsdhq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdh.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c new file mode 100644 index 0000000..c7fda43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmlsdhxq_s16 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) +{ + return vqrdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c new file mode 100644 index 0000000..eaa8ae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmlsdhxq_s32 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) +{ + return vqrdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c new file mode 100644 index 0000000..faca85e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmlsdhxq_s8 (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) +{ + return vqrdmlsdhxq (inactive, a, b); +} + +/* { dg-final { scan-assembler "vqrdmlsdhx.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c new file mode 100644 index 0000000..399d214 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c new file mode 100644 index 0000000..cdf08dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c new file mode 100644 index 0000000..82c221d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c new file mode 100644 index 0000000..d366ebe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c new file mode 100644 index 0000000..058492a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c new file mode 100644 index 0000000..9cb660b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c new file mode 100644 index 0000000..677e673 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c new file mode 100644 index 0000000..6cc14a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c new file mode 100644 index 0000000..0cbb8a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c new file mode 100644 index 0000000..30d8302 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c new file mode 100644 index 0000000..02ae638 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c new file mode 100644 index 0000000..db70681 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vqshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c new file mode 100644 index 0000000..fc8a6ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrev64q_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c new file mode 100644 index 0000000..8ee35c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vrev64q_m_s32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c new file mode 100644 index 0000000..390652c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev64q_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c new file mode 100644 index 0000000..51e7859 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrev64q_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c new file mode 100644 index 0000000..7bcd7c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vrev64q_m_u32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c new file mode 100644 index 0000000..96a9d2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev64q_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c new file mode 100644 index 0000000..348a1f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c new file mode 100644 index 0000000..c15c1ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c new file mode 100644 index 0000000..ac9b90d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c new file mode 100644 index 0000000..72fc614 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c new file mode 100644 index 0000000..db3db7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c new file mode 100644 index 0000000..74ee42d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vrshlq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c new file mode 100644 index 0000000..c028232 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c new file mode 100644 index 0000000..2d48bce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c new file mode 100644 index 0000000..ba8a62a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c new file mode 100644 index 0000000..6d16399 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c new file mode 100644 index 0000000..e597dd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c new file mode 100644 index 0000000..d95a312 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vshlq_m_r (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c new file mode 100644 index 0000000..64f6c98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vsliq_n_s16 (a, b, 15); +} + +/* { dg-final { scan-assembler "vsli.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vsliq (a, b, 15); +} + +/* { dg-final { scan-assembler "vsli.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c new file mode 100644 index 0000000..25bc97b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vsliq_n_s32 (a, b, 31); +} + +/* { dg-final { scan-assembler "vsli.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vsliq (a, b, 31); +} + +/* { dg-final { scan-assembler "vsli.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c new file mode 100644 index 0000000..6516b0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vsliq_n_s8 (a, b, 7); +} + +/* { dg-final { scan-assembler "vsli.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vsliq (a, b, 7); +} + +/* { dg-final { scan-assembler "vsli.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c new file mode 100644 index 0000000..dc70a65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vsliq_n_u16 (a, b, 15); +} + +/* { dg-final { scan-assembler "vsli.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vsliq (a, b, 15); +} + +/* { dg-final { scan-assembler "vsli.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c new file mode 100644 index 0000000..cb0d191 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vsliq_n_u32 (a, b, 31); +} + +/* { dg-final { scan-assembler "vsli.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vsliq (a, b, 31); +} + +/* { dg-final { scan-assembler "vsli.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c new file mode 100644 index 0000000..765853a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vsliq_n_u8 (a, b, 7); +} + +/* { dg-final { scan-assembler "vsli.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vsliq (a, b, 7); +} + +/* { dg-final { scan-assembler "vsli.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c new file mode 100644 index 0000000..f1a8091 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vsriq_n_s16 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c new file mode 100644 index 0000000..f128834 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vsriq_n_s32 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c new file mode 100644 index 0000000..5e51bd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vsriq_n_s8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c new file mode 100644 index 0000000..5ce35ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vsriq_n_u16 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c new file mode 100644 index 0000000..861a3b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vsriq_n_u32 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c new file mode 100644 index 0000000..bca0788 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vsriq_n_u8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vsriq (a, b, 4); +} + +/* { dg-final { scan-assembler "vsri.8" } } */ -- cgit v1.1 From e3678b4464a8dd9cc9386145b4acd2d3333bc071 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 16:37:18 +0000 Subject: [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. This patch supports following MVE ACLE intrinsics with ternary operands. vrmlaldavhaxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vaddlvaq_p_s32, vcvtbq_m_f16_f32, vcvtbq_m_f32_f16, vcvttq_m_f16_f32, vcvttq_m_f32_f16, vrev16q_m_s8, vrev32q_m_f16, vrmlaldavhq_p_s32, vrmlaldavhxq_p_s32, vrmlsldavhq_p_s32, vrmlsldavhxq_p_s32, vaddlvaq_p_u32, vrev16q_m_u8, vrmlaldavhq_p_u32, vmvnq_m_n_s16, vorrq_m_n_s16, vqrshrntq_n_s16, vqshrnbq_n_s16, vqshrntq_n_s16, vrshrnbq_n_s16, vrshrntq_n_s16, vshrnbq_n_s16, vshrntq_n_s16, vcmlaq_f16, vcmlaq_rot180_f16, vcmlaq_rot270_f16, vcmlaq_rot90_f16, vfmaq_f16, vfmaq_n_f16, vfmasq_n_f16, vfmsq_f16, vmlaldavaq_s16, vmlaldavaxq_s16, vmlsldavaq_s16, vmlsldavaxq_s16, vabsq_m_f16, vcvtmq_m_s16_f16, vcvtnq_m_s16_f16, vcvtpq_m_s16_f16, vcvtq_m_s16_f16, vdupq_m_n_f16, vmaxnmaq_m_f16, vmaxnmavq_p_f16, vmaxnmvq_p_f16, vminnmaq_m_f16, vminnmavq_p_f16, vminnmvq_p_f16, vmlaldavq_p_s16, vmlaldavxq_p_s16, vmlsldavq_p_s16, vmlsldavxq_p_s16, vmovlbq_m_s8, vmovltq_m_s8, vmovnbq_m_s16, vmovntq_m_s16, vnegq_m_f16, vpselq_f16, vqmovnbq_m_s16, vqmovntq_m_s16, vrev32q_m_s8, vrev64q_m_f16, vrndaq_m_f16, vrndmq_m_f16, vrndnq_m_f16, vrndpq_m_f16, vrndq_m_f16, vrndxq_m_f16, vcmpeqq_m_n_f16, vcmpgeq_m_f16, vcmpgeq_m_n_f16, vcmpgtq_m_f16, vcmpgtq_m_n_f16, vcmpleq_m_f16, vcmpleq_m_n_f16, vcmpltq_m_f16, vcmpltq_m_n_f16, vcmpneq_m_f16, vcmpneq_m_n_f16, vmvnq_m_n_u16, vorrq_m_n_u16, vqrshruntq_n_s16, vqshrunbq_n_s16, vqshruntq_n_s16, vcvtmq_m_u16_f16, vcvtnq_m_u16_f16, vcvtpq_m_u16_f16, vcvtq_m_u16_f16, vqmovunbq_m_s16, vqmovuntq_m_s16, vqrshrntq_n_u16, vqshrnbq_n_u16, vqshrntq_n_u16, vrshrnbq_n_u16, vrshrntq_n_u16, vshrnbq_n_u16, vshrntq_n_u16, vmlaldavaq_u16, vmlaldavaxq_u16, vmlaldavq_p_u16, vmlaldavxq_p_u16, vmovlbq_m_u8, vmovltq_m_u8, vmovnbq_m_u16, vmovntq_m_u16, vqmovnbq_m_u16, vqmovntq_m_u16, vrev32q_m_u8, vmvnq_m_n_s32, vorrq_m_n_s32, vqrshrntq_n_s32, vqshrnbq_n_s32, vqshrntq_n_s32, vrshrnbq_n_s32, vrshrntq_n_s32, vshrnbq_n_s32, vshrntq_n_s32, vcmlaq_f32, vcmlaq_rot180_f32, vcmlaq_rot270_f32, vcmlaq_rot90_f32, vfmaq_f32, vfmaq_n_f32, vfmasq_n_f32, vfmsq_f32, vmlaldavaq_s32, vmlaldavaxq_s32, vmlsldavaq_s32, vmlsldavaxq_s32, vabsq_m_f32, vcvtmq_m_s32_f32, vcvtnq_m_s32_f32, vcvtpq_m_s32_f32, vcvtq_m_s32_f32, vdupq_m_n_f32, vmaxnmaq_m_f32, vmaxnmavq_p_f32, vmaxnmvq_p_f32, vminnmaq_m_f32, vminnmavq_p_f32, vminnmvq_p_f32, vmlaldavq_p_s32, vmlaldavxq_p_s32, vmlsldavq_p_s32, vmlsldavxq_p_s32, vmovlbq_m_s16, vmovltq_m_s16, vmovnbq_m_s32, vmovntq_m_s32, vnegq_m_f32, vpselq_f32, vqmovnbq_m_s32, vqmovntq_m_s32, vrev32q_m_s16, vrev64q_m_f32, vrndaq_m_f32, vrndmq_m_f32, vrndnq_m_f32, vrndpq_m_f32, vrndq_m_f32, vrndxq_m_f32, vcmpeqq_m_n_f32, vcmpgeq_m_f32, vcmpgeq_m_n_f32, vcmpgtq_m_f32, vcmpgtq_m_n_f32, vcmpleq_m_f32, vcmpleq_m_n_f32, vcmpltq_m_f32, vcmpltq_m_n_f32, vcmpneq_m_f32, vcmpneq_m_n_f32, vmvnq_m_n_u32, vorrq_m_n_u32, vqrshruntq_n_s32, vqshrunbq_n_s32, vqshruntq_n_s32, vcvtmq_m_u32_f32, vcvtnq_m_u32_f32, vcvtpq_m_u32_f32, vcvtq_m_u32_f32, vqmovunbq_m_s32, vqmovuntq_m_s32, vqrshrntq_n_u32, vqshrnbq_n_u32, vqshrntq_n_u32, vrshrnbq_n_u32, vrshrntq_n_u32, vshrnbq_n_u32, vshrntq_n_u32, vmlaldavaq_u32, vmlaldavaxq_u32, vmlaldavq_p_u32, vmlaldavxq_p_u32, vmovlbq_m_u16, vmovltq_m_u16, vmovnbq_m_u32, vmovntq_m_u32, vqmovnbq_m_u32, vqmovntq_m_u32, vrev32q_m_u16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. (vrmlsldavhaq_s32): Likewise. (vrmlsldavhaxq_s32): Likewise. (vaddlvaq_p_s32): Likewise. (vcvtbq_m_f16_f32): Likewise. (vcvtbq_m_f32_f16): Likewise. (vcvttq_m_f16_f32): Likewise. (vcvttq_m_f32_f16): Likewise. (vrev16q_m_s8): Likewise. (vrev32q_m_f16): Likewise. (vrmlaldavhq_p_s32): Likewise. (vrmlaldavhxq_p_s32): Likewise. (vrmlsldavhq_p_s32): Likewise. (vrmlsldavhxq_p_s32): Likewise. (vaddlvaq_p_u32): Likewise. (vrev16q_m_u8): Likewise. (vrmlaldavhq_p_u32): Likewise. (vmvnq_m_n_s16): Likewise. (vorrq_m_n_s16): Likewise. (vqrshrntq_n_s16): Likewise. (vqshrnbq_n_s16): Likewise. (vqshrntq_n_s16): Likewise. (vrshrnbq_n_s16): Likewise. (vrshrntq_n_s16): Likewise. (vshrnbq_n_s16): Likewise. (vshrntq_n_s16): Likewise. (vcmlaq_f16): Likewise. (vcmlaq_rot180_f16): Likewise. (vcmlaq_rot270_f16): Likewise. (vcmlaq_rot90_f16): Likewise. (vfmaq_f16): Likewise. (vfmaq_n_f16): Likewise. (vfmasq_n_f16): Likewise. (vfmsq_f16): Likewise. (vmlaldavaq_s16): Likewise. (vmlaldavaxq_s16): Likewise. (vmlsldavaq_s16): Likewise. (vmlsldavaxq_s16): Likewise. (vabsq_m_f16): Likewise. (vcvtmq_m_s16_f16): Likewise. (vcvtnq_m_s16_f16): Likewise. (vcvtpq_m_s16_f16): Likewise. (vcvtq_m_s16_f16): Likewise. (vdupq_m_n_f16): Likewise. (vmaxnmaq_m_f16): Likewise. (vmaxnmavq_p_f16): Likewise. (vmaxnmvq_p_f16): Likewise. (vminnmaq_m_f16): Likewise. (vminnmavq_p_f16): Likewise. (vminnmvq_p_f16): Likewise. (vmlaldavq_p_s16): Likewise. (vmlaldavxq_p_s16): Likewise. (vmlsldavq_p_s16): Likewise. (vmlsldavxq_p_s16): Likewise. (vmovlbq_m_s8): Likewise. (vmovltq_m_s8): Likewise. (vmovnbq_m_s16): Likewise. (vmovntq_m_s16): Likewise. (vnegq_m_f16): Likewise. (vpselq_f16): Likewise. (vqmovnbq_m_s16): Likewise. (vqmovntq_m_s16): Likewise. (vrev32q_m_s8): Likewise. (vrev64q_m_f16): Likewise. (vrndaq_m_f16): Likewise. (vrndmq_m_f16): Likewise. (vrndnq_m_f16): Likewise. (vrndpq_m_f16): Likewise. (vrndq_m_f16): Likewise. (vrndxq_m_f16): Likewise. (vcmpeqq_m_n_f16): Likewise. (vcmpgeq_m_f16): Likewise. (vcmpgeq_m_n_f16): Likewise. (vcmpgtq_m_f16): Likewise. (vcmpgtq_m_n_f16): Likewise. (vcmpleq_m_f16): Likewise. (vcmpleq_m_n_f16): Likewise. (vcmpltq_m_f16): Likewise. (vcmpltq_m_n_f16): Likewise. (vcmpneq_m_f16): Likewise. (vcmpneq_m_n_f16): Likewise. (vmvnq_m_n_u16): Likewise. (vorrq_m_n_u16): Likewise. (vqrshruntq_n_s16): Likewise. (vqshrunbq_n_s16): Likewise. (vqshruntq_n_s16): Likewise. (vcvtmq_m_u16_f16): Likewise. (vcvtnq_m_u16_f16): Likewise. (vcvtpq_m_u16_f16): Likewise. (vcvtq_m_u16_f16): Likewise. (vqmovunbq_m_s16): Likewise. (vqmovuntq_m_s16): Likewise. (vqrshrntq_n_u16): Likewise. (vqshrnbq_n_u16): Likewise. (vqshrntq_n_u16): Likewise. (vrshrnbq_n_u16): Likewise. (vrshrntq_n_u16): Likewise. (vshrnbq_n_u16): Likewise. (vshrntq_n_u16): Likewise. (vmlaldavaq_u16): Likewise. (vmlaldavaxq_u16): Likewise. (vmlaldavq_p_u16): Likewise. (vmlaldavxq_p_u16): Likewise. (vmovlbq_m_u8): Likewise. (vmovltq_m_u8): Likewise. (vmovnbq_m_u16): Likewise. (vmovntq_m_u16): Likewise. (vqmovnbq_m_u16): Likewise. (vqmovntq_m_u16): Likewise. (vrev32q_m_u8): Likewise. (vmvnq_m_n_s32): Likewise. (vorrq_m_n_s32): Likewise. (vqrshrntq_n_s32): Likewise. (vqshrnbq_n_s32): Likewise. (vqshrntq_n_s32): Likewise. (vrshrnbq_n_s32): Likewise. (vrshrntq_n_s32): Likewise. (vshrnbq_n_s32): Likewise. (vshrntq_n_s32): Likewise. (vcmlaq_f32): Likewise. (vcmlaq_rot180_f32): Likewise. (vcmlaq_rot270_f32): Likewise. (vcmlaq_rot90_f32): Likewise. (vfmaq_f32): Likewise. (vfmaq_n_f32): Likewise. (vfmasq_n_f32): Likewise. (vfmsq_f32): Likewise. (vmlaldavaq_s32): Likewise. (vmlaldavaxq_s32): Likewise. (vmlsldavaq_s32): Likewise. (vmlsldavaxq_s32): Likewise. (vabsq_m_f32): Likewise. (vcvtmq_m_s32_f32): Likewise. (vcvtnq_m_s32_f32): Likewise. (vcvtpq_m_s32_f32): Likewise. (vcvtq_m_s32_f32): Likewise. (vdupq_m_n_f32): Likewise. (vmaxnmaq_m_f32): Likewise. (vmaxnmavq_p_f32): Likewise. (vmaxnmvq_p_f32): Likewise. (vminnmaq_m_f32): Likewise. (vminnmavq_p_f32): Likewise. (vminnmvq_p_f32): Likewise. (vmlaldavq_p_s32): Likewise. (vmlaldavxq_p_s32): Likewise. (vmlsldavq_p_s32): Likewise. (vmlsldavxq_p_s32): Likewise. (vmovlbq_m_s16): Likewise. (vmovltq_m_s16): Likewise. (vmovnbq_m_s32): Likewise. (vmovntq_m_s32): Likewise. (vnegq_m_f32): Likewise. (vpselq_f32): Likewise. (vqmovnbq_m_s32): Likewise. (vqmovntq_m_s32): Likewise. (vrev32q_m_s16): Likewise. (vrev64q_m_f32): Likewise. (vrndaq_m_f32): Likewise. (vrndmq_m_f32): Likewise. (vrndnq_m_f32): Likewise. (vrndpq_m_f32): Likewise. (vrndq_m_f32): Likewise. (vrndxq_m_f32): Likewise. (vcmpeqq_m_n_f32): Likewise. (vcmpgeq_m_f32): Likewise. (vcmpgeq_m_n_f32): Likewise. (vcmpgtq_m_f32): Likewise. (vcmpgtq_m_n_f32): Likewise. (vcmpleq_m_f32): Likewise. (vcmpleq_m_n_f32): Likewise. (vcmpltq_m_f32): Likewise. (vcmpltq_m_n_f32): Likewise. (vcmpneq_m_f32): Likewise. (vcmpneq_m_n_f32): Likewise. (vmvnq_m_n_u32): Likewise. (vorrq_m_n_u32): Likewise. (vqrshruntq_n_s32): Likewise. (vqshrunbq_n_s32): Likewise. (vqshruntq_n_s32): Likewise. (vcvtmq_m_u32_f32): Likewise. (vcvtnq_m_u32_f32): Likewise. (vcvtpq_m_u32_f32): Likewise. (vcvtq_m_u32_f32): Likewise. (vqmovunbq_m_s32): Likewise. (vqmovuntq_m_s32): Likewise. (vqrshrntq_n_u32): Likewise. (vqshrnbq_n_u32): Likewise. (vqshrntq_n_u32): Likewise. (vrshrnbq_n_u32): Likewise. (vrshrntq_n_u32): Likewise. (vshrnbq_n_u32): Likewise. (vshrntq_n_u32): Likewise. (vmlaldavaq_u32): Likewise. (vmlaldavaxq_u32): Likewise. (vmlaldavq_p_u32): Likewise. (vmlaldavxq_p_u32): Likewise. (vmovlbq_m_u16): Likewise. (vmovltq_m_u16): Likewise. (vmovnbq_m_u32): Likewise. (vmovntq_m_u32): Likewise. (vqmovnbq_m_u32): Likewise. (vqmovntq_m_u32): Likewise. (vrev32q_m_u16): Likewise. (__arm_vrmlaldavhaxq_s32): Define intrinsic. (__arm_vrmlsldavhaq_s32): Likewise. (__arm_vrmlsldavhaxq_s32): Likewise. (__arm_vaddlvaq_p_s32): Likewise. (__arm_vrev16q_m_s8): Likewise. (__arm_vrmlaldavhq_p_s32): Likewise. (__arm_vrmlaldavhxq_p_s32): Likewise. (__arm_vrmlsldavhq_p_s32): Likewise. (__arm_vrmlsldavhxq_p_s32): Likewise. (__arm_vaddlvaq_p_u32): Likewise. (__arm_vrev16q_m_u8): Likewise. (__arm_vrmlaldavhq_p_u32): Likewise. (__arm_vmvnq_m_n_s16): Likewise. (__arm_vorrq_m_n_s16): Likewise. (__arm_vqrshrntq_n_s16): Likewise. (__arm_vqshrnbq_n_s16): Likewise. (__arm_vqshrntq_n_s16): Likewise. (__arm_vrshrnbq_n_s16): Likewise. (__arm_vrshrntq_n_s16): Likewise. (__arm_vshrnbq_n_s16): Likewise. (__arm_vshrntq_n_s16): Likewise. (__arm_vmlaldavaq_s16): Likewise. (__arm_vmlaldavaxq_s16): Likewise. (__arm_vmlsldavaq_s16): Likewise. (__arm_vmlsldavaxq_s16): Likewise. (__arm_vmlaldavq_p_s16): Likewise. (__arm_vmlaldavxq_p_s16): Likewise. (__arm_vmlsldavq_p_s16): Likewise. (__arm_vmlsldavxq_p_s16): Likewise. (__arm_vmovlbq_m_s8): Likewise. (__arm_vmovltq_m_s8): Likewise. (__arm_vmovnbq_m_s16): Likewise. (__arm_vmovntq_m_s16): Likewise. (__arm_vqmovnbq_m_s16): Likewise. (__arm_vqmovntq_m_s16): Likewise. (__arm_vrev32q_m_s8): Likewise. (__arm_vmvnq_m_n_u16): Likewise. (__arm_vorrq_m_n_u16): Likewise. (__arm_vqrshruntq_n_s16): Likewise. (__arm_vqshrunbq_n_s16): Likewise. (__arm_vqshruntq_n_s16): Likewise. (__arm_vqmovunbq_m_s16): Likewise. (__arm_vqmovuntq_m_s16): Likewise. (__arm_vqrshrntq_n_u16): Likewise. (__arm_vqshrnbq_n_u16): Likewise. (__arm_vqshrntq_n_u16): Likewise. (__arm_vrshrnbq_n_u16): Likewise. (__arm_vrshrntq_n_u16): Likewise. (__arm_vshrnbq_n_u16): Likewise. (__arm_vshrntq_n_u16): Likewise. (__arm_vmlaldavaq_u16): Likewise. (__arm_vmlaldavaxq_u16): Likewise. (__arm_vmlaldavq_p_u16): Likewise. (__arm_vmlaldavxq_p_u16): Likewise. (__arm_vmovlbq_m_u8): Likewise. (__arm_vmovltq_m_u8): Likewise. (__arm_vmovnbq_m_u16): Likewise. (__arm_vmovntq_m_u16): Likewise. (__arm_vqmovnbq_m_u16): Likewise. (__arm_vqmovntq_m_u16): Likewise. (__arm_vrev32q_m_u8): Likewise. (__arm_vmvnq_m_n_s32): Likewise. (__arm_vorrq_m_n_s32): Likewise. (__arm_vqrshrntq_n_s32): Likewise. (__arm_vqshrnbq_n_s32): Likewise. (__arm_vqshrntq_n_s32): Likewise. (__arm_vrshrnbq_n_s32): Likewise. (__arm_vrshrntq_n_s32): Likewise. (__arm_vshrnbq_n_s32): Likewise. (__arm_vshrntq_n_s32): Likewise. (__arm_vmlaldavaq_s32): Likewise. (__arm_vmlaldavaxq_s32): Likewise. (__arm_vmlsldavaq_s32): Likewise. (__arm_vmlsldavaxq_s32): Likewise. (__arm_vmlaldavq_p_s32): Likewise. (__arm_vmlaldavxq_p_s32): Likewise. (__arm_vmlsldavq_p_s32): Likewise. (__arm_vmlsldavxq_p_s32): Likewise. (__arm_vmovlbq_m_s16): Likewise. (__arm_vmovltq_m_s16): Likewise. (__arm_vmovnbq_m_s32): Likewise. (__arm_vmovntq_m_s32): Likewise. (__arm_vqmovnbq_m_s32): Likewise. (__arm_vqmovntq_m_s32): Likewise. (__arm_vrev32q_m_s16): Likewise. (__arm_vmvnq_m_n_u32): Likewise. (__arm_vorrq_m_n_u32): Likewise. (__arm_vqrshruntq_n_s32): Likewise. (__arm_vqshrunbq_n_s32): Likewise. (__arm_vqshruntq_n_s32): Likewise. (__arm_vqmovunbq_m_s32): Likewise. (__arm_vqmovuntq_m_s32): Likewise. (__arm_vqrshrntq_n_u32): Likewise. (__arm_vqshrnbq_n_u32): Likewise. (__arm_vqshrntq_n_u32): Likewise. (__arm_vrshrnbq_n_u32): Likewise. (__arm_vrshrntq_n_u32): Likewise. (__arm_vshrnbq_n_u32): Likewise. (__arm_vshrntq_n_u32): Likewise. (__arm_vmlaldavaq_u32): Likewise. (__arm_vmlaldavaxq_u32): Likewise. (__arm_vmlaldavq_p_u32): Likewise. (__arm_vmlaldavxq_p_u32): Likewise. (__arm_vmovlbq_m_u16): Likewise. (__arm_vmovltq_m_u16): Likewise. (__arm_vmovnbq_m_u32): Likewise. (__arm_vmovntq_m_u32): Likewise. (__arm_vqmovnbq_m_u32): Likewise. (__arm_vqmovntq_m_u32): Likewise. (__arm_vrev32q_m_u16): Likewise. (__arm_vcvtbq_m_f16_f32): Likewise. (__arm_vcvtbq_m_f32_f16): Likewise. (__arm_vcvttq_m_f16_f32): Likewise. (__arm_vcvttq_m_f32_f16): Likewise. (__arm_vrev32q_m_f16): Likewise. (__arm_vcmlaq_f16): Likewise. (__arm_vcmlaq_rot180_f16): Likewise. (__arm_vcmlaq_rot270_f16): Likewise. (__arm_vcmlaq_rot90_f16): Likewise. (__arm_vfmaq_f16): Likewise. (__arm_vfmaq_n_f16): Likewise. (__arm_vfmasq_n_f16): Likewise. (__arm_vfmsq_f16): Likewise. (__arm_vabsq_m_f16): Likewise. (__arm_vcvtmq_m_s16_f16): Likewise. (__arm_vcvtnq_m_s16_f16): Likewise. (__arm_vcvtpq_m_s16_f16): Likewise. (__arm_vcvtq_m_s16_f16): Likewise. (__arm_vdupq_m_n_f16): Likewise. (__arm_vmaxnmaq_m_f16): Likewise. (__arm_vmaxnmavq_p_f16): Likewise. (__arm_vmaxnmvq_p_f16): Likewise. (__arm_vminnmaq_m_f16): Likewise. (__arm_vminnmavq_p_f16): Likewise. (__arm_vminnmvq_p_f16): Likewise. (__arm_vnegq_m_f16): Likewise. (__arm_vpselq_f16): Likewise. (__arm_vrev64q_m_f16): Likewise. (__arm_vrndaq_m_f16): Likewise. (__arm_vrndmq_m_f16): Likewise. (__arm_vrndnq_m_f16): Likewise. (__arm_vrndpq_m_f16): Likewise. (__arm_vrndq_m_f16): Likewise. (__arm_vrndxq_m_f16): Likewise. (__arm_vcmpeqq_m_n_f16): Likewise. (__arm_vcmpgeq_m_f16): Likewise. (__arm_vcmpgeq_m_n_f16): Likewise. (__arm_vcmpgtq_m_f16): Likewise. (__arm_vcmpgtq_m_n_f16): Likewise. (__arm_vcmpleq_m_f16): Likewise. (__arm_vcmpleq_m_n_f16): Likewise. (__arm_vcmpltq_m_f16): Likewise. (__arm_vcmpltq_m_n_f16): Likewise. (__arm_vcmpneq_m_f16): Likewise. (__arm_vcmpneq_m_n_f16): Likewise. (__arm_vcvtmq_m_u16_f16): Likewise. (__arm_vcvtnq_m_u16_f16): Likewise. (__arm_vcvtpq_m_u16_f16): Likewise. (__arm_vcvtq_m_u16_f16): Likewise. (__arm_vcmlaq_f32): Likewise. (__arm_vcmlaq_rot180_f32): Likewise. (__arm_vcmlaq_rot270_f32): Likewise. (__arm_vcmlaq_rot90_f32): Likewise. (__arm_vfmaq_f32): Likewise. (__arm_vfmaq_n_f32): Likewise. (__arm_vfmasq_n_f32): Likewise. (__arm_vfmsq_f32): Likewise. (__arm_vabsq_m_f32): Likewise. (__arm_vcvtmq_m_s32_f32): Likewise. (__arm_vcvtnq_m_s32_f32): Likewise. (__arm_vcvtpq_m_s32_f32): Likewise. (__arm_vcvtq_m_s32_f32): Likewise. (__arm_vdupq_m_n_f32): Likewise. (__arm_vmaxnmaq_m_f32): Likewise. (__arm_vmaxnmavq_p_f32): Likewise. (__arm_vmaxnmvq_p_f32): Likewise. (__arm_vminnmaq_m_f32): Likewise. (__arm_vminnmavq_p_f32): Likewise. (__arm_vminnmvq_p_f32): Likewise. (__arm_vnegq_m_f32): Likewise. (__arm_vpselq_f32): Likewise. (__arm_vrev64q_m_f32): Likewise. (__arm_vrndaq_m_f32): Likewise. (__arm_vrndmq_m_f32): Likewise. (__arm_vrndnq_m_f32): Likewise. (__arm_vrndpq_m_f32): Likewise. (__arm_vrndq_m_f32): Likewise. (__arm_vrndxq_m_f32): Likewise. (__arm_vcmpeqq_m_n_f32): Likewise. (__arm_vcmpgeq_m_f32): Likewise. (__arm_vcmpgeq_m_n_f32): Likewise. (__arm_vcmpgtq_m_f32): Likewise. (__arm_vcmpgtq_m_n_f32): Likewise. (__arm_vcmpleq_m_f32): Likewise. (__arm_vcmpleq_m_n_f32): Likewise. (__arm_vcmpltq_m_f32): Likewise. (__arm_vcmpltq_m_n_f32): Likewise. (__arm_vcmpneq_m_f32): Likewise. (__arm_vcmpneq_m_n_f32): Likewise. (__arm_vcvtmq_m_u32_f32): Likewise. (__arm_vcvtnq_m_u32_f32): Likewise. (__arm_vcvtpq_m_u32_f32): Likewise. (__arm_vcvtq_m_u32_f32): Likewise. (vcvtq_m): Define polymorphic variant. (vabsq_m): Likewise. (vcmlaq): Likewise. (vcmlaq_rot180): Likewise. (vcmlaq_rot270): Likewise. (vcmlaq_rot90): Likewise. (vcmpeqq_m_n): Likewise. (vcmpgeq_m_n): Likewise. (vrndxq_m): Likewise. (vrndq_m): Likewise. (vrndpq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpneq_m): Likewise. (vcmpneq_m_n): Likewise. (vcvtbq_m): Likewise. (vcvttq_m): Likewise. (vcvtmq_m): Likewise. (vcvtnq_m): Likewise. (vcvtpq_m): Likewise. (vdupq_m_n): Likewise. (vfmaq_n): Likewise. (vfmaq): Likewise. (vfmasq_n): Likewise. (vfmsq): Likewise. (vmaxnmaq_m): Likewise. (vmaxnmavq_m): Likewise. (vmaxnmvq_m): Likewise. (vmaxnmavq_p): Likewise. (vmaxnmvq_p): Likewise. (vminnmaq_m): Likewise. (vminnmavq_p): Likewise. (vminnmvq_p): Likewise. (vrndnq_m): Likewise. (vrndaq_m): Likewise. (vrndmq_m): Likewise. (vrev64q_m): Likewise. (vrev32q_m): Likewise. (vpselq): Likewise. (vnegq_m): Likewise. (vcmpgeq_m): Likewise. (vshrntq_n): Likewise. (vrshrntq_n): Likewise. (vmovlbq_m): Likewise. (vmovnbq_m): Likewise. (vmovntq_m): Likewise. (vmvnq_m_n): Likewise. (vmvnq_m): Likewise. (vshrnbq_n): Likewise. (vrshrnbq_n): Likewise. (vqshruntq_n): Likewise. (vrev16q_m): Likewise. (vqshrunbq_n): Likewise. (vqshrntq_n): Likewise. (vqrshruntq_n): Likewise. (vqrshrntq_n): Likewise. (vqshrnbq_n): Likewise. (vqmovuntq_m): Likewise. (vqmovntq_m): Likewise. (vqmovnbq_m): Likewise. (vorrq_m_n): Likewise. (vmovltq_m): Likewise. (vqmovunbq_m): Likewise. (vaddlvaq_p): Likewise. (vmlaldavaq): Likewise. (vmlaldavaxq): Likewise. (vmlaldavq_p): Likewise. (vmlaldavxq_p): Likewise. (vmlsldavaq): Likewise. (vmlsldavaxq): Likewise. (vmlsldavq_p): Likewise. (vmlsldavxq_p): Likewise. (vrmlaldavhaxq): Likewise. (vrmlaldavhq_p): Likewise. (vrmlaldavhxq_p): Likewise. (vrmlsldavhaq): Likewise. (vrmlsldavhaxq): Likewise. (vrmlsldavhq_p): Likewise. (vrmlsldavhxq_p): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_IMM): Likewise. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. (MVE_pred3): Likewise. (MVE_constraint1): Likewise. (MVE_pred1): Likewise. (VMLALDAVQ_P): Define iterator. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise. (VORRQ_M_N): Likewise. (VREV32Q_M): Likewise. (VREV16Q_M): Likewise. (VQRSHRNTQ_N): Likewise. (VMOVNTQ_M): Likewise. (VMOVLBQ_M): Likewise. (VMLALDAVAQ): Likewise. (VQSHRNBQ_N): Likewise. (VSHRNBQ_N): Likewise. (VRSHRNBQ_N): Likewise. (VMLALDAVXQ_P): Likewise. (VQMOVNTQ_M): Likewise. (VMVNQ_M_N): Likewise. (VQSHRNTQ_N): Likewise. (VMLALDAVAXQ): Likewise. (VSHRNTQ_N): Likewise. (VCVTMQ_M): Likewise. (VCVTNQ_M): Likewise. (VCVTPQ_M): Likewise. (VCVTQ_M_N_FROM_F): Likewise. (VCVTQ_M_FROM_F): Likewise. (VRMLALDAVHQ_P): Likewise. (VADDLVAQ_P): Likewise. (mve_vrndq_m_f): Define RTL pattern. (mve_vabsq_m_f): Likewise. (mve_vaddlvaq_p_v4si): Likewise. (mve_vcmlaq_f): Likewise. (mve_vcmlaq_rot180_f): Likewise. (mve_vcmlaq_rot270_f): Likewise. (mve_vcmlaq_rot90_f): Likewise. (mve_vcmpeqq_m_n_f): Likewise. (mve_vcmpgeq_m_f): Likewise. (mve_vcmpgeq_m_n_f): Likewise. (mve_vcmpgtq_m_f): Likewise. (mve_vcmpgtq_m_n_f): Likewise. (mve_vcmpleq_m_f): Likewise. (mve_vcmpleq_m_n_f): Likewise. (mve_vcmpltq_m_f): Likewise. (mve_vcmpltq_m_n_f): Likewise. (mve_vcmpneq_m_f): Likewise. (mve_vcmpneq_m_n_f): Likewise. (mve_vcvtbq_m_f16_f32v8hf): Likewise. (mve_vcvtbq_m_f32_f16v4sf): Likewise. (mve_vcvttq_m_f16_f32v8hf): Likewise. (mve_vcvttq_m_f32_f16v4sf): Likewise. (mve_vdupq_m_n_f): Likewise. (mve_vfmaq_f): Likewise. (mve_vfmaq_n_f): Likewise. (mve_vfmasq_n_f): Likewise. (mve_vfmsq_f): Likewise. (mve_vmaxnmaq_m_f): Likewise. (mve_vmaxnmavq_p_f): Likewise. (mve_vmaxnmvq_p_f): Likewise. (mve_vminnmaq_m_f): Likewise. (mve_vminnmavq_p_f): Likewise. (mve_vminnmvq_p_f): Likewise. (mve_vmlaldavaq_): Likewise. (mve_vmlaldavaxq_): Likewise. (mve_vmlaldavq_p_): Likewise. (mve_vmlaldavxq_p_): Likewise. (mve_vmlsldavaq_s): Likewise. (mve_vmlsldavaxq_s): Likewise. (mve_vmlsldavq_p_s): Likewise. (mve_vmlsldavxq_p_s): Likewise. (mve_vmovlbq_m_): Likewise. (mve_vmovltq_m_): Likewise. (mve_vmovnbq_m_): Likewise. (mve_vmovntq_m_): Likewise. (mve_vmvnq_m_n_): Likewise. (mve_vnegq_m_f): Likewise. (mve_vorrq_m_n_): Likewise. (mve_vpselq_f): Likewise. (mve_vqmovnbq_m_): Likewise. (mve_vqmovntq_m_): Likewise. (mve_vqmovunbq_m_s): Likewise. (mve_vqmovuntq_m_s): Likewise. (mve_vqrshrntq_n_): Likewise. (mve_vqrshruntq_n_s): Likewise. (mve_vqshrnbq_n_): Likewise. (mve_vqshrntq_n_): Likewise. (mve_vqshrunbq_n_s): Likewise. (mve_vqshruntq_n_s): Likewise. (mve_vrev32q_m_fv8hf): Likewise. (mve_vrev32q_m_): Likewise. (mve_vrev64q_m_f): Likewise. (mve_vrmlaldavhaxq_sv4si): Likewise. (mve_vrmlaldavhxq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_sv4si): Likewise. (mve_vrmlsldavhq_p_sv4si): Likewise. (mve_vrmlsldavhxq_p_sv4si): Likewise. (mve_vrndaq_m_f): Likewise. (mve_vrndmq_m_f): Likewise. (mve_vrndnq_m_f): Likewise. (mve_vrndpq_m_f): Likewise. (mve_vrndxq_m_f): Likewise. (mve_vrshrnbq_n_): Likewise. (mve_vrshrntq_n_): Likewise. (mve_vshrnbq_n_): Likewise. (mve_vshrntq_n_): Likewise. (mve_vcvtmq_m_): Likewise. (mve_vcvtpq_m_): Likewise. (mve_vcvtnq_m_): Likewise. (mve_vcvtq_m_n_from_f_): Likewise. (mve_vrev16q_m_v16qi): Likewise. (mve_vcvtq_m_from_f_): Likewise. (mve_vrmlaldavhq_p_v4si): Likewise. (mve_vrmlsldavhaq_sv4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise. --- gcc/ChangeLog | 621 +++ gcc/config/arm/arm_mve.h | 5785 ++++++++++++++------ gcc/config/arm/arm_mve_builtins.def | 108 + gcc/config/arm/mve.md | 1421 ++++- gcc/testsuite/ChangeLog | 208 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 23 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ebbdb8e..1d1efbd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,627 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. + (vrmlsldavhaq_s32): Likewise. + (vrmlsldavhaxq_s32): Likewise. + (vaddlvaq_p_s32): Likewise. + (vcvtbq_m_f16_f32): Likewise. + (vcvtbq_m_f32_f16): Likewise. + (vcvttq_m_f16_f32): Likewise. + (vcvttq_m_f32_f16): Likewise. + (vrev16q_m_s8): Likewise. + (vrev32q_m_f16): Likewise. + (vrmlaldavhq_p_s32): Likewise. + (vrmlaldavhxq_p_s32): Likewise. + (vrmlsldavhq_p_s32): Likewise. + (vrmlsldavhxq_p_s32): Likewise. + (vaddlvaq_p_u32): Likewise. + (vrev16q_m_u8): Likewise. + (vrmlaldavhq_p_u32): Likewise. + (vmvnq_m_n_s16): Likewise. + (vorrq_m_n_s16): Likewise. + (vqrshrntq_n_s16): Likewise. + (vqshrnbq_n_s16): Likewise. + (vqshrntq_n_s16): Likewise. + (vrshrnbq_n_s16): Likewise. + (vrshrntq_n_s16): Likewise. + (vshrnbq_n_s16): Likewise. + (vshrntq_n_s16): Likewise. + (vcmlaq_f16): Likewise. + (vcmlaq_rot180_f16): Likewise. + (vcmlaq_rot270_f16): Likewise. + (vcmlaq_rot90_f16): Likewise. + (vfmaq_f16): Likewise. + (vfmaq_n_f16): Likewise. + (vfmasq_n_f16): Likewise. + (vfmsq_f16): Likewise. + (vmlaldavaq_s16): Likewise. + (vmlaldavaxq_s16): Likewise. + (vmlsldavaq_s16): Likewise. + (vmlsldavaxq_s16): Likewise. + (vabsq_m_f16): Likewise. + (vcvtmq_m_s16_f16): Likewise. + (vcvtnq_m_s16_f16): Likewise. + (vcvtpq_m_s16_f16): Likewise. + (vcvtq_m_s16_f16): Likewise. + (vdupq_m_n_f16): Likewise. + (vmaxnmaq_m_f16): Likewise. + (vmaxnmavq_p_f16): Likewise. + (vmaxnmvq_p_f16): Likewise. + (vminnmaq_m_f16): Likewise. + (vminnmavq_p_f16): Likewise. + (vminnmvq_p_f16): Likewise. + (vmlaldavq_p_s16): Likewise. + (vmlaldavxq_p_s16): Likewise. + (vmlsldavq_p_s16): Likewise. + (vmlsldavxq_p_s16): Likewise. + (vmovlbq_m_s8): Likewise. + (vmovltq_m_s8): Likewise. + (vmovnbq_m_s16): Likewise. + (vmovntq_m_s16): Likewise. + (vnegq_m_f16): Likewise. + (vpselq_f16): Likewise. + (vqmovnbq_m_s16): Likewise. + (vqmovntq_m_s16): Likewise. + (vrev32q_m_s8): Likewise. + (vrev64q_m_f16): Likewise. + (vrndaq_m_f16): Likewise. + (vrndmq_m_f16): Likewise. + (vrndnq_m_f16): Likewise. + (vrndpq_m_f16): Likewise. + (vrndq_m_f16): Likewise. + (vrndxq_m_f16): Likewise. + (vcmpeqq_m_n_f16): Likewise. + (vcmpgeq_m_f16): Likewise. + (vcmpgeq_m_n_f16): Likewise. + (vcmpgtq_m_f16): Likewise. + (vcmpgtq_m_n_f16): Likewise. + (vcmpleq_m_f16): Likewise. + (vcmpleq_m_n_f16): Likewise. + (vcmpltq_m_f16): Likewise. + (vcmpltq_m_n_f16): Likewise. + (vcmpneq_m_f16): Likewise. + (vcmpneq_m_n_f16): Likewise. + (vmvnq_m_n_u16): Likewise. + (vorrq_m_n_u16): Likewise. + (vqrshruntq_n_s16): Likewise. + (vqshrunbq_n_s16): Likewise. + (vqshruntq_n_s16): Likewise. + (vcvtmq_m_u16_f16): Likewise. + (vcvtnq_m_u16_f16): Likewise. + (vcvtpq_m_u16_f16): Likewise. + (vcvtq_m_u16_f16): Likewise. + (vqmovunbq_m_s16): Likewise. + (vqmovuntq_m_s16): Likewise. + (vqrshrntq_n_u16): Likewise. + (vqshrnbq_n_u16): Likewise. + (vqshrntq_n_u16): Likewise. + (vrshrnbq_n_u16): Likewise. + (vrshrntq_n_u16): Likewise. + (vshrnbq_n_u16): Likewise. + (vshrntq_n_u16): Likewise. + (vmlaldavaq_u16): Likewise. + (vmlaldavaxq_u16): Likewise. + (vmlaldavq_p_u16): Likewise. + (vmlaldavxq_p_u16): Likewise. + (vmovlbq_m_u8): Likewise. + (vmovltq_m_u8): Likewise. + (vmovnbq_m_u16): Likewise. + (vmovntq_m_u16): Likewise. + (vqmovnbq_m_u16): Likewise. + (vqmovntq_m_u16): Likewise. + (vrev32q_m_u8): Likewise. + (vmvnq_m_n_s32): Likewise. + (vorrq_m_n_s32): Likewise. + (vqrshrntq_n_s32): Likewise. + (vqshrnbq_n_s32): Likewise. + (vqshrntq_n_s32): Likewise. + (vrshrnbq_n_s32): Likewise. + (vrshrntq_n_s32): Likewise. + (vshrnbq_n_s32): Likewise. + (vshrntq_n_s32): Likewise. + (vcmlaq_f32): Likewise. + (vcmlaq_rot180_f32): Likewise. + (vcmlaq_rot270_f32): Likewise. + (vcmlaq_rot90_f32): Likewise. + (vfmaq_f32): Likewise. + (vfmaq_n_f32): Likewise. + (vfmasq_n_f32): Likewise. + (vfmsq_f32): Likewise. + (vmlaldavaq_s32): Likewise. + (vmlaldavaxq_s32): Likewise. + (vmlsldavaq_s32): Likewise. + (vmlsldavaxq_s32): Likewise. + (vabsq_m_f32): Likewise. + (vcvtmq_m_s32_f32): Likewise. + (vcvtnq_m_s32_f32): Likewise. + (vcvtpq_m_s32_f32): Likewise. + (vcvtq_m_s32_f32): Likewise. + (vdupq_m_n_f32): Likewise. + (vmaxnmaq_m_f32): Likewise. + (vmaxnmavq_p_f32): Likewise. + (vmaxnmvq_p_f32): Likewise. + (vminnmaq_m_f32): Likewise. + (vminnmavq_p_f32): Likewise. + (vminnmvq_p_f32): Likewise. + (vmlaldavq_p_s32): Likewise. + (vmlaldavxq_p_s32): Likewise. + (vmlsldavq_p_s32): Likewise. + (vmlsldavxq_p_s32): Likewise. + (vmovlbq_m_s16): Likewise. + (vmovltq_m_s16): Likewise. + (vmovnbq_m_s32): Likewise. + (vmovntq_m_s32): Likewise. + (vnegq_m_f32): Likewise. + (vpselq_f32): Likewise. + (vqmovnbq_m_s32): Likewise. + (vqmovntq_m_s32): Likewise. + (vrev32q_m_s16): Likewise. + (vrev64q_m_f32): Likewise. + (vrndaq_m_f32): Likewise. + (vrndmq_m_f32): Likewise. + (vrndnq_m_f32): Likewise. + (vrndpq_m_f32): Likewise. + (vrndq_m_f32): Likewise. + (vrndxq_m_f32): Likewise. + (vcmpeqq_m_n_f32): Likewise. + (vcmpgeq_m_f32): Likewise. + (vcmpgeq_m_n_f32): Likewise. + (vcmpgtq_m_f32): Likewise. + (vcmpgtq_m_n_f32): Likewise. + (vcmpleq_m_f32): Likewise. + (vcmpleq_m_n_f32): Likewise. + (vcmpltq_m_f32): Likewise. + (vcmpltq_m_n_f32): Likewise. + (vcmpneq_m_f32): Likewise. + (vcmpneq_m_n_f32): Likewise. + (vmvnq_m_n_u32): Likewise. + (vorrq_m_n_u32): Likewise. + (vqrshruntq_n_s32): Likewise. + (vqshrunbq_n_s32): Likewise. + (vqshruntq_n_s32): Likewise. + (vcvtmq_m_u32_f32): Likewise. + (vcvtnq_m_u32_f32): Likewise. + (vcvtpq_m_u32_f32): Likewise. + (vcvtq_m_u32_f32): Likewise. + (vqmovunbq_m_s32): Likewise. + (vqmovuntq_m_s32): Likewise. + (vqrshrntq_n_u32): Likewise. + (vqshrnbq_n_u32): Likewise. + (vqshrntq_n_u32): Likewise. + (vrshrnbq_n_u32): Likewise. + (vrshrntq_n_u32): Likewise. + (vshrnbq_n_u32): Likewise. + (vshrntq_n_u32): Likewise. + (vmlaldavaq_u32): Likewise. + (vmlaldavaxq_u32): Likewise. + (vmlaldavq_p_u32): Likewise. + (vmlaldavxq_p_u32): Likewise. + (vmovlbq_m_u16): Likewise. + (vmovltq_m_u16): Likewise. + (vmovnbq_m_u32): Likewise. + (vmovntq_m_u32): Likewise. + (vqmovnbq_m_u32): Likewise. + (vqmovntq_m_u32): Likewise. + (vrev32q_m_u16): Likewise. + (__arm_vrmlaldavhaxq_s32): Define intrinsic. + (__arm_vrmlsldavhaq_s32): Likewise. + (__arm_vrmlsldavhaxq_s32): Likewise. + (__arm_vaddlvaq_p_s32): Likewise. + (__arm_vrev16q_m_s8): Likewise. + (__arm_vrmlaldavhq_p_s32): Likewise. + (__arm_vrmlaldavhxq_p_s32): Likewise. + (__arm_vrmlsldavhq_p_s32): Likewise. + (__arm_vrmlsldavhxq_p_s32): Likewise. + (__arm_vaddlvaq_p_u32): Likewise. + (__arm_vrev16q_m_u8): Likewise. + (__arm_vrmlaldavhq_p_u32): Likewise. + (__arm_vmvnq_m_n_s16): Likewise. + (__arm_vorrq_m_n_s16): Likewise. + (__arm_vqrshrntq_n_s16): Likewise. + (__arm_vqshrnbq_n_s16): Likewise. + (__arm_vqshrntq_n_s16): Likewise. + (__arm_vrshrnbq_n_s16): Likewise. + (__arm_vrshrntq_n_s16): Likewise. + (__arm_vshrnbq_n_s16): Likewise. + (__arm_vshrntq_n_s16): Likewise. + (__arm_vmlaldavaq_s16): Likewise. + (__arm_vmlaldavaxq_s16): Likewise. + (__arm_vmlsldavaq_s16): Likewise. + (__arm_vmlsldavaxq_s16): Likewise. + (__arm_vmlaldavq_p_s16): Likewise. + (__arm_vmlaldavxq_p_s16): Likewise. + (__arm_vmlsldavq_p_s16): Likewise. + (__arm_vmlsldavxq_p_s16): Likewise. + (__arm_vmovlbq_m_s8): Likewise. + (__arm_vmovltq_m_s8): Likewise. + (__arm_vmovnbq_m_s16): Likewise. + (__arm_vmovntq_m_s16): Likewise. + (__arm_vqmovnbq_m_s16): Likewise. + (__arm_vqmovntq_m_s16): Likewise. + (__arm_vrev32q_m_s8): Likewise. + (__arm_vmvnq_m_n_u16): Likewise. + (__arm_vorrq_m_n_u16): Likewise. + (__arm_vqrshruntq_n_s16): Likewise. + (__arm_vqshrunbq_n_s16): Likewise. + (__arm_vqshruntq_n_s16): Likewise. + (__arm_vqmovunbq_m_s16): Likewise. + (__arm_vqmovuntq_m_s16): Likewise. + (__arm_vqrshrntq_n_u16): Likewise. + (__arm_vqshrnbq_n_u16): Likewise. + (__arm_vqshrntq_n_u16): Likewise. + (__arm_vrshrnbq_n_u16): Likewise. + (__arm_vrshrntq_n_u16): Likewise. + (__arm_vshrnbq_n_u16): Likewise. + (__arm_vshrntq_n_u16): Likewise. + (__arm_vmlaldavaq_u16): Likewise. + (__arm_vmlaldavaxq_u16): Likewise. + (__arm_vmlaldavq_p_u16): Likewise. + (__arm_vmlaldavxq_p_u16): Likewise. + (__arm_vmovlbq_m_u8): Likewise. + (__arm_vmovltq_m_u8): Likewise. + (__arm_vmovnbq_m_u16): Likewise. + (__arm_vmovntq_m_u16): Likewise. + (__arm_vqmovnbq_m_u16): Likewise. + (__arm_vqmovntq_m_u16): Likewise. + (__arm_vrev32q_m_u8): Likewise. + (__arm_vmvnq_m_n_s32): Likewise. + (__arm_vorrq_m_n_s32): Likewise. + (__arm_vqrshrntq_n_s32): Likewise. + (__arm_vqshrnbq_n_s32): Likewise. + (__arm_vqshrntq_n_s32): Likewise. + (__arm_vrshrnbq_n_s32): Likewise. + (__arm_vrshrntq_n_s32): Likewise. + (__arm_vshrnbq_n_s32): Likewise. + (__arm_vshrntq_n_s32): Likewise. + (__arm_vmlaldavaq_s32): Likewise. + (__arm_vmlaldavaxq_s32): Likewise. + (__arm_vmlsldavaq_s32): Likewise. + (__arm_vmlsldavaxq_s32): Likewise. + (__arm_vmlaldavq_p_s32): Likewise. + (__arm_vmlaldavxq_p_s32): Likewise. + (__arm_vmlsldavq_p_s32): Likewise. + (__arm_vmlsldavxq_p_s32): Likewise. + (__arm_vmovlbq_m_s16): Likewise. + (__arm_vmovltq_m_s16): Likewise. + (__arm_vmovnbq_m_s32): Likewise. + (__arm_vmovntq_m_s32): Likewise. + (__arm_vqmovnbq_m_s32): Likewise. + (__arm_vqmovntq_m_s32): Likewise. + (__arm_vrev32q_m_s16): Likewise. + (__arm_vmvnq_m_n_u32): Likewise. + (__arm_vorrq_m_n_u32): Likewise. + (__arm_vqrshruntq_n_s32): Likewise. + (__arm_vqshrunbq_n_s32): Likewise. + (__arm_vqshruntq_n_s32): Likewise. + (__arm_vqmovunbq_m_s32): Likewise. + (__arm_vqmovuntq_m_s32): Likewise. + (__arm_vqrshrntq_n_u32): Likewise. + (__arm_vqshrnbq_n_u32): Likewise. + (__arm_vqshrntq_n_u32): Likewise. + (__arm_vrshrnbq_n_u32): Likewise. + (__arm_vrshrntq_n_u32): Likewise. + (__arm_vshrnbq_n_u32): Likewise. + (__arm_vshrntq_n_u32): Likewise. + (__arm_vmlaldavaq_u32): Likewise. + (__arm_vmlaldavaxq_u32): Likewise. + (__arm_vmlaldavq_p_u32): Likewise. + (__arm_vmlaldavxq_p_u32): Likewise. + (__arm_vmovlbq_m_u16): Likewise. + (__arm_vmovltq_m_u16): Likewise. + (__arm_vmovnbq_m_u32): Likewise. + (__arm_vmovntq_m_u32): Likewise. + (__arm_vqmovnbq_m_u32): Likewise. + (__arm_vqmovntq_m_u32): Likewise. + (__arm_vrev32q_m_u16): Likewise. + (__arm_vcvtbq_m_f16_f32): Likewise. + (__arm_vcvtbq_m_f32_f16): Likewise. + (__arm_vcvttq_m_f16_f32): Likewise. + (__arm_vcvttq_m_f32_f16): Likewise. + (__arm_vrev32q_m_f16): Likewise. + (__arm_vcmlaq_f16): Likewise. + (__arm_vcmlaq_rot180_f16): Likewise. + (__arm_vcmlaq_rot270_f16): Likewise. + (__arm_vcmlaq_rot90_f16): Likewise. + (__arm_vfmaq_f16): Likewise. + (__arm_vfmaq_n_f16): Likewise. + (__arm_vfmasq_n_f16): Likewise. + (__arm_vfmsq_f16): Likewise. + (__arm_vabsq_m_f16): Likewise. + (__arm_vcvtmq_m_s16_f16): Likewise. + (__arm_vcvtnq_m_s16_f16): Likewise. + (__arm_vcvtpq_m_s16_f16): Likewise. + (__arm_vcvtq_m_s16_f16): Likewise. + (__arm_vdupq_m_n_f16): Likewise. + (__arm_vmaxnmaq_m_f16): Likewise. + (__arm_vmaxnmavq_p_f16): Likewise. + (__arm_vmaxnmvq_p_f16): Likewise. + (__arm_vminnmaq_m_f16): Likewise. + (__arm_vminnmavq_p_f16): Likewise. + (__arm_vminnmvq_p_f16): Likewise. + (__arm_vnegq_m_f16): Likewise. + (__arm_vpselq_f16): Likewise. + (__arm_vrev64q_m_f16): Likewise. + (__arm_vrndaq_m_f16): Likewise. + (__arm_vrndmq_m_f16): Likewise. + (__arm_vrndnq_m_f16): Likewise. + (__arm_vrndpq_m_f16): Likewise. + (__arm_vrndq_m_f16): Likewise. + (__arm_vrndxq_m_f16): Likewise. + (__arm_vcmpeqq_m_n_f16): Likewise. + (__arm_vcmpgeq_m_f16): Likewise. + (__arm_vcmpgeq_m_n_f16): Likewise. + (__arm_vcmpgtq_m_f16): Likewise. + (__arm_vcmpgtq_m_n_f16): Likewise. + (__arm_vcmpleq_m_f16): Likewise. + (__arm_vcmpleq_m_n_f16): Likewise. + (__arm_vcmpltq_m_f16): Likewise. + (__arm_vcmpltq_m_n_f16): Likewise. + (__arm_vcmpneq_m_f16): Likewise. + (__arm_vcmpneq_m_n_f16): Likewise. + (__arm_vcvtmq_m_u16_f16): Likewise. + (__arm_vcvtnq_m_u16_f16): Likewise. + (__arm_vcvtpq_m_u16_f16): Likewise. + (__arm_vcvtq_m_u16_f16): Likewise. + (__arm_vcmlaq_f32): Likewise. + (__arm_vcmlaq_rot180_f32): Likewise. + (__arm_vcmlaq_rot270_f32): Likewise. + (__arm_vcmlaq_rot90_f32): Likewise. + (__arm_vfmaq_f32): Likewise. + (__arm_vfmaq_n_f32): Likewise. + (__arm_vfmasq_n_f32): Likewise. + (__arm_vfmsq_f32): Likewise. + (__arm_vabsq_m_f32): Likewise. + (__arm_vcvtmq_m_s32_f32): Likewise. + (__arm_vcvtnq_m_s32_f32): Likewise. + (__arm_vcvtpq_m_s32_f32): Likewise. + (__arm_vcvtq_m_s32_f32): Likewise. + (__arm_vdupq_m_n_f32): Likewise. + (__arm_vmaxnmaq_m_f32): Likewise. + (__arm_vmaxnmavq_p_f32): Likewise. + (__arm_vmaxnmvq_p_f32): Likewise. + (__arm_vminnmaq_m_f32): Likewise. + (__arm_vminnmavq_p_f32): Likewise. + (__arm_vminnmvq_p_f32): Likewise. + (__arm_vnegq_m_f32): Likewise. + (__arm_vpselq_f32): Likewise. + (__arm_vrev64q_m_f32): Likewise. + (__arm_vrndaq_m_f32): Likewise. + (__arm_vrndmq_m_f32): Likewise. + (__arm_vrndnq_m_f32): Likewise. + (__arm_vrndpq_m_f32): Likewise. + (__arm_vrndq_m_f32): Likewise. + (__arm_vrndxq_m_f32): Likewise. + (__arm_vcmpeqq_m_n_f32): Likewise. + (__arm_vcmpgeq_m_f32): Likewise. + (__arm_vcmpgeq_m_n_f32): Likewise. + (__arm_vcmpgtq_m_f32): Likewise. + (__arm_vcmpgtq_m_n_f32): Likewise. + (__arm_vcmpleq_m_f32): Likewise. + (__arm_vcmpleq_m_n_f32): Likewise. + (__arm_vcmpltq_m_f32): Likewise. + (__arm_vcmpltq_m_n_f32): Likewise. + (__arm_vcmpneq_m_f32): Likewise. + (__arm_vcmpneq_m_n_f32): Likewise. + (__arm_vcvtmq_m_u32_f32): Likewise. + (__arm_vcvtnq_m_u32_f32): Likewise. + (__arm_vcvtpq_m_u32_f32): Likewise. + (__arm_vcvtq_m_u32_f32): Likewise. + (vcvtq_m): Define polymorphic variant. + (vabsq_m): Likewise. + (vcmlaq): Likewise. + (vcmlaq_rot180): Likewise. + (vcmlaq_rot270): Likewise. + (vcmlaq_rot90): Likewise. + (vcmpeqq_m_n): Likewise. + (vcmpgeq_m_n): Likewise. + (vrndxq_m): Likewise. + (vrndq_m): Likewise. + (vrndpq_m): Likewise. + (vcmpgtq_m_n): Likewise. + (vcmpgtq_m): Likewise. + (vcmpleq_m): Likewise. + (vcmpleq_m_n): Likewise. + (vcmpltq_m_n): Likewise. + (vcmpltq_m): Likewise. + (vcmpneq_m): Likewise. + (vcmpneq_m_n): Likewise. + (vcvtbq_m): Likewise. + (vcvttq_m): Likewise. + (vcvtmq_m): Likewise. + (vcvtnq_m): Likewise. + (vcvtpq_m): Likewise. + (vdupq_m_n): Likewise. + (vfmaq_n): Likewise. + (vfmaq): Likewise. + (vfmasq_n): Likewise. + (vfmsq): Likewise. + (vmaxnmaq_m): Likewise. + (vmaxnmavq_m): Likewise. + (vmaxnmvq_m): Likewise. + (vmaxnmavq_p): Likewise. + (vmaxnmvq_p): Likewise. + (vminnmaq_m): Likewise. + (vminnmavq_p): Likewise. + (vminnmvq_p): Likewise. + (vrndnq_m): Likewise. + (vrndaq_m): Likewise. + (vrndmq_m): Likewise. + (vrev64q_m): Likewise. + (vrev32q_m): Likewise. + (vpselq): Likewise. + (vnegq_m): Likewise. + (vcmpgeq_m): Likewise. + (vshrntq_n): Likewise. + (vrshrntq_n): Likewise. + (vmovlbq_m): Likewise. + (vmovnbq_m): Likewise. + (vmovntq_m): Likewise. + (vmvnq_m_n): Likewise. + (vmvnq_m): Likewise. + (vshrnbq_n): Likewise. + (vrshrnbq_n): Likewise. + (vqshruntq_n): Likewise. + (vrev16q_m): Likewise. + (vqshrunbq_n): Likewise. + (vqshrntq_n): Likewise. + (vqrshruntq_n): Likewise. + (vqrshrntq_n): Likewise. + (vqshrnbq_n): Likewise. + (vqmovuntq_m): Likewise. + (vqmovntq_m): Likewise. + (vqmovnbq_m): Likewise. + (vorrq_m_n): Likewise. + (vmovltq_m): Likewise. + (vqmovunbq_m): Likewise. + (vaddlvaq_p): Likewise. + (vmlaldavaq): Likewise. + (vmlaldavaxq): Likewise. + (vmlaldavq_p): Likewise. + (vmlaldavxq_p): Likewise. + (vmlsldavaq): Likewise. + (vmlsldavaxq): Likewise. + (vmlsldavq_p): Likewise. + (vmlsldavxq_p): Likewise. + (vrmlaldavhaxq): Likewise. + (vrmlaldavhq_p): Likewise. + (vrmlaldavhxq_p): Likewise. + (vrmlsldavhaq): Likewise. + (vrmlsldavhaxq): Likewise. + (vrmlsldavhq_p): Likewise. + (vrmlsldavhxq_p): Likewise. + * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use + builtin qualifier. + (TERNOP_NONE_NONE_NONE_IMM): Likewise. + (TERNOP_NONE_NONE_NONE_NONE): Likewise. + (TERNOP_NONE_NONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. + (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. + (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. + (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. + (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. + * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. + (MVE_pred3): Likewise. + (MVE_constraint1): Likewise. + (MVE_pred1): Likewise. + (VMLALDAVQ_P): Define iterator. + (VQMOVNBQ_M): Likewise. + (VMOVLTQ_M): Likewise. + (VMOVNBQ_M): Likewise. + (VRSHRNTQ_N): Likewise. + (VORRQ_M_N): Likewise. + (VREV32Q_M): Likewise. + (VREV16Q_M): Likewise. + (VQRSHRNTQ_N): Likewise. + (VMOVNTQ_M): Likewise. + (VMOVLBQ_M): Likewise. + (VMLALDAVAQ): Likewise. + (VQSHRNBQ_N): Likewise. + (VSHRNBQ_N): Likewise. + (VRSHRNBQ_N): Likewise. + (VMLALDAVXQ_P): Likewise. + (VQMOVNTQ_M): Likewise. + (VMVNQ_M_N): Likewise. + (VQSHRNTQ_N): Likewise. + (VMLALDAVAXQ): Likewise. + (VSHRNTQ_N): Likewise. + (VCVTMQ_M): Likewise. + (VCVTNQ_M): Likewise. + (VCVTPQ_M): Likewise. + (VCVTQ_M_N_FROM_F): Likewise. + (VCVTQ_M_FROM_F): Likewise. + (VRMLALDAVHQ_P): Likewise. + (VADDLVAQ_P): Likewise. + (mve_vrndq_m_f): Define RTL pattern. + (mve_vabsq_m_f): Likewise. + (mve_vaddlvaq_p_v4si): Likewise. + (mve_vcmlaq_f): Likewise. + (mve_vcmlaq_rot180_f): Likewise. + (mve_vcmlaq_rot270_f): Likewise. + (mve_vcmlaq_rot90_f): Likewise. + (mve_vcmpeqq_m_n_f): Likewise. + (mve_vcmpgeq_m_f): Likewise. + (mve_vcmpgeq_m_n_f): Likewise. + (mve_vcmpgtq_m_f): Likewise. + (mve_vcmpgtq_m_n_f): Likewise. + (mve_vcmpleq_m_f): Likewise. + (mve_vcmpleq_m_n_f): Likewise. + (mve_vcmpltq_m_f): Likewise. + (mve_vcmpltq_m_n_f): Likewise. + (mve_vcmpneq_m_f): Likewise. + (mve_vcmpneq_m_n_f): Likewise. + (mve_vcvtbq_m_f16_f32v8hf): Likewise. + (mve_vcvtbq_m_f32_f16v4sf): Likewise. + (mve_vcvttq_m_f16_f32v8hf): Likewise. + (mve_vcvttq_m_f32_f16v4sf): Likewise. + (mve_vdupq_m_n_f): Likewise. + (mve_vfmaq_f): Likewise. + (mve_vfmaq_n_f): Likewise. + (mve_vfmasq_n_f): Likewise. + (mve_vfmsq_f): Likewise. + (mve_vmaxnmaq_m_f): Likewise. + (mve_vmaxnmavq_p_f): Likewise. + (mve_vmaxnmvq_p_f): Likewise. + (mve_vminnmaq_m_f): Likewise. + (mve_vminnmavq_p_f): Likewise. + (mve_vminnmvq_p_f): Likewise. + (mve_vmlaldavaq_): Likewise. + (mve_vmlaldavaxq_): Likewise. + (mve_vmlaldavq_p_): Likewise. + (mve_vmlaldavxq_p_): Likewise. + (mve_vmlsldavaq_s): Likewise. + (mve_vmlsldavaxq_s): Likewise. + (mve_vmlsldavq_p_s): Likewise. + (mve_vmlsldavxq_p_s): Likewise. + (mve_vmovlbq_m_): Likewise. + (mve_vmovltq_m_): Likewise. + (mve_vmovnbq_m_): Likewise. + (mve_vmovntq_m_): Likewise. + (mve_vmvnq_m_n_): Likewise. + (mve_vnegq_m_f): Likewise. + (mve_vorrq_m_n_): Likewise. + (mve_vpselq_f): Likewise. + (mve_vqmovnbq_m_): Likewise. + (mve_vqmovntq_m_): Likewise. + (mve_vqmovunbq_m_s): Likewise. + (mve_vqmovuntq_m_s): Likewise. + (mve_vqrshrntq_n_): Likewise. + (mve_vqrshruntq_n_s): Likewise. + (mve_vqshrnbq_n_): Likewise. + (mve_vqshrntq_n_): Likewise. + (mve_vqshrunbq_n_s): Likewise. + (mve_vqshruntq_n_s): Likewise. + (mve_vrev32q_m_fv8hf): Likewise. + (mve_vrev32q_m_): Likewise. + (mve_vrev64q_m_f): Likewise. + (mve_vrmlaldavhaxq_sv4si): Likewise. + (mve_vrmlaldavhxq_p_sv4si): Likewise. + (mve_vrmlsldavhaxq_sv4si): Likewise. + (mve_vrmlsldavhq_p_sv4si): Likewise. + (mve_vrmlsldavhxq_p_sv4si): Likewise. + (mve_vrndaq_m_f): Likewise. + (mve_vrndmq_m_f): Likewise. + (mve_vrndnq_m_f): Likewise. + (mve_vrndpq_m_f): Likewise. + (mve_vrndxq_m_f): Likewise. + (mve_vrshrnbq_n_): Likewise. + (mve_vrshrntq_n_): Likewise. + (mve_vshrnbq_n_): Likewise. + (mve_vshrntq_n_): Likewise. + (mve_vcvtmq_m_): Likewise. + (mve_vcvtpq_m_): Likewise. + (mve_vcvtnq_m_): Likewise. + (mve_vcvtq_m_n_from_f_): Likewise. + (mve_vrev16q_m_v16qi): Likewise. + (mve_vcvtq_m_from_f_): Likewise. + (mve_vrmlaldavhq_p_v4si): Likewise. + (mve_vrmlsldavhaq_sv4si): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vpselq_u8): Define macro. (vpselq_s8): Likewise. (vrev64q_m_u8): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index f852c68..363f9ca 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1033,6 +1033,205 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsliq_n_s32(__a, __b, __imm) __arm_vsliq_n_s32(__a, __b, __imm) #define vpselq_u64(__a, __b, __p) __arm_vpselq_u64(__a, __b, __p) #define vpselq_s64(__a, __b, __p) __arm_vpselq_s64(__a, __b, __p) +#define vrmlaldavhaxq_s32(__a, __b, __c) __arm_vrmlaldavhaxq_s32(__a, __b, __c) +#define vrmlsldavhaq_s32(__a, __b, __c) __arm_vrmlsldavhaq_s32(__a, __b, __c) +#define vrmlsldavhaxq_s32(__a, __b, __c) __arm_vrmlsldavhaxq_s32(__a, __b, __c) +#define vaddlvaq_p_s32(__a, __b, __p) __arm_vaddlvaq_p_s32(__a, __b, __p) +#define vcvtbq_m_f16_f32(__a, __b, __p) __arm_vcvtbq_m_f16_f32(__a, __b, __p) +#define vcvtbq_m_f32_f16(__inactive, __a, __p) __arm_vcvtbq_m_f32_f16(__inactive, __a, __p) +#define vcvttq_m_f16_f32(__a, __b, __p) __arm_vcvttq_m_f16_f32(__a, __b, __p) +#define vcvttq_m_f32_f16(__inactive, __a, __p) __arm_vcvttq_m_f32_f16(__inactive, __a, __p) +#define vrev16q_m_s8(__inactive, __a, __p) __arm_vrev16q_m_s8(__inactive, __a, __p) +#define vrev32q_m_f16(__inactive, __a, __p) __arm_vrev32q_m_f16(__inactive, __a, __p) +#define vrmlaldavhq_p_s32(__a, __b, __p) __arm_vrmlaldavhq_p_s32(__a, __b, __p) +#define vrmlaldavhxq_p_s32(__a, __b, __p) __arm_vrmlaldavhxq_p_s32(__a, __b, __p) +#define vrmlsldavhq_p_s32(__a, __b, __p) __arm_vrmlsldavhq_p_s32(__a, __b, __p) +#define vrmlsldavhxq_p_s32(__a, __b, __p) __arm_vrmlsldavhxq_p_s32(__a, __b, __p) +#define vaddlvaq_p_u32(__a, __b, __p) __arm_vaddlvaq_p_u32(__a, __b, __p) +#define vrev16q_m_u8(__inactive, __a, __p) __arm_vrev16q_m_u8(__inactive, __a, __p) +#define vrmlaldavhq_p_u32(__a, __b, __p) __arm_vrmlaldavhq_p_u32(__a, __b, __p) +#define vmvnq_m_n_s16(__inactive, __imm, __p) __arm_vmvnq_m_n_s16(__inactive, __imm, __p) +#define vorrq_m_n_s16(__a, __imm, __p) __arm_vorrq_m_n_s16(__a, __imm, __p) +#define vqrshrntq_n_s16(__a, __b, __imm) __arm_vqrshrntq_n_s16(__a, __b, __imm) +#define vqshrnbq_n_s16(__a, __b, __imm) __arm_vqshrnbq_n_s16(__a, __b, __imm) +#define vqshrntq_n_s16(__a, __b, __imm) __arm_vqshrntq_n_s16(__a, __b, __imm) +#define vrshrnbq_n_s16(__a, __b, __imm) __arm_vrshrnbq_n_s16(__a, __b, __imm) +#define vrshrntq_n_s16(__a, __b, __imm) __arm_vrshrntq_n_s16(__a, __b, __imm) +#define vshrnbq_n_s16(__a, __b, __imm) __arm_vshrnbq_n_s16(__a, __b, __imm) +#define vshrntq_n_s16(__a, __b, __imm) __arm_vshrntq_n_s16(__a, __b, __imm) +#define vcmlaq_f16(__a, __b, __c) __arm_vcmlaq_f16(__a, __b, __c) +#define vcmlaq_rot180_f16(__a, __b, __c) __arm_vcmlaq_rot180_f16(__a, __b, __c) +#define vcmlaq_rot270_f16(__a, __b, __c) __arm_vcmlaq_rot270_f16(__a, __b, __c) +#define vcmlaq_rot90_f16(__a, __b, __c) __arm_vcmlaq_rot90_f16(__a, __b, __c) +#define vfmaq_f16(__a, __b, __c) __arm_vfmaq_f16(__a, __b, __c) +#define vfmaq_n_f16(__a, __b, __c) __arm_vfmaq_n_f16(__a, __b, __c) +#define vfmasq_n_f16(__a, __b, __c) __arm_vfmasq_n_f16(__a, __b, __c) +#define vfmsq_f16(__a, __b, __c) __arm_vfmsq_f16(__a, __b, __c) +#define vmlaldavaq_s16(__a, __b, __c) __arm_vmlaldavaq_s16(__a, __b, __c) +#define vmlaldavaxq_s16(__a, __b, __c) __arm_vmlaldavaxq_s16(__a, __b, __c) +#define vmlsldavaq_s16(__a, __b, __c) __arm_vmlsldavaq_s16(__a, __b, __c) +#define vmlsldavaxq_s16(__a, __b, __c) __arm_vmlsldavaxq_s16(__a, __b, __c) +#define vabsq_m_f16(__inactive, __a, __p) __arm_vabsq_m_f16(__inactive, __a, __p) +#define vcvtmq_m_s16_f16(__inactive, __a, __p) __arm_vcvtmq_m_s16_f16(__inactive, __a, __p) +#define vcvtnq_m_s16_f16(__inactive, __a, __p) __arm_vcvtnq_m_s16_f16(__inactive, __a, __p) +#define vcvtpq_m_s16_f16(__inactive, __a, __p) __arm_vcvtpq_m_s16_f16(__inactive, __a, __p) +#define vcvtq_m_s16_f16(__inactive, __a, __p) __arm_vcvtq_m_s16_f16(__inactive, __a, __p) +#define vdupq_m_n_f16(__inactive, __a, __p) __arm_vdupq_m_n_f16(__inactive, __a, __p) +#define vmaxnmaq_m_f16(__a, __b, __p) __arm_vmaxnmaq_m_f16(__a, __b, __p) +#define vmaxnmavq_p_f16(__a, __b, __p) __arm_vmaxnmavq_p_f16(__a, __b, __p) +#define vmaxnmvq_p_f16(__a, __b, __p) __arm_vmaxnmvq_p_f16(__a, __b, __p) +#define vminnmaq_m_f16(__a, __b, __p) __arm_vminnmaq_m_f16(__a, __b, __p) +#define vminnmavq_p_f16(__a, __b, __p) __arm_vminnmavq_p_f16(__a, __b, __p) +#define vminnmvq_p_f16(__a, __b, __p) __arm_vminnmvq_p_f16(__a, __b, __p) +#define vmlaldavq_p_s16(__a, __b, __p) __arm_vmlaldavq_p_s16(__a, __b, __p) +#define vmlaldavxq_p_s16(__a, __b, __p) __arm_vmlaldavxq_p_s16(__a, __b, __p) +#define vmlsldavq_p_s16(__a, __b, __p) __arm_vmlsldavq_p_s16(__a, __b, __p) +#define vmlsldavxq_p_s16(__a, __b, __p) __arm_vmlsldavxq_p_s16(__a, __b, __p) +#define vmovlbq_m_s8(__inactive, __a, __p) __arm_vmovlbq_m_s8(__inactive, __a, __p) +#define vmovltq_m_s8(__inactive, __a, __p) __arm_vmovltq_m_s8(__inactive, __a, __p) +#define vmovnbq_m_s16(__a, __b, __p) __arm_vmovnbq_m_s16(__a, __b, __p) +#define vmovntq_m_s16(__a, __b, __p) __arm_vmovntq_m_s16(__a, __b, __p) +#define vnegq_m_f16(__inactive, __a, __p) __arm_vnegq_m_f16(__inactive, __a, __p) +#define vpselq_f16(__a, __b, __p) __arm_vpselq_f16(__a, __b, __p) +#define vqmovnbq_m_s16(__a, __b, __p) __arm_vqmovnbq_m_s16(__a, __b, __p) +#define vqmovntq_m_s16(__a, __b, __p) __arm_vqmovntq_m_s16(__a, __b, __p) +#define vrev32q_m_s8(__inactive, __a, __p) __arm_vrev32q_m_s8(__inactive, __a, __p) +#define vrev64q_m_f16(__inactive, __a, __p) __arm_vrev64q_m_f16(__inactive, __a, __p) +#define vrndaq_m_f16(__inactive, __a, __p) __arm_vrndaq_m_f16(__inactive, __a, __p) +#define vrndmq_m_f16(__inactive, __a, __p) __arm_vrndmq_m_f16(__inactive, __a, __p) +#define vrndnq_m_f16(__inactive, __a, __p) __arm_vrndnq_m_f16(__inactive, __a, __p) +#define vrndpq_m_f16(__inactive, __a, __p) __arm_vrndpq_m_f16(__inactive, __a, __p) +#define vrndq_m_f16(__inactive, __a, __p) __arm_vrndq_m_f16(__inactive, __a, __p) +#define vrndxq_m_f16(__inactive, __a, __p) __arm_vrndxq_m_f16(__inactive, __a, __p) +#define vcmpeqq_m_n_f16(__a, __b, __p) __arm_vcmpeqq_m_n_f16(__a, __b, __p) +#define vcmpgeq_m_f16(__a, __b, __p) __arm_vcmpgeq_m_f16(__a, __b, __p) +#define vcmpgeq_m_n_f16(__a, __b, __p) __arm_vcmpgeq_m_n_f16(__a, __b, __p) +#define vcmpgtq_m_f16(__a, __b, __p) __arm_vcmpgtq_m_f16(__a, __b, __p) +#define vcmpgtq_m_n_f16(__a, __b, __p) __arm_vcmpgtq_m_n_f16(__a, __b, __p) +#define vcmpleq_m_f16(__a, __b, __p) __arm_vcmpleq_m_f16(__a, __b, __p) +#define vcmpleq_m_n_f16(__a, __b, __p) __arm_vcmpleq_m_n_f16(__a, __b, __p) +#define vcmpltq_m_f16(__a, __b, __p) __arm_vcmpltq_m_f16(__a, __b, __p) +#define vcmpltq_m_n_f16(__a, __b, __p) __arm_vcmpltq_m_n_f16(__a, __b, __p) +#define vcmpneq_m_f16(__a, __b, __p) __arm_vcmpneq_m_f16(__a, __b, __p) +#define vcmpneq_m_n_f16(__a, __b, __p) __arm_vcmpneq_m_n_f16(__a, __b, __p) +#define vmvnq_m_n_u16(__inactive, __imm, __p) __arm_vmvnq_m_n_u16(__inactive, __imm, __p) +#define vorrq_m_n_u16(__a, __imm, __p) __arm_vorrq_m_n_u16(__a, __imm, __p) +#define vqrshruntq_n_s16(__a, __b, __imm) __arm_vqrshruntq_n_s16(__a, __b, __imm) +#define vqshrunbq_n_s16(__a, __b, __imm) __arm_vqshrunbq_n_s16(__a, __b, __imm) +#define vqshruntq_n_s16(__a, __b, __imm) __arm_vqshruntq_n_s16(__a, __b, __imm) +#define vcvtmq_m_u16_f16(__inactive, __a, __p) __arm_vcvtmq_m_u16_f16(__inactive, __a, __p) +#define vcvtnq_m_u16_f16(__inactive, __a, __p) __arm_vcvtnq_m_u16_f16(__inactive, __a, __p) +#define vcvtpq_m_u16_f16(__inactive, __a, __p) __arm_vcvtpq_m_u16_f16(__inactive, __a, __p) +#define vcvtq_m_u16_f16(__inactive, __a, __p) __arm_vcvtq_m_u16_f16(__inactive, __a, __p) +#define vqmovunbq_m_s16(__a, __b, __p) __arm_vqmovunbq_m_s16(__a, __b, __p) +#define vqmovuntq_m_s16(__a, __b, __p) __arm_vqmovuntq_m_s16(__a, __b, __p) +#define vqrshrntq_n_u16(__a, __b, __imm) __arm_vqrshrntq_n_u16(__a, __b, __imm) +#define vqshrnbq_n_u16(__a, __b, __imm) __arm_vqshrnbq_n_u16(__a, __b, __imm) +#define vqshrntq_n_u16(__a, __b, __imm) __arm_vqshrntq_n_u16(__a, __b, __imm) +#define vrshrnbq_n_u16(__a, __b, __imm) __arm_vrshrnbq_n_u16(__a, __b, __imm) +#define vrshrntq_n_u16(__a, __b, __imm) __arm_vrshrntq_n_u16(__a, __b, __imm) +#define vshrnbq_n_u16(__a, __b, __imm) __arm_vshrnbq_n_u16(__a, __b, __imm) +#define vshrntq_n_u16(__a, __b, __imm) __arm_vshrntq_n_u16(__a, __b, __imm) +#define vmlaldavaq_u16(__a, __b, __c) __arm_vmlaldavaq_u16(__a, __b, __c) +#define vmlaldavq_p_u16(__a, __b, __p) __arm_vmlaldavq_p_u16(__a, __b, __p) +#define vmovlbq_m_u8(__inactive, __a, __p) __arm_vmovlbq_m_u8(__inactive, __a, __p) +#define vmovltq_m_u8(__inactive, __a, __p) __arm_vmovltq_m_u8(__inactive, __a, __p) +#define vmovnbq_m_u16(__a, __b, __p) __arm_vmovnbq_m_u16(__a, __b, __p) +#define vmovntq_m_u16(__a, __b, __p) __arm_vmovntq_m_u16(__a, __b, __p) +#define vqmovnbq_m_u16(__a, __b, __p) __arm_vqmovnbq_m_u16(__a, __b, __p) +#define vqmovntq_m_u16(__a, __b, __p) __arm_vqmovntq_m_u16(__a, __b, __p) +#define vrev32q_m_u8(__inactive, __a, __p) __arm_vrev32q_m_u8(__inactive, __a, __p) +#define vmvnq_m_n_s32(__inactive, __imm, __p) __arm_vmvnq_m_n_s32(__inactive, __imm, __p) +#define vorrq_m_n_s32(__a, __imm, __p) __arm_vorrq_m_n_s32(__a, __imm, __p) +#define vqrshrntq_n_s32(__a, __b, __imm) __arm_vqrshrntq_n_s32(__a, __b, __imm) +#define vqshrnbq_n_s32(__a, __b, __imm) __arm_vqshrnbq_n_s32(__a, __b, __imm) +#define vqshrntq_n_s32(__a, __b, __imm) __arm_vqshrntq_n_s32(__a, __b, __imm) +#define vrshrnbq_n_s32(__a, __b, __imm) __arm_vrshrnbq_n_s32(__a, __b, __imm) +#define vrshrntq_n_s32(__a, __b, __imm) __arm_vrshrntq_n_s32(__a, __b, __imm) +#define vshrnbq_n_s32(__a, __b, __imm) __arm_vshrnbq_n_s32(__a, __b, __imm) +#define vshrntq_n_s32(__a, __b, __imm) __arm_vshrntq_n_s32(__a, __b, __imm) +#define vcmlaq_f32(__a, __b, __c) __arm_vcmlaq_f32(__a, __b, __c) +#define vcmlaq_rot180_f32(__a, __b, __c) __arm_vcmlaq_rot180_f32(__a, __b, __c) +#define vcmlaq_rot270_f32(__a, __b, __c) __arm_vcmlaq_rot270_f32(__a, __b, __c) +#define vcmlaq_rot90_f32(__a, __b, __c) __arm_vcmlaq_rot90_f32(__a, __b, __c) +#define vfmaq_f32(__a, __b, __c) __arm_vfmaq_f32(__a, __b, __c) +#define vfmaq_n_f32(__a, __b, __c) __arm_vfmaq_n_f32(__a, __b, __c) +#define vfmasq_n_f32(__a, __b, __c) __arm_vfmasq_n_f32(__a, __b, __c) +#define vfmsq_f32(__a, __b, __c) __arm_vfmsq_f32(__a, __b, __c) +#define vmlaldavaq_s32(__a, __b, __c) __arm_vmlaldavaq_s32(__a, __b, __c) +#define vmlaldavaxq_s32(__a, __b, __c) __arm_vmlaldavaxq_s32(__a, __b, __c) +#define vmlsldavaq_s32(__a, __b, __c) __arm_vmlsldavaq_s32(__a, __b, __c) +#define vmlsldavaxq_s32(__a, __b, __c) __arm_vmlsldavaxq_s32(__a, __b, __c) +#define vabsq_m_f32(__inactive, __a, __p) __arm_vabsq_m_f32(__inactive, __a, __p) +#define vcvtmq_m_s32_f32(__inactive, __a, __p) __arm_vcvtmq_m_s32_f32(__inactive, __a, __p) +#define vcvtnq_m_s32_f32(__inactive, __a, __p) __arm_vcvtnq_m_s32_f32(__inactive, __a, __p) +#define vcvtpq_m_s32_f32(__inactive, __a, __p) __arm_vcvtpq_m_s32_f32(__inactive, __a, __p) +#define vcvtq_m_s32_f32(__inactive, __a, __p) __arm_vcvtq_m_s32_f32(__inactive, __a, __p) +#define vdupq_m_n_f32(__inactive, __a, __p) __arm_vdupq_m_n_f32(__inactive, __a, __p) +#define vmaxnmaq_m_f32(__a, __b, __p) __arm_vmaxnmaq_m_f32(__a, __b, __p) +#define vmaxnmavq_p_f32(__a, __b, __p) __arm_vmaxnmavq_p_f32(__a, __b, __p) +#define vmaxnmvq_p_f32(__a, __b, __p) __arm_vmaxnmvq_p_f32(__a, __b, __p) +#define vminnmaq_m_f32(__a, __b, __p) __arm_vminnmaq_m_f32(__a, __b, __p) +#define vminnmavq_p_f32(__a, __b, __p) __arm_vminnmavq_p_f32(__a, __b, __p) +#define vminnmvq_p_f32(__a, __b, __p) __arm_vminnmvq_p_f32(__a, __b, __p) +#define vmlaldavq_p_s32(__a, __b, __p) __arm_vmlaldavq_p_s32(__a, __b, __p) +#define vmlaldavxq_p_s32(__a, __b, __p) __arm_vmlaldavxq_p_s32(__a, __b, __p) +#define vmlsldavq_p_s32(__a, __b, __p) __arm_vmlsldavq_p_s32(__a, __b, __p) +#define vmlsldavxq_p_s32(__a, __b, __p) __arm_vmlsldavxq_p_s32(__a, __b, __p) +#define vmovlbq_m_s16(__inactive, __a, __p) __arm_vmovlbq_m_s16(__inactive, __a, __p) +#define vmovltq_m_s16(__inactive, __a, __p) __arm_vmovltq_m_s16(__inactive, __a, __p) +#define vmovnbq_m_s32(__a, __b, __p) __arm_vmovnbq_m_s32(__a, __b, __p) +#define vmovntq_m_s32(__a, __b, __p) __arm_vmovntq_m_s32(__a, __b, __p) +#define vnegq_m_f32(__inactive, __a, __p) __arm_vnegq_m_f32(__inactive, __a, __p) +#define vpselq_f32(__a, __b, __p) __arm_vpselq_f32(__a, __b, __p) +#define vqmovnbq_m_s32(__a, __b, __p) __arm_vqmovnbq_m_s32(__a, __b, __p) +#define vqmovntq_m_s32(__a, __b, __p) __arm_vqmovntq_m_s32(__a, __b, __p) +#define vrev32q_m_s16(__inactive, __a, __p) __arm_vrev32q_m_s16(__inactive, __a, __p) +#define vrev64q_m_f32(__inactive, __a, __p) __arm_vrev64q_m_f32(__inactive, __a, __p) +#define vrndaq_m_f32(__inactive, __a, __p) __arm_vrndaq_m_f32(__inactive, __a, __p) +#define vrndmq_m_f32(__inactive, __a, __p) __arm_vrndmq_m_f32(__inactive, __a, __p) +#define vrndnq_m_f32(__inactive, __a, __p) __arm_vrndnq_m_f32(__inactive, __a, __p) +#define vrndpq_m_f32(__inactive, __a, __p) __arm_vrndpq_m_f32(__inactive, __a, __p) +#define vrndq_m_f32(__inactive, __a, __p) __arm_vrndq_m_f32(__inactive, __a, __p) +#define vrndxq_m_f32(__inactive, __a, __p) __arm_vrndxq_m_f32(__inactive, __a, __p) +#define vcmpeqq_m_n_f32(__a, __b, __p) __arm_vcmpeqq_m_n_f32(__a, __b, __p) +#define vcmpgeq_m_f32(__a, __b, __p) __arm_vcmpgeq_m_f32(__a, __b, __p) +#define vcmpgeq_m_n_f32(__a, __b, __p) __arm_vcmpgeq_m_n_f32(__a, __b, __p) +#define vcmpgtq_m_f32(__a, __b, __p) __arm_vcmpgtq_m_f32(__a, __b, __p) +#define vcmpgtq_m_n_f32(__a, __b, __p) __arm_vcmpgtq_m_n_f32(__a, __b, __p) +#define vcmpleq_m_f32(__a, __b, __p) __arm_vcmpleq_m_f32(__a, __b, __p) +#define vcmpleq_m_n_f32(__a, __b, __p) __arm_vcmpleq_m_n_f32(__a, __b, __p) +#define vcmpltq_m_f32(__a, __b, __p) __arm_vcmpltq_m_f32(__a, __b, __p) +#define vcmpltq_m_n_f32(__a, __b, __p) __arm_vcmpltq_m_n_f32(__a, __b, __p) +#define vcmpneq_m_f32(__a, __b, __p) __arm_vcmpneq_m_f32(__a, __b, __p) +#define vcmpneq_m_n_f32(__a, __b, __p) __arm_vcmpneq_m_n_f32(__a, __b, __p) +#define vmvnq_m_n_u32(__inactive, __imm, __p) __arm_vmvnq_m_n_u32(__inactive, __imm, __p) +#define vorrq_m_n_u32(__a, __imm, __p) __arm_vorrq_m_n_u32(__a, __imm, __p) +#define vqrshruntq_n_s32(__a, __b, __imm) __arm_vqrshruntq_n_s32(__a, __b, __imm) +#define vqshrunbq_n_s32(__a, __b, __imm) __arm_vqshrunbq_n_s32(__a, __b, __imm) +#define vqshruntq_n_s32(__a, __b, __imm) __arm_vqshruntq_n_s32(__a, __b, __imm) +#define vcvtmq_m_u32_f32(__inactive, __a, __p) __arm_vcvtmq_m_u32_f32(__inactive, __a, __p) +#define vcvtnq_m_u32_f32(__inactive, __a, __p) __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) +#define vcvtpq_m_u32_f32(__inactive, __a, __p) __arm_vcvtpq_m_u32_f32(__inactive, __a, __p) +#define vcvtq_m_u32_f32(__inactive, __a, __p) __arm_vcvtq_m_u32_f32(__inactive, __a, __p) +#define vqmovunbq_m_s32(__a, __b, __p) __arm_vqmovunbq_m_s32(__a, __b, __p) +#define vqmovuntq_m_s32(__a, __b, __p) __arm_vqmovuntq_m_s32(__a, __b, __p) +#define vqrshrntq_n_u32(__a, __b, __imm) __arm_vqrshrntq_n_u32(__a, __b, __imm) +#define vqshrnbq_n_u32(__a, __b, __imm) __arm_vqshrnbq_n_u32(__a, __b, __imm) +#define vqshrntq_n_u32(__a, __b, __imm) __arm_vqshrntq_n_u32(__a, __b, __imm) +#define vrshrnbq_n_u32(__a, __b, __imm) __arm_vrshrnbq_n_u32(__a, __b, __imm) +#define vrshrntq_n_u32(__a, __b, __imm) __arm_vrshrntq_n_u32(__a, __b, __imm) +#define vshrnbq_n_u32(__a, __b, __imm) __arm_vshrnbq_n_u32(__a, __b, __imm) +#define vshrntq_n_u32(__a, __b, __imm) __arm_vshrntq_n_u32(__a, __b, __imm) +#define vmlaldavaq_u32(__a, __b, __c) __arm_vmlaldavaq_u32(__a, __b, __c) +#define vmlaldavq_p_u32(__a, __b, __p) __arm_vmlaldavq_p_u32(__a, __b, __p) +#define vmovlbq_m_u16(__inactive, __a, __p) __arm_vmovlbq_m_u16(__inactive, __a, __p) +#define vmovltq_m_u16(__inactive, __a, __p) __arm_vmovltq_m_u16(__inactive, __a, __p) +#define vmovnbq_m_u32(__a, __b, __p) __arm_vmovnbq_m_u32(__a, __b, __p) +#define vmovntq_m_u32(__a, __b, __p) __arm_vmovntq_m_u32(__a, __b, __p) +#define vqmovnbq_m_u32(__a, __b, __p) __arm_vqmovnbq_m_u32(__a, __b, __p) +#define vqmovntq_m_u32(__a, __b, __p) __arm_vqmovntq_m_u32(__a, __b, __p) +#define vrev32q_m_u16(__inactive, __a, __p) __arm_vrev32q_m_u16(__inactive, __a, __p) #endif __extension__ extern __inline void @@ -6755,1063 +6954,2457 @@ __arm_vpselq_s64 (int64x2_t __a, int64x2_t __b, mve_pred16_t __p) { return __builtin_mve_vpselq_sv2di (__a, __b, __p); } -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -__extension__ extern __inline void +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +__arm_vrmlaldavhaxq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv8hf (__addr, __rv.__o); + return __builtin_mve_vrmlaldavhaxq_sv4si (__a, __b, __c); } -__extension__ extern __inline void +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +__arm_vrmlsldavhaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv4sf (__addr, __rv.__o); + return __builtin_mve_vrmlsldavhaq_sv4si (__a, __b, __c); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f16 (float16x8_t __a) +__arm_vrmlsldavhaxq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - return __builtin_mve_vrndxq_fv8hf (__a); + return __builtin_mve_vrmlsldavhaxq_sv4si (__a, __b, __c); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f32 (float32x4_t __a) +__arm_vaddlvaq_p_s32 (int64_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndxq_fv4sf (__a); + return __builtin_mve_vaddlvaq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f16 (float16x8_t __a) +__arm_vrev16q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vrndq_fv8hf (__a); + return __builtin_mve_vrev16q_m_sv16qi (__inactive, __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f32 (float32x4_t __a) +__arm_vrmlaldavhq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndq_fv4sf (__a); + return __builtin_mve_vrmlaldavhq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f16 (float16x8_t __a) +__arm_vrmlaldavhxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndpq_fv8hf (__a); + return __builtin_mve_vrmlaldavhxq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f32 (float32x4_t __a) +__arm_vrmlsldavhq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndpq_fv4sf (__a); + return __builtin_mve_vrmlsldavhq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f16 (float16x8_t __a) +__arm_vrmlsldavhxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndnq_fv8hf (__a); + return __builtin_mve_vrmlsldavhxq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f32 (float32x4_t __a) +__arm_vaddlvaq_p_u32 (uint64_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndnq_fv4sf (__a); + return __builtin_mve_vaddlvaq_p_uv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f16 (float16x8_t __a) +__arm_vrev16q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vrndmq_fv8hf (__a); + return __builtin_mve_vrev16q_m_uv16qi (__inactive, __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f32 (float32x4_t __a) +__arm_vrmlaldavhq_p_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndmq_fv4sf (__a); + return __builtin_mve_vrmlaldavhq_p_uv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f16 (float16x8_t __a) +__arm_vmvnq_m_n_s16 (int16x8_t __inactive, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndaq_fv8hf (__a); + return __builtin_mve_vmvnq_m_n_sv8hi (__inactive, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f32 (float32x4_t __a) +__arm_vorrq_m_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndaq_fv4sf (__a); + return __builtin_mve_vorrq_m_n_sv8hi (__a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f16 (float16x8_t __a) +__arm_vqrshrntq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vrev64q_fv8hf (__a); + return __builtin_mve_vqrshrntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f32 (float32x4_t __a) +__arm_vqshrnbq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vrev64q_fv4sf (__a); + return __builtin_mve_vqshrnbq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f16 (float16x8_t __a) +__arm_vqshrntq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vnegq_fv8hf (__a); + return __builtin_mve_vqshrntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f32 (float32x4_t __a) +__arm_vrshrnbq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vnegq_fv4sf (__a); + return __builtin_mve_vrshrnbq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f16 (float16_t __a) +__arm_vrshrntq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vdupq_n_fv8hf (__a); + return __builtin_mve_vrshrntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f32 (float32_t __a) +__arm_vshrnbq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vdupq_n_fv4sf (__a); + return __builtin_mve_vshrnbq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f16 (float16x8_t __a) +__arm_vshrntq_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vabsq_fv8hf (__a); + return __builtin_mve_vshrntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f32 (float32x4_t __a) +__arm_vmlaldavaq_s16 (int64_t __a, int16x8_t __b, int16x8_t __c) { - return __builtin_mve_vabsq_fv4sf (__a); + return __builtin_mve_vmlaldavaq_sv8hi (__a, __b, __c); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_f16 (float16x8_t __a) +__arm_vmlaldavaxq_s16 (int64_t __a, int16x8_t __b, int16x8_t __c) { - return __builtin_mve_vrev32q_fv8hf (__a); + return __builtin_mve_vmlaldavaxq_sv8hi (__a, __b, __c); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_f32_f16 (float16x8_t __a) +__arm_vmlsldavaq_s16 (int64_t __a, int16x8_t __b, int16x8_t __c) { - return __builtin_mve_vcvttq_f32_f16v4sf (__a); + return __builtin_mve_vmlsldavaq_sv8hi (__a, __b, __c); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_f32_f16 (float16x8_t __a) +__arm_vmlsldavaxq_s16 (int64_t __a, int16x8_t __b, int16x8_t __c) { - return __builtin_mve_vcvtbq_f32_f16v4sf (__a); + return __builtin_mve_vmlsldavaxq_sv8hi (__a, __b, __c); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_s16 (int16x8_t __a) +__arm_vmlaldavq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_sv8hf (__a); + return __builtin_mve_vmlaldavq_p_sv8hi (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_s32 (int32x4_t __a) +__arm_vmlaldavxq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_sv4sf (__a); + return __builtin_mve_vmlaldavxq_p_sv8hi (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_u16 (uint16x8_t __a) +__arm_vmlsldavq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_uv8hf (__a); + return __builtin_mve_vmlsldavq_p_sv8hi (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_u32 (uint32x4_t __a) +__arm_vmlsldavxq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_uv4sf (__a); + return __builtin_mve_vmlsldavxq_p_sv8hi (__a, __b, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s16_f16 (float16x8_t __a) +__arm_vmovlbq_m_s8 (int16x8_t __inactive, int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_sv8hi (__a); + return __builtin_mve_vmovlbq_m_sv16qi (__inactive, __a, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s32_f32 (float32x4_t __a) +__arm_vmovltq_m_s8 (int16x8_t __inactive, int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_sv4si (__a); + return __builtin_mve_vmovltq_m_sv16qi (__inactive, __a, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u16_f16 (float16x8_t __a) +__arm_vmovnbq_m_s16 (int8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_uv8hi (__a); + return __builtin_mve_vmovnbq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u32_f32 (float32x4_t __a) +__arm_vmovntq_m_s16 (int8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_uv4si (__a); + return __builtin_mve_vmovntq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u16_f16 (float16x8_t __a) +__arm_vqmovnbq_m_s16 (int8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_uv8hi (__a); + return __builtin_mve_vqmovnbq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u32_f32 (float32x4_t __a) +__arm_vqmovntq_m_s16 (int8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_uv4si (__a); + return __builtin_mve_vqmovntq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_u16_f16 (float16x8_t __a) +__arm_vrev32q_m_s8 (int8x16_t __inactive, int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_uv8hi (__a); + return __builtin_mve_vrev32q_m_sv16qi (__inactive, __a, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u16_f16 (float16x8_t __a) +__arm_vmvnq_m_n_u16 (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_uv8hi (__a); + return __builtin_mve_vmvnq_m_n_uv8hi (__inactive, __imm, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u32_f32 (float32x4_t __a) +__arm_vorrq_m_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_uv4si (__a); + return __builtin_mve_vorrq_m_n_uv8hi (__a, __imm, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u16_f16 (float16x8_t __a) +__arm_vqrshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vcvtaq_uv8hi (__a); + return __builtin_mve_vqrshruntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u32_f32 (float32x4_t __a) +__arm_vqshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vcvtaq_uv4si (__a); + return __builtin_mve_vqshrunbq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s16_f16 (float16x8_t __a) +__arm_vqshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) { - return __builtin_mve_vcvtaq_sv8hi (__a); + return __builtin_mve_vqshruntq_n_sv8hi (__a, __b, __imm); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s32_f32 (float32x4_t __a) +__arm_vqmovunbq_m_s16 (uint8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_sv4si (__a); + return __builtin_mve_vqmovunbq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s16_f16 (float16x8_t __a) +__arm_vqmovuntq_m_s16 (uint8x16_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_sv8hi (__a); + return __builtin_mve_vqmovuntq_m_sv8hi (__a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s32_f32 (float32x4_t __a) +__arm_vqrshrntq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vcvtnq_sv4si (__a); + return __builtin_mve_vqrshrntq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s16_f16 (float16x8_t __a) +__arm_vqshrnbq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vcvtpq_sv8hi (__a); + return __builtin_mve_vqshrnbq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s32_f32 (float32x4_t __a) +__arm_vqshrntq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vcvtpq_sv4si (__a); + return __builtin_mve_vqshrntq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s16_f16 (float16x8_t __a) +__arm_vrshrnbq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vcvtmq_sv8hi (__a); + return __builtin_mve_vrshrnbq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s32_f32 (float32x4_t __a) +__arm_vrshrntq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vcvtmq_sv4si (__a); + return __builtin_mve_vrshrntq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vshrnbq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vsubq_n_fv8hf (__a, __b); + return __builtin_mve_vshrnbq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vshrntq_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm) { - return __builtin_mve_vsubq_n_fv4sf (__a, __b); + return __builtin_mve_vshrntq_n_uv8hi (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +__arm_vmlaldavaq_u16 (uint64_t __a, uint16x8_t __b, uint16x8_t __c) { - return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); + return __builtin_mve_vmlaldavaq_uv8hi (__a, __b, __c); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +__arm_vmlaldavq_p_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); + return __builtin_mve_vmlaldavq_p_uv8hi (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +__arm_vmovlbq_m_u8 (uint16x8_t __inactive, uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); + return __builtin_mve_vmovlbq_m_uv16qi (__inactive, __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +__arm_vmovltq_m_u8 (uint16x8_t __inactive, uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); + return __builtin_mve_vmovltq_m_uv16qi (__inactive, __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +__arm_vmovnbq_m_u16 (uint8x16_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); + return __builtin_mve_vmovnbq_m_uv8hi (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +__arm_vmovntq_m_u16 (uint8x16_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); + return __builtin_mve_vmovntq_m_uv8hi (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +__arm_vqmovnbq_m_u16 (uint8x16_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcreateq_fv8hf (__a, __b); + return __builtin_mve_vqmovnbq_m_uv8hi (__a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +__arm_vqmovntq_m_u16 (uint8x16_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcreateq_fv4sf (__a, __b); + return __builtin_mve_vqmovntq_m_uv8hi (__a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +__arm_vrev32q_m_u8 (uint8x16_t __inactive, uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); + return __builtin_mve_vrev32q_m_uv16qi (__inactive, __a, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +__arm_vmvnq_m_n_s32 (int32x4_t __inactive, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); + return __builtin_mve_vmvnq_m_n_sv4si (__inactive, __imm, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +__arm_vorrq_m_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); + return __builtin_mve_vorrq_m_n_sv4si (__a, __imm, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +__arm_vqrshrntq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); + return __builtin_mve_vqrshrntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vqshrnbq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpneq_n_fv8hf (__a, __b); + return __builtin_mve_vqshrnbq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqshrntq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpneq_fv8hf (__a, __b); + return __builtin_mve_vqshrntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b) -{ - return __builtin_mve_vcmpltq_n_fv8hf (__a, __b); -} - -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vrshrnbq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpltq_fv8hf (__a, __b); + return __builtin_mve_vrshrnbq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vrshrntq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpleq_n_fv8hf (__a, __b); + return __builtin_mve_vrshrntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vshrnbq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpleq_fv8hf (__a, __b); + return __builtin_mve_vshrnbq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vshrntq_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b); + return __builtin_mve_vshrntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlaldavaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - return __builtin_mve_vcmpgtq_fv8hf (__a, __b); + return __builtin_mve_vmlaldavaq_sv4si (__a, __b, __c); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmlaldavaxq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b); + return __builtin_mve_vmlaldavaxq_sv4si (__a, __b, __c); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlsldavaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - return __builtin_mve_vcmpgeq_fv8hf (__a, __b); + return __builtin_mve_vmlsldavaq_sv4si (__a, __b, __c); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmlsldavaxq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) { - return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b); + return __builtin_mve_vmlsldavaxq_sv4si (__a, __b, __c); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlaldavq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_fv8hf (__a, __b); + return __builtin_mve_vmlaldavq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlaldavxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_fv8hf (__a, __b); + return __builtin_mve_vmlaldavxq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlsldavq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vorrq_fv8hf (__a, __b); + return __builtin_mve_vmlsldavq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmlsldavxq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vornq_fv8hf (__a, __b); + return __builtin_mve_vmlsldavxq_p_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmovlbq_m_s16 (int32x4_t __inactive, int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vmulq_n_fv8hf (__a, __b); + return __builtin_mve_vmovlbq_m_sv8hi (__inactive, __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmovltq_m_s16 (int32x4_t __inactive, int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vmulq_fv8hf (__a, __b); + return __builtin_mve_vmovltq_m_sv8hi (__inactive, __a, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b) +__arm_vmovnbq_m_s32 (int16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmvq_fv8hf (__a, __b); + return __builtin_mve_vmovnbq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmovntq_m_s32 (int16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmq_fv8hf (__a, __b); + return __builtin_mve_vmovntq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b) +__arm_vqmovnbq_m_s32 (int16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmavq_fv8hf (__a, __b); + return __builtin_mve_vqmovnbq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqmovntq_m_s32 (int16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmaq_fv8hf (__a, __b); + return __builtin_mve_vqmovntq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b) +__arm_vrev32q_m_s16 (int16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vmaxnmvq_fv8hf (__a, __b); + return __builtin_mve_vrev32q_m_sv8hi (__inactive, __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmvnq_m_n_u32 (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vmaxnmq_fv8hf (__a, __b); + return __builtin_mve_vmvnq_m_n_uv4si (__inactive, __imm, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b) +__arm_vorrq_m_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vmaxnmavq_fv8hf (__a, __b); + return __builtin_mve_vorrq_m_n_uv4si (__a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqrshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vmaxnmaq_fv8hf (__a, __b); + return __builtin_mve_vqrshruntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_veorq_fv8hf (__a, __b); + return __builtin_mve_vqshrunbq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) { - return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); + return __builtin_mve_vqshruntq_n_sv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqmovunbq_m_s32 (uint16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); + return __builtin_mve_vqmovunbq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqmovuntq_m_s32 (uint16x8_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); + return __builtin_mve_vqmovuntq_m_sv4si (__a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqrshrntq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vcmulq_fv8hf (__a, __b); + return __builtin_mve_vqrshrntq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqshrnbq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); + return __builtin_mve_vqshrnbq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) +__arm_vqshrntq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); + return __builtin_mve_vqshrntq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vrshrnbq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vbicq_fv8hf (__a, __b); + return __builtin_mve_vrshrnbq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vrshrntq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vandq_fv8hf (__a, __b); + return __builtin_mve_vrshrntq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vshrnbq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vaddq_n_fv8hf (__a, __b); + return __builtin_mve_vshrnbq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vshrntq_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm) { - return __builtin_mve_vabdq_fv8hf (__a, __b); + return __builtin_mve_vshrntq_n_uv4si (__a, __b, __imm); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmlaldavaq_u32 (uint64_t __a, uint32x4_t __b, uint32x4_t __c) { - return __builtin_mve_vcmpneq_n_fv4sf (__a, __b); + return __builtin_mve_vmlaldavaq_uv4si (__a, __b, __c); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmlaldavq_p_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_fv4sf (__a, __b); + return __builtin_mve_vmlaldavq_p_uv4si (__a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmovlbq_m_u16 (uint32x4_t __inactive, uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_n_fv4sf (__a, __b); + return __builtin_mve_vmovlbq_m_uv8hi (__inactive, __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmovltq_m_u16 (uint32x4_t __inactive, uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_fv4sf (__a, __b); + return __builtin_mve_vmovltq_m_uv8hi (__inactive, __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmovnbq_m_u32 (uint16x8_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_n_fv4sf (__a, __b); + return __builtin_mve_vmovnbq_m_uv4si (__a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmovntq_m_u32 (uint16x8_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_fv4sf (__a, __b); + return __builtin_mve_vmovntq_m_uv4si (__a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vqmovnbq_m_u32 (uint16x8_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b); + return __builtin_mve_vqmovnbq_m_uv4si (__a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vqmovntq_m_u32 (uint16x8_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_fv4sf (__a, __b); + return __builtin_mve_vqmovntq_m_uv4si (__a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vrev32q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b); + return __builtin_mve_vrev32q_m_uv8hi (__inactive, __a, __p); } +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) { - return __builtin_mve_vcmpgeq_fv4sf (__a, __b); + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hf (__addr, __rv.__o); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) { - return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b); + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4sf (__addr, __rv.__o); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndxq_f16 (float16x8_t __a) { - return __builtin_mve_vcmpeqq_fv4sf (__a, __b); + return __builtin_mve_vrndxq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndxq_f32 (float32x4_t __a) { - return __builtin_mve_vsubq_fv4sf (__a, __b); + return __builtin_mve_vrndxq_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndq_f16 (float16x8_t __a) { - return __builtin_mve_vorrq_fv4sf (__a, __b); + return __builtin_mve_vrndq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndq_f32 (float32x4_t __a) { - return __builtin_mve_vornq_fv4sf (__a, __b); + return __builtin_mve_vrndq_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vrndpq_f16 (float16x8_t __a) { - return __builtin_mve_vmulq_n_fv4sf (__a, __b); + return __builtin_mve_vrndpq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndpq_f32 (float32x4_t __a) { - return __builtin_mve_vmulq_fv4sf (__a, __b); + return __builtin_mve_vrndpq_fv4sf (__a); } -__extension__ extern __inline float32_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b) +__arm_vrndnq_f16 (float16x8_t __a) { - return __builtin_mve_vminnmvq_fv4sf (__a, __b); + return __builtin_mve_vrndnq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndnq_f32 (float32x4_t __a) { - return __builtin_mve_vminnmq_fv4sf (__a, __b); + return __builtin_mve_vrndnq_fv4sf (__a); } -__extension__ extern __inline float32_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b) +__arm_vrndmq_f16 (float16x8_t __a) { - return __builtin_mve_vminnmavq_fv4sf (__a, __b); + return __builtin_mve_vrndmq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndmq_f32 (float32x4_t __a) { - return __builtin_mve_vminnmaq_fv4sf (__a, __b); + return __builtin_mve_vrndmq_fv4sf (__a); } -__extension__ extern __inline float32_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b) +__arm_vrndaq_f16 (float16x8_t __a) { - return __builtin_mve_vmaxnmvq_fv4sf (__a, __b); + return __builtin_mve_vrndaq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrndaq_f32 (float32x4_t __a) { - return __builtin_mve_vmaxnmq_fv4sf (__a, __b); + return __builtin_mve_vrndaq_fv4sf (__a); } -__extension__ extern __inline float32_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b) +__arm_vrev64q_f16 (float16x8_t __a) { - return __builtin_mve_vmaxnmavq_fv4sf (__a, __b); + return __builtin_mve_vrev64q_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrev64q_f32 (float32x4_t __a) { - return __builtin_mve_vmaxnmaq_fv4sf (__a, __b); + return __builtin_mve_vrev64q_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vnegq_f16 (float16x8_t __a) { - return __builtin_mve_veorq_fv4sf (__a, __b); + return __builtin_mve_vnegq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) +__arm_vnegq_f32 (float32x4_t __a) { - return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); + return __builtin_mve_vnegq_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) +__arm_vdupq_n_f16 (float16_t __a) { - return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); + return __builtin_mve_vdupq_n_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) +__arm_vdupq_n_f32 (float32_t __a) { - return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); + return __builtin_mve_vdupq_n_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vabsq_f16 (float16x8_t __a) { - return __builtin_mve_vcmulq_fv4sf (__a, __b); + return __builtin_mve_vabsq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) +__arm_vabsq_f32 (float32x4_t __a) { - return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); + return __builtin_mve_vabsq_fv4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) +__arm_vrev32q_f16 (float16x8_t __a) { - return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); + return __builtin_mve_vrev32q_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcvttq_f32_f16 (float16x8_t __a) { - return __builtin_mve_vbicq_fv4sf (__a, __b); + return __builtin_mve_vcvttq_f32_f16v4sf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcvtbq_f32_f16 (float16x8_t __a) { - return __builtin_mve_vandq_fv4sf (__a, __b); + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vcvtq_f16_s16 (int16x8_t __a) { - return __builtin_mve_vaddq_n_fv4sf (__a, __b); + return __builtin_mve_vcvtq_to_f_sv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcvtq_f32_s32 (int32x4_t __a) { - return __builtin_mve_vabdq_fv4sf (__a, __b); + return __builtin_mve_vcvtq_to_f_sv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b) +__arm_vcvtq_f16_u16 (uint16x8_t __a) { - return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b); + return __builtin_mve_vcvtq_to_f_uv8hf (__a); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) +__arm_vcvtq_f32_u32 (uint32x4_t __a) { - return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); + return __builtin_mve_vcvtq_to_f_uv4sf (__a); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vcvtq_s16_f16 (float16x8_t __a) { - return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vcvtq_from_f_sv8hi (__a); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vcvtq_s32_f32 (float32x4_t __a) { - return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vcvtq_from_f_sv4si (__a); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vcvtq_u16_f16 (float16x8_t __a) { - return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p); + return __builtin_mve_vcvtq_from_f_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv4si (__a); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vcvtpq_u16_f16 (float16x8_t __a) { - return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p); + return __builtin_mve_vcvtpq_uv8hi (__a); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vcvtpq_u32_f32 (float32x4_t __a) { - return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p); + return __builtin_mve_vcvtpq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_uv8hi (__a); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vcvtmq_u32_f32 (float32x4_t __a) { - return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p); + return __builtin_mve_vcvtmq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_uv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtnq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_sv4si (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) { - return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p); + return __builtin_mve_vsubq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vsubq_n_fv4sf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) { - return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p); + return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) { - return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p); + return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) { - return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p); + return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); } -#endif +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); +} -enum { - __ARM_mve_type_float16_t = 1, - __ARM_mve_type_float16_t_ptr, - __ARM_mve_type_float16_t_const_ptr, - __ARM_mve_type_float16x8_t, - __ARM_mve_type_float16x8x2_t, - __ARM_mve_type_float16x8x4_t, - __ARM_mve_type_float32_t, - __ARM_mve_type_float32_t_ptr, - __ARM_mve_type_float32_t_const_ptr, - __ARM_mve_type_float32x4_t, - __ARM_mve_type_float32x4x2_t, - __ARM_mve_type_float32x4x4_t, - __ARM_mve_type_int16_t, - __ARM_mve_type_int16_t_ptr, - __ARM_mve_type_int16_t_const_ptr, - __ARM_mve_type_int16x8_t, - __ARM_mve_type_int16x8x2_t, - __ARM_mve_type_int16x8x4_t, - __ARM_mve_type_int32_t, - __ARM_mve_type_int32_t_ptr, - __ARM_mve_type_int32_t_const_ptr, - __ARM_mve_type_int32x4_t, - __ARM_mve_type_int32x4x2_t, - __ARM_mve_type_int32x4x4_t, - __ARM_mve_type_int64_t, - __ARM_mve_type_int64_t_ptr, +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv4sf (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpneq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpneq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpltq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpltq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpleq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpleq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgtq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgeq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpeqq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vsubq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vorrq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vornq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vmulq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_veorq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vbicq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vandq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vaddq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vabdq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpneq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpneq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpltq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpltq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpleq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpleq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgtq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgeq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpeqq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vsubq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vorrq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vornq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vmulq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_veorq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vbicq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vandq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vaddq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vabdq_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p); +} + + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcvtbq_m_f16_f32v8hf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtbq_m_f32_f16v4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcvttq_m_f16_f32v8hf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vfmaq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +{ + return __builtin_mve_vfmaq_n_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +{ + return __builtin_mve_vfmasq_n_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vfmsq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndaq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndmq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndnq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndpq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndxq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vfmaq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return __builtin_mve_vfmaq_n_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return __builtin_mve_vfmasq_n_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vfmsq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndaq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndmq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndnq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndpq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndxq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p); +} + +#endif + +enum { + __ARM_mve_type_float16_t = 1, + __ARM_mve_type_float16_t_ptr, + __ARM_mve_type_float16_t_const_ptr, + __ARM_mve_type_float16x8_t, + __ARM_mve_type_float16x8x2_t, + __ARM_mve_type_float16x8x4_t, + __ARM_mve_type_float32_t, + __ARM_mve_type_float32_t_ptr, + __ARM_mve_type_float32_t_const_ptr, + __ARM_mve_type_float32x4_t, + __ARM_mve_type_float32x4x2_t, + __ARM_mve_type_float32x4x4_t, + __ARM_mve_type_int16_t, + __ARM_mve_type_int16_t_ptr, + __ARM_mve_type_int16_t_const_ptr, + __ARM_mve_type_int16x8_t, + __ARM_mve_type_int16x8x2_t, + __ARM_mve_type_int16x8x4_t, + __ARM_mve_type_int32_t, + __ARM_mve_type_int32_t_ptr, + __ARM_mve_type_int32_t_const_ptr, + __ARM_mve_type_int32x4_t, + __ARM_mve_type_int32x4x2_t, + __ARM_mve_type_int32x4x4_t, + __ARM_mve_type_int64_t, + __ARM_mve_type_int64_t_ptr, __ARM_mve_type_int64_t_const_ptr, __ARM_mve_type_int64x2_t, __ARM_mve_type_int8_t, @@ -7845,1497 +9438,2115 @@ enum { __ARM_mve_unsupported_type }; -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -#define __ARM_mve_typeid(x) _Generic(x, \ - float16_t: __ARM_mve_type_float16_t, \ - float16_t *: __ARM_mve_type_float16_t_ptr, \ - float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ - float16x8_t: __ARM_mve_type_float16x8_t, \ - float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ - float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ - float32_t: __ARM_mve_type_float32_t, \ - float32_t *: __ARM_mve_type_float32_t_ptr, \ - float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ - float32x4_t: __ARM_mve_type_float32x4_t, \ - float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ - float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ - int16_t: __ARM_mve_type_int16_t, \ - int16_t *: __ARM_mve_type_int16_t_ptr, \ - int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ - int16x8_t: __ARM_mve_type_int16x8_t, \ - int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ - int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ - int32_t: __ARM_mve_type_int32_t, \ - int32_t *: __ARM_mve_type_int32_t_ptr, \ - int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ - int32x4_t: __ARM_mve_type_int32x4_t, \ - int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ - int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ - int64_t: __ARM_mve_type_int64_t, \ - int64_t *: __ARM_mve_type_int64_t_ptr, \ - int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ - int64x2_t: __ARM_mve_type_int64x2_t, \ - int8_t: __ARM_mve_type_int8_t, \ - int8_t *: __ARM_mve_type_int8_t_ptr, \ - int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ - int8x16_t: __ARM_mve_type_int8x16_t, \ - int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ - int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ - uint16_t: __ARM_mve_type_uint16_t, \ - uint16_t *: __ARM_mve_type_uint16_t_ptr, \ - uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ - uint16x8_t: __ARM_mve_type_uint16x8_t, \ - uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ - uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ - uint32_t: __ARM_mve_type_uint32_t, \ - uint32_t *: __ARM_mve_type_uint32_t_ptr, \ - uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ - uint32x4_t: __ARM_mve_type_uint32x4_t, \ - uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ - uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ - uint64_t: __ARM_mve_type_uint64_t, \ - uint64_t *: __ARM_mve_type_uint64_t_ptr, \ - uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ - uint64x2_t: __ARM_mve_type_uint64x2_t, \ - uint8_t: __ARM_mve_type_uint8_t, \ - uint8_t *: __ARM_mve_type_uint8_t_ptr, \ - uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ - uint8x16_t: __ARM_mve_type_uint8x16_t, \ - uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ - uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ - default: _Generic(x, \ - signed char: __ARM_mve_type_int8_t, \ - short: __ARM_mve_type_int16_t, \ - int: __ARM_mve_type_int32_t, \ - long: __ARM_mve_type_int32_t, \ - long long: __ARM_mve_type_int64_t, \ - unsigned char: __ARM_mve_type_uint8_t, \ - unsigned short: __ARM_mve_type_uint16_t, \ - unsigned int: __ARM_mve_type_uint32_t, \ - unsigned long: __ARM_mve_type_uint32_t, \ - unsigned long long: __ARM_mve_type_uint64_t, \ - default: __ARM_mve_unsupported_type)) -#else -#define __ARM_mve_typeid(x) _Generic(x, \ - int16_t: __ARM_mve_type_int16_t, \ - int16_t *: __ARM_mve_type_int16_t_ptr, \ - int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ - int16x8_t: __ARM_mve_type_int16x8_t, \ - int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ - int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ - int32_t: __ARM_mve_type_int32_t, \ - int32_t *: __ARM_mve_type_int32_t_ptr, \ - int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ - int32x4_t: __ARM_mve_type_int32x4_t, \ - int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ - int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ - int64_t: __ARM_mve_type_int64_t, \ - int64_t *: __ARM_mve_type_int64_t_ptr, \ - int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ - int64x2_t: __ARM_mve_type_int64x2_t, \ - int8_t: __ARM_mve_type_int8_t, \ - int8_t *: __ARM_mve_type_int8_t_ptr, \ - int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ - int8x16_t: __ARM_mve_type_int8x16_t, \ - int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ - int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ - uint16_t: __ARM_mve_type_uint16_t, \ - uint16_t *: __ARM_mve_type_uint16_t_ptr, \ - uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ - uint16x8_t: __ARM_mve_type_uint16x8_t, \ - uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ - uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ - uint32_t: __ARM_mve_type_uint32_t, \ - uint32_t *: __ARM_mve_type_uint32_t_ptr, \ - uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ - uint32x4_t: __ARM_mve_type_uint32x4_t, \ - uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ - uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ - uint64_t: __ARM_mve_type_uint64_t, \ - uint64_t *: __ARM_mve_type_uint64_t_ptr, \ - uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ - uint64x2_t: __ARM_mve_type_uint64x2_t, \ - uint8_t: __ARM_mve_type_uint8_t, \ - uint8_t *: __ARM_mve_type_uint8_t_ptr, \ - uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ - uint8x16_t: __ARM_mve_type_uint8x16_t, \ - uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ - uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ - default: _Generic(x, \ - signed char: __ARM_mve_type_int8_t, \ - short: __ARM_mve_type_int16_t, \ - int: __ARM_mve_type_int32_t, \ - long: __ARM_mve_type_int32_t, \ - long long: __ARM_mve_type_int64_t, \ - unsigned char: __ARM_mve_type_uint8_t, \ - unsigned short: __ARM_mve_type_uint16_t, \ - unsigned int: __ARM_mve_type_uint32_t, \ - unsigned long: __ARM_mve_type_uint32_t, \ - unsigned long long: __ARM_mve_type_uint64_t, \ - default: __ARM_mve_unsupported_type)) -#endif /* MVE Floating point. */ +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define __ARM_mve_typeid(x) _Generic(x, \ + float16_t: __ARM_mve_type_float16_t, \ + float16_t *: __ARM_mve_type_float16_t_ptr, \ + float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ + float16x8_t: __ARM_mve_type_float16x8_t, \ + float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ + float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ + float32_t: __ARM_mve_type_float32_t, \ + float32_t *: __ARM_mve_type_float32_t_ptr, \ + float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ + float32x4_t: __ARM_mve_type_float32x4_t, \ + float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ + float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#else +#define __ARM_mve_typeid(x) _Generic(x, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#endif /* MVE Floating point. */ + +extern void *__ARM_undef; +#define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) +#define __ARM_mve_coerce1(param, type) \ + _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef) + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vdupq_n(p0) __arm_vdupq_n(p0) +#define __arm_vdupq_n(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vdupq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vdupq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vsubq_n(p0,p1) __arm_vsubq_n(p0,p1) +#define __arm_vsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + +#define vshlq(p0,p1) __arm_vshlq(p0,p1) +#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vshrq(p0,p1) __arm_vshrq(p0,p1) +#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) +#define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_n_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_n_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vsubq_n(p0,p1) __arm_vsubq_n(p0,p1) +#define __arm_vsubq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vsubq(p0,p1) __arm_vsubq(p0,p1) +#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vorrq(p0,p1) __arm_vorrq(p0,p1) +#define __arm_vorrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vabdq(p0,p1) __arm_vabdq(p0,p1) +#define __arm_vabdq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vaddq(p0,p1) __arm_vaddq(p0,p1) +#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vandq(p0,p1) __arm_vandq(p0,p1) +#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vbicq(p0,p1) __arm_vbicq(p0,p1) +#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vornq(p0,p1) __arm_vornq(p0,p1) +#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vmulq_n(p0,p1) __arm_vmulq_n(p0,p1) +#define __arm_vmulq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vmulq(p0,p1) __arm_vmulq(p0,p1) +#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcaddq_rot270(p0,p1) __arm_vcaddq_rot270(p0,p1) +#define __arm_vcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmpeqq(p0,p1) __arm_vcmpeqq(p0,p1) +#define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcaddq_rot90(p0,p1) __arm_vcaddq_rot90(p0,p1) +#define __arm_vcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -extern void *__ARM_undef; -#define __ARM_mve_coerce(param, type) \ - _Generic(param, type: param, default: *(type *)__ARM_undef) +#define vcmpgeq_n(p0,p1) __arm_vcmpgeq_n(p0,p1) +#define __arm_vcmpgeq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) +#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vst4q(p0,p1) __arm_vst4q(p0,p1) -#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndxq(p0) __arm_vrndxq(p0) -#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vcmpleq(p0,p1) __arm_vcmpleq(p0,p1) +#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpltq(p0,p1) __arm_vcmpltq(p0,p1) +#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + +#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) +#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq(p0,p1) __arm_vcmulq(p0,p1) +#define __arm_vcmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vcmulq_rot180(p0,p1) __arm_vcmulq_rot180(p0,p1) +#define __arm_vcmulq_rot180(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndq(p0) __arm_vrndq(p0) -#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vcmulq_rot270(p0,p1) __arm_vcmulq_rot270(p0,p1) +#define __arm_vcmulq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndpq(p0) __arm_vrndpq(p0) -#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vcmulq_rot90(p0,p1) __arm_vcmulq_rot90(p0,p1) +#define __arm_vcmulq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndnq(p0) __arm_vrndnq(p0) -#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define veorq(p0,p1) __arm_veorq(p0,p1) +#define __arm_veorq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndmq(p0) __arm_vrndmq(p0) -#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmaxnmaq(p0,p1) __arm_vmaxnmaq(p0,p1) +#define __arm_vmaxnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrndaq(p0) __arm_vrndaq(p0) -#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmaxnmavq(p0,p1) __arm_vmaxnmavq(p0,p1) +#define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrev64q(p0) __arm_vrev64q(p0) -#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmaxnmq(p0,p1) __arm_vmaxnmq(p0,p1) +#define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vnegq(p0) __arm_vnegq(p0) -#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) +#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vdupq_n(p0) __arm_vdupq_n(p0) -#define __arm_vdupq_n(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vdupq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vdupq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) +#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vabsq(p0) __arm_vabsq(p0) -#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vminnmaq(p0,p1) __arm_vminnmaq(p0,p1) +#define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrev32q(p0) __arm_vrev32q(p0) -#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vminnmavq(p0,p1) __arm_vminnmavq(p0,p1) +#define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) -#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) +#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) -#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) -#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vminnmq(p0,p1) __arm_vminnmq(p0,p1) +#define __arm_vminnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vrev16q(p0) __arm_vrev16q(p0) -#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) +#define vsubq(p0,p1) __arm_vsubq(p0,p1) +#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vqabsq(p0) __arm_vqabsq(p0) -#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vminnmvq(p0,p1) __arm_vminnmvq(p0,p1) +#define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) -#define vqnegq(p0) __arm_vqnegq(p0) -#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#define vmvnq(p0) __arm_vmvnq(p0) -#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_r(p0,p1) __arm_vshlq_r(p0,p1) +#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vmovlbq(p0) __arm_vmovlbq(p0) -#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_n(p0,p1) __arm_vshlq_n(p0,p1) +#define __arm_vshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vmovltq(p0) __arm_vmovltq(p0) -#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vshlltq(p0,p1) __arm_vshlltq(p0,p1) +#define __arm_vshlltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) -#define vclzq(p0) __arm_vclzq(p0) -#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vshllbq(p0,p1) __arm_vshllbq(p0,p1) +#define __arm_vshllbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) -#define vclsq(p0) __arm_vclsq(p0) -#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) +#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vcvtq(p0) __arm_vcvtq(p0) -#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) +#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vsubq(p0,p1) __arm_vsubq(p0,p1) -#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) +#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vshlq(p0,p1) __arm_vshlq(p0,p1) -#define __arm_vshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrmulhq(p0,p1) __arm_vrmulhq(p0,p1) +#define __arm_vrmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vshrq(p0,p1) __arm_vshrq(p0,p1) -#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrhaddq(p0,p1) __arm_vrhaddq(p0,p1) +#define __arm_vrhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) +#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqshluq(p0,p1) __arm_vqshluq(p0,p1) +#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) -#define vcvtq_n(p0,p1) __arm_vcvtq_n(p0,p1) -#define __arm_vcvtq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqshlq(p0,p1) __arm_vqshlq(p0,p1) +#define __arm_vqshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqshlq_r(p0,p1) __arm_vqshlq_r(p0,p1) +#define __arm_vqshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_n_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_n_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_n_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_n_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) -#define vorrq(p0,p1) __arm_vorrq(p0,p1) -#define __arm_vorrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqshlq_n(p0,p1) __arm_vqshlq_n(p0,p1) +#define __arm_vqshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + +#define vqrshlq(p0,p1) __arm_vqrshlq(p0,p1) +#define __arm_vqrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) -#define vabdq(p0,p1) __arm_vabdq(p0,p1) -#define __arm_vabdq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmulhq(p0,p1) __arm_vqrdmulhq(p0,p1) +#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) -#define vaddq(p0,p1) __arm_vaddq(p0,p1) -#define __arm_vaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmlaldavxq(p0,p1) __arm_vmlaldavxq(p0,p1) +#define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vandq(p0,p1) __arm_vandq(p0,p1) -#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovuntq(p0,p1) __arm_vqmovuntq(p0,p1) +#define __arm_vqmovuntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +#define vqmovntq(p0,p1) __arm_vqmovntq(p0,p1) +#define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vqmovnbq(p0,p1) __arm_vqmovnbq(p0,p1) +#define __arm_vqmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vbicq(p0,p1) __arm_vbicq(p0,p1) -#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmulltq(p0,p1) __arm_vqdmulltq(p0,p1) +#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vornq(p0,p1) __arm_vornq(p0,p1) -#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovunbq(p0,p1) __arm_vqmovunbq(p0,p1) +#define __arm_vqmovunbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vmulq_n(p0,p1) __arm_vmulq_n(p0,p1) -#define __arm_vmulq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmullbq(p0,p1) __arm_vqdmullbq(p0,p1) +#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vmulq(p0,p1) __arm_vmulq(p0,p1) -#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmulhq(p0,p1) __arm_vqdmulhq(p0,p1) +#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcaddq_rot270(p0,p1) __arm_vcaddq_rot270(p0,p1) -#define __arm_vcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) +#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmpeqq(p0,p1) __arm_vcmpeqq(p0,p1) -#define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmulltq_poly(p0,p1) __arm_vmulltq_poly(p0,p1) +#define __arm_vmulltq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) -#define vcaddq_rot90(p0,p1) __arm_vcaddq_rot90(p0,p1) -#define __arm_vcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmullbq_poly(p0,p1) __arm_vmullbq_poly(p0,p1) +#define __arm_vmullbq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) -#define vcmpgeq_n(p0,p1) __arm_vcmpgeq_n(p0,p1) -#define __arm_vcmpgeq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmulltq_int(p0,p1) __arm_vmulltq_int(p0,p1) +#define __arm_vmulltq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) -#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) +#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) -#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vhcaddq_rot270(p0,p1) __arm_vhcaddq_rot270(p0,p1) +#define __arm_vhcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcmpleq(p0,p1) __arm_vcmpleq(p0,p1) -#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vhcaddq_rot90(p0,p1) __arm_vhcaddq_rot90(p0,p1) +#define __arm_vhcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcmpltq(p0,p1) __arm_vcmpltq(p0,p1) -#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) +#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmpneq(p0,p1) __arm_vcmpneq(p0,p1) -#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vminq(p0,p1) __arm_vminq(p0,p1) +#define __arm_vminq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmulq(p0,p1) __arm_vcmulq(p0,p1) -#define __arm_vcmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vminaq(p0,p1) __arm_vminaq(p0,p1) +#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcmulq_rot180(p0,p1) __arm_vcmulq_rot180(p0,p1) -#define __arm_vcmulq_rot180(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxq(p0,p1) __arm_vmaxq(p0,p1) +#define __arm_vmaxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vcmulq_rot270(p0,p1) __arm_vcmulq_rot270(p0,p1) -#define __arm_vcmulq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxaq(p0,p1) __arm_vmaxaq(p0,p1) +#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) -#define vcmulq_rot90(p0,p1) __arm_vcmulq_rot90(p0,p1) -#define __arm_vcmulq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovntq(p0,p1) __arm_vmovntq(p0,p1) +#define __arm_vmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define veorq(p0,p1) __arm_veorq(p0,p1) -#define __arm_veorq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovnbq(p0,p1) __arm_vmovnbq(p0,p1) +#define __arm_vmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vmaxnmaq(p0,p1) __arm_vmaxnmaq(p0,p1) -#define __arm_vmaxnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmulhq(p0,p1) __arm_vmulhq(p0,p1) +#define __arm_vmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vmaxnmavq(p0,p1) __arm_vmaxnmavq(p0,p1) -#define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmullbq_int(p0,p1) __arm_vmullbq_int(p0,p1) +#define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) -#define vmaxnmq(p0,p1) __arm_vmaxnmq(p0,p1) -#define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) -#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) +#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) +#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vmaxnmvq(p0,p1) __arm_vmaxnmvq(p0,p1) -#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) +#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vminnmaq(p0,p1) __arm_vminnmaq(p0,p1) -#define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) +#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vclsq_m(p0,p1,p2) __arm_vclsq_m(p0,p1,p2) +#define __arm_vclsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vminnmavq(p0,p1) __arm_vminnmavq(p0,p1) -#define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vclzq_m(p0,p1,p2) __arm_vclzq_m(p0,p1,p2) +#define __arm_vclzq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) - -#define vbrsrq(p0,p1) __arm_vbrsrq(p0,p1) -#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclzq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclzq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclzq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vclzq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vclzq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vclzq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vminnmq(p0,p1) __arm_vminnmq(p0,p1) -#define __arm_vminnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxaq_m(p0,p1,p2) __arm_vmaxaq_m(p0,p1,p2) +#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vminnmvq(p0,p1) __arm_vminnmvq(p0,p1) -#define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vminaq_m(p0,p1,p2) __arm_vminaq_m(p0,p1,p2) +#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) -#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmlaq(p0,p1,p2) __arm_vmlaq(p0,p1,p2) +#define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vshlq_r(p0,p1) __arm_vshlq_r(p0,p1) -#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vsriq(p0,p1,p2) __arm_vsriq(p0,p1,p2) +#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vshlq_n(p0,p1) __arm_vshlq_n(p0,p1) -#define __arm_vshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vsliq(p0,p1,p2) __arm_vsliq(p0,p1,p2) +#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vshlltq(p0,p1) __arm_vshlltq(p0,p1) -#define __arm_vshlltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) +#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define vshllbq(p0,p1) __arm_vshllbq(p0,p1) -#define __arm_vshllbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrshlq_m_n(p0,p1,p2) __arm_vrshlq_m_n(p0,p1,p2) +#define __arm_vrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __p1, p2));}) -#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) -#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqshlq_m_r(p0,p1,p2) __arm_vqshlq_m_r(p0,p1,p2) +#define __arm_vqshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define vrshrq(p0,p1) __arm_vrshrq(p0,p1) -#define __arm_vrshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrshlq_m_n(p0,p1,p2) __arm_vqrshlq_m_n(p0,p1,p2) +#define __arm_vqrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define vrshlq(p0,p1) __arm_vrshlq(p0,p1) -#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmlsdhxq(p0,p1,p2) __arm_vqrdmlsdhxq(p0,p1,p2) +#define __arm_vqrdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vrmulhq(p0,p1) __arm_vrmulhq(p0,p1) -#define __arm_vrmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmlsdhq(p0,p1,p2) __arm_vqrdmlsdhq(p0,p1,p2) +#define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vrhaddq(p0,p1) __arm_vrhaddq(p0,p1) -#define __arm_vrhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmlashq(p0,p1,p2) __arm_vqrdmlashq(p0,p1,p2) +#define __arm_vqrdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlashq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlashq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlashq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vqsubq(p0,p1) __arm_vqsubq(p0,p1) -#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmlahq(p0,p1,p2) __arm_vqrdmlahq(p0,p1,p2) +#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vqshluq(p0,p1) __arm_vqshluq(p0,p1) -#define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshluq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshluq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1));}) +#define vmlasq(p0,p1,p2) __arm_vmlasq(p0,p1,p2) +#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vqshlq(p0,p1) __arm_vqshlq(p0,p1) -#define __arm_vqshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmlahq(p0,p1,p2) __arm_vqdmlahq(p0,p1,p2) +#define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vqshlq_r(p0,p1) __arm_vqshlq_r(p0,p1) -#define __arm_vqshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vqrdmladhxq(p0,p1,p2) __arm_vqrdmladhxq(p0,p1,p2) +#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vqshlq_n(p0,p1) __arm_vqshlq_n(p0,p1) -#define __arm_vqshlq_n(p0,p1) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));}) +#define vqrdmladhq(p0,p1,p2) __arm_vqrdmladhq(p0,p1,p2) +#define __arm_vqrdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vqrshlq(p0,p1) __arm_vqrshlq(p0,p1) -#define __arm_vqrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vqnegq_m(p0,p1,p2) __arm_vqnegq_m(p0,p1,p2) +#define __arm_vqnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqdmlsdhxq(p0,p1,p2) __arm_vqdmlsdhxq(p0,p1,p2) +#define __arm_vqdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmlsdhq(p0,p1,p2) __arm_vqdmlsdhq(p0,p1,p2) +#define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmladhxq(p0,p1,p2) __arm_vqdmladhxq(p0,p1,p2) +#define __arm_vqdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vqdmladhq(p0,p1,p2) __arm_vqdmladhq(p0,p1,p2) +#define __arm_vqdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vqrdmulhq(p0,p1) __arm_vqrdmulhq(p0,p1) -#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovlbq_m(p0,p1,p2) __arm_vmovlbq_m(p0,p1,p2) +#define __arm_vmovlbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vmovlbq_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vmovlbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) -#define vmlaldavxq(p0,p1) __arm_vmlaldavxq(p0,p1) -#define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovnbq_m(p0,p1,p2) __arm_vmovnbq_m(p0,p1,p2) +#define __arm_vmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqmovuntq(p0,p1) __arm_vqmovuntq(p0,p1) -#define __arm_vqmovuntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovntq_m(p0,p1,p2) __arm_vmovntq_m(p0,p1,p2) +#define __arm_vmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqmovntq(p0,p1) __arm_vqmovntq(p0,p1) -#define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmovltq_m(p0,p1,p2) __arm_vmovltq_m(p0,p1,p2) +#define __arm_vmovltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vmovltq_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vmovltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vmovltq_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vmovltq_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) -#define vqmovnbq(p0,p1) __arm_vqmovnbq(p0,p1) -#define __arm_vqmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vshrntq(p0,p1,p2) __arm_vshrntq(p0,p1,p2) +#define __arm_vshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmulltq(p0,p1) __arm_vqdmulltq(p0,p1) -#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vshrnbq(p0,p1,p2) __arm_vshrnbq(p0,p1,p2) +#define __arm_vshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqmovunbq(p0,p1) __arm_vqmovunbq(p0,p1) -#define __arm_vqmovunbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrntq(p0,p1,p2) __arm_vrshrntq(p0,p1,p2) +#define __arm_vrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmullbq(p0,p1) __arm_vqdmullbq(p0,p1) -#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvtaq_m(p0,p1,p2) __arm_vcvtaq_m(p0,p1,p2) +#define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqdmulhq(p0,p1) __arm_vqdmulhq(p0,p1) -#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvtq_m(p0,p1,p2) __arm_vcvtq_m(p0,p1,p2) +#define __arm_vcvtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcvtq_m_f32_u32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqaddq(p0,p1) __arm_vqaddq(p0,p1) -#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vabsq_m(p0,p1,p2) __arm_vabsq_m(p0,p1,p2) +#define __arm_vabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabsq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabsq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmulltq_poly(p0,p1) __arm_vmulltq_poly(p0,p1) -#define __arm_vmulltq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmlaq(p0,p1,p2) __arm_vcmlaq(p0,p1,p2) +#define __arm_vcmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vcmlaq_rot180(p0,p1,p2) __arm_vcmlaq_rot180(p0,p1,p2) +#define __arm_vcmlaq_rot180(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot180_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot180_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vcmlaq_rot270(p0,p1,p2) __arm_vcmlaq_rot270(p0,p1,p2) +#define __arm_vcmlaq_rot270(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot270_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot270_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vcmlaq_rot90(p0,p1,p2) __arm_vcmlaq_rot90(p0,p1,p2) +#define __arm_vcmlaq_rot90(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vcmpeqq_m_n(p0,p1,p2) __arm_vcmpeqq_m_n(p0,p1,p2) +#define __arm_vcmpeqq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vmullbq_poly(p0,p1) __arm_vmullbq_poly(p0,p1) -#define __arm_vmullbq_poly(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrndxq_m(p0,p1,p2) __arm_vrndxq_m(p0,p1,p2) +#define __arm_vrndxq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_p8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_p16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndxq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndxq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmulltq_int(p0,p1) __arm_vmulltq_int(p0,p1) -#define __arm_vmulltq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrndq_m(p0,p1,p2) __arm_vrndq_m(p0,p1,p2) +#define __arm_vrndq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vhaddq(p0,p1) __arm_vhaddq(p0,p1) -#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vrndpq_m(p0,p1,p2) __arm_vrndpq_m(p0,p1,p2) +#define __arm_vrndpq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndpq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndpq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vhcaddq_rot270(p0,p1) __arm_vhcaddq_rot270(p0,p1) -#define __arm_vhcaddq_rot270(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpgtq_m(p0,p1,p2) __arm_vcmpgtq_m(p0,p1,p2) +#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vhcaddq_rot90(p0,p1) __arm_vhcaddq_rot90(p0,p1) -#define __arm_vhcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpleq_m(p0,p1,p2) __arm_vcmpleq_m(p0,p1,p2) +#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vhsubq(p0,p1) __arm_vhsubq(p0,p1) -#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpltq_m(p0,p1,p2) __arm_vcmpltq_m(p0,p1,p2) +#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vminq(p0,p1) __arm_vminq(p0,p1) -#define __arm_vminq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpneq_m(p0,p1,p2) __arm_vcmpneq_m(p0,p1,p2) +#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vminaq(p0,p1) __arm_vminaq(p0,p1) -#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvtbq_m(p0,p1,p2) __arm_vcvtbq_m(p0,p1,p2) +#define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float16x8_t]: __arm_vcvtbq_m_f32_f16 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float32x4_t]: __arm_vcvtbq_m_f16_f32 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmaxq(p0,p1) __arm_vmaxq(p0,p1) -#define __arm_vmaxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvttq_m(p0,p1,p2) __arm_vcvttq_m(p0,p1,p2) +#define __arm_vcvttq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float16x8_t]: __arm_vcvttq_m_f32_f16 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float32x4_t]: __arm_vcvttq_m_f16_f32 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmaxaq(p0,p1) __arm_vmaxaq(p0,p1) -#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvtmq_m(p0,p1,p2) __arm_vcvtmq_m(p0,p1,p2) +#define __arm_vcvtmq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtmq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtmq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtmq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtmq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmovntq(p0,p1) __arm_vmovntq(p0,p1) -#define __arm_vmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vcvtnq_m(p0,p1,p2) __arm_vcvtnq_m(p0,p1,p2) +#define __arm_vcvtnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtnq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtnq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtnq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtnq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vcvtpq_m(p0,p1,p2) __arm_vcvtpq_m(p0,p1,p2) +#define __arm_vcvtpq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtpq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtpq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtpq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtpq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vcmpltq(p0,p1) __arm_vcmpltq(p0,p1) +#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vdupq_m(p0,p1,p2) __arm_vdupq_m(p0,p1,p2) +#define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vdupq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vdupq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vdupq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vdupq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vdupq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) + +#define vfmaq_n(p0,p1,p2) __arm_vfmaq_n(p0,p1,p2) +#define __arm_vfmaq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));}) + +#define vfmaq(p0,p1,p2) __arm_vfmaq(p0,p1,p2) +#define __arm_vfmaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) -#define vmovnbq(p0,p1) __arm_vmovnbq(p0,p1) -#define __arm_vmovnbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vfmasq_n(p0,p1,p2) __arm_vfmasq_n(p0,p1,p2) +#define __arm_vfmasq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));}) -#define vmulhq(p0,p1) __arm_vmulhq(p0,p1) -#define __arm_vmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vfmsq(p0,p1,p2) __arm_vfmsq(p0,p1,p2) +#define __arm_vfmsq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmsq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmsq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) -#define vmullbq_int(p0,p1) __arm_vmullbq_int(p0,p1) -#define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmaq_m(p0,p1,p2) __arm_vmaxnmaq_m(p0,p1,p2) +#define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) -#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmavq_m(p0,p1,p2) __arm_vmaxnmavq_m(p0,p1,p2) +#define __arm_vmaxnmavq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) - -#define vbicq_m_n(p0,p1,p2) __arm_vbicq_m_n(p0,p1,p2) -#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vbicq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vbicq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqrshrnbq(p0,p1,p2) __arm_vqrshrnbq(p0,p1,p2) -#define __arm_vqrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmvq_m(p0,p1,p2) __arm_vmaxnmvq_m(p0,p1,p2) +#define __arm_vmaxnmvq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqrshrunbq(p0,p1,p2) __arm_vqrshrunbq(p0,p1,p2) -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmavq_p(p0,p1,p2) __arm_vmaxnmavq_p(p0,p1,p2) +#define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - -#define vshlcq(p0,p1,p2) __arm_vshlcq(p0,p1,p2) -#define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vclsq_m(p0,p1,p2) __arm_vclsq_m(p0,p1,p2) -#define __arm_vclsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmvq_p(p0,p1,p2) __arm_vmaxnmvq_p(p0,p1,p2) +#define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vclzq_m(p0,p1,p2) __arm_vclzq_m(p0,p1,p2) -#define __arm_vclzq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vminnmaq_m(p0,p1,p2) __arm_vminnmaq_m(p0,p1,p2) +#define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vclzq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vclzq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vclzq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vclzq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vclzq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vclzq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmaxaq_m(p0,p1,p2) __arm_vmaxaq_m(p0,p1,p2) -#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vminnmavq_p(p0,p1,p2) __arm_vminnmavq_p(p0,p1,p2) +#define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vminaq_m(p0,p1,p2) __arm_vminaq_m(p0,p1,p2) -#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vminnmvq_p(p0,p1,p2) __arm_vminnmvq_p(p0,p1,p2) +#define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_float16_t][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce(__p0, float16_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce(__p0, float32_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vmlaq(p0,p1,p2) __arm_vmlaq(p0,p1,p2) -#define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrndnq_m(p0,p1,p2) __arm_vrndnq_m(p0,p1,p2) +#define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndnq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndnq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __p2));}) -#define vsriq(p0,p1,p2) __arm_vsriq(p0,p1,p2) -#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrndaq_m(p0,p1,p2) __arm_vrndaq_m(p0,p1,p2) +#define __arm_vrndaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vsliq(p0,p1,p2) __arm_vsliq(p0,p1,p2) -#define __arm_vsliq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrndmq_m(p0,p1,p2) __arm_vrndmq_m(p0,p1,p2) +#define __arm_vrndmq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - -#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) -#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrndmq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrndmq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vrshlq_m_n(p0,p1,p2) __arm_vrshlq_m_n(p0,p1,p2) -#define __arm_vrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrev64q_m(p0,p1,p2) __arm_vrev64q_m(p0,p1,p2) +#define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __p1, p2));}) - -#define vqshlq_m_r(p0,p1,p2) __arm_vqshlq_m_r(p0,p1,p2) -#define __arm_vqshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev64q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev64q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrev64q_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev64q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev64q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrev64q_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrev64q_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vrev64q_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqrshlq_m_n(p0,p1,p2) __arm_vqrshlq_m_n(p0,p1,p2) -#define __arm_vqrshlq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vqrshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vqrshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vqrshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) +#define vrev32q_m(p0,p1,p2) __arm_vrev32q_m(p0,p1,p2) +#define __arm_vrev32q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev32q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev32q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vrev32q_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2));}) -#define vqrdmlsdhxq(p0,p1,p2) __arm_vqrdmlsdhxq(p0,p1,p2) -#define __arm_vqrdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vpselq(p0,p1,p2) __arm_vpselq(p0,p1,p2) +#define __arm_vpselq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vpselq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vpselq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vpselq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int64x2_t]: __arm_vpselq_s64 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vpselq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vpselq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vpselq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint64x2_t]: __arm_vpselq_u64 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vpselq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vpselq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#define vqrdmlsdhq(p0,p1,p2) __arm_vqrdmlsdhq(p0,p1,p2) -#define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpgeq(p0,p1) __arm_vcmpgeq(p0,p1) +#define __arm_vcmpgeq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#define vqrdmlashq(p0,p1,p2) __arm_vqrdmlashq(p0,p1,p2) -#define __arm_vqrdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) +#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlashq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlashq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlashq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vqrdmlahq(p0,p1,p2) __arm_vqrdmlahq(p0,p1,p2) -#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmpgtq(p0,p1) __arm_vcmpgtq(p0,p1) +#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqrdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqrdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqrdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t)));}) -#define vmlasq(p0,p1,p2) __arm_vmlasq(p0,p1,p2) -#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrnbq(p0,p1,p2) __arm_vrshrnbq(p0,p1,p2) +#define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmlahq(p0,p1,p2) __arm_vqdmlahq(p0,p1,p2) -#define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vrev16q_m(p0,p1,p2) __arm_vrev16q_m(p0,p1,p2) +#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqdmlahq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqdmlahq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqdmlahq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) -#define vqrdmladhxq(p0,p1,p2) __arm_vqrdmladhxq(p0,p1,p2) -#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqshruntq(p0,p1,p2) __arm_vqshruntq(p0,p1,p2) +#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vqrdmladhq(p0,p1,p2) __arm_vqrdmladhq(p0,p1,p2) -#define __arm_vqrdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqshrunbq_n(p0,p1,p2) __arm_vqshrunbq_n(p0,p1,p2) +#define __arm_vqshrunbq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vqnegq_m(p0,p1,p2) __arm_vqnegq_m(p0,p1,p2) -#define __arm_vqnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqshrnbq(p0,p1,p2) __arm_vqshrnbq(p0,p1,p2) +#define __arm_vqshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmlsdhxq(p0,p1,p2) __arm_vqdmlsdhxq(p0,p1,p2) -#define __arm_vqdmlsdhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqshrntq(p0,p1,p2) __arm_vqshrntq(p0,p1,p2) +#define __arm_vqshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmlsdhq(p0,p1,p2) __arm_vqdmlsdhq(p0,p1,p2) -#define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) +#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vqdmladhxq(p0,p1,p2) __arm_vqdmladhxq(p0,p1,p2) -#define __arm_vqdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovnbq_m(p0,p1,p2) __arm_vqmovnbq_m(p0,p1,p2) +#define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqdmladhq(p0,p1,p2) __arm_vqdmladhq(p0,p1,p2) -#define __arm_vqdmladhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovntq_m(p0,p1,p2) __arm_vqmovntq_m(p0,p1,p2) +#define __arm_vqmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) -#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovunbq_m(p0,p1,p2) __arm_vqmovunbq_m(p0,p1,p2) +#define __arm_vqmovunbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) -#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqmovuntq_m(p0,p1,p2) __arm_vqmovuntq_m(p0,p1,p2) +#define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) -#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqrshrntq(p0,p1,p2) __arm_vqrshrntq(p0,p1,p2) +#define __arm_vqrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vcvtaq_m(p0,p1,p2) __arm_vcvtaq_m(p0,p1,p2) -#define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) +#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtaq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtaq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vcvtq_m(p0,p1,p2) __arm_vcvtq_m(p0,p1,p2) -#define __arm_vcvtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vnegq_m(p0,p1,p2) __arm_vnegq_m(p0,p1,p2) +#define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcvtq_m_f32_u32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vnegq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vnegq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vcmpgeq_m(p0,p1,p2) __arm_vcmpgeq_m(p0,p1,p2) +#define __arm_vcmpgeq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) -#else /* MVE Interger. */ +#else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ @@ -10654,17 +12865,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) -#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) -#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define vnegq_m(p0,p1,p2) __arm_vnegq_m(p0,p1,p2) #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -10725,14 +12925,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) -#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) -#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define vminaq_m(p0,p1,p2) __arm_vminaq_m(p0,p1,p2) #define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -10938,7 +13130,302 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) -#endif /* MVE Floating point. */ +#define vshrntq(p0,p1,p2) __arm_vshrntq(p0,p1,p2) +#define __arm_vshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrshrntq(p0,p1,p2) __arm_vrshrntq(p0,p1,p2) +#define __arm_vrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmovlbq_m(p0,p1,p2) __arm_vmovlbq_m(p0,p1,p2) +#define __arm_vmovlbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vmovlbq_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vmovlbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vmovnbq_m(p0,p1,p2) __arm_vmovnbq_m(p0,p1,p2) +#define __arm_vmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmovntq_m(p0,p1,p2) __arm_vmovntq_m(p0,p1,p2) +#define __arm_vmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vshrnbq(p0,p1,p2) __arm_vshrnbq(p0,p1,p2) +#define __arm_vshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrshrnbq(p0,p1,p2) __arm_vrshrnbq(p0,p1,p2) +#define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrev32q_m(p0,p1,p2) __arm_vrev32q_m(p0,p1,p2) +#define __arm_vrev32q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev32q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrev32q_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vqshruntq(p0,p1,p2) __arm_vqshruntq(p0,p1,p2) +#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vrev16q_m(p0,p1,p2) __arm_vrev16q_m(p0,p1,p2) +#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) + +#define vqshrntq(p0,p1,p2) __arm_vqshrntq(p0,p1,p2) +#define __arm_vqshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) +#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqrshrntq(p0,p1,p2) __arm_vqrshrntq(p0,p1,p2) +#define __arm_vqrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqshrnbq(p0,p1,p2) __arm_vqshrnbq(p0,p1,p2) +#define __arm_vqshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqmovuntq_m(p0,p1,p2) __arm_vqmovuntq_m(p0,p1,p2) +#define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqmovntq_m(p0,p1,p2) __arm_vqmovntq_m(p0,p1,p2) +#define __arm_vqmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqmovnbq_m(p0,p1,p2) __arm_vqmovnbq_m(p0,p1,p2) +#define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmovltq_m(p0,p1,p2) __arm_vmovltq_m(p0,p1,p2) +#define __arm_vmovltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vmovltq_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vmovltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vmovltq_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vmovltq_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vqmovunbq_m(p0,p1,p2) __arm_vqmovunbq_m(p0,p1,p2) +#define __arm_vqmovunbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vaddlvaq_p(p0,p1,p2) __arm_vaddlvaq_p(p0,p1,p2) +#define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmlaldavaq(p0,p1,p2) __arm_vmlaldavaq(p0,p1,p2) +#define __arm_vmlaldavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vmlaldavaxq(p0,p1,p2) __arm_vmlaldavaxq(p0,p1,p2) +#define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vmlaldavq_p(p0,p1,p2) __arm_vmlaldavq_p(p0,p1,p2) +#define __arm_vmlaldavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavq_p_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavq_p_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vmlaldavxq_p(p0,p1,p2) __arm_vmlaldavxq_p(p0,p1,p2) +#define __arm_vmlaldavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavxq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavxq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlsldavaq(p0,p1,p2) __arm_vmlsldavaq(p0,p1,p2) +#define __arm_vmlsldavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaq_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaq_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vmlsldavaxq(p0,p1,p2) __arm_vmlsldavaxq(p0,p1,p2) +#define __arm_vmlsldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaxq_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaxq_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + +#define vmlsldavq_p(p0,p1,p2) __arm_vmlsldavq_p(p0,p1,p2) +#define __arm_vmlsldavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmlsldavxq_p(p0,p1,p2) __arm_vmlsldavxq_p(p0,p1,p2) +#define __arm_vmlsldavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavxq_p_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavxq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vrmlaldavhaxq(p0,p1,p2) __arm_vrmlaldavhaxq(p0,p1,p2) +#define __arm_vrmlaldavhaxq(p0,p1,p2) __arm_vrmlaldavhaxq_s32(p0,p1,p2) + +#define vrmlaldavhq_p(p0,p1,p2) __arm_vrmlaldavhq_p(p0,p1,p2) +#define __arm_vrmlaldavhq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhq_p_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhq_p_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrmlaldavhxq_p(p0,p1,p2) __arm_vrmlaldavhxq_p(p0,p1,p2) +#define __arm_vrmlaldavhxq_p(p0,p1,p2) __arm_vrmlaldavhxq_p_s32(p0,p1,p2) + +#define vrmlsldavhaq(p0,p1,p2) __arm_vrmlsldavhaq(p0,p1,p2) +#define __arm_vrmlsldavhaq(p0,p1,p2) __arm_vrmlsldavhaq_s32(p0,p1,p2) + +#define vrmlsldavhaxq(p0,p1,p2) __arm_vrmlsldavhaxq(p0,p1,p2) +#define __arm_vrmlsldavhaxq(p0,p1,p2) __arm_vrmlsldavhaxq_s32(p0,p1,p2) + +#define vrmlsldavhq_p(p0,p1,p2) __arm_vrmlsldavhq_p(p0,p1,p2) +#define __arm_vrmlsldavhq_p(p0,p1,p2) __arm_vrmlsldavhq_p_s32(p0,p1,p2) + +#define vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p(p0,p1,p2) +#define __arm_vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p_s32(p0,p1,p2) + +#endif /* MVE Integer. */ + +#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) +#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) +#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) + +#define vorrq_m_n(p0,p1,p2) __arm_vorrq_m_n(p0,p1,p2) +#define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vorrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vorrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqshrunbq(p0,p1,p2) __arm_vqshrunbq(p0,p1,p2) +#define __arm_vqshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) #ifdef __cplusplus } diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 25badfb..f625eed 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -394,3 +394,111 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev32q_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovntq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovnbq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovntq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovnbq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovltq_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovlbq_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavq_p_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrntq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrnbq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrntq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrnbq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrntq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrnbq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrntq_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovuntq_m_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovunbq_m_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtq_m_from_f_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtpq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtnq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtmq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshruntq_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf) +VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndnq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndmq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovntq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovnbq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vpselq_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovntq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovnbq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovltq_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovlbq_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavxq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavxq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmvq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmavq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmvq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmavq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_from_f_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtpq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtnq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtmq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaxq_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaq_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaxq_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaq_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmsq_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmasq_n_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_n_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrntq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrnbq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrntq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrnbq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrntq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vorrq_m_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vmvnq_m_n_s, v8hi, v4si) +VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si) +VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi) +VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b9985a0..dc7c3cb 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -110,7 +110,37 @@ VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S - VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S]) + VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S + VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S + VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S + VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F + VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S + VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F + VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S + VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F + VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F + VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F + VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F + VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F + VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F + VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S + VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F + VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U + VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S + VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U + VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S + VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S + VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S + VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U + VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S + VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S + VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U + VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32 + VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S + VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U + VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U + VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U + VCVTQ_M_N_FROM_F_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -193,7 +223,28 @@ (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s") (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u") (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s") - (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")]) + (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u") + (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s") + (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s") + (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s") + (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s") + (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s") + (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s") + (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u") + (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u") + (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u") + (VREV16Q_M_S "s") (VREV16Q_M_U "u") + (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u") + (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u") + (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u") + (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u") + (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s") + (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u") + (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s") + (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s") + (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u") + (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u") + (VCVTQ_M_N_FROM_F_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -205,6 +256,11 @@ (define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")]) (define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15") (V4SI "mve_imm_31")]) +(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")]) +(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")]) + +(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) +(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -323,6 +379,34 @@ (define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U]) (define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U]) (define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U]) +(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S]) +(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U]) +(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S]) +(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S]) +(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S]) +(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U]) +(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U]) +(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U]) +(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S]) +(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S]) +(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S]) +(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U]) +(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S]) +(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S]) +(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U]) +(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S]) +(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S]) +(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S]) +(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S]) +(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U]) +(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U]) +(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U]) +(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U]) +(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U]) +(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U]) +(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S]) +(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U]) +(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -422,6 +506,22 @@ [(set_attr "length" "16")]) ;; +;; [vrndq_m_f]) +;; +(define_insn "mve_vrndq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintzt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; ;; [vrndxq_f]) ;; (define_insn "mve_vrndxq_f" @@ -4266,3 +4366,1320 @@ "vmladavax.s%#\t%0, %q2, %q3" [(set_attr "type" "mve_move") ]) +;; +;; [vabsq_m_f]) +;; +(define_insn "mve_vabsq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VABSQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vabst.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddlvaq_p_s vaddlvaq_p_u]) +;; +(define_insn "mve_vaddlvaq_p_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VADDLVAQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddlvat.32 %Q0, %R0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vcmlaq_f]) +;; +(define_insn "mve_vcmlaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VCMLAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmla.f%# %q0, %q2, %q3, #0" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmlaq_rot180_f]) +;; +(define_insn "mve_vcmlaq_rot180_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VCMLAQ_ROT180_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmla.f%# %q0, %q2, %q3, #180" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmlaq_rot270_f]) +;; +(define_insn "mve_vcmlaq_rot270_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VCMLAQ_ROT270_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmla.f%# %q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmlaq_rot90_f]) +;; +(define_insn "mve_vcmlaq_rot90_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VCMLAQ_ROT90_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcmla.f%# %q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcmpeqq_m_n_f]) +;; +(define_insn "mve_vcmpeqq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPEQQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# eq, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgeq_m_f]) +;; +(define_insn "mve_vcmpgeq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGEQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# ge, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgeq_m_n_f]) +;; +(define_insn "mve_vcmpgeq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGEQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# ge, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgtq_m_f]) +;; +(define_insn "mve_vcmpgtq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGTQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# gt, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpgtq_m_n_f]) +;; +(define_insn "mve_vcmpgtq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPGTQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# gt, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpleq_m_f]) +;; +(define_insn "mve_vcmpleq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLEQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# le, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpleq_m_n_f]) +;; +(define_insn "mve_vcmpleq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLEQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# le, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpltq_m_f]) +;; +(define_insn "mve_vcmpltq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLTQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# lt, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpltq_m_n_f]) +;; +(define_insn "mve_vcmpltq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPLTQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# lt, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpneq_m_f]) +;; +(define_insn "mve_vcmpneq_m_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPNEQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# ne, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmpneq_m_n_f]) +;; +(define_insn "mve_vcmpneq_m_n_f" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCMPNEQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmpt.f%# ne, %q1, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtbq_m_f16_f32]) +;; +(define_insn "mve_vcvtbq_m_f16_f32v8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTBQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtbt.f16.f32 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtbq_m_f32_f16]) +;; +(define_insn "mve_vcvtbq_m_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") + (match_operand:V8HF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTBQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtbt.f32.f16 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvttq_m_f16_f32]) +;; +(define_insn "mve_vcvttq_m_f16_f32v8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTTQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvttt.f16.f32 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvttq_m_f32_f16]) +;; +(define_insn "mve_vcvttq_m_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") + (match_operand:V8HF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTTQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvttt.f32.f16 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vdupq_m_n_f]) +;; +(define_insn "mve_vdupq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "r") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VDUPQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vdupt.%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vfmaq_f]) +;; +(define_insn "mve_vfmaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VFMAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vfma.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vfmaq_n_f]) +;; +(define_insn "mve_vfmaq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VFMAQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vfma.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vfmasq_n_f]) +;; +(define_insn "mve_vfmasq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r")] + VFMASQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vfmas.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) +;; +;; [vfmsq_f]) +;; +(define_insn "mve_vfmsq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w")] + VFMSQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vfms.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmaxnmaq_m_f]) +;; +(define_insn "mve_vmaxnmaq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXNMAQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmaxnmat.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vmaxnmavq_p_f]) +;; +(define_insn "mve_vmaxnmavq_p_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXNMAVQ_P_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmaxnmavt.f%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxnmvq_p_f]) +;; +(define_insn "mve_vmaxnmvq_p_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMAXNMVQ_P_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmaxnmvt.f%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vminnmaq_m_f]) +;; +(define_insn "mve_vminnmaq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINNMAQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vminnmat.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminnmavq_p_f]) +;; +(define_insn "mve_vminnmavq_p_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINNMAVQ_P_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vminnmavt.f%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vminnmvq_p_f]) +;; +(define_insn "mve_vminnmvq_p_f" + [ + (set (match_operand: 0 "s_register_operand" "=r") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMINNMVQ_P_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vminnmvt.f%# %0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlaldavaq_s, vmlaldavaq_u]) +;; +(define_insn "mve_vmlaldavaq_" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w")] + VMLALDAVAQ)) + ] + "TARGET_HAVE_MVE" + "vmlaldava.%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlaldavaxq_s]) +;; +(define_insn "mve_vmlaldavaxq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w")] + VMLALDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlaldavax.s%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlaldavq_p_u, vmlaldavq_p_s]) +;; +(define_insn "mve_vmlaldavq_p_" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLALDAVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlaldavt.%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlaldavxq_p_s]) +;; +(define_insn "mve_vmlaldavxq_p_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLALDAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlaldavxt.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vmlsldavaq_s]) +;; +(define_insn "mve_vmlsldavaq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w")] + VMLSLDAVAQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsldava.s%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsldavaxq_s]) +;; +(define_insn "mve_vmlsldavaxq_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w")] + VMLSLDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vmlsldavax.s%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmlsldavq_p_s]) +;; +(define_insn "mve_vmlsldavq_p_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLSLDAVQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsldavt.s%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsldavxq_p_s]) +;; +(define_insn "mve_vmlsldavxq_p_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMLSLDAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsldavxt.s%# %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vmovlbq_m_u, vmovlbq_m_s]) +;; +(define_insn "mve_vmovlbq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMOVLBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmovlbt.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vmovltq_m_u, vmovltq_m_s]) +;; +(define_insn "mve_vmovltq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMOVLTQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmovltt.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vmovnbq_m_u, vmovnbq_m_s]) +;; +(define_insn "mve_vmovnbq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMOVNBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmovnbt.i%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmovntq_m_u, vmovntq_m_s]) +;; +(define_insn "mve_vmovntq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMOVNTQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmovntt.i%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmvnq_m_n_u, vmvnq_m_n_s]) +;; +(define_insn "mve_vmvnq_m_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VMVNQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmvnt.i%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vnegq_m_f]) +;; +(define_insn "mve_vnegq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VNEGQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vnegt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vorrq_m_n_s, vorrq_m_n_u]) +;; +(define_insn "mve_vorrq_m_n_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VORRQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vorrt.i%# %q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) +;; +;; [vpselq_f]) +;; +(define_insn "mve_vpselq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VPSELQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpsel %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqmovnbq_m_s, vqmovnbq_m_u]) +;; +(define_insn "mve_vqmovnbq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQMOVNBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqmovnbt.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqmovntq_m_u, vqmovntq_m_s]) +;; +(define_insn "mve_vqmovntq_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQMOVNTQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqmovntt.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqmovunbq_m_s]) +;; +(define_insn "mve_vqmovunbq_m_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQMOVUNBQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqmovunbt.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqmovuntq_m_s]) +;; +(define_insn "mve_vqmovuntq_m_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VQMOVUNTQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqmovuntt.s%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshrntq_n_u, vqrshrntq_n_s]) +;; +(define_insn "mve_vqrshrntq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQRSHRNTQ_N)) + ] + "TARGET_HAVE_MVE" + "vqrshrnt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqrshruntq_n_s]) +;; +(define_insn "mve_vqrshruntq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQRSHRUNTQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqrshrunt.s%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshrnbq_n_u, vqshrnbq_n_s]) +;; +(define_insn "mve_vqshrnbq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "")] + VQSHRNBQ_N)) + ] + "TARGET_HAVE_MVE" + "vqshrnb.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshrntq_n_u, vqshrntq_n_s]) +;; +(define_insn "mve_vqshrntq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQSHRNTQ_N)) + ] + "TARGET_HAVE_MVE" + "vqshrnt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshrunbq_n_s]) +;; +(define_insn "mve_vqshrunbq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i")] + VQSHRUNBQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqshrunb.s%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshruntq_n_s]) +;; +(define_insn "mve_vqshruntq_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VQSHRUNTQ_N_S)) + ] + "TARGET_HAVE_MVE" + "vqshrunt.s%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_m_f]) +;; +(define_insn "mve_vrev32q_m_fv8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") + (match_operand:V8HF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VREV32Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrev32t.16 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrev32q_m_s, vrev32q_m_u]) +;; +(define_insn "mve_vrev32q_m_" + [ + (set (match_operand:MVE_3 0 "s_register_operand" "=w") + (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VREV32Q_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrev32t.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrev64q_m_f]) +;; +(define_insn "mve_vrev64q_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VREV64Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrev64t.%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlaldavhaxq_s]) +;; +(define_insn "mve_vrmlaldavhaxq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w")] + VRMLALDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlaldavhxq_p_s]) +;; +(define_insn "mve_vrmlaldavhxq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRMLALDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlsldavhaxq_s]) +;; +(define_insn "mve_vrmlsldavhaxq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w")] + VRMLSLDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrmlsldavhq_p_s]) +;; +(define_insn "mve_vrmlsldavhq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRMLSLDAVHQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlsldavhxq_p_s]) +;; +(define_insn "mve_vrmlsldavhxq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRMLSLDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrndaq_m_f]) +;; +(define_insn "mve_vrndaq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDAQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintat.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrndmq_m_f]) +;; +(define_insn "mve_vrndmq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDMQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintmt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrndnq_m_f]) +;; +(define_insn "mve_vrndnq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDNQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintnt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrndpq_m_f]) +;; +(define_insn "mve_vrndpq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDPQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintpt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrndxq_m_f]) +;; +(define_insn "mve_vrndxq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRNDXQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vrintxt.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshrnbq_n_s, vrshrnbq_n_u]) +;; +(define_insn "mve_vrshrnbq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VRSHRNBQ_N)) + ] + "TARGET_HAVE_MVE" + "vrshrnb.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrshrntq_n_u, vrshrntq_n_s]) +;; +(define_insn "mve_vrshrntq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb")] + VRSHRNTQ_N)) + ] + "TARGET_HAVE_MVE" + "vrshrnt.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshrnbq_n_u, vshrnbq_n_s]) +;; +(define_insn "mve_vshrnbq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "")] + VSHRNBQ_N)) + ] + "TARGET_HAVE_MVE" + "vshrnb.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vshrntq_n_s, vshrntq_n_u]) +;; +(define_insn "mve_vshrntq_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "")] + VSHRNTQ_N)) + ] + "TARGET_HAVE_MVE" + "vshrnt.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtmq_m_s, vcvtmq_m_u]) +;; +(define_insn "mve_vcvtmq_m_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTMQ_M)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtmt.%#.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtpq_m_u, vcvtpq_m_s]) +;; +(define_insn "mve_vcvtpq_m_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTPQ_M)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtpt.%#.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtnq_m_s, vcvtnq_m_u]) +;; +(define_insn "mve_vcvtnq_m_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTNQ_M)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtnt.%#.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]) +;; +(define_insn "mve_vcvtq_m_n_from_f_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_16" "Rd") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCVTQ_M_N_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtt.%#.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrev16q_m_u, vrev16q_m_s]) +;; +(define_insn "mve_vrev16q_m_v16qi" + [ + (set (match_operand:V16QI 0 "s_register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") + (match_operand:V16QI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VREV16Q_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrev16t.8 %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]) +;; +(define_insn "mve_vcvtq_m_from_f_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VCVTQ_M_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtt.%#.f%# %q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]) +;; +(define_insn "mve_vrmlaldavhq_p_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VRMLALDAVHQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlaldavht.32 %Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlsldavhaq_s]) +;; +(define_insn "mve_vrmlsldavhaq_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w")] + VRMLSLDAVHAQ_S)) + ] + "TARGET_HAVE_MVE" + "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6cae249..c0777a3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,214 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c new file mode 100644 index 0000000..6529ec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vabsq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c new file mode 100644 index 0000000..12f64f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vabsq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vabsq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c new file mode 100644 index 0000000..8ff3020 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddlvaq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddlvat.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddlvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddlvat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c new file mode 100644 index 0000000..bd9ac8e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddlvaq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vaddlvat.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddlvaq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vaddlvat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c new file mode 100644 index 0000000..148e07b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c new file mode 100644 index 0000000..2608b72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c new file mode 100644 index 0000000..6f5f7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot180_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot180 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c new file mode 100644 index 0000000..dc0faae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot180_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot180 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c new file mode 100644 index 0000000..325d9ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot270_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot270 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c new file mode 100644 index 0000000..0d3b72f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot270_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot270 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c new file mode 100644 index 0000000..a2542f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot90_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vcmlaq_rot90 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c new file mode 100644 index 0000000..e47a274 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot90_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vcmlaq_rot90 (a, b, c); +} + +/* { dg-final { scan-assembler "vcmla.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c new file mode 100644 index 0000000..0601434 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c new file mode 100644 index 0000000..1d58073 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpeqq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpeqq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c new file mode 100644 index 0000000..2a199da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpgeq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c new file mode 100644 index 0000000..87cd830 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpgeq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c new file mode 100644 index 0000000..45def8d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c new file mode 100644 index 0000000..d073006 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpgeq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpgeq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c new file mode 100644 index 0000000..34ceeeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpgtq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c new file mode 100644 index 0000000..6c457a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpgtq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpgtq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c new file mode 100644 index 0000000..252d4a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c new file mode 100644 index 0000000..c5e5a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpgtq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c new file mode 100644 index 0000000..f295dd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpleq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c new file mode 100644 index 0000000..6962012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpleq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpleq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c new file mode 100644 index 0000000..e8433e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpleq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpleq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c new file mode 100644 index 0000000..e506345 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpleq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpleq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c new file mode 100644 index 0000000..33c6c56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpltq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c new file mode 100644 index 0000000..534e923 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpltq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpltq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c new file mode 100644 index 0000000..8cbfa35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpltq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpltq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c new file mode 100644 index 0000000..4765b05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpltq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpltq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c new file mode 100644 index 0000000..21c23cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c new file mode 100644 index 0000000..a9a230e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmpneq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c new file mode 100644 index 0000000..5ab3bb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f16" } } */ + +mve_pred16_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vcmpneq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c new file mode 100644 index 0000000..17cfafb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpneq_m_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmpt.f32" } } */ + +mve_pred16_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vcmpneq_m_n (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c new file mode 100644 index 0000000..665ae2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float32x4_t b, mve_pred16_t p) +{ + return vcvtbq_m_f16_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtbt.f16.f32" } } */ + +float16x8_t +foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +{ + return vcvtbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c new file mode 100644 index 0000000..0725f82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtbq_m_f32_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtbq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c new file mode 100644 index 0000000..fb742b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_m_s16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c new file mode 100644 index 0000000..0ed20bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_m_s32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c new file mode 100644 index 0000000..062fb97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_m_u16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c new file mode 100644 index 0000000..1790beb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_m_u32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c new file mode 100644 index 0000000..4c13982 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_m_s16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c new file mode 100644 index 0000000..97ab45f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_m_s32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c new file mode 100644 index 0000000..c5c9d2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_m_u16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c new file mode 100644 index 0000000..67268b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_m_u32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c new file mode 100644 index 0000000..0505efd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_m_s16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c new file mode 100644 index 0000000..45b0338 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_m_s32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c new file mode 100644 index 0000000..78e22d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_m_u16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c new file mode 100644 index 0000000..3deb3b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_m_u32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c new file mode 100644 index 0000000..9478d48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_s16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c new file mode 100644 index 0000000..53279cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_s32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c new file mode 100644 index 0000000..261f4d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_u16_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c new file mode 100644 index 0000000..24ac27e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_u32_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c new file mode 100644 index 0000000..79ac686 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float32x4_t b, mve_pred16_t p) +{ + return vcvttq_m_f16_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvttt.f16.f32" } } */ + +float16x8_t +foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +{ + return vcvttq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c new file mode 100644 index 0000000..e1dff8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvttq_m_f32_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvttq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c new file mode 100644 index 0000000..7097dd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16_t a, mve_pred16_t p) +{ + return vdupq_m_n_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c new file mode 100644 index 0000000..98d89a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32_t a, mve_pred16_t p) +{ + return vdupq_m_n_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p) +{ + return vdupq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c new file mode 100644 index 0000000..88ebc5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vfmaq_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vfmaq (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c new file mode 100644 index 0000000..0eec958 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vfmaq_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vfmaq (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c new file mode 100644 index 0000000..09c927a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16_t c) +{ + return vfmaq_n_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16_t c) +{ + return vfmaq_n (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c new file mode 100644 index 0000000..ad3b7c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32_t c) +{ + return vfmaq_n_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32_t c) +{ + return vfmaq_n (a, b, c); +} + +/* { dg-final { scan-assembler "vfma.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c new file mode 100644 index 0000000..30e797e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16_t c) +{ + return vfmasq_n_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vfmas.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16_t c) +{ + return vfmasq_n (a, b, c); +} + +/* { dg-final { scan-assembler "vfmas.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c new file mode 100644 index 0000000..14a45a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32_t c) +{ + return vfmasq_n_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vfmas.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32_t c) +{ + return vfmasq_n (a, b, c); +} + +/* { dg-final { scan-assembler "vfmas.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c new file mode 100644 index 0000000..082699a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vfmsq_f16 (a, b, c); +} + +/* { dg-final { scan-assembler "vfms.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c) +{ + return vfmsq (a, b, c); +} + +/* { dg-final { scan-assembler "vfms.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c new file mode 100644 index 0000000..3bbef3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vfmsq_f32 (a, b, c); +} + +/* { dg-final { scan-assembler "vfms.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c) +{ + return vfmsq (a, b, c); +} + +/* { dg-final { scan-assembler "vfms.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c new file mode 100644 index 0000000..dab1111 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmaq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c new file mode 100644 index 0000000..82204412 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmaq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c new file mode 100644 index 0000000..011dac2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmavq_p_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmavt.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmavt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c new file mode 100644 index 0000000..7bfdc6c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmavq_p_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmavt.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmavt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c new file mode 100644 index 0000000..76ebd12 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmvq_p_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmvt.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmvt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c new file mode 100644 index 0000000..0dc9688 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmvq_p_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmvt.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmaxnmvt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c new file mode 100644 index 0000000..711bc95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmaq_m_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c new file mode 100644 index 0000000..7943fa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmaq_m_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmaq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c new file mode 100644 index 0000000..a7c709a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmavq_p_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmavt.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmavt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c new file mode 100644 index 0000000..7fdcaf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmavq_p_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmavt.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmavt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c new file mode 100644 index 0000000..e386049 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16_t +foo (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmvq_p_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmvt.f16" } } */ + +float16_t +foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmvt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c new file mode 100644 index 0000000..dd33ab3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32_t +foo (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmvq_p_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmvt.f32" } } */ + +float32_t +foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmvq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vminnmvt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c new file mode 100644 index 0000000..1aab14cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlaldavaq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlaldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c new file mode 100644 index 0000000..dbfaf09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlaldavaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlaldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c new file mode 100644 index 0000000..8cfbc64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint16x8_t b, uint16x8_t c) +{ + return vmlaldavaq_u16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.u16" } } */ + +uint64_t +foo1 (uint64_t a, uint16x8_t b, uint16x8_t c) +{ + return vmlaldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c new file mode 100644 index 0000000..58922bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, uint32x4_t c) +{ + return vmlaldavaq_u32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, uint32x4_t c) +{ + return vmlaldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldava.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c new file mode 100644 index 0000000..067017c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlaldavaxq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldavax.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlaldavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldavax.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c new file mode 100644 index 0000000..5cbbc72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlaldavaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldavax.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlaldavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlaldavax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c new file mode 100644 index 0000000..5e2b949 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlaldavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlaldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c new file mode 100644 index 0000000..de90999 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlaldavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlaldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c new file mode 100644 index 0000000..a21fb90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmlaldavq_p_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ + +uint64_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmlaldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c new file mode 100644 index 0000000..c5d2eb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmlaldavq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ + +uint64_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmlaldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c new file mode 100644 index 0000000..2631030 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlaldavxq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlaldavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c new file mode 100644 index 0000000..ebd8cea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlaldavxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlaldavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c new file mode 100644 index 0000000..926c399 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlsldavaq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldava.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlsldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldava.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c new file mode 100644 index 0000000..0594ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlsldavaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldava.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlsldavaq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldava.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c new file mode 100644 index 0000000..538f7e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlsldavaxq_s16 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c) +{ + return vmlsldavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c new file mode 100644 index 0000000..ec831a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlsldavaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vmlsldavaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c new file mode 100644 index 0000000..56ebf0f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsldavq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c new file mode 100644 index 0000000..8ea3975 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsldavq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsldavq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c new file mode 100644 index 0000000..056540f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsldavxq_p_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ + +int64_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmlsldavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c new file mode 100644 index 0000000..121a251 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsldavxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmlsldavxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c new file mode 100644 index 0000000..c02612c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmovlbq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmovlbq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c new file mode 100644 index 0000000..bdb0d26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmovlbq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmovlbq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c new file mode 100644 index 0000000..6a2c7a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmovlbq_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmovlbq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c new file mode 100644 index 0000000..c305beb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmovlbq_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmovlbq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c new file mode 100644 index 0000000..1676666 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmovltq_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vmovltq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c new file mode 100644 index 0000000..44ddb09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmovltq_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vmovltq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c new file mode 100644 index 0000000..ac886d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmovltq_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vmovltq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c new file mode 100644 index 0000000..cfe51ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmovltq_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vmovltq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c new file mode 100644 index 0000000..e26a051 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmovnbq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c new file mode 100644 index 0000000..72d88aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vmovnbq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c new file mode 100644 index 0000000..0cbce92 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmovnbq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c new file mode 100644 index 0000000..b98f1e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmovnbq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c new file mode 100644 index 0000000..6603643 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmovntq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovntt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c new file mode 100644 index 0000000..7c15d9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vmovntq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovntt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c new file mode 100644 index 0000000..73bd1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmovntq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovntt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c new file mode 100644 index 0000000..3b3cdf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmovntq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovntt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c new file mode 100644 index 0000000..47edf29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, mve_pred16_t p) +{ + return vmvnq_m_n_s16 (inactive, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, mve_pred16_t p) +{ + return vmvnq_m (inactive, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c new file mode 100644 index 0000000..92fcbf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, mve_pred16_t p) +{ + return vmvnq_m_n_s32 (inactive, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, mve_pred16_t p) +{ + return vmvnq_m (inactive, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c new file mode 100644 index 0000000..cac62ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, mve_pred16_t p) +{ + return vmvnq_m_n_u16 (inactive, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, mve_pred16_t p) +{ + return vmvnq_m (inactive, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c new file mode 100644 index 0000000..2e90323 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, mve_pred16_t p) +{ + return vmvnq_m_n_u32 (inactive, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, mve_pred16_t p) +{ + return vmvnq_m (inactive, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c new file mode 100644 index 0000000..94fba1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vnegq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c new file mode 100644 index 0000000..978e86d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vnegq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vnegq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c new file mode 100644 index 0000000..ea53cf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vorrq_m_n_s16 (a, 253, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vorrq_m_n (a, 253, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c new file mode 100644 index 0000000..ccdac83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vorrq_m_n_s32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vorrq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c new file mode 100644 index 0000000..c17b92d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vorrq_m_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vorrq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c new file mode 100644 index 0000000..686373a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vorrq_m_n_u32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vorrq_m_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c new file mode 100644 index 0000000..f69b63d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vpselq_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c new file mode 100644 index 0000000..f8bbc5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vpselq_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vpselq (a, b, p); +} + +/* { dg-final { scan-assembler "vpsel" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c new file mode 100644 index 0000000..1217cb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovnbq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovnbt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c new file mode 100644 index 0000000..3b2a5b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovnbq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovnbt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c new file mode 100644 index 0000000..aa506e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqmovnbq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovnbt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c new file mode 100644 index 0000000..864be99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqmovnbq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovnbt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqmovnbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c new file mode 100644 index 0000000..86b921e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovntq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovntt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c new file mode 100644 index 0000000..688a71a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovntq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovntt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c new file mode 100644 index 0000000..b2ae37e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqmovntq_m_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovntt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c new file mode 100644 index 0000000..cab5bfb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqmovntq_m_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovntt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqmovntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c new file mode 100644 index 0000000..c5c8e94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovunbq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovunbt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovunbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c new file mode 100644 index 0000000..a9c2907 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovunbq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovunbt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovunbq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c new file mode 100644 index 0000000..0bb12fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovuntq_m_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovuntt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqmovuntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c new file mode 100644 index 0000000..d2b438f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovuntq_m_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqmovuntt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqmovuntq_m (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c new file mode 100644 index 0000000..c1e2978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqrshrntq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c new file mode 100644 index 0000000..4a9d374 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqrshrntq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c new file mode 100644 index 0000000..64df22d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqrshrntq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c new file mode 100644 index 0000000..3a464c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqrshrntq_n_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c new file mode 100644 index 0000000..eeb7f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqrshruntq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqrshruntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c new file mode 100644 index 0000000..120d41a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqrshruntq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqrshruntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c new file mode 100644 index 0000000..698e347 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqshrnbq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnb.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c new file mode 100644 index 0000000..01d1453 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqshrnbq_n_s32 (a, b, 2); +} + +/* { dg-final { scan-assembler "vqshrnb.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqshrnbq (a, b, 2); +} + +/* { dg-final { scan-assembler "vqshrnb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c new file mode 100644 index 0000000..3ad9d94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqshrnbq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnb.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c new file mode 100644 index 0000000..9e8a9dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqshrnbq_n_u32 (a, b, 15); +} + +/* { dg-final { scan-assembler "vqshrnb.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqshrnbq (a, b, 15); +} + +/* { dg-final { scan-assembler "vqshrnb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c new file mode 100644 index 0000000..309a11c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vqshrntq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vqshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c new file mode 100644 index 0000000..f595427 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vqshrntq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vqshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c new file mode 100644 index 0000000..c072815 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vqshrntq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vqshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c new file mode 100644 index 0000000..cddae95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vqshrntq_n_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vqshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrnt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c new file mode 100644 index 0000000..833be37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqshrunbq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunb.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqshrunbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c new file mode 100644 index 0000000..414aaae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqshrunbq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunb.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqshrunbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c new file mode 100644 index 0000000..09be21c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b) +{ + return vqshruntq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b) +{ + return vqshruntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c new file mode 100644 index 0000000..cd60207 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b) +{ + return vqshruntq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b) +{ + return vqshruntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vqshrunt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c new file mode 100644 index 0000000..dfb0204 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev16q_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev16t.8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev16q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c new file mode 100644 index 0000000..07bd733 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev16q_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev16t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev16q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c new file mode 100644 index 0000000..c2d1823 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrev32q_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrev32q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c new file mode 100644 index 0000000..84b23d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrev32q_m_s16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrev32q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c new file mode 100644 index 0000000..e2d2748 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev32q_m_s8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrev32q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c new file mode 100644 index 0000000..18ef6de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrev32q_m_u16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrev32q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c new file mode 100644 index 0000000..a0c9e99 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev32q_m_u8 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrev32q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c new file mode 100644 index 0000000..0bc493f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrev64q_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c new file mode 100644 index 0000000..0289d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrev64q_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrev64q_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c new file mode 100644 index 0000000..100eca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlaldavhaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlaldavhaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c new file mode 100644 index 0000000..7c435f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c new file mode 100644 index 0000000..4a0a7aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhq_p_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ + +uint64_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c new file mode 100644 index 0000000..51c8bbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlaldavhxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c new file mode 100644 index 0000000..94ef2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlsldavhaq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlsldavhaq (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c new file mode 100644 index 0000000..9a3d0b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlsldavhaxq_s32 (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c) +{ + return vrmlsldavhaxq (a, b, c); +} + +/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c new file mode 100644 index 0000000..157a610 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlsldavhq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlsldavhq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c new file mode 100644 index 0000000..3c31665 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlsldavhxq_p_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ + +int64_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmlsldavhxq_p (a, b, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c new file mode 100644 index 0000000..cc217d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndaq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintat.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c new file mode 100644 index 0000000..f71372a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndaq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintat.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndaq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c new file mode 100644 index 0000000..9c97109 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndmq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c new file mode 100644 index 0000000..e3ed265 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndmq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndmq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c new file mode 100644 index 0000000..17d6e15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndnq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintnt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c new file mode 100644 index 0000000..28952c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndnq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintnt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndnq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c new file mode 100644 index 0000000..5a6f414 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndpq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintpt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c new file mode 100644 index 0000000..eef9fc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndpq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintpt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndpq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c new file mode 100644 index 0000000..ced3b3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintzt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c new file mode 100644 index 0000000..27a9015 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintzt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c new file mode 100644 index 0000000..fedc6ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndxq_m_f16 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintxt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vrndxq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c new file mode 100644 index 0000000..52c2dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndxq_m_f32 (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintxt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vrndxq_m (inactive, a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c new file mode 100644 index 0000000..a93228c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vrshrnbq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c new file mode 100644 index 0000000..65435d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vrshrnbq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c new file mode 100644 index 0000000..0f72b27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vrshrnbq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c new file mode 100644 index 0000000..3c497d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vrshrnbq_n_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vrshrnbq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c new file mode 100644 index 0000000..12f82cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vrshrntq_n_s16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c new file mode 100644 index 0000000..6f31cff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vrshrntq_n_s32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c new file mode 100644 index 0000000..7764009 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vrshrntq_n_u16 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c new file mode 100644 index 0000000..199f88a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vrshrntq_n_u32 (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vrshrntq (a, b, 1); +} + +/* { dg-final { scan-assembler "vrshrnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c new file mode 100644 index 0000000..249e85a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vshrnbq_n_s16 (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnb.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vshrnbq (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c new file mode 100644 index 0000000..19391aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vshrnbq_n_s32 (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnb.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vshrnbq (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c new file mode 100644 index 0000000..f9973a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vshrnbq_n_u16 (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnb.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vshrnbq (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnb.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c new file mode 100644 index 0000000..2b0007b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vshrnbq_n_u32 (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnb.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vshrnbq (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnb.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c new file mode 100644 index 0000000..b16cd95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b) +{ + return vshrntq_n_s16 (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b) +{ + return vshrntq (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c new file mode 100644 index 0000000..9521a42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b) +{ + return vshrntq_n_s32 (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b) +{ + return vshrntq (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c new file mode 100644 index 0000000..19362a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b) +{ + return vshrntq_n_u16 (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b) +{ + return vshrntq (a, b, 8); +} + +/* { dg-final { scan-assembler "vshrnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c new file mode 100644 index 0000000..154c74b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b) +{ + return vshrntq_n_u32 (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b) +{ + return vshrntq (a, b, 16); +} + +/* { dg-final { scan-assembler "vshrnt.i32" } } */ -- cgit v1.1 From db5db9d254853decad675afbb4272cf30fec179d Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 16:47:31 +0000 Subject: [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. This patch supports following MVE ACLE intrinsics with quaternary operands. vsriq_m_n_s8, vsubq_m_s8, vsubq_x_s8, vcvtq_m_n_f16_u16, vcvtq_x_n_f16_u16, vqshluq_m_n_s8, vabavq_p_s8, vsriq_m_n_u8, vshlq_m_u8, vshlq_x_u8, vsubq_m_u8, vsubq_x_u8, vabavq_p_u8, vshlq_m_s8, vshlq_x_s8, vcvtq_m_n_f16_s16, vcvtq_x_n_f16_s16, vsriq_m_n_s16, vsubq_m_s16, vsubq_x_s16, vcvtq_m_n_f32_u32, vcvtq_x_n_f32_u32, vqshluq_m_n_s16, vabavq_p_s16, vsriq_m_n_u16, vshlq_m_u16, vshlq_x_u16, vsubq_m_u16, vsubq_x_u16, vabavq_p_u16, vshlq_m_s16, vshlq_x_s16, vcvtq_m_n_f32_s32, vcvtq_x_n_f32_s32, vsriq_m_n_s32, vsubq_m_s32, vsubq_x_s32, vqshluq_m_n_s32, vabavq_p_s32, vsriq_m_n_u32, vshlq_m_u32, vshlq_x_u32, vsubq_m_u32, vsubq_x_u32, vabavq_p_u32, vshlq_m_s32, vshlq_x_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Define builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. (vsubq_m_s8): Likewise. (vcvtq_m_n_f16_u16): Likewise. (vqshluq_m_n_s8): Likewise. (vabavq_p_s8): Likewise. (vsriq_m_n_u8): Likewise. (vshlq_m_u8): Likewise. (vsubq_m_u8): Likewise. (vabavq_p_u8): Likewise. (vshlq_m_s8): Likewise. (vcvtq_m_n_f16_s16): Likewise. (vsriq_m_n_s16): Likewise. (vsubq_m_s16): Likewise. (vcvtq_m_n_f32_u32): Likewise. (vqshluq_m_n_s16): Likewise. (vabavq_p_s16): Likewise. (vsriq_m_n_u16): Likewise. (vshlq_m_u16): Likewise. (vsubq_m_u16): Likewise. (vabavq_p_u16): Likewise. (vshlq_m_s16): Likewise. (vcvtq_m_n_f32_s32): Likewise. (vsriq_m_n_s32): Likewise. (vsubq_m_s32): Likewise. (vqshluq_m_n_s32): Likewise. (vabavq_p_s32): Likewise. (vsriq_m_n_u32): Likewise. (vshlq_m_u32): Likewise. (vsubq_m_u32): Likewise. (vabavq_p_u32): Likewise. (vshlq_m_s32): Likewise. (__arm_vsriq_m_n_s8): Define intrinsic. (__arm_vsubq_m_s8): Likewise. (__arm_vqshluq_m_n_s8): Likewise. (__arm_vabavq_p_s8): Likewise. (__arm_vsriq_m_n_u8): Likewise. (__arm_vshlq_m_u8): Likewise. (__arm_vsubq_m_u8): Likewise. (__arm_vabavq_p_u8): Likewise. (__arm_vshlq_m_s8): Likewise. (__arm_vsriq_m_n_s16): Likewise. (__arm_vsubq_m_s16): Likewise. (__arm_vqshluq_m_n_s16): Likewise. (__arm_vabavq_p_s16): Likewise. (__arm_vsriq_m_n_u16): Likewise. (__arm_vshlq_m_u16): Likewise. (__arm_vsubq_m_u16): Likewise. (__arm_vabavq_p_u16): Likewise. (__arm_vshlq_m_s16): Likewise. (__arm_vsriq_m_n_s32): Likewise. (__arm_vsubq_m_s32): Likewise. (__arm_vqshluq_m_n_s32): Likewise. (__arm_vabavq_p_s32): Likewise. (__arm_vsriq_m_n_u32): Likewise. (__arm_vshlq_m_u32): Likewise. (__arm_vsubq_m_u32): Likewise. (__arm_vabavq_p_u32): Likewise. (__arm_vshlq_m_s32): Likewise. (__arm_vcvtq_m_n_f16_u16): Likewise. (__arm_vcvtq_m_n_f16_s16): Likewise. (__arm_vcvtq_m_n_f32_u32): Likewise. (__arm_vcvtq_m_n_f32_s32): Likewise. (vcvtq_m_n): Define polymorphic variant. (vqshluq_m_n): Likewise. (vshlq_m): Likewise. (vsriq_m_n): Likewise. (vsubq_m): Likewise. (vabavq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/mve.md (VABAVQ_P): Define iterator. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (mve_vabavq_p_): Define RTL pattern. (mve_vqshluq_m_n_s): Likewise. (mve_vshlq_m_): Likewise. (mve_vsriq_m_n_): Likewise. (mve_vsubq_m_): Likewise. (mve_vcvtq_m_n_to_f_): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. --- gcc/ChangeLog | 102 +++++++ gcc/config/arm/arm-builtins.c | 56 ++++ gcc/config/arm/arm_mve.h | 326 ++++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 11 + gcc/config/arm/mve.md | 126 +++++++- gcc/testsuite/ChangeLog | 36 +++ .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 22 ++ .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 24 ++ .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 24 ++ .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 24 ++ .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 24 ++ .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 23 ++ .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 23 ++ .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 23 ++ 37 files changed, 1347 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1d1efbd..eaf5ff5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,108 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): + Define builtin qualifier. + (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. + (vsubq_m_s8): Likewise. + (vcvtq_m_n_f16_u16): Likewise. + (vqshluq_m_n_s8): Likewise. + (vabavq_p_s8): Likewise. + (vsriq_m_n_u8): Likewise. + (vshlq_m_u8): Likewise. + (vsubq_m_u8): Likewise. + (vabavq_p_u8): Likewise. + (vshlq_m_s8): Likewise. + (vcvtq_m_n_f16_s16): Likewise. + (vsriq_m_n_s16): Likewise. + (vsubq_m_s16): Likewise. + (vcvtq_m_n_f32_u32): Likewise. + (vqshluq_m_n_s16): Likewise. + (vabavq_p_s16): Likewise. + (vsriq_m_n_u16): Likewise. + (vshlq_m_u16): Likewise. + (vsubq_m_u16): Likewise. + (vabavq_p_u16): Likewise. + (vshlq_m_s16): Likewise. + (vcvtq_m_n_f32_s32): Likewise. + (vsriq_m_n_s32): Likewise. + (vsubq_m_s32): Likewise. + (vqshluq_m_n_s32): Likewise. + (vabavq_p_s32): Likewise. + (vsriq_m_n_u32): Likewise. + (vshlq_m_u32): Likewise. + (vsubq_m_u32): Likewise. + (vabavq_p_u32): Likewise. + (vshlq_m_s32): Likewise. + (__arm_vsriq_m_n_s8): Define intrinsic. + (__arm_vsubq_m_s8): Likewise. + (__arm_vqshluq_m_n_s8): Likewise. + (__arm_vabavq_p_s8): Likewise. + (__arm_vsriq_m_n_u8): Likewise. + (__arm_vshlq_m_u8): Likewise. + (__arm_vsubq_m_u8): Likewise. + (__arm_vabavq_p_u8): Likewise. + (__arm_vshlq_m_s8): Likewise. + (__arm_vsriq_m_n_s16): Likewise. + (__arm_vsubq_m_s16): Likewise. + (__arm_vqshluq_m_n_s16): Likewise. + (__arm_vabavq_p_s16): Likewise. + (__arm_vsriq_m_n_u16): Likewise. + (__arm_vshlq_m_u16): Likewise. + (__arm_vsubq_m_u16): Likewise. + (__arm_vabavq_p_u16): Likewise. + (__arm_vshlq_m_s16): Likewise. + (__arm_vsriq_m_n_s32): Likewise. + (__arm_vsubq_m_s32): Likewise. + (__arm_vqshluq_m_n_s32): Likewise. + (__arm_vabavq_p_s32): Likewise. + (__arm_vsriq_m_n_u32): Likewise. + (__arm_vshlq_m_u32): Likewise. + (__arm_vsubq_m_u32): Likewise. + (__arm_vabavq_p_u32): Likewise. + (__arm_vshlq_m_s32): Likewise. + (__arm_vcvtq_m_n_f16_u16): Likewise. + (__arm_vcvtq_m_n_f16_s16): Likewise. + (__arm_vcvtq_m_n_f32_u32): Likewise. + (__arm_vcvtq_m_n_f32_s32): Likewise. + (vcvtq_m_n): Define polymorphic variant. + (vqshluq_m_n): Likewise. + (vshlq_m): Likewise. + (vsriq_m_n): Likewise. + (vsubq_m): Likewise. + (vabavq_p): Likewise. + * config/arm/arm_mve_builtins.def + (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. + (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. + (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. + (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. + * config/arm/mve.md (VABAVQ_P): Define iterator. + (VSHLQ_M): Likewise. + (VSRIQ_M_N): Likewise. + (VSUBQ_M): Likewise. + (VCVTQ_M_N_TO_F): Likewise. + (mve_vabavq_p_): Define RTL pattern. + (mve_vqshluq_m_n_s): Likewise. + (mve_vshlq_m_): Likewise. + (mve_vsriq_m_n_): Likewise. + (mve_vsubq_m_): Likewise. + (mve_vcvtq_m_n_to_f_): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. (vrmlsldavhaq_s32): Likewise. (vrmlsldavhaxq_s32): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index af4f3b6..26f0379 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -523,6 +523,62 @@ arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS \ (arm_ternop_none_none_none_none_qualifiers) +static enum arm_type_qualifiers +arm_quadop_unone_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none, + qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_none_none_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_none_none_none_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, + qualifier_immediate, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_none_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_none_none_unone_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_immediate, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_none, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_none_unone_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 363f9ca..e236bff 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1232,6 +1232,37 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vqmovnbq_m_u32(__a, __b, __p) __arm_vqmovnbq_m_u32(__a, __b, __p) #define vqmovntq_m_u32(__a, __b, __p) __arm_vqmovntq_m_u32(__a, __b, __p) #define vrev32q_m_u16(__inactive, __a, __p) __arm_vrev32q_m_u16(__inactive, __a, __p) +#define vsriq_m_n_s8(__a, __b, __imm, __p) __arm_vsriq_m_n_s8(__a, __b, __imm, __p) +#define vsubq_m_s8(__inactive, __a, __b, __p) __arm_vsubq_m_s8(__inactive, __a, __b, __p) +#define vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) +#define vqshluq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s8(__inactive, __a, __imm, __p) +#define vabavq_p_s8(__a, __b, __c, __p) __arm_vabavq_p_s8(__a, __b, __c, __p) +#define vsriq_m_n_u8(__a, __b, __imm, __p) __arm_vsriq_m_n_u8(__a, __b, __imm, __p) +#define vshlq_m_u8(__inactive, __a, __b, __p) __arm_vshlq_m_u8(__inactive, __a, __b, __p) +#define vsubq_m_u8(__inactive, __a, __b, __p) __arm_vsubq_m_u8(__inactive, __a, __b, __p) +#define vabavq_p_u8(__a, __b, __c, __p) __arm_vabavq_p_u8(__a, __b, __c, __p) +#define vshlq_m_s8(__inactive, __a, __b, __p) __arm_vshlq_m_s8(__inactive, __a, __b, __p) +#define vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) +#define vsriq_m_n_s16(__a, __b, __imm, __p) __arm_vsriq_m_n_s16(__a, __b, __imm, __p) +#define vsubq_m_s16(__inactive, __a, __b, __p) __arm_vsubq_m_s16(__inactive, __a, __b, __p) +#define vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) +#define vqshluq_m_n_s16(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s16(__inactive, __a, __imm, __p) +#define vabavq_p_s16(__a, __b, __c, __p) __arm_vabavq_p_s16(__a, __b, __c, __p) +#define vsriq_m_n_u16(__a, __b, __imm, __p) __arm_vsriq_m_n_u16(__a, __b, __imm, __p) +#define vshlq_m_u16(__inactive, __a, __b, __p) __arm_vshlq_m_u16(__inactive, __a, __b, __p) +#define vsubq_m_u16(__inactive, __a, __b, __p) __arm_vsubq_m_u16(__inactive, __a, __b, __p) +#define vabavq_p_u16(__a, __b, __c, __p) __arm_vabavq_p_u16(__a, __b, __c, __p) +#define vshlq_m_s16(__inactive, __a, __b, __p) __arm_vshlq_m_s16(__inactive, __a, __b, __p) +#define vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) +#define vsriq_m_n_s32(__a, __b, __imm, __p) __arm_vsriq_m_n_s32(__a, __b, __imm, __p) +#define vsubq_m_s32(__inactive, __a, __b, __p) __arm_vsubq_m_s32(__inactive, __a, __b, __p) +#define vqshluq_m_n_s32(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s32(__inactive, __a, __imm, __p) +#define vabavq_p_s32(__a, __b, __c, __p) __arm_vabavq_p_s32(__a, __b, __c, __p) +#define vsriq_m_n_u32(__a, __b, __imm, __p) __arm_vsriq_m_n_u32(__a, __b, __imm, __p) +#define vshlq_m_u32(__inactive, __a, __b, __p) __arm_vshlq_m_u32(__inactive, __a, __b, __p) +#define vsubq_m_u32(__inactive, __a, __b, __p) __arm_vsubq_m_u32(__inactive, __a, __b, __p) +#define vabavq_p_u32(__a, __b, __c, __p) __arm_vabavq_p_u32(__a, __b, __c, __p) +#define vshlq_m_s32(__inactive, __a, __b, __p) __arm_vshlq_m_s32(__inactive, __a, __b, __p) #endif __extension__ extern __inline void @@ -7696,6 +7727,196 @@ __arm_vrev32q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) { return __builtin_mve_vrev32q_m_uv8hi (__inactive, __a, __p); } + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s8 (uint8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s8 (uint32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s16 (uint16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s16 (uint32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s32 (uint32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s32 (uint32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv4si (__inactive, __a, __b, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -9376,6 +9597,34 @@ __arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p); +} + #endif enum { @@ -11008,6 +11257,15 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) +#define vcvtq_m_n(p0,p1,p2,p3) __arm_vcvtq_m_n(p0,p1,p2,p3) +#define __arm_vcvtq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_n_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_n_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_n_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcvtq_m_n_f32_u32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + #define vabsq_m(p0,p1,p2) __arm_vabsq_m(p0,p1,p2) #define __arm_vabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -11050,19 +11308,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) -#define vcmpeqq_m_n(p0,p1,p2) __arm_vcmpeqq_m_n(p0,p1,p2) -#define __arm_vcmpeqq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) - #define vrndxq_m(p0,p1,p2) __arm_vrndxq_m(p0,p1,p2) #define __arm_vrndxq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -13387,6 +13632,30 @@ extern void *__ARM_undef; #define vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p(p0,p1,p2) #define __arm_vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p_s32(p0,p1,p2) +#define vsubq_m(p0,p1,p2,p3) __arm_vsubq_m(p0,p1,p2,p3) +#define __arm_vsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vabavq_p(p0,p1,p2,p3) __arm_vabavq_p(p0,p1,p2,p3) +#define __arm_vabavq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabavq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabavq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabavq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabavq_p_u8(__p0, __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabavq_p_u16(__p0, __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabavq_p_u32(__p0, __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + #endif /* MVE Integer. */ #define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) @@ -13427,6 +13696,37 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) +#define vqshluq_m(p0,p1,p2,p3) __arm_vqshluq_m(p0,p1,p2,p3) +#define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshluq_m_n_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshluq_m_n_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshluq_m_n_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vshlq_m(p0,p1,p2,p3) __arm_vshlq_m(p0,p1,p2,p3) +#define __arm_vshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3) +#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + #ifdef __cplusplus } #endif diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index f625eed..c7d64ff 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -502,3 +502,14 @@ VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsriq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsriq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_u, v16qi, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vcvtq_m_n_to_f_u, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_to_f_s, v8hf, v4sf) +VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshluq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index dc7c3cb..b65849c 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -140,7 +140,10 @@ VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U - VCVTQ_M_N_FROM_F_U]) + VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S + VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S + VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U + VCVTQ_M_N_TO_F_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -244,7 +247,11 @@ (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s") (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u") (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u") - (VCVTQ_M_N_FROM_F_S "s")]) + (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u") + (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u") + (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s") + (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s") + (VCVTQ_M_N_TO_F_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -407,6 +414,11 @@ (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S]) (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U]) (define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S]) +(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U]) +(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U]) +(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U]) +(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S]) +(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -5551,7 +5563,7 @@ VSHRNTQ_N)) ] "TARGET_HAVE_MVE" - "vshrnt.i%# %q0, %q2, %3" + "vshrnt.i%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") ]) @@ -5567,7 +5579,7 @@ VCVTMQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtmt.%#.f%# %q0, %q2" + "vpst\;vcvtmt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5583,7 +5595,7 @@ VCVTPQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtpt.%#.f%# %q0, %q2" + "vpst\;vcvtpt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5599,7 +5611,7 @@ VCVTNQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtnt.%#.f%# %q0, %q2" + "vpst\;vcvtnt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5616,7 +5628,7 @@ VCVTQ_M_N_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%# %q0, %q2, %3" + "vpst\;vcvtt.%#.f%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5648,7 +5660,7 @@ VCVTQ_M_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%# %q0, %q2" + "vpst\;vcvtt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5683,3 +5695,101 @@ "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" [(set_attr "type" "mve_move") ]) + +;; +;; [vabavq_p_s, vabavq_p_u]) +;; +(define_insn "mve_vabavq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VABAVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vabavt.%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshluq_m_n_s]) +;; +(define_insn "mve_vqshluq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_7" "Ra") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHLUQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\n\tvqshlut.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move")]) + +;; +;; [vshlq_m_s, vshlq_m_u]) +;; +(define_insn "mve_vshlq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHLQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move")]) + +;; +;; [vsriq_m_n_s, vsriq_m_n_u]) +;; +(define_insn "mve_vsriq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSRIQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsrit.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move")]) + +;; +;; [vsubq_m_u, vsubq_m_s]) +;; +(define_insn "mve_vsubq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSUBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsubt.i%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move")]) + +;; +;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) +;; +(define_insn "mve_vcvtq_m_n_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_16" "Rd") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCVTQ_M_N_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtt.f%#.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c0777a3..f4e117c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,42 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c new file mode 100644 index 0000000..c9d9f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vabavq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s16" } } */ + +uint32_t +foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c new file mode 100644 index 0000000..a5b1da8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vabavq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c new file mode 100644 index 0000000..15b9552 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vabavq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s8" } } */ + +uint32_t +foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c new file mode 100644 index 0000000..1c27b6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vabavq_p_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c new file mode 100644 index 0000000..c50fe7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vabavq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c new file mode 100644 index 0000000..0566222 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vabavq_p_u8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c new file mode 100644 index 0000000..e5b5e9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f16_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c new file mode 100644 index 0000000..271fb1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f16_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c new file mode 100644 index 0000000..280c510 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f32_s32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c new file mode 100644 index 0000000..691756b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f32_u32 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c new file mode 100644 index 0000000..03016b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s16 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshluq_m (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c new file mode 100644 index 0000000..3f812e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s32 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshluq_m (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c new file mode 100644 index 0000000..59c0108 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s8 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshluq_m (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c new file mode 100644 index 0000000..26b664d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c new file mode 100644 index 0000000..2bc8336 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c new file mode 100644 index 0000000..5dec31e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c new file mode 100644 index 0000000..d4e42d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c new file mode 100644 index 0000000..8c0b62d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c new file mode 100644 index 0000000..429b2f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c new file mode 100644 index 0000000..041cc72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsriq_m_n_s16 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c new file mode 100644 index 0000000..52cd978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsriq_m_n_s32 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c new file mode 100644 index 0000000..208f8dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsriq_m_n_s8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c new file mode 100644 index 0000000..c1a1c4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsriq_m_n_u16 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c new file mode 100644 index 0000000..3524c50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsriq_m_n_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c new file mode 100644 index 0000000..4636544 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsriq_m_n_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c new file mode 100644 index 0000000..142b91f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsubq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c new file mode 100644 index 0000000..d82af8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsubq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c new file mode 100644 index 0000000..182b7c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsubq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c new file mode 100644 index 0000000..abafd6c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsubq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c new file mode 100644 index 0000000..dbd8341 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsubq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c new file mode 100644 index 0000000..3acbefb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsubq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ -- cgit v1.1 From 8eb3b6b9cf2e285450fc5efc98a63cf717d2b002 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 16:58:10 +0000 Subject: [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. This patch supports following MVE ACLE intrinsics with quaternary operands. vabdq_m_s8, vabdq_m_s32, vabdq_m_s16, vabdq_m_u8, vabdq_m_u32, vabdq_m_u16, vaddq_m_n_s8, vaddq_m_n_s32, vaddq_m_n_s16, vaddq_m_n_u8, vaddq_m_n_u32, vaddq_m_n_u16, vaddq_m_s8, vaddq_m_s32, vaddq_m_s16, vaddq_m_u8, vaddq_m_u32, vaddq_m_u16, vandq_m_s8, vandq_m_s32, vandq_m_s16, vandq_m_u8, vandq_m_u32, vandq_m_u16, vbicq_m_s8, vbicq_m_s32, vbicq_m_s16, vbicq_m_u8, vbicq_m_u32, vbicq_m_u16, vbrsrq_m_n_s8, vbrsrq_m_n_s32, vbrsrq_m_n_s16, vbrsrq_m_n_u8, vbrsrq_m_n_u32, vbrsrq_m_n_u16, vcaddq_rot270_m_s8, vcaddq_rot270_m_s32, vcaddq_rot270_m_s16, vcaddq_rot270_m_u8, vcaddq_rot270_m_u32, vcaddq_rot270_m_u16, vcaddq_rot90_m_s8, vcaddq_rot90_m_s32, vcaddq_rot90_m_s16, vcaddq_rot90_m_u8, vcaddq_rot90_m_u32, vcaddq_rot90_m_u16, veorq_m_s8, veorq_m_s32, veorq_m_s16, veorq_m_u8, veorq_m_u32, veorq_m_u16, vhaddq_m_n_s8, vhaddq_m_n_s32, vhaddq_m_n_s16, vhaddq_m_n_u8, vhaddq_m_n_u32, vhaddq_m_n_u16, vhaddq_m_s8, vhaddq_m_s32, vhaddq_m_s16, vhaddq_m_u8, vhaddq_m_u32, vhaddq_m_u16, vhcaddq_rot270_m_s8, vhcaddq_rot270_m_s32, vhcaddq_rot270_m_s16, vhcaddq_rot90_m_s8, vhcaddq_rot90_m_s32, vhcaddq_rot90_m_s16, vhsubq_m_n_s8, vhsubq_m_n_s32, vhsubq_m_n_s16, vhsubq_m_n_u8, vhsubq_m_n_u32, vhsubq_m_n_u16, vhsubq_m_s8, vhsubq_m_s32, vhsubq_m_s16, vhsubq_m_u8, vhsubq_m_u32, vhsubq_m_u16, vmaxq_m_s8, vmaxq_m_s32, vmaxq_m_s16, vmaxq_m_u8, vmaxq_m_u32, vmaxq_m_u16, vminq_m_s8, vminq_m_s32, vminq_m_s16, vminq_m_u8, vminq_m_u32, vminq_m_u16, vmladavaq_p_s8, vmladavaq_p_s32, vmladavaq_p_s16, vmladavaq_p_u8, vmladavaq_p_u32, vmladavaq_p_u16, vmladavaxq_p_s8, vmladavaxq_p_s32, vmladavaxq_p_s16, vmlaq_m_n_s8, vmlaq_m_n_s32, vmlaq_m_n_s16, vmlaq_m_n_u8, vmlaq_m_n_u32, vmlaq_m_n_u16, vmlasq_m_n_s8, vmlasq_m_n_s32, vmlasq_m_n_s16, vmlasq_m_n_u8, vmlasq_m_n_u32, vmlasq_m_n_u16, vmlsdavaq_p_s8, vmlsdavaq_p_s32, vmlsdavaq_p_s16, vmlsdavaxq_p_s8, vmlsdavaxq_p_s32, vmlsdavaxq_p_s16, vmulhq_m_s8, vmulhq_m_s32, vmulhq_m_s16, vmulhq_m_u8, vmulhq_m_u32, vmulhq_m_u16, vmullbq_int_m_s8, vmullbq_int_m_s32, vmullbq_int_m_s16, vmullbq_int_m_u8, vmullbq_int_m_u32, vmullbq_int_m_u16, vmulltq_int_m_s8, vmulltq_int_m_s32, vmulltq_int_m_s16, vmulltq_int_m_u8, vmulltq_int_m_u32, vmulltq_int_m_u16, vmulq_m_n_s8, vmulq_m_n_s32, vmulq_m_n_s16, vmulq_m_n_u8, vmulq_m_n_u32, vmulq_m_n_u16, vmulq_m_s8, vmulq_m_s32, vmulq_m_s16, vmulq_m_u8, vmulq_m_u32, vmulq_m_u16, vornq_m_s8, vornq_m_s32, vornq_m_s16, vornq_m_u8, vornq_m_u32, vornq_m_u16, vorrq_m_s8, vorrq_m_s32, vorrq_m_s16, vorrq_m_u8, vorrq_m_u32, vorrq_m_u16, vqaddq_m_n_s8, vqaddq_m_n_s32, vqaddq_m_n_s16, vqaddq_m_n_u8, vqaddq_m_n_u32, vqaddq_m_n_u16, vqaddq_m_s8, vqaddq_m_s32, vqaddq_m_s16, vqaddq_m_u8, vqaddq_m_u32, vqaddq_m_u16, vqdmladhq_m_s8, vqdmladhq_m_s32, vqdmladhq_m_s16, vqdmladhxq_m_s8, vqdmladhxq_m_s32, vqdmladhxq_m_s16, vqdmlahq_m_n_s8, vqdmlahq_m_n_s32, vqdmlahq_m_n_s16, vqdmlahq_m_n_u8, vqdmlahq_m_n_u32, vqdmlahq_m_n_u16, vqdmlsdhq_m_s8, vqdmlsdhq_m_s32, vqdmlsdhq_m_s16, vqdmlsdhxq_m_s8, vqdmlsdhxq_m_s32, vqdmlsdhxq_m_s16, vqdmulhq_m_n_s8, vqdmulhq_m_n_s32, vqdmulhq_m_n_s16, vqdmulhq_m_s8, vqdmulhq_m_s32, vqdmulhq_m_s16, vqrdmladhq_m_s8, vqrdmladhq_m_s32, vqrdmladhq_m_s16, vqrdmladhxq_m_s8, vqrdmladhxq_m_s32, vqrdmladhxq_m_s16, vqrdmlahq_m_n_s8, vqrdmlahq_m_n_s32, vqrdmlahq_m_n_s16, vqrdmlahq_m_n_u8, vqrdmlahq_m_n_u32, vqrdmlahq_m_n_u16, vqrdmlashq_m_n_s8, vqrdmlashq_m_n_s32, vqrdmlashq_m_n_s16, vqrdmlashq_m_n_u8, vqrdmlashq_m_n_u32, vqrdmlashq_m_n_u16, vqrdmlsdhq_m_s8, vqrdmlsdhq_m_s32, vqrdmlsdhq_m_s16, vqrdmlsdhxq_m_s8, vqrdmlsdhxq_m_s32, vqrdmlsdhxq_m_s16, vqrdmulhq_m_n_s8, vqrdmulhq_m_n_s32, vqrdmulhq_m_n_s16, vqrdmulhq_m_s8, vqrdmulhq_m_s32, vqrdmulhq_m_s16, vqrshlq_m_s8, vqrshlq_m_s32, vqrshlq_m_s16, vqrshlq_m_u8, vqrshlq_m_u32, vqrshlq_m_u16, vqshlq_m_n_s8, vqshlq_m_n_s32, vqshlq_m_n_s16, vqshlq_m_n_u8, vqshlq_m_n_u32, vqshlq_m_n_u16, vqshlq_m_s8, vqshlq_m_s32, vqshlq_m_s16, vqshlq_m_u8, vqshlq_m_u32, vqshlq_m_u16, vqsubq_m_n_s8, vqsubq_m_n_s32, vqsubq_m_n_s16, vqsubq_m_n_u8, vqsubq_m_n_u32, vqsubq_m_n_u16, vqsubq_m_s8, vqsubq_m_s32, vqsubq_m_s16, vqsubq_m_u8, vqsubq_m_u32, vqsubq_m_u16, vrhaddq_m_s8, vrhaddq_m_s32, vrhaddq_m_s16, vrhaddq_m_u8, vrhaddq_m_u32, vrhaddq_m_u16, vrmulhq_m_s8, vrmulhq_m_s32, vrmulhq_m_s16, vrmulhq_m_u8, vrmulhq_m_u32, vrmulhq_m_u16, vrshlq_m_s8, vrshlq_m_s32, vrshlq_m_s16, vrshlq_m_u8, vrshlq_m_u32, vrshlq_m_u16, vrshrq_m_n_s8, vrshrq_m_n_s32, vrshrq_m_n_s16, vrshrq_m_n_u8, vrshrq_m_n_u32, vrshrq_m_n_u16, vshlq_m_n_s8, vshlq_m_n_s32, vshlq_m_n_s16, vshlq_m_n_u8, vshlq_m_n_u32, vshlq_m_n_u16, vshrq_m_n_s8, vshrq_m_n_s32, vshrq_m_n_s16, vshrq_m_n_u8, vshrq_m_n_u32, vshrq_m_n_u16, vsliq_m_n_s8, vsliq_m_n_s32, vsliq_m_n_s16, vsliq_m_n_u8, vsliq_m_n_u32, vsliq_m_n_u16, vsubq_m_n_s8, vsubq_m_n_s32, vsubq_m_n_s16, vsubq_m_n_u8, vsubq_m_n_u32, vsubq_m_n_u16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vabdq_m_s8): Define macro. (vabdq_m_s32): Likewise. (vabdq_m_s16): Likewise. (vabdq_m_u8): Likewise. (vabdq_m_u32): Likewise. (vabdq_m_u16): Likewise. (vaddq_m_n_s8): Likewise. (vaddq_m_n_s32): Likewise. (vaddq_m_n_s16): Likewise. (vaddq_m_n_u8): Likewise. (vaddq_m_n_u32): Likewise. (vaddq_m_n_u16): Likewise. (vaddq_m_s8): Likewise. (vaddq_m_s32): Likewise. (vaddq_m_s16): Likewise. (vaddq_m_u8): Likewise. (vaddq_m_u32): Likewise. (vaddq_m_u16): Likewise. (vandq_m_s8): Likewise. (vandq_m_s32): Likewise. (vandq_m_s16): Likewise. (vandq_m_u8): Likewise. (vandq_m_u32): Likewise. (vandq_m_u16): Likewise. (vbicq_m_s8): Likewise. (vbicq_m_s32): Likewise. (vbicq_m_s16): Likewise. (vbicq_m_u8): Likewise. (vbicq_m_u32): Likewise. (vbicq_m_u16): Likewise. (vbrsrq_m_n_s8): Likewise. (vbrsrq_m_n_s32): Likewise. (vbrsrq_m_n_s16): Likewise. (vbrsrq_m_n_u8): Likewise. (vbrsrq_m_n_u32): Likewise. (vbrsrq_m_n_u16): Likewise. (vcaddq_rot270_m_s8): Likewise. (vcaddq_rot270_m_s32): Likewise. (vcaddq_rot270_m_s16): Likewise. (vcaddq_rot270_m_u8): Likewise. (vcaddq_rot270_m_u32): Likewise. (vcaddq_rot270_m_u16): Likewise. (vcaddq_rot90_m_s8): Likewise. (vcaddq_rot90_m_s32): Likewise. (vcaddq_rot90_m_s16): Likewise. (vcaddq_rot90_m_u8): Likewise. (vcaddq_rot90_m_u32): Likewise. (vcaddq_rot90_m_u16): Likewise. (veorq_m_s8): Likewise. (veorq_m_s32): Likewise. (veorq_m_s16): Likewise. (veorq_m_u8): Likewise. (veorq_m_u32): Likewise. (veorq_m_u16): Likewise. (vhaddq_m_n_s8): Likewise. (vhaddq_m_n_s32): Likewise. (vhaddq_m_n_s16): Likewise. (vhaddq_m_n_u8): Likewise. (vhaddq_m_n_u32): Likewise. (vhaddq_m_n_u16): Likewise. (vhaddq_m_s8): Likewise. (vhaddq_m_s32): Likewise. (vhaddq_m_s16): Likewise. (vhaddq_m_u8): Likewise. (vhaddq_m_u32): Likewise. (vhaddq_m_u16): Likewise. (vhcaddq_rot270_m_s8): Likewise. (vhcaddq_rot270_m_s32): Likewise. (vhcaddq_rot270_m_s16): Likewise. (vhcaddq_rot90_m_s8): Likewise. (vhcaddq_rot90_m_s32): Likewise. (vhcaddq_rot90_m_s16): Likewise. (vhsubq_m_n_s8): Likewise. (vhsubq_m_n_s32): Likewise. (vhsubq_m_n_s16): Likewise. (vhsubq_m_n_u8): Likewise. (vhsubq_m_n_u32): Likewise. (vhsubq_m_n_u16): Likewise. (vhsubq_m_s8): Likewise. (vhsubq_m_s32): Likewise. (vhsubq_m_s16): Likewise. (vhsubq_m_u8): Likewise. (vhsubq_m_u32): Likewise. (vhsubq_m_u16): Likewise. (vmaxq_m_s8): Likewise. (vmaxq_m_s32): Likewise. (vmaxq_m_s16): Likewise. (vmaxq_m_u8): Likewise. (vmaxq_m_u32): Likewise. (vmaxq_m_u16): Likewise. (vminq_m_s8): Likewise. (vminq_m_s32): Likewise. (vminq_m_s16): Likewise. (vminq_m_u8): Likewise. (vminq_m_u32): Likewise. (vminq_m_u16): Likewise. (vmladavaq_p_s8): Likewise. (vmladavaq_p_s32): Likewise. (vmladavaq_p_s16): Likewise. (vmladavaq_p_u8): Likewise. (vmladavaq_p_u32): Likewise. (vmladavaq_p_u16): Likewise. (vmladavaxq_p_s8): Likewise. (vmladavaxq_p_s32): Likewise. (vmladavaxq_p_s16): Likewise. (vmlaq_m_n_s8): Likewise. (vmlaq_m_n_s32): Likewise. (vmlaq_m_n_s16): Likewise. (vmlaq_m_n_u8): Likewise. (vmlaq_m_n_u32): Likewise. (vmlaq_m_n_u16): Likewise. (vmlasq_m_n_s8): Likewise. (vmlasq_m_n_s32): Likewise. (vmlasq_m_n_s16): Likewise. (vmlasq_m_n_u8): Likewise. (vmlasq_m_n_u32): Likewise. (vmlasq_m_n_u16): Likewise. (vmlsdavaq_p_s8): Likewise. (vmlsdavaq_p_s32): Likewise. (vmlsdavaq_p_s16): Likewise. (vmlsdavaxq_p_s8): Likewise. (vmlsdavaxq_p_s32): Likewise. (vmlsdavaxq_p_s16): Likewise. (vmulhq_m_s8): Likewise. (vmulhq_m_s32): Likewise. (vmulhq_m_s16): Likewise. (vmulhq_m_u8): Likewise. (vmulhq_m_u32): Likewise. (vmulhq_m_u16): Likewise. (vmullbq_int_m_s8): Likewise. (vmullbq_int_m_s32): Likewise. (vmullbq_int_m_s16): Likewise. (vmullbq_int_m_u8): Likewise. (vmullbq_int_m_u32): Likewise. (vmullbq_int_m_u16): Likewise. (vmulltq_int_m_s8): Likewise. (vmulltq_int_m_s32): Likewise. (vmulltq_int_m_s16): Likewise. (vmulltq_int_m_u8): Likewise. (vmulltq_int_m_u32): Likewise. (vmulltq_int_m_u16): Likewise. (vmulq_m_n_s8): Likewise. (vmulq_m_n_s32): Likewise. (vmulq_m_n_s16): Likewise. (vmulq_m_n_u8): Likewise. (vmulq_m_n_u32): Likewise. (vmulq_m_n_u16): Likewise. (vmulq_m_s8): Likewise. (vmulq_m_s32): Likewise. (vmulq_m_s16): Likewise. (vmulq_m_u8): Likewise. (vmulq_m_u32): Likewise. (vmulq_m_u16): Likewise. (vornq_m_s8): Likewise. (vornq_m_s32): Likewise. (vornq_m_s16): Likewise. (vornq_m_u8): Likewise. (vornq_m_u32): Likewise. (vornq_m_u16): Likewise. (vorrq_m_s8): Likewise. (vorrq_m_s32): Likewise. (vorrq_m_s16): Likewise. (vorrq_m_u8): Likewise. (vorrq_m_u32): Likewise. (vorrq_m_u16): Likewise. (vqaddq_m_n_s8): Likewise. (vqaddq_m_n_s32): Likewise. (vqaddq_m_n_s16): Likewise. (vqaddq_m_n_u8): Likewise. (vqaddq_m_n_u32): Likewise. (vqaddq_m_n_u16): Likewise. (vqaddq_m_s8): Likewise. (vqaddq_m_s32): Likewise. (vqaddq_m_s16): Likewise. (vqaddq_m_u8): Likewise. (vqaddq_m_u32): Likewise. (vqaddq_m_u16): Likewise. (vqdmladhq_m_s8): Likewise. (vqdmladhq_m_s32): Likewise. (vqdmladhq_m_s16): Likewise. (vqdmladhxq_m_s8): Likewise. (vqdmladhxq_m_s32): Likewise. (vqdmladhxq_m_s16): Likewise. (vqdmlahq_m_n_s8): Likewise. (vqdmlahq_m_n_s32): Likewise. (vqdmlahq_m_n_s16): Likewise. (vqdmlahq_m_n_u8): Likewise. (vqdmlahq_m_n_u32): Likewise. (vqdmlahq_m_n_u16): Likewise. (vqdmlsdhq_m_s8): Likewise. (vqdmlsdhq_m_s32): Likewise. (vqdmlsdhq_m_s16): Likewise. (vqdmlsdhxq_m_s8): Likewise. (vqdmlsdhxq_m_s32): Likewise. (vqdmlsdhxq_m_s16): Likewise. (vqdmulhq_m_n_s8): Likewise. (vqdmulhq_m_n_s32): Likewise. (vqdmulhq_m_n_s16): Likewise. (vqdmulhq_m_s8): Likewise. (vqdmulhq_m_s32): Likewise. (vqdmulhq_m_s16): Likewise. (vqrdmladhq_m_s8): Likewise. (vqrdmladhq_m_s32): Likewise. (vqrdmladhq_m_s16): Likewise. (vqrdmladhxq_m_s8): Likewise. (vqrdmladhxq_m_s32): Likewise. (vqrdmladhxq_m_s16): Likewise. (vqrdmlahq_m_n_s8): Likewise. (vqrdmlahq_m_n_s32): Likewise. (vqrdmlahq_m_n_s16): Likewise. (vqrdmlahq_m_n_u8): Likewise. (vqrdmlahq_m_n_u32): Likewise. (vqrdmlahq_m_n_u16): Likewise. (vqrdmlashq_m_n_s8): Likewise. (vqrdmlashq_m_n_s32): Likewise. (vqrdmlashq_m_n_s16): Likewise. (vqrdmlashq_m_n_u8): Likewise. (vqrdmlashq_m_n_u32): Likewise. (vqrdmlashq_m_n_u16): Likewise. (vqrdmlsdhq_m_s8): Likewise. (vqrdmlsdhq_m_s32): Likewise. (vqrdmlsdhq_m_s16): Likewise. (vqrdmlsdhxq_m_s8): Likewise. (vqrdmlsdhxq_m_s32): Likewise. (vqrdmlsdhxq_m_s16): Likewise. (vqrdmulhq_m_n_s8): Likewise. (vqrdmulhq_m_n_s32): Likewise. (vqrdmulhq_m_n_s16): Likewise. (vqrdmulhq_m_s8): Likewise. (vqrdmulhq_m_s32): Likewise. (vqrdmulhq_m_s16): Likewise. (vqrshlq_m_s8): Likewise. (vqrshlq_m_s32): Likewise. (vqrshlq_m_s16): Likewise. (vqrshlq_m_u8): Likewise. (vqrshlq_m_u32): Likewise. (vqrshlq_m_u16): Likewise. (vqshlq_m_n_s8): Likewise. (vqshlq_m_n_s32): Likewise. (vqshlq_m_n_s16): Likewise. (vqshlq_m_n_u8): Likewise. (vqshlq_m_n_u32): Likewise. (vqshlq_m_n_u16): Likewise. (vqshlq_m_s8): Likewise. (vqshlq_m_s32): Likewise. (vqshlq_m_s16): Likewise. (vqshlq_m_u8): Likewise. (vqshlq_m_u32): Likewise. (vqshlq_m_u16): Likewise. (vqsubq_m_n_s8): Likewise. (vqsubq_m_n_s32): Likewise. (vqsubq_m_n_s16): Likewise. (vqsubq_m_n_u8): Likewise. (vqsubq_m_n_u32): Likewise. (vqsubq_m_n_u16): Likewise. (vqsubq_m_s8): Likewise. (vqsubq_m_s32): Likewise. (vqsubq_m_s16): Likewise. (vqsubq_m_u8): Likewise. (vqsubq_m_u32): Likewise. (vqsubq_m_u16): Likewise. (vrhaddq_m_s8): Likewise. (vrhaddq_m_s32): Likewise. (vrhaddq_m_s16): Likewise. (vrhaddq_m_u8): Likewise. (vrhaddq_m_u32): Likewise. (vrhaddq_m_u16): Likewise. (vrmulhq_m_s8): Likewise. (vrmulhq_m_s32): Likewise. (vrmulhq_m_s16): Likewise. (vrmulhq_m_u8): Likewise. (vrmulhq_m_u32): Likewise. (vrmulhq_m_u16): Likewise. (vrshlq_m_s8): Likewise. (vrshlq_m_s32): Likewise. (vrshlq_m_s16): Likewise. (vrshlq_m_u8): Likewise. (vrshlq_m_u32): Likewise. (vrshlq_m_u16): Likewise. (vrshrq_m_n_s8): Likewise. (vrshrq_m_n_s32): Likewise. (vrshrq_m_n_s16): Likewise. (vrshrq_m_n_u8): Likewise. (vrshrq_m_n_u32): Likewise. (vrshrq_m_n_u16): Likewise. (vshlq_m_n_s8): Likewise. (vshlq_m_n_s32): Likewise. (vshlq_m_n_s16): Likewise. (vshlq_m_n_u8): Likewise. (vshlq_m_n_u32): Likewise. (vshlq_m_n_u16): Likewise. (vshrq_m_n_s8): Likewise. (vshrq_m_n_s32): Likewise. (vshrq_m_n_s16): Likewise. (vshrq_m_n_u8): Likewise. (vshrq_m_n_u32): Likewise. (vshrq_m_n_u16): Likewise. (vsliq_m_n_s8): Likewise. (vsliq_m_n_s32): Likewise. (vsliq_m_n_s16): Likewise. (vsliq_m_n_u8): Likewise. (vsliq_m_n_u32): Likewise. (vsliq_m_n_u16): Likewise. (vsubq_m_n_s8): Likewise. (vsubq_m_n_s32): Likewise. (vsubq_m_n_s16): Likewise. (vsubq_m_n_u8): Likewise. (vsubq_m_n_u32): Likewise. (vsubq_m_n_u16): Likewise. (__arm_vabdq_m_s8): Define intrinsic. (__arm_vabdq_m_s32): Likewise. (__arm_vabdq_m_s16): Likewise. (__arm_vabdq_m_u8): Likewise. (__arm_vabdq_m_u32): Likewise. (__arm_vabdq_m_u16): Likewise. (__arm_vaddq_m_n_s8): Likewise. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m_s8): Likewise. (__arm_vaddq_m_s32): Likewise. (__arm_vaddq_m_s16): Likewise. (__arm_vaddq_m_u8): Likewise. (__arm_vaddq_m_u32): Likewise. (__arm_vaddq_m_u16): Likewise. (__arm_vandq_m_s8): Likewise. (__arm_vandq_m_s32): Likewise. (__arm_vandq_m_s16): Likewise. (__arm_vandq_m_u8): Likewise. (__arm_vandq_m_u32): Likewise. (__arm_vandq_m_u16): Likewise. (__arm_vbicq_m_s8): Likewise. (__arm_vbicq_m_s32): Likewise. (__arm_vbicq_m_s16): Likewise. (__arm_vbicq_m_u8): Likewise. (__arm_vbicq_m_u32): Likewise. (__arm_vbicq_m_u16): Likewise. (__arm_vbrsrq_m_n_s8): Likewise. (__arm_vbrsrq_m_n_s32): Likewise. (__arm_vbrsrq_m_n_s16): Likewise. (__arm_vbrsrq_m_n_u8): Likewise. (__arm_vbrsrq_m_n_u32): Likewise. (__arm_vbrsrq_m_n_u16): Likewise. (__arm_vcaddq_rot270_m_s8): Likewise. (__arm_vcaddq_rot270_m_s32): Likewise. (__arm_vcaddq_rot270_m_s16): Likewise. (__arm_vcaddq_rot270_m_u8): Likewise. (__arm_vcaddq_rot270_m_u32): Likewise. (__arm_vcaddq_rot270_m_u16): Likewise. (__arm_vcaddq_rot90_m_s8): Likewise. (__arm_vcaddq_rot90_m_s32): Likewise. (__arm_vcaddq_rot90_m_s16): Likewise. (__arm_vcaddq_rot90_m_u8): Likewise. (__arm_vcaddq_rot90_m_u32): Likewise. (__arm_vcaddq_rot90_m_u16): Likewise. (__arm_veorq_m_s8): Likewise. (__arm_veorq_m_s32): Likewise. (__arm_veorq_m_s16): Likewise. (__arm_veorq_m_u8): Likewise. (__arm_veorq_m_u32): Likewise. (__arm_veorq_m_u16): Likewise. (__arm_vhaddq_m_n_s8): Likewise. (__arm_vhaddq_m_n_s32): Likewise. (__arm_vhaddq_m_n_s16): Likewise. (__arm_vhaddq_m_n_u8): Likewise. (__arm_vhaddq_m_n_u32): Likewise. (__arm_vhaddq_m_n_u16): Likewise. (__arm_vhaddq_m_s8): Likewise. (__arm_vhaddq_m_s32): Likewise. (__arm_vhaddq_m_s16): Likewise. (__arm_vhaddq_m_u8): Likewise. (__arm_vhaddq_m_u32): Likewise. (__arm_vhaddq_m_u16): Likewise. (__arm_vhcaddq_rot270_m_s8): Likewise. (__arm_vhcaddq_rot270_m_s32): Likewise. (__arm_vhcaddq_rot270_m_s16): Likewise. (__arm_vhcaddq_rot90_m_s8): Likewise. (__arm_vhcaddq_rot90_m_s32): Likewise. (__arm_vhcaddq_rot90_m_s16): Likewise. (__arm_vhsubq_m_n_s8): Likewise. (__arm_vhsubq_m_n_s32): Likewise. (__arm_vhsubq_m_n_s16): Likewise. (__arm_vhsubq_m_n_u8): Likewise. (__arm_vhsubq_m_n_u32): Likewise. (__arm_vhsubq_m_n_u16): Likewise. (__arm_vhsubq_m_s8): Likewise. (__arm_vhsubq_m_s32): Likewise. (__arm_vhsubq_m_s16): Likewise. (__arm_vhsubq_m_u8): Likewise. (__arm_vhsubq_m_u32): Likewise. (__arm_vhsubq_m_u16): Likewise. (__arm_vmaxq_m_s8): Likewise. (__arm_vmaxq_m_s32): Likewise. (__arm_vmaxq_m_s16): Likewise. (__arm_vmaxq_m_u8): Likewise. (__arm_vmaxq_m_u32): Likewise. (__arm_vmaxq_m_u16): Likewise. (__arm_vminq_m_s8): Likewise. (__arm_vminq_m_s32): Likewise. (__arm_vminq_m_s16): Likewise. (__arm_vminq_m_u8): Likewise. (__arm_vminq_m_u32): Likewise. (__arm_vminq_m_u16): Likewise. (__arm_vmladavaq_p_s8): Likewise. (__arm_vmladavaq_p_s32): Likewise. (__arm_vmladavaq_p_s16): Likewise. (__arm_vmladavaq_p_u8): Likewise. (__arm_vmladavaq_p_u32): Likewise. (__arm_vmladavaq_p_u16): Likewise. (__arm_vmladavaxq_p_s8): Likewise. (__arm_vmladavaxq_p_s32): Likewise. (__arm_vmladavaxq_p_s16): Likewise. (__arm_vmlaq_m_n_s8): Likewise. (__arm_vmlaq_m_n_s32): Likewise. (__arm_vmlaq_m_n_s16): Likewise. (__arm_vmlaq_m_n_u8): Likewise. (__arm_vmlaq_m_n_u32): Likewise. (__arm_vmlaq_m_n_u16): Likewise. (__arm_vmlasq_m_n_s8): Likewise. (__arm_vmlasq_m_n_s32): Likewise. (__arm_vmlasq_m_n_s16): Likewise. (__arm_vmlasq_m_n_u8): Likewise. (__arm_vmlasq_m_n_u32): Likewise. (__arm_vmlasq_m_n_u16): Likewise. (__arm_vmlsdavaq_p_s8): Likewise. (__arm_vmlsdavaq_p_s32): Likewise. (__arm_vmlsdavaq_p_s16): Likewise. (__arm_vmlsdavaxq_p_s8): Likewise. (__arm_vmlsdavaxq_p_s32): Likewise. (__arm_vmlsdavaxq_p_s16): Likewise. (__arm_vmulhq_m_s8): Likewise. (__arm_vmulhq_m_s32): Likewise. (__arm_vmulhq_m_s16): Likewise. (__arm_vmulhq_m_u8): Likewise. (__arm_vmulhq_m_u32): Likewise. (__arm_vmulhq_m_u16): Likewise. (__arm_vmullbq_int_m_s8): Likewise. (__arm_vmullbq_int_m_s32): Likewise. (__arm_vmullbq_int_m_s16): Likewise. (__arm_vmullbq_int_m_u8): Likewise. (__arm_vmullbq_int_m_u32): Likewise. (__arm_vmullbq_int_m_u16): Likewise. (__arm_vmulltq_int_m_s8): Likewise. (__arm_vmulltq_int_m_s32): Likewise. (__arm_vmulltq_int_m_s16): Likewise. (__arm_vmulltq_int_m_u8): Likewise. (__arm_vmulltq_int_m_u32): Likewise. (__arm_vmulltq_int_m_u16): Likewise. (__arm_vmulq_m_n_s8): Likewise. (__arm_vmulq_m_n_s32): Likewise. (__arm_vmulq_m_n_s16): Likewise. (__arm_vmulq_m_n_u8): Likewise. (__arm_vmulq_m_n_u32): Likewise. (__arm_vmulq_m_n_u16): Likewise. (__arm_vmulq_m_s8): Likewise. (__arm_vmulq_m_s32): Likewise. (__arm_vmulq_m_s16): Likewise. (__arm_vmulq_m_u8): Likewise. (__arm_vmulq_m_u32): Likewise. (__arm_vmulq_m_u16): Likewise. (__arm_vornq_m_s8): Likewise. (__arm_vornq_m_s32): Likewise. (__arm_vornq_m_s16): Likewise. (__arm_vornq_m_u8): Likewise. (__arm_vornq_m_u32): Likewise. (__arm_vornq_m_u16): Likewise. (__arm_vorrq_m_s8): Likewise. (__arm_vorrq_m_s32): Likewise. (__arm_vorrq_m_s16): Likewise. (__arm_vorrq_m_u8): Likewise. (__arm_vorrq_m_u32): Likewise. (__arm_vorrq_m_u16): Likewise. (__arm_vqaddq_m_n_s8): Likewise. (__arm_vqaddq_m_n_s32): Likewise. (__arm_vqaddq_m_n_s16): Likewise. (__arm_vqaddq_m_n_u8): Likewise. (__arm_vqaddq_m_n_u32): Likewise. (__arm_vqaddq_m_n_u16): Likewise. (__arm_vqaddq_m_s8): Likewise. (__arm_vqaddq_m_s32): Likewise. (__arm_vqaddq_m_s16): Likewise. (__arm_vqaddq_m_u8): Likewise. (__arm_vqaddq_m_u32): Likewise. (__arm_vqaddq_m_u16): Likewise. (__arm_vqdmladhq_m_s8): Likewise. (__arm_vqdmladhq_m_s32): Likewise. (__arm_vqdmladhq_m_s16): Likewise. (__arm_vqdmladhxq_m_s8): Likewise. (__arm_vqdmladhxq_m_s32): Likewise. (__arm_vqdmladhxq_m_s16): Likewise. (__arm_vqdmlahq_m_n_s8): Likewise. (__arm_vqdmlahq_m_n_s32): Likewise. (__arm_vqdmlahq_m_n_s16): Likewise. (__arm_vqdmlahq_m_n_u8): Likewise. (__arm_vqdmlahq_m_n_u32): Likewise. (__arm_vqdmlahq_m_n_u16): Likewise. (__arm_vqdmlsdhq_m_s8): Likewise. (__arm_vqdmlsdhq_m_s32): Likewise. (__arm_vqdmlsdhq_m_s16): Likewise. (__arm_vqdmlsdhxq_m_s8): Likewise. (__arm_vqdmlsdhxq_m_s32): Likewise. (__arm_vqdmlsdhxq_m_s16): Likewise. (__arm_vqdmulhq_m_n_s8): Likewise. (__arm_vqdmulhq_m_n_s32): Likewise. (__arm_vqdmulhq_m_n_s16): Likewise. (__arm_vqdmulhq_m_s8): Likewise. (__arm_vqdmulhq_m_s32): Likewise. (__arm_vqdmulhq_m_s16): Likewise. (__arm_vqrdmladhq_m_s8): Likewise. (__arm_vqrdmladhq_m_s32): Likewise. (__arm_vqrdmladhq_m_s16): Likewise. (__arm_vqrdmladhxq_m_s8): Likewise. (__arm_vqrdmladhxq_m_s32): Likewise. (__arm_vqrdmladhxq_m_s16): Likewise. (__arm_vqrdmlahq_m_n_s8): Likewise. (__arm_vqrdmlahq_m_n_s32): Likewise. (__arm_vqrdmlahq_m_n_s16): Likewise. (__arm_vqrdmlahq_m_n_u8): Likewise. (__arm_vqrdmlahq_m_n_u32): Likewise. (__arm_vqrdmlahq_m_n_u16): Likewise. (__arm_vqrdmlashq_m_n_s8): Likewise. (__arm_vqrdmlashq_m_n_s32): Likewise. (__arm_vqrdmlashq_m_n_s16): Likewise. (__arm_vqrdmlashq_m_n_u8): Likewise. (__arm_vqrdmlashq_m_n_u32): Likewise. (__arm_vqrdmlashq_m_n_u16): Likewise. (__arm_vqrdmlsdhq_m_s8): Likewise. (__arm_vqrdmlsdhq_m_s32): Likewise. (__arm_vqrdmlsdhq_m_s16): Likewise. (__arm_vqrdmlsdhxq_m_s8): Likewise. (__arm_vqrdmlsdhxq_m_s32): Likewise. (__arm_vqrdmlsdhxq_m_s16): Likewise. (__arm_vqrdmulhq_m_n_s8): Likewise. (__arm_vqrdmulhq_m_n_s32): Likewise. (__arm_vqrdmulhq_m_n_s16): Likewise. (__arm_vqrdmulhq_m_s8): Likewise. (__arm_vqrdmulhq_m_s32): Likewise. (__arm_vqrdmulhq_m_s16): Likewise. (__arm_vqrshlq_m_s8): Likewise. (__arm_vqrshlq_m_s32): Likewise. (__arm_vqrshlq_m_s16): Likewise. (__arm_vqrshlq_m_u8): Likewise. (__arm_vqrshlq_m_u32): Likewise. (__arm_vqrshlq_m_u16): Likewise. (__arm_vqshlq_m_n_s8): Likewise. (__arm_vqshlq_m_n_s32): Likewise. (__arm_vqshlq_m_n_s16): Likewise. (__arm_vqshlq_m_n_u8): Likewise. (__arm_vqshlq_m_n_u32): Likewise. (__arm_vqshlq_m_n_u16): Likewise. (__arm_vqshlq_m_s8): Likewise. (__arm_vqshlq_m_s32): Likewise. (__arm_vqshlq_m_s16): Likewise. (__arm_vqshlq_m_u8): Likewise. (__arm_vqshlq_m_u32): Likewise. (__arm_vqshlq_m_u16): Likewise. (__arm_vqsubq_m_n_s8): Likewise. (__arm_vqsubq_m_n_s32): Likewise. (__arm_vqsubq_m_n_s16): Likewise. (__arm_vqsubq_m_n_u8): Likewise. (__arm_vqsubq_m_n_u32): Likewise. (__arm_vqsubq_m_n_u16): Likewise. (__arm_vqsubq_m_s8): Likewise. (__arm_vqsubq_m_s32): Likewise. (__arm_vqsubq_m_s16): Likewise. (__arm_vqsubq_m_u8): Likewise. (__arm_vqsubq_m_u32): Likewise. (__arm_vqsubq_m_u16): Likewise. (__arm_vrhaddq_m_s8): Likewise. (__arm_vrhaddq_m_s32): Likewise. (__arm_vrhaddq_m_s16): Likewise. (__arm_vrhaddq_m_u8): Likewise. (__arm_vrhaddq_m_u32): Likewise. (__arm_vrhaddq_m_u16): Likewise. (__arm_vrmulhq_m_s8): Likewise. (__arm_vrmulhq_m_s32): Likewise. (__arm_vrmulhq_m_s16): Likewise. (__arm_vrmulhq_m_u8): Likewise. (__arm_vrmulhq_m_u32): Likewise. (__arm_vrmulhq_m_u16): Likewise. (__arm_vrshlq_m_s8): Likewise. (__arm_vrshlq_m_s32): Likewise. (__arm_vrshlq_m_s16): Likewise. (__arm_vrshlq_m_u8): Likewise. (__arm_vrshlq_m_u32): Likewise. (__arm_vrshlq_m_u16): Likewise. (__arm_vrshrq_m_n_s8): Likewise. (__arm_vrshrq_m_n_s32): Likewise. (__arm_vrshrq_m_n_s16): Likewise. (__arm_vrshrq_m_n_u8): Likewise. (__arm_vrshrq_m_n_u32): Likewise. (__arm_vrshrq_m_n_u16): Likewise. (__arm_vshlq_m_n_s8): Likewise. (__arm_vshlq_m_n_s32): Likewise. (__arm_vshlq_m_n_s16): Likewise. (__arm_vshlq_m_n_u8): Likewise. (__arm_vshlq_m_n_u32): Likewise. (__arm_vshlq_m_n_u16): Likewise. (__arm_vshrq_m_n_s8): Likewise. (__arm_vshrq_m_n_s32): Likewise. (__arm_vshrq_m_n_s16): Likewise. (__arm_vshrq_m_n_u8): Likewise. (__arm_vshrq_m_n_u32): Likewise. (__arm_vshrq_m_n_u16): Likewise. (__arm_vsliq_m_n_s8): Likewise. (__arm_vsliq_m_n_s32): Likewise. (__arm_vsliq_m_n_s16): Likewise. (__arm_vsliq_m_n_u8): Likewise. (__arm_vsliq_m_n_u32): Likewise. (__arm_vsliq_m_n_u16): Likewise. (__arm_vsubq_m_n_s8): Likewise. (__arm_vsubq_m_n_s32): Likewise. (__arm_vsubq_m_n_s16): Likewise. (__arm_vsubq_m_n_u8): Likewise. (__arm_vsubq_m_n_u32): Likewise. (__arm_vsubq_m_n_u16): Likewise. (vqdmladhq_m): Define polymorphic variant. (vqdmladhxq_m): Likewise. (vqdmlsdhq_m): Likewise. (vqdmlsdhxq_m): Likewise. (vabdq_m): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (veorq_m): Likewise. (vmaxq_m): Likewise. (vminq_m): Likewise. (vmladavaq_p): Likewise. (vmlaq_m_n): Likewise. (vmlasq_m_n): Likewise. (vmulhq_m): Likewise. (vmullbq_int_m): Likewise. (vmulltq_int_m): Likewise. (vornq_m): Likewise. (vorrq_m): Likewise. (vqdmlahq_m_n): Likewise. (vqrdmlahq_m_n): Likewise. (vqrdmlashq_m_n): Likewise. (vqrshlq_m): Likewise. (vqshlq_m_n): Likewise. (vqshlq_m): Likewise. (vrhaddq_m): Likewise. (vrmulhq_m): Likewise. (vrshlq_m): Likewise. (vrshrq_m_n): Likewise. (vshlq_m_n): Likewise. (vshrq_m_n): Likewise. (vsliq_m): Likewise. (vaddq_m_n): Likewise. (vaddq_m): Likewise. (vhaddq_m_n): Likewise. (vhaddq_m): Likewise. (vhcaddq_rot270_m): Likewise. (vhcaddq_rot90_m): Likewise. (vhsubq_m): Likewise. (vhsubq_m_n): Likewise. (vmulq_m_n): Likewise. (vmulq_m): Likewise. (vqaddq_m_n): Likewise. (vqaddq_m): Likewise. (vqdmulhq_m_n): Likewise. (vqdmulhq_m): Likewise. (vsubq_m_n): Likewise. (vsliq_m_n): Likewise. (vqsubq_m_n): Likewise. (vqsubq_m): Likewise. (vqrdmulhq_m): Likewise. (vqrdmulhq_m_n): Likewise. (vqrdmlsdhxq_m): Likewise. (vqrdmlsdhq_m): Likewise. (vqrdmladhq_m): Likewise. (vqrdmladhxq_m): Likewise. (vmlsdavaxq_p): Likewise. (vmlsdavaq_p): Likewise. (vmladavaxq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VHSUBQ_M): Define iterators. (VSLIQ_M_N): Likewise. (VQRDMLAHQ_M_N): Likewise. (VRSHLQ_M): Likewise. (VMINQ_M): Likewise. (VMULLBQ_INT_M): Likewise. (VMULHQ_M): Likewise. (VMULQ_M): Likewise. (VHSUBQ_M_N): Likewise. (VHADDQ_M_N): Likewise. (VORRQ_M): Likewise. (VRMULHQ_M): Likewise. (VQADDQ_M): Likewise. (VRSHRQ_M_N): Likewise. (VQSUBQ_M_N): Likewise. (VADDQ_M): Likewise. (VORNQ_M): Likewise. (VQDMLAHQ_M_N): Likewise. (VRHADDQ_M): Likewise. (VQSHLQ_M): Likewise. (VANDQ_M): Likewise. (VBICQ_M): Likewise. (VSHLQ_M_N): Likewise. (VCADDQ_ROT270_M): Likewise. (VQRSHLQ_M): Likewise. (VQADDQ_M_N): Likewise. (VADDQ_M_N): Likewise. (VMAXQ_M): Likewise. (VQSUBQ_M): Likewise. (VMLASQ_M_N): Likewise. (VMLADAVAQ_P): Likewise. (VBRSRQ_M_N): Likewise. (VMULQ_M_N): Likewise. (VCADDQ_ROT90_M): Likewise. (VMULLTQ_INT_M): Likewise. (VEORQ_M): Likewise. (VSHRQ_M_N): Likewise. (VSUBQ_M_N): Likewise. (VHADDQ_M): Likewise. (VABDQ_M): Likewise. (VQRDMLASHQ_M_N): Likewise. (VMLAQ_M_N): Likewise. (VQSHLQ_M_N): Likewise. (mve_vabdq_m_): Define RTL pattern. (mve_vaddq_m_n_): Likewise. (mve_vaddq_m_): Likewise. (mve_vandq_m_): Likewise. (mve_vbicq_m_): Likewise. (mve_vbrsrq_m_n_): Likewise. (mve_vcaddq_rot270_m_): Likewise. (mve_vcaddq_rot90_m_): Likewise. (mve_veorq_m_): Likewise. (mve_vhaddq_m_n_): Likewise. (mve_vhaddq_m_): Likewise. (mve_vhsubq_m_n_): Likewise. (mve_vhsubq_m_): Likewise. (mve_vmaxq_m_): Likewise. (mve_vminq_m_): Likewise. (mve_vmladavaq_p_): Likewise. (mve_vmlaq_m_n_): Likewise. (mve_vmlasq_m_n_): Likewise. (mve_vmulhq_m_): Likewise. (mve_vmullbq_int_m_): Likewise. (mve_vmulltq_int_m_): Likewise. (mve_vmulq_m_n_): Likewise. (mve_vmulq_m_): Likewise. (mve_vornq_m_): Likewise. (mve_vorrq_m_): Likewise. (mve_vqaddq_m_n_): Likewise. (mve_vqaddq_m_): Likewise. (mve_vqdmlahq_m_n_): Likewise. (mve_vqrdmlahq_m_n_): Likewise. (mve_vqrdmlashq_m_n_): Likewise. (mve_vqrshlq_m_): Likewise. (mve_vqshlq_m_n_): Likewise. (mve_vqshlq_m_): Likewise. (mve_vqsubq_m_n_): Likewise. (mve_vqsubq_m_): Likewise. (mve_vrhaddq_m_): Likewise. (mve_vrmulhq_m_): Likewise. (mve_vrshlq_m_): Likewise. (mve_vrshrq_m_n_): Likewise. (mve_vshlq_m_n_): Likewise. (mve_vshrq_m_n_): Likewise. (mve_vsliq_m_n_): Likewise. (mve_vsubq_m_n_): Likewise. (mve_vhcaddq_rot270_m_s): Likewise. (mve_vhcaddq_rot90_m_s): Likewise. (mve_vmladavaxq_p_s): Likewise. (mve_vmlsdavaq_p_s): Likewise. (mve_vmlsdavaxq_p_s): Likewise. (mve_vqdmladhq_m_s): Likewise. (mve_vqdmladhxq_m_s): Likewise. (mve_vqdmlsdhq_m_s): Likewise. (mve_vqdmlsdhxq_m_s): Likewise. (mve_vqdmulhq_m_n_s): Likewise. (mve_vqdmulhq_m_s): Likewise. (mve_vqrdmladhq_m_s): Likewise. (mve_vqrdmladhxq_m_s): Likewise. (mve_vqrdmlsdhq_m_s): Likewise. (mve_vqrdmlsdhxq_m_s): Likewise. (mve_vqrdmulhq_m_n_s): Likewise. (mve_vqrdmulhq_m_s): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. --- gcc/ChangeLog | 793 ++++++ gcc/config/arm/arm_mve.h | 3012 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 100 + gcc/config/arm/mve.md | 1125 +++++++- gcc/testsuite/ChangeLog | 314 ++ .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 24 + 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eaf5ff5..e9e019a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,799 @@ 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni + + * config/arm/arm_mve.h (vabdq_m_s8): Define macro. + (vabdq_m_s32): Likewise. + (vabdq_m_s16): Likewise. + (vabdq_m_u8): Likewise. + (vabdq_m_u32): Likewise. + (vabdq_m_u16): Likewise. + (vaddq_m_n_s8): Likewise. + (vaddq_m_n_s32): Likewise. + (vaddq_m_n_s16): Likewise. + (vaddq_m_n_u8): Likewise. + (vaddq_m_n_u32): Likewise. + (vaddq_m_n_u16): Likewise. + (vaddq_m_s8): Likewise. + (vaddq_m_s32): Likewise. + (vaddq_m_s16): Likewise. + (vaddq_m_u8): Likewise. + (vaddq_m_u32): Likewise. + (vaddq_m_u16): Likewise. + (vandq_m_s8): Likewise. + (vandq_m_s32): Likewise. + (vandq_m_s16): Likewise. + (vandq_m_u8): Likewise. + (vandq_m_u32): Likewise. + (vandq_m_u16): Likewise. + (vbicq_m_s8): Likewise. + (vbicq_m_s32): Likewise. + (vbicq_m_s16): Likewise. + (vbicq_m_u8): Likewise. + (vbicq_m_u32): Likewise. + (vbicq_m_u16): Likewise. + (vbrsrq_m_n_s8): Likewise. + (vbrsrq_m_n_s32): Likewise. + (vbrsrq_m_n_s16): Likewise. + (vbrsrq_m_n_u8): Likewise. + (vbrsrq_m_n_u32): Likewise. + (vbrsrq_m_n_u16): Likewise. + (vcaddq_rot270_m_s8): Likewise. + (vcaddq_rot270_m_s32): Likewise. + (vcaddq_rot270_m_s16): Likewise. + (vcaddq_rot270_m_u8): Likewise. + (vcaddq_rot270_m_u32): Likewise. + (vcaddq_rot270_m_u16): Likewise. + (vcaddq_rot90_m_s8): Likewise. + (vcaddq_rot90_m_s32): Likewise. + (vcaddq_rot90_m_s16): Likewise. + (vcaddq_rot90_m_u8): Likewise. + (vcaddq_rot90_m_u32): Likewise. + (vcaddq_rot90_m_u16): Likewise. + (veorq_m_s8): Likewise. + (veorq_m_s32): Likewise. + (veorq_m_s16): Likewise. + (veorq_m_u8): Likewise. + (veorq_m_u32): Likewise. + (veorq_m_u16): Likewise. + (vhaddq_m_n_s8): Likewise. + (vhaddq_m_n_s32): Likewise. + (vhaddq_m_n_s16): Likewise. + (vhaddq_m_n_u8): Likewise. + (vhaddq_m_n_u32): Likewise. + (vhaddq_m_n_u16): Likewise. + (vhaddq_m_s8): Likewise. + (vhaddq_m_s32): Likewise. + (vhaddq_m_s16): Likewise. + (vhaddq_m_u8): Likewise. + (vhaddq_m_u32): Likewise. + (vhaddq_m_u16): Likewise. + (vhcaddq_rot270_m_s8): Likewise. + (vhcaddq_rot270_m_s32): Likewise. + (vhcaddq_rot270_m_s16): Likewise. + (vhcaddq_rot90_m_s8): Likewise. + (vhcaddq_rot90_m_s32): Likewise. + (vhcaddq_rot90_m_s16): Likewise. + (vhsubq_m_n_s8): Likewise. + (vhsubq_m_n_s32): Likewise. + (vhsubq_m_n_s16): Likewise. + (vhsubq_m_n_u8): Likewise. + (vhsubq_m_n_u32): Likewise. + (vhsubq_m_n_u16): Likewise. + (vhsubq_m_s8): Likewise. + (vhsubq_m_s32): Likewise. + (vhsubq_m_s16): Likewise. + (vhsubq_m_u8): Likewise. + (vhsubq_m_u32): Likewise. + (vhsubq_m_u16): Likewise. + (vmaxq_m_s8): Likewise. + (vmaxq_m_s32): Likewise. + (vmaxq_m_s16): Likewise. + (vmaxq_m_u8): Likewise. + (vmaxq_m_u32): Likewise. + (vmaxq_m_u16): Likewise. + (vminq_m_s8): Likewise. + (vminq_m_s32): Likewise. + (vminq_m_s16): Likewise. + (vminq_m_u8): Likewise. + (vminq_m_u32): Likewise. + (vminq_m_u16): Likewise. + (vmladavaq_p_s8): Likewise. + (vmladavaq_p_s32): Likewise. + (vmladavaq_p_s16): Likewise. + (vmladavaq_p_u8): Likewise. + (vmladavaq_p_u32): Likewise. + (vmladavaq_p_u16): Likewise. + (vmladavaxq_p_s8): Likewise. + (vmladavaxq_p_s32): Likewise. + (vmladavaxq_p_s16): Likewise. + (vmlaq_m_n_s8): Likewise. + (vmlaq_m_n_s32): Likewise. + (vmlaq_m_n_s16): Likewise. + (vmlaq_m_n_u8): Likewise. + (vmlaq_m_n_u32): Likewise. + (vmlaq_m_n_u16): Likewise. + (vmlasq_m_n_s8): Likewise. + (vmlasq_m_n_s32): Likewise. + (vmlasq_m_n_s16): Likewise. + (vmlasq_m_n_u8): Likewise. + (vmlasq_m_n_u32): Likewise. + (vmlasq_m_n_u16): Likewise. + (vmlsdavaq_p_s8): Likewise. + (vmlsdavaq_p_s32): Likewise. + (vmlsdavaq_p_s16): Likewise. + (vmlsdavaxq_p_s8): Likewise. + (vmlsdavaxq_p_s32): Likewise. + (vmlsdavaxq_p_s16): Likewise. + (vmulhq_m_s8): Likewise. + (vmulhq_m_s32): Likewise. + (vmulhq_m_s16): Likewise. + (vmulhq_m_u8): Likewise. + (vmulhq_m_u32): Likewise. + (vmulhq_m_u16): Likewise. + (vmullbq_int_m_s8): Likewise. + (vmullbq_int_m_s32): Likewise. + (vmullbq_int_m_s16): Likewise. + (vmullbq_int_m_u8): Likewise. + (vmullbq_int_m_u32): Likewise. + (vmullbq_int_m_u16): Likewise. + (vmulltq_int_m_s8): Likewise. + (vmulltq_int_m_s32): Likewise. + (vmulltq_int_m_s16): Likewise. + (vmulltq_int_m_u8): Likewise. + (vmulltq_int_m_u32): Likewise. + (vmulltq_int_m_u16): Likewise. + (vmulq_m_n_s8): Likewise. + (vmulq_m_n_s32): Likewise. + (vmulq_m_n_s16): Likewise. + (vmulq_m_n_u8): Likewise. + (vmulq_m_n_u32): Likewise. + (vmulq_m_n_u16): Likewise. + (vmulq_m_s8): Likewise. + (vmulq_m_s32): Likewise. + (vmulq_m_s16): Likewise. + (vmulq_m_u8): Likewise. + (vmulq_m_u32): Likewise. + (vmulq_m_u16): Likewise. + (vornq_m_s8): Likewise. + (vornq_m_s32): Likewise. + (vornq_m_s16): Likewise. + (vornq_m_u8): Likewise. + (vornq_m_u32): Likewise. + (vornq_m_u16): Likewise. + (vorrq_m_s8): Likewise. + (vorrq_m_s32): Likewise. + (vorrq_m_s16): Likewise. + (vorrq_m_u8): Likewise. + (vorrq_m_u32): Likewise. + (vorrq_m_u16): Likewise. + (vqaddq_m_n_s8): Likewise. + (vqaddq_m_n_s32): Likewise. + (vqaddq_m_n_s16): Likewise. + (vqaddq_m_n_u8): Likewise. + (vqaddq_m_n_u32): Likewise. + (vqaddq_m_n_u16): Likewise. + (vqaddq_m_s8): Likewise. + (vqaddq_m_s32): Likewise. + (vqaddq_m_s16): Likewise. + (vqaddq_m_u8): Likewise. + (vqaddq_m_u32): Likewise. + (vqaddq_m_u16): Likewise. + (vqdmladhq_m_s8): Likewise. + (vqdmladhq_m_s32): Likewise. + (vqdmladhq_m_s16): Likewise. + (vqdmladhxq_m_s8): Likewise. + (vqdmladhxq_m_s32): Likewise. + (vqdmladhxq_m_s16): Likewise. + (vqdmlahq_m_n_s8): Likewise. + (vqdmlahq_m_n_s32): Likewise. + (vqdmlahq_m_n_s16): Likewise. + (vqdmlahq_m_n_u8): Likewise. + (vqdmlahq_m_n_u32): Likewise. + (vqdmlahq_m_n_u16): Likewise. + (vqdmlsdhq_m_s8): Likewise. + (vqdmlsdhq_m_s32): Likewise. + (vqdmlsdhq_m_s16): Likewise. + (vqdmlsdhxq_m_s8): Likewise. + (vqdmlsdhxq_m_s32): Likewise. + (vqdmlsdhxq_m_s16): Likewise. + (vqdmulhq_m_n_s8): Likewise. + (vqdmulhq_m_n_s32): Likewise. + (vqdmulhq_m_n_s16): Likewise. + (vqdmulhq_m_s8): Likewise. + (vqdmulhq_m_s32): Likewise. + (vqdmulhq_m_s16): Likewise. + (vqrdmladhq_m_s8): Likewise. + (vqrdmladhq_m_s32): Likewise. + (vqrdmladhq_m_s16): Likewise. + (vqrdmladhxq_m_s8): Likewise. + (vqrdmladhxq_m_s32): Likewise. + (vqrdmladhxq_m_s16): Likewise. + (vqrdmlahq_m_n_s8): Likewise. + (vqrdmlahq_m_n_s32): Likewise. + (vqrdmlahq_m_n_s16): Likewise. + (vqrdmlahq_m_n_u8): Likewise. + (vqrdmlahq_m_n_u32): Likewise. + (vqrdmlahq_m_n_u16): Likewise. + (vqrdmlashq_m_n_s8): Likewise. + (vqrdmlashq_m_n_s32): Likewise. + (vqrdmlashq_m_n_s16): Likewise. + (vqrdmlashq_m_n_u8): Likewise. + (vqrdmlashq_m_n_u32): Likewise. + (vqrdmlashq_m_n_u16): Likewise. + (vqrdmlsdhq_m_s8): Likewise. + (vqrdmlsdhq_m_s32): Likewise. + (vqrdmlsdhq_m_s16): Likewise. + (vqrdmlsdhxq_m_s8): Likewise. + (vqrdmlsdhxq_m_s32): Likewise. + (vqrdmlsdhxq_m_s16): Likewise. + (vqrdmulhq_m_n_s8): Likewise. + (vqrdmulhq_m_n_s32): Likewise. + (vqrdmulhq_m_n_s16): Likewise. + (vqrdmulhq_m_s8): Likewise. + (vqrdmulhq_m_s32): Likewise. + (vqrdmulhq_m_s16): Likewise. + (vqrshlq_m_s8): Likewise. + (vqrshlq_m_s32): Likewise. + (vqrshlq_m_s16): Likewise. + (vqrshlq_m_u8): Likewise. + (vqrshlq_m_u32): Likewise. + (vqrshlq_m_u16): Likewise. + (vqshlq_m_n_s8): Likewise. + (vqshlq_m_n_s32): Likewise. + (vqshlq_m_n_s16): Likewise. + (vqshlq_m_n_u8): Likewise. + (vqshlq_m_n_u32): Likewise. + (vqshlq_m_n_u16): Likewise. + (vqshlq_m_s8): Likewise. + (vqshlq_m_s32): Likewise. + (vqshlq_m_s16): Likewise. + (vqshlq_m_u8): Likewise. + (vqshlq_m_u32): Likewise. + (vqshlq_m_u16): Likewise. + (vqsubq_m_n_s8): Likewise. + (vqsubq_m_n_s32): Likewise. + (vqsubq_m_n_s16): Likewise. + (vqsubq_m_n_u8): Likewise. + (vqsubq_m_n_u32): Likewise. + (vqsubq_m_n_u16): Likewise. + (vqsubq_m_s8): Likewise. + (vqsubq_m_s32): Likewise. + (vqsubq_m_s16): Likewise. + (vqsubq_m_u8): Likewise. + (vqsubq_m_u32): Likewise. + (vqsubq_m_u16): Likewise. + (vrhaddq_m_s8): Likewise. + (vrhaddq_m_s32): Likewise. + (vrhaddq_m_s16): Likewise. + (vrhaddq_m_u8): Likewise. + (vrhaddq_m_u32): Likewise. + (vrhaddq_m_u16): Likewise. + (vrmulhq_m_s8): Likewise. + (vrmulhq_m_s32): Likewise. + (vrmulhq_m_s16): Likewise. + (vrmulhq_m_u8): Likewise. + (vrmulhq_m_u32): Likewise. + (vrmulhq_m_u16): Likewise. + (vrshlq_m_s8): Likewise. + (vrshlq_m_s32): Likewise. + (vrshlq_m_s16): Likewise. + (vrshlq_m_u8): Likewise. + (vrshlq_m_u32): Likewise. + (vrshlq_m_u16): Likewise. + (vrshrq_m_n_s8): Likewise. + (vrshrq_m_n_s32): Likewise. + (vrshrq_m_n_s16): Likewise. + (vrshrq_m_n_u8): Likewise. + (vrshrq_m_n_u32): Likewise. + (vrshrq_m_n_u16): Likewise. + (vshlq_m_n_s8): Likewise. + (vshlq_m_n_s32): Likewise. + (vshlq_m_n_s16): Likewise. + (vshlq_m_n_u8): Likewise. + (vshlq_m_n_u32): Likewise. + (vshlq_m_n_u16): Likewise. + (vshrq_m_n_s8): Likewise. + (vshrq_m_n_s32): Likewise. + (vshrq_m_n_s16): Likewise. + (vshrq_m_n_u8): Likewise. + (vshrq_m_n_u32): Likewise. + (vshrq_m_n_u16): Likewise. + (vsliq_m_n_s8): Likewise. + (vsliq_m_n_s32): Likewise. + (vsliq_m_n_s16): Likewise. + (vsliq_m_n_u8): Likewise. + (vsliq_m_n_u32): Likewise. + (vsliq_m_n_u16): Likewise. + (vsubq_m_n_s8): Likewise. + (vsubq_m_n_s32): Likewise. + (vsubq_m_n_s16): Likewise. + (vsubq_m_n_u8): Likewise. + (vsubq_m_n_u32): Likewise. + (vsubq_m_n_u16): Likewise. + (__arm_vabdq_m_s8): Define intrinsic. + (__arm_vabdq_m_s32): Likewise. + (__arm_vabdq_m_s16): Likewise. + (__arm_vabdq_m_u8): Likewise. + (__arm_vabdq_m_u32): Likewise. + (__arm_vabdq_m_u16): Likewise. + (__arm_vaddq_m_n_s8): Likewise. + (__arm_vaddq_m_n_s32): Likewise. + (__arm_vaddq_m_n_s16): Likewise. + (__arm_vaddq_m_n_u8): Likewise. + (__arm_vaddq_m_n_u32): Likewise. + (__arm_vaddq_m_n_u16): Likewise. + (__arm_vaddq_m_s8): Likewise. + (__arm_vaddq_m_s32): Likewise. + (__arm_vaddq_m_s16): Likewise. + (__arm_vaddq_m_u8): Likewise. + (__arm_vaddq_m_u32): Likewise. + (__arm_vaddq_m_u16): Likewise. + (__arm_vandq_m_s8): Likewise. + (__arm_vandq_m_s32): Likewise. + (__arm_vandq_m_s16): Likewise. + (__arm_vandq_m_u8): Likewise. + (__arm_vandq_m_u32): Likewise. + (__arm_vandq_m_u16): Likewise. + (__arm_vbicq_m_s8): Likewise. + (__arm_vbicq_m_s32): Likewise. + (__arm_vbicq_m_s16): Likewise. + (__arm_vbicq_m_u8): Likewise. + (__arm_vbicq_m_u32): Likewise. + (__arm_vbicq_m_u16): Likewise. + (__arm_vbrsrq_m_n_s8): Likewise. + (__arm_vbrsrq_m_n_s32): Likewise. + (__arm_vbrsrq_m_n_s16): Likewise. + (__arm_vbrsrq_m_n_u8): Likewise. + (__arm_vbrsrq_m_n_u32): Likewise. + (__arm_vbrsrq_m_n_u16): Likewise. + (__arm_vcaddq_rot270_m_s8): Likewise. + (__arm_vcaddq_rot270_m_s32): Likewise. + (__arm_vcaddq_rot270_m_s16): Likewise. + (__arm_vcaddq_rot270_m_u8): Likewise. + (__arm_vcaddq_rot270_m_u32): Likewise. + (__arm_vcaddq_rot270_m_u16): Likewise. + (__arm_vcaddq_rot90_m_s8): Likewise. + (__arm_vcaddq_rot90_m_s32): Likewise. + (__arm_vcaddq_rot90_m_s16): Likewise. + (__arm_vcaddq_rot90_m_u8): Likewise. + (__arm_vcaddq_rot90_m_u32): Likewise. + (__arm_vcaddq_rot90_m_u16): Likewise. + (__arm_veorq_m_s8): Likewise. + (__arm_veorq_m_s32): Likewise. + (__arm_veorq_m_s16): Likewise. + (__arm_veorq_m_u8): Likewise. + (__arm_veorq_m_u32): Likewise. + (__arm_veorq_m_u16): Likewise. + (__arm_vhaddq_m_n_s8): Likewise. + (__arm_vhaddq_m_n_s32): Likewise. + (__arm_vhaddq_m_n_s16): Likewise. + (__arm_vhaddq_m_n_u8): Likewise. + (__arm_vhaddq_m_n_u32): Likewise. + (__arm_vhaddq_m_n_u16): Likewise. + (__arm_vhaddq_m_s8): Likewise. + (__arm_vhaddq_m_s32): Likewise. + (__arm_vhaddq_m_s16): Likewise. + (__arm_vhaddq_m_u8): Likewise. + (__arm_vhaddq_m_u32): Likewise. + (__arm_vhaddq_m_u16): Likewise. + (__arm_vhcaddq_rot270_m_s8): Likewise. + (__arm_vhcaddq_rot270_m_s32): Likewise. + (__arm_vhcaddq_rot270_m_s16): Likewise. + (__arm_vhcaddq_rot90_m_s8): Likewise. + (__arm_vhcaddq_rot90_m_s32): Likewise. + (__arm_vhcaddq_rot90_m_s16): Likewise. + (__arm_vhsubq_m_n_s8): Likewise. + (__arm_vhsubq_m_n_s32): Likewise. + (__arm_vhsubq_m_n_s16): Likewise. + (__arm_vhsubq_m_n_u8): Likewise. + (__arm_vhsubq_m_n_u32): Likewise. + (__arm_vhsubq_m_n_u16): Likewise. + (__arm_vhsubq_m_s8): Likewise. + (__arm_vhsubq_m_s32): Likewise. + (__arm_vhsubq_m_s16): Likewise. + (__arm_vhsubq_m_u8): Likewise. + (__arm_vhsubq_m_u32): Likewise. + (__arm_vhsubq_m_u16): Likewise. + (__arm_vmaxq_m_s8): Likewise. + (__arm_vmaxq_m_s32): Likewise. + (__arm_vmaxq_m_s16): Likewise. + (__arm_vmaxq_m_u8): Likewise. + (__arm_vmaxq_m_u32): Likewise. + (__arm_vmaxq_m_u16): Likewise. + (__arm_vminq_m_s8): Likewise. + (__arm_vminq_m_s32): Likewise. + (__arm_vminq_m_s16): Likewise. + (__arm_vminq_m_u8): Likewise. + (__arm_vminq_m_u32): Likewise. + (__arm_vminq_m_u16): Likewise. + (__arm_vmladavaq_p_s8): Likewise. + (__arm_vmladavaq_p_s32): Likewise. + (__arm_vmladavaq_p_s16): Likewise. + (__arm_vmladavaq_p_u8): Likewise. + (__arm_vmladavaq_p_u32): Likewise. + (__arm_vmladavaq_p_u16): Likewise. + (__arm_vmladavaxq_p_s8): Likewise. + (__arm_vmladavaxq_p_s32): Likewise. + (__arm_vmladavaxq_p_s16): Likewise. + (__arm_vmlaq_m_n_s8): Likewise. + (__arm_vmlaq_m_n_s32): Likewise. + (__arm_vmlaq_m_n_s16): Likewise. + (__arm_vmlaq_m_n_u8): Likewise. + (__arm_vmlaq_m_n_u32): Likewise. + (__arm_vmlaq_m_n_u16): Likewise. + (__arm_vmlasq_m_n_s8): Likewise. + (__arm_vmlasq_m_n_s32): Likewise. + (__arm_vmlasq_m_n_s16): Likewise. + (__arm_vmlasq_m_n_u8): Likewise. + (__arm_vmlasq_m_n_u32): Likewise. + (__arm_vmlasq_m_n_u16): Likewise. + (__arm_vmlsdavaq_p_s8): Likewise. + (__arm_vmlsdavaq_p_s32): Likewise. + (__arm_vmlsdavaq_p_s16): Likewise. + (__arm_vmlsdavaxq_p_s8): Likewise. + (__arm_vmlsdavaxq_p_s32): Likewise. + (__arm_vmlsdavaxq_p_s16): Likewise. + (__arm_vmulhq_m_s8): Likewise. + (__arm_vmulhq_m_s32): Likewise. + (__arm_vmulhq_m_s16): Likewise. + (__arm_vmulhq_m_u8): Likewise. + (__arm_vmulhq_m_u32): Likewise. + (__arm_vmulhq_m_u16): Likewise. + (__arm_vmullbq_int_m_s8): Likewise. + (__arm_vmullbq_int_m_s32): Likewise. + (__arm_vmullbq_int_m_s16): Likewise. + (__arm_vmullbq_int_m_u8): Likewise. + (__arm_vmullbq_int_m_u32): Likewise. + (__arm_vmullbq_int_m_u16): Likewise. + (__arm_vmulltq_int_m_s8): Likewise. + (__arm_vmulltq_int_m_s32): Likewise. + (__arm_vmulltq_int_m_s16): Likewise. + (__arm_vmulltq_int_m_u8): Likewise. + (__arm_vmulltq_int_m_u32): Likewise. + (__arm_vmulltq_int_m_u16): Likewise. + (__arm_vmulq_m_n_s8): Likewise. + (__arm_vmulq_m_n_s32): Likewise. + (__arm_vmulq_m_n_s16): Likewise. + (__arm_vmulq_m_n_u8): Likewise. + (__arm_vmulq_m_n_u32): Likewise. + (__arm_vmulq_m_n_u16): Likewise. + (__arm_vmulq_m_s8): Likewise. + (__arm_vmulq_m_s32): Likewise. + (__arm_vmulq_m_s16): Likewise. + (__arm_vmulq_m_u8): Likewise. + (__arm_vmulq_m_u32): Likewise. + (__arm_vmulq_m_u16): Likewise. + (__arm_vornq_m_s8): Likewise. + (__arm_vornq_m_s32): Likewise. + (__arm_vornq_m_s16): Likewise. + (__arm_vornq_m_u8): Likewise. + (__arm_vornq_m_u32): Likewise. + (__arm_vornq_m_u16): Likewise. + (__arm_vorrq_m_s8): Likewise. + (__arm_vorrq_m_s32): Likewise. + (__arm_vorrq_m_s16): Likewise. + (__arm_vorrq_m_u8): Likewise. + (__arm_vorrq_m_u32): Likewise. + (__arm_vorrq_m_u16): Likewise. + (__arm_vqaddq_m_n_s8): Likewise. + (__arm_vqaddq_m_n_s32): Likewise. + (__arm_vqaddq_m_n_s16): Likewise. + (__arm_vqaddq_m_n_u8): Likewise. + (__arm_vqaddq_m_n_u32): Likewise. + (__arm_vqaddq_m_n_u16): Likewise. + (__arm_vqaddq_m_s8): Likewise. + (__arm_vqaddq_m_s32): Likewise. + (__arm_vqaddq_m_s16): Likewise. + (__arm_vqaddq_m_u8): Likewise. + (__arm_vqaddq_m_u32): Likewise. + (__arm_vqaddq_m_u16): Likewise. + (__arm_vqdmladhq_m_s8): Likewise. + (__arm_vqdmladhq_m_s32): Likewise. + (__arm_vqdmladhq_m_s16): Likewise. + (__arm_vqdmladhxq_m_s8): Likewise. + (__arm_vqdmladhxq_m_s32): Likewise. + (__arm_vqdmladhxq_m_s16): Likewise. + (__arm_vqdmlahq_m_n_s8): Likewise. + (__arm_vqdmlahq_m_n_s32): Likewise. + (__arm_vqdmlahq_m_n_s16): Likewise. + (__arm_vqdmlahq_m_n_u8): Likewise. + (__arm_vqdmlahq_m_n_u32): Likewise. + (__arm_vqdmlahq_m_n_u16): Likewise. + (__arm_vqdmlsdhq_m_s8): Likewise. + (__arm_vqdmlsdhq_m_s32): Likewise. + (__arm_vqdmlsdhq_m_s16): Likewise. + (__arm_vqdmlsdhxq_m_s8): Likewise. + (__arm_vqdmlsdhxq_m_s32): Likewise. + (__arm_vqdmlsdhxq_m_s16): Likewise. + (__arm_vqdmulhq_m_n_s8): Likewise. + (__arm_vqdmulhq_m_n_s32): Likewise. + (__arm_vqdmulhq_m_n_s16): Likewise. + (__arm_vqdmulhq_m_s8): Likewise. + (__arm_vqdmulhq_m_s32): Likewise. + (__arm_vqdmulhq_m_s16): Likewise. + (__arm_vqrdmladhq_m_s8): Likewise. + (__arm_vqrdmladhq_m_s32): Likewise. + (__arm_vqrdmladhq_m_s16): Likewise. + (__arm_vqrdmladhxq_m_s8): Likewise. + (__arm_vqrdmladhxq_m_s32): Likewise. + (__arm_vqrdmladhxq_m_s16): Likewise. + (__arm_vqrdmlahq_m_n_s8): Likewise. + (__arm_vqrdmlahq_m_n_s32): Likewise. + (__arm_vqrdmlahq_m_n_s16): Likewise. + (__arm_vqrdmlahq_m_n_u8): Likewise. + (__arm_vqrdmlahq_m_n_u32): Likewise. + (__arm_vqrdmlahq_m_n_u16): Likewise. + (__arm_vqrdmlashq_m_n_s8): Likewise. + (__arm_vqrdmlashq_m_n_s32): Likewise. + (__arm_vqrdmlashq_m_n_s16): Likewise. + (__arm_vqrdmlashq_m_n_u8): Likewise. + (__arm_vqrdmlashq_m_n_u32): Likewise. + (__arm_vqrdmlashq_m_n_u16): Likewise. + (__arm_vqrdmlsdhq_m_s8): Likewise. + (__arm_vqrdmlsdhq_m_s32): Likewise. + (__arm_vqrdmlsdhq_m_s16): Likewise. + (__arm_vqrdmlsdhxq_m_s8): Likewise. + (__arm_vqrdmlsdhxq_m_s32): Likewise. + (__arm_vqrdmlsdhxq_m_s16): Likewise. + (__arm_vqrdmulhq_m_n_s8): Likewise. + (__arm_vqrdmulhq_m_n_s32): Likewise. + (__arm_vqrdmulhq_m_n_s16): Likewise. + (__arm_vqrdmulhq_m_s8): Likewise. + (__arm_vqrdmulhq_m_s32): Likewise. + (__arm_vqrdmulhq_m_s16): Likewise. + (__arm_vqrshlq_m_s8): Likewise. + (__arm_vqrshlq_m_s32): Likewise. + (__arm_vqrshlq_m_s16): Likewise. + (__arm_vqrshlq_m_u8): Likewise. + (__arm_vqrshlq_m_u32): Likewise. + (__arm_vqrshlq_m_u16): Likewise. + (__arm_vqshlq_m_n_s8): Likewise. + (__arm_vqshlq_m_n_s32): Likewise. + (__arm_vqshlq_m_n_s16): Likewise. + (__arm_vqshlq_m_n_u8): Likewise. + (__arm_vqshlq_m_n_u32): Likewise. + (__arm_vqshlq_m_n_u16): Likewise. + (__arm_vqshlq_m_s8): Likewise. + (__arm_vqshlq_m_s32): Likewise. + (__arm_vqshlq_m_s16): Likewise. + (__arm_vqshlq_m_u8): Likewise. + (__arm_vqshlq_m_u32): Likewise. + (__arm_vqshlq_m_u16): Likewise. + (__arm_vqsubq_m_n_s8): Likewise. + (__arm_vqsubq_m_n_s32): Likewise. + (__arm_vqsubq_m_n_s16): Likewise. + (__arm_vqsubq_m_n_u8): Likewise. + (__arm_vqsubq_m_n_u32): Likewise. + (__arm_vqsubq_m_n_u16): Likewise. + (__arm_vqsubq_m_s8): Likewise. + (__arm_vqsubq_m_s32): Likewise. + (__arm_vqsubq_m_s16): Likewise. + (__arm_vqsubq_m_u8): Likewise. + (__arm_vqsubq_m_u32): Likewise. + (__arm_vqsubq_m_u16): Likewise. + (__arm_vrhaddq_m_s8): Likewise. + (__arm_vrhaddq_m_s32): Likewise. + (__arm_vrhaddq_m_s16): Likewise. + (__arm_vrhaddq_m_u8): Likewise. + (__arm_vrhaddq_m_u32): Likewise. + (__arm_vrhaddq_m_u16): Likewise. + (__arm_vrmulhq_m_s8): Likewise. + (__arm_vrmulhq_m_s32): Likewise. + (__arm_vrmulhq_m_s16): Likewise. + (__arm_vrmulhq_m_u8): Likewise. + (__arm_vrmulhq_m_u32): Likewise. + (__arm_vrmulhq_m_u16): Likewise. + (__arm_vrshlq_m_s8): Likewise. + (__arm_vrshlq_m_s32): Likewise. + (__arm_vrshlq_m_s16): Likewise. + (__arm_vrshlq_m_u8): Likewise. + (__arm_vrshlq_m_u32): Likewise. + (__arm_vrshlq_m_u16): Likewise. + (__arm_vrshrq_m_n_s8): Likewise. + (__arm_vrshrq_m_n_s32): Likewise. + (__arm_vrshrq_m_n_s16): Likewise. + (__arm_vrshrq_m_n_u8): Likewise. + (__arm_vrshrq_m_n_u32): Likewise. + (__arm_vrshrq_m_n_u16): Likewise. + (__arm_vshlq_m_n_s8): Likewise. + (__arm_vshlq_m_n_s32): Likewise. + (__arm_vshlq_m_n_s16): Likewise. + (__arm_vshlq_m_n_u8): Likewise. + (__arm_vshlq_m_n_u32): Likewise. + (__arm_vshlq_m_n_u16): Likewise. + (__arm_vshrq_m_n_s8): Likewise. + (__arm_vshrq_m_n_s32): Likewise. + (__arm_vshrq_m_n_s16): Likewise. + (__arm_vshrq_m_n_u8): Likewise. + (__arm_vshrq_m_n_u32): Likewise. + (__arm_vshrq_m_n_u16): Likewise. + (__arm_vsliq_m_n_s8): Likewise. + (__arm_vsliq_m_n_s32): Likewise. + (__arm_vsliq_m_n_s16): Likewise. + (__arm_vsliq_m_n_u8): Likewise. + (__arm_vsliq_m_n_u32): Likewise. + (__arm_vsliq_m_n_u16): Likewise. + (__arm_vsubq_m_n_s8): Likewise. + (__arm_vsubq_m_n_s32): Likewise. + (__arm_vsubq_m_n_s16): Likewise. + (__arm_vsubq_m_n_u8): Likewise. + (__arm_vsubq_m_n_u32): Likewise. + (__arm_vsubq_m_n_u16): Likewise. + (vqdmladhq_m): Define polymorphic variant. + (vqdmladhxq_m): Likewise. + (vqdmlsdhq_m): Likewise. + (vqdmlsdhxq_m): Likewise. + (vabdq_m): Likewise. + (vandq_m): Likewise. + (vbicq_m): Likewise. + (vbrsrq_m_n): Likewise. + (vcaddq_rot270_m): Likewise. + (vcaddq_rot90_m): Likewise. + (veorq_m): Likewise. + (vmaxq_m): Likewise. + (vminq_m): Likewise. + (vmladavaq_p): Likewise. + (vmlaq_m_n): Likewise. + (vmlasq_m_n): Likewise. + (vmulhq_m): Likewise. + (vmullbq_int_m): Likewise. + (vmulltq_int_m): Likewise. + (vornq_m): Likewise. + (vorrq_m): Likewise. + (vqdmlahq_m_n): Likewise. + (vqrdmlahq_m_n): Likewise. + (vqrdmlashq_m_n): Likewise. + (vqrshlq_m): Likewise. + (vqshlq_m_n): Likewise. + (vqshlq_m): Likewise. + (vrhaddq_m): Likewise. + (vrmulhq_m): Likewise. + (vrshlq_m): Likewise. + (vrshrq_m_n): Likewise. + (vshlq_m_n): Likewise. + (vshrq_m_n): Likewise. + (vsliq_m): Likewise. + (vaddq_m_n): Likewise. + (vaddq_m): Likewise. + (vhaddq_m_n): Likewise. + (vhaddq_m): Likewise. + (vhcaddq_rot270_m): Likewise. + (vhcaddq_rot90_m): Likewise. + (vhsubq_m): Likewise. + (vhsubq_m_n): Likewise. + (vmulq_m_n): Likewise. + (vmulq_m): Likewise. + (vqaddq_m_n): Likewise. + (vqaddq_m): Likewise. + (vqdmulhq_m_n): Likewise. + (vqdmulhq_m): Likewise. + (vsubq_m_n): Likewise. + (vsliq_m_n): Likewise. + (vqsubq_m_n): Likewise. + (vqsubq_m): Likewise. + (vqrdmulhq_m): Likewise. + (vqrdmulhq_m_n): Likewise. + (vqrdmlsdhxq_m): Likewise. + (vqrdmlsdhq_m): Likewise. + (vqrdmladhq_m): Likewise. + (vqrdmladhxq_m): Likewise. + (vmlsdavaxq_p): Likewise. + (vmlsdavaq_p): Likewise. + (vmladavaxq_p): Likewise. + * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use + builtin qualifier. + (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. + * config/arm/mve.md (VHSUBQ_M): Define iterators. + (VSLIQ_M_N): Likewise. + (VQRDMLAHQ_M_N): Likewise. + (VRSHLQ_M): Likewise. + (VMINQ_M): Likewise. + (VMULLBQ_INT_M): Likewise. + (VMULHQ_M): Likewise. + (VMULQ_M): Likewise. + (VHSUBQ_M_N): Likewise. + (VHADDQ_M_N): Likewise. + (VORRQ_M): Likewise. + (VRMULHQ_M): Likewise. + (VQADDQ_M): Likewise. + (VRSHRQ_M_N): Likewise. + (VQSUBQ_M_N): Likewise. + (VADDQ_M): Likewise. + (VORNQ_M): Likewise. + (VQDMLAHQ_M_N): Likewise. + (VRHADDQ_M): Likewise. + (VQSHLQ_M): Likewise. + (VANDQ_M): Likewise. + (VBICQ_M): Likewise. + (VSHLQ_M_N): Likewise. + (VCADDQ_ROT270_M): Likewise. + (VQRSHLQ_M): Likewise. + (VQADDQ_M_N): Likewise. + (VADDQ_M_N): Likewise. + (VMAXQ_M): Likewise. + (VQSUBQ_M): Likewise. + (VMLASQ_M_N): Likewise. + (VMLADAVAQ_P): Likewise. + (VBRSRQ_M_N): Likewise. + (VMULQ_M_N): Likewise. + (VCADDQ_ROT90_M): Likewise. + (VMULLTQ_INT_M): Likewise. + (VEORQ_M): Likewise. + (VSHRQ_M_N): Likewise. + (VSUBQ_M_N): Likewise. + (VHADDQ_M): Likewise. + (VABDQ_M): Likewise. + (VQRDMLASHQ_M_N): Likewise. + (VMLAQ_M_N): Likewise. + (VQSHLQ_M_N): Likewise. + (mve_vabdq_m_): Define RTL pattern. + (mve_vaddq_m_n_): Likewise. + (mve_vaddq_m_): Likewise. + (mve_vandq_m_): Likewise. + (mve_vbicq_m_): Likewise. + (mve_vbrsrq_m_n_): Likewise. + (mve_vcaddq_rot270_m_): Likewise. + (mve_vcaddq_rot90_m_): Likewise. + (mve_veorq_m_): Likewise. + (mve_vhaddq_m_n_): Likewise. + (mve_vhaddq_m_): Likewise. + (mve_vhsubq_m_n_): Likewise. + (mve_vhsubq_m_): Likewise. + (mve_vmaxq_m_): Likewise. + (mve_vminq_m_): Likewise. + (mve_vmladavaq_p_): Likewise. + (mve_vmlaq_m_n_): Likewise. + (mve_vmlasq_m_n_): Likewise. + (mve_vmulhq_m_): Likewise. + (mve_vmullbq_int_m_): Likewise. + (mve_vmulltq_int_m_): Likewise. + (mve_vmulq_m_n_): Likewise. + (mve_vmulq_m_): Likewise. + (mve_vornq_m_): Likewise. + (mve_vorrq_m_): Likewise. + (mve_vqaddq_m_n_): Likewise. + (mve_vqaddq_m_): Likewise. + (mve_vqdmlahq_m_n_): Likewise. + (mve_vqrdmlahq_m_n_): Likewise. + (mve_vqrdmlashq_m_n_): Likewise. + (mve_vqrshlq_m_): Likewise. + (mve_vqshlq_m_n_): Likewise. + (mve_vqshlq_m_): Likewise. + (mve_vqsubq_m_n_): Likewise. + (mve_vqsubq_m_): Likewise. + (mve_vrhaddq_m_): Likewise. + (mve_vrmulhq_m_): Likewise. + (mve_vrshlq_m_): Likewise. + (mve_vrshrq_m_n_): Likewise. + (mve_vshlq_m_n_): Likewise. + (mve_vshrq_m_n_): Likewise. + (mve_vsliq_m_n_): Likewise. + (mve_vsubq_m_n_): Likewise. + (mve_vhcaddq_rot270_m_s): Likewise. + (mve_vhcaddq_rot90_m_s): Likewise. + (mve_vmladavaxq_p_s): Likewise. + (mve_vmlsdavaq_p_s): Likewise. + (mve_vmlsdavaxq_p_s): Likewise. + (mve_vqdmladhq_m_s): Likewise. + (mve_vqdmladhxq_m_s): Likewise. + (mve_vqdmlsdhq_m_s): Likewise. + (mve_vqdmlsdhxq_m_s): Likewise. + (mve_vqdmulhq_m_n_s): Likewise. + (mve_vqdmulhq_m_s): Likewise. + (mve_vqrdmladhq_m_s): Likewise. + (mve_vqrdmladhxq_m_s): Likewise. + (mve_vqrdmlsdhq_m_s): Likewise. + (mve_vqrdmlsdhxq_m_s): Likewise. + (mve_vqrdmulhq_m_n_s): Likewise. + (mve_vqrdmulhq_m_s): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Define builtin qualifier. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index e236bff..53bf29e 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1263,6 +1263,306 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsubq_m_u32(__inactive, __a, __b, __p) __arm_vsubq_m_u32(__inactive, __a, __b, __p) #define vabavq_p_u32(__a, __b, __c, __p) __arm_vabavq_p_u32(__a, __b, __c, __p) #define vshlq_m_s32(__inactive, __a, __b, __p) __arm_vshlq_m_s32(__inactive, __a, __b, __p) +#define vabdq_m_s8(__inactive, __a, __b, __p) __arm_vabdq_m_s8(__inactive, __a, __b, __p) +#define vabdq_m_s32(__inactive, __a, __b, __p) __arm_vabdq_m_s32(__inactive, __a, __b, __p) +#define vabdq_m_s16(__inactive, __a, __b, __p) __arm_vabdq_m_s16(__inactive, __a, __b, __p) +#define vabdq_m_u8(__inactive, __a, __b, __p) __arm_vabdq_m_u8(__inactive, __a, __b, __p) +#define vabdq_m_u32(__inactive, __a, __b, __p) __arm_vabdq_m_u32(__inactive, __a, __b, __p) +#define vabdq_m_u16(__inactive, __a, __b, __p) __arm_vabdq_m_u16(__inactive, __a, __b, __p) +#define vaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vaddq_m_n_s8(__inactive, __a, __b, __p) +#define vaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vaddq_m_n_s32(__inactive, __a, __b, __p) +#define vaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vaddq_m_n_s16(__inactive, __a, __b, __p) +#define vaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vaddq_m_n_u8(__inactive, __a, __b, __p) +#define vaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vaddq_m_n_u32(__inactive, __a, __b, __p) +#define vaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vaddq_m_n_u16(__inactive, __a, __b, __p) +#define vaddq_m_s8(__inactive, __a, __b, __p) __arm_vaddq_m_s8(__inactive, __a, __b, __p) +#define vaddq_m_s32(__inactive, __a, __b, __p) __arm_vaddq_m_s32(__inactive, __a, __b, __p) +#define vaddq_m_s16(__inactive, __a, __b, __p) __arm_vaddq_m_s16(__inactive, __a, __b, __p) +#define vaddq_m_u8(__inactive, __a, __b, __p) __arm_vaddq_m_u8(__inactive, __a, __b, __p) +#define vaddq_m_u32(__inactive, __a, __b, __p) __arm_vaddq_m_u32(__inactive, __a, __b, __p) +#define vaddq_m_u16(__inactive, __a, __b, __p) __arm_vaddq_m_u16(__inactive, __a, __b, __p) +#define vandq_m_s8(__inactive, __a, __b, __p) __arm_vandq_m_s8(__inactive, __a, __b, __p) +#define vandq_m_s32(__inactive, __a, __b, __p) __arm_vandq_m_s32(__inactive, __a, __b, __p) +#define vandq_m_s16(__inactive, __a, __b, __p) __arm_vandq_m_s16(__inactive, __a, __b, __p) +#define vandq_m_u8(__inactive, __a, __b, __p) __arm_vandq_m_u8(__inactive, __a, __b, __p) +#define vandq_m_u32(__inactive, __a, __b, __p) __arm_vandq_m_u32(__inactive, __a, __b, __p) +#define vandq_m_u16(__inactive, __a, __b, __p) __arm_vandq_m_u16(__inactive, __a, __b, __p) +#define vbicq_m_s8(__inactive, __a, __b, __p) __arm_vbicq_m_s8(__inactive, __a, __b, __p) +#define vbicq_m_s32(__inactive, __a, __b, __p) __arm_vbicq_m_s32(__inactive, __a, __b, __p) +#define vbicq_m_s16(__inactive, __a, __b, __p) __arm_vbicq_m_s16(__inactive, __a, __b, __p) +#define vbicq_m_u8(__inactive, __a, __b, __p) __arm_vbicq_m_u8(__inactive, __a, __b, __p) +#define vbicq_m_u32(__inactive, __a, __b, __p) __arm_vbicq_m_u32(__inactive, __a, __b, __p) +#define vbicq_m_u16(__inactive, __a, __b, __p) __arm_vbicq_m_u16(__inactive, __a, __b, __p) +#define vbrsrq_m_n_s8(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s8(__inactive, __a, __b, __p) +#define vbrsrq_m_n_s32(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s32(__inactive, __a, __b, __p) +#define vbrsrq_m_n_s16(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s16(__inactive, __a, __b, __p) +#define vbrsrq_m_n_u8(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u8(__inactive, __a, __b, __p) +#define vbrsrq_m_n_u32(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u32(__inactive, __a, __b, __p) +#define vbrsrq_m_n_u16(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u16(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_s8(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s8(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_s32(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s32(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_s16(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s16(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_u8(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u8(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_u32(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u32(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_u16(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u16(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_s8(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s8(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_s32(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s32(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_s16(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s16(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_u8(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u8(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_u32(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u32(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_u16(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u16(__inactive, __a, __b, __p) +#define veorq_m_s8(__inactive, __a, __b, __p) __arm_veorq_m_s8(__inactive, __a, __b, __p) +#define veorq_m_s32(__inactive, __a, __b, __p) __arm_veorq_m_s32(__inactive, __a, __b, __p) +#define veorq_m_s16(__inactive, __a, __b, __p) __arm_veorq_m_s16(__inactive, __a, __b, __p) +#define veorq_m_u8(__inactive, __a, __b, __p) __arm_veorq_m_u8(__inactive, __a, __b, __p) +#define veorq_m_u32(__inactive, __a, __b, __p) __arm_veorq_m_u32(__inactive, __a, __b, __p) +#define veorq_m_u16(__inactive, __a, __b, __p) __arm_veorq_m_u16(__inactive, __a, __b, __p) +#define vhaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s8(__inactive, __a, __b, __p) +#define vhaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s32(__inactive, __a, __b, __p) +#define vhaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s16(__inactive, __a, __b, __p) +#define vhaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u8(__inactive, __a, __b, __p) +#define vhaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u32(__inactive, __a, __b, __p) +#define vhaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u16(__inactive, __a, __b, __p) +#define vhaddq_m_s8(__inactive, __a, __b, __p) __arm_vhaddq_m_s8(__inactive, __a, __b, __p) +#define vhaddq_m_s32(__inactive, __a, __b, __p) __arm_vhaddq_m_s32(__inactive, __a, __b, __p) +#define vhaddq_m_s16(__inactive, __a, __b, __p) __arm_vhaddq_m_s16(__inactive, __a, __b, __p) +#define vhaddq_m_u8(__inactive, __a, __b, __p) __arm_vhaddq_m_u8(__inactive, __a, __b, __p) +#define vhaddq_m_u32(__inactive, __a, __b, __p) __arm_vhaddq_m_u32(__inactive, __a, __b, __p) +#define vhaddq_m_u16(__inactive, __a, __b, __p) __arm_vhaddq_m_u16(__inactive, __a, __b, __p) +#define vhcaddq_rot270_m_s8(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s8(__inactive, __a, __b, __p) +#define vhcaddq_rot270_m_s32(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s32(__inactive, __a, __b, __p) +#define vhcaddq_rot270_m_s16(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s16(__inactive, __a, __b, __p) +#define vhcaddq_rot90_m_s8(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s8(__inactive, __a, __b, __p) +#define vhcaddq_rot90_m_s32(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s32(__inactive, __a, __b, __p) +#define vhcaddq_rot90_m_s16(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s16(__inactive, __a, __b, __p) +#define vhsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s8(__inactive, __a, __b, __p) +#define vhsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s32(__inactive, __a, __b, __p) +#define vhsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s16(__inactive, __a, __b, __p) +#define vhsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u8(__inactive, __a, __b, __p) +#define vhsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u32(__inactive, __a, __b, __p) +#define vhsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u16(__inactive, __a, __b, __p) +#define vhsubq_m_s8(__inactive, __a, __b, __p) __arm_vhsubq_m_s8(__inactive, __a, __b, __p) +#define vhsubq_m_s32(__inactive, __a, __b, __p) __arm_vhsubq_m_s32(__inactive, __a, __b, __p) +#define vhsubq_m_s16(__inactive, __a, __b, __p) __arm_vhsubq_m_s16(__inactive, __a, __b, __p) +#define vhsubq_m_u8(__inactive, __a, __b, __p) __arm_vhsubq_m_u8(__inactive, __a, __b, __p) +#define vhsubq_m_u32(__inactive, __a, __b, __p) __arm_vhsubq_m_u32(__inactive, __a, __b, __p) +#define vhsubq_m_u16(__inactive, __a, __b, __p) __arm_vhsubq_m_u16(__inactive, __a, __b, __p) +#define vmaxq_m_s8(__inactive, __a, __b, __p) __arm_vmaxq_m_s8(__inactive, __a, __b, __p) +#define vmaxq_m_s32(__inactive, __a, __b, __p) __arm_vmaxq_m_s32(__inactive, __a, __b, __p) +#define vmaxq_m_s16(__inactive, __a, __b, __p) __arm_vmaxq_m_s16(__inactive, __a, __b, __p) +#define vmaxq_m_u8(__inactive, __a, __b, __p) __arm_vmaxq_m_u8(__inactive, __a, __b, __p) +#define vmaxq_m_u32(__inactive, __a, __b, __p) __arm_vmaxq_m_u32(__inactive, __a, __b, __p) +#define vmaxq_m_u16(__inactive, __a, __b, __p) __arm_vmaxq_m_u16(__inactive, __a, __b, __p) +#define vminq_m_s8(__inactive, __a, __b, __p) __arm_vminq_m_s8(__inactive, __a, __b, __p) +#define vminq_m_s32(__inactive, __a, __b, __p) __arm_vminq_m_s32(__inactive, __a, __b, __p) +#define vminq_m_s16(__inactive, __a, __b, __p) __arm_vminq_m_s16(__inactive, __a, __b, __p) +#define vminq_m_u8(__inactive, __a, __b, __p) __arm_vminq_m_u8(__inactive, __a, __b, __p) +#define vminq_m_u32(__inactive, __a, __b, __p) __arm_vminq_m_u32(__inactive, __a, __b, __p) +#define vminq_m_u16(__inactive, __a, __b, __p) __arm_vminq_m_u16(__inactive, __a, __b, __p) +#define vmladavaq_p_s8(__a, __b, __c, __p) __arm_vmladavaq_p_s8(__a, __b, __c, __p) +#define vmladavaq_p_s32(__a, __b, __c, __p) __arm_vmladavaq_p_s32(__a, __b, __c, __p) +#define vmladavaq_p_s16(__a, __b, __c, __p) __arm_vmladavaq_p_s16(__a, __b, __c, __p) +#define vmladavaq_p_u8(__a, __b, __c, __p) __arm_vmladavaq_p_u8(__a, __b, __c, __p) +#define vmladavaq_p_u32(__a, __b, __c, __p) __arm_vmladavaq_p_u32(__a, __b, __c, __p) +#define vmladavaq_p_u16(__a, __b, __c, __p) __arm_vmladavaq_p_u16(__a, __b, __c, __p) +#define vmladavaxq_p_s8(__a, __b, __c, __p) __arm_vmladavaxq_p_s8(__a, __b, __c, __p) +#define vmladavaxq_p_s32(__a, __b, __c, __p) __arm_vmladavaxq_p_s32(__a, __b, __c, __p) +#define vmladavaxq_p_s16(__a, __b, __c, __p) __arm_vmladavaxq_p_s16(__a, __b, __c, __p) +#define vmlaq_m_n_s8(__a, __b, __c, __p) __arm_vmlaq_m_n_s8(__a, __b, __c, __p) +#define vmlaq_m_n_s32(__a, __b, __c, __p) __arm_vmlaq_m_n_s32(__a, __b, __c, __p) +#define vmlaq_m_n_s16(__a, __b, __c, __p) __arm_vmlaq_m_n_s16(__a, __b, __c, __p) +#define vmlaq_m_n_u8(__a, __b, __c, __p) __arm_vmlaq_m_n_u8(__a, __b, __c, __p) +#define vmlaq_m_n_u32(__a, __b, __c, __p) __arm_vmlaq_m_n_u32(__a, __b, __c, __p) +#define vmlaq_m_n_u16(__a, __b, __c, __p) __arm_vmlaq_m_n_u16(__a, __b, __c, __p) +#define vmlasq_m_n_s8(__a, __b, __c, __p) __arm_vmlasq_m_n_s8(__a, __b, __c, __p) +#define vmlasq_m_n_s32(__a, __b, __c, __p) __arm_vmlasq_m_n_s32(__a, __b, __c, __p) +#define vmlasq_m_n_s16(__a, __b, __c, __p) __arm_vmlasq_m_n_s16(__a, __b, __c, __p) +#define vmlasq_m_n_u8(__a, __b, __c, __p) __arm_vmlasq_m_n_u8(__a, __b, __c, __p) +#define vmlasq_m_n_u32(__a, __b, __c, __p) __arm_vmlasq_m_n_u32(__a, __b, __c, __p) +#define vmlasq_m_n_u16(__a, __b, __c, __p) __arm_vmlasq_m_n_u16(__a, __b, __c, __p) +#define vmlsdavaq_p_s8(__a, __b, __c, __p) __arm_vmlsdavaq_p_s8(__a, __b, __c, __p) +#define vmlsdavaq_p_s32(__a, __b, __c, __p) __arm_vmlsdavaq_p_s32(__a, __b, __c, __p) +#define vmlsdavaq_p_s16(__a, __b, __c, __p) __arm_vmlsdavaq_p_s16(__a, __b, __c, __p) +#define vmlsdavaxq_p_s8(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s8(__a, __b, __c, __p) +#define vmlsdavaxq_p_s32(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s32(__a, __b, __c, __p) +#define vmlsdavaxq_p_s16(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s16(__a, __b, __c, __p) +#define vmulhq_m_s8(__inactive, __a, __b, __p) __arm_vmulhq_m_s8(__inactive, __a, __b, __p) +#define vmulhq_m_s32(__inactive, __a, __b, __p) __arm_vmulhq_m_s32(__inactive, __a, __b, __p) +#define vmulhq_m_s16(__inactive, __a, __b, __p) __arm_vmulhq_m_s16(__inactive, __a, __b, __p) +#define vmulhq_m_u8(__inactive, __a, __b, __p) __arm_vmulhq_m_u8(__inactive, __a, __b, __p) +#define vmulhq_m_u32(__inactive, __a, __b, __p) __arm_vmulhq_m_u32(__inactive, __a, __b, __p) +#define vmulhq_m_u16(__inactive, __a, __b, __p) __arm_vmulhq_m_u16(__inactive, __a, __b, __p) +#define vmullbq_int_m_s8(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s8(__inactive, __a, __b, __p) +#define vmullbq_int_m_s32(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s32(__inactive, __a, __b, __p) +#define vmullbq_int_m_s16(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s16(__inactive, __a, __b, __p) +#define vmullbq_int_m_u8(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u8(__inactive, __a, __b, __p) +#define vmullbq_int_m_u32(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u32(__inactive, __a, __b, __p) +#define vmullbq_int_m_u16(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u16(__inactive, __a, __b, __p) +#define vmulltq_int_m_s8(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s8(__inactive, __a, __b, __p) +#define vmulltq_int_m_s32(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s32(__inactive, __a, __b, __p) +#define vmulltq_int_m_s16(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s16(__inactive, __a, __b, __p) +#define vmulltq_int_m_u8(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u8(__inactive, __a, __b, __p) +#define vmulltq_int_m_u32(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u32(__inactive, __a, __b, __p) +#define vmulltq_int_m_u16(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u16(__inactive, __a, __b, __p) +#define vmulq_m_n_s8(__inactive, __a, __b, __p) __arm_vmulq_m_n_s8(__inactive, __a, __b, __p) +#define vmulq_m_n_s32(__inactive, __a, __b, __p) __arm_vmulq_m_n_s32(__inactive, __a, __b, __p) +#define vmulq_m_n_s16(__inactive, __a, __b, __p) __arm_vmulq_m_n_s16(__inactive, __a, __b, __p) +#define vmulq_m_n_u8(__inactive, __a, __b, __p) __arm_vmulq_m_n_u8(__inactive, __a, __b, __p) +#define vmulq_m_n_u32(__inactive, __a, __b, __p) __arm_vmulq_m_n_u32(__inactive, __a, __b, __p) +#define vmulq_m_n_u16(__inactive, __a, __b, __p) __arm_vmulq_m_n_u16(__inactive, __a, __b, __p) +#define vmulq_m_s8(__inactive, __a, __b, __p) __arm_vmulq_m_s8(__inactive, __a, __b, __p) +#define vmulq_m_s32(__inactive, __a, __b, __p) __arm_vmulq_m_s32(__inactive, __a, __b, __p) +#define vmulq_m_s16(__inactive, __a, __b, __p) __arm_vmulq_m_s16(__inactive, __a, __b, __p) +#define vmulq_m_u8(__inactive, __a, __b, __p) __arm_vmulq_m_u8(__inactive, __a, __b, __p) +#define vmulq_m_u32(__inactive, __a, __b, __p) __arm_vmulq_m_u32(__inactive, __a, __b, __p) +#define vmulq_m_u16(__inactive, __a, __b, __p) __arm_vmulq_m_u16(__inactive, __a, __b, __p) +#define vornq_m_s8(__inactive, __a, __b, __p) __arm_vornq_m_s8(__inactive, __a, __b, __p) +#define vornq_m_s32(__inactive, __a, __b, __p) __arm_vornq_m_s32(__inactive, __a, __b, __p) +#define vornq_m_s16(__inactive, __a, __b, __p) __arm_vornq_m_s16(__inactive, __a, __b, __p) +#define vornq_m_u8(__inactive, __a, __b, __p) __arm_vornq_m_u8(__inactive, __a, __b, __p) +#define vornq_m_u32(__inactive, __a, __b, __p) __arm_vornq_m_u32(__inactive, __a, __b, __p) +#define vornq_m_u16(__inactive, __a, __b, __p) __arm_vornq_m_u16(__inactive, __a, __b, __p) +#define vorrq_m_s8(__inactive, __a, __b, __p) __arm_vorrq_m_s8(__inactive, __a, __b, __p) +#define vorrq_m_s32(__inactive, __a, __b, __p) __arm_vorrq_m_s32(__inactive, __a, __b, __p) +#define vorrq_m_s16(__inactive, __a, __b, __p) __arm_vorrq_m_s16(__inactive, __a, __b, __p) +#define vorrq_m_u8(__inactive, __a, __b, __p) __arm_vorrq_m_u8(__inactive, __a, __b, __p) +#define vorrq_m_u32(__inactive, __a, __b, __p) __arm_vorrq_m_u32(__inactive, __a, __b, __p) +#define vorrq_m_u16(__inactive, __a, __b, __p) __arm_vorrq_m_u16(__inactive, __a, __b, __p) +#define vqaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s8(__inactive, __a, __b, __p) +#define vqaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s32(__inactive, __a, __b, __p) +#define vqaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s16(__inactive, __a, __b, __p) +#define vqaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u8(__inactive, __a, __b, __p) +#define vqaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u32(__inactive, __a, __b, __p) +#define vqaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u16(__inactive, __a, __b, __p) +#define vqaddq_m_s8(__inactive, __a, __b, __p) __arm_vqaddq_m_s8(__inactive, __a, __b, __p) +#define vqaddq_m_s32(__inactive, __a, __b, __p) __arm_vqaddq_m_s32(__inactive, __a, __b, __p) +#define vqaddq_m_s16(__inactive, __a, __b, __p) __arm_vqaddq_m_s16(__inactive, __a, __b, __p) +#define vqaddq_m_u8(__inactive, __a, __b, __p) __arm_vqaddq_m_u8(__inactive, __a, __b, __p) +#define vqaddq_m_u32(__inactive, __a, __b, __p) __arm_vqaddq_m_u32(__inactive, __a, __b, __p) +#define vqaddq_m_u16(__inactive, __a, __b, __p) __arm_vqaddq_m_u16(__inactive, __a, __b, __p) +#define vqdmladhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s8(__inactive, __a, __b, __p) +#define vqdmladhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s32(__inactive, __a, __b, __p) +#define vqdmladhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s16(__inactive, __a, __b, __p) +#define vqdmladhxq_m_s8(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s8(__inactive, __a, __b, __p) +#define vqdmladhxq_m_s32(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s32(__inactive, __a, __b, __p) +#define vqdmladhxq_m_s16(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s16(__inactive, __a, __b, __p) +#define vqdmlahq_m_n_s8(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s8(__a, __b, __c, __p) +#define vqdmlahq_m_n_s32(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s32(__a, __b, __c, __p) +#define vqdmlahq_m_n_s16(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s16(__a, __b, __c, __p) +#define vqdmlsdhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s8(__inactive, __a, __b, __p) +#define vqdmlsdhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s32(__inactive, __a, __b, __p) +#define vqdmlsdhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s16(__inactive, __a, __b, __p) +#define vqdmlsdhxq_m_s8(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s8(__inactive, __a, __b, __p) +#define vqdmlsdhxq_m_s32(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s32(__inactive, __a, __b, __p) +#define vqdmlsdhxq_m_s16(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s16(__inactive, __a, __b, __p) +#define vqdmulhq_m_n_s8(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s8(__inactive, __a, __b, __p) +#define vqdmulhq_m_n_s32(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s32(__inactive, __a, __b, __p) +#define vqdmulhq_m_n_s16(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s16(__inactive, __a, __b, __p) +#define vqdmulhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s8(__inactive, __a, __b, __p) +#define vqdmulhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s32(__inactive, __a, __b, __p) +#define vqdmulhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s16(__inactive, __a, __b, __p) +#define vqrdmladhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s8(__inactive, __a, __b, __p) +#define vqrdmladhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s32(__inactive, __a, __b, __p) +#define vqrdmladhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s16(__inactive, __a, __b, __p) +#define vqrdmladhxq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s8(__inactive, __a, __b, __p) +#define vqrdmladhxq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s32(__inactive, __a, __b, __p) +#define vqrdmladhxq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s16(__inactive, __a, __b, __p) +#define vqrdmlahq_m_n_s8(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s8(__a, __b, __c, __p) +#define vqrdmlahq_m_n_s32(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s32(__a, __b, __c, __p) +#define vqrdmlahq_m_n_s16(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s16(__a, __b, __c, __p) +#define vqrdmlashq_m_n_s8(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s8(__a, __b, __c, __p) +#define vqrdmlashq_m_n_s32(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s32(__a, __b, __c, __p) +#define vqrdmlashq_m_n_s16(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s16(__a, __b, __c, __p) +#define vqrdmlsdhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s8(__inactive, __a, __b, __p) +#define vqrdmlsdhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s32(__inactive, __a, __b, __p) +#define vqrdmlsdhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s16(__inactive, __a, __b, __p) +#define vqrdmlsdhxq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s8(__inactive, __a, __b, __p) +#define vqrdmlsdhxq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s32(__inactive, __a, __b, __p) +#define vqrdmlsdhxq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s16(__inactive, __a, __b, __p) +#define vqrdmulhq_m_n_s8(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s8(__inactive, __a, __b, __p) +#define vqrdmulhq_m_n_s32(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s32(__inactive, __a, __b, __p) +#define vqrdmulhq_m_n_s16(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s16(__inactive, __a, __b, __p) +#define vqrdmulhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s8(__inactive, __a, __b, __p) +#define vqrdmulhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s32(__inactive, __a, __b, __p) +#define vqrdmulhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s16(__inactive, __a, __b, __p) +#define vqrshlq_m_s8(__inactive, __a, __b, __p) __arm_vqrshlq_m_s8(__inactive, __a, __b, __p) +#define vqrshlq_m_s32(__inactive, __a, __b, __p) __arm_vqrshlq_m_s32(__inactive, __a, __b, __p) +#define vqrshlq_m_s16(__inactive, __a, __b, __p) __arm_vqrshlq_m_s16(__inactive, __a, __b, __p) +#define vqrshlq_m_u8(__inactive, __a, __b, __p) __arm_vqrshlq_m_u8(__inactive, __a, __b, __p) +#define vqrshlq_m_u32(__inactive, __a, __b, __p) __arm_vqrshlq_m_u32(__inactive, __a, __b, __p) +#define vqrshlq_m_u16(__inactive, __a, __b, __p) __arm_vqrshlq_m_u16(__inactive, __a, __b, __p) +#define vqshlq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s8(__inactive, __a, __imm, __p) +#define vqshlq_m_n_s32(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s32(__inactive, __a, __imm, __p) +#define vqshlq_m_n_s16(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s16(__inactive, __a, __imm, __p) +#define vqshlq_m_n_u8(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u8(__inactive, __a, __imm, __p) +#define vqshlq_m_n_u32(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u32(__inactive, __a, __imm, __p) +#define vqshlq_m_n_u16(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u16(__inactive, __a, __imm, __p) +#define vqshlq_m_s8(__inactive, __a, __b, __p) __arm_vqshlq_m_s8(__inactive, __a, __b, __p) +#define vqshlq_m_s32(__inactive, __a, __b, __p) __arm_vqshlq_m_s32(__inactive, __a, __b, __p) +#define vqshlq_m_s16(__inactive, __a, __b, __p) __arm_vqshlq_m_s16(__inactive, __a, __b, __p) +#define vqshlq_m_u8(__inactive, __a, __b, __p) __arm_vqshlq_m_u8(__inactive, __a, __b, __p) +#define vqshlq_m_u32(__inactive, __a, __b, __p) __arm_vqshlq_m_u32(__inactive, __a, __b, __p) +#define vqshlq_m_u16(__inactive, __a, __b, __p) __arm_vqshlq_m_u16(__inactive, __a, __b, __p) +#define vqsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s8(__inactive, __a, __b, __p) +#define vqsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s32(__inactive, __a, __b, __p) +#define vqsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s16(__inactive, __a, __b, __p) +#define vqsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u8(__inactive, __a, __b, __p) +#define vqsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u32(__inactive, __a, __b, __p) +#define vqsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u16(__inactive, __a, __b, __p) +#define vqsubq_m_s8(__inactive, __a, __b, __p) __arm_vqsubq_m_s8(__inactive, __a, __b, __p) +#define vqsubq_m_s32(__inactive, __a, __b, __p) __arm_vqsubq_m_s32(__inactive, __a, __b, __p) +#define vqsubq_m_s16(__inactive, __a, __b, __p) __arm_vqsubq_m_s16(__inactive, __a, __b, __p) +#define vqsubq_m_u8(__inactive, __a, __b, __p) __arm_vqsubq_m_u8(__inactive, __a, __b, __p) +#define vqsubq_m_u32(__inactive, __a, __b, __p) __arm_vqsubq_m_u32(__inactive, __a, __b, __p) +#define vqsubq_m_u16(__inactive, __a, __b, __p) __arm_vqsubq_m_u16(__inactive, __a, __b, __p) +#define vrhaddq_m_s8(__inactive, __a, __b, __p) __arm_vrhaddq_m_s8(__inactive, __a, __b, __p) +#define vrhaddq_m_s32(__inactive, __a, __b, __p) __arm_vrhaddq_m_s32(__inactive, __a, __b, __p) +#define vrhaddq_m_s16(__inactive, __a, __b, __p) __arm_vrhaddq_m_s16(__inactive, __a, __b, __p) +#define vrhaddq_m_u8(__inactive, __a, __b, __p) __arm_vrhaddq_m_u8(__inactive, __a, __b, __p) +#define vrhaddq_m_u32(__inactive, __a, __b, __p) __arm_vrhaddq_m_u32(__inactive, __a, __b, __p) +#define vrhaddq_m_u16(__inactive, __a, __b, __p) __arm_vrhaddq_m_u16(__inactive, __a, __b, __p) +#define vrmulhq_m_s8(__inactive, __a, __b, __p) __arm_vrmulhq_m_s8(__inactive, __a, __b, __p) +#define vrmulhq_m_s32(__inactive, __a, __b, __p) __arm_vrmulhq_m_s32(__inactive, __a, __b, __p) +#define vrmulhq_m_s16(__inactive, __a, __b, __p) __arm_vrmulhq_m_s16(__inactive, __a, __b, __p) +#define vrmulhq_m_u8(__inactive, __a, __b, __p) __arm_vrmulhq_m_u8(__inactive, __a, __b, __p) +#define vrmulhq_m_u32(__inactive, __a, __b, __p) __arm_vrmulhq_m_u32(__inactive, __a, __b, __p) +#define vrmulhq_m_u16(__inactive, __a, __b, __p) __arm_vrmulhq_m_u16(__inactive, __a, __b, __p) +#define vrshlq_m_s8(__inactive, __a, __b, __p) __arm_vrshlq_m_s8(__inactive, __a, __b, __p) +#define vrshlq_m_s32(__inactive, __a, __b, __p) __arm_vrshlq_m_s32(__inactive, __a, __b, __p) +#define vrshlq_m_s16(__inactive, __a, __b, __p) __arm_vrshlq_m_s16(__inactive, __a, __b, __p) +#define vrshlq_m_u8(__inactive, __a, __b, __p) __arm_vrshlq_m_u8(__inactive, __a, __b, __p) +#define vrshlq_m_u32(__inactive, __a, __b, __p) __arm_vrshlq_m_u32(__inactive, __a, __b, __p) +#define vrshlq_m_u16(__inactive, __a, __b, __p) __arm_vrshlq_m_u16(__inactive, __a, __b, __p) +#define vrshrq_m_n_s8(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s8(__inactive, __a, __imm, __p) +#define vrshrq_m_n_s32(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s32(__inactive, __a, __imm, __p) +#define vrshrq_m_n_s16(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s16(__inactive, __a, __imm, __p) +#define vrshrq_m_n_u8(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u8(__inactive, __a, __imm, __p) +#define vrshrq_m_n_u32(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u32(__inactive, __a, __imm, __p) +#define vrshrq_m_n_u16(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u16(__inactive, __a, __imm, __p) +#define vshlq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s8(__inactive, __a, __imm, __p) +#define vshlq_m_n_s32(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s32(__inactive, __a, __imm, __p) +#define vshlq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s16(__inactive, __a, __imm, __p) +#define vshlq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u8(__inactive, __a, __imm, __p) +#define vshlq_m_n_u32(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u32(__inactive, __a, __imm, __p) +#define vshlq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u16(__inactive, __a, __imm, __p) +#define vshrq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s8(__inactive, __a, __imm, __p) +#define vshrq_m_n_s32(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s32(__inactive, __a, __imm, __p) +#define vshrq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s16(__inactive, __a, __imm, __p) +#define vshrq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u8(__inactive, __a, __imm, __p) +#define vshrq_m_n_u32(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u32(__inactive, __a, __imm, __p) +#define vshrq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u16(__inactive, __a, __imm, __p) +#define vsliq_m_n_s8(__a, __b, __imm, __p) __arm_vsliq_m_n_s8(__a, __b, __imm, __p) +#define vsliq_m_n_s32(__a, __b, __imm, __p) __arm_vsliq_m_n_s32(__a, __b, __imm, __p) +#define vsliq_m_n_s16(__a, __b, __imm, __p) __arm_vsliq_m_n_s16(__a, __b, __imm, __p) +#define vsliq_m_n_u8(__a, __b, __imm, __p) __arm_vsliq_m_n_u8(__a, __b, __imm, __p) +#define vsliq_m_n_u32(__a, __b, __imm, __p) __arm_vsliq_m_n_u32(__a, __b, __imm, __p) +#define vsliq_m_n_u16(__a, __b, __imm, __p) __arm_vsliq_m_n_u16(__a, __b, __imm, __p) +#define vsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vsubq_m_n_s8(__inactive, __a, __b, __p) +#define vsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vsubq_m_n_s32(__inactive, __a, __b, __p) +#define vsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vsubq_m_n_s16(__inactive, __a, __b, __p) +#define vsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vsubq_m_n_u8(__inactive, __a, __b, __p) +#define vsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vsubq_m_n_u32(__inactive, __a, __b, __p) +#define vsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vsubq_m_n_u16(__inactive, __a, __b, __p) #endif __extension__ extern __inline void @@ -7917,6 +8217,2106 @@ __arm_vshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred1 return __builtin_mve_vshlq_m_sv4si (__inactive, __a, __b, __p); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhaddq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot270_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot270_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot270_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot270_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot90_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot90_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhcaddq_rot90_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhcaddq_rot90_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vhsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vhsubq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_uv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaq_p_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaq_p_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaxq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmladavaxq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmladavaxq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_uv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaq_m_n_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_uv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlasq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlasq_m_n_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaxq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsdavaxq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsdavaxq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulhq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulhq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_s8 (int16x8_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_u8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_u32 (uint64x2_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_int_m_u16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_int_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_s8 (int16x8_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_u8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_u32 (uint64x2_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_int_m_u16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_int_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqaddq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhxq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhxq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmladhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmladhxq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlahq_m_n_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlahq_m_n_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlahq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlahq_m_n_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhxq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhxq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmlsdhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmlsdhxq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhxq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhxq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmladhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmladhxq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlahq_m_n_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlahq_m_n_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlahq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlahq_m_n_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlashq_m_n_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlashq_m_n_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlashq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlashq_m_n_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhxq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhxq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmlsdhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmlsdhxq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrdmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrdmulhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqrshlq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqshlq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_n_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqsubq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrhaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrhaddq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmulhq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrmulhq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vrshlq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_sv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_uv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsliq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsliq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_uv8hi (__inactive, __a, __b, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -13637,6 +16037,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -13656,8 +16062,593 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabavq_p_u16(__p0, __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabavq_p_u32(__p0, __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) +#define vabdq_m(p0,p1,p2,p3) __arm_vabdq_m(p0,p1,p2,p3) +#define __arm_vabdq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vandq_m(p0,p1,p2,p3) __arm_vandq_m(p0,p1,p2,p3) +#define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vbicq_m(p0,p1,p2,p3) __arm_vbicq_m(p0,p1,p2,p3) +#define __arm_vbicq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vbrsrq_m(p0,p1,p2,p3) __arm_vbrsrq_m(p0,p1,p2,p3) +#define __arm_vbrsrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbrsrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbrsrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbrsrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __p2, p3));}) + +#define vcaddq_rot270_m(p0,p1,p2,p3) __arm_vcaddq_rot270_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vcaddq_rot90_m(p0,p1,p2,p3) __arm_vcaddq_rot90_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define veorq_m(p0,p1,p2,p3) __arm_veorq_m(p0,p1,p2,p3) +#define __arm_veorq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmaxq_m(p0,p1,p2,p3) __arm_vmaxq_m(p0,p1,p2,p3) +#define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vminq_m(p0,p1,p2,p3) __arm_vminq_m(p0,p1,p2,p3) +#define __arm_vminq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmladavaq_p(p0,p1,p2,p3) __arm_vmladavaq_p(p0,p1,p2,p3) +#define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmlaq_m(p0,p1,p2,p3) __arm_vmlaq_m(p0,p1,p2,p3) +#define __arm_vmlaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + +#define vmlasq_m(p0,p1,p2,p3) __arm_vmlasq_m(p0,p1,p2,p3) +#define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + +#define vmulhq_m(p0,p1,p2,p3) __arm_vmulhq_m(p0,p1,p2,p3) +#define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmullbq_int_m(p0,p1,p2,p3) __arm_vmullbq_int_m(p0,p1,p2,p3) +#define __arm_vmullbq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmulltq_int_m(p0,p1,p2,p3) __arm_vmulltq_int_m(p0,p1,p2,p3) +#define __arm_vmulltq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vornq_m(p0,p1,p2,p3) __arm_vornq_m(p0,p1,p2,p3) +#define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vorrq_m(p0,p1,p2,p3) __arm_vorrq_m(p0,p1,p2,p3) +#define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vqdmlahq_m(p0,p1,p2,p3) __arm_vqdmlahq_m(p0,p1,p2,p3) +#define __arm_vqdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + +#define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) +#define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + +#define vqrdmlashq_m(p0,p1,p2,p3) __arm_vqrdmlashq_m(p0,p1,p2,p3) +#define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + +#define vqrshlq_m(p0,p1,p2,p3) __arm_vqrshlq_m(p0,p1,p2,p3) +#define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqshlq_m_n(p0,p1,p2,p3) __arm_vqshlq_m_n(p0,p1,p2,p3) +#define __arm_vqshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqshlq_m(p0,p1,p2,p3) __arm_vqshlq_m(p0,p1,p2,p3) +#define __arm_vqshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vrhaddq_m(p0,p1,p2,p3) __arm_vrhaddq_m(p0,p1,p2,p3) +#define __arm_vrhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrmulhq_m(p0,p1,p2,p3) __arm_vrmulhq_m(p0,p1,p2,p3) +#define __arm_vrmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrshlq_m(p0,p1,p2,p3) __arm_vrshlq_m(p0,p1,p2,p3) +#define __arm_vrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vrshrq_m(p0,p1,p2,p3) __arm_vrshrq_m(p0,p1,p2,p3) +#define __arm_vrshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshrq_m(p0,p1,p2,p3) __arm_vshrq_m(p0,p1,p2,p3) +#define __arm_vshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vsliq_m(p0,p1,p2,p3) __arm_vsliq_m(p0,p1,p2,p3) +#define __arm_vsliq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vaddq_m(p0,p1,p2,p3) __arm_vaddq_m(p0,p1,p2,p3) +#define __arm_vaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vhaddq_m(p0,p1,p2,p3) __arm_vhaddq_m(p0,p1,p2,p3) +#define __arm_vhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vhcaddq_rot270_m(p0,p1,p2,p3) __arm_vhcaddq_rot270_m(p0,p1,p2,p3) +#define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vhcaddq_rot90_m(p0,p1,p2,p3) __arm_vhcaddq_rot90_m(p0,p1,p2,p3) +#define __arm_vhcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vhsubq_m(p0,p1,p2,p3) __arm_vhsubq_m(p0,p1,p2,p3) +#define __arm_vhsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + +#define vmulq_m(p0,p1,p2,p3) __arm_vmulq_m(p0,p1,p2,p3) +#define __arm_vmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vqaddq_m(p0,p1,p2,p3) __arm_vqaddq_m(p0,p1,p2,p3) +#define __arm_vqaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vqdmulhq_m(p0,p1,p2,p3) __arm_vqdmulhq_m(p0,p1,p2,p3) +#define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqsubq_m(p0,p1,p2,p3) __arm_vqsubq_m(p0,p1,p2,p3) +#define __arm_vqsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vqrdmulhq_m(p0,p1,p2,p3) __arm_vqrdmulhq_m(p0,p1,p2,p3) +#define __arm_vqrdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + + +#define vqrdmlsdhxq_m(p0,p1,p2,p3) __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) +#define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqrdmlsdhq_m(p0,p1,p2,p3) __arm_vqrdmlsdhq_m(p0,p1,p2,p3) +#define __arm_vqrdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqrdmladhq_m(p0,p1,p2,p3) __arm_vqrdmladhq_m(p0,p1,p2,p3) +#define __arm_vqrdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqrdmladhxq_m(p0,p1,p2,p3) __arm_vqrdmladhxq_m(p0,p1,p2,p3) +#define __arm_vqrdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vmlsdavaxq_p(p0,p1,p2,p3) __arm_vmlsdavaxq_p(p0,p1,p2,p3) +#define __arm_vmlsdavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaxq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaxq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaxq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vmlsdavaq_p(p0,p1,p2,p3) __arm_vmlsdavaq_p(p0,p1,p2,p3) +#define __arm_vmlsdavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vmladavaxq_p(p0,p1,p2,p3) __arm_vmladavaxq_p(p0,p1,p2,p3) +#define __arm_vmladavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + #endif /* MVE Integer. */ +#define vqdmladhq_m(p0,p1,p2,p3) __arm_vqdmladhq_m(p0,p1,p2,p3) +#define __arm_vqdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqdmladhxq_m(p0,p1,p2,p3) __arm_vqdmladhxq_m(p0,p1,p2,p3) +#define __arm_vqdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqdmlsdhq_m(p0,p1,p2,p3) __arm_vqdmlsdhq_m(p0,p1,p2,p3) +#define __arm_vqdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqdmlsdhxq_m(p0,p1,p2,p3) __arm_vqdmlsdhxq_m(p0,p1,p2,p3) +#define __arm_vqdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + #define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) #define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -13716,6 +16707,27 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) +#define vshlq_m_n(p0,p1,p2,p3) __arm_vshlq_m_n(p0,p1,p2,p3) +#define __arm_vshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) +#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + #define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3) #define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index c7d64ff..6665588 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -513,3 +513,103 @@ VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmulhq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrhaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vorrq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vornq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_int_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_int_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulhq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlasq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmladavaq_p_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vminq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmaxq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, veorq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot90_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot270_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vbicq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vandq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabdq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vrshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqrshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vbrsrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsliq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrhaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlashq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlahq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlahq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulltq_int_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmullbq_int_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaxq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlasq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaxq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot90_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot270_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsliq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b65849c..254cf93 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -143,7 +143,37 @@ VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U - VCVTQ_M_N_TO_F_S]) + VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S + VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S + VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S + VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U + VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S + VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F + VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U + VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S + VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U + VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S + VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F + VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S + VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F + VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U + VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U + VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U + VMULLBQ_INT_M_S VCADDQ_ROT90_M_F + VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U + VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U + VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S + VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S + VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S + VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S + VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U + VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S + VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S + VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S + VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S + VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S + VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S + VQRDMULHQ_M_N_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -251,7 +281,37 @@ (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u") (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s") (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s") - (VCVTQ_M_N_TO_F_U "u")]) + (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u") + (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u") + (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s") + (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u") + (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s") + (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s") + (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u") + (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u") + (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u") + (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u") + (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s") + (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u") + (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u") + (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s") + (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s") + (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u") + (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u") + (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u") + (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u") + (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u") + (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s") + (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u") + (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u") + (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u") + (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s") + (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s") + (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u") + (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s") + (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u") + (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u") + (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -419,6 +479,47 @@ (define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U]) (define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S]) (define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S]) +(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U]) +(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S]) +(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U]) +(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U]) +(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S]) +(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U]) +(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U]) +(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U]) +(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U]) +(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U]) +(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S]) +(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S]) +(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U]) +(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S]) +(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S]) +(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S]) +(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S]) +(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S]) +(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S]) +(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S]) +(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U]) +(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S]) +(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S]) +(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S]) +(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U]) +(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U]) +(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S]) +(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S]) +(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S]) +(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S]) +(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S]) +(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S]) +(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U]) +(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U]) +(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U]) +(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U]) +(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U]) +(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U]) +(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U]) +(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U]) + (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -5793,3 +5894,1023 @@ "vpst\;vcvtt.f%#.%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) +;; +;; [vabdq_m_s, vabdq_m_u]) +;; +(define_insn "mve_vabdq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VABDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vabdt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddq_m_n_s, vaddq_m_n_u]) +;; +(define_insn "mve_vaddq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADDQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddt.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddq_m_u, vaddq_m_s]) +;; +(define_insn "mve_vaddq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vaddt.i%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vandq_m_u, vandq_m_s]) +;; +(define_insn "mve_vandq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VANDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vandt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vbicq_m_u, vbicq_m_s]) +;; +(define_insn "mve_vbicq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VBICQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vbict %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vbrsrq_m_n_u, vbrsrq_m_n_s]) +;; +(define_insn "mve_vbrsrq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VBRSRQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vbrsrt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]) +;; +(define_insn "mve_vcaddq_rot270_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCADDQ_ROT270_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcaddt.i%# %q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]) +;; +(define_insn "mve_vcaddq_rot90_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCADDQ_ROT90_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vcaddt.i%# %q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [veorq_m_s, veorq_m_u]) +;; +(define_insn "mve_veorq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VEORQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;veort %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhaddq_m_n_s, vhaddq_m_n_u]) +;; +(define_insn "mve_vhaddq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHADDQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhaddt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhaddq_m_s, vhaddq_m_u]) +;; +(define_insn "mve_vhaddq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHADDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhaddt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhsubq_m_n_s, vhsubq_m_n_u]) +;; +(define_insn "mve_vhsubq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHSUBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhsubt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhsubq_m_s, vhsubq_m_u]) +;; +(define_insn "mve_vhsubq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHSUBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhsubt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxq_m_s, vmaxq_m_u]) +;; +(define_insn "mve_vmaxq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMAXQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmaxt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminq_m_s, vminq_m_u]) +;; +(define_insn "mve_vminq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMINQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmint.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmladavaq_p_u, vmladavaq_p_s]) +;; +(define_insn "mve_vmladavaq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLADAVAQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmladavat.%# %0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlaq_m_n_s, vmlaq_m_n_u]) +;; +(define_insn "mve_vmlaq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLAQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlat.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlasq_m_n_u, vmlasq_m_n_s]) +;; +(define_insn "mve_vmlasq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLASQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlast.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulhq_m_s, vmulhq_m_u]) +;; +(define_insn "mve_vmulhq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULHQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmulht.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmullbq_int_m_u, vmullbq_int_m_s]) +;; +(define_insn "mve_vmullbq_int_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULLBQ_INT_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmullbt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulltq_int_m_s, vmulltq_int_m_u]) +;; +(define_insn "mve_vmulltq_int_m_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULLTQ_INT_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmulltt.%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulq_m_n_u, vmulq_m_n_s]) +;; +(define_insn "mve_vmulq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmult.i%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulq_m_s, vmulq_m_u]) +;; +(define_insn "mve_vmulq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmult.i%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vornq_m_u, vornq_m_s]) +;; +(define_insn "mve_vornq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VORNQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vornt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vorrq_m_s, vorrq_m_u]) +;; +(define_insn "mve_vorrq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VORRQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vorrt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqaddq_m_n_u, vqaddq_m_n_s]) +;; +(define_insn "mve_vqaddq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQADDQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqaddt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqaddq_m_u, vqaddq_m_s]) +;; +(define_insn "mve_vqaddq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQADDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqaddt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmlahq_m_n_s]) +;; +(define_insn "mve_vqdmlahq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMLAHQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmlaht.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmlahq_m_n_s]) +;; +(define_insn "mve_vqrdmlahq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLAHQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmlaht.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmlashq_m_n_s]) +;; +(define_insn "mve_vqrdmlashq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLASHQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmlasht.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshlq_m_u, vqrshlq_m_s]) +;; +(define_insn "mve_vqrshlq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRSHLQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshlt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshlq_m_n_s, vqshlq_m_n_u]) +;; +(define_insn "mve_vqshlq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHLQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshlt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshlq_m_u, vqshlq_m_s]) +;; +(define_insn "mve_vqshlq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHLQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshlt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqsubq_m_n_u, vqsubq_m_n_s]) +;; +(define_insn "mve_vqsubq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSUBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqsubt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqsubq_m_u, vqsubq_m_s]) +;; +(define_insn "mve_vqsubq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSUBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqsubt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrhaddq_m_u, vrhaddq_m_s]) +;; +(define_insn "mve_vrhaddq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRHADDQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrhaddt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmulhq_m_u, vrmulhq_m_s]) +;; +(define_insn "mve_vrmulhq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMULHQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmulht.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshlq_m_s, vrshlq_m_u]) +;; +(define_insn "mve_vrshlq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRSHLQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrshlt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshrq_m_n_s, vrshrq_m_n_u]) +;; +(define_insn "mve_vrshrq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRSHRQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrshrt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshlq_m_n_s, vshlq_m_n_u]) +;; +(define_insn "mve_vshlq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHLQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshrq_m_n_s, vshrq_m_n_u]) +;; +(define_insn "mve_vshrq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHRQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshrt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vsliq_m_n_u, vsliq_m_n_s]) +;; +(define_insn "mve_vsliq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSLIQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vslit.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vsubq_m_n_s, vsubq_m_n_u]) +;; +(define_insn "mve_vsubq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSUBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsubt.i%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhcaddq_rot270_m_s]) +;; +(define_insn "mve_vhcaddq_rot270_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHCADDQ_ROT270_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhcaddt.s%#\t%q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vhcaddq_rot90_m_s]) +;; +(define_insn "mve_vhcaddq_rot90_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VHCADDQ_ROT90_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vhcaddt.s%#\t%q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmladavaxq_p_s]) +;; +(define_insn "mve_vmladavaxq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLADAVAXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmladavaxt.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsdavaq_p_s]) +;; +(define_insn "mve_vmlsdavaq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLSDAVAQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsdavat.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsdavaxq_p_s]) +;; +(define_insn "mve_vmlsdavaxq_p_s" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLSDAVAXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsdavaxt.s%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmladhq_m_s]) +;; +(define_insn "mve_vqdmladhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMLADHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmladht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmladhxq_m_s]) +;; +(define_insn "mve_vqdmladhxq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMLADHXQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmladhxt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmlsdhq_m_s]) +;; +(define_insn "mve_vqdmlsdhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMLSDHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmlsdht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmlsdhxq_m_s]) +;; +(define_insn "mve_vqdmlsdhxq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMLSDHXQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmlsdhxt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmulhq_m_n_s]) +;; +(define_insn "mve_vqdmulhq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULHQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmulht.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmulhq_m_s]) +;; +(define_insn "mve_vqdmulhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmulht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmladhq_m_s]) +;; +(define_insn "mve_vqrdmladhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLADHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmladht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmladhxq_m_s]) +;; +(define_insn "mve_vqrdmladhxq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLADHXQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmladhxt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmlsdhq_m_s]) +;; +(define_insn "mve_vqrdmlsdhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLSDHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmlsdht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmlsdhxq_m_s]) +;; +(define_insn "mve_vqrdmlsdhxq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMLSDHXQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmlsdhxt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmulhq_m_n_s]) +;; +(define_insn "mve_vqrdmulhq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMULHQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmulht.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrdmulhq_m_s]) +;; +(define_insn "mve_vqrdmulhq_m_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRDMULHQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrdmulht.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f4e117c..276c55f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,320 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c new file mode 100644 index 0000000..a51b4cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vabdq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c new file mode 100644 index 0000000..cddc068 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vabdq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c new file mode 100644 index 0000000..d6cbba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vabdq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c new file mode 100644 index 0000000..b35d8d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vabdq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c new file mode 100644 index 0000000..3055fc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vabdq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c new file mode 100644 index 0000000..03be33f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vabdq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c new file mode 100644 index 0000000..c18e1d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vaddq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c new file mode 100644 index 0000000..37b4443 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vaddq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c new file mode 100644 index 0000000..89cacc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vaddq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c new file mode 100644 index 0000000..9039f51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vaddq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c new file mode 100644 index 0000000..fdf11aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vaddq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c new file mode 100644 index 0000000..35b71db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vaddq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c new file mode 100644 index 0000000..337b766 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c new file mode 100644 index 0000000..5832354 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c new file mode 100644 index 0000000..9c40875 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c new file mode 100644 index 0000000..9bab84e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c new file mode 100644 index 0000000..b758ca6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c new file mode 100644 index 0000000..f5918d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c new file mode 100644 index 0000000..aa96d4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vandq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c new file mode 100644 index 0000000..e266b74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vandq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c new file mode 100644 index 0000000..680d98c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vandq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c new file mode 100644 index 0000000..ab5bb94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vandq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c new file mode 100644 index 0000000..408a309 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vandq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c new file mode 100644 index 0000000..0b63381 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vandq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c new file mode 100644 index 0000000..3e1e8a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vbicq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c new file mode 100644 index 0000000..20b2366 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vbicq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c new file mode 100644 index 0000000..a54609d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vbicq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c new file mode 100644 index 0000000..18f29b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vbicq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c new file mode 100644 index 0000000..840f613 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vbicq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c new file mode 100644 index 0000000..7ee6103 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vbicq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c new file mode 100644 index 0000000..fe011ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c new file mode 100644 index 0000000..22b2673 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c new file mode 100644 index 0000000..fab7ec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c new file mode 100644 index 0000000..6b0a5c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c new file mode 100644 index 0000000..68e4015 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c new file mode 100644 index 0000000..d9956dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c new file mode 100644 index 0000000..f906858 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c new file mode 100644 index 0000000..87d347c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c new file mode 100644 index 0000000..708d174 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c new file mode 100644 index 0000000..070a4fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c new file mode 100644 index 0000000..9f75313 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c new file mode 100644 index 0000000..4cb5a30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c new file mode 100644 index 0000000..30da2de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c new file mode 100644 index 0000000..4ee23c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c new file mode 100644 index 0000000..42f83a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c new file mode 100644 index 0000000..1bbaaf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c new file mode 100644 index 0000000..16ac73d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c new file mode 100644 index 0000000..bd4fdba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c new file mode 100644 index 0000000..7c3ff0d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return veorq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c new file mode 100644 index 0000000..a4e62e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return veorq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c new file mode 100644 index 0000000..e7c91aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return veorq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c new file mode 100644 index 0000000..9b2a380 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return veorq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c new file mode 100644 index 0000000..fdfc5de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return veorq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c new file mode 100644 index 0000000..741e186 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return veorq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c new file mode 100644 index 0000000..72cc006 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhaddq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c new file mode 100644 index 0000000..84c5f5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhaddq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c new file mode 100644 index 0000000..2a391cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhaddq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c new file mode 100644 index 0000000..3d6ce0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhaddq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c new file mode 100644 index 0000000..6acad1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhaddq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c new file mode 100644 index 0000000..709c8d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhaddq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c new file mode 100644 index 0000000..421116a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhaddq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c new file mode 100644 index 0000000..2f9b1bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhaddq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c new file mode 100644 index 0000000..b9cec7d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhaddq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c new file mode 100644 index 0000000..8045faf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhaddq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c new file mode 100644 index 0000000..c65a2e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhaddq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c new file mode 100644 index 0000000..164098a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhaddq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c new file mode 100644 index 0000000..bb9aa15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c new file mode 100644 index 0000000..d1a0f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c new file mode 100644 index 0000000..65ba174 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c new file mode 100644 index 0000000..3289c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c new file mode 100644 index 0000000..266c821 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c new file mode 100644 index 0000000..b42af74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c new file mode 100644 index 0000000..5e283a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhsubq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c new file mode 100644 index 0000000..ceefcd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhsubq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c new file mode 100644 index 0000000..85dde18 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhsubq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c new file mode 100644 index 0000000..ceeb5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhsubq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c new file mode 100644 index 0000000..b0656bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhsubq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c new file mode 100644 index 0000000..a1b9e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhsubq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c new file mode 100644 index 0000000..a5cc707 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhsubq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c new file mode 100644 index 0000000..7a0322f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhsubq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c new file mode 100644 index 0000000..c9f84d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhsubq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c new file mode 100644 index 0000000..0ea33ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhsubq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c new file mode 100644 index 0000000..5ee5da89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhsubq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c new file mode 100644 index 0000000..c5e2130 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhsubq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c new file mode 100644 index 0000000..d1ae619 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c new file mode 100644 index 0000000..7d23817 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c new file mode 100644 index 0000000..3f4f8d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c new file mode 100644 index 0000000..6d56612 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c new file mode 100644 index 0000000..fd7a4b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c new file mode 100644 index 0000000..885d9ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c new file mode 100644 index 0000000..84b8960 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c new file mode 100644 index 0000000..6181b85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c new file mode 100644 index 0000000..99fe68e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c new file mode 100644 index 0000000..a3f307d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c new file mode 100644 index 0000000..10b17c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c new file mode 100644 index 0000000..54898e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c new file mode 100644 index 0000000..3ec6294 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmladavaq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s16" } } */ +/* { dg-final { scan-assembler "vmladavat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c new file mode 100644 index 0000000..5af847d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmladavaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s32" } } */ +/* { dg-final { scan-assembler "vmladavat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c new file mode 100644 index 0000000..dc3d230 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmladavaq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.s8" } } */ +/* { dg-final { scan-assembler "vmladavat.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c new file mode 100644 index 0000000..8fe3ade --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmladavaq_p_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u16" } } */ +/* { dg-final { scan-assembler "vmladavat.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c new file mode 100644 index 0000000..924322e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmladavaq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u32" } } */ +/* { dg-final { scan-assembler "vmladavat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c new file mode 100644 index 0000000..6e44d37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vmladavaq_p_u8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vmladavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavat.u8" } } */ +/* { dg-final { scan-assembler "vmladavat.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c new file mode 100644 index 0000000..5ddefa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmladavaxq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmladavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ +/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c new file mode 100644 index 0000000..f25f764 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmladavaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmladavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ +/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c new file mode 100644 index 0000000..3ea63d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmladavaxq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmladavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ +/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c new file mode 100644 index 0000000..01b73b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vmlaq_m_n_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c new file mode 100644 index 0000000..c800e7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vmlaq_m_n_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c new file mode 100644 index 0000000..8fb6c70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vmlaq_m_n_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c new file mode 100644 index 0000000..9ec669a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) +{ + return vmlaq_m_n_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c new file mode 100644 index 0000000..2809abd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) +{ + return vmlaq_m_n_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c new file mode 100644 index 0000000..a662b26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) +{ + return vmlaq_m_n_u8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) +{ + return vmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlat.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c new file mode 100644 index 0000000..bf2209d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vmlasq_m_n_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c new file mode 100644 index 0000000..014f571 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vmlasq_m_n_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c new file mode 100644 index 0000000..a347adc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vmlasq_m_n_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c new file mode 100644 index 0000000..c0e3a26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) +{ + return vmlasq_m_n_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c new file mode 100644 index 0000000..c74df5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) +{ + return vmlasq_m_n_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c new file mode 100644 index 0000000..3ca4a4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) +{ + return vmlasq_m_n_u8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) +{ + return vmlasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmlast.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c new file mode 100644 index 0000000..8ef9665 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsdavaq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsdavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ +/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c new file mode 100644 index 0000000..40326c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsdavaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsdavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ +/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c new file mode 100644 index 0000000..5e035a3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmlsdavaq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmlsdavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ +/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c new file mode 100644 index 0000000..a1f4fe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ + +int32_t +foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ +/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c new file mode 100644 index 0000000..c659aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ + +int32_t +foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ +/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c new file mode 100644 index 0000000..462c04c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ + +int32_t +foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vmlsdavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ +/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c new file mode 100644 index 0000000..e73de9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c new file mode 100644 index 0000000..21fa61f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c new file mode 100644 index 0000000..e789775 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c new file mode 100644 index 0000000..0b6dba7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulhq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c new file mode 100644 index 0000000..265212a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulhq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c new file mode 100644 index 0000000..5212df1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulhq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c new file mode 100644 index 0000000..d1548b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c new file mode 100644 index 0000000..8ae8963 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c new file mode 100644 index 0000000..a5959c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c new file mode 100644 index 0000000..2fb7217 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c new file mode 100644 index 0000000..2ba1bfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u32" } } */ + +uint64x2_t +foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c new file mode 100644 index 0000000..fa15fd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c new file mode 100644 index 0000000..8c602dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c new file mode 100644 index 0000000..a5a3e8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c new file mode 100644 index 0000000..3dd90ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c new file mode 100644 index 0000000..9a8d766 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c new file mode 100644 index 0000000..0f072e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u32" } } */ + +uint64x2_t +foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c new file mode 100644 index 0000000..20c067b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c new file mode 100644 index 0000000..5c73b8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vmulq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c new file mode 100644 index 0000000..8cfa1b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vmulq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c new file mode 100644 index 0000000..82492dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vmulq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c new file mode 100644 index 0000000..9e2e483 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vmulq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c new file mode 100644 index 0000000..4aced38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vmulq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c new file mode 100644 index 0000000..7afcd47 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vmulq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c new file mode 100644 index 0000000..1b32d9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c new file mode 100644 index 0000000..cb4e54b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c new file mode 100644 index 0000000..90c8d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c new file mode 100644 index 0000000..7f10e89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c new file mode 100644 index 0000000..521658c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c new file mode 100644 index 0000000..d9af6fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c new file mode 100644 index 0000000..bc2c3b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vornq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c new file mode 100644 index 0000000..2c50ea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vornq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c new file mode 100644 index 0000000..20bf2eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vornq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c new file mode 100644 index 0000000..d3e68c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vornq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c new file mode 100644 index 0000000..594822e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vornq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c new file mode 100644 index 0000000..fcab2ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vornq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c new file mode 100644 index 0000000..cd55980 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vorrq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c new file mode 100644 index 0000000..6f7ce55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vorrq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c new file mode 100644 index 0000000..ed99e51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vorrq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c new file mode 100644 index 0000000..e48050a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vorrq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c new file mode 100644 index 0000000..611e815 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vorrq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c new file mode 100644 index 0000000..e2d49f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vorrq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c new file mode 100644 index 0000000..367bf20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqaddq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c new file mode 100644 index 0000000..3082db0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqaddq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c new file mode 100644 index 0000000..12e6573 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqaddq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c new file mode 100644 index 0000000..1ca7a1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vqaddq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c new file mode 100644 index 0000000..b27a7d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vqaddq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c new file mode 100644 index 0000000..434125e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vqaddq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c new file mode 100644 index 0000000..de13f24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqaddq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c new file mode 100644 index 0000000..57044b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqaddq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c new file mode 100644 index 0000000..6fa2718 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqaddq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c new file mode 100644 index 0000000..9f304eeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqaddq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c new file mode 100644 index 0000000..3fd179f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqaddq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c new file mode 100644 index 0000000..136cdb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vqaddq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vqaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c new file mode 100644 index 0000000..8061679 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmladhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c new file mode 100644 index 0000000..e6ee9a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmladhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c new file mode 100644 index 0000000..bf4ff90 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmladhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c new file mode 100644 index 0000000..d45c6e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmladhxq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c new file mode 100644 index 0000000..daea1cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmladhxq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c new file mode 100644 index 0000000..138cfd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmladhxq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c new file mode 100644 index 0000000..91e8889 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqdmlahq_m_n_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c new file mode 100644 index 0000000..2e08547 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqdmlahq_m_n_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c new file mode 100644 index 0000000..430a9cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqdmlahq_m_n_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlaht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c new file mode 100644 index 0000000..a79b13d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c new file mode 100644 index 0000000..c15b74a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c new file mode 100644 index 0000000..571962d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c new file mode 100644 index 0000000..47b95dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c new file mode 100644 index 0000000..6e20e5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c new file mode 100644 index 0000000..297db07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c new file mode 100644 index 0000000..747fd3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmulhq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c new file mode 100644 index 0000000..b50f914 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmulhq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c new file mode 100644 index 0000000..1f4dc63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqdmulhq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c new file mode 100644 index 0000000..59e6b18 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmulhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c new file mode 100644 index 0000000..b806a66 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmulhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c new file mode 100644 index 0000000..3f8fcf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmulhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c new file mode 100644 index 0000000..ba1b44d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmladhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c new file mode 100644 index 0000000..8503dfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmladhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c new file mode 100644 index 0000000..f13b625 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmladhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmladhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c new file mode 100644 index 0000000..854eac4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c new file mode 100644 index 0000000..b96ca34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c new file mode 100644 index 0000000..af480b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmladhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c new file mode 100644 index 0000000..b9cd42e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqrdmlahq_m_n_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqrdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c new file mode 100644 index 0000000..cf14605 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqrdmlahq_m_n_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqrdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c new file mode 100644 index 0000000..4ac58f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqrdmlahq_m_n_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqrdmlahq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c new file mode 100644 index 0000000..f62974e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqrdmlashq_m_n_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) +{ + return vqrdmlashq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c new file mode 100644 index 0000000..2250d74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqrdmlashq_m_n_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) +{ + return vqrdmlashq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c new file mode 100644 index 0000000..f85f302 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqrdmlashq_m_n_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) +{ + return vqrdmlashq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c new file mode 100644 index 0000000..0aae23f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c new file mode 100644 index 0000000..3490312 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c new file mode 100644 index 0000000..4fef001 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmlsdhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c new file mode 100644 index 0000000..ac86aae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c new file mode 100644 index 0000000..7dd2d42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c new file mode 100644 index 0000000..da2d78e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmlsdhxq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c new file mode 100644 index 0000000..ebea67e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c new file mode 100644 index 0000000..2ae4b9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c new file mode 100644 index 0000000..f44778e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c new file mode 100644 index 0000000..9acdb2f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c new file mode 100644 index 0000000..5b041f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c new file mode 100644 index 0000000..bb339ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmulhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrdmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c new file mode 100644 index 0000000..7139190 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshlq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c new file mode 100644 index 0000000..3fd1b46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshlq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c new file mode 100644 index 0000000..f23f5c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrshlq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c new file mode 100644 index 0000000..2675da7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshlq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c new file mode 100644 index 0000000..3da5ec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshlq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c new file mode 100644 index 0000000..2dd5be9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrshlq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c new file mode 100644 index 0000000..7077b94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshlq_m_n_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c new file mode 100644 index 0000000..301e9d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshlq_m_n_s32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c new file mode 100644 index 0000000..1cb13d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshlq_m_n_s8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c new file mode 100644 index 0000000..5832a1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vqshlq_m_n_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c new file mode 100644 index 0000000..73a8789 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vqshlq_m_n_u32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c new file mode 100644 index 0000000..18fd866 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vqshlq_m_n_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vqshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c new file mode 100644 index 0000000..ebca2cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshlq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c new file mode 100644 index 0000000..9e0c647 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshlq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c new file mode 100644 index 0000000..86850b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqshlq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c new file mode 100644 index 0000000..1615cbf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshlq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c new file mode 100644 index 0000000..97ac94c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshlq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c new file mode 100644 index 0000000..1f2de6d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqshlq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c new file mode 100644 index 0000000..823c1f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqsubq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c new file mode 100644 index 0000000..98c1c21 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqsubq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c new file mode 100644 index 0000000..dfe88e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqsubq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c new file mode 100644 index 0000000..2ede884 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vqsubq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c new file mode 100644 index 0000000..6396a97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vqsubq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c new file mode 100644 index 0000000..fadfcf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vqsubq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c new file mode 100644 index 0000000..d890d7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqsubq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c new file mode 100644 index 0000000..450a5bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqsubq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c new file mode 100644 index 0000000..88afb82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqsubq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c new file mode 100644 index 0000000..8a85984 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqsubq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c new file mode 100644 index 0000000..42bc3c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqsubq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c new file mode 100644 index 0000000..936a383 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vqsubq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vqsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqsubt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c new file mode 100644 index 0000000..e7c6df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrhaddq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c new file mode 100644 index 0000000..9643ad8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrhaddq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c new file mode 100644 index 0000000..a1e0411 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrhaddq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c new file mode 100644 index 0000000..490217c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrhaddq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c new file mode 100644 index 0000000..7935fae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrhaddq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c new file mode 100644 index 0000000..c49845b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrhaddq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrhaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c new file mode 100644 index 0000000..421fda1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrmulhq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c new file mode 100644 index 0000000..226747c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmulhq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c new file mode 100644 index 0000000..d90b02e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrmulhq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c new file mode 100644 index 0000000..1a3618d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrmulhq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c new file mode 100644 index 0000000..42b5efe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmulhq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c new file mode 100644 index 0000000..0bc3808 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrmulhq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrmulhq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c new file mode 100644 index 0000000..4143012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c new file mode 100644 index 0000000..9e0bb7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c new file mode 100644 index 0000000..5bcf233 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c new file mode 100644 index 0000000..59dd870 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c new file mode 100644 index 0000000..a5d72a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c new file mode 100644 index 0000000..0580991 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c new file mode 100644 index 0000000..bf8b870 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrshrq_m_n_s16 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c new file mode 100644 index 0000000..f6029fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vrshrq_m_n_s32 (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c new file mode 100644 index 0000000..07100c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrshrq_m_n_s8 (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c new file mode 100644 index 0000000..957d0e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrshrq_m_n_u16 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c new file mode 100644 index 0000000..bcca8e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vrshrq_m_n_u32 (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c new file mode 100644 index 0000000..2b53dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrshrq_m_n_u8 (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vrshrq_m (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c new file mode 100644 index 0000000..632b7bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshlq_m_n_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c new file mode 100644 index 0000000..833cef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vshlq_m_n_s32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c new file mode 100644 index 0000000..58b570d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshlq_m_n_s8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c new file mode 100644 index 0000000..b98324c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshlq_m_n_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c new file mode 100644 index 0000000..ddd72af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vshlq_m_n_u32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c new file mode 100644 index 0000000..ff9e57c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshlq_m_n_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshlq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c new file mode 100644 index 0000000..b9a31a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshrq_m_n_s16 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c new file mode 100644 index 0000000..b3a7767 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vshrq_m_n_s32 (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c new file mode 100644 index 0000000..f298429 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshrq_m_n_s8 (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c new file mode 100644 index 0000000..23099df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshrq_m_n_u16 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c new file mode 100644 index 0000000..12c1866 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vshrq_m_n_u32 (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c new file mode 100644 index 0000000..d88c5af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshrq_m_n_u8 (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshrq_m (inactive, a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c new file mode 100644 index 0000000..edaa7bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsliq_m_n_s16 (a, b, 15, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 15, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c new file mode 100644 index 0000000..8ea0d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsliq_m_n_s32 (a, b, 31, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 31, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c new file mode 100644 index 0000000..96c3bbc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsliq_m_n_s8 (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c new file mode 100644 index 0000000..40d0b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsliq_m_n_u16 (a, b, 15, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 15, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c new file mode 100644 index 0000000..14fcc4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsliq_m_n_u32 (a, b, 31, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 31, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c new file mode 100644 index 0000000..506bbd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsliq_m_n_u8 (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsliq_m (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vslit.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c new file mode 100644 index 0000000..42367dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vsubq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c new file mode 100644 index 0000000..31d2913 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vsubq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c new file mode 100644 index 0000000..052f06d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vsubq_m_n_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c new file mode 100644 index 0000000..5d1a1da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vsubq_m_n_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c new file mode 100644 index 0000000..64a7578 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vsubq_m_n_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c new file mode 100644 index 0000000..9eee226 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vsubq_m_n_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ -- cgit v1.1 From f2170a379b0fcd79191b5363cddaf0cbc508fd2b Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 17:06:58 +0000 Subject: [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. This patch supports following MVE ACLE intrinsics with quaternary operands. vmlaldavaq_p_s16, vmlaldavaq_p_s32, vmlaldavaq_p_u16, vmlaldavaq_p_u32, vmlaldavaxq_p_s16, vmlaldavaxq_p_s32, vmlaldavaxq_p_u16, vmlaldavaxq_p_u32, vmlsldavaq_p_s16, vmlsldavaq_p_s32, vmlsldavaxq_p_s16, vmlsldavaxq_p_s32, vmullbq_poly_m_p16, vmullbq_poly_m_p8, vmulltq_poly_m_p16, vmulltq_poly_m_p8, vqdmullbq_m_n_s16, vqdmullbq_m_n_s32, vqdmullbq_m_s16, vqdmullbq_m_s32, vqdmulltq_m_n_s16, vqdmulltq_m_n_s32, vqdmulltq_m_s16, vqdmulltq_m_s32, vqrshrnbq_m_n_s16, vqrshrnbq_m_n_s32, vqrshrnbq_m_n_u16, vqrshrnbq_m_n_u32, vqrshrntq_m_n_s16, vqrshrntq_m_n_s32, vqrshrntq_m_n_u16, vqrshrntq_m_n_u32, vqrshrunbq_m_n_s16, vqrshrunbq_m_n_s32, vqrshruntq_m_n_s16, vqrshruntq_m_n_s32, vqshrnbq_m_n_s16, vqshrnbq_m_n_s32, vqshrnbq_m_n_u16, vqshrnbq_m_n_u32, vqshrntq_m_n_s16, vqshrntq_m_n_s32, vqshrntq_m_n_u16, vqshrntq_m_n_u32, vqshrunbq_m_n_s16, vqshrunbq_m_n_s32, vqshruntq_m_n_s16, vqshruntq_m_n_s32, vrmlaldavhaq_p_s32, vrmlaldavhaq_p_u32, vrmlaldavhaxq_p_s32, vrmlsldavhaq_p_s32, vrmlsldavhaxq_p_s32, vrshrnbq_m_n_s16, vrshrnbq_m_n_s32, vrshrnbq_m_n_u16, vrshrnbq_m_n_u32, vrshrntq_m_n_s16, vrshrntq_m_n_s32, vrshrntq_m_n_u16, vrshrntq_m_n_u32, vshllbq_m_n_s16, vshllbq_m_n_s8, vshllbq_m_n_u16, vshllbq_m_n_u8, vshlltq_m_n_s16, vshlltq_m_n_s8, vshlltq_m_n_u16, vshlltq_m_n_u8, vshrnbq_m_n_s16, vshrnbq_m_n_s32, vshrnbq_m_n_u16, vshrnbq_m_n_u32, vshrntq_m_n_s16, vshrntq_m_n_s32, vshrntq_m_n_u16, vshrntq_m_n_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-protos.h (arm_mve_immediate_check): * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check mode and interger value. * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. (vmlaldavaq_p_s16): Likewise. (vmlaldavaq_p_u32): Likewise. (vmlaldavaq_p_u16): Likewise. (vmlaldavaxq_p_s32): Likewise. (vmlaldavaxq_p_s16): Likewise. (vmlaldavaxq_p_u32): Likewise. (vmlaldavaxq_p_u16): Likewise. (vmlsldavaq_p_s32): Likewise. (vmlsldavaq_p_s16): Likewise. (vmlsldavaxq_p_s32): Likewise. (vmlsldavaxq_p_s16): Likewise. (vmullbq_poly_m_p8): Likewise. (vmullbq_poly_m_p16): Likewise. (vmulltq_poly_m_p8): Likewise. (vmulltq_poly_m_p16): Likewise. (vqdmullbq_m_n_s32): Likewise. (vqdmullbq_m_n_s16): Likewise. (vqdmullbq_m_s32): Likewise. (vqdmullbq_m_s16): Likewise. (vqdmulltq_m_n_s32): Likewise. (vqdmulltq_m_n_s16): Likewise. (vqdmulltq_m_s32): Likewise. (vqdmulltq_m_s16): Likewise. (vqrshrnbq_m_n_s32): Likewise. (vqrshrnbq_m_n_s16): Likewise. (vqrshrnbq_m_n_u32): Likewise. (vqrshrnbq_m_n_u16): Likewise. (vqrshrntq_m_n_s32): Likewise. (vqrshrntq_m_n_s16): Likewise. (vqrshrntq_m_n_u32): Likewise. (vqrshrntq_m_n_u16): Likewise. (vqrshrunbq_m_n_s32): Likewise. (vqrshrunbq_m_n_s16): Likewise. (vqrshruntq_m_n_s32): Likewise. (vqrshruntq_m_n_s16): Likewise. (vqshrnbq_m_n_s32): Likewise. (vqshrnbq_m_n_s16): Likewise. (vqshrnbq_m_n_u32): Likewise. (vqshrnbq_m_n_u16): Likewise. (vqshrntq_m_n_s32): Likewise. (vqshrntq_m_n_s16): Likewise. (vqshrntq_m_n_u32): Likewise. (vqshrntq_m_n_u16): Likewise. (vqshrunbq_m_n_s32): Likewise. (vqshrunbq_m_n_s16): Likewise. (vqshruntq_m_n_s32): Likewise. (vqshruntq_m_n_s16): Likewise. (vrmlaldavhaq_p_s32): Likewise. (vrmlaldavhaq_p_u32): Likewise. (vrmlaldavhaxq_p_s32): Likewise. (vrmlsldavhaq_p_s32): Likewise. (vrmlsldavhaxq_p_s32): Likewise. (vrshrnbq_m_n_s32): Likewise. (vrshrnbq_m_n_s16): Likewise. (vrshrnbq_m_n_u32): Likewise. (vrshrnbq_m_n_u16): Likewise. (vrshrntq_m_n_s32): Likewise. (vrshrntq_m_n_s16): Likewise. (vrshrntq_m_n_u32): Likewise. (vrshrntq_m_n_u16): Likewise. (vshllbq_m_n_s8): Likewise. (vshllbq_m_n_s16): Likewise. (vshllbq_m_n_u8): Likewise. (vshllbq_m_n_u16): Likewise. (vshlltq_m_n_s8): Likewise. (vshlltq_m_n_s16): Likewise. (vshlltq_m_n_u8): Likewise. (vshlltq_m_n_u16): Likewise. (vshrnbq_m_n_s32): Likewise. (vshrnbq_m_n_s16): Likewise. (vshrnbq_m_n_u32): Likewise. (vshrnbq_m_n_u16): Likewise. (vshrntq_m_n_s32): Likewise. (vshrntq_m_n_s16): Likewise. (vshrntq_m_n_u32): Likewise. (vshrntq_m_n_u16): Likewise. (__arm_vmlaldavaq_p_s32): Define intrinsic. (__arm_vmlaldavaq_p_s16): Likewise. (__arm_vmlaldavaq_p_u32): Likewise. (__arm_vmlaldavaq_p_u16): Likewise. (__arm_vmlaldavaxq_p_s32): Likewise. (__arm_vmlaldavaxq_p_s16): Likewise. (__arm_vmlaldavaxq_p_u32): Likewise. (__arm_vmlaldavaxq_p_u16): Likewise. (__arm_vmlsldavaq_p_s32): Likewise. (__arm_vmlsldavaq_p_s16): Likewise. (__arm_vmlsldavaxq_p_s32): Likewise. (__arm_vmlsldavaxq_p_s16): Likewise. (__arm_vmullbq_poly_m_p8): Likewise. (__arm_vmullbq_poly_m_p16): Likewise. (__arm_vmulltq_poly_m_p8): Likewise. (__arm_vmulltq_poly_m_p16): Likewise. (__arm_vqdmullbq_m_n_s32): Likewise. (__arm_vqdmullbq_m_n_s16): Likewise. (__arm_vqdmullbq_m_s32): Likewise. (__arm_vqdmullbq_m_s16): Likewise. (__arm_vqdmulltq_m_n_s32): Likewise. (__arm_vqdmulltq_m_n_s16): Likewise. (__arm_vqdmulltq_m_s32): Likewise. (__arm_vqdmulltq_m_s16): Likewise. (__arm_vqrshrnbq_m_n_s32): Likewise. (__arm_vqrshrnbq_m_n_s16): Likewise. (__arm_vqrshrnbq_m_n_u32): Likewise. (__arm_vqrshrnbq_m_n_u16): Likewise. (__arm_vqrshrntq_m_n_s32): Likewise. (__arm_vqrshrntq_m_n_s16): Likewise. (__arm_vqrshrntq_m_n_u32): Likewise. (__arm_vqrshrntq_m_n_u16): Likewise. (__arm_vqrshrunbq_m_n_s32): Likewise. (__arm_vqrshrunbq_m_n_s16): Likewise. (__arm_vqrshruntq_m_n_s32): Likewise. (__arm_vqrshruntq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_s32): Likewise. (__arm_vqshrnbq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_u32): Likewise. (__arm_vqshrnbq_m_n_u16): Likewise. (__arm_vqshrntq_m_n_s32): Likewise. (__arm_vqshrntq_m_n_s16): Likewise. (__arm_vqshrntq_m_n_u32): Likewise. (__arm_vqshrntq_m_n_u16): Likewise. (__arm_vqshrunbq_m_n_s32): Likewise. (__arm_vqshrunbq_m_n_s16): Likewise. (__arm_vqshruntq_m_n_s32): Likewise. (__arm_vqshruntq_m_n_s16): Likewise. (__arm_vrmlaldavhaq_p_s32): Likewise. (__arm_vrmlaldavhaq_p_u32): Likewise. (__arm_vrmlaldavhaxq_p_s32): Likewise. (__arm_vrmlsldavhaq_p_s32): Likewise. (__arm_vrmlsldavhaxq_p_s32): Likewise. (__arm_vrshrnbq_m_n_s32): Likewise. (__arm_vrshrnbq_m_n_s16): Likewise. (__arm_vrshrnbq_m_n_u32): Likewise. (__arm_vrshrnbq_m_n_u16): Likewise. (__arm_vrshrntq_m_n_s32): Likewise. (__arm_vrshrntq_m_n_s16): Likewise. (__arm_vrshrntq_m_n_u32): Likewise. (__arm_vrshrntq_m_n_u16): Likewise. (__arm_vshllbq_m_n_s8): Likewise. (__arm_vshllbq_m_n_s16): Likewise. (__arm_vshllbq_m_n_u8): Likewise. (__arm_vshllbq_m_n_u16): Likewise. (__arm_vshlltq_m_n_s8): Likewise. (__arm_vshlltq_m_n_s16): Likewise. (__arm_vshlltq_m_n_u8): Likewise. (__arm_vshlltq_m_n_u16): Likewise. (__arm_vshrnbq_m_n_s32): Likewise. (__arm_vshrnbq_m_n_s16): Likewise. (__arm_vshrnbq_m_n_u32): Likewise. (__arm_vshrnbq_m_n_u16): Likewise. (__arm_vshrntq_m_n_s32): Likewise. (__arm_vshrntq_m_n_s16): Likewise. (__arm_vshrntq_m_n_u32): Likewise. (__arm_vshrntq_m_n_u16): Likewise. (vmullbq_poly_m): Define polymorphic variant. (vmulltq_poly_m): Likewise. (vshllbq_m): Likewise. (vshrntq_m_n): Likewise. (vshrnbq_m_n): Likewise. (vshlltq_m_n): Likewise. (vshllbq_m_n): Likewise. (vrshrntq_m_n): Likewise. (vrshrnbq_m_n): Likewise. (vqshruntq_m_n): Likewise. (vqshrunbq_m_n): Likewise. (vqdmullbq_m_n): Likewise. (vqdmullbq_m): Likewise. (vqdmulltq_m_n): Likewise. (vqdmulltq_m): Likewise. (vqrshrnbq_m_n): Likewise. (vqrshrntq_m_n): Likewise. (vqrshrunbq_m_n): Likewise. (vqrshruntq_m_n): Likewise. (vqshrnbq_m_n): Likewise. (vqshrntq_m_n): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifiers. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. (VMLALDAVAXQ_P): Likewise. (VQRSHRNBQ_M_N): Likewise. (VQRSHRNTQ_M_N): Likewise. (VQSHRNBQ_M_N): Likewise. (VQSHRNTQ_M_N): Likewise. (VRSHRNBQ_M_N): Likewise. (VRSHRNTQ_M_N): Likewise. (VSHLLBQ_M_N): Likewise. (VSHLLTQ_M_N): Likewise. (VSHRNBQ_M_N): Likewise. (VSHRNTQ_M_N): Likewise. (mve_vmlaldavaq_p_): Define RTL pattern. (mve_vmlaldavaxq_p_): Likewise. (mve_vqrshrnbq_m_n_): Likewise. (mve_vqrshrntq_m_n_): Likewise. (mve_vqshrnbq_m_n_): Likewise. (mve_vqshrntq_m_n_): Likewise. (mve_vrmlaldavhaq_p_sv4si): Likewise. (mve_vrshrnbq_m_n_): Likewise. (mve_vrshrntq_m_n_): Likewise. (mve_vshllbq_m_n_): Likewise. (mve_vshlltq_m_n_): Likewise. (mve_vshrnbq_m_n_): Likewise. (mve_vshrntq_m_n_): Likewise. (mve_vmlsldavaq_p_s): Likewise. (mve_vmlsldavaxq_p_s): Likewise. (mve_vmullbq_poly_m_p): Likewise. (mve_vmulltq_poly_m_p): Likewise. (mve_vqdmullbq_m_n_s): Likewise. (mve_vqdmullbq_m_s): Likewise. (mve_vqdmulltq_m_n_s): Likewise. (mve_vqdmulltq_m_s): Likewise. (mve_vqrshrunbq_m_n_s): Likewise. (mve_vqrshruntq_m_n_s): Likewise. (mve_vqshrunbq_m_n_s): Likewise. (mve_vqshruntq_m_n_s): Likewise. (mve_vrmlaldavhaq_p_uv4si): Likewise. (mve_vrmlaldavhaxq_p_sv4si): Likewise. (mve_vrmlsldavhaq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_p_sv4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. --- gcc/ChangeLog | 230 ++++++ gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 25 + gcc/config/arm/arm_mve.h | 824 ++++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 41 + gcc/config/arm/mve.md | 535 ++++++++++++- gcc/testsuite/ChangeLog | 82 ++ .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + 84 files changed, 3547 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e9e019a..8bb2b7e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,236 @@ 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni + + * config/arm/arm-protos.h (arm_mve_immediate_check): + * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check + mode and interger value. + * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. + (vmlaldavaq_p_s16): Likewise. + (vmlaldavaq_p_u32): Likewise. + (vmlaldavaq_p_u16): Likewise. + (vmlaldavaxq_p_s32): Likewise. + (vmlaldavaxq_p_s16): Likewise. + (vmlaldavaxq_p_u32): Likewise. + (vmlaldavaxq_p_u16): Likewise. + (vmlsldavaq_p_s32): Likewise. + (vmlsldavaq_p_s16): Likewise. + (vmlsldavaxq_p_s32): Likewise. + (vmlsldavaxq_p_s16): Likewise. + (vmullbq_poly_m_p8): Likewise. + (vmullbq_poly_m_p16): Likewise. + (vmulltq_poly_m_p8): Likewise. + (vmulltq_poly_m_p16): Likewise. + (vqdmullbq_m_n_s32): Likewise. + (vqdmullbq_m_n_s16): Likewise. + (vqdmullbq_m_s32): Likewise. + (vqdmullbq_m_s16): Likewise. + (vqdmulltq_m_n_s32): Likewise. + (vqdmulltq_m_n_s16): Likewise. + (vqdmulltq_m_s32): Likewise. + (vqdmulltq_m_s16): Likewise. + (vqrshrnbq_m_n_s32): Likewise. + (vqrshrnbq_m_n_s16): Likewise. + (vqrshrnbq_m_n_u32): Likewise. + (vqrshrnbq_m_n_u16): Likewise. + (vqrshrntq_m_n_s32): Likewise. + (vqrshrntq_m_n_s16): Likewise. + (vqrshrntq_m_n_u32): Likewise. + (vqrshrntq_m_n_u16): Likewise. + (vqrshrunbq_m_n_s32): Likewise. + (vqrshrunbq_m_n_s16): Likewise. + (vqrshruntq_m_n_s32): Likewise. + (vqrshruntq_m_n_s16): Likewise. + (vqshrnbq_m_n_s32): Likewise. + (vqshrnbq_m_n_s16): Likewise. + (vqshrnbq_m_n_u32): Likewise. + (vqshrnbq_m_n_u16): Likewise. + (vqshrntq_m_n_s32): Likewise. + (vqshrntq_m_n_s16): Likewise. + (vqshrntq_m_n_u32): Likewise. + (vqshrntq_m_n_u16): Likewise. + (vqshrunbq_m_n_s32): Likewise. + (vqshrunbq_m_n_s16): Likewise. + (vqshruntq_m_n_s32): Likewise. + (vqshruntq_m_n_s16): Likewise. + (vrmlaldavhaq_p_s32): Likewise. + (vrmlaldavhaq_p_u32): Likewise. + (vrmlaldavhaxq_p_s32): Likewise. + (vrmlsldavhaq_p_s32): Likewise. + (vrmlsldavhaxq_p_s32): Likewise. + (vrshrnbq_m_n_s32): Likewise. + (vrshrnbq_m_n_s16): Likewise. + (vrshrnbq_m_n_u32): Likewise. + (vrshrnbq_m_n_u16): Likewise. + (vrshrntq_m_n_s32): Likewise. + (vrshrntq_m_n_s16): Likewise. + (vrshrntq_m_n_u32): Likewise. + (vrshrntq_m_n_u16): Likewise. + (vshllbq_m_n_s8): Likewise. + (vshllbq_m_n_s16): Likewise. + (vshllbq_m_n_u8): Likewise. + (vshllbq_m_n_u16): Likewise. + (vshlltq_m_n_s8): Likewise. + (vshlltq_m_n_s16): Likewise. + (vshlltq_m_n_u8): Likewise. + (vshlltq_m_n_u16): Likewise. + (vshrnbq_m_n_s32): Likewise. + (vshrnbq_m_n_s16): Likewise. + (vshrnbq_m_n_u32): Likewise. + (vshrnbq_m_n_u16): Likewise. + (vshrntq_m_n_s32): Likewise. + (vshrntq_m_n_s16): Likewise. + (vshrntq_m_n_u32): Likewise. + (vshrntq_m_n_u16): Likewise. + (__arm_vmlaldavaq_p_s32): Define intrinsic. + (__arm_vmlaldavaq_p_s16): Likewise. + (__arm_vmlaldavaq_p_u32): Likewise. + (__arm_vmlaldavaq_p_u16): Likewise. + (__arm_vmlaldavaxq_p_s32): Likewise. + (__arm_vmlaldavaxq_p_s16): Likewise. + (__arm_vmlaldavaxq_p_u32): Likewise. + (__arm_vmlaldavaxq_p_u16): Likewise. + (__arm_vmlsldavaq_p_s32): Likewise. + (__arm_vmlsldavaq_p_s16): Likewise. + (__arm_vmlsldavaxq_p_s32): Likewise. + (__arm_vmlsldavaxq_p_s16): Likewise. + (__arm_vmullbq_poly_m_p8): Likewise. + (__arm_vmullbq_poly_m_p16): Likewise. + (__arm_vmulltq_poly_m_p8): Likewise. + (__arm_vmulltq_poly_m_p16): Likewise. + (__arm_vqdmullbq_m_n_s32): Likewise. + (__arm_vqdmullbq_m_n_s16): Likewise. + (__arm_vqdmullbq_m_s32): Likewise. + (__arm_vqdmullbq_m_s16): Likewise. + (__arm_vqdmulltq_m_n_s32): Likewise. + (__arm_vqdmulltq_m_n_s16): Likewise. + (__arm_vqdmulltq_m_s32): Likewise. + (__arm_vqdmulltq_m_s16): Likewise. + (__arm_vqrshrnbq_m_n_s32): Likewise. + (__arm_vqrshrnbq_m_n_s16): Likewise. + (__arm_vqrshrnbq_m_n_u32): Likewise. + (__arm_vqrshrnbq_m_n_u16): Likewise. + (__arm_vqrshrntq_m_n_s32): Likewise. + (__arm_vqrshrntq_m_n_s16): Likewise. + (__arm_vqrshrntq_m_n_u32): Likewise. + (__arm_vqrshrntq_m_n_u16): Likewise. + (__arm_vqrshrunbq_m_n_s32): Likewise. + (__arm_vqrshrunbq_m_n_s16): Likewise. + (__arm_vqrshruntq_m_n_s32): Likewise. + (__arm_vqrshruntq_m_n_s16): Likewise. + (__arm_vqshrnbq_m_n_s32): Likewise. + (__arm_vqshrnbq_m_n_s16): Likewise. + (__arm_vqshrnbq_m_n_u32): Likewise. + (__arm_vqshrnbq_m_n_u16): Likewise. + (__arm_vqshrntq_m_n_s32): Likewise. + (__arm_vqshrntq_m_n_s16): Likewise. + (__arm_vqshrntq_m_n_u32): Likewise. + (__arm_vqshrntq_m_n_u16): Likewise. + (__arm_vqshrunbq_m_n_s32): Likewise. + (__arm_vqshrunbq_m_n_s16): Likewise. + (__arm_vqshruntq_m_n_s32): Likewise. + (__arm_vqshruntq_m_n_s16): Likewise. + (__arm_vrmlaldavhaq_p_s32): Likewise. + (__arm_vrmlaldavhaq_p_u32): Likewise. + (__arm_vrmlaldavhaxq_p_s32): Likewise. + (__arm_vrmlsldavhaq_p_s32): Likewise. + (__arm_vrmlsldavhaxq_p_s32): Likewise. + (__arm_vrshrnbq_m_n_s32): Likewise. + (__arm_vrshrnbq_m_n_s16): Likewise. + (__arm_vrshrnbq_m_n_u32): Likewise. + (__arm_vrshrnbq_m_n_u16): Likewise. + (__arm_vrshrntq_m_n_s32): Likewise. + (__arm_vrshrntq_m_n_s16): Likewise. + (__arm_vrshrntq_m_n_u32): Likewise. + (__arm_vrshrntq_m_n_u16): Likewise. + (__arm_vshllbq_m_n_s8): Likewise. + (__arm_vshllbq_m_n_s16): Likewise. + (__arm_vshllbq_m_n_u8): Likewise. + (__arm_vshllbq_m_n_u16): Likewise. + (__arm_vshlltq_m_n_s8): Likewise. + (__arm_vshlltq_m_n_s16): Likewise. + (__arm_vshlltq_m_n_u8): Likewise. + (__arm_vshlltq_m_n_u16): Likewise. + (__arm_vshrnbq_m_n_s32): Likewise. + (__arm_vshrnbq_m_n_s16): Likewise. + (__arm_vshrnbq_m_n_u32): Likewise. + (__arm_vshrnbq_m_n_u16): Likewise. + (__arm_vshrntq_m_n_s32): Likewise. + (__arm_vshrntq_m_n_s16): Likewise. + (__arm_vshrntq_m_n_u32): Likewise. + (__arm_vshrntq_m_n_u16): Likewise. + (vmullbq_poly_m): Define polymorphic variant. + (vmulltq_poly_m): Likewise. + (vshllbq_m): Likewise. + (vshrntq_m_n): Likewise. + (vshrnbq_m_n): Likewise. + (vshlltq_m_n): Likewise. + (vshllbq_m_n): Likewise. + (vrshrntq_m_n): Likewise. + (vrshrnbq_m_n): Likewise. + (vqshruntq_m_n): Likewise. + (vqshrunbq_m_n): Likewise. + (vqdmullbq_m_n): Likewise. + (vqdmullbq_m): Likewise. + (vqdmulltq_m_n): Likewise. + (vqdmulltq_m): Likewise. + (vqrshrnbq_m_n): Likewise. + (vqrshrntq_m_n): Likewise. + (vqrshrunbq_m_n): Likewise. + (vqrshruntq_m_n): Likewise. + (vqshrnbq_m_n): Likewise. + (vqshrntq_m_n): Likewise. + * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use + builtin qualifiers. + (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. + (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. + * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. + (VMLALDAVAXQ_P): Likewise. + (VQRSHRNBQ_M_N): Likewise. + (VQRSHRNTQ_M_N): Likewise. + (VQSHRNBQ_M_N): Likewise. + (VQSHRNTQ_M_N): Likewise. + (VRSHRNBQ_M_N): Likewise. + (VRSHRNTQ_M_N): Likewise. + (VSHLLBQ_M_N): Likewise. + (VSHLLTQ_M_N): Likewise. + (VSHRNBQ_M_N): Likewise. + (VSHRNTQ_M_N): Likewise. + (mve_vmlaldavaq_p_): Define RTL pattern. + (mve_vmlaldavaxq_p_): Likewise. + (mve_vqrshrnbq_m_n_): Likewise. + (mve_vqrshrntq_m_n_): Likewise. + (mve_vqshrnbq_m_n_): Likewise. + (mve_vqshrntq_m_n_): Likewise. + (mve_vrmlaldavhaq_p_sv4si): Likewise. + (mve_vrshrnbq_m_n_): Likewise. + (mve_vrshrntq_m_n_): Likewise. + (mve_vshllbq_m_n_): Likewise. + (mve_vshlltq_m_n_): Likewise. + (mve_vshrnbq_m_n_): Likewise. + (mve_vshrntq_m_n_): Likewise. + (mve_vmlsldavaq_p_s): Likewise. + (mve_vmlsldavaxq_p_s): Likewise. + (mve_vmullbq_poly_m_p): Likewise. + (mve_vmulltq_poly_m_p): Likewise. + (mve_vqdmullbq_m_n_s): Likewise. + (mve_vqdmullbq_m_s): Likewise. + (mve_vqdmulltq_m_n_s): Likewise. + (mve_vqdmulltq_m_s): Likewise. + (mve_vqrshrunbq_m_n_s): Likewise. + (mve_vqrshruntq_m_n_s): Likewise. + (mve_vqshrunbq_m_n_s): Likewise. + (mve_vqshruntq_m_n_s): Likewise. + (mve_vrmlaldavhaq_p_uv4si): Likewise. + (mve_vrmlaldavhaxq_p_sv4si): Likewise. + (mve_vrmlsldavhaq_p_sv4si): Likewise. + (mve_vrmlsldavhaxq_p_sv4si): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni * config/arm/arm_mve.h (vabdq_m_s8): Define macro. (vabdq_m_s32): Likewise. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index b6710a6..9571b60 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -579,4 +579,5 @@ void arm_initialize_isa (sbitmap, const enum isa_feature *); const char * arm_gen_far_branch (rtx *, int, const char * , const char *); +bool arm_mve_immediate_check(rtx, machine_mode, bool); #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b3dfa28..9b79908 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -32702,6 +32702,31 @@ arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode, return true; } +/* To check op's immediate values matches the mode of the defined insn. */ +bool +arm_mve_immediate_check (rtx op, machine_mode mode, bool val) +{ + if (val) + { + if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7) + && (mode == E_V16QImode)) + || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15) + && (mode == E_V8HImode)) + || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 31) + && (mode == E_V4SImode))) + return true; + } + else + { + if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7) + && (mode == E_V8HImode)) + || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15) + && (mode == E_V4SImode))) + return true; + } + return false; +} + /* Can output mi_thunk for all cases except for non-zero vcall_offset in Thumb1. */ static bool diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 53bf29e..0662812 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1563,6 +1563,83 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vsubq_m_n_u8(__inactive, __a, __b, __p) #define vsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vsubq_m_n_u32(__inactive, __a, __b, __p) #define vsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vsubq_m_n_u16(__inactive, __a, __b, __p) +#define vmlaldavaq_p_s32(__a, __b, __c, __p) __arm_vmlaldavaq_p_s32(__a, __b, __c, __p) +#define vmlaldavaq_p_s16(__a, __b, __c, __p) __arm_vmlaldavaq_p_s16(__a, __b, __c, __p) +#define vmlaldavaq_p_u32(__a, __b, __c, __p) __arm_vmlaldavaq_p_u32(__a, __b, __c, __p) +#define vmlaldavaq_p_u16(__a, __b, __c, __p) __arm_vmlaldavaq_p_u16(__a, __b, __c, __p) +#define vmlaldavaxq_p_s32(__a, __b, __c, __p) __arm_vmlaldavaxq_p_s32(__a, __b, __c, __p) +#define vmlaldavaxq_p_s16(__a, __b, __c, __p) __arm_vmlaldavaxq_p_s16(__a, __b, __c, __p) +#define vmlaldavaxq_p_u32(__a, __b, __c, __p) __arm_vmlaldavaxq_p_u32(__a, __b, __c, __p) +#define vmlaldavaxq_p_u16(__a, __b, __c, __p) __arm_vmlaldavaxq_p_u16(__a, __b, __c, __p) +#define vmlsldavaq_p_s32(__a, __b, __c, __p) __arm_vmlsldavaq_p_s32(__a, __b, __c, __p) +#define vmlsldavaq_p_s16(__a, __b, __c, __p) __arm_vmlsldavaq_p_s16(__a, __b, __c, __p) +#define vmlsldavaxq_p_s32(__a, __b, __c, __p) __arm_vmlsldavaxq_p_s32(__a, __b, __c, __p) +#define vmlsldavaxq_p_s16(__a, __b, __c, __p) __arm_vmlsldavaxq_p_s16(__a, __b, __c, __p) +#define vmullbq_poly_m_p8(__inactive, __a, __b, __p) __arm_vmullbq_poly_m_p8(__inactive, __a, __b, __p) +#define vmullbq_poly_m_p16(__inactive, __a, __b, __p) __arm_vmullbq_poly_m_p16(__inactive, __a, __b, __p) +#define vmulltq_poly_m_p8(__inactive, __a, __b, __p) __arm_vmulltq_poly_m_p8(__inactive, __a, __b, __p) +#define vmulltq_poly_m_p16(__inactive, __a, __b, __p) __arm_vmulltq_poly_m_p16(__inactive, __a, __b, __p) +#define vqdmullbq_m_n_s32(__inactive, __a, __b, __p) __arm_vqdmullbq_m_n_s32(__inactive, __a, __b, __p) +#define vqdmullbq_m_n_s16(__inactive, __a, __b, __p) __arm_vqdmullbq_m_n_s16(__inactive, __a, __b, __p) +#define vqdmullbq_m_s32(__inactive, __a, __b, __p) __arm_vqdmullbq_m_s32(__inactive, __a, __b, __p) +#define vqdmullbq_m_s16(__inactive, __a, __b, __p) __arm_vqdmullbq_m_s16(__inactive, __a, __b, __p) +#define vqdmulltq_m_n_s32(__inactive, __a, __b, __p) __arm_vqdmulltq_m_n_s32(__inactive, __a, __b, __p) +#define vqdmulltq_m_n_s16(__inactive, __a, __b, __p) __arm_vqdmulltq_m_n_s16(__inactive, __a, __b, __p) +#define vqdmulltq_m_s32(__inactive, __a, __b, __p) __arm_vqdmulltq_m_s32(__inactive, __a, __b, __p) +#define vqdmulltq_m_s16(__inactive, __a, __b, __p) __arm_vqdmulltq_m_s16(__inactive, __a, __b, __p) +#define vqrshrnbq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshrnbq_m_n_s32(__a, __b, __imm, __p) +#define vqrshrnbq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshrnbq_m_n_s16(__a, __b, __imm, __p) +#define vqrshrnbq_m_n_u32(__a, __b, __imm, __p) __arm_vqrshrnbq_m_n_u32(__a, __b, __imm, __p) +#define vqrshrnbq_m_n_u16(__a, __b, __imm, __p) __arm_vqrshrnbq_m_n_u16(__a, __b, __imm, __p) +#define vqrshrntq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshrntq_m_n_s32(__a, __b, __imm, __p) +#define vqrshrntq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshrntq_m_n_s16(__a, __b, __imm, __p) +#define vqrshrntq_m_n_u32(__a, __b, __imm, __p) __arm_vqrshrntq_m_n_u32(__a, __b, __imm, __p) +#define vqrshrntq_m_n_u16(__a, __b, __imm, __p) __arm_vqrshrntq_m_n_u16(__a, __b, __imm, __p) +#define vqrshrunbq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshrunbq_m_n_s32(__a, __b, __imm, __p) +#define vqrshrunbq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshrunbq_m_n_s16(__a, __b, __imm, __p) +#define vqrshruntq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshruntq_m_n_s32(__a, __b, __imm, __p) +#define vqrshruntq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshruntq_m_n_s16(__a, __b, __imm, __p) +#define vqshrnbq_m_n_s32(__a, __b, __imm, __p) __arm_vqshrnbq_m_n_s32(__a, __b, __imm, __p) +#define vqshrnbq_m_n_s16(__a, __b, __imm, __p) __arm_vqshrnbq_m_n_s16(__a, __b, __imm, __p) +#define vqshrnbq_m_n_u32(__a, __b, __imm, __p) __arm_vqshrnbq_m_n_u32(__a, __b, __imm, __p) +#define vqshrnbq_m_n_u16(__a, __b, __imm, __p) __arm_vqshrnbq_m_n_u16(__a, __b, __imm, __p) +#define vqshrntq_m_n_s32(__a, __b, __imm, __p) __arm_vqshrntq_m_n_s32(__a, __b, __imm, __p) +#define vqshrntq_m_n_s16(__a, __b, __imm, __p) __arm_vqshrntq_m_n_s16(__a, __b, __imm, __p) +#define vqshrntq_m_n_u32(__a, __b, __imm, __p) __arm_vqshrntq_m_n_u32(__a, __b, __imm, __p) +#define vqshrntq_m_n_u16(__a, __b, __imm, __p) __arm_vqshrntq_m_n_u16(__a, __b, __imm, __p) +#define vqshrunbq_m_n_s32(__a, __b, __imm, __p) __arm_vqshrunbq_m_n_s32(__a, __b, __imm, __p) +#define vqshrunbq_m_n_s16(__a, __b, __imm, __p) __arm_vqshrunbq_m_n_s16(__a, __b, __imm, __p) +#define vqshruntq_m_n_s32(__a, __b, __imm, __p) __arm_vqshruntq_m_n_s32(__a, __b, __imm, __p) +#define vqshruntq_m_n_s16(__a, __b, __imm, __p) __arm_vqshruntq_m_n_s16(__a, __b, __imm, __p) +#define vrmlaldavhaq_p_s32(__a, __b, __c, __p) __arm_vrmlaldavhaq_p_s32(__a, __b, __c, __p) +#define vrmlaldavhaq_p_u32(__a, __b, __c, __p) __arm_vrmlaldavhaq_p_u32(__a, __b, __c, __p) +#define vrmlaldavhaxq_p_s32(__a, __b, __c, __p) __arm_vrmlaldavhaxq_p_s32(__a, __b, __c, __p) +#define vrmlsldavhaq_p_s32(__a, __b, __c, __p) __arm_vrmlsldavhaq_p_s32(__a, __b, __c, __p) +#define vrmlsldavhaxq_p_s32(__a, __b, __c, __p) __arm_vrmlsldavhaxq_p_s32(__a, __b, __c, __p) +#define vrshrnbq_m_n_s32(__a, __b, __imm, __p) __arm_vrshrnbq_m_n_s32(__a, __b, __imm, __p) +#define vrshrnbq_m_n_s16(__a, __b, __imm, __p) __arm_vrshrnbq_m_n_s16(__a, __b, __imm, __p) +#define vrshrnbq_m_n_u32(__a, __b, __imm, __p) __arm_vrshrnbq_m_n_u32(__a, __b, __imm, __p) +#define vrshrnbq_m_n_u16(__a, __b, __imm, __p) __arm_vrshrnbq_m_n_u16(__a, __b, __imm, __p) +#define vrshrntq_m_n_s32(__a, __b, __imm, __p) __arm_vrshrntq_m_n_s32(__a, __b, __imm, __p) +#define vrshrntq_m_n_s16(__a, __b, __imm, __p) __arm_vrshrntq_m_n_s16(__a, __b, __imm, __p) +#define vrshrntq_m_n_u32(__a, __b, __imm, __p) __arm_vrshrntq_m_n_u32(__a, __b, __imm, __p) +#define vrshrntq_m_n_u16(__a, __b, __imm, __p) __arm_vrshrntq_m_n_u16(__a, __b, __imm, __p) +#define vshllbq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshllbq_m_n_s8(__inactive, __a, __imm, __p) +#define vshllbq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshllbq_m_n_s16(__inactive, __a, __imm, __p) +#define vshllbq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshllbq_m_n_u8(__inactive, __a, __imm, __p) +#define vshllbq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshllbq_m_n_u16(__inactive, __a, __imm, __p) +#define vshlltq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshlltq_m_n_s8(__inactive, __a, __imm, __p) +#define vshlltq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshlltq_m_n_s16(__inactive, __a, __imm, __p) +#define vshlltq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshlltq_m_n_u8(__inactive, __a, __imm, __p) +#define vshlltq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshlltq_m_n_u16(__inactive, __a, __imm, __p) +#define vshrnbq_m_n_s32(__a, __b, __imm, __p) __arm_vshrnbq_m_n_s32(__a, __b, __imm, __p) +#define vshrnbq_m_n_s16(__a, __b, __imm, __p) __arm_vshrnbq_m_n_s16(__a, __b, __imm, __p) +#define vshrnbq_m_n_u32(__a, __b, __imm, __p) __arm_vshrnbq_m_n_u32(__a, __b, __imm, __p) +#define vshrnbq_m_n_u16(__a, __b, __imm, __p) __arm_vshrnbq_m_n_u16(__a, __b, __imm, __p) +#define vshrntq_m_n_s32(__a, __b, __imm, __p) __arm_vshrntq_m_n_s32(__a, __b, __imm, __p) +#define vshrntq_m_n_s16(__a, __b, __imm, __p) __arm_vshrntq_m_n_s16(__a, __b, __imm, __p) +#define vshrntq_m_n_u32(__a, __b, __imm, __p) __arm_vshrntq_m_n_u32(__a, __b, __imm, __p) +#define vshrntq_m_n_u16(__a, __b, __imm, __p) __arm_vshrntq_m_n_u16(__a, __b, __imm, __p) #endif __extension__ extern __inline void @@ -10317,6 +10394,545 @@ __arm_vsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pr return __builtin_mve_vsubq_m_n_uv8hi (__inactive, __a, __b, __p); } +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaq_p_s16 (int64_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaq_p_u32 (uint64_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaq_p_u16 (uint64_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaq_p_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaxq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaxq_p_s16 (int64_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaxq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaxq_p_u32 (uint64_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaxq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlaldavaxq_p_u16 (uint64_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlaldavaxq_p_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsldavaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsldavaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsldavaq_p_s16 (int64_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsldavaq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsldavaxq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsldavaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmlsldavaxq_p_s16 (int64_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vmlsldavaxq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_poly_m_p8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_poly_m_pv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmullbq_poly_m_p16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmullbq_poly_m_pv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_poly_m_p8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_poly_m_pv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulltq_poly_m_p16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulltq_poly_m_pv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmullbq_m_n_s32 (int64x2_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmullbq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmullbq_m_n_s16 (int32x4_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmullbq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmullbq_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmullbq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmullbq_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmullbq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulltq_m_n_s32 (int64x2_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulltq_m_n_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulltq_m_n_s16 (int32x4_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulltq_m_n_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulltq_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulltq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqdmulltq_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vqdmulltq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrnbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrnbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrnbq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrnbq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrnbq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrntq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrntq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrntq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrntq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrntq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrunbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshrunbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshruntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqrshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqrshruntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrnbq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrnbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrnbq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrnbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrnbq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrnbq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrnbq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrnbq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrntq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrntq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrntq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrntq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrntq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrunbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshrunbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshruntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshruntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vrmlaldavhaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhaq_p_u32 (uint64_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vrmlaldavhaq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlaldavhaxq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vrmlaldavhaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlsldavhaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vrmlsldavhaq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrmlsldavhaxq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vrmlsldavhaxq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrnbq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrnbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrnbq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrnbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrnbq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrnbq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrnbq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrnbq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrntq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrntq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrntq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrntq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrntq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshllbq_m_n_s8 (int16x8_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshllbq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshllbq_m_n_s16 (int32x4_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshllbq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshllbq_m_n_u8 (uint16x8_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshllbq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshllbq_m_n_u16 (uint32x4_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshllbq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlltq_m_n_s8 (int16x8_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlltq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlltq_m_n_s16 (int32x4_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlltq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlltq_m_n_u8 (uint16x8_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlltq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlltq_m_n_u16 (uint32x4_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlltq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrnbq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrnbq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrnbq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrnbq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrnbq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrnbq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrnbq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrnbq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrntq_m_n_s32 (int16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrntq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrntq_m_n_s16 (int8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrntq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrntq_m_n_u32 (uint16x8_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrntq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrntq_m_n_uv8hi (__a, __b, __imm, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -16547,7 +17163,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) - #define vqrdmlsdhxq_m(p0,p1,p2,p3) __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -16611,6 +17226,213 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) +#define vmullbq_poly_m(p0,p1,p2,p3) __arm_vmullbq_poly_m(p0,p1,p2,p3) +#define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + +#define vmulltq_poly_m(p0,p1,p2,p3) __arm_vmulltq_poly_m(p0,p1,p2,p3) +#define __arm_vmulltq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + +#define vshllbq_m(p0,p1,p2,p3) __arm_vshllbq_m(p0,p1,p2,p3) +#define __arm_vshllbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshllbq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshllbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshllbq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshllbq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vshrntq_m(p0,p1,p2,p3) __arm_vshrntq_m(p0,p1,p2,p3) +#define __arm_vshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshrnbq_m(p0,p1,p2,p3) __arm_vshrnbq_m(p0,p1,p2,p3) +#define __arm_vshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshlltq_m(p0,p1,p2,p3) __arm_vshlltq_m(p0,p1,p2,p3) +#define __arm_vshlltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshlltq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshlltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshlltq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshlltq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vrshrntq_m(p0,p1,p2,p3) __arm_vrshrntq_m(p0,p1,p2,p3) +#define __arm_vrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqshruntq_m(p0,p1,p2,p3) __arm_vqshruntq_m(p0,p1,p2,p3) +#define __arm_vqshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqshrunbq_m(p0,p1,p2,p3) __arm_vqshrunbq_m(p0,p1,p2,p3) +#define __arm_vqshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqdmullbq_m(p0,p1,p2,p3) __arm_vqdmullbq_m(p0,p1,p2,p3) +#define __arm_vqdmullbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + +#define vqdmulltq_m(p0,p1,p2,p3) __arm_vqdmulltq_m(p0,p1,p2,p3) +#define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqrshrnbq_m(p0,p1,p2,p3) __arm_vqrshrnbq_m(p0,p1,p2,p3) +#define __arm_vqrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqrshrntq_m(p0,p1,p2,p3) __arm_vqrshrntq_m(p0,p1,p2,p3) +#define __arm_vqrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqrshrunbq_m(p0,p1,p2,p3) __arm_vqrshrunbq_m(p0,p1,p2,p3) +#define __arm_vqrshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqrshruntq_m(p0,p1,p2,p3) __arm_vqrshruntq_m(p0,p1,p2,p3) +#define __arm_vqrshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqshrnbq_m(p0,p1,p2,p3) __arm_vqshrnbq_m(p0,p1,p2,p3) +#define __arm_vqshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqshrntq_m(p0,p1,p2,p3) __arm_vqshrntq_m(p0,p1,p2,p3) +#define __arm_vqshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vrshrnbq_m(p0,p1,p2,p3) __arm_vrshrnbq_m(p0,p1,p2,p3) +#define __arm_vrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vmlaldavaq_p(p0,p1,p2,p3) __arm_vmlaldavaq_p(p0,p1,p2,p3) +#define __arm_vmlaldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmlaldavaxq_p(p0,p1,p2,p3) __arm_vmlaldavaxq_p(p0,p1,p2,p3) +#define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaxq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaxq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmlsldavaq_p(p0,p1,p2,p3) __arm_vmlsldavaq_p(p0,p1,p2,p3) +#define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vmlsldavaxq_p(p0,p1,p2,p3) __arm_vmlsldavaxq_p(p0,p1,p2,p3) +#define __arm_vmlsldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaxq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaxq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vrmlaldavhaq_p(p0,p1,p2,p3) __arm_vrmlaldavhaq_p(p0,p1,p2,p3) +#define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) +#define __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p_s32(p0,p1,p2,p3) + +#define vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p(p0,p1,p2,p3) +#define __arm_vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p_s32(p0,p1,p2,p3) + +#define vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) +#define __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p_s32(p0,p1,p2,p3) + #endif /* MVE Integer. */ #define vqdmladhq_m(p0,p1,p2,p3) __arm_vqdmladhq_m(p0,p1,p2,p3) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 6665588..6048591 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -613,3 +613,44 @@ VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_poly_m_p, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_poly_m_p, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaxq_p_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_p_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlltq_m_n_u, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshllbq_m_n_u, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshruntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshrunbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshruntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshrunbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaxq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaxq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlltq_m_n_s, v16qi, v8hi) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshllbq_m_n_s, v16qi, v8hi) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrnbq_m_n_s, v8hi, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 254cf93..3dd33d8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -173,7 +173,20 @@ VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S - VQRDMULHQ_M_N_S]) + VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U + VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S + VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S + VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U + VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S + VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U + VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U + VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S + VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P + VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S + VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S + VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S + VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S + VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -311,7 +324,20 @@ (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s") (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u") (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u") - (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")]) + (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s") + (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u") + (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s") + (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u") + (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u") + (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u") + (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u") + (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s") + (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s") + (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u") + (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") + (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") + (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") + (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -519,7 +545,18 @@ (define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U]) (define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U]) (define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U]) - +(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S]) +(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S]) +(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S]) +(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U]) +(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S]) +(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U]) +(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S]) +(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S]) +(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S]) +(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) +(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) +(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -6914,3 +6951,495 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) +;; +;; [vmlaldavaq_p_u, vmlaldavaq_p_s]) +;; +(define_insn "mve_vmlaldavaq_p_" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLALDAVAQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlaldavat.%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s]) +;; +(define_insn "mve_vmlaldavaxq_p_" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLALDAVAXQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlaldavaxt.%# %Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]) +;; +(define_insn "mve_vqrshrnbq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRSHRNBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshrnbt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]) +;; +(define_insn "mve_vqrshrntq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRSHRNTQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshrntt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]) +;; +(define_insn "mve_vqshrnbq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHRNBQ_M_N)) + ] + "TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], mode, 0)" + "vpst\n\tvqshrnbt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshrntq_m_n_s, vqshrntq_m_n_u]) +;; +(define_insn "mve_vqshrntq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHRNTQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshrntt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlaldavhaq_p_s]) +;; +(define_insn "mve_vrmlaldavhaq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMLALDAVHAQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]) +;; +(define_insn "mve_vrshrnbq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRSHRNBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrshrnbt.i%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrshrntq_m_n_u, vrshrntq_m_n_s]) +;; +(define_insn "mve_vrshrntq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRSHRNTQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrshrntt.i%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshllbq_m_n_u, vshllbq_m_n_s]) +;; +(define_insn "mve_vshllbq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHLLBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshllbt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshlltq_m_n_u, vshlltq_m_n_s]) +;; +(define_insn "mve_vshlltq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:SI 3 "immediate_operand" "i") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHLLTQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlltt.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshrnbq_m_n_s, vshrnbq_m_n_u]) +;; +(define_insn "mve_vshrnbq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHRNBQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshrnbt.i%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshrntq_m_n_s, vshrntq_m_n_u]) +;; +(define_insn "mve_vshrntq_m_n_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "" "") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHRNTQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshrntt.i%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsldavaq_p_s]) +;; +(define_insn "mve_vmlsldavaq_p_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLSLDAVAQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsldavat.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmlsldavaxq_p_s]) +;; +(define_insn "mve_vmlsldavaxq_p_s" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMLSLDAVAXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmlsldavaxt.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmullbq_poly_m_p]) +;; +(define_insn "mve_vmullbq_poly_m_p" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:MVE_3 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULLBQ_POLY_M_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmullbt.p%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulltq_poly_m_p]) +;; +(define_insn "mve_vmulltq_poly_m_p" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_3 2 "s_register_operand" "w") + (match_operand:MVE_3 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULLTQ_POLY_M_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vmulltt.p%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmullbq_m_n_s]) +;; +(define_insn "mve_vqdmullbq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULLBQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmullbt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmullbq_m_s]) +;; +(define_insn "mve_vqdmullbq_m_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULLBQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmullbt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmulltq_m_n_s]) +;; +(define_insn "mve_vqdmulltq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULLTQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmulltt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqdmulltq_m_s]) +;; +(define_insn "mve_vqdmulltq_m_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:MVE_5 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQDMULLTQ_M_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqdmulltt.s%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshrunbq_m_n_s]) +;; +(define_insn "mve_vqrshrunbq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRSHRUNBQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshrunbt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqrshruntq_m_n_s]) +;; +(define_insn "mve_vqrshruntq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQRSHRUNTQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqrshruntt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshrunbq_m_n_s]) +;; +(define_insn "mve_vqshrunbq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHRUNBQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshrunbt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vqshruntq_m_n_s]) +;; +(define_insn "mve_vqshruntq_m_n_s" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand: 1 "s_register_operand" "0") + (match_operand:MVE_5 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHRUNTQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vqshruntt.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlaldavhaq_p_u]) +;; +(define_insn "mve_vrmlaldavhaq_p_uv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMLALDAVHAQ_P_U)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlaldavhaxq_p_s]) +;; +(define_insn "mve_vrmlaldavhaxq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMLALDAVHAXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlsldavhaq_p_s]) +;; +(define_insn "mve_vrmlsldavhaq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMLSLDAVHAQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vrmlsldavhaxq_p_s]) +;; +(define_insn "mve_vrmlsldavhaxq_p_sv4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VRMLSLDAVHAXQ_P_S)) + ] + "TARGET_HAVE_MVE" + "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 276c55f..650a6b9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,88 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c new file mode 100644 index 0000000..e984789 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlaldavaq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlaldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c new file mode 100644 index 0000000..e59f1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlaldavaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlaldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c new file mode 100644 index 0000000..78a3161 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmlaldavaq_p_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ + +uint64_t +foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmlaldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c new file mode 100644 index 0000000..093fa2e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmlaldavaq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmlaldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c new file mode 100644 index 0000000..ddc03ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c new file mode 100644 index 0000000..e2aa7b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c new file mode 100644 index 0000000..937e6f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.u16" } } */ + +uint64_t +foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c new file mode 100644 index 0000000..6f650f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vmlaldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlaldavaxt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c new file mode 100644 index 0000000..6b7e4b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsldavaq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c new file mode 100644 index 0000000..82867b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsldavaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsldavaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c new file mode 100644 index 0000000..8a44364 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsldavaxq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ + +int64_t +foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vmlsldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c new file mode 100644 index 0000000..e030858 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsldavaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vmlsldavaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c new file mode 100644 index 0000000..9128d66 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_poly_m_p16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_poly_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c new file mode 100644 index 0000000..32716b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_poly_m_p8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_poly_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c new file mode 100644 index 0000000..0ee24e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_poly_m_p16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_poly_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c new file mode 100644 index 0000000..2138081 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_poly_m_p8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_poly_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c new file mode 100644 index 0000000..df6fc10 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmullbq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmullbq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c new file mode 100644 index 0000000..337b9a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmullbq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmullbq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c new file mode 100644 index 0000000..b9054a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmullbq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmullbq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c new file mode 100644 index 0000000..65d14fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmullbq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmullbq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c new file mode 100644 index 0000000..dee11f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmulltq_m_n_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vqdmulltq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c new file mode 100644 index 0000000..abba2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmulltq_m_n_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vqdmulltq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c new file mode 100644 index 0000000..45ee4a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmulltq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vqdmulltq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c new file mode 100644 index 0000000..692fcf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmulltq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ + +int64x2_t +foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vqdmulltq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c new file mode 100644 index 0000000..fca9f97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrnbq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c new file mode 100644 index 0000000..f3b3eba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrnbq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c new file mode 100644 index 0000000..1a64f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqrshrnbq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c new file mode 100644 index 0000000..3956775 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqrshrnbq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c new file mode 100644 index 0000000..be88766 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrntq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c new file mode 100644 index 0000000..d17caae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrntq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c new file mode 100644 index 0000000..76328bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqrshrntq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c new file mode 100644 index 0000000..175fd6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqrshrntq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c new file mode 100644 index 0000000..dfad144 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrunbq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshrunbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c new file mode 100644 index 0000000..4fdd296 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrunbq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshrunbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c new file mode 100644 index 0000000..ad01c2f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshruntq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqrshruntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c new file mode 100644 index 0000000..a4d10ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshruntq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqrshruntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c new file mode 100644 index 0000000..94c369e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrnbq_m_n_s16 (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrnbq_m (a, b, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c new file mode 100644 index 0000000..33cc442 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrnbq_m_n_s32 (a, b, 11, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrnbq_m (a, b, 11, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c new file mode 100644 index 0000000..49ce2de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqshrnbq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c new file mode 100644 index 0000000..56bc3fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqshrnbq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c new file mode 100644 index 0000000..b746c16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrntq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.s16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c new file mode 100644 index 0000000..9132ac1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrntq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.s32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c new file mode 100644 index 0000000..3124c83 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqshrntq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.u16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vqshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c new file mode 100644 index 0000000..ebef349 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqshrntq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.u32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vqshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrntt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c new file mode 100644 index 0000000..f4fdc0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrunbq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshrunbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c new file mode 100644 index 0000000..d6a0eb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrunbq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshrunbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c new file mode 100644 index 0000000..47b3c9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshruntq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshruntt.s16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vqshruntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshruntt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c new file mode 100644 index 0000000..7697660 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshruntq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshruntt.s32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vqshruntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshruntt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c new file mode 100644 index 0000000..5dbd263 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhat.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c new file mode 100644 index 0000000..02fd762 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhat.u32" } } */ + +uint64_t +foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhat.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c new file mode 100644 index 0000000..45ae394 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlaldavhaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c new file mode 100644 index 0000000..d32aa69 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlsldavhaq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlsldavhaq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c new file mode 100644 index 0000000..2b629f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlsldavhaxq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ + +int64_t +foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vrmlsldavhaxq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c new file mode 100644 index 0000000..b3bb8b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshrnbq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c new file mode 100644 index 0000000..375be7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshrnbq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c new file mode 100644 index 0000000..73a1f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrshrnbq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c new file mode 100644 index 0000000..30d4125 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrshrnbq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrshrnbq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c new file mode 100644 index 0000000..29c76ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshrntq_m_n_s16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c new file mode 100644 index 0000000..ae490fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshrntq_m_n_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c new file mode 100644 index 0000000..5163f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrshrntq_m_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c new file mode 100644 index 0000000..bba6543 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrshrntq_m_n_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrshrntq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrntt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c new file mode 100644 index 0000000..adf52c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshllbq_m_n_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshllbq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c new file mode 100644 index 0000000..6ae43ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshllbq_m_n_s8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshllbq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c new file mode 100644 index 0000000..b643afb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshllbq_m_n_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshllbq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c new file mode 100644 index 0000000..79648c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshllbq_m_n_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshllbq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c new file mode 100644 index 0000000..7f0b0dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshlltq_m_n_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s16" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vshlltq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c new file mode 100644 index 0000000..cfea61d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshlltq_m_n_s8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s8" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vshlltq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c new file mode 100644 index 0000000..cc3b7b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshlltq_m_n_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u16" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vshlltq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c new file mode 100644 index 0000000..857d954 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshlltq_m_n_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u8" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) +{ + return vshlltq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c new file mode 100644 index 0000000..e2d86a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vshrnbq_m_n_s16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vshrnbq_m (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c new file mode 100644 index 0000000..d13b28d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vshrnbq_m_n_s32 (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vshrnbq_m (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c new file mode 100644 index 0000000..d008bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vshrnbq_m_n_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vshrnbq_m (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c new file mode 100644 index 0000000..daad549 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vshrnbq_m_n_u32 (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vshrnbq_m (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrnbt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c new file mode 100644 index 0000000..86dbb1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vshrntq_m_n_s16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i16" } } */ + +int8x16_t +foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) +{ + return vshrntq_m (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c new file mode 100644 index 0000000..df4d5aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vshrntq_m_n_s32 (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i32" } } */ + +int16x8_t +foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) +{ + return vshrntq_m (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c new file mode 100644 index 0000000..4d2111f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vshrntq_m_n_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i16" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) +{ + return vshrntq_m (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c new file mode 100644 index 0000000..6c3eda5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vshrntq_m_n_u32 (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i32" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) +{ + return vshrntq_m (a, b, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrntt.i32" } } */ -- cgit v1.1 From 532e9e2402a62367b965b0901478d27570b6d3a2 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 17:16:21 +0000 Subject: [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. This patch supports following MVE ACLE intrinsics with quaternary operands. vabdq_m_f32, vabdq_m_f16, vaddq_m_f32, vaddq_m_f16, vaddq_m_n_f32, vaddq_m_n_f16, vandq_m_f32, vandq_m_f16, vbicq_m_f32, vbicq_m_f16, vbrsrq_m_n_f32, vbrsrq_m_n_f16, vcaddq_rot270_m_f32, vcaddq_rot270_m_f16, vcaddq_rot90_m_f32, vcaddq_rot90_m_f16, vcmlaq_m_f32, vcmlaq_m_f16, vcmlaq_rot180_m_f32, vcmlaq_rot180_m_f16, vcmlaq_rot270_m_f32, vcmlaq_rot270_m_f16, vcmlaq_rot90_m_f32, vcmlaq_rot90_m_f16, vcmulq_m_f32, vcmulq_m_f16, vcmulq_rot180_m_f32, vcmulq_rot180_m_f16, vcmulq_rot270_m_f32, vcmulq_rot270_m_f16, vcmulq_rot90_m_f32, vcmulq_rot90_m_f16, vcvtq_m_n_s32_f32, vcvtq_m_n_s16_f16, vcvtq_m_n_u32_f32, vcvtq_m_n_u16_f16, veorq_m_f32, veorq_m_f16, vfmaq_m_f32, vfmaq_m_f16, vfmaq_m_n_f32, vfmaq_m_n_f16, vfmasq_m_n_f32, vfmasq_m_n_f16, vfmsq_m_f32, vfmsq_m_f16, vmaxnmq_m_f32, vmaxnmq_m_f16, vminnmq_m_f32, vminnmq_m_f16, vmulq_m_f32, vmulq_m_f16, vmulq_m_n_f32, vmulq_m_n_f16, vornq_m_f32, vornq_m_f16, vorrq_m_f32, vorrq_m_f16, vsubq_m_f32, vsubq_m_f16, vsubq_m_n_f32, vsubq_m_n_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vabdq_m_f32): Define macro. (vabdq_m_f16): Likewise. (vaddq_m_f32): Likewise. (vaddq_m_f16): Likewise. (vaddq_m_n_f32): Likewise. (vaddq_m_n_f16): Likewise. (vandq_m_f32): Likewise. (vandq_m_f16): Likewise. (vbicq_m_f32): Likewise. (vbicq_m_f16): Likewise. (vbrsrq_m_n_f32): Likewise. (vbrsrq_m_n_f16): Likewise. (vcaddq_rot270_m_f32): Likewise. (vcaddq_rot270_m_f16): Likewise. (vcaddq_rot90_m_f32): Likewise. (vcaddq_rot90_m_f16): Likewise. (vcmlaq_m_f32): Likewise. (vcmlaq_m_f16): Likewise. (vcmlaq_rot180_m_f32): Likewise. (vcmlaq_rot180_m_f16): Likewise. (vcmlaq_rot270_m_f32): Likewise. (vcmlaq_rot270_m_f16): Likewise. (vcmlaq_rot90_m_f32): Likewise. (vcmlaq_rot90_m_f16): Likewise. (vcmulq_m_f32): Likewise. (vcmulq_m_f16): Likewise. (vcmulq_rot180_m_f32): Likewise. (vcmulq_rot180_m_f16): Likewise. (vcmulq_rot270_m_f32): Likewise. (vcmulq_rot270_m_f16): Likewise. (vcmulq_rot90_m_f32): Likewise. (vcmulq_rot90_m_f16): Likewise. (vcvtq_m_n_s32_f32): Likewise. (vcvtq_m_n_s16_f16): Likewise. (vcvtq_m_n_u32_f32): Likewise. (vcvtq_m_n_u16_f16): Likewise. (veorq_m_f32): Likewise. (veorq_m_f16): Likewise. (vfmaq_m_f32): Likewise. (vfmaq_m_f16): Likewise. (vfmaq_m_n_f32): Likewise. (vfmaq_m_n_f16): Likewise. (vfmasq_m_n_f32): Likewise. (vfmasq_m_n_f16): Likewise. (vfmsq_m_f32): Likewise. (vfmsq_m_f16): Likewise. (vmaxnmq_m_f32): Likewise. (vmaxnmq_m_f16): Likewise. (vminnmq_m_f32): Likewise. (vminnmq_m_f16): Likewise. (vmulq_m_f32): Likewise. (vmulq_m_f16): Likewise. (vmulq_m_n_f32): Likewise. (vmulq_m_n_f16): Likewise. (vornq_m_f32): Likewise. (vornq_m_f16): Likewise. (vorrq_m_f32): Likewise. (vorrq_m_f16): Likewise. (vsubq_m_f32): Likewise. (vsubq_m_f16): Likewise. (vsubq_m_n_f32): Likewise. (vsubq_m_n_f16): Likewise. (__attribute__): Likewise. (__arm_vabdq_m_f32): Likewise. (__arm_vabdq_m_f16): Likewise. (__arm_vaddq_m_f32): Likewise. (__arm_vaddq_m_f16): Likewise. (__arm_vaddq_m_n_f32): Likewise. (__arm_vaddq_m_n_f16): Likewise. (__arm_vandq_m_f32): Likewise. (__arm_vandq_m_f16): Likewise. (__arm_vbicq_m_f32): Likewise. (__arm_vbicq_m_f16): Likewise. (__arm_vbrsrq_m_n_f32): Likewise. (__arm_vbrsrq_m_n_f16): Likewise. (__arm_vcaddq_rot270_m_f32): Likewise. (__arm_vcaddq_rot270_m_f16): Likewise. (__arm_vcaddq_rot90_m_f32): Likewise. (__arm_vcaddq_rot90_m_f16): Likewise. (__arm_vcmlaq_m_f32): Likewise. (__arm_vcmlaq_m_f16): Likewise. (__arm_vcmlaq_rot180_m_f32): Likewise. (__arm_vcmlaq_rot180_m_f16): Likewise. (__arm_vcmlaq_rot270_m_f32): Likewise. (__arm_vcmlaq_rot270_m_f16): Likewise. (__arm_vcmlaq_rot90_m_f32): Likewise. (__arm_vcmlaq_rot90_m_f16): Likewise. (__arm_vcmulq_m_f32): Likewise. (__arm_vcmulq_m_f16): Likewise. (__arm_vcmulq_rot180_m_f32): Define intrinsic. (__arm_vcmulq_rot180_m_f16): Likewise. (__arm_vcmulq_rot270_m_f32): Likewise. (__arm_vcmulq_rot270_m_f16): Likewise. (__arm_vcmulq_rot90_m_f32): Likewise. (__arm_vcmulq_rot90_m_f16): Likewise. (__arm_vcvtq_m_n_s32_f32): Likewise. (__arm_vcvtq_m_n_s16_f16): Likewise. (__arm_vcvtq_m_n_u32_f32): Likewise. (__arm_vcvtq_m_n_u16_f16): Likewise. (__arm_veorq_m_f32): Likewise. (__arm_veorq_m_f16): Likewise. (__arm_vfmaq_m_f32): Likewise. (__arm_vfmaq_m_f16): Likewise. (__arm_vfmaq_m_n_f32): Likewise. (__arm_vfmaq_m_n_f16): Likewise. (__arm_vfmasq_m_n_f32): Likewise. (__arm_vfmasq_m_n_f16): Likewise. (__arm_vfmsq_m_f32): Likewise. (__arm_vfmsq_m_f16): Likewise. (__arm_vmaxnmq_m_f32): Likewise. (__arm_vmaxnmq_m_f16): Likewise. (__arm_vminnmq_m_f32): Likewise. (__arm_vminnmq_m_f16): Likewise. (__arm_vmulq_m_f32): Likewise. (__arm_vmulq_m_f16): Likewise. (__arm_vmulq_m_n_f32): Likewise. (__arm_vmulq_m_n_f16): Likewise. (__arm_vornq_m_f32): Likewise. (__arm_vornq_m_f16): Likewise. (__arm_vorrq_m_f32): Likewise. (__arm_vorrq_m_f16): Likewise. (__arm_vsubq_m_f32): Likewise. (__arm_vsubq_m_f16): Likewise. (__arm_vsubq_m_n_f32): Likewise. (__arm_vsubq_m_n_f16): Likewise. (vabdq_m): Define polymorphic variant. (vaddq_m): Likewise. (vaddq_m_n): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (vcmlaq_m): Likewise. (vcmlaq_rot180_m): Likewise. (vcmlaq_rot270_m): Likewise. (vcmlaq_rot90_m): Likewise. (vcmulq_m): Likewise. (vcmulq_rot180_m): Likewise. (vcmulq_rot270_m): Likewise. (vcmulq_rot90_m): Likewise. (veorq_m): Likewise. (vfmaq_m): Likewise. (vfmaq_m_n): Likewise. (vfmasq_m_n): Likewise. (vfmsq_m): Likewise. (vmaxnmq_m): Likewise. (vminnmq_m): Likewise. (vmulq_m): Likewise. (vmulq_m_n): Likewise. (vornq_m): Likewise. (vsubq_m): Likewise. (vsubq_m_n): Likewise. (vorrq_m): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. * config/arm/mve.md (mve_vabdq_m_f): Define RTL pattern. (mve_vaddq_m_f): Likewise. (mve_vaddq_m_n_f): Likewise. (mve_vandq_m_f): Likewise. (mve_vbicq_m_f): Likewise. (mve_vbrsrq_m_n_f): Likewise. (mve_vcaddq_rot270_m_f): Likewise. (mve_vcaddq_rot90_m_f): Likewise. (mve_vcmlaq_m_f): Likewise. (mve_vcmlaq_rot180_m_f): Likewise. (mve_vcmlaq_rot270_m_f): Likewise. (mve_vcmlaq_rot90_m_f): Likewise. (mve_vcmulq_m_f): Likewise. (mve_vcmulq_rot180_m_f): Likewise. (mve_vcmulq_rot270_m_f): Likewise. (mve_vcmulq_rot90_m_f): Likewise. (mve_veorq_m_f): Likewise. (mve_vfmaq_m_f): Likewise. (mve_vfmaq_m_n_f): Likewise. (mve_vfmasq_m_n_f): Likewise. (mve_vfmsq_m_f): Likewise. (mve_vmaxnmq_m_f): Likewise. (mve_vminnmq_m_f): Likewise. (mve_vmulq_m_f): Likewise. (mve_vmulq_m_n_f): Likewise. (mve_vornq_m_f): Likewise. (mve_vorrq_m_f): Likewise. (mve_vsubq_m_f): Likewise. (mve_vsubq_m_n_f): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. --- gcc/ChangeLog | 192 ++ gcc/config/arm/arm_mve.h | 2096 ++++++++++++++------ gcc/config/arm/arm_mve_builtins.def | 31 + gcc/config/arm/mve.md | 499 ++++- gcc/testsuite/ChangeLog | 67 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 24 + 67 files changed, 3722 insertions(+), 651 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8bb2b7e..3b1154b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,198 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vabdq_m_f32): Define macro. + (vabdq_m_f16): Likewise. + (vaddq_m_f32): Likewise. + (vaddq_m_f16): Likewise. + (vaddq_m_n_f32): Likewise. + (vaddq_m_n_f16): Likewise. + (vandq_m_f32): Likewise. + (vandq_m_f16): Likewise. + (vbicq_m_f32): Likewise. + (vbicq_m_f16): Likewise. + (vbrsrq_m_n_f32): Likewise. + (vbrsrq_m_n_f16): Likewise. + (vcaddq_rot270_m_f32): Likewise. + (vcaddq_rot270_m_f16): Likewise. + (vcaddq_rot90_m_f32): Likewise. + (vcaddq_rot90_m_f16): Likewise. + (vcmlaq_m_f32): Likewise. + (vcmlaq_m_f16): Likewise. + (vcmlaq_rot180_m_f32): Likewise. + (vcmlaq_rot180_m_f16): Likewise. + (vcmlaq_rot270_m_f32): Likewise. + (vcmlaq_rot270_m_f16): Likewise. + (vcmlaq_rot90_m_f32): Likewise. + (vcmlaq_rot90_m_f16): Likewise. + (vcmulq_m_f32): Likewise. + (vcmulq_m_f16): Likewise. + (vcmulq_rot180_m_f32): Likewise. + (vcmulq_rot180_m_f16): Likewise. + (vcmulq_rot270_m_f32): Likewise. + (vcmulq_rot270_m_f16): Likewise. + (vcmulq_rot90_m_f32): Likewise. + (vcmulq_rot90_m_f16): Likewise. + (vcvtq_m_n_s32_f32): Likewise. + (vcvtq_m_n_s16_f16): Likewise. + (vcvtq_m_n_u32_f32): Likewise. + (vcvtq_m_n_u16_f16): Likewise. + (veorq_m_f32): Likewise. + (veorq_m_f16): Likewise. + (vfmaq_m_f32): Likewise. + (vfmaq_m_f16): Likewise. + (vfmaq_m_n_f32): Likewise. + (vfmaq_m_n_f16): Likewise. + (vfmasq_m_n_f32): Likewise. + (vfmasq_m_n_f16): Likewise. + (vfmsq_m_f32): Likewise. + (vfmsq_m_f16): Likewise. + (vmaxnmq_m_f32): Likewise. + (vmaxnmq_m_f16): Likewise. + (vminnmq_m_f32): Likewise. + (vminnmq_m_f16): Likewise. + (vmulq_m_f32): Likewise. + (vmulq_m_f16): Likewise. + (vmulq_m_n_f32): Likewise. + (vmulq_m_n_f16): Likewise. + (vornq_m_f32): Likewise. + (vornq_m_f16): Likewise. + (vorrq_m_f32): Likewise. + (vorrq_m_f16): Likewise. + (vsubq_m_f32): Likewise. + (vsubq_m_f16): Likewise. + (vsubq_m_n_f32): Likewise. + (vsubq_m_n_f16): Likewise. + (__attribute__): Likewise. + (__arm_vabdq_m_f32): Likewise. + (__arm_vabdq_m_f16): Likewise. + (__arm_vaddq_m_f32): Likewise. + (__arm_vaddq_m_f16): Likewise. + (__arm_vaddq_m_n_f32): Likewise. + (__arm_vaddq_m_n_f16): Likewise. + (__arm_vandq_m_f32): Likewise. + (__arm_vandq_m_f16): Likewise. + (__arm_vbicq_m_f32): Likewise. + (__arm_vbicq_m_f16): Likewise. + (__arm_vbrsrq_m_n_f32): Likewise. + (__arm_vbrsrq_m_n_f16): Likewise. + (__arm_vcaddq_rot270_m_f32): Likewise. + (__arm_vcaddq_rot270_m_f16): Likewise. + (__arm_vcaddq_rot90_m_f32): Likewise. + (__arm_vcaddq_rot90_m_f16): Likewise. + (__arm_vcmlaq_m_f32): Likewise. + (__arm_vcmlaq_m_f16): Likewise. + (__arm_vcmlaq_rot180_m_f32): Likewise. + (__arm_vcmlaq_rot180_m_f16): Likewise. + (__arm_vcmlaq_rot270_m_f32): Likewise. + (__arm_vcmlaq_rot270_m_f16): Likewise. + (__arm_vcmlaq_rot90_m_f32): Likewise. + (__arm_vcmlaq_rot90_m_f16): Likewise. + (__arm_vcmulq_m_f32): Likewise. + (__arm_vcmulq_m_f16): Likewise. + (__arm_vcmulq_rot180_m_f32): Define intrinsic. + (__arm_vcmulq_rot180_m_f16): Likewise. + (__arm_vcmulq_rot270_m_f32): Likewise. + (__arm_vcmulq_rot270_m_f16): Likewise. + (__arm_vcmulq_rot90_m_f32): Likewise. + (__arm_vcmulq_rot90_m_f16): Likewise. + (__arm_vcvtq_m_n_s32_f32): Likewise. + (__arm_vcvtq_m_n_s16_f16): Likewise. + (__arm_vcvtq_m_n_u32_f32): Likewise. + (__arm_vcvtq_m_n_u16_f16): Likewise. + (__arm_veorq_m_f32): Likewise. + (__arm_veorq_m_f16): Likewise. + (__arm_vfmaq_m_f32): Likewise. + (__arm_vfmaq_m_f16): Likewise. + (__arm_vfmaq_m_n_f32): Likewise. + (__arm_vfmaq_m_n_f16): Likewise. + (__arm_vfmasq_m_n_f32): Likewise. + (__arm_vfmasq_m_n_f16): Likewise. + (__arm_vfmsq_m_f32): Likewise. + (__arm_vfmsq_m_f16): Likewise. + (__arm_vmaxnmq_m_f32): Likewise. + (__arm_vmaxnmq_m_f16): Likewise. + (__arm_vminnmq_m_f32): Likewise. + (__arm_vminnmq_m_f16): Likewise. + (__arm_vmulq_m_f32): Likewise. + (__arm_vmulq_m_f16): Likewise. + (__arm_vmulq_m_n_f32): Likewise. + (__arm_vmulq_m_n_f16): Likewise. + (__arm_vornq_m_f32): Likewise. + (__arm_vornq_m_f16): Likewise. + (__arm_vorrq_m_f32): Likewise. + (__arm_vorrq_m_f16): Likewise. + (__arm_vsubq_m_f32): Likewise. + (__arm_vsubq_m_f16): Likewise. + (__arm_vsubq_m_n_f32): Likewise. + (__arm_vsubq_m_n_f16): Likewise. + (vabdq_m): Define polymorphic variant. + (vaddq_m): Likewise. + (vaddq_m_n): Likewise. + (vandq_m): Likewise. + (vbicq_m): Likewise. + (vbrsrq_m_n): Likewise. + (vcaddq_rot270_m): Likewise. + (vcaddq_rot90_m): Likewise. + (vcmlaq_m): Likewise. + (vcmlaq_rot180_m): Likewise. + (vcmlaq_rot270_m): Likewise. + (vcmlaq_rot90_m): Likewise. + (vcmulq_m): Likewise. + (vcmulq_rot180_m): Likewise. + (vcmulq_rot270_m): Likewise. + (vcmulq_rot90_m): Likewise. + (veorq_m): Likewise. + (vfmaq_m): Likewise. + (vfmaq_m_n): Likewise. + (vfmasq_m_n): Likewise. + (vfmsq_m): Likewise. + (vmaxnmq_m): Likewise. + (vminnmq_m): Likewise. + (vmulq_m): Likewise. + (vmulq_m_n): Likewise. + (vornq_m): Likewise. + (vsubq_m): Likewise. + (vsubq_m_n): Likewise. + (vorrq_m): Likewise. + * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use + builtin qualifier. + (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. + (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. + * config/arm/mve.md (mve_vabdq_m_f): Define RTL pattern. + (mve_vaddq_m_f): Likewise. + (mve_vaddq_m_n_f): Likewise. + (mve_vandq_m_f): Likewise. + (mve_vbicq_m_f): Likewise. + (mve_vbrsrq_m_n_f): Likewise. + (mve_vcaddq_rot270_m_f): Likewise. + (mve_vcaddq_rot90_m_f): Likewise. + (mve_vcmlaq_m_f): Likewise. + (mve_vcmlaq_rot180_m_f): Likewise. + (mve_vcmlaq_rot270_m_f): Likewise. + (mve_vcmlaq_rot90_m_f): Likewise. + (mve_vcmulq_m_f): Likewise. + (mve_vcmulq_rot180_m_f): Likewise. + (mve_vcmulq_rot270_m_f): Likewise. + (mve_vcmulq_rot90_m_f): Likewise. + (mve_veorq_m_f): Likewise. + (mve_vfmaq_m_f): Likewise. + (mve_vfmaq_m_n_f): Likewise. + (mve_vfmasq_m_n_f): Likewise. + (mve_vfmsq_m_f): Likewise. + (mve_vmaxnmq_m_f): Likewise. + (mve_vminnmq_m_f): Likewise. + (mve_vmulq_m_f): Likewise. + (mve_vmulq_m_n_f): Likewise. + (mve_vornq_m_f): Likewise. + (mve_vorrq_m_f): Likewise. + (mve_vsubq_m_f): Likewise. + (mve_vsubq_m_n_f): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-protos.h (arm_mve_immediate_check): * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check mode and interger value. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 0662812..4f8135d 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1640,6 +1640,68 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vshrntq_m_n_s16(__a, __b, __imm, __p) __arm_vshrntq_m_n_s16(__a, __b, __imm, __p) #define vshrntq_m_n_u32(__a, __b, __imm, __p) __arm_vshrntq_m_n_u32(__a, __b, __imm, __p) #define vshrntq_m_n_u16(__a, __b, __imm, __p) __arm_vshrntq_m_n_u16(__a, __b, __imm, __p) +#define vabdq_m_f32(__inactive, __a, __b, __p) __arm_vabdq_m_f32(__inactive, __a, __b, __p) +#define vabdq_m_f16(__inactive, __a, __b, __p) __arm_vabdq_m_f16(__inactive, __a, __b, __p) +#define vaddq_m_f32(__inactive, __a, __b, __p) __arm_vaddq_m_f32(__inactive, __a, __b, __p) +#define vaddq_m_f16(__inactive, __a, __b, __p) __arm_vaddq_m_f16(__inactive, __a, __b, __p) +#define vaddq_m_n_f32(__inactive, __a, __b, __p) __arm_vaddq_m_n_f32(__inactive, __a, __b, __p) +#define vaddq_m_n_f16(__inactive, __a, __b, __p) __arm_vaddq_m_n_f16(__inactive, __a, __b, __p) +#define vandq_m_f32(__inactive, __a, __b, __p) __arm_vandq_m_f32(__inactive, __a, __b, __p) +#define vandq_m_f16(__inactive, __a, __b, __p) __arm_vandq_m_f16(__inactive, __a, __b, __p) +#define vbicq_m_f32(__inactive, __a, __b, __p) __arm_vbicq_m_f32(__inactive, __a, __b, __p) +#define vbicq_m_f16(__inactive, __a, __b, __p) __arm_vbicq_m_f16(__inactive, __a, __b, __p) +#define vbrsrq_m_n_f32(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_f32(__inactive, __a, __b, __p) +#define vbrsrq_m_n_f16(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_f16(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_f32(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_f32(__inactive, __a, __b, __p) +#define vcaddq_rot270_m_f16(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_f16(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_f32(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_f32(__inactive, __a, __b, __p) +#define vcaddq_rot90_m_f16(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_f16(__inactive, __a, __b, __p) +#define vcmlaq_m_f32(__a, __b, __c, __p) __arm_vcmlaq_m_f32(__a, __b, __c, __p) +#define vcmlaq_m_f16(__a, __b, __c, __p) __arm_vcmlaq_m_f16(__a, __b, __c, __p) +#define vcmlaq_rot180_m_f32(__a, __b, __c, __p) __arm_vcmlaq_rot180_m_f32(__a, __b, __c, __p) +#define vcmlaq_rot180_m_f16(__a, __b, __c, __p) __arm_vcmlaq_rot180_m_f16(__a, __b, __c, __p) +#define vcmlaq_rot270_m_f32(__a, __b, __c, __p) __arm_vcmlaq_rot270_m_f32(__a, __b, __c, __p) +#define vcmlaq_rot270_m_f16(__a, __b, __c, __p) __arm_vcmlaq_rot270_m_f16(__a, __b, __c, __p) +#define vcmlaq_rot90_m_f32(__a, __b, __c, __p) __arm_vcmlaq_rot90_m_f32(__a, __b, __c, __p) +#define vcmlaq_rot90_m_f16(__a, __b, __c, __p) __arm_vcmlaq_rot90_m_f16(__a, __b, __c, __p) +#define vcmulq_m_f32(__inactive, __a, __b, __p) __arm_vcmulq_m_f32(__inactive, __a, __b, __p) +#define vcmulq_m_f16(__inactive, __a, __b, __p) __arm_vcmulq_m_f16(__inactive, __a, __b, __p) +#define vcmulq_rot180_m_f32(__inactive, __a, __b, __p) __arm_vcmulq_rot180_m_f32(__inactive, __a, __b, __p) +#define vcmulq_rot180_m_f16(__inactive, __a, __b, __p) __arm_vcmulq_rot180_m_f16(__inactive, __a, __b, __p) +#define vcmulq_rot270_m_f32(__inactive, __a, __b, __p) __arm_vcmulq_rot270_m_f32(__inactive, __a, __b, __p) +#define vcmulq_rot270_m_f16(__inactive, __a, __b, __p) __arm_vcmulq_rot270_m_f16(__inactive, __a, __b, __p) +#define vcmulq_rot90_m_f32(__inactive, __a, __b, __p) __arm_vcmulq_rot90_m_f32(__inactive, __a, __b, __p) +#define vcmulq_rot90_m_f16(__inactive, __a, __b, __p) __arm_vcmulq_rot90_m_f16(__inactive, __a, __b, __p) +#define vcvtq_m_n_s32_f32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_s32_f32(__inactive, __a, __imm6, __p) +#define vcvtq_m_n_s16_f16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_s16_f16(__inactive, __a, __imm6, __p) +#define vcvtq_m_n_u32_f32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_u32_f32(__inactive, __a, __imm6, __p) +#define vcvtq_m_n_u16_f16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_u16_f16(__inactive, __a, __imm6, __p) +#define veorq_m_f32(__inactive, __a, __b, __p) __arm_veorq_m_f32(__inactive, __a, __b, __p) +#define veorq_m_f16(__inactive, __a, __b, __p) __arm_veorq_m_f16(__inactive, __a, __b, __p) +#define vfmaq_m_f32(__a, __b, __c, __p) __arm_vfmaq_m_f32(__a, __b, __c, __p) +#define vfmaq_m_f16(__a, __b, __c, __p) __arm_vfmaq_m_f16(__a, __b, __c, __p) +#define vfmaq_m_n_f32(__a, __b, __c, __p) __arm_vfmaq_m_n_f32(__a, __b, __c, __p) +#define vfmaq_m_n_f16(__a, __b, __c, __p) __arm_vfmaq_m_n_f16(__a, __b, __c, __p) +#define vfmasq_m_n_f32(__a, __b, __c, __p) __arm_vfmasq_m_n_f32(__a, __b, __c, __p) +#define vfmasq_m_n_f16(__a, __b, __c, __p) __arm_vfmasq_m_n_f16(__a, __b, __c, __p) +#define vfmsq_m_f32(__a, __b, __c, __p) __arm_vfmsq_m_f32(__a, __b, __c, __p) +#define vfmsq_m_f16(__a, __b, __c, __p) __arm_vfmsq_m_f16(__a, __b, __c, __p) +#define vmaxnmq_m_f32(__inactive, __a, __b, __p) __arm_vmaxnmq_m_f32(__inactive, __a, __b, __p) +#define vmaxnmq_m_f16(__inactive, __a, __b, __p) __arm_vmaxnmq_m_f16(__inactive, __a, __b, __p) +#define vminnmq_m_f32(__inactive, __a, __b, __p) __arm_vminnmq_m_f32(__inactive, __a, __b, __p) +#define vminnmq_m_f16(__inactive, __a, __b, __p) __arm_vminnmq_m_f16(__inactive, __a, __b, __p) +#define vmulq_m_f32(__inactive, __a, __b, __p) __arm_vmulq_m_f32(__inactive, __a, __b, __p) +#define vmulq_m_f16(__inactive, __a, __b, __p) __arm_vmulq_m_f16(__inactive, __a, __b, __p) +#define vmulq_m_n_f32(__inactive, __a, __b, __p) __arm_vmulq_m_n_f32(__inactive, __a, __b, __p) +#define vmulq_m_n_f16(__inactive, __a, __b, __p) __arm_vmulq_m_n_f16(__inactive, __a, __b, __p) +#define vornq_m_f32(__inactive, __a, __b, __p) __arm_vornq_m_f32(__inactive, __a, __b, __p) +#define vornq_m_f16(__inactive, __a, __b, __p) __arm_vornq_m_f16(__inactive, __a, __b, __p) +#define vorrq_m_f32(__inactive, __a, __b, __p) __arm_vorrq_m_f32(__inactive, __a, __b, __p) +#define vorrq_m_f16(__inactive, __a, __b, __p) __arm_vorrq_m_f16(__inactive, __a, __b, __p) +#define vsubq_m_f32(__inactive, __a, __b, __p) __arm_vsubq_m_f32(__inactive, __a, __b, __p) +#define vsubq_m_f16(__inactive, __a, __b, __p) __arm_vsubq_m_f16(__inactive, __a, __b, __p) +#define vsubq_m_n_f32(__inactive, __a, __b, __p) __arm_vsubq_m_n_f32(__inactive, __a, __b, __p) +#define vsubq_m_n_f16(__inactive, __a, __b, __p) __arm_vsubq_m_n_f16(__inactive, __a, __b, __p) #endif __extension__ extern __inline void @@ -12641,6 +12703,439 @@ __arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6 return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p); } +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot180_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot180_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot270_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot270_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot90_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot90_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot180_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot180_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot270_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot270_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot90_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot90_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_s32_f32 (int32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_sv4si (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_s16_f16 (int16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_sv8hi (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_u32_f32 (uint32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_uv4si (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_u16_f16 (uint16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_uv8hi (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_n_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_n_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmasq_m_n_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmasq_m_n_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmsq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); +} #endif enum { @@ -14277,6 +14772,10 @@ extern void *__ARM_undef; #define __arm_vcvtq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_n_s16_f16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_n_s32_f32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_n_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_n_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2, p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_n_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_n_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_n_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ @@ -14682,130 +15181,427 @@ extern void *__ARM_undef; #define vrshrnbq(p0,p1,p2) __arm_vrshrnbq(p0,p1,p2) #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrev16q_m(p0,p1,p2) __arm_vrev16q_m(p0,p1,p2) +#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) + +#define vqshruntq(p0,p1,p2) __arm_vqshruntq(p0,p1,p2) +#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqshrunbq_n(p0,p1,p2) __arm_vqshrunbq_n(p0,p1,p2) +#define __arm_vqshrunbq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqshrnbq(p0,p1,p2) __arm_vqshrnbq(p0,p1,p2) +#define __arm_vqshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqshrntq(p0,p1,p2) __arm_vqshrntq(p0,p1,p2) +#define __arm_vqshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) +#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqmovnbq_m(p0,p1,p2) __arm_vqmovnbq_m(p0,p1,p2) +#define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqmovntq_m(p0,p1,p2) __arm_vqmovntq_m(p0,p1,p2) +#define __arm_vqmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqmovunbq_m(p0,p1,p2) __arm_vqmovunbq_m(p0,p1,p2) +#define __arm_vqmovunbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqmovuntq_m(p0,p1,p2) __arm_vqmovuntq_m(p0,p1,p2) +#define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vqrshrntq(p0,p1,p2) __arm_vqrshrntq(p0,p1,p2) +#define __arm_vqrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) +#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vnegq_m(p0,p1,p2) __arm_vnegq_m(p0,p1,p2) +#define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vnegq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vnegq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vcmpgeq_m(p0,p1,p2) __arm_vcmpgeq_m(p0,p1,p2) +#define __arm_vcmpgeq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vabdq_m(p0,p1,p2,p3) __arm_vabdq_m(p0,p1,p2,p3) +#define __arm_vabdq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vaddq_m(p0,p1,p2,p3) __arm_vaddq_m(p0,p1,p2,p3) +#define __arm_vaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) + +#define vandq_m(p0,p1,p2,p3) __arm_vandq_m(p0,p1,p2,p3) +#define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vbicq_m(p0,p1,p2,p3) __arm_vbicq_m(p0,p1,p2,p3) +#define __arm_vbicq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vbrsrq_m(p0,p1,p2,p3) __arm_vbrsrq_m(p0,p1,p2,p3) +#define __arm_vbrsrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbrsrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbrsrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbrsrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbrsrq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbrsrq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2, p3));}) + +#define vcaddq_rot270_m(p0,p1,p2,p3) __arm_vcaddq_rot270_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcaddq_rot90_m(p0,p1,p2,p3) __arm_vcaddq_rot90_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmlaq_m(p0,p1,p2,p3) __arm_vcmlaq_m(p0,p1,p2,p3) +#define __arm_vcmlaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmlaq_rot180_m(p0,p1,p2,p3) __arm_vcmlaq_rot180_m(p0,p1,p2,p3) +#define __arm_vcmlaq_rot180_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot180_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot180_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmlaq_rot270_m(p0,p1,p2,p3) __arm_vcmlaq_rot270_m(p0,p1,p2,p3) +#define __arm_vcmlaq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot270_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot270_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmlaq_rot90_m(p0,p1,p2,p3) __arm_vcmlaq_rot90_m(p0,p1,p2,p3) +#define __arm_vcmlaq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot90_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot90_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vrev16q_m(p0,p1,p2) __arm_vrev16q_m(p0,p1,p2) -#define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmulq_m(p0,p1,p2,p3) __arm_vcmulq_m(p0,p1,p2,p3) +#define __arm_vcmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqshruntq(p0,p1,p2) __arm_vqshruntq(p0,p1,p2) -#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmulq_rot180_m(p0,p1,p2,p3) __arm_vcmulq_rot180_m(p0,p1,p2,p3) +#define __arm_vcmulq_rot180_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqshrunbq_n(p0,p1,p2) __arm_vqshrunbq_n(p0,p1,p2) -#define __arm_vqshrunbq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmulq_rot270_m(p0,p1,p2,p3) __arm_vcmulq_rot270_m(p0,p1,p2,p3) +#define __arm_vcmulq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqshrnbq(p0,p1,p2) __arm_vqshrnbq(p0,p1,p2) -#define __arm_vqshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vcmulq_rot90_m(p0,p1,p2,p3) __arm_vcmulq_rot90_m(p0,p1,p2,p3) +#define __arm_vcmulq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)] [__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_m_f16(__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_m_f32(__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqshrntq(p0,p1,p2) __arm_vqshrntq(p0,p1,p2) -#define __arm_vqshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define veorq_m(p0,p1,p2,p3) __arm_veorq_m(p0,p1,p2,p3) +#define __arm_veorq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vfmaq_m(p0,p1,p2,p3) __arm_vfmaq_m(p0,p1,p2,p3) +#define __arm_vfmaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) -#define vqmovnbq_m(p0,p1,p2) __arm_vqmovnbq_m(p0,p1,p2) -#define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vfmasq_m(p0,p1,p2,p3) __arm_vfmasq_m(p0,p1,p2,p3) +#define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovnbq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovnbq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovnbq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovnbq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) -#define vqmovntq_m(p0,p1,p2) __arm_vqmovntq_m(p0,p1,p2) -#define __arm_vqmovntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vfmsq_m(p0,p1,p2,p3) __arm_vfmsq_m(p0,p1,p2,p3) +#define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovntq_m_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovntq_m_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqmovntq_m_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqmovntq_m_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmsq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmsq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqmovunbq_m(p0,p1,p2) __arm_vqmovunbq_m(p0,p1,p2) -#define __arm_vqmovunbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxnmq_m(p0,p1,p2,p3) __arm_vmaxnmq_m(p0,p1,p2,p3) +#define __arm_vmaxnmq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovunbq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovunbq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqmovuntq_m(p0,p1,p2) __arm_vqmovuntq_m(p0,p1,p2) -#define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vminnmq_m(p0,p1,p2,p3) __arm_vminnmq_m(p0,p1,p2,p3) +#define __arm_vminnmq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vqrshrntq(p0,p1,p2) __arm_vqrshrntq(p0,p1,p2) -#define __arm_vqrshrntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vmulq_m(p0,p1,p2,p3) __arm_vmulq_m(p0,p1,p2,p3) +#define __arm_vmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) -#define vqrshruntq(p0,p1,p2) __arm_vqrshruntq(p0,p1,p2) -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vornq_m(p0,p1,p2,p3) __arm_vornq_m(p0,p1,p2,p3) +#define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) -#define vnegq_m(p0,p1,p2) __arm_vnegq_m(p0,p1,p2) -#define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vsubq_m(p0,p1,p2,p3) __arm_vsubq_m(p0,p1,p2,p3) +#define __arm_vsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vnegq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vnegq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vnegq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vnegq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vnegq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) -#define vcmpgeq_m(p0,p1,p2) __arm_vcmpgeq_m(p0,p1,p2) -#define __arm_vcmpgeq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vorrq_m(p0,p1,p2,p3) __arm_vorrq_m(p0,p1,p2,p3) +#define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) #else /* MVE Integer. */ @@ -16714,149 +17510,65 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vbrsrq_m(p0,p1,p2,p3) __arm_vbrsrq_m(p0,p1,p2,p3) -#define __arm_vbrsrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbrsrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbrsrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbrsrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __p2, p3));}) - -#define vcaddq_rot270_m(p0,p1,p2,p3) __arm_vcaddq_rot270_m(p0,p1,p2,p3) -#define __arm_vcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vcaddq_rot90_m(p0,p1,p2,p3) __arm_vcaddq_rot90_m(p0,p1,p2,p3) -#define __arm_vcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define veorq_m(p0,p1,p2,p3) __arm_veorq_m(p0,p1,p2,p3) -#define __arm_veorq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vmaxq_m(p0,p1,p2,p3) __arm_vmaxq_m(p0,p1,p2,p3) -#define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vminq_m(p0,p1,p2,p3) __arm_vminq_m(p0,p1,p2,p3) -#define __arm_vminq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vmladavaq_p(p0,p1,p2,p3) __arm_vmladavaq_p(p0,p1,p2,p3) -#define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vmlaq_m(p0,p1,p2,p3) __arm_vmlaq_m(p0,p1,p2,p3) -#define __arm_vmlaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vbrsrq_m(p0,p1,p2,p3) __arm_vbrsrq_m(p0,p1,p2,p3) +#define __arm_vbrsrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbrsrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbrsrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbrsrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __p2, p3));}) -#define vmlasq_m(p0,p1,p2,p3) __arm_vmlasq_m(p0,p1,p2,p3) -#define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vcaddq_rot270_m(p0,p1,p2,p3) __arm_vcaddq_rot270_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmulhq_m(p0,p1,p2,p3) __arm_vmulhq_m(p0,p1,p2,p3) -#define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vcaddq_rot90_m(p0,p1,p2,p3) __arm_vcaddq_rot90_m(p0,p1,p2,p3) +#define __arm_vcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmullbq_int_m(p0,p1,p2,p3) __arm_vmullbq_int_m(p0,p1,p2,p3) -#define __arm_vmullbq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define veorq_m(p0,p1,p2,p3) __arm_veorq_m(p0,p1,p2,p3) +#define __arm_veorq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmulltq_int_m(p0,p1,p2,p3) __arm_vmulltq_int_m(p0,p1,p2,p3) -#define __arm_vmulltq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmladavaq_p(p0,p1,p2,p3) __arm_vmladavaq_p(p0,p1,p2,p3) +#define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define vornq_m(p0,p1,p2,p3) __arm_vornq_m(p0,p1,p2,p3) #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ @@ -16882,14 +17594,43 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vqdmlahq_m(p0,p1,p2,p3) __arm_vqdmlahq_m(p0,p1,p2,p3) -#define __arm_vqdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vaddq_m(p0,p1,p2,p3) __arm_vaddq_m(p0,p1,p2,p3) +#define __arm_vaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmulq_m(p0,p1,p2,p3) __arm_vmulq_m(p0,p1,p2,p3) +#define __arm_vmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#endif /* MVE Integer. */ #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ @@ -16968,170 +17709,50 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vrshlq_m(p0,p1,p2,p3) __arm_vrshlq_m(p0,p1,p2,p3) -#define __arm_vrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) - -#define vrshrq_m(p0,p1,p2,p3) __arm_vrshrq_m(p0,p1,p2,p3) -#define __arm_vrshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - -#define vshrq_m(p0,p1,p2,p3) __arm_vshrq_m(p0,p1,p2,p3) -#define __arm_vshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - -#define vsliq_m(p0,p1,p2,p3) __arm_vsliq_m(p0,p1,p2,p3) -#define __arm_vsliq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - -#define vaddq_m(p0,p1,p2,p3) __arm_vaddq_m(p0,p1,p2,p3) -#define __arm_vaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vhaddq_m(p0,p1,p2,p3) __arm_vhaddq_m(p0,p1,p2,p3) -#define __arm_vhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vhcaddq_rot270_m(p0,p1,p2,p3) __arm_vhcaddq_rot270_m(p0,p1,p2,p3) -#define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) - -#define vhcaddq_rot90_m(p0,p1,p2,p3) __arm_vhcaddq_rot90_m(p0,p1,p2,p3) -#define __arm_vhcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) - -#define vhsubq_m(p0,p1,p2,p3) __arm_vhsubq_m(p0,p1,p2,p3) -#define __arm_vhsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) - -#define vmulq_m(p0,p1,p2,p3) __arm_vmulq_m(p0,p1,p2,p3) -#define __arm_vmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vqaddq_m(p0,p1,p2,p3) __arm_vqaddq_m(p0,p1,p2,p3) -#define __arm_vqaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vrshlq_m(p0,p1,p2,p3) __arm_vrshlq_m(p0,p1,p2,p3) +#define __arm_vrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqdmulhq_m(p0,p1,p2,p3) __arm_vqdmulhq_m(p0,p1,p2,p3) -#define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vrshrq_m(p0,p1,p2,p3) __arm_vrshrq_m(p0,p1,p2,p3) +#define __arm_vrshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshrq_m(p0,p1,p2,p3) __arm_vshrq_m(p0,p1,p2,p3) +#define __arm_vshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vsliq_m(p0,p1,p2,p3) __arm_vsliq_m(p0,p1,p2,p3) +#define __arm_vsliq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) #define vqsubq_m(p0,p1,p2,p3) __arm_vqsubq_m(p0,p1,p2,p3) #define __arm_vqsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ @@ -17181,385 +17802,560 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqrdmladhq_m(p0,p1,p2,p3) __arm_vqrdmladhq_m(p0,p1,p2,p3) -#define __arm_vqrdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vshllbq_m(p0,p1,p2,p3) __arm_vshllbq_m(p0,p1,p2,p3) +#define __arm_vshllbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshllbq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshllbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshllbq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshllbq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vshrntq_m(p0,p1,p2,p3) __arm_vshrntq_m(p0,p1,p2,p3) +#define __arm_vshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshrnbq_m(p0,p1,p2,p3) __arm_vshrnbq_m(p0,p1,p2,p3) +#define __arm_vshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshlltq_m(p0,p1,p2,p3) __arm_vshlltq_m(p0,p1,p2,p3) +#define __arm_vshlltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshlltq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshlltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshlltq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshlltq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vrshrntq_m(p0,p1,p2,p3) __arm_vrshrntq_m(p0,p1,p2,p3) +#define __arm_vrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqshruntq_m(p0,p1,p2,p3) __arm_vqshruntq_m(p0,p1,p2,p3) +#define __arm_vqshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqshrunbq_m(p0,p1,p2,p3) __arm_vqshrunbq_m(p0,p1,p2,p3) +#define __arm_vqshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqrshrnbq_m(p0,p1,p2,p3) __arm_vqrshrnbq_m(p0,p1,p2,p3) +#define __arm_vqrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqrshrntq_m(p0,p1,p2,p3) __arm_vqrshrntq_m(p0,p1,p2,p3) +#define __arm_vqrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqrshrunbq_m(p0,p1,p2,p3) __arm_vqrshrunbq_m(p0,p1,p2,p3) +#define __arm_vqrshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqrshruntq_m(p0,p1,p2,p3) __arm_vqrshruntq_m(p0,p1,p2,p3) +#define __arm_vqrshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vqshrnbq_m(p0,p1,p2,p3) __arm_vqshrnbq_m(p0,p1,p2,p3) +#define __arm_vqshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vqshrntq_m(p0,p1,p2,p3) __arm_vqshrntq_m(p0,p1,p2,p3) +#define __arm_vqshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vrshrnbq_m(p0,p1,p2,p3) __arm_vrshrnbq_m(p0,p1,p2,p3) +#define __arm_vrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vmlaldavaq_p(p0,p1,p2,p3) __arm_vmlaldavaq_p(p0,p1,p2,p3) +#define __arm_vmlaldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vqrdmladhxq_m(p0,p1,p2,p3) __arm_vqrdmladhxq_m(p0,p1,p2,p3) -#define __arm_vqrdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlaldavaxq_p(p0,p1,p2,p3) __arm_vmlaldavaxq_p(p0,p1,p2,p3) +#define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaxq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaxq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmlsdavaxq_p(p0,p1,p2,p3) __arm_vmlsdavaxq_p(p0,p1,p2,p3) -#define __arm_vmlsdavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlsldavaq_p(p0,p1,p2,p3) __arm_vmlsldavaq_p(p0,p1,p2,p3) +#define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaxq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaxq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaxq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vmlsdavaq_p(p0,p1,p2,p3) __arm_vmlsdavaq_p(p0,p1,p2,p3) -#define __arm_vmlsdavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlsldavaxq_p(p0,p1,p2,p3) __arm_vmlsldavaxq_p(p0,p1,p2,p3) +#define __arm_vmlsldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaxq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaxq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vmladavaxq_p(p0,p1,p2,p3) __arm_vmladavaxq_p(p0,p1,p2,p3) -#define __arm_vmladavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vrmlaldavhaq_p(p0,p1,p2,p3) __arm_vrmlaldavhaq_p(p0,p1,p2,p3) +#define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) +#define __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p_s32(p0,p1,p2,p3) + +#define vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p(p0,p1,p2,p3) +#define __arm_vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p_s32(p0,p1,p2,p3) + +#define vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) +#define __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p_s32(p0,p1,p2,p3) + +#define vqdmladhq_m(p0,p1,p2,p3) __arm_vqdmladhq_m(p0,p1,p2,p3) +#define __arm_vqdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vqdmladhxq_m(p0,p1,p2,p3) __arm_vqdmladhxq_m(p0,p1,p2,p3) +#define __arm_vqdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vmullbq_poly_m(p0,p1,p2,p3) __arm_vmullbq_poly_m(p0,p1,p2,p3) -#define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmlsdhq_m(p0,p1,p2,p3) __arm_vqdmlsdhq_m(p0,p1,p2,p3) +#define __arm_vqdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vmulltq_poly_m(p0,p1,p2,p3) __arm_vmulltq_poly_m(p0,p1,p2,p3) -#define __arm_vmulltq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmlsdhxq_m(p0,p1,p2,p3) __arm_vqdmlsdhxq_m(p0,p1,p2,p3) +#define __arm_vqdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vshllbq_m(p0,p1,p2,p3) __arm_vshllbq_m(p0,p1,p2,p3) -#define __arm_vshllbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) +#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshllbq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshllbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshllbq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshllbq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vshrntq_m(p0,p1,p2,p3) __arm_vshrntq_m(p0,p1,p2,p3) -#define __arm_vshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) +#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) -#define vshrnbq_m(p0,p1,p2,p3) __arm_vshrnbq_m(p0,p1,p2,p3) -#define __arm_vshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vorrq_m_n(p0,p1,p2) __arm_vorrq_m_n(p0,p1,p2) +#define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vorrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vorrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vqshrunbq(p0,p1,p2) __arm_vqshrunbq(p0,p1,p2) +#define __arm_vqshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define vshlltq_m(p0,p1,p2,p3) __arm_vshlltq_m(p0,p1,p2,p3) -#define __arm_vshlltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqshluq_m(p0,p1,p2,p3) __arm_vqshluq_m(p0,p1,p2,p3) +#define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t]: __arm_vshlltq_m_n_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t]: __arm_vshlltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshlltq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshlltq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshluq_m_n_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshluq_m_n_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshluq_m_n_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) -#define vrshrntq_m(p0,p1,p2,p3) __arm_vrshrntq_m(p0,p1,p2,p3) -#define __arm_vrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_m(p0,p1,p2,p3) __arm_vshlq_m(p0,p1,p2,p3) +#define __arm_vshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqshruntq_m(p0,p1,p2,p3) __arm_vqshruntq_m(p0,p1,p2,p3) -#define __arm_vqshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_m_n(p0,p1,p2,p3) __arm_vshlq_m_n(p0,p1,p2,p3) +#define __arm_vshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) -#define vqshrunbq_m(p0,p1,p2,p3) __arm_vqshrunbq_m(p0,p1,p2,p3) -#define __arm_vqshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) +#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + +#define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3) +#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) -#define vqdmullbq_m(p0,p1,p2,p3) __arm_vqdmullbq_m(p0,p1,p2,p3) -#define __arm_vqdmullbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vhaddq_m(p0,p1,p2,p3) __arm_vhaddq_m(p0,p1,p2,p3) +#define __arm_vhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vqdmulltq_m(p0,p1,p2,p3) __arm_vqdmulltq_m(p0,p1,p2,p3) -#define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vhcaddq_rot270_m(p0,p1,p2,p3) __arm_vhcaddq_rot270_m(p0,p1,p2,p3) +#define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) - -#define vqrshrnbq_m(p0,p1,p2,p3) __arm_vqrshrnbq_m(p0,p1,p2,p3) -#define __arm_vqrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - -#define vqrshrntq_m(p0,p1,p2,p3) __arm_vqrshrntq_m(p0,p1,p2,p3) -#define __arm_vqrshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqrshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqrshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqrshrunbq_m(p0,p1,p2,p3) __arm_vqrshrunbq_m(p0,p1,p2,p3) -#define __arm_vqrshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vhcaddq_rot90_m(p0,p1,p2,p3) __arm_vhcaddq_rot90_m(p0,p1,p2,p3) +#define __arm_vhcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqrshruntq_m(p0,p1,p2,p3) __arm_vqrshruntq_m(p0,p1,p2,p3) -#define __arm_vqrshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vhsubq_m(p0,p1,p2,p3) __arm_vhsubq_m(p0,p1,p2,p3) +#define __arm_vhsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) -#define vqshrnbq_m(p0,p1,p2,p3) __arm_vqshrnbq_m(p0,p1,p2,p3) -#define __arm_vqshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmaxq_m(p0,p1,p2,p3) __arm_vmaxq_m(p0,p1,p2,p3) +#define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vqshrntq_m(p0,p1,p2,p3) __arm_vqshrntq_m(p0,p1,p2,p3) -#define __arm_vqshrntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vminq_m(p0,p1,p2,p3) __arm_vminq_m(p0,p1,p2,p3) +#define __arm_vminq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrntq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrntq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vqshrntq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vqshrntq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vrshrnbq_m(p0,p1,p2,p3) __arm_vrshrnbq_m(p0,p1,p2,p3) -#define __arm_vrshrnbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlaq_m(p0,p1,p2,p3) __arm_vmlaq_m(p0,p1,p2,p3) +#define __arm_vmlaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int16x8_t]: __arm_vrshrnbq_m_n_s16 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32x4_t]: __arm_vrshrnbq_m_n_s32 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrnbq_m_n_u16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrnbq_m_n_u32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) -#define vmlaldavaq_p(p0,p1,p2,p3) __arm_vmlaldavaq_p(p0,p1,p2,p3) -#define __arm_vmlaldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlasq_m(p0,p1,p2,p3) __arm_vmlasq_m(p0,p1,p2,p3) +#define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) -#define vmlaldavaxq_p(p0,p1,p2,p3) __arm_vmlaldavaxq_p(p0,p1,p2,p3) -#define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmulhq_m(p0,p1,p2,p3) __arm_vmulhq_m(p0,p1,p2,p3) +#define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaxq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaxq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmlsldavaq_p(p0,p1,p2,p3) __arm_vmlsldavaq_p(p0,p1,p2,p3) -#define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmullbq_int_m(p0,p1,p2,p3) __arm_vmullbq_int_m(p0,p1,p2,p3) +#define __arm_vmullbq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vmlsldavaxq_p(p0,p1,p2,p3) __arm_vmlsldavaxq_p(p0,p1,p2,p3) -#define __arm_vmlsldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmulltq_int_m(p0,p1,p2,p3) __arm_vmulltq_int_m(p0,p1,p2,p3) +#define __arm_vmulltq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsldavaxq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsldavaxq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vrmlaldavhaq_p(p0,p1,p2,p3) __arm_vrmlaldavhaq_p(p0,p1,p2,p3) -#define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmulltq_poly_m(p0,p1,p2,p3) __arm_vmulltq_poly_m(p0,p1,p2,p3) +#define __arm_vmulltq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int64_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) - -#define vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) -#define __arm_vrmlaldavhaxq_p(p0,p1,p2,p3) __arm_vrmlaldavhaxq_p_s32(p0,p1,p2,p3) - -#define vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p(p0,p1,p2,p3) -#define __arm_vrmlsldavhaq_p(p0,p1,p2,p3) __arm_vrmlsldavhaq_p_s32(p0,p1,p2,p3) - -#define vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) -#define __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p_s32(p0,p1,p2,p3) - -#endif /* MVE Integer. */ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) -#define vqdmladhq_m(p0,p1,p2,p3) __arm_vqdmladhq_m(p0,p1,p2,p3) -#define __arm_vqdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqaddq_m(p0,p1,p2,p3) __arm_vqaddq_m(p0,p1,p2,p3) +#define __arm_vqaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) -#define vqdmladhxq_m(p0,p1,p2,p3) __arm_vqdmladhxq_m(p0,p1,p2,p3) -#define __arm_vqdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmlahq_m(p0,p1,p2,p3) __arm_vqdmlahq_m(p0,p1,p2,p3) +#define __arm_vqdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) -#define vqdmlsdhq_m(p0,p1,p2,p3) __arm_vqdmlsdhq_m(p0,p1,p2,p3) -#define __arm_vqdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmulhq_m(p0,p1,p2,p3) __arm_vqdmulhq_m(p0,p1,p2,p3) +#define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqdmlsdhxq_m(p0,p1,p2,p3) __arm_vqdmlsdhxq_m(p0,p1,p2,p3) -#define __arm_vqdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmullbq_m(p0,p1,p2,p3) __arm_vqdmullbq_m(p0,p1,p2,p3) +#define __arm_vqdmullbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) -#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2) -#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqdmulltq_m(p0,p1,p2,p3) __arm_vqdmulltq_m(p0,p1,p2,p3) +#define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqabsq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqabsq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqabsq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vmvnq_m(p0,p1,p2) __arm_vmvnq_m(p0,p1,p2) -#define __arm_vmvnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmladhq_m(p0,p1,p2,p3) __arm_vqrdmladhq_m(p0,p1,p2,p3) +#define __arm_vqrdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmvnq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmvnq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmvnq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32_t]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) - -#define vorrq_m_n(p0,p1,p2) __arm_vorrq_m_n(p0,p1,p2) -#define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vorrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vorrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqshrunbq(p0,p1,p2) __arm_vqshrunbq(p0,p1,p2) -#define __arm_vqshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vqrdmladhxq_m(p0,p1,p2,p3) __arm_vqrdmladhxq_m(p0,p1,p2,p3) +#define __arm_vqrdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vqshluq_m(p0,p1,p2,p3) __arm_vqshluq_m(p0,p1,p2,p3) -#define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlsdavaxq_p(p0,p1,p2,p3) __arm_vmlsdavaxq_p(p0,p1,p2,p3) +#define __arm_vmlsdavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshluq_m_n_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshluq_m_n_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshluq_m_n_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaxq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaxq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaxq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vshlq_m(p0,p1,p2,p3) __arm_vshlq_m(p0,p1,p2,p3) -#define __arm_vshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmlsdavaq_p(p0,p1,p2,p3) __arm_vmlsdavaq_p(p0,p1,p2,p3) +#define __arm_vmlsdavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vshlq_m_n(p0,p1,p2,p3) __arm_vshlq_m_n(p0,p1,p2,p3) -#define __arm_vshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmladavaxq_p(p0,p1,p2,p3) __arm_vmladavaxq_p(p0,p1,p2,p3) +#define __arm_vmladavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - -#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2) -#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) -#define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3) -#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ +#define vmullbq_poly_m(p0,p1,p2,p3) __arm_vmullbq_poly_m(p0,p1,p2,p3) +#define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) #ifdef __cplusplus } diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 6048591..b448889 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -654,3 +654,34 @@ VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_u, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminnmq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxnmq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmsq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmasq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot180_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot180_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3dd33d8..bf4eb5d 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -186,7 +186,12 @@ VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S - VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S]) + VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S + VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F + VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F + VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F + VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F + VMINNMQ_M_F VSUBQ_M_F]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -7443,3 +7448,495 @@ "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" [(set_attr "type" "mve_move") (set_attr "length""8")]) +;; +;; [vabdq_m_f]) +;; +(define_insn "mve_vabdq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VABDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vabdt.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddq_m_f]) +;; +(define_insn "mve_vaddq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vaddt.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vaddq_m_n_f]) +;; +(define_insn "mve_vaddq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADDQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vaddt.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vandq_m_f]) +;; +(define_insn "mve_vandq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VANDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vandt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vbicq_m_f]) +;; +(define_insn "mve_vbicq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VBICQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vbict %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vbrsrq_m_n_f]) +;; +(define_insn "mve_vbrsrq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:SI 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VBRSRQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vbrsrt.%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcaddq_rot270_m_f]) +;; +(define_insn "mve_vcaddq_rot270_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCADDQ_ROT270_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcaddt.f%# %q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcaddq_rot90_m_f]) +;; +(define_insn "mve_vcaddq_rot90_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCADDQ_ROT90_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcaddt.f%# %q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmlaq_m_f]) +;; +(define_insn "mve_vcmlaq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMLAQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmlat.f%# %q0, %q2, %q3, #0" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmlaq_rot180_m_f]) +;; +(define_insn "mve_vcmlaq_rot180_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMLAQ_ROT180_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmlat.f%# %q0, %q2, %q3, #180" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmlaq_rot270_m_f]) +;; +(define_insn "mve_vcmlaq_rot270_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMLAQ_ROT270_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmlat.f%# %q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmlaq_rot90_m_f]) +;; +(define_insn "mve_vcmlaq_rot90_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMLAQ_ROT90_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmlat.f%# %q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmulq_m_f]) +;; +(define_insn "mve_vcmulq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMULQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmult.f%# %q0, %q2, %q3, #0" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmulq_rot180_m_f]) +;; +(define_insn "mve_vcmulq_rot180_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMULQ_ROT180_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmult.f%# %q0, %q2, %q3, #180" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmulq_rot270_m_f]) +;; +(define_insn "mve_vcmulq_rot270_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMULQ_ROT270_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmult.f%# %q0, %q2, %q3, #270" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vcmulq_rot90_m_f]) +;; +(define_insn "mve_vcmulq_rot90_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCMULQ_ROT90_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcmult.f%# %q0, %q2, %q3, #90" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [veorq_m_f]) +;; +(define_insn "mve_veorq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VEORQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;veort %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vfmaq_m_f]) +;; +(define_insn "mve_vfmaq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VFMAQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vfmat.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vfmaq_m_n_f]) +;; +(define_insn "mve_vfmaq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VFMAQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vfmat.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vfmasq_m_n_f]) +;; +(define_insn "mve_vfmasq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VFMASQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vfmast.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vfmsq_m_f]) +;; +(define_insn "mve_vfmsq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VFMSQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vfmst.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmaxnmq_m_f]) +;; +(define_insn "mve_vmaxnmq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMAXNMQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmaxnmt.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vminnmq_m_f]) +;; +(define_insn "mve_vminnmq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMINNMQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vminnmt.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulq_m_f]) +;; +(define_insn "mve_vmulq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmult.f%# %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vmulq_m_n_f]) +;; +(define_insn "mve_vmulq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VMULQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vmult.f%# %q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vornq_m_f]) +;; +(define_insn "mve_vornq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VORNQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vornt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vorrq_m_f]) +;; +(define_insn "mve_vorrq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VORRQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vorrt %q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vsubq_m_f]) +;; +(define_insn "mve_vsubq_m_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand:MVE_0 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSUBQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vsubt.f%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vsubq_m_n_f]) +;; +(define_insn "mve_vsubq_m_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" "r") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSUBQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vsubt.f%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 650a6b9..4ed6dc7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,73 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c new file mode 100644 index 0000000..dac3dd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vabdq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c new file mode 100644 index 0000000..d1b59ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vabdq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vabdq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c new file mode 100644 index 0000000..b52b719 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vaddq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c new file mode 100644 index 0000000..c3e7c2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vaddq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c new file mode 100644 index 0000000..94d6b6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vaddq_m_n_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c new file mode 100644 index 0000000..ab100cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vaddq_m_n_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vaddq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c new file mode 100644 index 0000000..c641fce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vandq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c new file mode 100644 index 0000000..a3344d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vandq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vandq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c new file mode 100644 index 0000000..f3237a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vbicq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c new file mode 100644 index 0000000..975d9db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vbicq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vbicq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c new file mode 100644 index 0000000..afb5ef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c new file mode 100644 index 0000000..3b612cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m_n_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c new file mode 100644 index 0000000..52af15c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c new file mode 100644 index 0000000..b5fb2e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c new file mode 100644 index 0000000..8db12c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c new file mode 100644 index 0000000..fae494c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c new file mode 100644 index 0000000..3f86c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c new file mode 100644 index 0000000..3cc3342 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c new file mode 100644 index 0000000..197d8ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot180_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot180_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c new file mode 100644 index 0000000..3bd195f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot180_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot180_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c new file mode 100644 index 0000000..29e8638 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot270_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot270_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c new file mode 100644 index 0000000..a4ca602 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot270_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot270_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c new file mode 100644 index 0000000..55afaf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot90_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vcmlaq_rot90_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c new file mode 100644 index 0000000..89be04b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot90_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vcmlaq_rot90_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmlat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c new file mode 100644 index 0000000..c83be6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c new file mode 100644 index 0000000..acea3b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c new file mode 100644 index 0000000..78e7606 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot180_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot180_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c new file mode 100644 index 0000000..8643de0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot180_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot180_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c new file mode 100644 index 0000000..632e21c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot270_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c new file mode 100644 index 0000000..e5f35de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot270_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot270_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c new file mode 100644 index 0000000..dfd5d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot90_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c new file mode 100644 index 0000000..7b87791 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot90_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot90_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c new file mode 100644 index 0000000..62c3086 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_s16_f16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c new file mode 100644 index 0000000..0eeba94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_s32_f32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c new file mode 100644 index 0000000..fbc3b9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_u16_f16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c new file mode 100644 index 0000000..b7719de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_u32_f32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c new file mode 100644 index 0000000..8a70933 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return veorq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c new file mode 100644 index 0000000..37ab556 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return veorq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return veorq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c new file mode 100644 index 0000000..f27d664 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vfmaq_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vfmaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c new file mode 100644 index 0000000..7e7d38f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vfmaq_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vfmaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c new file mode 100644 index 0000000..93c8aa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +{ + return vfmaq_m_n_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +{ + return vfmaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c new file mode 100644 index 0000000..1f9189a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +{ + return vfmaq_m_n_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +{ + return vfmaq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmat.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c new file mode 100644 index 0000000..4f91179 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +{ + return vfmasq_m_n_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmast.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +{ + return vfmasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmast.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c new file mode 100644 index 0000000..e630f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +{ + return vfmasq_m_n_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmast.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +{ + return vfmasq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmast.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c new file mode 100644 index 0000000..2cda2e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vfmsq_m_f16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmst.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) +{ + return vfmsq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmst.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c new file mode 100644 index 0000000..773edf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vfmsq_m_f32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmst.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) +{ + return vfmsq_m (a, b, c, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vfmst.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c new file mode 100644 index 0000000..43858dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c new file mode 100644 index 0000000..a3b7e8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c new file mode 100644 index 0000000..d01e266 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c new file mode 100644 index 0000000..5193b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c new file mode 100644 index 0000000..43b751b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmulq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c new file mode 100644 index 0000000..6dee764 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmulq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c new file mode 100644 index 0000000..a0b2d53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vmulq_m_n_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c new file mode 100644 index 0000000..c457195 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vmulq_m_n_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vmulq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c new file mode 100644 index 0000000..9833268 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vornq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c new file mode 100644 index 0000000..48a720a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vornq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vornq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c new file mode 100644 index 0000000..6e8591e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vorrq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c new file mode 100644 index 0000000..09ee673 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vorrq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vorrq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c new file mode 100644 index 0000000..383491d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vsubq_m_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c new file mode 100644 index 0000000..327b524 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vsubq_m_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c new file mode 100644 index 0000000..5657c36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vsubq_m_n_f16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c new file mode 100644 index 0000000..c9502cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vsubq_m_n_f32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ -- cgit v1.1 From 4ff685759913e6b86d027c6007c592460e17974f Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 17:54:30 +0000 Subject: [ARM][GCC][1/5x]: MVE store intrinsics. This patch supports the following MVE ACLE store intrinsics. vstrbq_scatter_offset_s8, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_u8, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u16, vstrbq_s8, vstrbq_s32, vstrbq_s16, vstrbq_u8, vstrbq_u32, vstrbq_u16, vstrwq_scatter_base_s32, vstrwq_scatter_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_s8): Define macro. (vstrbq_u8): Likewise. (vstrbq_u16): Likewise. (vstrbq_scatter_offset_s8): Likewise. (vstrbq_scatter_offset_u8): Likewise. (vstrbq_scatter_offset_u16): Likewise. (vstrbq_s16): Likewise. (vstrbq_u32): Likewise. (vstrbq_scatter_offset_s16): Likewise. (vstrbq_scatter_offset_u32): Likewise. (vstrbq_s32): Likewise. (vstrbq_scatter_offset_s32): Likewise. (vstrwq_scatter_base_s32): Likewise. (vstrwq_scatter_base_u32): Likewise. (__arm_vstrbq_scatter_offset_s8): Define intrinsic. (__arm_vstrbq_scatter_offset_s32): Likewise. (__arm_vstrbq_scatter_offset_s16): Likewise. (__arm_vstrbq_scatter_offset_u8): Likewise. (__arm_vstrbq_scatter_offset_u32): Likewise. (__arm_vstrbq_scatter_offset_u16): Likewise. (__arm_vstrbq_s8): Likewise. (__arm_vstrbq_s32): Likewise. (__arm_vstrbq_s16): Likewise. (__arm_vstrbq_u8): Likewise. (__arm_vstrbq_u32): Likewise. (__arm_vstrbq_u16): Likewise. (__arm_vstrwq_scatter_base_s32): Likewise. (__arm_vstrwq_scatter_base_u32): Likewise. (vstrbq): Define polymorphic variant. (vstrbq_scatter_offset): Likewise. (vstrwq_scatter_base): Likewise. * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. (VSTRWSBQ): Define iterators. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (mve_vstrbq_): Define RTL pattern. (mve_vstrbq_scatter_offset_): Likewise. (mve_vstrwq_scatter_base_v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. --- gcc/ChangeLog | 56 +++++++++ gcc/config/arm/arm-builtins.c | 33 +++++ gcc/config/arm/arm_mve.h | 140 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 6 + gcc/config/arm/mve.md | 73 ++++++++++- gcc/testsuite/ChangeLog | 19 +++ .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 22 ++++ .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 22 ++++ .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 22 ++++ .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 22 ++++ 20 files changed, 633 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3b1154b..be4eb7e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,62 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. + (STRU_QUALIFIERS): Likewise. + (STRSS_QUALIFIERS): Likewise. + (STRSU_QUALIFIERS): Likewise. + (STRSBS_QUALIFIERS): Likewise. + (STRSBU_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vstrbq_s8): Define macro. + (vstrbq_u8): Likewise. + (vstrbq_u16): Likewise. + (vstrbq_scatter_offset_s8): Likewise. + (vstrbq_scatter_offset_u8): Likewise. + (vstrbq_scatter_offset_u16): Likewise. + (vstrbq_s16): Likewise. + (vstrbq_u32): Likewise. + (vstrbq_scatter_offset_s16): Likewise. + (vstrbq_scatter_offset_u32): Likewise. + (vstrbq_s32): Likewise. + (vstrbq_scatter_offset_s32): Likewise. + (vstrwq_scatter_base_s32): Likewise. + (vstrwq_scatter_base_u32): Likewise. + (__arm_vstrbq_scatter_offset_s8): Define intrinsic. + (__arm_vstrbq_scatter_offset_s32): Likewise. + (__arm_vstrbq_scatter_offset_s16): Likewise. + (__arm_vstrbq_scatter_offset_u8): Likewise. + (__arm_vstrbq_scatter_offset_u32): Likewise. + (__arm_vstrbq_scatter_offset_u16): Likewise. + (__arm_vstrbq_s8): Likewise. + (__arm_vstrbq_s32): Likewise. + (__arm_vstrbq_s16): Likewise. + (__arm_vstrbq_u8): Likewise. + (__arm_vstrbq_u32): Likewise. + (__arm_vstrbq_u16): Likewise. + (__arm_vstrwq_scatter_base_s32): Likewise. + (__arm_vstrwq_scatter_base_u32): Likewise. + (vstrbq): Define polymorphic variant. + (vstrbq_scatter_offset): Likewise. + (vstrwq_scatter_base): Likewise. + * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin + qualifier. + (STRU_QUALIFIERS): Likewise. + (STRSS_QUALIFIERS): Likewise. + (STRSU_QUALIFIERS): Likewise. + (STRSBS_QUALIFIERS): Likewise. + (STRSBU_QUALIFIERS): Likewise. + * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. + (VSTRWSBQ): Define iterators. + (VSTRBSOQ): Likewise. + (VSTRBQ): Likewise. + (mve_vstrbq_): Define RTL pattern. + (mve_vstrbq_scatter_offset_): Likewise. + (mve_vstrwq_scatter_base_v4si): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vabdq_m_f32): Define macro. (vabdq_m_f16): Likewise. (vaddq_m_f32): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 26f0379..b285f07 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -579,6 +579,39 @@ arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ (arm_quadop_unone_unone_unone_none_unone_qualifiers) +static enum arm_type_qualifiers +arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_none }; +#define STRS_QUALIFIERS (arm_strs_qualifiers) + +static enum arm_type_qualifiers +arm_stru_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned }; +#define STRU_QUALIFIERS (arm_stru_qualifiers) + +static enum arm_type_qualifiers +arm_strss_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_none}; +#define STRSS_QUALIFIERS (arm_strss_qualifiers) + +static enum arm_type_qualifiers +arm_strsu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define STRSU_QUALIFIERS (arm_strsu_qualifiers) + +static enum arm_type_qualifiers +arm_strsbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, qualifier_none}; +#define STRSBS_QUALIFIERS (arm_strsbs_qualifiers) + +static enum arm_type_qualifiers +arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 4f8135d..019e907 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1702,6 +1702,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsubq_m_f16(__inactive, __a, __b, __p) __arm_vsubq_m_f16(__inactive, __a, __b, __p) #define vsubq_m_n_f32(__inactive, __a, __b, __p) __arm_vsubq_m_n_f32(__inactive, __a, __b, __p) #define vsubq_m_n_f16(__inactive, __a, __b, __p) __arm_vsubq_m_n_f16(__inactive, __a, __b, __p) +#define vstrbq_s8( __addr, __value) __arm_vstrbq_s8( __addr, __value) +#define vstrbq_u8( __addr, __value) __arm_vstrbq_u8( __addr, __value) +#define vstrbq_u16( __addr, __value) __arm_vstrbq_u16( __addr, __value) +#define vstrbq_scatter_offset_s8( __base, __offset, __value) __arm_vstrbq_scatter_offset_s8( __base, __offset, __value) +#define vstrbq_scatter_offset_u8( __base, __offset, __value) __arm_vstrbq_scatter_offset_u8( __base, __offset, __value) +#define vstrbq_scatter_offset_u16( __base, __offset, __value) __arm_vstrbq_scatter_offset_u16( __base, __offset, __value) +#define vstrbq_s16( __addr, __value) __arm_vstrbq_s16( __addr, __value) +#define vstrbq_u32( __addr, __value) __arm_vstrbq_u32( __addr, __value) +#define vstrbq_scatter_offset_s16( __base, __offset, __value) __arm_vstrbq_scatter_offset_s16( __base, __offset, __value) +#define vstrbq_scatter_offset_u32( __base, __offset, __value) __arm_vstrbq_scatter_offset_u32( __base, __offset, __value) +#define vstrbq_s32( __addr, __value) __arm_vstrbq_s32( __addr, __value) +#define vstrbq_scatter_offset_s32( __base, __offset, __value) __arm_vstrbq_scatter_offset_s32( __base, __offset, __value) +#define vstrwq_scatter_base_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_s32(__addr, __offset, __value) +#define vstrwq_scatter_base_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_u32(__addr, __offset, __value) #endif __extension__ extern __inline void @@ -10995,6 +11009,103 @@ __arm_vshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred return __builtin_mve_vshrntq_m_n_uv8hi (__a, __b, __imm, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s8 (int8_t * __base, uint8x16_t __offset, int8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s32 (int8_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s16 (int8_t * __base, uint16x8_t __offset, int16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u8 (uint8_t * __base, uint8x16_t __offset, uint8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u32 (uint8_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u16 (uint8_t * __base, uint16x8_t __offset, uint16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s8 (int8_t * __addr, int8x16_t __value) +{ + __builtin_mve_vstrbq_sv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s32 (int8_t * __addr, int32x4_t __value) +{ + __builtin_mve_vstrbq_sv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s16 (int8_t * __addr, int16x8_t __value) +{ + __builtin_mve_vstrbq_sv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u8 (uint8_t * __addr, uint8x16_t __value) +{ + __builtin_mve_vstrbq_uv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u32 (uint8_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vstrbq_uv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u16 (uint8_t * __addr, uint16x8_t __value) +{ + __builtin_mve_vstrbq_uv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_s32 (uint32x4_t __addr, const int __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_sv4si (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_u32 (uint32x4_t __addr, const int __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -17630,6 +17741,35 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) +#define vstrbq(p0,p1) __arm_vstrbq(p0,p1) +#define __arm_vstrbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrbq_scatter_offset(p0,p1,p2) __arm_vstrbq_scatter_offset(p0,p1,p2) +#define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_base(p0,p1,p2) __arm_vstrwq_scatter_base(p0,p1,p2) +#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + #endif /* MVE Integer. */ #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index b448889..2c67524 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -685,3 +685,9 @@ VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) +VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si) +VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si) +VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) +VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si) +VAR1 (STRSBS, vstrwq_scatter_base_s, v4si) +VAR1 (STRSBU, vstrwq_scatter_base_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index bf4eb5d..3d0a172 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -191,7 +191,8 @@ VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F - VMINNMQ_M_F VSUBQ_M_F]) + VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -342,7 +343,9 @@ (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") - (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")]) + (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") + (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -359,6 +362,7 @@ (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) +(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -562,6 +566,9 @@ (define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) +(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) +(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) +(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -7940,3 +7947,65 @@ "vpst\;vsubt.f%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) + +;; +;; [vstrbq_s vstrbq_u] +;; +(define_insn "mve_vstrbq_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w")] + VSTRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn("vstrb.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] +;; +(define_insn "mve_vstrbq_scatter_offset_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VSTRBSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrb.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] +;; +(define_insn "mve_vstrwq_scatter_base_v4si" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSTRWSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4ed6dc7..9b79f8d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c new file mode 100644 index 0000000..80fce9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int16x8_t value) +{ + vstrbq_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * addr, int16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c new file mode 100644 index 0000000..ae3c89e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int32x4_t value) +{ + vstrbq_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * addr, int32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c new file mode 100644 index 0000000..72a3673 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value) +{ + vstrbq_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c new file mode 100644 index 0000000..b4ad4f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset_s16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c new file mode 100644 index 0000000..507eef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c new file mode 100644 index 0000000..f5467c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset_s8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c new file mode 100644 index 0000000..cea6699 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset_u16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c new file mode 100644 index 0000000..6ad7ec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c new file mode 100644 index 0000000..4122622 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset_u8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c new file mode 100644 index 0000000..5871fbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint16x8_t value) +{ + vstrbq_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * addr, uint16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c new file mode 100644 index 0000000..31d6d86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint32x4_t value) +{ + vstrbq_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * addr, uint32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c new file mode 100644 index 0000000..7415b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value) +{ + vstrbq_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c new file mode 100644 index 0000000..0fb6af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base_s32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c new file mode 100644 index 0000000..795c0b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base_u32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ -- cgit v1.1 From 535a8645bb882bf4cc3cc4c9d05b3745022d0a6d Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 18:13:53 +0000 Subject: [ARM][GCC][2/5x]: MVE load intrinsics. This patch supports the following MVE ACLE load intrinsics. vldrbq_gather_offset_u8, vldrbq_gather_offset_s8, vldrbq_s8, vldrbq_u8, vldrbq_gather_offset_u16, vldrbq_gather_offset_s16, vldrbq_s16, vldrbq_u16, vldrbq_gather_offset_u32, vldrbq_gather_offset_s32, vldrbq_s32, vldrbq_u32, vldrwq_gather_base_s32, vldrwq_gather_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. (vldrbq_gather_offset_s8): Likewise. (vldrbq_s8): Likewise. (vldrbq_u8): Likewise. (vldrbq_gather_offset_u16): Likewise. (vldrbq_gather_offset_s16): Likewise. (vldrbq_s16): Likewise. (vldrbq_u16): Likewise. (vldrbq_gather_offset_u32): Likewise. (vldrbq_gather_offset_s32): Likewise. (vldrbq_s32): Likewise. (vldrbq_u32): Likewise. (vldrwq_gather_base_s32): Likewise. (vldrwq_gather_base_u32): Likewise. (__arm_vldrbq_gather_offset_u8): Define intrinsic. (__arm_vldrbq_gather_offset_s8): Likewise. (__arm_vldrbq_s8): Likewise. (__arm_vldrbq_u8): Likewise. (__arm_vldrbq_gather_offset_u16): Likewise. (__arm_vldrbq_gather_offset_s16): Likewise. (__arm_vldrbq_s16): Likewise. (__arm_vldrbq_u16): Likewise. (__arm_vldrbq_gather_offset_u32): Likewise. (__arm_vldrbq_gather_offset_s32): Likewise. (__arm_vldrbq_s32): Likewise. (__arm_vldrbq_u32): Likewise. (__arm_vldrwq_gather_base_s32): Likewise. (__arm_vldrwq_gather_base_u32): Likewise. (vldrbq_gather_offset): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/mve.md (VLDRBGOQ): Define iterator. (VLDRBQ): Likewise. (VLDRWGBQ): Likewise. (mve_vldrbq_gather_offset_): Define RTL pattern. (mve_vldrbq_): Likewise. (mve_vldrwq_gather_base_v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. --- gcc/ChangeLog | 54 +++++++ gcc/config/arm/arm-builtins.c | 30 ++++ gcc/config/arm/arm_mve.h | 175 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 6 + gcc/config/arm/mve.md | 72 ++++++++- gcc/testsuite/ChangeLog | 19 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 +++ .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 ++ .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 ++ .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 ++ .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 ++ 20 files changed, 598 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index be4eb7e1..729a1c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,60 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin + qualifier. + (LDRGS_QUALIFIERS): Likewise. + (LDRS_QUALIFIERS): Likewise. + (LDRU_QUALIFIERS): Likewise. + (LDRGBS_QUALIFIERS): Likewise. + (LDRGBU_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. + (vldrbq_gather_offset_s8): Likewise. + (vldrbq_s8): Likewise. + (vldrbq_u8): Likewise. + (vldrbq_gather_offset_u16): Likewise. + (vldrbq_gather_offset_s16): Likewise. + (vldrbq_s16): Likewise. + (vldrbq_u16): Likewise. + (vldrbq_gather_offset_u32): Likewise. + (vldrbq_gather_offset_s32): Likewise. + (vldrbq_s32): Likewise. + (vldrbq_u32): Likewise. + (vldrwq_gather_base_s32): Likewise. + (vldrwq_gather_base_u32): Likewise. + (__arm_vldrbq_gather_offset_u8): Define intrinsic. + (__arm_vldrbq_gather_offset_s8): Likewise. + (__arm_vldrbq_s8): Likewise. + (__arm_vldrbq_u8): Likewise. + (__arm_vldrbq_gather_offset_u16): Likewise. + (__arm_vldrbq_gather_offset_s16): Likewise. + (__arm_vldrbq_s16): Likewise. + (__arm_vldrbq_u16): Likewise. + (__arm_vldrbq_gather_offset_u32): Likewise. + (__arm_vldrbq_gather_offset_s32): Likewise. + (__arm_vldrbq_s32): Likewise. + (__arm_vldrbq_u32): Likewise. + (__arm_vldrwq_gather_base_s32): Likewise. + (__arm_vldrwq_gather_base_u32): Likewise. + (vldrbq_gather_offset): Define polymorphic variant. + * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin + qualifier. + (LDRGS_QUALIFIERS): Likewise. + (LDRS_QUALIFIERS): Likewise. + (LDRU_QUALIFIERS): Likewise. + (LDRGBS_QUALIFIERS): Likewise. + (LDRGBU_QUALIFIERS): Likewise. + * config/arm/mve.md (VLDRBGOQ): Define iterator. + (VLDRBQ): Likewise. + (VLDRWGBQ): Likewise. + (mve_vldrbq_gather_offset_): Define RTL pattern. + (mve_vldrbq_): Likewise. + (mve_vldrwq_gather_base_v4si): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b285f07..aced55f 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -612,6 +612,36 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_unsigned}; #define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) +static enum arm_type_qualifiers +arm_ldrgu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; +#define LDRGU_QUALIFIERS (arm_ldrgu_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_pointer, qualifier_unsigned}; +#define LDRGS_QUALIFIERS (arm_ldrgs_qualifiers) + +static enum arm_type_qualifiers +arm_ldrs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_pointer}; +#define LDRS_QUALIFIERS (arm_ldrs_qualifiers) + +static enum arm_type_qualifiers +arm_ldru_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_pointer}; +#define LDRU_QUALIFIERS (arm_ldru_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_immediate}; +#define LDRGBS_QUALIFIERS (arm_ldrgbs_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; +#define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 019e907..c2c195a 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1716,6 +1716,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrbq_scatter_offset_s32( __base, __offset, __value) __arm_vstrbq_scatter_offset_s32( __base, __offset, __value) #define vstrwq_scatter_base_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_s32(__addr, __offset, __value) #define vstrwq_scatter_base_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_u32(__addr, __offset, __value) +#define vldrbq_gather_offset_u8(__base, __offset) __arm_vldrbq_gather_offset_u8(__base, __offset) +#define vldrbq_gather_offset_s8(__base, __offset) __arm_vldrbq_gather_offset_s8(__base, __offset) +#define vldrbq_s8(__base) __arm_vldrbq_s8(__base) +#define vldrbq_u8(__base) __arm_vldrbq_u8(__base) +#define vldrbq_gather_offset_u16(__base, __offset) __arm_vldrbq_gather_offset_u16(__base, __offset) +#define vldrbq_gather_offset_s16(__base, __offset) __arm_vldrbq_gather_offset_s16(__base, __offset) +#define vldrbq_s16(__base) __arm_vldrbq_s16(__base) +#define vldrbq_u16(__base) __arm_vldrbq_u16(__base) +#define vldrbq_gather_offset_u32(__base, __offset) __arm_vldrbq_gather_offset_u32(__base, __offset) +#define vldrbq_gather_offset_s32(__base, __offset) __arm_vldrbq_gather_offset_s32(__base, __offset) +#define vldrbq_s32(__base) __arm_vldrbq_s32(__base) +#define vldrbq_u32(__base) __arm_vldrbq_u32(__base) +#define vldrwq_gather_base_s32(__addr, __offset) __arm_vldrwq_gather_base_s32(__addr, __offset) +#define vldrwq_gather_base_u32(__addr, __offset) __arm_vldrwq_gather_base_u32(__addr, __offset) #endif __extension__ extern __inline void @@ -11106,6 +11120,105 @@ __arm_vstrwq_scatter_base_u32 (uint32x4_t __addr, const int __offset, uint32x4_t { __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); } + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u8 (uint8_t const * __base, uint8x16_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_uv16qi ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s8 (int8_t const * __base, uint8x16_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv16qi ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s8 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u8 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u16 (uint8_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_uv8hi ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s16 (int8_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv8hi ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s16 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv8hi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u16 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv8hi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u32 (uint8_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_uv4si ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s32 (int8_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv4si ((__builtin_neon_qi *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s32 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv4si ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u32 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv4si ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_s32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_sv4si (__addr, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_u32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_uv4si (__addr, __offset); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -17770,6 +17883,57 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) +#define vldrbq_gather_offset(p0,p1) __arm_vldrbq_gather_offset(p0,p1) +#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrbq_p(p0,p1,p2) __arm_vstrbq_p(p0,p1,p2) +#define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vstrbq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrwq_scatter_base_p(p0,p1,p2,p3) __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2) +#define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #endif /* MVE Integer. */ #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) @@ -18497,6 +18661,17 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_m_p8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_m_p16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) +#define vldrbq_gather_offset(p0,p1) __arm_vldrbq_gather_offset(p0,p1) +#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + #ifdef __cplusplus } #endif diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 2c67524..f6d0fec 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -691,3 +691,9 @@ VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si) VAR1 (STRSBS, vstrwq_scatter_base_s, v4si) VAR1 (STRSBU, vstrwq_scatter_base_u, v4si) +VAR3 (LDRGU, vldrbq_gather_offset_u, v16qi, v8hi, v4si) +VAR3 (LDRGS, vldrbq_gather_offset_s, v16qi, v8hi, v4si) +VAR3 (LDRS, vldrbq_s, v16qi, v8hi, v4si) +VAR3 (LDRU, vldrbq_u, v16qi, v8hi, v4si) +VAR1 (LDRGBS, vldrwq_gather_base_s, v4si) +VAR1 (LDRGBU, vldrwq_gather_base_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3d0a172..be1b9fa 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -192,7 +192,8 @@ VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U - VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U]) + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S + VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -345,7 +346,9 @@ (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") - (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")]) + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u") + (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s") + (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -569,6 +572,9 @@ (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) (define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) (define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) +(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U]) +(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) +(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -8009,3 +8015,65 @@ return ""; } [(set_attr "length" "4")]) + +;; +;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] +;; +(define_insn "mve_vldrbq_gather_offset_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VLDRBGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + if (!strcmp ("","s") && == 8) + output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vldrb.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrbq_s vldrbq_u] +;; +(define_insn "mve_vldrbq_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us")] + VLDRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vldrb.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_base_s vldrwq_gather_base_u] +;; +(define_insn "mve_vldrwq_gather_base_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VLDRWGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9b79f8d..4f5f1a1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c new file mode 100644 index 0000000..d945c65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ + +int16x8_t +foo1 (int8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c new file mode 100644 index 0000000..de7c681 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ + +int32x4_t +foo1 (int8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c new file mode 100644 index 0000000..6e85ec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset_s8 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +int8x16_t +foo1 (int8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c new file mode 100644 index 0000000..d093cd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ + +uint16x8_t +foo1 (uint8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c new file mode 100644 index 0000000..671b3a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ + +uint32x4_t +foo1 (uint8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c new file mode 100644 index 0000000..57c086e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset_u8 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c new file mode 100644 index 0000000..695fc17 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base) +{ + return vldrbq_s16 (base); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c new file mode 100644 index 0000000..22ac325 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base) +{ + return vldrbq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c new file mode 100644 index 0000000..437639c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base) +{ + return vldrbq_s8 (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c new file mode 100644 index 0000000..2a48af1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base) +{ + return vldrbq_u16 (base); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c new file mode 100644 index 0000000..ef37295 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base) +{ + return vldrbq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c new file mode 100644 index 0000000..7366faa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base) +{ + return vldrbq_u8 (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c new file mode 100644 index 0000000..a9a695d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t addr) +{ + return vldrwq_gather_base_s32 (addr, 4); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c new file mode 100644 index 0000000..8c2b541 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t addr) +{ + return vldrwq_gather_base_u32 (addr, 4); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ -- cgit v1.1 From 405e918c31418b00b4939efefc333cd378cabf43 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 18:22:21 +0000 Subject: [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. This patch supports the following MVE ACLE store intrinsics with predicated suffix. vstrbq_p_s8, vstrbq_p_s32, vstrbq_p_s16, vstrbq_p_u8, vstrbq_p_u32, vstrbq_p_u16, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u16, vstrwq_scatter_base_p_s32, vstrwq_scatter_base_p_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. (vstrbq_p_s32): Likewise. (vstrbq_p_s16): Likewise. (vstrbq_p_u8): Likewise. (vstrbq_p_u32): Likewise. (vstrbq_p_u16): Likewise. (vstrbq_scatter_offset_p_s8): Likewise. (vstrbq_scatter_offset_p_s32): Likewise. (vstrbq_scatter_offset_p_s16): Likewise. (vstrbq_scatter_offset_p_u8): Likewise. (vstrbq_scatter_offset_p_u32): Likewise. (vstrbq_scatter_offset_p_u16): Likewise. (vstrwq_scatter_base_p_s32): Likewise. (vstrwq_scatter_base_p_u32): Likewise. (__arm_vstrbq_p_s8): Define intrinsic. (__arm_vstrbq_p_s32): Likewise. (__arm_vstrbq_p_s16): Likewise. (__arm_vstrbq_p_u8): Likewise. (__arm_vstrbq_p_u32): Likewise. (__arm_vstrbq_p_u16): Likewise. (__arm_vstrbq_scatter_offset_p_s8): Likewise. (__arm_vstrbq_scatter_offset_p_s32): Likewise. (__arm_vstrbq_scatter_offset_p_s16): Likewise. (__arm_vstrbq_scatter_offset_p_u8): Likewise. (__arm_vstrbq_scatter_offset_p_u32): Likewise. (__arm_vstrbq_scatter_offset_p_u16): Likewise. (__arm_vstrwq_scatter_base_p_s32): Likewise. (__arm_vstrwq_scatter_base_p_u32): Likewise. (vstrbq_p): Define polymorphic variant. (vstrbq_scatter_offset_p): Likewise. (vstrwq_scatter_base_p): Likewise. * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vstrbq_scatter_offset_p_): Define RTL pattern. (mve_vstrwq_scatter_base_p_v4si): Likewise. (mve_vstrbq_p_): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. --- gcc/ChangeLog | 54 ++++++++++ gcc/config/arm/arm-builtins.c | 35 +++++++ gcc/config/arm/arm_mve.h | 111 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 6 ++ gcc/config/arm/mve.md | 65 ++++++++++++ gcc/testsuite/ChangeLog | 19 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 22 ++++ .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 22 ++++ .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 22 ++++ .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 22 ++++ 20 files changed, 598 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 729a1c8..33c02eb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,60 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin + qualifier. + (STRU_P_QUALIFIERS): Likewise. + (STRSU_P_QUALIFIERS): Likewise. + (STRSS_P_QUALIFIERS): Likewise. + (STRSBS_P_QUALIFIERS): Likewise. + (STRSBU_P_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. + (vstrbq_p_s32): Likewise. + (vstrbq_p_s16): Likewise. + (vstrbq_p_u8): Likewise. + (vstrbq_p_u32): Likewise. + (vstrbq_p_u16): Likewise. + (vstrbq_scatter_offset_p_s8): Likewise. + (vstrbq_scatter_offset_p_s32): Likewise. + (vstrbq_scatter_offset_p_s16): Likewise. + (vstrbq_scatter_offset_p_u8): Likewise. + (vstrbq_scatter_offset_p_u32): Likewise. + (vstrbq_scatter_offset_p_u16): Likewise. + (vstrwq_scatter_base_p_s32): Likewise. + (vstrwq_scatter_base_p_u32): Likewise. + (__arm_vstrbq_p_s8): Define intrinsic. + (__arm_vstrbq_p_s32): Likewise. + (__arm_vstrbq_p_s16): Likewise. + (__arm_vstrbq_p_u8): Likewise. + (__arm_vstrbq_p_u32): Likewise. + (__arm_vstrbq_p_u16): Likewise. + (__arm_vstrbq_scatter_offset_p_s8): Likewise. + (__arm_vstrbq_scatter_offset_p_s32): Likewise. + (__arm_vstrbq_scatter_offset_p_s16): Likewise. + (__arm_vstrbq_scatter_offset_p_u8): Likewise. + (__arm_vstrbq_scatter_offset_p_u32): Likewise. + (__arm_vstrbq_scatter_offset_p_u16): Likewise. + (__arm_vstrwq_scatter_base_p_s32): Likewise. + (__arm_vstrwq_scatter_base_p_u32): Likewise. + (vstrbq_p): Define polymorphic variant. + (vstrbq_scatter_offset_p): Likewise. + (vstrwq_scatter_base_p): Likewise. + * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin + qualifier. + (STRU_P_QUALIFIERS): Likewise. + (STRSU_P_QUALIFIERS): Likewise. + (STRSS_P_QUALIFIERS): Likewise. + (STRSBS_P_QUALIFIERS): Likewise. + (STRSBU_P_QUALIFIERS): Likewise. + * config/arm/mve.md (mve_vstrbq_scatter_offset_p_): Define + RTL pattern. + (mve_vstrwq_scatter_base_p_v4si): Likewise. + (mve_vstrbq_p_): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index aced55f..c87fa31 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -613,6 +613,41 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) static enum arm_type_qualifiers +arm_strs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_none, qualifier_unsigned}; +#define STRS_P_QUALIFIERS (arm_strs_p_qualifiers) + +static enum arm_type_qualifiers +arm_stru_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define STRU_P_QUALIFIERS (arm_stru_p_qualifiers) + +static enum arm_type_qualifiers +arm_strsu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned, qualifier_unsigned}; +#define STRSU_P_QUALIFIERS (arm_strsu_p_qualifiers) + +static enum arm_type_qualifiers +arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_none, qualifier_unsigned}; +#define STRSS_P_QUALIFIERS (arm_strss_p_qualifiers) + +static enum arm_type_qualifiers +arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, + qualifier_none, qualifier_unsigned}; +#define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers) + +static enum arm_type_qualifiers +arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned, qualifier_unsigned}; +#define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers) + +static enum arm_type_qualifiers arm_ldrgu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; #define LDRGU_QUALIFIERS (arm_ldrgu_qualifiers) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index c2c195a..deed81c 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1730,6 +1730,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vldrbq_u32(__base) __arm_vldrbq_u32(__base) #define vldrwq_gather_base_s32(__addr, __offset) __arm_vldrwq_gather_base_s32(__addr, __offset) #define vldrwq_gather_base_u32(__addr, __offset) __arm_vldrwq_gather_base_u32(__addr, __offset) +#define vstrbq_p_s8( __addr, __value, __p) __arm_vstrbq_p_s8( __addr, __value, __p) +#define vstrbq_p_s32( __addr, __value, __p) __arm_vstrbq_p_s32( __addr, __value, __p) +#define vstrbq_p_s16( __addr, __value, __p) __arm_vstrbq_p_s16( __addr, __value, __p) +#define vstrbq_p_u8( __addr, __value, __p) __arm_vstrbq_p_u8( __addr, __value, __p) +#define vstrbq_p_u32( __addr, __value, __p) __arm_vstrbq_p_u32( __addr, __value, __p) +#define vstrbq_p_u16( __addr, __value, __p) __arm_vstrbq_p_u16( __addr, __value, __p) +#define vstrbq_scatter_offset_p_s8( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_s8( __base, __offset, __value, __p) +#define vstrbq_scatter_offset_p_s32( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_s32( __base, __offset, __value, __p) +#define vstrbq_scatter_offset_p_s16( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_s16( __base, __offset, __value, __p) +#define vstrbq_scatter_offset_p_u8( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u8( __base, __offset, __value, __p) +#define vstrbq_scatter_offset_p_u32( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u32( __base, __offset, __value, __p) +#define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) +#define vstrwq_scatter_base_p_s32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_p_s32(__addr, __offset, __value, __p) +#define vstrwq_scatter_base_p_u32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_p_u32(__addr, __offset, __value, __p) #endif __extension__ extern __inline void @@ -11219,6 +11233,103 @@ __arm_vldrwq_gather_base_u32 (uint32x4_t __addr, const int __offset) return __builtin_mve_vldrwq_gather_base_uv4si (__addr, __offset); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_sv16qi ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_s32 (int8_t * __addr, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_sv4si ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_s16 (int8_t * __addr, int16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_sv8hi ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_uv16qi ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_u32 (uint8_t * __addr, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_uv4si ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_p_u16 (uint8_t * __addr, uint16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_p_uv8hi ((__builtin_neon_qi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_s8 (int8_t * __base, uint8x16_t __offset, int8x16_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_sv16qi ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_s32 (int8_t * __base, uint32x4_t __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_sv4si ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_s16 (int8_t * __base, uint16x8_t __offset, int16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_sv8hi ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_u8 (uint8_t * __base, uint8x16_t __offset, uint8x16_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_uv16qi ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_u32 (uint8_t * __base, uint32x4_t __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_uv4si ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_p_u16 (uint8_t * __base, uint16x8_t __offset, uint16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrbq_scatter_offset_p_uv8hi ((__builtin_neon_qi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_p_s32 (uint32x4_t __addr, const int __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_p_sv4si (__addr, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_p_u32 (uint32x4_t __addr, const int __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value, __p); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index f6d0fec..c6e065d 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -697,3 +697,9 @@ VAR3 (LDRS, vldrbq_s, v16qi, v8hi, v4si) VAR3 (LDRU, vldrbq_u, v16qi, v8hi, v4si) VAR1 (LDRGBS, vldrwq_gather_base_s, v4si) VAR1 (LDRGBU, vldrwq_gather_base_u, v4si) +VAR3 (STRS_P, vstrbq_p_s, v16qi, v8hi, v4si) +VAR3 (STRU_P, vstrbq_p_u, v16qi, v8hi, v4si) +VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi, v8hi, v4si) +VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si) +VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si) +VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index be1b9fa..0e8b04f 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -8077,3 +8077,68 @@ return ""; } [(set_attr "length" "4")]) + +;; +;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u] +;; +(define_insn "mve_vstrbq_scatter_offset_p_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRBSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrbt.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u] +;; +(define_insn "mve_vstrwq_scatter_base_p_v4si" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrbq_p_s vstrbq_p_u] +;; +(define_insn "mve_vstrbq_p_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VSTRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vpst\n\tvstrbt.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4f5f1a1..1998f3e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c new file mode 100644 index 0000000..704ac27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int16x8_t value, mve_pred16_t p) +{ + vstrbq_p_s16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ + +void +foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c new file mode 100644 index 0000000..0c6c0a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrbq_p_s32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ + +void +foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c new file mode 100644 index 0000000..aa8ce92 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vstrbq_p_s8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c new file mode 100644 index 0000000..e9911c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vstrbq_p_u16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ + +void +foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c new file mode 100644 index 0000000..39e0cd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrbq_p_u32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ + +void +foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c new file mode 100644 index 0000000..809fe38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vstrbq_p_u8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vstrbq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c new file mode 100644 index 0000000..8813fbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_s16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ + +void +foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c new file mode 100644 index 0000000..f6116ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_s32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ + +void +foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c new file mode 100644 index 0000000..7fa63ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_s8 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c new file mode 100644 index 0000000..3db472a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_u16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ + +void +foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c new file mode 100644 index 0000000..4055d70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_u32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ + +void +foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c new file mode 100644 index 0000000..e96f7a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p_u8 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) +{ + vstrbq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c new file mode 100644 index 0000000..0bce9e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p_s32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c new file mode 100644 index 0000000..59b21d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p_u32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ -- cgit v1.1 From 429d607bc468828ea1e40852bbf8a1e9bbc34e7a Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 18:35:17 +0000 Subject: [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. This patch supports the following MVE ACLE load intrinsics with zero(_z) suffix. * ``_z`` (zero) which indicates false-predicated lanes are filled with zeroes, these are only used for load instructions. vldrbq_gather_offset_z_s16, vldrbq_gather_offset_z_u8, vldrbq_gather_offset_z_s32, vldrbq_gather_offset_z_u16, vldrbq_gather_offset_z_u32, vldrbq_gather_offset_z_s8, vldrbq_z_s16, vldrbq_z_u8, vldrbq_z_s8, vldrbq_z_s32, vldrbq_z_u16, vldrbq_z_u32, vldrwq_gather_base_z_u32, vldrwq_gather_base_z_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. (vldrbq_gather_offset_z_u8): Likewise. (vldrbq_gather_offset_z_s32): Likewise. (vldrbq_gather_offset_z_u16): Likewise. (vldrbq_gather_offset_z_u32): Likewise. (vldrbq_gather_offset_z_s8): Likewise. (vldrbq_z_s16): Likewise. (vldrbq_z_u8): Likewise. (vldrbq_z_s8): Likewise. (vldrbq_z_s32): Likewise. (vldrbq_z_u16): Likewise. (vldrbq_z_u32): Likewise. (vldrwq_gather_base_z_u32): Likewise. (vldrwq_gather_base_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. (__arm_vldrbq_gather_offset_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s16): Likewise. (__arm_vldrbq_gather_offset_z_u8): Likewise. (__arm_vldrbq_gather_offset_z_u32): Likewise. (__arm_vldrbq_gather_offset_z_u16): Likewise. (__arm_vldrbq_z_s8): Likewise. (__arm_vldrbq_z_s32): Likewise. (__arm_vldrbq_z_s16): Likewise. (__arm_vldrbq_z_u8): Likewise. (__arm_vldrbq_z_u32): Likewise. (__arm_vldrbq_z_u16): Likewise. (__arm_vldrwq_gather_base_z_s32): Likewise. (__arm_vldrwq_gather_base_z_u32): Likewise. (vldrbq_gather_offset_z): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vldrbq_gather_offset_z_): Define RTL pattern. (mve_vldrbq_z_): Likewise. (mve_vldrwq_gather_base_z_v4si): Likewise. gcc/testsuite/ChangeLog: Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. --- gcc/ChangeLog | 52 +++++++++ gcc/config/arm/arm-builtins.c | 34 ++++++ gcc/config/arm/arm_mve.h | 118 ++++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 6 ++ gcc/config/arm/mve.md | 66 ++++++++++++ gcc/testsuite/ChangeLog | 19 ++++ .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 ++++ .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 ++++ .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 ++++ .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 ++++ .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 ++++ .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 ++++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 +++ .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 +++ .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 +++ .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 +++ 20 files changed, 537 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 33c02eb..4d4f9b1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,58 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin + qualifier. + (LDRGBU_Z_QUALIFIERS): Likewise. + (LDRGS_Z_QUALIFIERS): Likewise. + (LDRGU_Z_QUALIFIERS): Likewise. + (LDRS_Z_QUALIFIERS): Likewise. + (LDRU_Z_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. + (vldrbq_gather_offset_z_u8): Likewise. + (vldrbq_gather_offset_z_s32): Likewise. + (vldrbq_gather_offset_z_u16): Likewise. + (vldrbq_gather_offset_z_u32): Likewise. + (vldrbq_gather_offset_z_s8): Likewise. + (vldrbq_z_s16): Likewise. + (vldrbq_z_u8): Likewise. + (vldrbq_z_s8): Likewise. + (vldrbq_z_s32): Likewise. + (vldrbq_z_u16): Likewise. + (vldrbq_z_u32): Likewise. + (vldrwq_gather_base_z_u32): Likewise. + (vldrwq_gather_base_z_s32): Likewise. + (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. + (__arm_vldrbq_gather_offset_z_s32): Likewise. + (__arm_vldrbq_gather_offset_z_s16): Likewise. + (__arm_vldrbq_gather_offset_z_u8): Likewise. + (__arm_vldrbq_gather_offset_z_u32): Likewise. + (__arm_vldrbq_gather_offset_z_u16): Likewise. + (__arm_vldrbq_z_s8): Likewise. + (__arm_vldrbq_z_s32): Likewise. + (__arm_vldrbq_z_s16): Likewise. + (__arm_vldrbq_z_u8): Likewise. + (__arm_vldrbq_z_u32): Likewise. + (__arm_vldrbq_z_u16): Likewise. + (__arm_vldrwq_gather_base_z_s32): Likewise. + (__arm_vldrwq_gather_base_z_u32): Likewise. + (vldrbq_gather_offset_z): Define polymorphic variant. + * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin + qualifier. + (LDRGBU_Z_QUALIFIERS): Likewise. + (LDRGS_Z_QUALIFIERS): Likewise. + (LDRGU_Z_QUALIFIERS): Likewise. + (LDRS_Z_QUALIFIERS): Likewise. + (LDRU_Z_QUALIFIERS): Likewise. + * config/arm/mve.md (mve_vldrbq_gather_offset_z_): Define + RTL pattern. + (mve_vldrbq_z_): Likewise. + (mve_vldrwq_gather_base_z_v4si): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin qualifier. (STRU_P_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index c87fa31..c3deb9e 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -677,6 +677,40 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; #define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers) +static enum arm_type_qualifiers +arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_pointer, qualifier_unsigned}; +#define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; +#define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index deed81c..4570a0b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1744,6 +1744,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) #define vstrwq_scatter_base_p_s32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_p_s32(__addr, __offset, __value, __p) #define vstrwq_scatter_base_p_u32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_p_u32(__addr, __offset, __value, __p) +#define vldrbq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s16(__base, __offset, __p) +#define vldrbq_gather_offset_z_u8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u8(__base, __offset, __p) +#define vldrbq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s32(__base, __offset, __p) +#define vldrbq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u16(__base, __offset, __p) +#define vldrbq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u32(__base, __offset, __p) +#define vldrbq_gather_offset_z_s8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s8(__base, __offset, __p) +#define vldrbq_z_s16(__base, __p) __arm_vldrbq_z_s16(__base, __p) +#define vldrbq_z_u8(__base, __p) __arm_vldrbq_z_u8(__base, __p) +#define vldrbq_z_s8(__base, __p) __arm_vldrbq_z_s8(__base, __p) +#define vldrbq_z_s32(__base, __p) __arm_vldrbq_z_s32(__base, __p) +#define vldrbq_z_u16(__base, __p) __arm_vldrbq_z_u16(__base, __p) +#define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p) +#define vldrwq_gather_base_z_u32(__addr, __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr, __offset, __p) +#define vldrwq_gather_base_z_s32(__addr, __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr, __offset, __p) #endif __extension__ extern __inline void @@ -11330,6 +11344,105 @@ __arm_vstrwq_scatter_base_p_u32 (uint32x4_t __addr, const int __offset, uint32x4 { __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value, __p); } + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s8 (int8_t const * __base, uint8x16_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv16qi ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s32 (int8_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv4si ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s16 (int8_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv8hi ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u8 (uint8_t const * __base, uint8x16_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv16qi ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u32 (uint8_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv4si ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u16 (uint8_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv8hi ((__builtin_neon_qi *) __base, __offset, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s8 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv16qi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s32 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv4si ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s16 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv8hi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u8 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv16qi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u32 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv4si ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u16 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv8hi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_s32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_sv4si (__addr, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -13471,6 +13584,7 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve { return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); } + #endif enum { @@ -18034,6 +18148,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) +#endif /* MVE Integer. */ + #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2) #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -18045,8 +18161,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#endif /* MVE Integer. */ - #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index c6e065d..0f466e4 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -703,3 +703,9 @@ VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi, v8hi, v4si) VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si) VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si) VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si) +VAR1 (LDRGBS_Z, vldrwq_gather_base_z_s, v4si) +VAR1 (LDRGBU_Z, vldrwq_gather_base_z_u, v4si) +VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si) +VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si) +VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si) +VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0e8b04f..03a90ab 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -8142,3 +8142,69 @@ return ""; } [(set_attr "length" "8")]) + +;; +;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] +;; +(define_insn "mve_vldrbq_gather_offset_z_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRBGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + if (!strcmp ("","s") && == 8) + output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vpst\n\tvldrbt.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrbq_z_s vldrbq_z_u] +;; +(define_insn "mve_vldrbq_z_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vpst\n\tvldrbt.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] +;; +(define_insn "mve_vldrwq_gather_base_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1998f3e..451f0ee 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,25 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c new file mode 100644 index 0000000..a51689f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ + +int16x8_t +foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c new file mode 100644 index 0000000..4b3b8ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ + +int32x4_t +foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c new file mode 100644 index 0000000..14e0f30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s8 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +int8x16_t +foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c new file mode 100644 index 0000000..7b07500 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ + +uint16x8_t +foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c new file mode 100644 index 0000000..c81ef6d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ + +uint32x4_t +foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c new file mode 100644 index 0000000..3c91278 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u8 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c new file mode 100644 index 0000000..c709db6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c new file mode 100644 index 0000000..aa47e23 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c new file mode 100644 index 0000000..85d7ef4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c new file mode 100644 index 0000000..0543057 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c new file mode 100644 index 0000000..73b9ea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c new file mode 100644 index 0000000..3925c9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c new file mode 100644 index 0000000..2e61760 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t addr, mve_pred16_t p) +{ + return vldrwq_gather_base_z_s32 (addr, 4, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c new file mode 100644 index 0000000..a71c562 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t addr, mve_pred16_t p) +{ + return vldrwq_gather_base_z_u32 (addr, 4, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ -- cgit v1.1 From bf1e3d5afa16045126c3d95ece8fd617e71cf9e6 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 18:48:05 +0000 Subject: [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from memory. This patch supports the following MVE ACLE load intrinsics which load a byte, halfword, or word from memory. vld1q_s8, vld1q_s32, vld1q_s16, vld1q_u8, vld1q_u32, vld1q_u16, vldrhq_gather_offset_s32, vldrhq_gather_offset_s16, vldrhq_gather_offset_u32, vldrhq_gather_offset_u16, vldrhq_gather_offset_z_s32, vldrhq_gather_offset_z_s16, vldrhq_gather_offset_z_u32, vldrhq_gather_offset_z_u16, vldrhq_gather_shifted_offset_s32,vldrwq_f32, vldrwq_z_f32, vldrhq_gather_shifted_offset_s16, vldrhq_gather_shifted_offset_u32, vldrhq_gather_shifted_offset_u16, vldrhq_gather_shifted_offset_z_s32, vldrhq_gather_shifted_offset_z_s16, vldrhq_gather_shifted_offset_z_u32, vldrhq_gather_shifted_offset_z_u16, vldrhq_s32, vldrhq_s16, vldrhq_u32, vldrhq_u16, vldrhq_z_s32, vldrhq_z_s16, vldrhq_z_u32, vldrhq_z_u16, vldrwq_s32, vldrwq_u32, vldrwq_z_s32, vldrwq_z_u32, vld1q_f32, vld1q_f16, vldrhq_f16, vldrhq_z_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_): Likewise. (mve_vldrhq_gather_offset_z_): Likewise. (mve_vldrhq_gather_shifted_offset_): Likewise. (mve_vldrhq_gather_shifted_offset_z_): Likewise. (mve_vldrhq_): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vld1q_f): Define RTL expand pattern. (mve_vld1q_): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. --- gcc/ChangeLog | 119 +++++++ gcc/config/arm/arm_mve.h | 378 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 23 ++ gcc/config/arm/mve.md | 298 +++++++++++++++- gcc/testsuite/ChangeLog | 45 +++ .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 ++ .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 ++ .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 ++ .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 ++ .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 ++ .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 ++ .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 ++ .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 ++ .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 ++ .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 ++ .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 ++ .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 ++ .../vldrhq_gather_shifted_offset_z_s16.c | 22 ++ .../vldrhq_gather_shifted_offset_z_s32.c | 22 ++ .../vldrhq_gather_shifted_offset_z_u16.c | 22 ++ .../vldrhq_gather_shifted_offset_z_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 14 + 45 files changed, 1610 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4d4f9b1..657683d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,125 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vld1q_s8): Define macro. + (vld1q_s32): Likewise. + (vld1q_s16): Likewise. + (vld1q_u8): Likewise. + (vld1q_u32): Likewise. + (vld1q_u16): Likewise. + (vldrhq_gather_offset_s32): Likewise. + (vldrhq_gather_offset_s16): Likewise. + (vldrhq_gather_offset_u32): Likewise. + (vldrhq_gather_offset_u16): Likewise. + (vldrhq_gather_offset_z_s32): Likewise. + (vldrhq_gather_offset_z_s16): Likewise. + (vldrhq_gather_offset_z_u32): Likewise. + (vldrhq_gather_offset_z_u16): Likewise. + (vldrhq_gather_shifted_offset_s32): Likewise. + (vldrhq_gather_shifted_offset_s16): Likewise. + (vldrhq_gather_shifted_offset_u32): Likewise. + (vldrhq_gather_shifted_offset_u16): Likewise. + (vldrhq_gather_shifted_offset_z_s32): Likewise. + (vldrhq_gather_shifted_offset_z_s16): Likewise. + (vldrhq_gather_shifted_offset_z_u32): Likewise. + (vldrhq_gather_shifted_offset_z_u16): Likewise. + (vldrhq_s32): Likewise. + (vldrhq_s16): Likewise. + (vldrhq_u32): Likewise. + (vldrhq_u16): Likewise. + (vldrhq_z_s32): Likewise. + (vldrhq_z_s16): Likewise. + (vldrhq_z_u32): Likewise. + (vldrhq_z_u16): Likewise. + (vldrwq_s32): Likewise. + (vldrwq_u32): Likewise. + (vldrwq_z_s32): Likewise. + (vldrwq_z_u32): Likewise. + (vld1q_f32): Likewise. + (vld1q_f16): Likewise. + (vldrhq_f16): Likewise. + (vldrhq_z_f16): Likewise. + (vldrwq_f32): Likewise. + (vldrwq_z_f32): Likewise. + (__arm_vld1q_s8): Define intrinsic. + (__arm_vld1q_s32): Likewise. + (__arm_vld1q_s16): Likewise. + (__arm_vld1q_u8): Likewise. + (__arm_vld1q_u32): Likewise. + (__arm_vld1q_u16): Likewise. + (__arm_vldrhq_gather_offset_s32): Likewise. + (__arm_vldrhq_gather_offset_s16): Likewise. + (__arm_vldrhq_gather_offset_u32): Likewise. + (__arm_vldrhq_gather_offset_u16): Likewise. + (__arm_vldrhq_gather_offset_z_s32): Likewise. + (__arm_vldrhq_gather_offset_z_s16): Likewise. + (__arm_vldrhq_gather_offset_z_u32): Likewise. + (__arm_vldrhq_gather_offset_z_u16): Likewise. + (__arm_vldrhq_gather_shifted_offset_s32): Likewise. + (__arm_vldrhq_gather_shifted_offset_s16): Likewise. + (__arm_vldrhq_gather_shifted_offset_u32): Likewise. + (__arm_vldrhq_gather_shifted_offset_u16): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. + (__arm_vldrhq_s32): Likewise. + (__arm_vldrhq_s16): Likewise. + (__arm_vldrhq_u32): Likewise. + (__arm_vldrhq_u16): Likewise. + (__arm_vldrhq_z_s32): Likewise. + (__arm_vldrhq_z_s16): Likewise. + (__arm_vldrhq_z_u32): Likewise. + (__arm_vldrhq_z_u16): Likewise. + (__arm_vldrwq_s32): Likewise. + (__arm_vldrwq_u32): Likewise. + (__arm_vldrwq_z_s32): Likewise. + (__arm_vldrwq_z_u32): Likewise. + (__arm_vld1q_f32): Likewise. + (__arm_vld1q_f16): Likewise. + (__arm_vldrwq_f32): Likewise. + (__arm_vldrwq_z_f32): Likewise. + (__arm_vldrhq_z_f16): Likewise. + (__arm_vldrhq_f16): Likewise. + (vld1q): Define polymorphic variant. + (vldrhq_gather_offset): Likewise. + (vldrhq_gather_offset_z): Likewise. + (vldrhq_gather_shifted_offset): Likewise. + (vldrhq_gather_shifted_offset_z): Likewise. + * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. + (LDRS): Likewise. + (LDRU_Z): Likewise. + (LDRS_Z): Likewise. + (LDRGU_Z): Likewise. + (LDRGU): Likewise. + (LDRGS_Z): Likewise. + (LDRGS): Likewise. + * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. + (V_sz_elem1): Likewise. + (VLD1Q): Define iterator. + (VLDRHGOQ): Likewise. + (VLDRHGSOQ): Likewise. + (VLDRHQ): Likewise. + (VLDRWQ): Likewise. + (mve_vldrhq_fv8hf): Define RTL pattern. + (mve_vldrhq_gather_offset_): Likewise. + (mve_vldrhq_gather_offset_z_): Likewise. + (mve_vldrhq_gather_shifted_offset_): Likewise. + (mve_vldrhq_gather_shifted_offset_z_): Likewise. + (mve_vldrhq_): Likewise. + (mve_vldrhq_z_fv8hf): Likewise. + (mve_vldrhq_z_): Likewise. + (mve_vldrwq_fv4sf): Likewise. + (mve_vldrwq_v4si): Likewise. + (mve_vldrwq_z_fv4sf): Likewise. + (mve_vldrwq_z_v4si): Likewise. + (mve_vld1q_f): Define RTL expand pattern. + (mve_vld1q_): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 4570a0b..9991e25 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1758,6 +1758,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p) #define vldrwq_gather_base_z_u32(__addr, __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr, __offset, __p) #define vldrwq_gather_base_z_s32(__addr, __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr, __offset, __p) +#define vld1q_s8(__base) __arm_vld1q_s8(__base) +#define vld1q_s32(__base) __arm_vld1q_s32(__base) +#define vld1q_s16(__base) __arm_vld1q_s16(__base) +#define vld1q_u8(__base) __arm_vld1q_u8(__base) +#define vld1q_u32(__base) __arm_vld1q_u32(__base) +#define vld1q_u16(__base) __arm_vld1q_u16(__base) +#define vldrhq_gather_offset_s32(__base, __offset) __arm_vldrhq_gather_offset_s32(__base, __offset) +#define vldrhq_gather_offset_s16(__base, __offset) __arm_vldrhq_gather_offset_s16(__base, __offset) +#define vldrhq_gather_offset_u32(__base, __offset) __arm_vldrhq_gather_offset_u32(__base, __offset) +#define vldrhq_gather_offset_u16(__base, __offset) __arm_vldrhq_gather_offset_u16(__base, __offset) +#define vldrhq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s32(__base, __offset, __p) +#define vldrhq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s16(__base, __offset, __p) +#define vldrhq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u32(__base, __offset, __p) +#define vldrhq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u16(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_s32(__base, __offset) __arm_vldrhq_gather_shifted_offset_s32(__base, __offset) +#define vldrhq_gather_shifted_offset_s16(__base, __offset) __arm_vldrhq_gather_shifted_offset_s16(__base, __offset) +#define vldrhq_gather_shifted_offset_u32(__base, __offset) __arm_vldrhq_gather_shifted_offset_u32(__base, __offset) +#define vldrhq_gather_shifted_offset_u16(__base, __offset) __arm_vldrhq_gather_shifted_offset_u16(__base, __offset) +#define vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p) +#define vldrhq_s32(__base) __arm_vldrhq_s32(__base) +#define vldrhq_s16(__base) __arm_vldrhq_s16(__base) +#define vldrhq_u32(__base) __arm_vldrhq_u32(__base) +#define vldrhq_u16(__base) __arm_vldrhq_u16(__base) +#define vldrhq_z_s32(__base, __p) __arm_vldrhq_z_s32(__base, __p) +#define vldrhq_z_s16(__base, __p) __arm_vldrhq_z_s16(__base, __p) +#define vldrhq_z_u32(__base, __p) __arm_vldrhq_z_u32(__base, __p) +#define vldrhq_z_u16(__base, __p) __arm_vldrhq_z_u16(__base, __p) +#define vldrwq_s32(__base) __arm_vldrwq_s32(__base) +#define vldrwq_u32(__base) __arm_vldrwq_u32(__base) +#define vldrwq_z_s32(__base, __p) __arm_vldrwq_z_s32(__base, __p) +#define vldrwq_z_u32(__base, __p) __arm_vldrwq_z_u32(__base, __p) +#define vld1q_f32(__base) __arm_vld1q_f32(__base) +#define vld1q_f16(__base) __arm_vld1q_f16(__base) +#define vldrhq_f16(__base) __arm_vldrhq_f16(__base) +#define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p) +#define vldrwq_f32(__base) __arm_vldrwq_f32(__base) +#define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p) #endif __extension__ extern __inline void @@ -11443,6 +11483,245 @@ __arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred1 return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s8 (int8_t const * __base) +{ + return __builtin_mve_vld1q_sv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s32 (int32_t const * __base) +{ + return __builtin_mve_vld1q_sv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s16 (int16_t const * __base) +{ + return __builtin_mve_vld1q_sv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u8 (uint8_t const * __base) +{ + return __builtin_mve_vld1q_uv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u32 (uint32_t const * __base) +{ + return __builtin_mve_vld1q_uv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u16 (uint16_t const * __base) +{ + return __builtin_mve_vld1q_uv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_s32 (int16_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_sv4si ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_s16 (int16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_sv8hi ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_u32 (uint16_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_uv4si ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_u16 (uint16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_uv8hi ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_s32 (int16_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_sv4si ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_s16 (int16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_sv8hi ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_u32 (uint16_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_uv4si ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_u16 (uint16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_uv8hi ((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_s32 (int16_t const * __base) +{ + return __builtin_mve_vldrhq_sv4si ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_s16 (int16_t const * __base) +{ + return __builtin_mve_vldrhq_sv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_u32 (uint16_t const * __base) +{ + return __builtin_mve_vldrhq_uv4si ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_u16 (uint16_t const * __base) +{ + return __builtin_mve_vldrhq_uv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_s32 (int16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_sv4si ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_s16 (int16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_sv8hi ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_u32 (uint16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_uv4si ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_u16 (uint16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_uv8hi ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_s32 (int32_t const * __base) +{ + return __builtin_mve_vldrwq_sv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_u32 (uint32_t const * __base) +{ + return __builtin_mve_vldrwq_uv4si ((__builtin_neon_si *) __base); +} + + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_s32 (int32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_sv4si ((__builtin_neon_si *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -13585,6 +13864,47 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); } +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f32 (float32_t const * __base) +{ + return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f16 (float16_t const * __base) +{ + return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_f32 (float32_t const * __base) +{ + return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_f16 (float16_t const * __base) +{ + return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base); +} #endif enum { @@ -16052,6 +16372,18 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) +#define vld1q(p0) __arm_vld1q(p0) +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));}) + #else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -18148,6 +18480,52 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) +#define vld1q(p0) __arm_vld1q(p0) +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)));}) + +#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1) +#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vldrhq_gather_offset_z(p0,p1,p2) __arm_vldrhq_gather_offset_z(p0,p1,p2) +#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vldrhq_gather_shifted_offset(p0,p1) __arm_vldrhq_gather_shifted_offset(p0,p1) +#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vldrhq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) +#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #endif /* MVE Integer. */ #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 0f466e4..bafc953 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -709,3 +709,26 @@ VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si) VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si) VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si) VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si) +VAR3 (LDRU, vld1q_u, v16qi, v8hi, v4si) +VAR3 (LDRS, vld1q_s, v16qi, v8hi, v4si) +VAR2 (LDRU_Z, vldrhq_z_u, v8hi, v4si) +VAR2 (LDRU, vldrhq_u, v8hi, v4si) +VAR2 (LDRS_Z, vldrhq_z_s, v8hi, v4si) +VAR2 (LDRS, vldrhq_s, v8hi, v4si) +VAR2 (LDRS, vld1q_f, v8hf, v4sf) +VAR2 (LDRGU_Z, vldrhq_gather_shifted_offset_z_u, v8hi, v4si) +VAR2 (LDRGU_Z, vldrhq_gather_offset_z_u, v8hi, v4si) +VAR2 (LDRGU, vldrhq_gather_shifted_offset_u, v8hi, v4si) +VAR2 (LDRGU, vldrhq_gather_offset_u, v8hi, v4si) +VAR2 (LDRGS_Z, vldrhq_gather_shifted_offset_z_s, v8hi, v4si) +VAR2 (LDRGS_Z, vldrhq_gather_offset_z_s, v8hi, v4si) +VAR2 (LDRGS, vldrhq_gather_shifted_offset_s, v8hi, v4si) +VAR2 (LDRGS, vldrhq_gather_offset_s, v8hi, v4si) +VAR1 (LDRS, vldrhq_f, v8hf) +VAR1 (LDRS_Z, vldrhq_z_f, v8hf) +VAR1 (LDRS, vldrwq_f, v4sf) +VAR1 (LDRS, vldrwq_s, v4si) +VAR1 (LDRU, vldrwq_u, v4si) +VAR1 (LDRS_Z, vldrwq_z_f, v4sf) +VAR1 (LDRS_Z, vldrwq_z_s, v4si) +VAR1 (LDRU_Z, vldrwq_z_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 03a90ab..89ff2e2 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -26,6 +26,7 @@ (define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) +(define_mode_iterator MVE_6 [V8HI V4SI]) (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F @@ -193,10 +194,13 @@ VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S - VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U]) + VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U + VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S + VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U + VLDRWQ_F VLDRWQ_S VLDRWQ_U]) -(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") - (V8HF "V8HI") (V4SF "V4SI")]) +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") + (V4SF "V4SI")]) (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") @@ -348,7 +352,11 @@ (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u") (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s") - (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")]) + (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u") + (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s") + (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u") + (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s") + (VLDRWQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -362,10 +370,12 @@ (V4SI "mve_imm_31")]) (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")]) (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")]) - (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) +(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")]) +(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h") + (V4SF "w")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -575,6 +585,11 @@ (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U]) (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U]) +(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U]) +(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U]) +(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U]) +(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U]) +(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -8208,3 +8223,276 @@ return ""; } [(set_attr "length" "8")]) + +;; +;; [vldrhq_f] +;; +(define_insn "mve_vldrhq_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")] + VLDRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vldrh.f16\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] +;; +(define_insn "mve_vldrhq_gather_offset_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VLDRHGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + if (!strcmp ("","s") && == 16) + output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vldrh.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] +;; +(define_insn "mve_vldrhq_gather_offset_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up") + ]VLDRHGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + if (!strcmp ("","s") && == 16) + output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VLDRHGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + if (!strcmp ("","s") && == 16) + output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops); + else + output_asm_insn ("vldrh.\t%q0, [%m1, %q2, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up") + ]VLDRHGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + if (!strcmp ("","s") && == 16) + output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops); + else + output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; +;; [vldrhq_s, vldrhq_u] +;; +(define_insn "mve_vldrhq_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")] + VLDRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vldrh.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_z_f] +;; +(define_insn "mve_vldrhq_z_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_z_s vldrhq_z_u] +;; +(define_insn "mve_vldrhq_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vpst\n\tvldrht.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_f] +;; +(define_insn "mve_vldrwq_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")] + VLDRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vldrw.f32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_s vldrwq_u] +;; +(define_insn "mve_vldrwq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")] + VLDRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vldrw.32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_z_f] +;; +(define_insn "mve_vldrwq_z_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_z_s vldrwq_z_u] +;; +(define_insn "mve_vldrwq_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = operands[1]; + output_asm_insn ("vpst\n\tvldrwt.32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vld1q_f" + [(match_operand:MVE_0 0 "s_register_operand") + (unspec:MVE_0 [(match_operand: 1 "memory_operand")] VLD1Q_F) + ] + "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" +{ + emit_insn (gen_mve_vldrq_f(operands[0],operands[1])); + DONE; +}) + +(define_expand "mve_vld1q_" + [(match_operand:MVE_2 0 "s_register_operand") + (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q) + ] + "TARGET_HAVE_MVE" +{ + emit_insn (gen_mve_vldrq_(operands[0],operands[1])); + DONE; +}) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 451f0ee..a86d0e6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,51 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c new file mode 100644 index 0000000..91e39f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base) +{ + return vld1q_f16 (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ + +float16x8_t +foo1 (float16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c new file mode 100644 index 0000000..0ef33ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base) +{ + return vld1q_f32 (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ + +float32x4_t +foo1 (float32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c new file mode 100644 index 0000000..adf2f5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base) +{ + return vld1q_s16 (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ + +int16x8_t +foo1 (int16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c new file mode 100644 index 0000000..94df0b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base) +{ + return vld1q_s32 (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ + +int32x4_t +foo1 (int32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c new file mode 100644 index 0000000..9a8b304 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base) +{ + return vld1q_s8 (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ + +int8x16_t +foo1 (int8_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c new file mode 100644 index 0000000..4c5916b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base) +{ + return vld1q_u16 (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c new file mode 100644 index 0000000..8f4d521 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base) +{ + return vld1q_u32 (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c new file mode 100644 index 0000000..3804394 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base) +{ + return vld1q_u8 (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c new file mode 100644 index 0000000..ef7b5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base) +{ + return vldrhq_f16 (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c new file mode 100644 index 0000000..72e5ae2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c new file mode 100644 index 0000000..14a850a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c new file mode 100644 index 0000000..6e8f881 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c new file mode 100644 index 0000000..5e18f63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c new file mode 100644 index 0000000..625a818 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c new file mode 100644 index 0000000..bb10468 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c new file mode 100644 index 0000000..8a69d05 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c new file mode 100644 index 0000000..f88dc5e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c new file mode 100644 index 0000000..b82323f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c new file mode 100644 index 0000000..15f496c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c new file mode 100644 index 0000000..ccf93d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c new file mode 100644 index 0000000..558893c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c new file mode 100644 index 0000000..c2f5429 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c new file mode 100644 index 0000000..2565592 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c new file mode 100644 index 0000000..3ade339 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c new file mode 100644 index 0000000..c37203b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c new file mode 100644 index 0000000..dd5b7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base) +{ + return vldrhq_s16 (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c new file mode 100644 index 0000000..ee3613c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base) +{ + return vldrhq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c new file mode 100644 index 0000000..460931f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base) +{ + return vldrhq_u16 (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c new file mode 100644 index 0000000..1cd04f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base) +{ + return vldrhq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c new file mode 100644 index 0000000..3ea1db7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_f16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c new file mode 100644 index 0000000..9a700ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c new file mode 100644 index 0000000..729b627 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c new file mode 100644 index 0000000..a511e3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c new file mode 100644 index 0000000..7b0a9a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c new file mode 100644 index 0000000..eea4571 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base) +{ + return vldrwq_f32 (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c new file mode 100644 index 0000000..4f18dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base) +{ + return vldrwq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c new file mode 100644 index 0000000..b3672e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base) +{ + return vldrwq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c new file mode 100644 index 0000000..0af5f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_f32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c new file mode 100644 index 0000000..a8589cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c new file mode 100644 index 0000000..d5fa5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ -- cgit v1.1 From 4cc23303bad126f844a14f88c344317e6cf4c3dc Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 18:58:48 +0000 Subject: [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word or double word from memory. This patch supports the following Remaining MVE ACLE load intrinsics which load an halfword, word or double word from memory. vldrdq_gather_base_s64, vldrdq_gather_base_u64, vldrdq_gather_base_z_s64, vldrdq_gather_base_z_u64, vldrdq_gather_offset_s64, vldrdq_gather_offset_u64, vldrdq_gather_offset_z_s64, vldrdq_gather_offset_z_u64, vldrdq_gather_shifted_offset_s64, vldrdq_gather_shifted_offset_u64, vldrdq_gather_shifted_offset_z_s64, vldrdq_gather_shifted_offset_z_u64, vldrhq_gather_offset_f16, vldrhq_gather_offset_z_f16, vldrhq_gather_shifted_offset_f16, vldrhq_gather_shifted_offset_z_f16, vldrwq_gather_base_f32, vldrwq_gather_base_z_f32, vldrwq_gather_offset_f32, vldrwq_gather_offset_s32, vldrwq_gather_offset_u32, vldrwq_gather_offset_z_f32, vldrwq_gather_offset_z_s32, vldrwq_gather_offset_z_u32, vldrwq_gather_shifted_offset_f32, vldrwq_gather_shifted_offset_s32, vldrwq_gather_shifted_offset_u32, vldrwq_gather_shifted_offset_z_f32, vldrwq_gather_shifted_offset_z_s32, vldrwq_gather_shifted_offset_z_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_): Likewise. (mve_vldrhq_gather_offset_z_): Likewise. (mve_vldrhq_gather_shifted_offset_): Likewise. (mve_vldrhq_gather_shifted_offset_z_): Likewise. (mve_vldrhq_): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vld1q_f): Define RTL expand pattern. (mve_vld1q_): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. --- gcc/ChangeLog | 119 ++++++ gcc/config/arm/arm_mve.h | 359 +++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 30 ++ gcc/config/arm/mve.md | 432 ++++++++++++++++++++- gcc/testsuite/ChangeLog | 45 +++ .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 21 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 21 + .../vldrdq_gather_shifted_offset_z_s64.c | 21 + .../vldrdq_gather_shifted_offset_z_u64.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 21 + .../vldrhq_gather_shifted_offset_z_f16.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 21 + .../vldrwq_gather_shifted_offset_z_f32.c | 21 + .../vldrwq_gather_shifted_offset_z_s32.c | 21 + .../vldrwq_gather_shifted_offset_z_u32.c | 21 + 35 files changed, 1565 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 657683d..2a29c2d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -121,6 +121,125 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vld1q_s8): Define macro. + (vld1q_s32): Likewise. + (vld1q_s16): Likewise. + (vld1q_u8): Likewise. + (vld1q_u32): Likewise. + (vld1q_u16): Likewise. + (vldrhq_gather_offset_s32): Likewise. + (vldrhq_gather_offset_s16): Likewise. + (vldrhq_gather_offset_u32): Likewise. + (vldrhq_gather_offset_u16): Likewise. + (vldrhq_gather_offset_z_s32): Likewise. + (vldrhq_gather_offset_z_s16): Likewise. + (vldrhq_gather_offset_z_u32): Likewise. + (vldrhq_gather_offset_z_u16): Likewise. + (vldrhq_gather_shifted_offset_s32): Likewise. + (vldrhq_gather_shifted_offset_s16): Likewise. + (vldrhq_gather_shifted_offset_u32): Likewise. + (vldrhq_gather_shifted_offset_u16): Likewise. + (vldrhq_gather_shifted_offset_z_s32): Likewise. + (vldrhq_gather_shifted_offset_z_s16): Likewise. + (vldrhq_gather_shifted_offset_z_u32): Likewise. + (vldrhq_gather_shifted_offset_z_u16): Likewise. + (vldrhq_s32): Likewise. + (vldrhq_s16): Likewise. + (vldrhq_u32): Likewise. + (vldrhq_u16): Likewise. + (vldrhq_z_s32): Likewise. + (vldrhq_z_s16): Likewise. + (vldrhq_z_u32): Likewise. + (vldrhq_z_u16): Likewise. + (vldrwq_s32): Likewise. + (vldrwq_u32): Likewise. + (vldrwq_z_s32): Likewise. + (vldrwq_z_u32): Likewise. + (vld1q_f32): Likewise. + (vld1q_f16): Likewise. + (vldrhq_f16): Likewise. + (vldrhq_z_f16): Likewise. + (vldrwq_f32): Likewise. + (vldrwq_z_f32): Likewise. + (__arm_vld1q_s8): Define intrinsic. + (__arm_vld1q_s32): Likewise. + (__arm_vld1q_s16): Likewise. + (__arm_vld1q_u8): Likewise. + (__arm_vld1q_u32): Likewise. + (__arm_vld1q_u16): Likewise. + (__arm_vldrhq_gather_offset_s32): Likewise. + (__arm_vldrhq_gather_offset_s16): Likewise. + (__arm_vldrhq_gather_offset_u32): Likewise. + (__arm_vldrhq_gather_offset_u16): Likewise. + (__arm_vldrhq_gather_offset_z_s32): Likewise. + (__arm_vldrhq_gather_offset_z_s16): Likewise. + (__arm_vldrhq_gather_offset_z_u32): Likewise. + (__arm_vldrhq_gather_offset_z_u16): Likewise. + (__arm_vldrhq_gather_shifted_offset_s32): Likewise. + (__arm_vldrhq_gather_shifted_offset_s16): Likewise. + (__arm_vldrhq_gather_shifted_offset_u32): Likewise. + (__arm_vldrhq_gather_shifted_offset_u16): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. + (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. + (__arm_vldrhq_s32): Likewise. + (__arm_vldrhq_s16): Likewise. + (__arm_vldrhq_u32): Likewise. + (__arm_vldrhq_u16): Likewise. + (__arm_vldrhq_z_s32): Likewise. + (__arm_vldrhq_z_s16): Likewise. + (__arm_vldrhq_z_u32): Likewise. + (__arm_vldrhq_z_u16): Likewise. + (__arm_vldrwq_s32): Likewise. + (__arm_vldrwq_u32): Likewise. + (__arm_vldrwq_z_s32): Likewise. + (__arm_vldrwq_z_u32): Likewise. + (__arm_vld1q_f32): Likewise. + (__arm_vld1q_f16): Likewise. + (__arm_vldrwq_f32): Likewise. + (__arm_vldrwq_z_f32): Likewise. + (__arm_vldrhq_z_f16): Likewise. + (__arm_vldrhq_f16): Likewise. + (vld1q): Define polymorphic variant. + (vldrhq_gather_offset): Likewise. + (vldrhq_gather_offset_z): Likewise. + (vldrhq_gather_shifted_offset): Likewise. + (vldrhq_gather_shifted_offset_z): Likewise. + * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. + (LDRS): Likewise. + (LDRU_Z): Likewise. + (LDRS_Z): Likewise. + (LDRGU_Z): Likewise. + (LDRGU): Likewise. + (LDRGS_Z): Likewise. + (LDRGS): Likewise. + * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. + (V_sz_elem1): Likewise. + (VLD1Q): Define iterator. + (VLDRHGOQ): Likewise. + (VLDRHGSOQ): Likewise. + (VLDRHQ): Likewise. + (VLDRWQ): Likewise. + (mve_vldrhq_fv8hf): Define RTL pattern. + (mve_vldrhq_gather_offset_): Likewise. + (mve_vldrhq_gather_offset_z_): Likewise. + (mve_vldrhq_gather_shifted_offset_): Likewise. + (mve_vldrhq_gather_shifted_offset_z_): Likewise. + (mve_vldrhq_): Likewise. + (mve_vldrhq_z_fv8hf): Likewise. + (mve_vldrhq_z_): Likewise. + (mve_vldrwq_fv4sf): Likewise. + (mve_vldrwq_v4si): Likewise. + (mve_vldrwq_z_fv4sf): Likewise. + (mve_vldrwq_z_v4si): Likewise. + (mve_vld1q_f): Define RTL expand pattern. + (mve_vld1q_): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 9991e25..89cdc5b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1798,6 +1798,36 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p) #define vldrwq_f32(__base) __arm_vldrwq_f32(__base) #define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p) +#define vldrdq_gather_base_s64(__addr, __offset) __arm_vldrdq_gather_base_s64(__addr, __offset) +#define vldrdq_gather_base_u64(__addr, __offset) __arm_vldrdq_gather_base_u64(__addr, __offset) +#define vldrdq_gather_base_z_s64(__addr, __offset, __p) __arm_vldrdq_gather_base_z_s64(__addr, __offset, __p) +#define vldrdq_gather_base_z_u64(__addr, __offset, __p) __arm_vldrdq_gather_base_z_u64(__addr, __offset, __p) +#define vldrdq_gather_offset_s64(__base, __offset) __arm_vldrdq_gather_offset_s64(__base, __offset) +#define vldrdq_gather_offset_u64(__base, __offset) __arm_vldrdq_gather_offset_u64(__base, __offset) +#define vldrdq_gather_offset_z_s64(__base, __offset, __p) __arm_vldrdq_gather_offset_z_s64(__base, __offset, __p) +#define vldrdq_gather_offset_z_u64(__base, __offset, __p) __arm_vldrdq_gather_offset_z_u64(__base, __offset, __p) +#define vldrdq_gather_shifted_offset_s64(__base, __offset) __arm_vldrdq_gather_shifted_offset_s64(__base, __offset) +#define vldrdq_gather_shifted_offset_u64(__base, __offset) __arm_vldrdq_gather_shifted_offset_u64(__base, __offset) +#define vldrdq_gather_shifted_offset_z_s64(__base, __offset, __p) __arm_vldrdq_gather_shifted_offset_z_s64(__base, __offset, __p) +#define vldrdq_gather_shifted_offset_z_u64(__base, __offset, __p) __arm_vldrdq_gather_shifted_offset_z_u64(__base, __offset, __p) +#define vldrhq_gather_offset_f16(__base, __offset) __arm_vldrhq_gather_offset_f16(__base, __offset) +#define vldrhq_gather_offset_z_f16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_f16(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_f16(__base, __offset) __arm_vldrhq_gather_shifted_offset_f16(__base, __offset) +#define vldrhq_gather_shifted_offset_z_f16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_f16(__base, __offset, __p) +#define vldrwq_gather_base_f32(__addr, __offset) __arm_vldrwq_gather_base_f32(__addr, __offset) +#define vldrwq_gather_base_z_f32(__addr, __offset, __p) __arm_vldrwq_gather_base_z_f32(__addr, __offset, __p) +#define vldrwq_gather_offset_f32(__base, __offset) __arm_vldrwq_gather_offset_f32(__base, __offset) +#define vldrwq_gather_offset_s32(__base, __offset) __arm_vldrwq_gather_offset_s32(__base, __offset) +#define vldrwq_gather_offset_u32(__base, __offset) __arm_vldrwq_gather_offset_u32(__base, __offset) +#define vldrwq_gather_offset_z_f32(__base, __offset, __p) __arm_vldrwq_gather_offset_z_f32(__base, __offset, __p) +#define vldrwq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrwq_gather_offset_z_s32(__base, __offset, __p) +#define vldrwq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrwq_gather_offset_z_u32(__base, __offset, __p) +#define vldrwq_gather_shifted_offset_f32(__base, __offset) __arm_vldrwq_gather_shifted_offset_f32(__base, __offset) +#define vldrwq_gather_shifted_offset_s32(__base, __offset) __arm_vldrwq_gather_shifted_offset_s32(__base, __offset) +#define vldrwq_gather_shifted_offset_u32(__base, __offset) __arm_vldrwq_gather_shifted_offset_u32(__base, __offset) +#define vldrwq_gather_shifted_offset_z_f32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_f32(__base, __offset, __p) +#define vldrwq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_s32(__base, __offset, __p) +#define vldrwq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_u32(__base, __offset, __p) #endif __extension__ extern __inline void @@ -11722,6 +11752,147 @@ __arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p) return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p); } +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_s64 (uint64x2_t __addr, const int __offset) +{ + return __builtin_mve_vldrdq_gather_base_sv2di (__addr, __offset); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_u64 (uint64x2_t __addr, const int __offset) +{ + return __builtin_mve_vldrdq_gather_base_uv2di (__addr, __offset); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_z_s64 (uint64x2_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_base_z_sv2di (__addr, __offset, __p); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_z_u64 (uint64x2_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_base_z_uv2di (__addr, __offset, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_offset_s64 (int64_t const * __base, uint64x2_t __offset) +{ + return __builtin_mve_vldrdq_gather_offset_sv2di ((__builtin_neon_di *) __base, __offset); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_offset_u64 (uint64_t const * __base, uint64x2_t __offset) +{ + return __builtin_mve_vldrdq_gather_offset_uv2di ((__builtin_neon_di *) __base, __offset); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_offset_z_s64 (int64_t const * __base, uint64x2_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_offset_z_sv2di ((__builtin_neon_di *) __base, __offset, __p); +} + + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_offset_z_u64 (uint64_t const * __base, uint64x2_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_offset_z_uv2di ((__builtin_neon_di *) __base, __offset, __p); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_shifted_offset_s64 (int64_t const * __base, uint64x2_t __offset) +{ + return __builtin_mve_vldrdq_gather_shifted_offset_sv2di ((__builtin_neon_di *) __base, __offset); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_shifted_offset_u64 (uint64_t const * __base, uint64x2_t __offset) +{ + return __builtin_mve_vldrdq_gather_shifted_offset_uv2di ((__builtin_neon_di *) __base, __offset); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_shifted_offset_z_s64 (int64_t const * __base, uint64x2_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_shifted_offset_z_sv2di ((__builtin_neon_di *) __base, __offset, __p); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_shifted_offset_z_u64 (uint64_t const * __base, uint64x2_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrdq_gather_shifted_offset_z_uv2di ((__builtin_neon_di *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_s32 (int32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_offset_sv4si ((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_u32 (uint32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_offset_uv4si ((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_z_s32 (int32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_offset_z_sv4si ((__builtin_neon_si *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_z_u32 (uint32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_offset_z_uv4si ((__builtin_neon_si *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_s32 (int32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_sv4si ((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_u32 (uint32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_uv4si ((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_z_s32 (int32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_z_sv4si ((__builtin_neon_si *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_z_u32 (uint32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_z_uv4si ((__builtin_neon_si *) __base, __offset, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -13905,6 +14076,77 @@ __arm_vldrhq_f16 (float16_t const * __base) { return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base); } + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_f16 (float16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_fv8hf((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_fv8hf((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_f16 (float16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_fv8hf (__base, __offset); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_fv8hf (__base, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_f32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_fv4sf (__addr, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_f32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_fv4sf (__addr, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_f32 (float32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_offset_fv4sf((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_offset_z_fv4sf((__builtin_neon_si *) __base, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_f32 (float32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_fv4sf (__base, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p); +} + #endif enum { @@ -16384,6 +16626,74 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));}) +#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1) +#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce(__p0, float16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + +#define vldrhq_gather_offset_z(p0,p1,p2) __arm_vldrhq_gather_offset_z(p0,p1,p2) +#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce(__p0, float16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vldrhq_gather_shifted_offset(p0,p1) __arm_vldrhq_gather_shifted_offset(p0,p1) +#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce(__p0, float16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + +#define vldrhq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) +#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce(__p0, float16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vldrwq_gather_offset(p0,p1) __arm_vldrwq_gather_offset(p0,p1) +#define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1));}) + +#define vldrwq_gather_offset_z(p0,p1,p2) __arm_vldrwq_gather_offset_z(p0,p1,p2) +#define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1, p2));}) + +#define vldrwq_gather_shifted_offset(p0,p1) __arm_vldrwq_gather_shifted_offset(p0,p1) +#define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1));}) + +#define vldrwq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) +#define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1, p2));}) + #else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -18526,8 +18836,57 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) +#define vldrwq_gather_offset(p0,p1) __arm_vldrwq_gather_offset(p0,p1) +#define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1));}) + +#define vldrwq_gather_offset_z(p0,p1,p2) __arm_vldrwq_gather_offset_z(p0,p1,p2) +#define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2));}) + +#define vldrwq_gather_shifted_offset(p0,p1) __arm_vldrwq_gather_shifted_offset(p0,p1) +#define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1));}) + +#define vldrwq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) +#define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2));}) + #endif /* MVE Integer. */ +#define vldrdq_gather_offset(p0,p1) __arm_vldrdq_gather_offset(p0,p1) +#define __arm_vldrdq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int64_t_const_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce(__p0, int64_t const *), p1), \ + int (*)[__ARM_mve_type_uint64_t_const_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce(__p0, uint64_t const *), p1));}) + +#define vldrdq_gather_offset_z(p0,p1,p2) __arm_vldrdq_gather_offset_z(p0,p1,p2) +#define __arm_vldrdq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int64_t_const_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce(__p0, int64_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint64_t_const_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce(__p0, uint64_t const *), p1, p2));}) + +#define vldrdq_gather_shifted_offset(p0,p1) __arm_vldrdq_gather_shifted_offset(p0,p1) +#define __arm_vldrdq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t const *), p1), \ + int (*)[__ARM_mve_type_uint64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t const *), p1));}) + +#define vldrdq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) +#define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce(__p0, int64_t const *), p1, p2), \ + int (*)[__ARM_mve_type_uint64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce(__p0, uint64_t const *), p1, p2));}) + + #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2) #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index bafc953..fc30361 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -732,3 +732,33 @@ VAR1 (LDRU, vldrwq_u, v4si) VAR1 (LDRS_Z, vldrwq_z_f, v4sf) VAR1 (LDRS_Z, vldrwq_z_s, v4si) VAR1 (LDRU_Z, vldrwq_z_u, v4si) +VAR1 (LDRGBS, vldrdq_gather_base_s, v2di) +VAR1 (LDRGBS, vldrwq_gather_base_f, v4sf) +VAR1 (LDRGBS_Z, vldrdq_gather_base_z_s, v2di) +VAR1 (LDRGBS_Z, vldrwq_gather_base_z_f, v4sf) +VAR1 (LDRGBU, vldrdq_gather_base_u, v2di) +VAR1 (LDRGBU_Z, vldrdq_gather_base_z_u, v2di) +VAR1 (LDRGS, vldrdq_gather_offset_s, v2di) +VAR1 (LDRGS, vldrdq_gather_shifted_offset_s, v2di) +VAR1 (LDRGS, vldrhq_gather_offset_f, v8hf) +VAR1 (LDRGS, vldrhq_gather_shifted_offset_f, v8hf) +VAR1 (LDRGS, vldrwq_gather_offset_f, v4sf) +VAR1 (LDRGS, vldrwq_gather_offset_s, v4si) +VAR1 (LDRGS, vldrwq_gather_shifted_offset_f, v4sf) +VAR1 (LDRGS, vldrwq_gather_shifted_offset_s, v4si) +VAR1 (LDRGS_Z, vldrdq_gather_offset_z_s, v2di) +VAR1 (LDRGS_Z, vldrdq_gather_shifted_offset_z_s, v2di) +VAR1 (LDRGS_Z, vldrhq_gather_offset_z_f, v8hf) +VAR1 (LDRGS_Z, vldrhq_gather_shifted_offset_z_f, v8hf) +VAR1 (LDRGS_Z, vldrwq_gather_offset_z_f, v4sf) +VAR1 (LDRGS_Z, vldrwq_gather_offset_z_s, v4si) +VAR1 (LDRGS_Z, vldrwq_gather_shifted_offset_z_f, v4sf) +VAR1 (LDRGS_Z, vldrwq_gather_shifted_offset_z_s, v4si) +VAR1 (LDRGU, vldrdq_gather_offset_u, v2di) +VAR1 (LDRGU, vldrdq_gather_shifted_offset_u, v2di) +VAR1 (LDRGU, vldrwq_gather_offset_u, v4si) +VAR1 (LDRGU, vldrwq_gather_shifted_offset_u, v4si) +VAR1 (LDRGU_Z, vldrdq_gather_offset_z_u, v2di) +VAR1 (LDRGU_Z, vldrdq_gather_shifted_offset_z_u, v2di) +VAR1 (LDRGU_Z, vldrwq_gather_offset_z_u, v4si) +VAR1 (LDRGU_Z, vldrwq_gather_shifted_offset_z_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 89ff2e2..b0c0b87 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -197,7 +197,11 @@ VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U - VLDRWQ_F VLDRWQ_S VLDRWQ_U]) + VLDRWQ_F VLDRWQ_S VLDRWQ_U VLDRDQGB_S VLDRDQGB_U + VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U + VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F + VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S + VLDRWQGSO_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -356,7 +360,10 @@ (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s") (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u") (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s") - (VLDRWQ_U "u")]) + (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u") + (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s") + (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u") + (VLDRWQGSO_S "s") (VLDRWQGSO_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -590,6 +597,11 @@ (define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U]) (define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U]) (define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U]) +(define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U]) +(define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U]) +(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U]) +(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U]) +(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -8496,3 +8508,419 @@ emit_insn (gen_mve_vldrq_(operands[0],operands[1])); DONE; }) + +;; +;; [vldrdq_gather_base_s vldrdq_gather_base_u] +;; +(define_insn "mve_vldrdq_gather_base_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VLDRDGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u] +;; +(define_insn "mve_vldrdq_gather_base_z_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRDGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrdq_gather_offset_s vldrdq_gather_offset_u] +;; +(define_insn "mve_vldrdq_gather_offset_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") + (match_operand:V2DI 2 "s_register_operand" "w")] + VLDRDGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u] +;; +(define_insn "mve_vldrdq_gather_offset_z_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRDGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u] +;; +(define_insn "mve_vldrdq_gather_shifted_offset_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") + (match_operand:V2DI 2 "s_register_operand" "w")] + VLDRDGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u] +;; +(define_insn "mve_vldrdq_gather_shifted_offset_z_v2di" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRDGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_gather_offset_f] +;; +(define_insn "mve_vldrhq_gather_offset_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=&w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:V8HI 2 "s_register_operand" "w")] + VLDRHQGO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_offset_z_f] +;; +(define_insn "mve_vldrhq_gather_offset_z_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=&w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:V8HI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRHQGO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_gather_shifted_offset_f] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=&w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:V8HI 2 "s_register_operand" "w")] + VLDRHQGSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_shifted_offset_z_f] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=&w") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:V8HI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRHQGSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_base_f] +;; +(define_insn "mve_vldrwq_gather_base_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VLDRWQGB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_base_z_f] +;; +(define_insn "mve_vldrwq_gather_base_z_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWQGB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_offset_f] +;; +(define_insn "mve_vldrwq_gather_offset_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w")] + VLDRWQGO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_offset_s vldrwq_gather_offset_u] +;; +(define_insn "mve_vldrwq_gather_offset_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w")] + VLDRWGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_offset_z_f] +;; +(define_insn "mve_vldrwq_gather_offset_z_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWQGO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u] +;; +(define_insn "mve_vldrwq_gather_offset_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_shifted_offset_f] +;; +(define_insn "mve_vldrwq_gather_shifted_offset_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w")] + VLDRWQGSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u] +;; +(define_insn "mve_vldrwq_gather_shifted_offset_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w")] + VLDRWGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_shifted_offset_z_f] +;; +(define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWQGSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u] +;; +(define_insn "mve_vldrwq_gather_shifted_offset_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + ops[3] = operands[3]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a86d0e6..3b689b1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -47,6 +47,51 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c new file mode 100644 index 0000000..0116d35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (uint64x2_t addr) +{ + return vldrdq_gather_base_s64 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c new file mode 100644 index 0000000..191e5de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t addr) +{ + return vldrdq_gather_base_u64 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c new file mode 100644 index 0000000..9193b41 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (uint64x2_t addr, mve_pred16_t p) +{ + return vldrdq_gather_base_z_s64 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c new file mode 100644 index 0000000..9f15675 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t addr, mve_pred16_t p) +{ + return vldrdq_gather_base_z_u64 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c new file mode 100644 index 0000000..00547a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_offset_s64 (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ + +int64x2_t +foo1 (int64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c new file mode 100644 index 0000000..af59f95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_offset_u64 (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ + +uint64x2_t +foo1 (uint64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c new file mode 100644 index 0000000..7818470 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_offset_z_s64 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ + +int64x2_t +foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c new file mode 100644 index 0000000..4409410 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_offset_z_u64 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ + +uint64x2_t +foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c new file mode 100644 index 0000000..6dac7c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_shifted_offset_s64 (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ + +int64x2_t +foo1 (int64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c new file mode 100644 index 0000000..b33efc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_shifted_offset_u64 (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ + +uint64x2_t +foo1 (uint64_t const * base, uint64x2_t offset) +{ + return vldrdq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c new file mode 100644 index 0000000..9a0572e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64x2_t +foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_shifted_offset_z_s64 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ + +int64x2_t +foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c new file mode 100644 index 0000000..50a2cd16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_shifted_offset_z_u64 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ + +uint64x2_t +foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) +{ + return vldrdq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c new file mode 100644 index 0000000..a915959 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset_f16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c new file mode 100644 index 0000000..fdc6762 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_f16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c new file mode 100644 index 0000000..ba9d0f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset_f16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c new file mode 100644 index 0000000..561669f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_f16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c new file mode 100644 index 0000000..b398bab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t addr) +{ + return vldrwq_gather_base_f32 (addr, 4); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c new file mode 100644 index 0000000..bc219c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t addr, mve_pred16_t p) +{ + return vldrwq_gather_base_z_f32 (addr, 4, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c new file mode 100644 index 0000000..2e3b94f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset_f32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +float32x4_t +foo1 (float32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c new file mode 100644 index 0000000..fe5d51c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +int32x4_t +foo1 (int32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c new file mode 100644 index 0000000..89ec398 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c new file mode 100644 index 0000000..c85a0c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z_f32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +float32x4_t +foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c new file mode 100644 index 0000000..e128b43 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +int32x4_t +foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c new file mode 100644 index 0000000..b183b9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c new file mode 100644 index 0000000..67a42f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset_f32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +float32x4_t +foo1 (float32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c new file mode 100644 index 0000000..283d0a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +int32x4_t +foo1 (int32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c new file mode 100644 index 0000000..4783fae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, uint32x4_t offset) +{ + return vldrwq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c new file mode 100644 index 0000000..c144385 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z_f32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +float32x4_t +foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c new file mode 100644 index 0000000..b537998 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +int32x4_t +foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c new file mode 100644 index 0000000..a3d4fde --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrwq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ -- cgit v1.1 From 5cad47e0f85e59e21a5df04d34d813a860ff42d4 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 19:08:29 +0000 Subject: [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory. This patch supports the following MVE ACLE store intrinsics which stores a byte, halfword, or word to memory. vst1q_f32, vst1q_f16, vst1q_s8, vst1q_s32, vst1q_s16, vst1q_u8, vst1q_u32, vst1q_u16, vstrhq_f16, vstrhq_scatter_offset_s32, vstrhq_scatter_offset_s16, vstrhq_scatter_offset_u32, vstrhq_scatter_offset_u16, vstrhq_scatter_offset_p_s32, vstrhq_scatter_offset_p_s16, vstrhq_scatter_offset_p_u32, vstrhq_scatter_offset_p_u16, vstrhq_scatter_shifted_offset_s32, vstrhq_scatter_shifted_offset_s16, vstrhq_scatter_shifted_offset_u32, vstrhq_scatter_shifted_offset_u16, vstrhq_scatter_shifted_offset_p_s32, vstrhq_scatter_shifted_offset_p_s16, vstrhq_scatter_shifted_offset_p_u32, vstrhq_scatter_shifted_offset_p_u16, vstrhq_s32, vstrhq_s16, vstrhq_u32, vstrhq_u16, vstrhq_p_f16, vstrhq_p_s32, vstrhq_p_s16, vstrhq_p_u32, vstrhq_p_u16, vstrwq_f32, vstrwq_s32, vstrwq_u32, vstrwq_p_f32, vstrwq_p_s32, vstrwq_p_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vst1q_f32): Define macro. (vst1q_f16): Likewise. (vst1q_s8): Likewise. (vst1q_s32): Likewise. (vst1q_s16): Likewise. (vst1q_u8): Likewise. (vst1q_u32): Likewise. (vst1q_u16): Likewise. (vstrhq_f16): Likewise. (vstrhq_scatter_offset_s32): Likewise. (vstrhq_scatter_offset_s16): Likewise. (vstrhq_scatter_offset_u32): Likewise. (vstrhq_scatter_offset_u16): Likewise. (vstrhq_scatter_offset_p_s32): Likewise. (vstrhq_scatter_offset_p_s16): Likewise. (vstrhq_scatter_offset_p_u32): Likewise. (vstrhq_scatter_offset_p_u16): Likewise. (vstrhq_scatter_shifted_offset_s32): Likewise. (vstrhq_scatter_shifted_offset_s16): Likewise. (vstrhq_scatter_shifted_offset_u32): Likewise. (vstrhq_scatter_shifted_offset_u16): Likewise. (vstrhq_scatter_shifted_offset_p_s32): Likewise. (vstrhq_scatter_shifted_offset_p_s16): Likewise. (vstrhq_scatter_shifted_offset_p_u32): Likewise. (vstrhq_scatter_shifted_offset_p_u16): Likewise. (vstrhq_s32): Likewise. (vstrhq_s16): Likewise. (vstrhq_u32): Likewise. (vstrhq_u16): Likewise. (vstrhq_p_f16): Likewise. (vstrhq_p_s32): Likewise. (vstrhq_p_s16): Likewise. (vstrhq_p_u32): Likewise. (vstrhq_p_u16): Likewise. (vstrwq_f32): Likewise. (vstrwq_s32): Likewise. (vstrwq_u32): Likewise. (vstrwq_p_f32): Likewise. (vstrwq_p_s32): Likewise. (vstrwq_p_u32): Likewise. (__arm_vst1q_s8): Define intrinsic. (__arm_vst1q_s32): Likewise. (__arm_vst1q_s16): Likewise. (__arm_vst1q_u8): Likewise. (__arm_vst1q_u32): Likewise. (__arm_vst1q_u16): Likewise. (__arm_vstrhq_scatter_offset_s32): Likewise. (__arm_vstrhq_scatter_offset_s16): Likewise. (__arm_vstrhq_scatter_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_u16): Likewise. (__arm_vstrhq_scatter_offset_p_s32): Likewise. (__arm_vstrhq_scatter_offset_p_s16): Likewise. (__arm_vstrhq_scatter_offset_p_u32): Likewise. (__arm_vstrhq_scatter_offset_p_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. (__arm_vstrhq_s32): Likewise. (__arm_vstrhq_s16): Likewise. (__arm_vstrhq_u32): Likewise. (__arm_vstrhq_u16): Likewise. (__arm_vstrhq_p_s32): Likewise. (__arm_vstrhq_p_s16): Likewise. (__arm_vstrhq_p_u32): Likewise. (__arm_vstrhq_p_u16): Likewise. (__arm_vstrwq_s32): Likewise. (__arm_vstrwq_u32): Likewise. (__arm_vstrwq_p_s32): Likewise. (__arm_vstrwq_p_u32): Likewise. (__arm_vstrwq_p_f32): Likewise. (__arm_vstrwq_f32): Likewise. (__arm_vst1q_f32): Likewise. (__arm_vst1q_f16): Likewise. (__arm_vstrhq_f16): Likewise. (__arm_vstrhq_p_f16): Likewise. (vst1q): Define polymorphic variant. (vstrhq): Likewise. (vstrhq_p): Likewise. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrwq_p): Likewise. (vstrwq): Likewise. * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. (STRS_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. (STRU): Likewise. (STRU_P): Likewise. * config/arm/mve.md (VST1Q): Define iterator. (VSTRHSOQ): Likewise. (VSTRHSSOQ): Likewise. (VSTRHQ): Likewise. (VSTRWQ): Likewise. (mve_vstrhq_fv8hf): Define RTL pattern. (mve_vstrhq_p_fv8hf): Likewise. (mve_vstrhq_p_): Likewise. (mve_vstrhq_scatter_offset_p_): Likewise. (mve_vstrhq_scatter_offset_): Likewise. (mve_vstrhq_scatter_shifted_offset_p_): Likewise. (mve_vstrhq_scatter_shifted_offset_): Likewise. (mve_vstrhq_): Likewise. (mve_vstrwq_fv4sf): Likewise. (mve_vstrwq_p_fv4sf): Likewise. (mve_vstrwq_p_v4si): Likewise. (mve_vstrwq_v4si): Likewise. (mve_vst1q_f): Define expand. (mve_vst1q_): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. --- gcc/ChangeLog | 121 +++++ gcc/config/arm/arm_mve.h | 497 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 23 + gcc/config/arm/mve.md | 276 +++++++++++- gcc/testsuite/ChangeLog | 53 +++ .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 5 +- .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 5 +- .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 5 +- .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 5 +- .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 5 +- .../vldrdq_gather_shifted_offset_z_s64.c | 5 +- .../vldrdq_gather_shifted_offset_z_u64.c | 5 +- .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 5 +- .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 5 +- .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 5 +- .../vldrhq_gather_shifted_offset_z_f16.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 5 +- .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 5 +- .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 5 +- .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 5 +- .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 5 +- .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 5 +- .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 5 +- .../vldrwq_gather_shifted_offset_z_f32.c | 5 +- .../vldrwq_gather_shifted_offset_z_s32.c | 5 +- .../vldrwq_gather_shifted_offset_z_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 22 + .../vstrhq_scatter_shifted_offset_p_s16.c | 22 + .../vstrhq_scatter_shifted_offset_p_s32.c | 22 + .../vstrhq_scatter_shifted_offset_p_u16.c | 22 + .../vstrhq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 22 + 75 files changed, 1938 insertions(+), 62 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2a29c2d..acea775 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,127 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vst1q_f32): Define macro. + (vst1q_f16): Likewise. + (vst1q_s8): Likewise. + (vst1q_s32): Likewise. + (vst1q_s16): Likewise. + (vst1q_u8): Likewise. + (vst1q_u32): Likewise. + (vst1q_u16): Likewise. + (vstrhq_f16): Likewise. + (vstrhq_scatter_offset_s32): Likewise. + (vstrhq_scatter_offset_s16): Likewise. + (vstrhq_scatter_offset_u32): Likewise. + (vstrhq_scatter_offset_u16): Likewise. + (vstrhq_scatter_offset_p_s32): Likewise. + (vstrhq_scatter_offset_p_s16): Likewise. + (vstrhq_scatter_offset_p_u32): Likewise. + (vstrhq_scatter_offset_p_u16): Likewise. + (vstrhq_scatter_shifted_offset_s32): Likewise. + (vstrhq_scatter_shifted_offset_s16): Likewise. + (vstrhq_scatter_shifted_offset_u32): Likewise. + (vstrhq_scatter_shifted_offset_u16): Likewise. + (vstrhq_scatter_shifted_offset_p_s32): Likewise. + (vstrhq_scatter_shifted_offset_p_s16): Likewise. + (vstrhq_scatter_shifted_offset_p_u32): Likewise. + (vstrhq_scatter_shifted_offset_p_u16): Likewise. + (vstrhq_s32): Likewise. + (vstrhq_s16): Likewise. + (vstrhq_u32): Likewise. + (vstrhq_u16): Likewise. + (vstrhq_p_f16): Likewise. + (vstrhq_p_s32): Likewise. + (vstrhq_p_s16): Likewise. + (vstrhq_p_u32): Likewise. + (vstrhq_p_u16): Likewise. + (vstrwq_f32): Likewise. + (vstrwq_s32): Likewise. + (vstrwq_u32): Likewise. + (vstrwq_p_f32): Likewise. + (vstrwq_p_s32): Likewise. + (vstrwq_p_u32): Likewise. + (__arm_vst1q_s8): Define intrinsic. + (__arm_vst1q_s32): Likewise. + (__arm_vst1q_s16): Likewise. + (__arm_vst1q_u8): Likewise. + (__arm_vst1q_u32): Likewise. + (__arm_vst1q_u16): Likewise. + (__arm_vstrhq_scatter_offset_s32): Likewise. + (__arm_vstrhq_scatter_offset_s16): Likewise. + (__arm_vstrhq_scatter_offset_u32): Likewise. + (__arm_vstrhq_scatter_offset_u16): Likewise. + (__arm_vstrhq_scatter_offset_p_s32): Likewise. + (__arm_vstrhq_scatter_offset_p_s16): Likewise. + (__arm_vstrhq_scatter_offset_p_u32): Likewise. + (__arm_vstrhq_scatter_offset_p_u16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. + (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. + (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. + (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. + (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. + (__arm_vstrhq_s32): Likewise. + (__arm_vstrhq_s16): Likewise. + (__arm_vstrhq_u32): Likewise. + (__arm_vstrhq_u16): Likewise. + (__arm_vstrhq_p_s32): Likewise. + (__arm_vstrhq_p_s16): Likewise. + (__arm_vstrhq_p_u32): Likewise. + (__arm_vstrhq_p_u16): Likewise. + (__arm_vstrwq_s32): Likewise. + (__arm_vstrwq_u32): Likewise. + (__arm_vstrwq_p_s32): Likewise. + (__arm_vstrwq_p_u32): Likewise. + (__arm_vstrwq_p_f32): Likewise. + (__arm_vstrwq_f32): Likewise. + (__arm_vst1q_f32): Likewise. + (__arm_vst1q_f16): Likewise. + (__arm_vstrhq_f16): Likewise. + (__arm_vstrhq_p_f16): Likewise. + (vst1q): Define polymorphic variant. + (vstrhq): Likewise. + (vstrhq_p): Likewise. + (vstrhq_scatter_offset_p): Likewise. + (vstrhq_scatter_offset): Likewise. + (vstrhq_scatter_shifted_offset_p): Likewise. + (vstrhq_scatter_shifted_offset): Likewise. + (vstrwq_p): Likewise. + (vstrwq): Likewise. + * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. + (STRS_P): Likewise. + (STRSS): Likewise. + (STRSS_P): Likewise. + (STRSU): Likewise. + (STRSU_P): Likewise. + (STRU): Likewise. + (STRU_P): Likewise. + * config/arm/mve.md (VST1Q): Define iterator. + (VSTRHSOQ): Likewise. + (VSTRHSSOQ): Likewise. + (VSTRHQ): Likewise. + (VSTRWQ): Likewise. + (mve_vstrhq_fv8hf): Define RTL pattern. + (mve_vstrhq_p_fv8hf): Likewise. + (mve_vstrhq_p_): Likewise. + (mve_vstrhq_scatter_offset_p_): Likewise. + (mve_vstrhq_scatter_offset_): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_): Likewise. + (mve_vstrhq_scatter_shifted_offset_): Likewise. + (mve_vstrhq_): Likewise. + (mve_vstrwq_fv4sf): Likewise. + (mve_vstrwq_p_fv4sf): Likewise. + (mve_vstrwq_p_v4si): Likewise. + (mve_vstrwq_v4si): Likewise. + (mve_vst1q_f): Define expand. + (mve_vst1q_): Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 89cdc5b..7e32be6 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1828,6 +1828,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vldrwq_gather_shifted_offset_z_f32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_f32(__base, __offset, __p) #define vldrwq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_s32(__base, __offset, __p) #define vldrwq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vldrwq_gather_shifted_offset_z_u32(__base, __offset, __p) +#define vst1q_f32(__addr, __value) __arm_vst1q_f32(__addr, __value) +#define vst1q_f16(__addr, __value) __arm_vst1q_f16(__addr, __value) +#define vst1q_s8(__addr, __value) __arm_vst1q_s8(__addr, __value) +#define vst1q_s32(__addr, __value) __arm_vst1q_s32(__addr, __value) +#define vst1q_s16(__addr, __value) __arm_vst1q_s16(__addr, __value) +#define vst1q_u8(__addr, __value) __arm_vst1q_u8(__addr, __value) +#define vst1q_u32(__addr, __value) __arm_vst1q_u32(__addr, __value) +#define vst1q_u16(__addr, __value) __arm_vst1q_u16(__addr, __value) +#define vstrhq_f16(__addr, __value) __arm_vstrhq_f16(__addr, __value) +#define vstrhq_scatter_offset_s32( __base, __offset, __value) __arm_vstrhq_scatter_offset_s32( __base, __offset, __value) +#define vstrhq_scatter_offset_s16( __base, __offset, __value) __arm_vstrhq_scatter_offset_s16( __base, __offset, __value) +#define vstrhq_scatter_offset_u32( __base, __offset, __value) __arm_vstrhq_scatter_offset_u32( __base, __offset, __value) +#define vstrhq_scatter_offset_u16( __base, __offset, __value) __arm_vstrhq_scatter_offset_u16( __base, __offset, __value) +#define vstrhq_scatter_offset_p_s32( __base, __offset, __value, __p) __arm_vstrhq_scatter_offset_p_s32( __base, __offset, __value, __p) +#define vstrhq_scatter_offset_p_s16( __base, __offset, __value, __p) __arm_vstrhq_scatter_offset_p_s16( __base, __offset, __value, __p) +#define vstrhq_scatter_offset_p_u32( __base, __offset, __value, __p) __arm_vstrhq_scatter_offset_p_u32( __base, __offset, __value, __p) +#define vstrhq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm_vstrhq_scatter_offset_p_u16( __base, __offset, __value, __p) +#define vstrhq_scatter_shifted_offset_s32( __base, __offset, __value) __arm_vstrhq_scatter_shifted_offset_s32( __base, __offset, __value) +#define vstrhq_scatter_shifted_offset_s16( __base, __offset, __value) __arm_vstrhq_scatter_shifted_offset_s16( __base, __offset, __value) +#define vstrhq_scatter_shifted_offset_u32( __base, __offset, __value) __arm_vstrhq_scatter_shifted_offset_u32( __base, __offset, __value) +#define vstrhq_scatter_shifted_offset_u16( __base, __offset, __value) __arm_vstrhq_scatter_shifted_offset_u16( __base, __offset, __value) +#define vstrhq_scatter_shifted_offset_p_s32( __base, __offset, __value, __p) __arm_vstrhq_scatter_shifted_offset_p_s32( __base, __offset, __value, __p) +#define vstrhq_scatter_shifted_offset_p_s16( __base, __offset, __value, __p) __arm_vstrhq_scatter_shifted_offset_p_s16( __base, __offset, __value, __p) +#define vstrhq_scatter_shifted_offset_p_u32( __base, __offset, __value, __p) __arm_vstrhq_scatter_shifted_offset_p_u32( __base, __offset, __value, __p) +#define vstrhq_scatter_shifted_offset_p_u16( __base, __offset, __value, __p) __arm_vstrhq_scatter_shifted_offset_p_u16( __base, __offset, __value, __p) +#define vstrhq_s32(__addr, __value) __arm_vstrhq_s32(__addr, __value) +#define vstrhq_s16(__addr, __value) __arm_vstrhq_s16(__addr, __value) +#define vstrhq_u32(__addr, __value) __arm_vstrhq_u32(__addr, __value) +#define vstrhq_u16(__addr, __value) __arm_vstrhq_u16(__addr, __value) +#define vstrhq_p_f16(__addr, __value, __p) __arm_vstrhq_p_f16(__addr, __value, __p) +#define vstrhq_p_s32(__addr, __value, __p) __arm_vstrhq_p_s32(__addr, __value, __p) +#define vstrhq_p_s16(__addr, __value, __p) __arm_vstrhq_p_s16(__addr, __value, __p) +#define vstrhq_p_u32(__addr, __value, __p) __arm_vstrhq_p_u32(__addr, __value, __p) +#define vstrhq_p_u16(__addr, __value, __p) __arm_vstrhq_p_u16(__addr, __value, __p) +#define vstrwq_f32(__addr, __value) __arm_vstrwq_f32(__addr, __value) +#define vstrwq_s32(__addr, __value) __arm_vstrwq_s32(__addr, __value) +#define vstrwq_u32(__addr, __value) __arm_vstrwq_u32(__addr, __value) +#define vstrwq_p_f32(__addr, __value, __p) __arm_vstrwq_p_f32(__addr, __value, __p) +#define vstrwq_p_s32(__addr, __value, __p) __arm_vstrwq_p_s32(__addr, __value, __p) +#define vstrwq_p_u32(__addr, __value, __p) __arm_vstrwq_p_u32(__addr, __value, __p) #endif __extension__ extern __inline void @@ -11893,6 +11933,244 @@ __arm_vldrwq_gather_shifted_offset_z_u32 (uint32_t const * __base, uint32x4_t __ return __builtin_mve_vldrwq_gather_shifted_offset_z_uv4si ((__builtin_neon_si *) __base, __offset, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_s8 (int8_t * __addr, int8x16_t __value) +{ + __builtin_mve_vst1q_sv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_s32 (int32_t * __addr, int32x4_t __value) +{ + __builtin_mve_vst1q_sv4si ((__builtin_neon_si *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_s16 (int16_t * __addr, int16x8_t __value) +{ + __builtin_mve_vst1q_sv8hi ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_u8 (uint8_t * __addr, uint8x16_t __value) +{ + __builtin_mve_vst1q_uv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_u32 (uint32_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vst1q_uv4si ((__builtin_neon_si *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_u16 (uint16_t * __addr, uint16x8_t __value) +{ + __builtin_mve_vst1q_uv8hi ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_s32 (int16_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_sv4si ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_s16 (int16_t * __base, uint16x8_t __offset, int16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_sv8hi ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_u32 (uint16_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_uv4si ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_u16 (uint16_t * __base, uint16x8_t __offset, uint16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_uv8hi ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_s32 (int16_t * __base, uint32x4_t __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_sv4si ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_s16 (int16_t * __base, uint16x8_t __offset, int16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_sv8hi ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_u32 (uint16_t * __base, uint32x4_t __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_uv4si ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_u16 (uint16_t * __base, uint16x8_t __offset, uint16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_uv8hi ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_s32 (int16_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_sv4si ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_s16 (int16_t * __base, uint16x8_t __offset, int16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_sv8hi ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_u32 (uint16_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_uv4si ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_u16 (uint16_t * __base, uint16x8_t __offset, uint16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_uv8hi ((__builtin_neon_hi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_s32 (int16_t * __base, uint32x4_t __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_sv4si ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_s16 (int16_t * __base, uint16x8_t __offset, int16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_sv8hi ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_u32 (uint16_t * __base, uint32x4_t __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_uv4si ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_u16 (uint16_t * __base, uint16x8_t __offset, uint16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_uv8hi ((__builtin_neon_hi *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_s32 (int16_t * __addr, int32x4_t __value) +{ + __builtin_mve_vstrhq_sv4si ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_s16 (int16_t * __addr, int16x8_t __value) +{ + __builtin_mve_vstrhq_sv8hi ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_u32 (uint16_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vstrhq_uv4si ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_u16 (uint16_t * __addr, uint16x8_t __value) +{ + __builtin_mve_vstrhq_uv8hi ((__builtin_neon_hi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_s32 (int16_t * __addr, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_sv4si ((__builtin_neon_hi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_sv8hi ((__builtin_neon_hi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_u32 (uint16_t * __addr, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_uv4si ((__builtin_neon_hi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_uv8hi ((__builtin_neon_hi *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_s32 (int32_t * __addr, int32x4_t __value) +{ + __builtin_mve_vstrwq_sv4si ((__builtin_neon_si *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_u32 (uint32_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vstrwq_uv4si ((__builtin_neon_si *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_p_sv4si ((__builtin_neon_si *) __addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_p_uv4si ((__builtin_neon_si *) __addr, __value, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -14147,6 +14425,48 @@ __arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t _ return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_p_fv4sf (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_f32 (float32_t * __addr, float32x4_t __value) +{ + __builtin_mve_vstrwq_fv4sf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_f32 (float32_t * __addr, float32x4_t __value) +{ + __builtin_mve_vst1q_fv4sf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_f16 (float16_t * __addr, float16x8_t __value) +{ + __builtin_mve_vst1q_fv8hf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_f16 (float16_t * __addr, float16x8_t __value) +{ + __builtin_mve_vstrhq_fv8hf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p); +} + #endif enum { @@ -16694,6 +17014,99 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1, p2));}) +#define vst1q(p0,p1) __arm_vst1q(p0,p1) +#define __arm_vst1q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + +#define vstrhq(p0,p1) __arm_vstrhq(p0,p1) +#define __arm_vstrhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) + +#define vstrhq_p(p0,p1,p2) __arm_vstrhq_p(p0,p1,p2) +#define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) + +#define vstrhq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + +#define vstrhq_scatter_offset(p0,p1,p2) __arm_vstrhq_scatter_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + +#define vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + +#define vstrhq_scatter_shifted_offset(p0,p1,p2) __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + +#define vstrwq_p(p0,p1,p2) __arm_vstrwq_p(p0,p1,p2) +#define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vstrwq(p0,p1) __arm_vstrwq(p0,p1) +#define __arm_vstrwq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + #else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -18860,6 +19273,90 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1, p2), \ int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2));}) +#define vst1q(p0,p1) __arm_vst1q(p0,p1) +#define __arm_vst1q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrhq(p0,p1) __arm_vstrhq(p0,p1) +#define __arm_vstrhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrhq_p(p0,p1,p2) __arm_vstrhq_p(p0,p1,p2) +#define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vstrhq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrhq_scatter_offset(p0,p1,p2) __arm_vstrhq_scatter_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrhq_scatter_shifted_offset(p0,p1,p2) __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + +#define vstrwq(p0,p1) __arm_vstrwq(p0,p1) +#define __arm_vstrwq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrwq_p(p0,p1,p2) __arm_vstrwq_p(p0,p1,p2) +#define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #endif /* MVE Integer. */ #define vldrdq_gather_offset(p0,p1) __arm_vldrdq_gather_offset(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index fc30361..ca8ba6a 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -762,3 +762,26 @@ VAR1 (LDRGU_Z, vldrdq_gather_offset_z_u, v2di) VAR1 (LDRGU_Z, vldrdq_gather_shifted_offset_z_u, v2di) VAR1 (LDRGU_Z, vldrwq_gather_offset_z_u, v4si) VAR1 (LDRGU_Z, vldrwq_gather_shifted_offset_z_u, v4si) +VAR3 (STRU, vst1q_u, v16qi, v8hi, v4si) +VAR3 (STRS, vst1q_s, v16qi, v8hi, v4si) +VAR2 (STRU_P, vstrhq_p_u, v8hi, v4si) +VAR2 (STRU, vstrhq_u, v8hi, v4si) +VAR2 (STRS_P, vstrhq_p_s, v8hi, v4si) +VAR2 (STRS, vstrhq_s, v8hi, v4si) +VAR2 (STRS, vst1q_f, v8hf, v4sf) +VAR2 (STRSU_P, vstrhq_scatter_shifted_offset_p_u, v8hi, v4si) +VAR2 (STRSU_P, vstrhq_scatter_offset_p_u, v8hi, v4si) +VAR2 (STRSU, vstrhq_scatter_shifted_offset_u, v8hi, v4si) +VAR2 (STRSU, vstrhq_scatter_offset_u, v8hi, v4si) +VAR2 (STRSS_P, vstrhq_scatter_shifted_offset_p_s, v8hi, v4si) +VAR2 (STRSS_P, vstrhq_scatter_offset_p_s, v8hi, v4si) +VAR2 (STRSS, vstrhq_scatter_shifted_offset_s, v8hi, v4si) +VAR2 (STRSS, vstrhq_scatter_offset_s, v8hi, v4si) +VAR1 (STRS, vstrhq_f, v8hf) +VAR1 (STRS_P, vstrhq_p_f, v8hf) +VAR1 (STRS, vstrwq_f, v4sf) +VAR1 (STRS, vstrwq_s, v4si) +VAR1 (STRU, vstrwq_u, v4si) +VAR1 (STRS_P, vstrwq_p_f, v4sf) +VAR1 (STRS_P, vstrwq_p_s, v4si) +VAR1 (STRU_P, vstrwq_p_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b0c0b87..68cf57f 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -201,7 +201,9 @@ VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S - VLDRWQGSO_U]) + VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S + VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S + VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -363,7 +365,10 @@ (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u") (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s") (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u") - (VLDRWQGSO_S "s") (VLDRWQGSO_U "u")]) + (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s") + (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u") + (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s") + (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -602,6 +607,11 @@ (define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U]) (define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U]) (define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U]) +(define_int_iterator VST1Q [VST1Q_S VST1Q_U]) +(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U]) +(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U]) +(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U]) +(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -8924,3 +8934,265 @@ return ""; } [(set_attr "length" "8")]) + +;; +;; [vstrhq_f] +;; +(define_insn "mve_vstrhq_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")] + VSTRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vstrh.16\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_p_f] +;; +(define_insn "mve_vstrhq_p_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VSTRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vpst\n\tvstrht.16\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrhq_p_s vstrhq_p_u] +;; +(define_insn "mve_vstrhq_p_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_6 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VSTRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vpst\n\tvstrht.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u] +;; +(define_insn "mve_vstrhq_scatter_offset_p_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_6 1 "s_register_operand" "w") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRHSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrht.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u] +;; +(define_insn "mve_vstrhq_scatter_offset_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_6 1 "s_register_operand" "w") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VSTRHSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrh.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u] +;; +(define_insn "mve_vstrhq_scatter_shifted_offset_p_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_6 1 "s_register_operand" "w") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRHSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrht.\t%q2, [%m0, %q1, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u] +;; +(define_insn "mve_vstrhq_scatter_shifted_offset_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_6 1 "s_register_operand" "w") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VSTRHSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrh.\t%q2, [%m0, %q1, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_s, vstrhq_u] +;; +(define_insn "mve_vstrhq_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_6 1 "s_register_operand" "w")] + VSTRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vstrh.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_f] +;; +(define_insn "mve_vstrwq_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")] + VSTRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vstrw.32\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_p_f] +;; +(define_insn "mve_vstrwq_p_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VSTRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_p_s vstrwq_p_u] +;; +(define_insn "mve_vstrwq_p_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VSTRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_s vstrwq_u] +;; +(define_insn "mve_vstrwq_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")] + VSTRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn ("vstrw.32\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vst1q_f" + [(match_operand: 0 "memory_operand") + (unspec: [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F) + ] + "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" +{ + emit_insn (gen_mve_vstrq_f(operands[0],operands[1])); + DONE; +}) + +(define_expand "mve_vst1q_" + [(match_operand:MVE_2 0 "memory_operand") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q) + ] + "TARGET_HAVE_MVE" +{ + emit_insn (gen_mve_vstrq_(operands[0],operands[1])); + DONE; +}) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b689b1..13a4d4f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,59 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c index 0116d35..a1c731a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c index 191e5de..5c4d9c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c index 9193b41..3380aa0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c index 9f15675..4707180 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c index 00547a4..49b52eb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c index af59f95..cbe153e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c index 7818470..75a3e38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c index 4409410..763caf2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c index 6dac7c2..1aee458 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c index b33efc2..7009c35 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c index 9a0572e..1c56a7c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c index 50a2cd16..d11b2b5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c index a915959..383f4ea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c index fdc6762..02cc6cc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c index ba9d0f2..56b84000 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c index 561669f..c98a2f6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c index b398bab..e5b7c27 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c index bc219c7..07953a2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c index 2e3b94f..126ad5d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c index fe5d51c..c9eff1e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c index 89ec398..af2e3dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c index c85a0c2..71217c0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c index e128b43..9349dd9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c index b183b9a..6994a47 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c index 67a42f7..69d39e0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c index 283d0a5..1c0eec0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c index 4783fae..7a15cff 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c index c144385..989e0bb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c index b537998..bb9cea5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c index a3d4fde..1578610 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c new file mode 100644 index 0000000..4c31700 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8_t value) +{ + vst1q_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (float16_t * addr, float16x8_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c new file mode 100644 index 0000000..0575fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4_t value) +{ + vst1q_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (float32_t * addr, float32x4_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c new file mode 100644 index 0000000..fe0bb81 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8_t value) +{ + vst1q_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (int16_t * addr, int16x8_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c new file mode 100644 index 0000000..2c113f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4_t value) +{ + vst1q_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (int32_t * addr, int32x4_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c new file mode 100644 index 0000000..8a0ce0d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value) +{ + vst1q_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c new file mode 100644 index 0000000..839d196 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8_t value) +{ + vst1q_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c new file mode 100644 index 0000000..3934d88 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4_t value) +{ + vst1q_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c new file mode 100644 index 0000000..09e0b66 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value) +{ + vst1q_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value) +{ + vst1q (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c new file mode 100644 index 0000000..a11dc5a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8_t value) +{ + vstrhq_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (float16_t * addr, float16x8_t value) +{ + vstrhq (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c new file mode 100644 index 0000000..447a6ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vstrhq_p_f16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vstrhq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c new file mode 100644 index 0000000..ea20400 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vstrhq_p_s16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vstrhq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c new file mode 100644 index 0000000..3edcbc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrhq_p_s32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrhq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c new file mode 100644 index 0000000..7e1f106 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_p_u16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c new file mode 100644 index 0000000..4e7684e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_p_u32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c new file mode 100644 index 0000000..caeb621 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8_t value) +{ + vstrhq_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (int16_t * addr, int16x8_t value) +{ + vstrhq (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c new file mode 100644 index 0000000..b737ce6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int32x4_t value) +{ + vstrhq_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (int16_t * addr, int32x4_t value) +{ + vstrhq (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c new file mode 100644 index 0000000..a6582aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p_s16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c new file mode 100644 index 0000000..f26e962 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p_s32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c new file mode 100644 index 0000000..ab5b627 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p_u16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c new file mode 100644 index 0000000..e6cd0cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p_u32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c new file mode 100644 index 0000000..f7c8e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrhq_scatter_offset_s16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrhq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c new file mode 100644 index 0000000..aaac128 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrhq_scatter_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrhq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c new file mode 100644 index 0000000..114962f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrhq_scatter_offset_u16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrhq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c new file mode 100644 index 0000000..92f3aed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrhq_scatter_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrhq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c new file mode 100644 index 0000000..135b016 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c new file mode 100644 index 0000000..e8b1a78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c new file mode 100644 index 0000000..60f08eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c new file mode 100644 index 0000000..076e184 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ + +void +foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c new file mode 100644 index 0000000..5ad9952 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrhq_scatter_shifted_offset_s16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrhq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c new file mode 100644 index 0000000..e471a9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrhq_scatter_shifted_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrhq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c new file mode 100644 index 0000000..711a5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrhq_scatter_shifted_offset_u16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrhq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c new file mode 100644 index 0000000..7822855 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrhq_scatter_shifted_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrhq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c new file mode 100644 index 0000000..291590c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8_t value) +{ + vstrhq_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8_t value) +{ + vstrhq (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c new file mode 100644 index 0000000..283420e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint32x4_t value) +{ + vstrhq_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ + +void +foo1 (uint16_t * addr, uint32x4_t value) +{ + vstrhq (addr, value); +} + +/* { dg-final { scan-assembler "vstrh.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c new file mode 100644 index 0000000..5b463bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4_t value) +{ + vstrwq_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (float32_t * addr, float32x4_t value) +{ + vstrwq (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c new file mode 100644 index 0000000..98edf4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vstrwq_p_f32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vstrwq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c new file mode 100644 index 0000000..9bccebd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrwq_p_s32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vstrwq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c new file mode 100644 index 0000000..d87110b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_p_u32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c new file mode 100644 index 0000000..863689c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4_t value) +{ + vstrwq_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (int32_t * addr, int32x4_t value) +{ + vstrwq (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c new file mode 100644 index 0000000..4d2dd80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4_t value) +{ + vstrwq_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4_t value) +{ + vstrwq (addr, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ -- cgit v1.1 From 7a5fffa5ed0a8edfca772d43465d2c9b55bb23cc Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Wed, 18 Mar 2020 19:16:32 +0000 Subject: [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word and double word to memory. This patch supports the following MVE ACLE store intrinsics which stores an halfword, word or double word to memory. vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64, vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64, vstrdq_scatter_shifted_offset_u64, vstrhq_scatter_offset_f16, vstrhq_scatter_offset_p_f16, vstrhq_scatter_shifted_offset_f16, vstrhq_scatter_shifted_offset_p_f16, vstrwq_scatter_base_f32, vstrwq_scatter_base_p_f32, vstrwq_scatter_offset_f32, vstrwq_scatter_offset_p_f32, vstrwq_scatter_offset_p_s32, vstrwq_scatter_offset_p_u32, vstrwq_scatter_offset_s32, vstrwq_scatter_offset_u32, vstrwq_scatter_shifted_offset_f32, vstrwq_scatter_shifted_offset_p_f32, vstrwq_scatter_shifted_offset_p_s32, vstrwq_scatter_shifted_offset_p_u32, vstrwq_scatter_shifted_offset_s32, vstrwq_scatter_shifted_offset_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch a new predicate "Ri" is defined to check the immediate is in the range of +/-1016 and multiple of 8. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. (vstrdq_scatter_base_p_u64): Likewise. (vstrdq_scatter_base_s64): Likewise. (vstrdq_scatter_base_u64): Likewise. (vstrdq_scatter_offset_p_s64): Likewise. (vstrdq_scatter_offset_p_u64): Likewise. (vstrdq_scatter_offset_s64): Likewise. (vstrdq_scatter_offset_u64): Likewise. (vstrdq_scatter_shifted_offset_p_s64): Likewise. (vstrdq_scatter_shifted_offset_p_u64): Likewise. (vstrdq_scatter_shifted_offset_s64): Likewise. (vstrdq_scatter_shifted_offset_u64): Likewise. (vstrhq_scatter_offset_f16): Likewise. (vstrhq_scatter_offset_p_f16): Likewise. (vstrhq_scatter_shifted_offset_f16): Likewise. (vstrhq_scatter_shifted_offset_p_f16): Likewise. (vstrwq_scatter_base_f32): Likewise. (vstrwq_scatter_base_p_f32): Likewise. (vstrwq_scatter_offset_f32): Likewise. (vstrwq_scatter_offset_p_f32): Likewise. (vstrwq_scatter_offset_p_s32): Likewise. (vstrwq_scatter_offset_p_u32): Likewise. (vstrwq_scatter_offset_s32): Likewise. (vstrwq_scatter_offset_u32): Likewise. (vstrwq_scatter_shifted_offset_f32): Likewise. (vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrwq_scatter_shifted_offset_p_s32): Likewise. (vstrwq_scatter_shifted_offset_p_u32): Likewise. (vstrwq_scatter_shifted_offset_s32): Likewise. (vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. (__arm_vstrdq_scatter_base_p_u64): Likewise. (__arm_vstrdq_scatter_base_s64): Likewise. (__arm_vstrdq_scatter_base_u64): Likewise. (__arm_vstrdq_scatter_offset_p_s64): Likewise. (__arm_vstrdq_scatter_offset_p_u64): Likewise. (__arm_vstrdq_scatter_offset_s64): Likewise. (__arm_vstrdq_scatter_offset_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. (__arm_vstrwq_scatter_offset_p_s32): Likewise. (__arm_vstrwq_scatter_offset_p_u32): Likewise. (__arm_vstrwq_scatter_offset_s32): Likewise. (__arm_vstrwq_scatter_offset_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_f16): Likewise. (__arm_vstrhq_scatter_offset_p_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. (__arm_vstrwq_scatter_base_f32): Likewise. (__arm_vstrwq_scatter_base_p_f32): Likewise. (__arm_vstrwq_scatter_offset_f32): Likewise. (__arm_vstrwq_scatter_offset_p_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrhq_scatter_offset): Define polymorphic variant. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrwq_scatter_base): Likewise. (vstrwq_scatter_base_p): Likewise. (vstrwq_scatter_offset): Likewise. (vstrwq_scatter_offset_p): Likewise. (vstrwq_scatter_shifted_offset): Likewise. (vstrwq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_base_p): Likewise. (vstrdq_scatter_base): Likewise. (vstrdq_scatter_offset_p): Likewise. (vstrdq_scatter_offset): Likewise. (vstrdq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_shifted_offset): Likewise. * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. (STRSBS_P): Likewise. (STRSBU): Likewise. (STRSBU_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. * config/arm/constraints.md (Ri): Define. * config/arm/mve.md (VSTRDSBQ): Define iterator. (VSTRDSOQ): Likewise. (VSTRDSSOQ): Likewise. (VSTRWSOQ): Likewise. (VSTRWSSOQ): Likewise. (mve_vstrdq_scatter_base_p_v2di): Define RTL pattern. (mve_vstrdq_scatter_base_v2di): Likewise. (mve_vstrdq_scatter_offset_p_v2di): Likewise. (mve_vstrdq_scatter_offset_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_p_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_v2di): Likewise. (mve_vstrhq_scatter_offset_fv8hf): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. (mve_vstrwq_scatter_base_fv4sf): Likewise. (mve_vstrwq_scatter_base_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_v4si): Likewise. (mve_vstrwq_scatter_offset_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_v4si): Likewise. * config/arm/predicates.md (Ri): Define predicate to check immediate is the range +/-1016 and multiple of 8. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: New test. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. --- gcc/ChangeLog | 117 +++++ gcc/config/arm/arm_mve.h | 502 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 30 ++ gcc/config/arm/constraints.md | 6 +- gcc/config/arm/mve.md | 451 +++++++++++++++++- gcc/config/arm/predicates.md | 8 + gcc/testsuite/ChangeLog | 47 ++ .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 22 + .../vstrdq_scatter_shifted_offset_p_s64.c | 22 + .../vstrdq_scatter_shifted_offset_p_u64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 22 + .../vstrhq_scatter_shifted_offset_p_f16.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_s32.c | 22 + .../vstrwq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 22 + 37 files changed, 1818 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index acea775..0f7df20 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,123 @@ Mihail Ionescu Srinath Parvathaneni + * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. + (vstrdq_scatter_base_p_u64): Likewise. + (vstrdq_scatter_base_s64): Likewise. + (vstrdq_scatter_base_u64): Likewise. + (vstrdq_scatter_offset_p_s64): Likewise. + (vstrdq_scatter_offset_p_u64): Likewise. + (vstrdq_scatter_offset_s64): Likewise. + (vstrdq_scatter_offset_u64): Likewise. + (vstrdq_scatter_shifted_offset_p_s64): Likewise. + (vstrdq_scatter_shifted_offset_p_u64): Likewise. + (vstrdq_scatter_shifted_offset_s64): Likewise. + (vstrdq_scatter_shifted_offset_u64): Likewise. + (vstrhq_scatter_offset_f16): Likewise. + (vstrhq_scatter_offset_p_f16): Likewise. + (vstrhq_scatter_shifted_offset_f16): Likewise. + (vstrhq_scatter_shifted_offset_p_f16): Likewise. + (vstrwq_scatter_base_f32): Likewise. + (vstrwq_scatter_base_p_f32): Likewise. + (vstrwq_scatter_offset_f32): Likewise. + (vstrwq_scatter_offset_p_f32): Likewise. + (vstrwq_scatter_offset_p_s32): Likewise. + (vstrwq_scatter_offset_p_u32): Likewise. + (vstrwq_scatter_offset_s32): Likewise. + (vstrwq_scatter_offset_u32): Likewise. + (vstrwq_scatter_shifted_offset_f32): Likewise. + (vstrwq_scatter_shifted_offset_p_f32): Likewise. + (vstrwq_scatter_shifted_offset_p_s32): Likewise. + (vstrwq_scatter_shifted_offset_p_u32): Likewise. + (vstrwq_scatter_shifted_offset_s32): Likewise. + (vstrwq_scatter_shifted_offset_u32): Likewise. + (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. + (__arm_vstrdq_scatter_base_p_u64): Likewise. + (__arm_vstrdq_scatter_base_s64): Likewise. + (__arm_vstrdq_scatter_base_u64): Likewise. + (__arm_vstrdq_scatter_offset_p_s64): Likewise. + (__arm_vstrdq_scatter_offset_p_u64): Likewise. + (__arm_vstrdq_scatter_offset_s64): Likewise. + (__arm_vstrdq_scatter_offset_u64): Likewise. + (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. + (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. + (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. + (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. + (__arm_vstrwq_scatter_offset_p_s32): Likewise. + (__arm_vstrwq_scatter_offset_p_u32): Likewise. + (__arm_vstrwq_scatter_offset_s32): Likewise. + (__arm_vstrwq_scatter_offset_u32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. + (__arm_vstrhq_scatter_offset_f16): Likewise. + (__arm_vstrhq_scatter_offset_p_f16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. + (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. + (__arm_vstrwq_scatter_base_f32): Likewise. + (__arm_vstrwq_scatter_base_p_f32): Likewise. + (__arm_vstrwq_scatter_offset_f32): Likewise. + (__arm_vstrwq_scatter_offset_p_f32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. + (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. + (vstrhq_scatter_offset): Define polymorphic variant. + (vstrhq_scatter_offset_p): Likewise. + (vstrhq_scatter_shifted_offset): Likewise. + (vstrhq_scatter_shifted_offset_p): Likewise. + (vstrwq_scatter_base): Likewise. + (vstrwq_scatter_base_p): Likewise. + (vstrwq_scatter_offset): Likewise. + (vstrwq_scatter_offset_p): Likewise. + (vstrwq_scatter_shifted_offset): Likewise. + (vstrwq_scatter_shifted_offset_p): Likewise. + (vstrdq_scatter_base_p): Likewise. + (vstrdq_scatter_base): Likewise. + (vstrdq_scatter_offset_p): Likewise. + (vstrdq_scatter_offset): Likewise. + (vstrdq_scatter_shifted_offset_p): Likewise. + (vstrdq_scatter_shifted_offset): Likewise. + * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. + (STRSBS_P): Likewise. + (STRSBU): Likewise. + (STRSBU_P): Likewise. + (STRSS): Likewise. + (STRSS_P): Likewise. + (STRSU): Likewise. + (STRSU_P): Likewise. + * config/arm/constraints.md (Ri): Define. + * config/arm/mve.md (VSTRDSBQ): Define iterator. + (VSTRDSOQ): Likewise. + (VSTRDSSOQ): Likewise. + (VSTRWSOQ): Likewise. + (VSTRWSSOQ): Likewise. + (mve_vstrdq_scatter_base_p_v2di): Define RTL pattern. + (mve_vstrdq_scatter_base_v2di): Likewise. + (mve_vstrdq_scatter_offset_p_v2di): Likewise. + (mve_vstrdq_scatter_offset_v2di): Likewise. + (mve_vstrdq_scatter_shifted_offset_p_v2di): Likewise. + (mve_vstrdq_scatter_shifted_offset_v2di): Likewise. + (mve_vstrhq_scatter_offset_fv8hf): Likewise. + (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. + (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. + (mve_vstrwq_scatter_base_fv4sf): Likewise. + (mve_vstrwq_scatter_base_p_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_p_v4si): Likewise. + (mve_vstrwq_scatter_offset_v4si): Likewise. + (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_v4si): Likewise. + (mve_vstrwq_scatter_shifted_offset_v4si): Likewise. + * config/arm/predicates.md (Ri): Define predicate to check immediate + is the range +/-1016 and multiple of 8. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * config/arm/arm_mve.h (vst1q_f32): Define macro. (vst1q_f16): Likewise. (vst1q_s8): Likewise. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 7e32be6..5ea42bd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1868,6 +1868,36 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrwq_p_f32(__addr, __value, __p) __arm_vstrwq_p_f32(__addr, __value, __p) #define vstrwq_p_s32(__addr, __value, __p) __arm_vstrwq_p_s32(__addr, __value, __p) #define vstrwq_p_u32(__addr, __value, __p) __arm_vstrwq_p_u32(__addr, __value, __p) +#define vstrdq_scatter_base_p_s64(__addr, __offset, __value, __p) __arm_vstrdq_scatter_base_p_s64(__addr, __offset, __value, __p) +#define vstrdq_scatter_base_p_u64(__addr, __offset, __value, __p) __arm_vstrdq_scatter_base_p_u64(__addr, __offset, __value, __p) +#define vstrdq_scatter_base_s64(__addr, __offset, __value) __arm_vstrdq_scatter_base_s64(__addr, __offset, __value) +#define vstrdq_scatter_base_u64(__addr, __offset, __value) __arm_vstrdq_scatter_base_u64(__addr, __offset, __value) +#define vstrdq_scatter_offset_p_s64(__base, __offset, __value, __p) __arm_vstrdq_scatter_offset_p_s64(__base, __offset, __value, __p) +#define vstrdq_scatter_offset_p_u64(__base, __offset, __value, __p) __arm_vstrdq_scatter_offset_p_u64(__base, __offset, __value, __p) +#define vstrdq_scatter_offset_s64(__base, __offset, __value) __arm_vstrdq_scatter_offset_s64(__base, __offset, __value) +#define vstrdq_scatter_offset_u64(__base, __offset, __value) __arm_vstrdq_scatter_offset_u64(__base, __offset, __value) +#define vstrdq_scatter_shifted_offset_p_s64(__base, __offset, __value, __p) __arm_vstrdq_scatter_shifted_offset_p_s64(__base, __offset, __value, __p) +#define vstrdq_scatter_shifted_offset_p_u64(__base, __offset, __value, __p) __arm_vstrdq_scatter_shifted_offset_p_u64(__base, __offset, __value, __p) +#define vstrdq_scatter_shifted_offset_s64(__base, __offset, __value) __arm_vstrdq_scatter_shifted_offset_s64(__base, __offset, __value) +#define vstrdq_scatter_shifted_offset_u64(__base, __offset, __value) __arm_vstrdq_scatter_shifted_offset_u64(__base, __offset, __value) +#define vstrhq_scatter_offset_f16(__base, __offset, __value) __arm_vstrhq_scatter_offset_f16(__base, __offset, __value) +#define vstrhq_scatter_offset_p_f16(__base, __offset, __value, __p) __arm_vstrhq_scatter_offset_p_f16(__base, __offset, __value, __p) +#define vstrhq_scatter_shifted_offset_f16(__base, __offset, __value) __arm_vstrhq_scatter_shifted_offset_f16(__base, __offset, __value) +#define vstrhq_scatter_shifted_offset_p_f16(__base, __offset, __value, __p) __arm_vstrhq_scatter_shifted_offset_p_f16(__base, __offset, __value, __p) +#define vstrwq_scatter_base_f32(__addr, __offset, __value) __arm_vstrwq_scatter_base_f32(__addr, __offset, __value) +#define vstrwq_scatter_base_p_f32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_p_f32(__addr, __offset, __value, __p) +#define vstrwq_scatter_offset_f32(__base, __offset, __value) __arm_vstrwq_scatter_offset_f32(__base, __offset, __value) +#define vstrwq_scatter_offset_p_f32(__base, __offset, __value, __p) __arm_vstrwq_scatter_offset_p_f32(__base, __offset, __value, __p) +#define vstrwq_scatter_offset_p_s32(__base, __offset, __value, __p) __arm_vstrwq_scatter_offset_p_s32(__base, __offset, __value, __p) +#define vstrwq_scatter_offset_p_u32(__base, __offset, __value, __p) __arm_vstrwq_scatter_offset_p_u32(__base, __offset, __value, __p) +#define vstrwq_scatter_offset_s32(__base, __offset, __value) __arm_vstrwq_scatter_offset_s32(__base, __offset, __value) +#define vstrwq_scatter_offset_u32(__base, __offset, __value) __arm_vstrwq_scatter_offset_u32(__base, __offset, __value) +#define vstrwq_scatter_shifted_offset_f32(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset_f32(__base, __offset, __value) +#define vstrwq_scatter_shifted_offset_p_f32(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p_f32(__base, __offset, __value, __p) +#define vstrwq_scatter_shifted_offset_p_s32(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p_s32(__base, __offset, __value, __p) +#define vstrwq_scatter_shifted_offset_p_u32(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p_u32(__base, __offset, __value, __p) +#define vstrwq_scatter_shifted_offset_s32(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset_s32(__base, __offset, __value) +#define vstrwq_scatter_shifted_offset_u32(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset_u32(__base, __offset, __value) #endif __extension__ extern __inline void @@ -12171,6 +12201,146 @@ __arm_vstrwq_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p) __builtin_mve_vstrwq_p_uv4si ((__builtin_neon_si *) __addr, __value, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_p_s64 (uint64x2_t __addr, const int __offset, int64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_base_p_sv2di (__addr, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_p_u64 (uint64x2_t __addr, const int __offset, uint64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_base_p_uv2di (__addr, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_s64 (uint64x2_t __addr, const int __offset, int64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_base_sv2di (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_u64 (uint64x2_t __addr, const int __offset, uint64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_base_uv2di (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_offset_p_s64 (int64_t * __base, uint64x2_t __offset, int64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_offset_p_sv2di (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_offset_p_u64 (uint64_t * __base, uint64x2_t __offset, uint64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_offset_p_uv2di (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_offset_s64 (int64_t * __base, uint64x2_t __offset, int64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_offset_sv2di (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_offset_u64 (uint64_t * __base, uint64x2_t __offset, uint64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_offset_uv2di (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_shifted_offset_p_s64 (int64_t * __base, uint64x2_t __offset, int64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_shifted_offset_p_sv2di (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_shifted_offset_p_u64 (uint64_t * __base, uint64x2_t __offset, uint64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_shifted_offset_p_uv2di (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_shifted_offset_s64 (int64_t * __base, uint64x2_t __offset, int64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_shifted_offset_sv2di (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_shifted_offset_u64 (uint64_t * __base, uint64x2_t __offset, uint64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_shifted_offset_uv2di (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_p_s32 (int32_t * __base, uint32x4_t __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_offset_p_sv4si ((__builtin_neon_si *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_p_u32 (uint32_t * __base, uint32x4_t __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_offset_p_uv4si ((__builtin_neon_si *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_s32 (int32_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_offset_sv4si ((__builtin_neon_si *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_u32 (uint32_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_offset_uv4si ((__builtin_neon_si *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_p_s32 (int32_t * __base, uint32x4_t __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_p_sv4si ((__builtin_neon_si *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_p_u32 (uint32_t * __base, uint32x4_t __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_p_uv4si ((__builtin_neon_si *) __base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_s32 (int32_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_sv4si ((__builtin_neon_si *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_u32 (uint32_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_uv4si ((__builtin_neon_si *) __base, __offset, __value); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -14467,6 +14637,76 @@ __arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_fv8hf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_fv8hf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_fv8hf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_fv8hf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_fv4sf (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_p_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_p_fv4sf (__addr, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_offset_fv4sf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_offset_p_fv4sf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_fv4sf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p); +} + #endif enum { @@ -17107,6 +17347,136 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) +#define vstrhq_scatter_offset(p0,p1,p2) __arm_vstrhq_scatter_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + +#define vstrhq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + +#define vstrhq_scatter_shifted_offset(p0,p1,p2) __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + +#define vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + +#define vstrwq_scatter_base(p0,p1,p2) __arm_vstrwq_scatter_base(p0,p1,p2) +#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_f32 (p0, p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vstrwq_scatter_base_p(p0,p1,p2,p3) __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32(p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_p_f32(p0, p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vstrwq_scatter_offset(p0,p1,p2) __arm_vstrwq_scatter_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vstrwq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vstrwq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vstrwq_scatter_offset(p0,p1,p2) __arm_vstrwq_scatter_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vstrwq_scatter_shifted_offset(p0,p1,p2) __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vstrwq_scatter_shifted_offset(p0,p1,p2) __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + #else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -19357,6 +19727,138 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) +#define vstrdq_scatter_base_p(p0,p1,p2,p3) __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) +#define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_base_p_s64 (p0, p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_p_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + +#define vstrdq_scatter_base(p0,p1,p2) __arm_vstrdq_scatter_base(p0,p1,p2) +#define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_base_s64 (p0, p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + +#define vstrdq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), __p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), __p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + +#define vstrdq_scatter_offset(p0,p1,p2) __arm_vstrdq_scatter_offset(p0,p1,p2) +#define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), __p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), __p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + +#define vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), __p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), __p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + +#define vstrdq_scatter_shifted_offset(p0,p1,p2) __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), __p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), __p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + +#define vstrhq_scatter_offset(p0,p1,p2) __arm_vstrhq_scatter_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrhq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrhq_scatter_shifted_offset(p0,p1,p2) __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrwq_scatter_offset(p0,p1,p2) __arm_vstrwq_scatter_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vstrwq_scatter_offset(p0,p1,p2) __arm_vstrwq_scatter_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_shifted_offset(p0,p1,p2) __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) +#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + #endif /* MVE Integer. */ #define vldrdq_gather_offset(p0,p1) __arm_vldrdq_gather_offset(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index ca8ba6a..144547f 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -785,3 +785,33 @@ VAR1 (STRU, vstrwq_u, v4si) VAR1 (STRS_P, vstrwq_p_f, v4sf) VAR1 (STRS_P, vstrwq_p_s, v4si) VAR1 (STRU_P, vstrwq_p_u, v4si) +VAR1 (STRSBS, vstrdq_scatter_base_s, v2di) +VAR1 (STRSBS, vstrwq_scatter_base_f, v4sf) +VAR1 (STRSBS_P, vstrdq_scatter_base_p_s, v2di) +VAR1 (STRSBS_P, vstrwq_scatter_base_p_f, v4sf) +VAR1 (STRSBU, vstrdq_scatter_base_u, v2di) +VAR1 (STRSBU_P, vstrdq_scatter_base_p_u, v2di) +VAR1 (STRSS, vstrdq_scatter_offset_s, v2di) +VAR1 (STRSS, vstrdq_scatter_shifted_offset_s, v2di) +VAR1 (STRSS, vstrhq_scatter_offset_f, v8hf) +VAR1 (STRSS, vstrhq_scatter_shifted_offset_f, v8hf) +VAR1 (STRSS, vstrwq_scatter_offset_f, v4sf) +VAR1 (STRSS, vstrwq_scatter_offset_s, v4si) +VAR1 (STRSS, vstrwq_scatter_shifted_offset_f, v4sf) +VAR1 (STRSS, vstrwq_scatter_shifted_offset_s, v4si) +VAR1 (STRSS_P, vstrdq_scatter_offset_p_s, v2di) +VAR1 (STRSS_P, vstrdq_scatter_shifted_offset_p_s, v2di) +VAR1 (STRSS_P, vstrhq_scatter_offset_p_f, v8hf) +VAR1 (STRSS_P, vstrhq_scatter_shifted_offset_p_f, v8hf) +VAR1 (STRSS_P, vstrwq_scatter_offset_p_f, v4sf) +VAR1 (STRSS_P, vstrwq_scatter_offset_p_s, v4si) +VAR1 (STRSS_P, vstrwq_scatter_shifted_offset_p_f, v4sf) +VAR1 (STRSS_P, vstrwq_scatter_shifted_offset_p_s, v4si) +VAR1 (STRSU, vstrdq_scatter_offset_u, v2di) +VAR1 (STRSU, vstrdq_scatter_shifted_offset_u, v2di) +VAR1 (STRSU, vstrwq_scatter_offset_u, v4si) +VAR1 (STRSU, vstrwq_scatter_shifted_offset_u, v4si) +VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di) +VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di) +VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) +VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 2641669..41a85e2 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -35,7 +35,7 @@ ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra, -;; Rg +;; Rg, Ri ;; in all states: Pf, Pg ;; The following memory constraints have been used: @@ -90,6 +90,10 @@ (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) || (ival == 4) || (ival == 8))"))) +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. +(define_predicate "mve_vldrd_immediate" + (match_test "satisfies_constraint_Ri (op)")) + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 68cf57f..5667882 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -203,7 +203,11 @@ VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S - VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F]) + VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F VSTRDQSB_S + VSTRDQSB_U VSTRDQSO_S VSTRDQSO_U VSTRDQSSO_S + VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S + VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F + VSTRWQSO_F VSTRWQSSO_F]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -368,7 +372,11 @@ (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s") (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u") (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s") - (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")]) + (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u") + (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s") + (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u") + (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u") + (VSTRWQSSO_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -612,6 +620,11 @@ (define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U]) (define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U]) (define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U]) +(define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U]) +(define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U]) +(define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U]) +(define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U]) +(define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -9196,3 +9209,437 @@ emit_insn (gen_mve_vstrq_(operands[0],operands[1])); DONE; }) + +;; +;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u] +;; +(define_insn "mve_vstrdq_scatter_base_p_v2di" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V2DI 0 "s_register_operand" "w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRDSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrdq_scatter_base_s vstrdq_scatter_base_u] +;; +(define_insn "mve_vstrdq_scatter_base_v2di" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V2DI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "w")] + VSTRDSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u] +;; +(define_insn "mve_vstrdq_scatter_offset_p_v2di" + [(set (match_operand:V2DI 0 "memory_operand" "=Us") + (unspec:V2DI + [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRDSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\;\tvstrdt.64\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u] +;; +(define_insn "mve_vstrdq_scatter_offset_v2di" + [(set (match_operand:V2DI 0 "memory_operand" "=Us") + (unspec:V2DI + [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:V2DI 2 "s_register_operand" "w")] + VSTRDSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrd.64\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u] +;; +(define_insn "mve_vstrdq_scatter_shifted_offset_p_v2di" + [(set (match_operand:V2DI 0 "memory_operand" "=Us") + (unspec:V2DI + [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRDSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\;\tvstrdt.64\t%q2, [%m0, %q1, UXTW #3]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u] +;; +(define_insn "mve_vstrdq_scatter_shifted_offset_v2di" + [(set (match_operand:V2DI 0 "memory_operand" "=Us") + (unspec:V2DI + [(match_operand:V2DI 1 "s_register_operand" "w") + (match_operand:V2DI 2 "s_register_operand" "w")] + VSTRDSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrd.64\t%q2, [%m0, %q1, UXTW #3]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_scatter_offset_f] +;; +(define_insn "mve_vstrhq_scatter_offset_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI + [(match_operand:V8HI 1 "s_register_operand" "w") + (match_operand:V8HF 2 "s_register_operand" "w")] + VSTRHQSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrh.16\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_scatter_offset_p_f] +;; +(define_insn "mve_vstrhq_scatter_offset_p_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI + [(match_operand:V8HI 1 "s_register_operand" "w") + (match_operand:V8HF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRHQSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrht.16\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrhq_scatter_shifted_offset_f] +;; +(define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI + [(match_operand:V8HI 1 "s_register_operand" "w") + (match_operand:V8HF 2 "s_register_operand" "w")] + VSTRHQSSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrh.16\t%q2, [%m0, %q1, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrhq_scatter_shifted_offset_p_f] +;; +(define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf" + [(set (match_operand:V8HI 0 "memory_operand" "=Us") + (unspec:V8HI + [(match_operand:V8HI 1 "s_register_operand" "w") + (match_operand:V8HF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRHQSSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrht.16\t%q2, [%m0, %q1, uxtw #1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_base_f] +;; +(define_insn "mve_vstrwq_scatter_base_fv4sf" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SF 2 "s_register_operand" "w")] + VSTRWQSB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_base_p_f] +;; +(define_insn "mve_vstrwq_scatter_base_p_fv4sf" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWQSB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_offset_f] +;; +(define_insn "mve_vstrwq_scatter_offset_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SF 2 "s_register_operand" "w")] + VSTRWQSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrw.32\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_offset_p_f] +;; +(define_insn "mve_vstrwq_scatter_offset_p_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWQSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrwt.32\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_offset_p_s vstrwq_scatter_offset_p_u] +;; +(define_insn "mve_vstrwq_scatter_offset_p_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\n\tvstrwt.32\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] +;; +(define_insn "mve_vstrwq_scatter_offset_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSTRWSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrw.32\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_shifted_offset_f] +;; +(define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SF 2 "s_register_operand" "w")] + VSTRWQSSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrw.32\t%q2, [%m0, %q1, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_shifted_offset_p_f] +;; +(define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWQSSO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\;\tvstrwt.32\t%q2, [%m0, %q1, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u] +;; +(define_insn "mve_vstrwq_scatter_shifted_offset_p_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRWSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vpst\;\tvstrwt.32\t%q2, [%m0, %q1, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u] +;; +(define_insn "mve_vstrwq_scatter_shifted_offset_v4si" + [(set (match_operand:V4SI 0 "memory_operand" "=Us") + (unspec:V4SI + [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSTRWSSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn ("vstrw.32\t%q2, [%m0, %q1, uxtw #2]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 2b65e64..bb302ed 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -59,6 +59,14 @@ (define_predicate "mve_imm_selective_upto_8" (match_test "satisfies_constraint_Rg (op)")) +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. +(define_constraint "Ri" + "@internal In Thumb-2 state a constant is multiple of 8 and in range + of -/+ 1016 for MVE" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) + && ((ival % 8) == 0)"))) + ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns (define_predicate "guard_addr_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 13a4d4f..8fee29f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,53 @@ Mihail Ionescu Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: New test. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: + Likewise. + +2020-03-18 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c new file mode 100644 index 0000000..0899605 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_p_s64 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ + +void +foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c new file mode 100644 index 0000000..65c9ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_p_u64 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ + +void +foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c new file mode 100644 index 0000000..8ae6a96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t addr, const int offset, int64x2_t value) +{ + vstrdq_scatter_base_s64 (addr, 1016, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ + +void +foo1 (uint64x2_t addr, const int offset, int64x2_t value) +{ + vstrdq_scatter_base (addr, 1016, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c new file mode 100644 index 0000000..da15b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t addr, const int offset, uint64x2_t value) +{ + vstrdq_scatter_base_u64 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ + +void +foo1 (uint64x2_t addr, const int offset, uint64x2_t value) +{ + vstrdq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c new file mode 100644 index 0000000..01d2c68 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_offset_p_s64 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ + +void +foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c new file mode 100644 index 0000000..2458c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_offset_p_u64 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ + +void +foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c new file mode 100644 index 0000000..1e14a38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int64_t * base, uint64x2_t offset, int64x2_t value) +{ + vstrdq_scatter_offset_s64 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ + +void +foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) +{ + vstrdq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c new file mode 100644 index 0000000..fed19ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) +{ + vstrdq_scatter_offset_u64 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ + +void +foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) +{ + vstrdq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c new file mode 100644 index 0000000..b93bdd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ + +void +foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c new file mode 100644 index 0000000..9993028 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ + +void +foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c new file mode 100644 index 0000000..5cb7aed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int64_t * base, uint64x2_t offset, int64x2_t value) +{ + vstrdq_scatter_shifted_offset_s64 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ + +void +foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) +{ + vstrdq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c new file mode 100644 index 0000000..7053953 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) +{ + vstrdq_scatter_shifted_offset_u64 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ + +void +foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) +{ + vstrdq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c new file mode 100644 index 0000000..aea8adb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * base, uint16x8_t offset, float16x8_t value) +{ + vstrhq_scatter_offset_f16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) +{ + vstrhq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c new file mode 100644 index 0000000..dc4ce1d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p_f16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c new file mode 100644 index 0000000..1c90cc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * base, uint16x8_t offset, float16x8_t value) +{ + vstrhq_scatter_shifted_offset_f16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ + +void +foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) +{ + vstrhq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrh.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c new file mode 100644 index 0000000..e45d1d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) +{ + vstrhq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c new file mode 100644 index 0000000..7895a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, float32x4_t value) +{ + vstrwq_scatter_base_f32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, float32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c new file mode 100644 index 0000000..c0069c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p_f32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c new file mode 100644 index 0000000..a70fb85 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * base, uint32x4_t offset, float32x4_t value) +{ + vstrwq_scatter_offset_f32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +{ + vstrwq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c new file mode 100644 index 0000000..e8cc782 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p_f32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c new file mode 100644 index 0000000..7802ad5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p_s32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c new file mode 100644 index 0000000..a01fb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p_u32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c new file mode 100644 index 0000000..2523819 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrwq_scatter_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrwq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c new file mode 100644 index 0000000..ebdd83b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrwq_scatter_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrwq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c new file mode 100644 index 0000000..ce4e588 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * base, uint32x4_t offset, float32x4_t value) +{ + vstrwq_scatter_shifted_offset_f32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +{ + vstrwq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c new file mode 100644 index 0000000..452b540 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c new file mode 100644 index 0000000..56ceae4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c new file mode 100644 index 0000000..02c5970 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c new file mode 100644 index 0000000..4b08727 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrwq_scatter_shifted_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrwq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c new file mode 100644 index 0000000..6a9156c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrwq_scatter_shifted_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ + +void +foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrwq_scatter_shifted_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrw.32" } } */ -- cgit v1.1 From 3512dc0108afbed3bece2e9fa1719fb3ce1d73d9 Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Wed, 18 Mar 2020 14:47:29 -0600 Subject: PR ipa/92799 - ICE on a weakref function definition followed by a declaration gcc/testsuite/ChangeLog: PR ipa/92799 * gcc.dg/attr-weakref-5.c: New test. gcc/ChangeLog: PR ipa/92799 * cgraphunit.c (process_function_and_variable_attributes): Also complain about weakref function definitions and drop all effects of the attribute. --- gcc/ChangeLog | 7 +++++++ gcc/cgraphunit.c | 13 +++++++++++-- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f7df20..8694f27 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-18 Martin Sebor + + PR ipa/92799 + * cgraphunit.c (process_function_and_variable_attributes): Also + complain about weakref function definitions and drop all effects + of the attribute. + 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index a9dd288..fd58636 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -861,14 +861,23 @@ process_function_and_variable_attributes (cgraph_node *first, " attribute have effect only on public objects"); } if (lookup_attribute ("weakref", DECL_ATTRIBUTES (decl)) - && (node->definition && !node->alias)) + && node->definition + && (!node->alias || DECL_INITIAL (decl) != error_mark_node)) { - warning_at (DECL_SOURCE_LOCATION (node->decl), OPT_Wattributes, + /* NODE->DEFINITION && NODE->ALIAS is nonzero for valid weakref + function declarations; DECL_INITIAL is non-null for invalid + weakref functions that are also defined. */ + warning_at (DECL_SOURCE_LOCATION (decl), OPT_Wattributes, "% attribute ignored" " because function is defined"); DECL_WEAK (decl) = 0; DECL_ATTRIBUTES (decl) = remove_attribute ("weakref", DECL_ATTRIBUTES (decl)); + DECL_ATTRIBUTES (decl) = remove_attribute ("alias", + DECL_ATTRIBUTES (decl)); + node->alias = false; + node->weakref = false; + node->transparent_alias = false; } else if (lookup_attribute ("alias", DECL_ATTRIBUTES (decl)) && node->definition diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8fee29f..9e5fecd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Martin Sebor + + PR ipa/92799 + * gcc.dg/attr-weakref-5.c: New test. + 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.dg/attr-weakref-5.c b/gcc/testsuite/gcc.dg/attr-weakref-5.c new file mode 100644 index 0000000..e2f0406 --- /dev/null +++ b/gcc/testsuite/gcc.dg/attr-weakref-5.c @@ -0,0 +1,31 @@ +/* PR middle-end/92799 - ICE on a weakref function definition followed + by a declaration + { dg-do compile } + { dg-options "-Wall" } */ + +static __attribute__ ((weakref ("bar"))) void f0 (void) { } // { dg-warning "'weakref' attribute ignored because function is defined" } + +extern void f0 (void); + +void* use_f0 (void) { return f0; } + + +static __attribute__ ((weakref ("bar"))) void f1 (void) { } // { dg-warning "'weakref' attribute ignored because function is defined" } + +static void f1 (void); + +void* use_f1 (void) { return f1; } + + +static __attribute__ ((weakref ("bar"))) void f2 (void); + +static void f2 (void) { } // { dg-error "redefinition" } + +void* use_f2 (void) { return f2; } + + +static __attribute__ ((weakref ("bar"))) void f3 (void); + +void f3 (void) { } // { dg-error "redefinition" } + +void* use_f3 (void) { return f3; } -- cgit v1.1 From 529ea7d9596b26ba103578eeab448e9862a2d2c5 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Wed, 18 Mar 2020 16:07:28 -0600 Subject: Complete change to resolve pr90275. PR rtl-optimization/90275 * cse.c (cse_insn): Delete no-op register moves too. --- gcc/ChangeLog | 5 +++++ gcc/cse.c | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8694f27..3a2e491 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-12 Richard Sandiford + + PR rtl-optimization/90275 + * cse.c (cse_insn): Delete no-op register moves too. + 2020-03-18 Martin Sebor PR ipa/92799 diff --git a/gcc/cse.c b/gcc/cse.c index 08984c1..3e8724b 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -5329,7 +5329,6 @@ cse_insn (rtx_insn *insn) else if (n_sets == 1 && !CALL_P (insn) && (MEM_P (trial) || REG_P (trial)) - && MEM_P (dest) && rtx_equal_p (trial, dest) && !side_effects_p (dest) && (cfun->can_delete_dead_exceptions -- cgit v1.1 From 07fe4af4d51d74b63a76ea632d4db01d1f69f037 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Wed, 18 Mar 2020 21:58:45 +0000 Subject: rs6000: Add back some w* constraints (PR91886) In May and June last year I deleted many of our (vector) constraints. We can now just use "wa" for those, together with some other conditions, which can be per alternative using the "enabled" attribute (which in turn primarily uses the "isa" attribute). But, it turns out that Clang implements some of those constraints as well, and at least musl uses some of them. It is easy for us to add those contraints back (as undocumented aliases to "wa", which always did mean the same thing for valid inline assembler code), so do that. gcc/ * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented aliases for "wa". --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/constraints.md | 11 +++++++++++ 2 files changed, 16 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3a2e491..66202f0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-18 Segher Boessenkool + + * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented + aliases for "wa". + 2020-03-12 Richard Sandiford PR rtl-optimization/90275 diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 4074a11..c600535 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -45,6 +45,17 @@ FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}).") +(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "@internal A compatibility alias for @code{wa}.") +(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "@internal A compatibility alias for @code{wa}.") +(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "@internal A compatibility alias for @code{wa}.") +(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "@internal A compatibility alias for @code{wa}.") +(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "@internal A compatibility alias for @code{wa}.") + (define_register_constraint "h" "SPECIAL_REGS" "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).") -- cgit v1.1 From b5562f1187d47b0e8a20687a8d31d00c187aada9 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 19 Mar 2020 00:16:20 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 584bf4b..2cdfff0 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200318 +20200319 -- cgit v1.1 From 73bc09fa8c6b973a928a599498caa66a25c8bc8d Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 19 Mar 2020 10:15:52 +0100 Subject: middle-end/94216 fix another build_fold_addr_expr use 2020-03-19 Richard Biener PR middle-end/94216 * fold-const.c (fold_binary_loc): Avoid using build_fold_addr_expr when we really want an ADDR_EXPR. * g++.dg/torture/pr94216.C: New testcase. --- gcc/ChangeLog | 6 +++++ gcc/fold-const.c | 2 +- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/g++.dg/torture/pr94216.C | 45 ++++++++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66202f0..f015a55 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-19 Richard Biener + + PR middle-end/94216 + * fold-const.c (fold_binary_loc): Avoid using + build_fold_addr_expr when we really want an ADDR_EXPR. + 2020-03-18 Segher Boessenkool * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 3ab1a9a..9267914 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -10284,7 +10284,7 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type, if (!base) return NULL_TREE; return fold_build2 (MEM_REF, type, - build_fold_addr_expr (base), + build1 (ADDR_EXPR, TREE_TYPE (arg0), base), int_const_binop (PLUS_EXPR, arg1, size_int (coffset))); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9e5fecd..e828b7f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-19 Richard Biener + + PR middle-end/94216 + * g++.dg/torture/pr94216.C: New testcase. + 2020-03-18 Martin Sebor PR ipa/92799 diff --git a/gcc/testsuite/g++.dg/torture/pr94216.C b/gcc/testsuite/g++.dg/torture/pr94216.C new file mode 100644 index 0000000..e67239de9 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr94216.C @@ -0,0 +1,45 @@ +// { dg-do compile } +// { dg-additional-options "-g" } + +template struct A { typedef int _Type[_Nm]; }; +template struct B { + typename A<_Nm>::_Type _M_elems; + void operator[](int) { int a = *_M_elems; } +}; +class C { + struct D { + using type = int *; + }; + +public: + using pointer = D::type; +}; +class F { +public: + using pointer = C::pointer; + F(pointer); +}; +struct G { + int data; +}; +template struct H { + using dimensions_t = B; + dimensions_t dimensions; + G mem; +}; +template +H alloc_view(int, DimT, AlignT, Allocator) { + H b; + b.dimensions[0]; + return b; +} +namespace memory { + template using DynMdView = H<6>; +} +class I { + I(); + memory::DynMdView m_view; + F m_memory; +}; +int c, d, e; +I::I() : m_view(alloc_view<6>(c, d, e, [] {})), m_memory(&m_view.mem.data) {} -- cgit v1.1 From f3280e4c0c98e103603bafc466ea49651fe0b7f2 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 19 Mar 2020 10:19:24 +0100 Subject: ipa/94217 simplify offsetted address build This avoids using build_ref_for_offset and build_fold_addr_expr where type mixup easily results in something not IP invariant. 2020-03-19 Richard Biener PR ipa/94217 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr and build_ref_for_offset. --- gcc/ChangeLog | 6 ++++++ gcc/ipa-cp.c | 12 +++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f015a55..c91c73a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2020-03-19 Richard Biener + PR ipa/94217 + * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr + and build_ref_for_offset. + +2020-03-19 Richard Biener + PR middle-end/94216 * fold-const.c (fold_binary_loc): Avoid using build_fold_addr_expr when we really want an ADDR_EXPR. diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c index 27c020b..1c17010 100644 --- a/gcc/ipa-cp.c +++ b/gcc/ipa-cp.c @@ -1352,11 +1352,13 @@ ipa_get_jf_ancestor_result (struct ipa_jump_func *jfunc, tree input) gcc_checking_assert (TREE_CODE (input) != TREE_BINFO); if (TREE_CODE (input) == ADDR_EXPR) { - tree t = TREE_OPERAND (input, 0); - t = build_ref_for_offset (EXPR_LOCATION (t), t, - ipa_get_jf_ancestor_offset (jfunc), false, - ptr_type_node, NULL, false); - return build_fold_addr_expr (t); + gcc_checking_assert (is_gimple_ip_invariant_address (input)); + poly_int64 off = ipa_get_jf_ancestor_offset (jfunc); + if (known_eq (off, 0)) + return input; + return build1 (ADDR_EXPR, TREE_TYPE (input), + fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (input)), + input, build_int_cst (ptr_type_node, off))); } else return NULL_TREE; -- cgit v1.1 From c7e9019681857b329bbe4c1e7ec8dec8c736c0fe Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 19 Mar 2020 10:24:16 +0100 Subject: phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] Two years ago, I've added support for up to 2 simple preparation statements in value_replacement, but the - && estimate_num_insns (assign, &eni_time_weights) + && estimate_num_insns (bb_seq (middle_bb), &eni_time_weights) change, meant that we compute the cost of all those statements rather than just the single assign that has been the single supported non-debug statement in the bb before, doesn't do what I thought would do, gimple_seq is just gimple * and thus it can't be really overloaded depending on whether we pass a single gimple * or a whole sequence. Which means in the last two years it doesn't count all the statements, but only the first one. With -g that happens to be a DEBUG_STMT, or it could be e.g. the first preparation statement which could be much cheaper than the actual assign. 2020-03-19 Jakub Jelinek PR tree-optimization/94211 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq instead of estimate_num_insns for bb_seq (middle_bb). Rename emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust all uses. * gcc.dg/pr94211.c: New test. --- gcc/ChangeLog | 8 ++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr94211.c | 12 ++++++++++++ gcc/tree-ssa-phiopt.c | 10 +++++----- 4 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94211.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c91c73a..259d4ae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-19 Jakub Jelinek + + PR tree-optimization/94211 + * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq + instead of estimate_num_insns for bb_seq (middle_bb). Rename + emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust + all uses. + 2020-03-19 Richard Biener PR ipa/94217 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e828b7f..58f2e7e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-19 Jakub Jelinek + + PR tree-optimization/94211 + * gcc.dg/pr94211.c: New test. + 2020-03-19 Richard Biener PR middle-end/94216 diff --git a/gcc/testsuite/gcc.dg/pr94211.c b/gcc/testsuite/gcc.dg/pr94211.c new file mode 100644 index 0000000..3e160e4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94211.c @@ -0,0 +1,12 @@ +/* PR tree-optimization/94211 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +long +foo (long a, long b) +{ + if (__builtin_expect (b == 1, 1)) + return a; + int e = a + 1; + return a / b; +} diff --git a/gcc/tree-ssa-phiopt.c b/gcc/tree-ssa-phiopt.c index 947143b..9693118 100644 --- a/gcc/tree-ssa-phiopt.c +++ b/gcc/tree-ssa-phiopt.c @@ -1056,7 +1056,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb, gimple *cond; edge true_edge, false_edge; enum tree_code code; - bool emtpy_or_with_defined_p = true; + bool empty_or_with_defined_p = true; /* If the type says honor signed zeros we cannot do this optimization. */ @@ -1075,7 +1075,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb, { if (gimple_code (stmt) != GIMPLE_PREDICT && gimple_code (stmt) != GIMPLE_NOP) - emtpy_or_with_defined_p = false; + empty_or_with_defined_p = false; continue; } /* Now try to adjust arg0 or arg1 according to the computation @@ -1085,7 +1085,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb, && jump_function_from_stmt (&arg0, stmt)) || (lhs == arg1 && jump_function_from_stmt (&arg1, stmt))) - emtpy_or_with_defined_p = false; + empty_or_with_defined_p = false; } cond = last_stmt (cond_bb); @@ -1137,7 +1137,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb, /* If the middle basic block was empty or is defining the PHI arguments and this is a single phi where the args are different for the edges e0 and e1 then we can remove the middle basic block. */ - if (emtpy_or_with_defined_p + if (empty_or_with_defined_p && single_non_singleton_phi_for_edges (phi_nodes (gimple_bb (phi)), e0, e1) == phi) { @@ -1255,7 +1255,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb, && profile_status_for_fn (cfun) != PROFILE_ABSENT && EDGE_PRED (middle_bb, 0)->probability < profile_probability::even () /* If assign is cheap, there is no point avoiding it. */ - && estimate_num_insns (bb_seq (middle_bb), &eni_time_weights) + && estimate_num_insns_seq (bb_seq (middle_bb), &eni_time_weights) >= 3 * estimate_num_insns (cond, &eni_time_weights)) return 0; -- cgit v1.1 From 02f7334ac93f53ed06d881beb611e88be36dc56a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 19 Mar 2020 12:22:47 +0100 Subject: c++: Fix up handling of captured vars in lambdas in OpenMP clauses [PR93931] Without the parser.c change we were ICEing on the testcase, because while the uses of the captured vars inside of the constructs were replaced with capture proxy decls, we didn't do that for decls in OpenMP clauses. With that fixed, we don't ICE anymore, but the testcase is miscompiled and FAILs at runtime. This is because the capture proxy decls have DECL_VALUE_EXPR and during gimplification we were gimplifying those to their DECL_VALUE_EXPRs. That is fine for shared vars, but for privatized ones we must not do that. So that is what the cp-gimplify.c changes do. Had to add a DECL_CONTEXT check before calling is_capture_proxy because some VAR_DECLs don't have DECL_CONTEXT set (yet) and is_capture_proxy relies on that being non-NULL always. 2020-03-19 Jakub Jelinek PR c++/93931 * parser.c (cp_parser_omp_var_list_no_open): Call process_outer_var_ref on outer_automatic_var_p decls. * cp-gimplify.c (cxx_omp_disregard_value_expr): Return true also for capture proxy decls. * testsuite/libgomp.c++/pr93931.C: New test. --- gcc/cp/ChangeLog | 8 ++++++++ gcc/cp/cp-gimplify.c | 17 +++++++++++------ gcc/cp/parser.c | 2 ++ 3 files changed, 21 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index bb5f77f..b5d429b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2020-03-19 Jakub Jelinek + + PR c++/93931 + * parser.c (cp_parser_omp_var_list_no_open): Call process_outer_var_ref + on outer_automatic_var_p decls. + * cp-gimplify.c (cxx_omp_disregard_value_expr): Return true also for + capture proxy decls. + 2020-03-18 Nathan Sidwell PR c++/94147 - mangling of lambdas assigned to globals diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index 23a25e5..87c7e39 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -2260,12 +2260,17 @@ cxx_omp_finish_clause (tree c, gimple_seq *) bool cxx_omp_disregard_value_expr (tree decl, bool shared) { - return !shared - && VAR_P (decl) - && DECL_HAS_VALUE_EXPR_P (decl) - && DECL_ARTIFICIAL (decl) - && DECL_LANG_SPECIFIC (decl) - && DECL_OMP_PRIVATIZED_MEMBER (decl); + if (shared) + return false; + if (VAR_P (decl) + && DECL_HAS_VALUE_EXPR_P (decl) + && DECL_ARTIFICIAL (decl) + && DECL_LANG_SPECIFIC (decl) + && DECL_OMP_PRIVATIZED_MEMBER (decl)) + return true; + if (VAR_P (decl) && DECL_CONTEXT (decl) && is_capture_proxy (decl)) + return true; + return false; } /* Fold expression X which is used as an rvalue if RVAL is true. */ diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 198ab97..cbd5510 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -34059,6 +34059,8 @@ cp_parser_omp_var_list_no_open (cp_parser *parser, enum omp_clause_code kind, token->location); } } + if (outer_automatic_var_p (decl)) + decl = process_outer_var_ref (decl, tf_warning_or_error); if (decl == error_mark_node) ; else if (kind != 0) -- cgit v1.1 From c8429c2aba80f845939ffa6b2cfe8a0be1b50078 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Thu, 19 Mar 2020 16:56:27 +0100 Subject: API extension for binutils (type of symbols). * lto-section-in.c: Add ext_symtab. * lto-streamer-out.c (write_symbol_extension_info): New. (produce_symtab_extension): New. (produce_asm_for_decls): Stream also produce_symtab_extension. * lto-streamer.h (enum lto_section_type): New section. * lto-symtab.h (enum gcc_plugin_symbol_type): New. (enum gcc_plugin_symbol_section_kind): Likewise. * lto-plugin.c (LTO_SECTION_PREFIX): Rename to ... (LTO_SYMTAB_PREFIX): ... this. (LTO_SECTION_PREFIX_LEN): Rename to ... (LTO_SYMTAB_PREFIX_LEN): ... this. (LTO_SYMTAB_EXT_PREFIX): New. (LTO_SYMTAB_EXT_PREFIX_LEN): New. (LTO_LTO_PREFIX): New. (LTO_LTO_PREFIX_LEN): New. (parse_table_entry): Fill up unused to zero. (parse_table_entry_extension): New. (parse_symtab_extension): New. (finish_conflict_resolution): Change type for resolution. (process_symtab): Use new macro name. (process_symtab_extension): New. (claim_file_handler): Parse also process_symtab_extension. (onload): Call new add_symbols_v2. --- gcc/ChangeLog | 8 +++++ gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++-- gcc/lto-streamer.h | 1 + 4 files changed, 90 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 259d4ae..6b1b295 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-19 Martin Liska + + * lto-section-in.c: Add ext_symtab. + * lto-streamer-out.c (write_symbol_extension_info): New. + (produce_symtab_extension): New. + (produce_asm_for_decls): Stream also produce_symtab_extension. + * lto-streamer.h (enum lto_section_type): New section. + 2020-03-19 Jakub Jelinek PR tree-optimization/94211 diff --git a/gcc/lto-section-in.c b/gcc/lto-section-in.c index c17dd69..0923a8c 100644 --- a/gcc/lto-section-in.c +++ b/gcc/lto-section-in.c @@ -38,6 +38,7 @@ const char *lto_section_name[LTO_N_SECTION_TYPES] = "function_body", "statics", "symtab", + "ext_symtab", "refs", "asm", "jmpfuncs", diff --git a/gcc/lto-streamer-out.c b/gcc/lto-streamer-out.c index cea5e71..a219c1d 100644 --- a/gcc/lto-streamer-out.c +++ b/gcc/lto-streamer-out.c @@ -45,6 +45,7 @@ along with GCC; see the file COPYING3. If not see #include "print-tree.h" #include "tree-dfa.h" #include "file-prefix-map.h" /* remap_debug_filename() */ +#include "output.h" static void lto_write_tree (struct output_block*, tree, bool); @@ -2777,12 +2778,32 @@ write_symbol (struct streamer_tree_cache_d *cache, lto_write_data (&slot_num, 4); } +/* Write extension information for symbols (symbol type, section flags). */ + +static void +write_symbol_extension_info (tree t) +{ + unsigned char c; + c = ((unsigned char) TREE_CODE (t) == VAR_DECL + ? GCCST_VARIABLE : GCCST_FUNCTION); + lto_write_data (&c, 1); + unsigned char section_kind = 0; + if (TREE_CODE (t) == VAR_DECL) + { + section *s = get_variable_section (t, false); + if (s->common.flags & SECTION_BSS) + section_kind |= GCCSSK_BSS; + } + lto_write_data (§ion_kind, 1); +} + /* Write an IL symbol table to OB. SET and VSET are cgraph/varpool node sets we are outputting. */ -static void +static unsigned int produce_symtab (struct output_block *ob) { + unsigned int streamed_symbols = 0; struct streamer_tree_cache_d *cache = ob->writer_cache; char *section_name = lto_get_section_name (LTO_section_symtab, NULL, 0, NULL); lto_symtab_encoder_t encoder = ob->decl_state->symtab_node_encoder; @@ -2804,6 +2825,7 @@ produce_symtab (struct output_block *ob) if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ()) continue; write_symbol (cache, node->decl, &seen, false); + ++streamed_symbols; } for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei)) @@ -2813,8 +2835,61 @@ produce_symtab (struct output_block *ob) if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ()) continue; write_symbol (cache, node->decl, &seen, false); + ++streamed_symbols; + } + + lto_end_section (); + + return streamed_symbols; +} + +/* Symtab extension version. */ +#define LTO_SYMTAB_EXTENSION_VERSION 1 + +/* Write an IL symbol table extension to OB. + SET and VSET are cgraph/varpool node sets we are outputting. */ + +static void +produce_symtab_extension (struct output_block *ob, + unsigned int previous_streamed_symbols) +{ + unsigned int streamed_symbols = 0; + char *section_name = lto_get_section_name (LTO_section_symtab_extension, + NULL, 0, NULL); + lto_symtab_encoder_t encoder = ob->decl_state->symtab_node_encoder; + lto_symtab_encoder_iterator lsei; + + lto_begin_section (section_name, false); + free (section_name); + + unsigned char version = LTO_SYMTAB_EXTENSION_VERSION; + lto_write_data (&version, 1); + + /* Write the symbol table. + First write everything defined and then all declarations. + This is necessary to handle cases where we have duplicated symbols. */ + for (lsei = lsei_start (encoder); + !lsei_end_p (lsei); lsei_next (&lsei)) + { + symtab_node *node = lsei_node (lsei); + + if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ()) + continue; + write_symbol_extension_info (node->decl); + ++streamed_symbols; + } + for (lsei = lsei_start (encoder); + !lsei_end_p (lsei); lsei_next (&lsei)) + { + symtab_node *node = lsei_node (lsei); + + if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ()) + continue; + write_symbol_extension_info (node->decl); + ++streamed_symbols; } + gcc_assert (previous_streamed_symbols == streamed_symbols); lto_end_section (); } @@ -3001,7 +3076,10 @@ produce_asm_for_decls (void) /* Write the symbol table. It is used by linker to determine dependencies and thus we can skip it for WPA. */ if (!flag_wpa) - produce_symtab (ob); + { + unsigned int streamed_symbols = produce_symtab (ob); + produce_symtab_extension (ob, streamed_symbols); + } /* Write command line opts. */ lto_write_options (); diff --git a/gcc/lto-streamer.h b/gcc/lto-streamer.h index 25bf6c4..76aa6fe 100644 --- a/gcc/lto-streamer.h +++ b/gcc/lto-streamer.h @@ -219,6 +219,7 @@ enum lto_section_type LTO_section_function_body, LTO_section_static_initializer, LTO_section_symtab, + LTO_section_symtab_extension, LTO_section_refs, LTO_section_asm, LTO_section_jump_functions, -- cgit v1.1 From f22712bd8a2ed57d3cc7e6fa92730bd5852e27b3 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Thu, 19 Mar 2020 17:12:56 +0100 Subject: Fix inliner ICE on alias with flatten attribute [PR92372] gcc/ChangeLog: 2020-03-19 Jan Hubicka PR ipa/92372 * cgraphunit.c (process_function_and_variable_attributes): warn for flatten attribute on alias. * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. gcc/testsuite/ChangeLog: 2020-03-19 Jan Hubicka PR ipa/92372 * gcc.c-torture/pr92372.c: New test. * gcc.dg/attr-flatten-1.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/cgraphunit.c | 8 ++++++++ gcc/ipa-inline.c | 3 +++ gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.c-torture/pr92372.c | 16 ++++++++++++++++ gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 ++++++++++++++++++ 6 files changed, 58 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6b1b295..e1a778d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-19 Jan Hubicka + + PR ipa/92372 + * cgraphunit.c (process_function_and_variable_attributes): warn + for flatten attribute on alias. + * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. + 2020-03-19 Martin Liska * lto-section-in.c: Add ext_symtab. diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index fd58636..d7ed405 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -851,6 +851,14 @@ process_function_and_variable_attributes (cgraph_node *first, node = symtab->next_function (node)) { tree decl = node->decl; + + if (node->alias + && lookup_attribute ("flatten", DECL_ATTRIBUTES (decl))) + { + warning_at (DECL_SOURCE_LOCATION (node->decl), OPT_Wattributes, + "%" + " attribute attribute is ignored on aliases"); + } if (DECL_PRESERVE_P (decl)) node->mark_force_output (); else if (lookup_attribute ("externally_visible", DECL_ATTRIBUTES (decl))) diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c index 6b6ba9a..302ce16 100644 --- a/gcc/ipa-inline.c +++ b/gcc/ipa-inline.c @@ -2634,6 +2634,9 @@ ipa_inline (void) { node = order[i]; if (node->definition + /* Do not try to flatten aliases. These may happen for example when + creating local aliases. */ + && !node->alias && lookup_attribute ("flatten", DECL_ATTRIBUTES (node->decl)) != NULL) order[j--] = order[i]; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 58f2e7e..cce1603 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-19 Jan Hubicka + + PR ipa/92372 + * gcc.c-torture/pr92372.c: New test. + * gcc.dg/attr-flatten-1.c: New test. + 2020-03-19 Jakub Jelinek PR tree-optimization/94211 diff --git a/gcc/testsuite/gcc.c-torture/pr92372.c b/gcc/testsuite/gcc.c-torture/pr92372.c new file mode 100644 index 0000000..72a13bb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/pr92372.c @@ -0,0 +1,16 @@ +int fn2(int); +int fn3(int); + +__attribute__((flatten)) +int fn1(int p1) +{ + int a = fn2(p1); + return fn3(a); +} +__attribute__((flatten)) +int fn4(int p1) +{ + int j = fn2(p1); + return fn3(j); +} + diff --git a/gcc/testsuite/gcc.dg/attr-flatten-1.c b/gcc/testsuite/gcc.dg/attr-flatten-1.c new file mode 100644 index 0000000..ecb08fc --- /dev/null +++ b/gcc/testsuite/gcc.dg/attr-flatten-1.c @@ -0,0 +1,18 @@ +/* { dg-require-alias "" } */ +int fn2(int); +int fn3(int); + +__attribute__((flatten)) +int fn1(int p1) +{ + int a = fn2(p1); + return fn3(a); +} +__attribute__((flatten)) +__attribute__((alias("fn1"))) +int fn4(int p1); /* { dg-warning "ignored" } */ +int +test () +{ + return fn4(1); +} -- cgit v1.1 From 37482edc3f7f19110da7178d0d4c3003ea5272f3 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Tue, 17 Mar 2020 19:33:14 +0100 Subject: d/dmd: Merge upstream dmd d1a606599 Fixes long standing regression in the D front-end implemention, and adds a new field to allow retrieving a list of all content imports from the code generator. Reviewed-on: https://github.com/dlang/dmd/pull/10913 https://github.com/dlang/dmd/pull/10933 --- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/testsuite/gdc.test/compilable/imports/pr9471a.d | 2 ++ gcc/testsuite/gdc.test/compilable/imports/pr9471b.d | 5 +++++ gcc/testsuite/gdc.test/compilable/imports/pr9471c.d | 18 ++++++++++++++++++ gcc/testsuite/gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 ++++++ gcc/testsuite/gdc.test/runnable/traits.d | 4 ++-- 10 files changed, 37 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d (limited to 'gcc') diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index 6cbc4e3..a421448 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -b061bd744cb4eb94a7118581387d988d4ec25e97 +d1a606599e7c2bea8fda8bf5e3ddceb486ae69ac The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/dclass.c b/gcc/d/dmd/dclass.c index bbe2f8a..4609d6a 100644 --- a/gcc/d/dmd/dclass.c +++ b/gcc/d/dmd/dclass.c @@ -395,7 +395,6 @@ void ClassDeclaration::semantic(Scope *sc) } else if (symtab && !scx) { - semanticRun = PASSsemanticdone; return; } semanticRun = PASSsemantic; diff --git a/gcc/d/dmd/expressionsem.c b/gcc/d/dmd/expressionsem.c index 781bd3e..fed36cf 100644 --- a/gcc/d/dmd/expressionsem.c +++ b/gcc/d/dmd/expressionsem.c @@ -2370,6 +2370,7 @@ public: return setError(); } + sc->_module->contentImportedFiles.push(name); if (global.params.verbose) message("file %.*s\t(%s)", (int)se->len, (char *)se->string, name); if (global.params.moduleDeps != NULL) diff --git a/gcc/d/dmd/module.h b/gcc/d/dmd/module.h index 4a20356..f4253d3 100644 --- a/gcc/d/dmd/module.h +++ b/gcc/d/dmd/module.h @@ -76,6 +76,7 @@ public: unsigned numlines; // number of lines in source file int isDocFile; // if it is a documentation input file, not D source bool isPackageFile; // if it is a package.d + Strings contentImportedFiles; // array of files whose content was imported int needmoduleinfo; int selfimports; // 0: don't know, 1: does not, 2: does diff --git a/gcc/testsuite/gdc.test/compilable/imports/pr9471a.d b/gcc/testsuite/gdc.test/compilable/imports/pr9471a.d new file mode 100644 index 0000000..79b78e1 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/imports/pr9471a.d @@ -0,0 +1,2 @@ +import imports.pr9471c; +class AggregateDeclaration : ScopeDsymbol { } diff --git a/gcc/testsuite/gdc.test/compilable/imports/pr9471b.d b/gcc/testsuite/gdc.test/compilable/imports/pr9471b.d new file mode 100644 index 0000000..a46a12c --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/imports/pr9471b.d @@ -0,0 +1,5 @@ +import imports.pr9471a; +class ClassDeclaration : AggregateDeclaration +{ + void isBaseOf(); +} diff --git a/gcc/testsuite/gdc.test/compilable/imports/pr9471c.d b/gcc/testsuite/gdc.test/compilable/imports/pr9471c.d new file mode 100644 index 0000000..d80a614 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/imports/pr9471c.d @@ -0,0 +1,18 @@ +import imports.pr9471b; + +struct Array(T) +{ + static if (is(typeof(T.opCmp))) { } +} +alias ClassDeclarations = Array!ClassDeclaration; + +class Dsymbol +{ + void addObjcSymbols(ClassDeclarations); +} + +class ScopeDsymbol : Dsymbol +{ + import imports.pr9471d; + void importScope(); +} diff --git a/gcc/testsuite/gdc.test/compilable/imports/pr9471d.d b/gcc/testsuite/gdc.test/compilable/imports/pr9471d.d new file mode 100644 index 0000000..187b908 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/imports/pr9471d.d @@ -0,0 +1 @@ +// Module needs to be imported to trigger bug. diff --git a/gcc/testsuite/gdc.test/compilable/pr9471.d b/gcc/testsuite/gdc.test/compilable/pr9471.d new file mode 100644 index 0000000..37ff32e --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/pr9471.d @@ -0,0 +1,6 @@ +// PERMUTE_ARGS: +// EXTRA_FILES: imports/pr9471a.d imports/pr9471b.d imports/pr9471c.d imports/pr9471d.d +import imports.pr9471a; +import imports.pr9471b; + +static assert (__traits(getVirtualIndex, ClassDeclaration.isBaseOf) == 7); diff --git a/gcc/testsuite/gdc.test/runnable/traits.d b/gcc/testsuite/gdc.test/runnable/traits.d index 6c3bf78..b73ee01c 100644 --- a/gcc/testsuite/gdc.test/runnable/traits.d +++ b/gcc/testsuite/gdc.test/runnable/traits.d @@ -1253,7 +1253,7 @@ struct S10096X this(this) {} ~this() {} - string getStr() in(str) out(r; r == str) { return str; } + string getStr() in { assert(str); } out(r) { assert(r == str); } body { return str; } } static assert( [__traits(allMembers, S10096X)] == @@ -1271,7 +1271,7 @@ class C10096X this(int) {} ~this() {} - string getStr() in(str) out(r; r == str) { return str; + string getStr() in { assert(str); } out(r) { assert(r == str); } body { return str; } } static assert( [__traits(allMembers, C10096X)] == -- cgit v1.1 From 9def91e9f2a7051c9c146f16c1a10d1b25d33b47 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 19 Mar 2020 22:56:20 +0100 Subject: c: Fix up cfun->function_end_locus from the C FE [PR94029] On the following testcase we ICE because while DECL_STRUCT_FUNCTION (current_function_decl)->function_start_locus = c_parser_peek_token (parser)->location; and similarly DECL_SOURCE_LOCATION (fndecl) is set from some token's location, the end is set as: /* Store the end of the function, so that we get good line number info for the epilogue. */ cfun->function_end_locus = input_location; and the thing is that input_location is only very rarely set in the C FE (the primary spot that changes it is the cb_line_change/fe_file_change). Which means, e.g. for pretty much all C functions that are on a single line, function_start_locus column is > than function_end_locus column, and the testcase even has smaller line in function_end_locus because cb_line_change isn't performed while parsing multi-line arguments of a function-like macro. Attached are two possible fixes to achieve what the C++ FE does, in particular that cfun->function_end_locus is the locus of the closing } of the function. The first one updates input_location when we see a closing } of a compound statement (though any, not just the function body) and thus input_location in the finish_function call is what we need. The second instead propagates the location_t from the parsing of the outermost compound statement (the function body) to finish_function. The second one is this version. 2020-03-19 Jakub Jelinek PR gcov-profile/94029 * c-tree.h (finish_function): Add location_t argument defaulted to input_location. * c-parser.c (c_parser_compound_statement): Add endlocp argument and set it to the locus of closing } if non-NULL. (c_parser_compound_statement_nostart): Return locus of closing }. (c_parser_parse_rtl_body): Likewise. (c_parser_declaration_or_fndef): Propagate locus of closing } to finish_function. * c-decl.c (finish_function): Add end_loc argument, use it instead of input_location to set function_end_locus. * gcc.misc-tests/gcov-pr94029.c: New test. --- gcc/c/ChangeLog | 14 ++++++++ gcc/c/c-decl.c | 4 +-- gcc/c/c-parser.c | 51 +++++++++++++++++------------ gcc/c/c-tree.h | 2 +- gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 ++++++++ 6 files changed, 66 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c (limited to 'gcc') diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 25f8f5b..c0b65a5 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,17 @@ +2020-03-19 Jakub Jelinek + + PR gcov-profile/94029 + * c-tree.h (finish_function): Add location_t argument defaulted to + input_location. + * c-parser.c (c_parser_compound_statement): Add endlocp argument and + set it to the locus of closing } if non-NULL. + (c_parser_compound_statement_nostart): Return locus of closing }. + (c_parser_parse_rtl_body): Likewise. + (c_parser_declaration_or_fndef): Propagate locus of closing } to + finish_function. + * c-decl.c (finish_function): Add end_loc argument, use it instead of + input_location to set function_end_locus. + 2020-03-17 Jakub Jelinek PR c/94172 diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c index ed5163d..80fe318 100644 --- a/gcc/c/c-decl.c +++ b/gcc/c/c-decl.c @@ -9851,7 +9851,7 @@ temp_pop_parm_decls (void) This is called after parsing the body of the function definition. */ void -finish_function (void) +finish_function (location_t end_loc) { tree fndecl = current_function_decl; @@ -9947,7 +9947,7 @@ finish_function (void) /* Store the end of the function, so that we get good line number info for the epilogue. */ - cfun->function_end_locus = input_location; + cfun->function_end_locus = end_loc; /* Finalize the ELF visibility for the function. */ c_determine_visibility (fndecl); diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index 1e8f2f7..4b068a9 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -1487,8 +1487,8 @@ static struct c_expr c_parser_braced_init (c_parser *, tree, bool, static void c_parser_initelt (c_parser *, struct obstack *); static void c_parser_initval (c_parser *, struct c_expr *, struct obstack *); -static tree c_parser_compound_statement (c_parser *); -static void c_parser_compound_statement_nostart (c_parser *); +static tree c_parser_compound_statement (c_parser *, location_t * = NULL); +static location_t c_parser_compound_statement_nostart (c_parser *); static void c_parser_label (c_parser *); static void c_parser_statement (c_parser *, bool *, location_t * = NULL); static void c_parser_statement_after_labels (c_parser *, bool *, @@ -1583,8 +1583,7 @@ static void c_parser_objc_at_synthesize_declaration (c_parser *); static void c_parser_objc_at_dynamic_declaration (c_parser *); static bool c_parser_objc_diagnose_bad_element_prefix (c_parser *, struct c_declspecs *); - -static void c_parser_parse_rtl_body (c_parser *parser, char *start_with_pass); +static location_t c_parser_parse_rtl_body (c_parser *, char *); /* Parse a translation unit (C90 6.7, C99 6.9, C11 6.9). @@ -2472,12 +2471,13 @@ c_parser_declaration_or_fndef (c_parser *parser, bool fndef_ok, c_finish_oacc_routine (oacc_routine_data, current_function_decl, true); DECL_STRUCT_FUNCTION (current_function_decl)->function_start_locus = c_parser_peek_token (parser)->location; + location_t endloc; /* If the definition was marked with __RTL, use the RTL parser now, consuming the function body. */ if (specs->declspec_il == cdil_rtl) { - c_parser_parse_rtl_body (parser, specs->gimple_or_rtl_pass); + endloc = c_parser_parse_rtl_body (parser, specs->gimple_or_rtl_pass); /* Normally, store_parm_decls sets next_is_function_body, anticipating a function body. We need a push_scope/pop_scope @@ -2486,7 +2486,7 @@ c_parser_declaration_or_fndef (c_parser *parser, bool fndef_ok, push_scope (); pop_scope (); - finish_function (); + finish_function (endloc); return; } /* If the definition was marked with __GIMPLE then parse the @@ -2499,9 +2499,11 @@ c_parser_declaration_or_fndef (c_parser *parser, bool fndef_ok, specs->declspec_il, specs->entry_bb_count); in_late_binary_op = saved; + struct function *fun = DECL_STRUCT_FUNCTION (current_function_decl); + endloc = fun->function_start_locus; } else - fnbody = c_parser_compound_statement (parser); + fnbody = c_parser_compound_statement (parser, &endloc); tree fndecl = current_function_decl; if (nested) { @@ -2512,7 +2514,7 @@ c_parser_declaration_or_fndef (c_parser *parser, bool fndef_ok, by initializer_constant_valid_p. See gcc.dg/nested-fn-2.c. */ DECL_STATIC_CHAIN (decl) = 1; add_stmt (fnbody); - finish_function (); + finish_function (endloc); c_pop_function_context (); add_stmt (build_stmt (DECL_SOURCE_LOCATION (decl), DECL_EXPR, decl)); } @@ -2520,7 +2522,7 @@ c_parser_declaration_or_fndef (c_parser *parser, bool fndef_ok, { if (fnbody) add_stmt (fnbody); - finish_function (); + finish_function (endloc); } /* Get rid of the empty stmt list for GIMPLE/RTL. */ if (specs->declspec_il != cdil_none) @@ -5599,7 +5601,7 @@ c_parser_initval (c_parser *parser, struct c_expr *after, cancellation-point-directive */ static tree -c_parser_compound_statement (c_parser *parser) +c_parser_compound_statement (c_parser *parser, location_t *endlocp) { tree stmt; location_t brace_loc; @@ -5613,7 +5615,9 @@ c_parser_compound_statement (c_parser *parser) return error_mark_node; } stmt = c_begin_compound_stmt (true); - c_parser_compound_statement_nostart (parser); + location_t end_loc = c_parser_compound_statement_nostart (parser); + if (endlocp) + *endlocp = end_loc; return c_end_compound_stmt (brace_loc, stmt, true); } @@ -5622,7 +5626,7 @@ c_parser_compound_statement (c_parser *parser) used for parsing both compound statements and statement expressions (which follow different paths to handling the opening). */ -static void +static location_t c_parser_compound_statement_nostart (c_parser *parser) { bool last_stmt = false; @@ -5631,9 +5635,10 @@ c_parser_compound_statement_nostart (c_parser *parser) location_t label_loc = UNKNOWN_LOCATION; /* Quiet warning. */ if (c_parser_next_token_is (parser, CPP_CLOSE_BRACE)) { - add_debug_begin_stmt (c_parser_peek_token (parser)->location); + location_t endloc = c_parser_peek_token (parser)->location; + add_debug_begin_stmt (endloc); c_parser_consume_token (parser); - return; + return endloc; } mark_valid_location_for_stdc_pragma (true); if (c_parser_next_token_is_keyword (parser, RID_LABEL)) @@ -5674,8 +5679,9 @@ c_parser_compound_statement_nostart (c_parser *parser) { mark_valid_location_for_stdc_pragma (save_valid_for_pragma); c_parser_error (parser, "expected declaration or statement"); + location_t endloc = c_parser_peek_token (parser)->location; c_parser_consume_token (parser); - return; + return endloc; } while (c_parser_next_token_is_not (parser, CPP_CLOSE_BRACE)) { @@ -5773,7 +5779,7 @@ c_parser_compound_statement_nostart (c_parser *parser) { mark_valid_location_for_stdc_pragma (save_valid_for_pragma); c_parser_error (parser, "expected declaration or statement"); - return; + return c_parser_peek_token (parser)->location; } else if (c_parser_next_token_is_keyword (parser, RID_ELSE)) { @@ -5781,7 +5787,7 @@ c_parser_compound_statement_nostart (c_parser *parser) { mark_valid_location_for_stdc_pragma (save_valid_for_pragma); error_at (loc, "expected %<}%> before %"); - return; + return c_parser_peek_token (parser)->location; } else { @@ -5804,9 +5810,11 @@ c_parser_compound_statement_nostart (c_parser *parser) } if (last_label) error_at (label_loc, "label at end of compound statement"); + location_t endloc = c_parser_peek_token (parser)->location; c_parser_consume_token (parser); /* Restore the value we started with. */ mark_valid_location_for_stdc_pragma (save_valid_for_pragma); + return endloc; } /* Parse all consecutive labels, possibly preceded by standard @@ -21725,13 +21733,13 @@ c_parse_file (void) Take ownership of START_WITH_PASS, if non-NULL. */ -void +location_t c_parser_parse_rtl_body (c_parser *parser, char *start_with_pass) { if (!c_parser_require (parser, CPP_OPEN_BRACE, "expected %<{%>")) { free (start_with_pass); - return; + return c_parser_peek_token (parser)->location; } location_t start_loc = c_parser_peek_token (parser)->location; @@ -21753,7 +21761,7 @@ c_parser_parse_rtl_body (c_parser *parser, char *start_with_pass) case CPP_EOF: error_at (start_loc, "no closing brace"); free (start_with_pass); - return; + return c_parser_peek_token (parser)->location; default: break; } @@ -21771,12 +21779,13 @@ c_parser_parse_rtl_body (c_parser *parser, char *start_with_pass) if (!read_rtl_function_body_from_file_range (start_loc, end_loc)) { free (start_with_pass); - return; + return end_loc; } /* Run the backend on the cfun created above, transferring ownership of START_WITH_PASS. */ run_rtl_passes (start_with_pass); + return end_loc; } #include "gt-c-c-parser.h" diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h index 364d7e0..2015827 100644 --- a/gcc/c/c-tree.h +++ b/gcc/c/c-tree.h @@ -580,7 +580,7 @@ extern bool c_check_switch_jump_warnings (struct c_spot_bindings *, location_t, location_t); extern void finish_decl (tree, location_t, tree, tree, tree); extern tree finish_enum (tree, tree, tree); -extern void finish_function (void); +extern void finish_function (location_t = input_location); extern tree finish_struct (location_t, tree, tree, tree, class c_struct_parse_info *); extern tree c_simulate_enum_decl (location_t, const char *, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cce1603..bde605d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-19 Jakub Jelinek + + PR gcov-profile/94029 + * gcc.misc-tests/gcov-pr94029.c: New test. + 2020-03-19 Jan Hubicka PR ipa/92372 diff --git a/gcc/testsuite/gcc.misc-tests/gcov-pr94029.c b/gcc/testsuite/gcc.misc-tests/gcov-pr94029.c new file mode 100644 index 0000000..84d9b9b --- /dev/null +++ b/gcc/testsuite/gcc.misc-tests/gcov-pr94029.c @@ -0,0 +1,14 @@ +/* PR gcov-profile/94029 */ +/* { dg-options "-ftest-coverage" } */ +/* { dg-do compile } */ + +#define impl_test(name) void test_##name() { } +impl_test(t1 +) impl_test(t2) + +int main() +{ + return 0; +} + +/* { dg-final { run-gcov remove-gcda gcov-pr94029.c } } */ -- cgit v1.1 From f7dceb4e658399edfbf8dd0e08ce0c686bfa2c9d Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 20 Mar 2020 00:42:13 +0100 Subject: Fix cgraph_node::function_symbol availability compuattion [PR94202] this fixes ICE in inliner cache sanity check which is caused by very old bug in visibility calculation in cgraph_node::function_symbol and cgraph_node::function_or_virtual_thunk_symbol. In the testcase there is indirect call to a thunk. At begining we correctly see that its body as AVAIL_AVAILABLE but later we inline into the thunk and this turns it to AVAIL_INTERPOSABLE. This is because function_symbol incorrectly overwrites availability parameter by availability of the alias used in the call within thunk, which is a local alias. gcc/ChangeLog: 2020-03-19 Jan Hubicka PR ipa/94202 * cgraph.c (cgraph_node::function_symbol): Fix availability computation. (cgraph_node::function_or_virtual_thunk_symbol): Likewise. gcc/testsuite/ChangeLog: 2020-03-19 Jan Hubicka PR ipa/94202 * g++.dg/torture/pr94202.C: New test. --- gcc/ChangeLog | 6 ++++++ gcc/cgraph.c | 26 ++++++++++---------------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/torture/pr94202.C | 22 ++++++++++++++++++++++ 4 files changed, 43 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e1a778d..44e3206 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2020-03-19 Jan Hubicka + PR ipa/94202 + * cgraph.c (cgraph_node::function_symbol): Fix availability computation. + (cgraph_node::function_or_virtual_thunk_symbol): Likewise. + +2020-03-19 Jan Hubicka + PR ipa/92372 * cgraphunit.c (process_function_and_variable_attributes): warn for flatten attribute on alias. diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 9f0774f..b41dea1 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -3788,16 +3788,13 @@ cgraph_node::function_symbol (enum availability *availability, while (node->thunk.thunk_p) { + enum availability a; + ref = node; node = node->callees->callee; - if (availability) - { - enum availability a; - a = node->get_availability (ref); - if (a < *availability) - *availability = a; - } - node = node->ultimate_alias_target (availability, ref); + node = node->ultimate_alias_target (availability ? &a : NULL, ref); + if (availability && a < *availability) + *availability = a; } return node; } @@ -3818,16 +3815,13 @@ cgraph_node::function_or_virtual_thunk_symbol while (node->thunk.thunk_p && !node->thunk.virtual_offset_p) { + enum availability a; + ref = node; node = node->callees->callee; - if (availability) - { - enum availability a; - a = node->get_availability (ref); - if (a < *availability) - *availability = a; - } - node = node->ultimate_alias_target (availability, ref); + node = node->ultimate_alias_target (availability ? &a : NULL, ref); + if (availability && a < *availability) + *availability = a; } return node; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index bde605d..212c6ff 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-19 Jan Hubicka + + PR ipa/94202 + * g++.dg/torture/pr94202.C: New test. + 2020-03-19 Jakub Jelinek PR gcov-profile/94029 diff --git a/gcc/testsuite/g++.dg/torture/pr94202.C b/gcc/testsuite/g++.dg/torture/pr94202.C new file mode 100644 index 0000000..5ed3dcb --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr94202.C @@ -0,0 +1,22 @@ +// { dg-additional-options "-w" } +struct S1 { + virtual ~S1(); + virtual void v(); +}; +struct S2: S1 {}; +struct S3: S1, S2 { void v(); }; +struct S4: S3 { void v(); }; +void S4::v() { S3::v(); } +struct R { + S1 * m; + void f(S2 * x) { + static_cast(x)->v(); + x->v(); + m = x; + } +}; +void f() { + R r; + r.f(new S4); + r.f(new S3); +} -- cgit v1.1 From 3373d3e38eaf807573cd04150a12ab1e43035f4d Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 20 Mar 2020 00:16:30 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 2cdfff0..f4838be 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200319 +20200320 -- cgit v1.1 From 94e2418780f1d13235f3e2e6e5c09dbe821c1ce3 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Thu, 19 Mar 2020 11:06:52 -0400 Subject: c++: Avoid unnecessary empty class copy [94175]. A simple empty class copy is still simple when wrapped in a TARGET_EXPR, so we need to strip that as well. This change also exposed some unnecessary copies in return statements, which when returning by invisible reference led to >>, which gimplify_return_expr didn't like. So we also need to strip the _REF when we eliminate the INIT_EXPR. gcc/cp/ChangeLog 2020-03-19 Jason Merrill PR c++/94175 * cp-gimplify.c (simple_empty_class_p): Look through SIMPLE_TARGET_EXPR_P. (cp_gimplify_expr) [MODIFY_EXPR]: Likewise. [RETURN_EXPR]: Avoid producing 'return *retval;'. * call.c (build_call_a): Strip TARGET_EXPR from empty class arg. * cp-tree.h (SIMPLE_TARGET_EXPR_P): Check that TARGET_EXPR_INITIAL is non-null. --- gcc/cp/ChangeLog | 11 +++++++++++ gcc/cp/call.c | 4 ++++ gcc/cp/cp-gimplify.c | 13 ++++++++++++- gcc/cp/cp-tree.h | 1 + gcc/testsuite/g++.dg/abi/empty30.C | 14 ++++++++++++++ 5 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b5d429b..929e709 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,14 @@ +2020-03-19 Jason Merrill + + PR c++/94175 + * cp-gimplify.c (simple_empty_class_p): Look through + SIMPLE_TARGET_EXPR_P. + (cp_gimplify_expr) [MODIFY_EXPR]: Likewise. + [RETURN_EXPR]: Avoid producing 'return *retval;'. + * call.c (build_call_a): Strip TARGET_EXPR from empty class arg. + * cp-tree.h (SIMPLE_TARGET_EXPR_P): Check that TARGET_EXPR_INITIAL + is non-null. + 2020-03-19 Jakub Jelinek PR c++/93931 diff --git a/gcc/cp/call.c b/gcc/cp/call.c index 1715acc..65a3ea3 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -392,6 +392,10 @@ build_call_a (tree function, int n, tree *argarray) if (is_empty_class (TREE_TYPE (arg)) && simple_empty_class_p (TREE_TYPE (arg), arg, INIT_EXPR)) { + while (TREE_CODE (arg) == TARGET_EXPR) + /* We're disconnecting the initializer from its target, + don't create a temporary. */ + arg = TARGET_EXPR_INITIAL (arg); tree t = build0 (EMPTY_CLASS_EXPR, TREE_TYPE (arg)); arg = build2 (COMPOUND_EXPR, TREE_TYPE (t), arg, t); CALL_EXPR_ARG (function, i) = arg; diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index 87c7e39..aa80384 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -603,6 +603,10 @@ simple_empty_class_p (tree type, tree op, tree_code code) { if (TREE_CODE (op) == COMPOUND_EXPR) return simple_empty_class_p (type, TREE_OPERAND (op, 1), code); + if (SIMPLE_TARGET_EXPR_P (op) + && TYPE_HAS_TRIVIAL_DESTRUCTOR (type)) + /* The TARGET_EXPR is itself a simple copy, look through it. */ + return simple_empty_class_p (type, TARGET_EXPR_INITIAL (op), code); return (TREE_CODE (op) == EMPTY_CLASS_EXPR || code == MODIFY_EXPR @@ -740,6 +744,11 @@ cp_gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) else if (simple_empty_class_p (TREE_TYPE (op0), op1, code)) { + while (TREE_CODE (op1) == TARGET_EXPR) + /* We're disconnecting the initializer from its target, + don't create a temporary. */ + op1 = TARGET_EXPR_INITIAL (op1); + /* Remove any copies of empty classes. Also drop volatile variables on the RHS to avoid infinite recursion from gimplify_expr trying to load the value. */ @@ -754,6 +763,9 @@ cp_gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) gimplify_expr (&TREE_OPERAND (*expr_p, 0), pre_p, post_p, is_gimple_lvalue, fb_lvalue); *expr_p = TREE_OPERAND (*expr_p, 0); + if (code == RETURN_EXPR && REFERENCE_CLASS_P (*expr_p)) + /* Avoid 'return *;' */ + *expr_p = TREE_OPERAND (*expr_p, 0); } /* P0145 says that the RHS is sequenced before the LHS. gimplify_modify_expr gimplifies the RHS before the LHS, but that @@ -924,7 +936,6 @@ cp_gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) || TREE_CODE (TREE_OPERAND (*expr_p, 0)) == MODIFY_EXPR)) { expr_p = &TREE_OPERAND (*expr_p, 0); - code = TREE_CODE (*expr_p); /* Avoid going through the INIT_EXPR case, which can degrade INIT_EXPRs into AGGR_INIT_EXPRs. */ goto modify_expr_case; diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 757cdd8..0783b31 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -5145,6 +5145,7 @@ more_aggr_init_expr_args_p (const aggr_init_expr_arg_iterator *iter) the initializer has void type, it's doing something more complicated. */ #define SIMPLE_TARGET_EXPR_P(NODE) \ (TREE_CODE (NODE) == TARGET_EXPR \ + && TARGET_EXPR_INITIAL (NODE) \ && !VOID_TYPE_P (TREE_TYPE (TARGET_EXPR_INITIAL (NODE)))) /* True if EXPR expresses direct-initialization of a TYPE. */ diff --git a/gcc/testsuite/g++.dg/abi/empty30.C b/gcc/testsuite/g++.dg/abi/empty30.C new file mode 100644 index 0000000..f10d203 --- /dev/null +++ b/gcc/testsuite/g++.dg/abi/empty30.C @@ -0,0 +1,14 @@ +// PR c++/94175 +// { dg-do link } + +struct A {}; +extern A a; + +int i; +__attribute ((noinline, noclone)) +void f(A) { ++i; } + +int main() +{ + f(a); +} -- cgit v1.1 From 4a18f168f47cfa4a41a01aad64a6041eab64ad7b Mon Sep 17 00:00:00 2001 From: Bin Bin Lv Date: Thu, 19 Mar 2020 12:10:44 -0400 Subject: [rs6000] Rewrite the declaration of a variable Rewrite the declaration of toc_section from the source file rs6000.c to its header file for standardizing the code. Bootstrap and regression were done on powerpc64le-linux-gnu (LE) with no regressions. gcc/ChangeLog 2020-03-20 Bin Bin Lv * config/rs6000/rs6000-internal.h (toc_section): Remove the declaration. * config/rs6000/rs6000.h (toc_section): Add the declaration. * config/rs6000/rs6000.c (toc_section): Remove the declaration. --- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index d331b9e..9caef01 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -64,7 +64,6 @@ typedef struct rs6000_stack { extern int need_toc_init; extern char toc_label_name[10]; extern int rs6000_pic_labelno; -extern section *toc_section; #ifdef USING_ELFOS_H extern const char *rs6000_machine; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 2080c7d..4ecf972 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -181,7 +181,6 @@ static GTY(()) section *tls_private_data_section; static GTY(()) section *read_only_private_data_section; static GTY(()) section *sdata2_section; -extern GTY(()) section *toc_section; section *toc_section = 0; /* Describe the vector unit used for modes. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 79b3dd6..1adc371 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2492,6 +2492,7 @@ extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; #ifndef USED_FOR_TARGET extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; extern GTY(()) tree altivec_builtin_mask_for_load; +extern GTY(()) section *toc_section; /* A C structure for machine-specific, per-function data. This is added to the cfun structure. */ -- cgit v1.1 From 05009698eeb925d691a8ebb51539df8d8f28d849 Mon Sep 17 00:00:00 2001 From: Andre Simoes Dias Vieira Date: Fri, 20 Mar 2020 08:25:56 +0000 Subject: gcc, Arm: Fix no_cond issue introduced by MVE This was a matter of mistaken logic in (define_attr "conds" ..). This was setting the conds attribute for any neon instruction to no_cond which was messing up code generation. gcc/ChangeLog: 2020-03-20 Andre Vieira * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. --- gcc/ChangeLog | 4 ++++ gcc/config/arm/arm.md | 8 ++++---- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44e3206..f7672cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-03-20 Andre Vieira + + * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. + 2020-03-19 Jan Hubicka PR ipa/94202 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5387f97..b45109e 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -306,10 +306,10 @@ (eq_attr "type" "call")) (const_string "clob") (if_then_else - (ior (eq_attr "is_neon_type" "no") - (eq_attr "is_mve_type" "no")) - (const_string "nocond") - (const_string "unconditional")))) + (ior (eq_attr "is_neon_type" "yes") + (eq_attr "is_mve_type" "yes")) + (const_string "unconditional") + (const_string "nocond")))) ; Predicable means that the insn can be conditionally executed based on ; an automatically added predicate (additional patterns are generated by -- cgit v1.1 From 4119cd693d27e9dd87c547de75283edd45bf6dce Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 20 Mar 2020 09:33:38 +0100 Subject: store-merging: Fix up -fnon-call-exceptions handling [PR94224] When we are adding a single store into a store group, we are already checking that store->lp_nr matches, but we have also code to add further INTEGER_CST stores into the group right away if the ordering requires that either we put there all or none from a certain set of stores. And in those cases we weren't doing these lp_nr checks, which means we could end up with stores with different lp_nr in the same group, which then ICEs during output_merged_store. 2020-03-20 Jakub Jelinek PR tree-optimization/94224 * gimple-ssa-store-merging.c (imm_store_chain_info::coalesce_immediate): Don't consider overlapping or adjacent INTEGER_CST rhs_code stores as mergeable if they have different lp_nr. * g++.dg/tree-ssa/pr94224.C: New test. --- gcc/ChangeLog | 8 ++++++++ gcc/gimple-ssa-store-merging.c | 4 +++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 +++++++++++++++++++++++++++++++++ 4 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7672cc..00dd10c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-20 Jakub Jelinek + + PR tree-optimization/94224 + * gimple-ssa-store-merging.c + (imm_store_chain_info::coalesce_immediate): Don't consider overlapping + or adjacent INTEGER_CST rhs_code stores as mergeable if they have + different lp_nr. + 2020-03-20 Andre Vieira * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. diff --git a/gcc/gimple-ssa-store-merging.c b/gcc/gimple-ssa-store-merging.c index 4d4f549..83ae6c4 100644 --- a/gcc/gimple-ssa-store-merging.c +++ b/gcc/gimple-ssa-store-merging.c @@ -2773,7 +2773,8 @@ imm_store_chain_info::coalesce_immediate_stores () break; if (info2->order < try_order) { - if (info2->rhs_code != INTEGER_CST) + if (info2->rhs_code != INTEGER_CST + || info2->lp_nr != merged_store->lp_nr) { /* Normally check_no_overlap makes sure this doesn't happen, but if end grows below, @@ -2791,6 +2792,7 @@ imm_store_chain_info::coalesce_immediate_stores () info2->bitpos + info2->bitsize); } else if (info2->rhs_code == INTEGER_CST + && info2->lp_nr == merged_store->lp_nr && !last_iter) { max_order = MAX (max_order, info2->order + 1); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 212c6ff..d11f3fe 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-20 Jakub Jelinek + + PR tree-optimization/94224 + * g++.dg/tree-ssa/pr94224.C: New test. + 2020-03-19 Jan Hubicka PR ipa/94202 diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr94224.C b/gcc/testsuite/g++.dg/tree-ssa/pr94224.C new file mode 100644 index 0000000..5251917 --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/pr94224.C @@ -0,0 +1,34 @@ +// PR tree-optimization/94224 +// { dg-do compile } +// { dg-options "-O2 -fnon-call-exceptions -Wno-return-type" } + +void foo (int, int, long); + +static inline int +bar (int &x) +{ + x = 0; +} + +struct U +{ + int n, p; + long q; + bool *z; + int a; + U () : n (), z (), a (1) {} + ~U () { if (n) foo (p, n, q); } + void baz () { bar (a); } +}; + +struct W +{ + U w[2]; + W () { w[0].baz (); } +}; + +void +qux () +{ + new W; +} -- cgit v1.1 From 0efe7d8796e00a5737017fe472680b653bd83d90 Mon Sep 17 00:00:00 2001 From: Andre Simoes Dias Vieira Date: Fri, 20 Mar 2020 09:07:10 +0000 Subject: gcc, Arm: Fix MVE move from GPR -> GPR This patch fixes the pattern mve_mov for the case where both MVE vectors are in R registers and the move does not get optimized away. I use the same approach as we do for NEON, where we use four register moves. gcc/ChangeLog: 2020-03-20 Andre Vieira * config/arm/mve.md (mve_mov): Fix R->R case. gcc/testsuite/ChangeLog: 2020-03-20 Andre Vieira * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test. --- gcc/ChangeLog | 4 ++++ gcc/config/arm/mve.md | 4 ++-- gcc/testsuite/ChangeLog | 4 ++++ .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 ++++++++++++++++++ 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 00dd10c..ccda62f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-03-20 Andre Vieira + + * config/arm/mve.md (mve_mov): Fix R->R case. + 2020-03-20 Jakub Jelinek PR tree-optimization/94224 diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 5667882..b80a2a6 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -663,7 +663,7 @@ else return "vldrb.8 %q0, %E1"; case 5: - return output_move_neon (operands); + return output_move_quad (operands); case 7: return "vstrb.8 %q1, %E0"; default: @@ -671,7 +671,7 @@ return ""; } } - [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store") + [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store") (set_attr "length" "4,8,8,4,8,8,4,4") (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d11f3fe..a039f96 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-20 Andre Vieira + + * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test. + 2020-03-20 Jakub Jelinek PR tree-optimization/94224 diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c new file mode 100644 index 0000000..791b852 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2 -mfloat-abi=softfp" } */ + +#include "arm_mve.h" + +extern int bar (float16x8_t, float16_t); + +extern void foobar (float16_t); + +int +foo (float16x8_t a, float16_t b) +{ + foobar (b); + return bar (a, b); +} + -- cgit v1.1 From 005f6fc59e5fceb658e11f153402711ee7f12c1a Mon Sep 17 00:00:00 2001 From: Andre Simoes Dias Vieira Date: Fri, 20 Mar 2020 09:10:17 +0000 Subject: gcc, Arm: Fix testisms for MVE testsuite This patch fixes some testism where -mfpu=auto was missing or where we could end up with -mfloat-abi=hard and soft on the same command-line. gcc/testsuite/ChangeLog: 2020-03-20 Andre Vieira * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms. * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. --- gcc/testsuite/ChangeLog | 20 ++++++++++++++++++++ .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_vector_float.c | 3 ++- .../arm/mve/intrinsics/mve_vector_float1.c | 3 ++- .../arm/mve/intrinsics/mve_vector_float2.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_vector_int1.c | 11 ++++++----- .../gcc.target/arm/mve/intrinsics/mve_vector_int2.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_vector_uint.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_vector_uint1.c | 3 ++- .../gcc.target/arm/mve/intrinsics/mve_vector_uint2.c | 3 ++- .../gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c | 5 +++-- 18 files changed, 56 insertions(+), 20 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a039f96..8f8b088 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,25 @@ 2020-03-20 Andre Vieira + * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms. + * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. + +2020-03-20 Andre Vieira + * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test. 2020-03-20 Jakub Jelinek diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c index 17ba616..d552fbd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c index 7b877c4..e40b82e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb" } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c index 85fbb57..e04cb61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c index 23b3683..f52c362 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c index 8f7fa34..1f249ca 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { "" } } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb -mfpu=auto" } */ int foo1 (int value) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c index 7c38d31..03347d4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ float diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c index 773c844..f6291b7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ double diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c index ac51f7f..eac2c84 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c index d41900c..d531901 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c index f02dd8b..bf39fc6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c index dfe08b9..3a63b59 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c index cb96eb8..e15b10b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" @@ -10,7 +11,7 @@ int32x4_t value3; int64x2_t value4; int8x16_t -foo8 () +foo8 (void) { int8x16_t b = value1; return b; @@ -21,7 +22,7 @@ foo8 () /* { dg-final { scan-assembler "vldrb.8*" } } */ int16x8_t -foo16 () +foo16 (void) { int16x8_t b = value2; return b; @@ -32,7 +33,7 @@ foo16 () /* { dg-final { scan-assembler "vldrb.8*" } } */ int32x4_t -foo32 () +foo32 (void) { int32x4_t b = value3; return b; @@ -43,7 +44,7 @@ foo32 () /* { dg-final { scan-assembler "vldrb.8" } } */ int64x2_t -foo64 () +foo64 (void) { int64x2_t b = value4; return b; diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c index 32f589a..a7f66ce 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c index 1957d38..6e2e768 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c index 0561178..d6dba65 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c index 8b4f4cb..7009197 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c index 6c3eda5..2fe8c5f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h" -- cgit v1.1 From 719c864225e28c33a0737a331a772781ce8e6591 Mon Sep 17 00:00:00 2001 From: Andre Simoes Dias Vieira Date: Fri, 20 Mar 2020 09:18:18 +0000 Subject: gcc, Arm: Revert changes to {get,set}_fpscr MVE made changes to {get,set}_fpscr to enable the compiler to optimize unneccesary gets and sets when using these for intrinsics that use and/or write the carry bit. However, these actually get and set the full FPSCR register and are used by fp env intrinsics to modify the fp context. So MVE should not be using these. gcc/ChangeLog: 2020-03-20 Andre Vieira * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vfp.md | 7 +++---- 3 files changed, 10 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ccda62f..ded73b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2020-03-20 Andre Vieira + * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... + (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. + * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. + +2020-03-20 Andre Vieira + * config/arm/mve.md (mve_mov): Fix R->R case. 2020-03-20 Jakub Jelinek diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e76609f..f0b1f46 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,7 +170,6 @@ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. - UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. ]) @@ -217,6 +216,7 @@ VUNSPEC_SLX ; Represent a store-register-release-exclusive. VUNSPEC_LDA ; Represent a store-register-acquire. VUNSPEC_STL ; Represent a store-register-release. + VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index eb6ae7b..dfb1031 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2096,9 +2096,8 @@ ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" - [(set (reg:SI VFPCC_REGNUM) - (unspec_volatile:SI - [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] + VUNSPEC_SET_FPSCR)] "TARGET_VFP_BASE" "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" [(set_attr "type" "mrs")]) @@ -2106,7 +2105,7 @@ ;; Read Floating-point Status and Control Register. (define_insn "get_fpscr" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))] + (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] "TARGET_VFP_BASE" "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" [(set_attr "type" "mrs")]) -- cgit v1.1 From 8fefa21fcf67f30c467eb3cb73d09cb96d0ea6a8 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 20 Mar 2020 10:52:02 +0100 Subject: tree-optimization/94266 - fix object type extraction heuristics This fixes the heuristic deriving an actual object type from a MEM_REFs pointer operand to use the more sensible type of an actual object instead of the pointed to type. 2020-03-20 Richard Biener PR tree-optimization/94266 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the type of the underlying object to adjust for the containing field if available. --- gcc/ChangeLog | 7 +++++++ gcc/gimple-ssa-sprintf.c | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ded73b3..563be35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-20 Richard Biener + + PR tree-optimization/94266 + * gimple-ssa-sprintf.c (get_origin_and_offset): Use the + type of the underlying object to adjust for the containing + field if available. + 2020-03-20 Andre Vieira * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... diff --git a/gcc/gimple-ssa-sprintf.c b/gcc/gimple-ssa-sprintf.c index 13640e0..1879686 100644 --- a/gcc/gimple-ssa-sprintf.c +++ b/gcc/gimple-ssa-sprintf.c @@ -2331,7 +2331,9 @@ get_origin_and_offset (tree x, HOST_WIDE_INT *fldoff, HOST_WIDE_INT *off) if (off) { - tree xtype = TREE_TYPE (TREE_TYPE (x)); + tree xtype + = (TREE_CODE (x) == ADDR_EXPR + ? TREE_TYPE (TREE_OPERAND (x, 0)) : TREE_TYPE (TREE_TYPE (x))); /* The byte offset of the most basic struct member the byte offset *OFF corresponds to, or for a (multidimensional) -- cgit v1.1 From 7d4549b2cd209eb621453ce13be7ffd84ffa720a Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 20 Mar 2020 11:01:13 +0100 Subject: Fix correct offset in ipa_get_jf_ancestor_result. PR ipa/94232 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously build_ref_for_offset function was used and it transforms off to bytes from bits. --- gcc/ChangeLog | 7 +++++++ gcc/ipa-cp.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 563be35..c7b33258 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-03-20 Martin Liska + + PR ipa/94232 + * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously + build_ref_for_offset function was used and it transforms off to bytes + from bits. + 2020-03-20 Richard Biener PR tree-optimization/94266 diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c index 1c17010..c64e910 100644 --- a/gcc/ipa-cp.c +++ b/gcc/ipa-cp.c @@ -1356,9 +1356,10 @@ ipa_get_jf_ancestor_result (struct ipa_jump_func *jfunc, tree input) poly_int64 off = ipa_get_jf_ancestor_offset (jfunc); if (known_eq (off, 0)) return input; + poly_int64 byte_offset = exact_div (off, BITS_PER_UNIT); return build1 (ADDR_EXPR, TREE_TYPE (input), - fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (input)), - input, build_int_cst (ptr_type_node, off))); + fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (input)), input, + build_int_cst (ptr_type_node, byte_offset))); } else return NULL_TREE; -- cgit v1.1 From 3eff57aacfef6e05f55e9dd6ecae3ef8568aaac4 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 11:44:08 +0000 Subject: [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic plus operator. This patch supports following MVE ACLE vaddq intrinsics. The RTL patterns for this intrinsics are added using arithmetic "plus" operator. vaddq_s8, vaddq_s16, vaddq_s32, vaddq_u8, vaddq_u16, vaddq_u32, vaddq_f16, vaddq_f32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vaddq_s8): Define macro. (vaddq_s16): Likewise. (vaddq_s32): Likewise. (vaddq_u8): Likewise. (vaddq_u16): Likewise. (vaddq_u32): Likewise. (vaddq_f16): Likewise. (vaddq_f32): Likewise. (__arm_vaddq_s8): Define intrinsic. (__arm_vaddq_s16): Likewise. (__arm_vaddq_s32): Likewise. (__arm_vaddq_u8): Likewise. (__arm_vaddq_u16): Likewise. (__arm_vaddq_u32): Likewise. (__arm_vaddq_f16): Likewise. (__arm_vaddq_f32): Likewise. (vaddq): Define polymorphic variant. * config/arm/iterators.md (VNIM): Define mode iterator for common types Neon, IWMMXT and MVE. (VNINOTM): Likewise. * config/arm/mve.md (mve_vaddq): Define RTL pattern. (mve_vaddq_f): Define RTL pattern. * config/arm/neon.md (add3): Rename to addv4hf3 RTL pattern. (addv8hf3_neon): Define RTL pattern. * config/arm/vec-common.md (add3): Modify standard add RTL pattern to support MVE. (addv8hf3): Define standard RTL pattern for MVE and Neon. (add3): Modify existing standard add RTL pattern for Neon and IWMMXT. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * gcc.target/arm/mve/intrinsics/vaddq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise. --- gcc/ChangeLog | 33 +++++++++++ gcc/config/arm/arm_mve.h | 66 ++++++++++++++++++++++ gcc/config/arm/iterators.md | 8 +++ gcc/config/arm/mve.md | 28 +++++++++ gcc/config/arm/neon.md | 32 +++++++---- gcc/config/arm/vec-common.md | 42 ++++++++++++-- gcc/testsuite/ChangeLog | 13 +++++ .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 ++++++++ .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 ++++++++ 15 files changed, 383 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7b33258..b98f573 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * config/arm/arm_mve.h (vaddq_s8): Define macro. + (vaddq_s16): Likewise. + (vaddq_s32): Likewise. + (vaddq_u8): Likewise. + (vaddq_u16): Likewise. + (vaddq_u32): Likewise. + (vaddq_f16): Likewise. + (vaddq_f32): Likewise. + (__arm_vaddq_s8): Define intrinsic. + (__arm_vaddq_s16): Likewise. + (__arm_vaddq_s32): Likewise. + (__arm_vaddq_u8): Likewise. + (__arm_vaddq_u16): Likewise. + (__arm_vaddq_u32): Likewise. + (__arm_vaddq_f16): Likewise. + (__arm_vaddq_f32): Likewise. + (vaddq): Define polymorphic variant. + * config/arm/iterators.md (VNIM): Define mode iterator for common types + Neon, IWMMXT and MVE. + (VNINOTM): Likewise. + * config/arm/mve.md (mve_vaddq): Define RTL pattern. + (mve_vaddq_f): Define RTL pattern. + * config/arm/neon.md (add3): Rename to addv4hf3 RTL pattern. + (addv8hf3_neon): Define RTL pattern. + * config/arm/vec-common.md (add3): Modify standard add RTL pattern + to support MVE. + (addv8hf3): Define standard RTL pattern for MVE and Neon. + (add3): Modify existing standard add RTL pattern for Neon and IWMMXT. + 2020-03-20 Martin Liska PR ipa/94232 diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 5ea42bd..55c2569 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1898,6 +1898,14 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrwq_scatter_shifted_offset_p_u32(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p_u32(__base, __offset, __value, __p) #define vstrwq_scatter_shifted_offset_s32(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset_s32(__base, __offset, __value) #define vstrwq_scatter_shifted_offset_u32(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset_u32(__base, __offset, __value) +#define vaddq_s8(__a, __b) __arm_vaddq_s8(__a, __b) +#define vaddq_s16(__a, __b) __arm_vaddq_s16(__a, __b) +#define vaddq_s32(__a, __b) __arm_vaddq_s32(__a, __b) +#define vaddq_u8(__a, __b) __arm_vaddq_u8(__a, __b) +#define vaddq_u16(__a, __b) __arm_vaddq_u16(__a, __b) +#define vaddq_u32(__a, __b) __arm_vaddq_u32(__a, __b) +#define vaddq_f16(__a, __b) __arm_vaddq_f16(__a, __b) +#define vaddq_f32(__a, __b) __arm_vaddq_f32(__a, __b) #endif __extension__ extern __inline void @@ -12341,6 +12349,48 @@ __arm_vstrwq_scatter_shifted_offset_u32 (uint32_t * __base, uint32x4_t __offset, __builtin_mve_vstrwq_scatter_shifted_offset_uv4si ((__builtin_neon_si *) __base, __offset, __value); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_s8 (int8x16_t __a, int8x16_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_s16 (int16x8_t __a, int16x8_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_s32 (int32x4_t __a, int32x4_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + return __a + __b; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -14707,6 +14757,20 @@ __arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offs __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __a + __b; +} + #endif enum { @@ -15186,6 +15250,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t), __ARM_mve_coerce(p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t), __ARM_mve_coerce(p1, float32x4_t)), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 5c1a11b..f3cbc0d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -66,6 +66,14 @@ ;; Integer and float modes supported by Neon and IWMMXT. (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) +;; Integer and float modes supported by Neon, IWMMXT and MVE, used by +;; arithmetic epxand patterns. +(define_mode_iterator VNIM [V16QI V8HI V4SI V4SF]) + +;; Integer and float modes supported by Neon and IWMMXT but not MVE, used by +;; arithmetic epxand patterns. +(define_mode_iterator VNINOTM [V2SI V4HI V8QI V2SF V2DI]) + ;; Integer and float modes supported by Neon, IWMMXT and MVE. (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b80a2a6..77b36a7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9643,3 +9643,31 @@ return ""; } [(set_attr "length" "4")]) + +;; +;; [vaddq_s, vaddq_u]) +;; +(define_insn "mve_vaddq" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" + "vadd.i%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddq_f]) +;; +(define_insn "mve_vaddq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vadd.f%# %q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index fbfeef2..272e6c1 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -519,18 +519,30 @@ ;; As with SFmode, full support for HFmode vector arithmetic is only available ;; when flag-unsafe-math-optimizations is enabled. -(define_insn "add3" +;; Add pattern with modes V8HF and V4HF is split into separate patterns to add +;; support for standard pattern addv8hf3 in MVE. Following pattern is called +;; from "addv8hf3" standard pattern inside vec-common.md file. + +(define_insn "addv8hf3_neon" [(set - (match_operand:VH 0 "s_register_operand" "=w") - (plus:VH - (match_operand:VH 1 "s_register_operand" "w") - (match_operand:VH 2 "s_register_operand" "w")))] + (match_operand:V8HF 0 "s_register_operand" "=w") + (plus:V8HF + (match_operand:V8HF 1 "s_register_operand" "w") + (match_operand:V8HF 2 "s_register_operand" "w")))] "TARGET_NEON_FP16INST && flag_unsafe_math_optimizations" - "vadd.\t%0, %1, %2" - [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_addsub_s") - (const_string "neon_add")))] + "vadd.f16\t%0, %1, %2" + [(set_attr "type" "neon_fp_addsub_s_q")] +) + +(define_insn "addv4hf3" + [(set + (match_operand:V4HF 0 "s_register_operand" "=w") + (plus:V4HF + (match_operand:V4HF 1 "s_register_operand" "w") + (match_operand:V4HF 2 "s_register_operand" "w")))] + "TARGET_NEON_FP16INST && flag_unsafe_math_optimizations" + "vadd.f16\t%0, %1, %2" + [(set_attr "type" "neon_fp_addsub_s_q")] ) (define_insn "add3_fp16" diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 916e491..786daa6 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -77,19 +77,51 @@ } }) -;; Vector arithmetic. Expanders are blank, then unnamed insns implement -;; patterns separately for IWMMXT and Neon. +;; Vector arithmetic. Expanders are blank, then unnamed insns implement +;; patterns separately for Neon, IWMMXT and MVE. (define_expand "add3" - [(set (match_operand:VALL 0 "s_register_operand") - (plus:VALL (match_operand:VALL 1 "s_register_operand") - (match_operand:VALL 2 "s_register_operand")))] + [(set (match_operand:VNIM 0 "s_register_operand") + (plus:VNIM (match_operand:VNIM 1 "s_register_operand") + (match_operand:VNIM 2 "s_register_operand")))] + "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) + || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) + || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE(mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE(mode))" +{ +}) + +;; Vector arithmetic. Expanders are blank, then unnamed insns implement +;; patterns separately for Neon and MVE. + +(define_expand "addv8hf3" + [(set (match_operand:V8HF 0 "s_register_operand") + (plus:V8HF (match_operand:V8HF 1 "s_register_operand") + (match_operand:V8HF 2 "s_register_operand")))] + "(TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE(V8HFmode)) + || (TARGET_NEON_FP16INST && flag_unsafe_math_optimizations)" +{ + if (TARGET_NEON_FP16INST && flag_unsafe_math_optimizations) + emit_insn (gen_addv8hf3_neon (operands[0], operands[1], operands[2])); +}) + +;; Vector arithmetic. Expanders are blank, then unnamed insns implement +;; patterns separately for Neon and IWMMXT. + +(define_expand "add3" + [(set (match_operand:VNINOTM 0 "s_register_operand") + (plus:VNINOTM (match_operand:VNINOTM 1 "s_register_operand") + (match_operand:VNINOTM 2 "s_register_operand")))] "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) || flag_unsafe_math_optimizations)) || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" { }) +;; Vector arithmetic. Expanders are blank, then unnamed insns implement +;; patterns separately for IWMMXT and Neon. + (define_expand "sub3" [(set (match_operand:VALL 0 "s_register_operand") (minus:VALL (match_operand:VALL 1 "s_register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8f8b088..e4aeb83 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * gcc.target/arm/mve/intrinsics/vaddq_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise. + 2020-03-20 Andre Vieira * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c new file mode 100644 index 0000000..53b84d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b) +{ + return vaddq_f16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c new file mode 100644 index 0000000..9bb7d1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b) +{ + return vaddq_f32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c new file mode 100644 index 0000000..885473c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b) +{ + return vaddq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c new file mode 100644 index 0000000..90ea501 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b) +{ + return vaddq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c new file mode 100644 index 0000000..dbde92a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b) +{ + return vaddq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c new file mode 100644 index 0000000..bc96673 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b) +{ + return vaddq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c new file mode 100644 index 0000000..ed262c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b) +{ + return vaddq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c new file mode 100644 index 0000000..b12e657 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b) +{ + return vaddq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b) +{ + return vaddq (a, b); +} + +/* { dg-final { scan-assembler "vadd.i8" } } */ -- cgit v1.1 From 85a94e8790198cdafc6f2af8224b273075bab84d Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 11:50:21 +0000 Subject: [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. This patch supports following MVE ACLE intrinsics. vreinterpretq_s16_s32, vreinterpretq_s16_s64, vreinterpretq_s16_s8, vreinterpretq_s16_u16, vreinterpretq_s16_u32, vreinterpretq_s16_u64, vreinterpretq_s16_u8, vreinterpretq_s32_s16, vreinterpretq_s32_s64, vreinterpretq_s32_s8, vreinterpretq_s32_u16, vreinterpretq_s32_u32, vreinterpretq_s32_u64, vreinterpretq_s32_u8, vreinterpretq_s64_s16, vreinterpretq_s64_s32, vreinterpretq_s64_s8, vreinterpretq_s64_u16, vreinterpretq_s64_u32, vreinterpretq_s64_u64, vreinterpretq_s64_u8, vreinterpretq_s8_s16, vreinterpretq_s8_s32, vreinterpretq_s8_s64, vreinterpretq_s8_u16, vreinterpretq_s8_u32, vreinterpretq_s8_u64, vreinterpretq_s8_u8, vreinterpretq_u16_s16, vreinterpretq_u16_s32, vreinterpretq_u16_s64, vreinterpretq_u16_s8, vreinterpretq_u16_u32, vreinterpretq_u16_u64, vreinterpretq_u16_u8, vreinterpretq_u32_s16, vreinterpretq_u32_s32, vreinterpretq_u32_s64, vreinterpretq_u32_s8, vreinterpretq_u32_u16, vreinterpretq_u32_u64, vreinterpretq_u32_u8, vreinterpretq_u64_s16, vreinterpretq_u64_s32, vreinterpretq_u64_s64, vreinterpretq_u64_s8, vreinterpretq_u64_u16, vreinterpretq_u64_u32, vreinterpretq_u64_u8, vreinterpretq_u8_s16, vreinterpretq_u8_s32, vreinterpretq_u8_s64, vreinterpretq_u8_s8, vreinterpretq_u8_u16, vreinterpretq_u8_u32, vreinterpretq_u8_u64, vreinterpretq_s32_f16, vreinterpretq_s32_f32, vreinterpretq_u16_f16, vreinterpretq_u16_f32, vreinterpretq_u32_f16, vreinterpretq_u32_f32, vreinterpretq_u64_f16, vreinterpretq_u64_f32, vreinterpretq_u8_f16, vreinterpretq_u8_f32, vreinterpretq_f16_f32, vreinterpretq_f16_s16, vreinterpretq_f16_s32, vreinterpretq_f16_s64, vreinterpretq_f16_s8, vreinterpretq_f16_u16, vreinterpretq_f16_u32, vreinterpretq_f16_u64, vreinterpretq_f16_u8, vreinterpretq_f32_f16, vreinterpretq_f32_s16, vreinterpretq_f32_s32, vreinterpretq_f32_s64, vreinterpretq_f32_s8, vreinterpretq_f32_u16, vreinterpretq_f32_u32, vreinterpretq_f32_u64, vreinterpretq_f32_u8, vreinterpretq_s16_f16, vreinterpretq_s16_f32, vreinterpretq_s64_f16, vreinterpretq_s64_f32, vreinterpretq_s8_f16, vreinterpretq_s8_f32, vuninitializedq_u8, vuninitializedq_u16, vuninitializedq_u32, vuninitializedq_u64, vuninitializedq_s8, vuninitializedq_s16, vuninitializedq_s32, vuninitializedq_s64, vuninitializedq_f16, vuninitializedq_f32 and vuninitializedq. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. (vreinterpretq_s16_s64): Likewise. (vreinterpretq_s16_s8): Likewise. (vreinterpretq_s16_u16): Likewise. (vreinterpretq_s16_u32): Likewise. (vreinterpretq_s16_u64): Likewise. (vreinterpretq_s16_u8): Likewise. (vreinterpretq_s32_s16): Likewise. (vreinterpretq_s32_s64): Likewise. (vreinterpretq_s32_s8): Likewise. (vreinterpretq_s32_u16): Likewise. (vreinterpretq_s32_u32): Likewise. (vreinterpretq_s32_u64): Likewise. (vreinterpretq_s32_u8): Likewise. (vreinterpretq_s64_s16): Likewise. (vreinterpretq_s64_s32): Likewise. (vreinterpretq_s64_s8): Likewise. (vreinterpretq_s64_u16): Likewise. (vreinterpretq_s64_u32): Likewise. (vreinterpretq_s64_u64): Likewise. (vreinterpretq_s64_u8): Likewise. (vreinterpretq_s8_s16): Likewise. (vreinterpretq_s8_s32): Likewise. (vreinterpretq_s8_s64): Likewise. (vreinterpretq_s8_u16): Likewise. (vreinterpretq_s8_u32): Likewise. (vreinterpretq_s8_u64): Likewise. (vreinterpretq_s8_u8): Likewise. (vreinterpretq_u16_s16): Likewise. (vreinterpretq_u16_s32): Likewise. (vreinterpretq_u16_s64): Likewise. (vreinterpretq_u16_s8): Likewise. (vreinterpretq_u16_u32): Likewise. (vreinterpretq_u16_u64): Likewise. (vreinterpretq_u16_u8): Likewise. (vreinterpretq_u32_s16): Likewise. (vreinterpretq_u32_s32): Likewise. (vreinterpretq_u32_s64): Likewise. (vreinterpretq_u32_s8): Likewise. (vreinterpretq_u32_u16): Likewise. (vreinterpretq_u32_u64): Likewise. (vreinterpretq_u32_u8): Likewise. (vreinterpretq_u64_s16): Likewise. (vreinterpretq_u64_s32): Likewise. (vreinterpretq_u64_s64): Likewise. (vreinterpretq_u64_s8): Likewise. (vreinterpretq_u64_u16): Likewise. (vreinterpretq_u64_u32): Likewise. (vreinterpretq_u64_u8): Likewise. (vreinterpretq_u8_s16): Likewise. (vreinterpretq_u8_s32): Likewise. (vreinterpretq_u8_s64): Likewise. (vreinterpretq_u8_s8): Likewise. (vreinterpretq_u8_u16): Likewise. (vreinterpretq_u8_u32): Likewise. (vreinterpretq_u8_u64): Likewise. (vreinterpretq_s32_f16): Likewise. (vreinterpretq_s32_f32): Likewise. (vreinterpretq_u16_f16): Likewise. (vreinterpretq_u16_f32): Likewise. (vreinterpretq_u32_f16): Likewise. (vreinterpretq_u32_f32): Likewise. (vreinterpretq_u64_f16): Likewise. (vreinterpretq_u64_f32): Likewise. (vreinterpretq_u8_f16): Likewise. (vreinterpretq_u8_f32): Likewise. (vreinterpretq_f16_f32): Likewise. (vreinterpretq_f16_s16): Likewise. (vreinterpretq_f16_s32): Likewise. (vreinterpretq_f16_s64): Likewise. (vreinterpretq_f16_s8): Likewise. (vreinterpretq_f16_u16): Likewise. (vreinterpretq_f16_u32): Likewise. (vreinterpretq_f16_u64): Likewise. (vreinterpretq_f16_u8): Likewise. (vreinterpretq_f32_f16): Likewise. (vreinterpretq_f32_s16): Likewise. (vreinterpretq_f32_s32): Likewise. (vreinterpretq_f32_s64): Likewise. (vreinterpretq_f32_s8): Likewise. (vreinterpretq_f32_u16): Likewise. (vreinterpretq_f32_u32): Likewise. (vreinterpretq_f32_u64): Likewise. (vreinterpretq_f32_u8): Likewise. (vreinterpretq_s16_f16): Likewise. (vreinterpretq_s16_f32): Likewise. (vreinterpretq_s64_f16): Likewise. (vreinterpretq_s64_f32): Likewise. (vreinterpretq_s8_f16): Likewise. (vreinterpretq_s8_f32): Likewise. (vuninitializedq_u8): Likewise. (vuninitializedq_u16): Likewise. (vuninitializedq_u32): Likewise. (vuninitializedq_u64): Likewise. (vuninitializedq_s8): Likewise. (vuninitializedq_s16): Likewise. (vuninitializedq_s32): Likewise. (vuninitializedq_s64): Likewise. (vuninitializedq_f16): Likewise. (vuninitializedq_f32): Likewise. (__arm_vuninitializedq_u8): Define intrinsic. (__arm_vuninitializedq_u16): Likewise. (__arm_vuninitializedq_u32): Likewise. (__arm_vuninitializedq_u64): Likewise. (__arm_vuninitializedq_s8): Likewise. (__arm_vuninitializedq_s16): Likewise. (__arm_vuninitializedq_s32): Likewise. (__arm_vuninitializedq_s64): Likewise. (__arm_vreinterpretq_s16_s32): Likewise. (__arm_vreinterpretq_s16_s64): Likewise. (__arm_vreinterpretq_s16_s8): Likewise. (__arm_vreinterpretq_s16_u16): Likewise. (__arm_vreinterpretq_s16_u32): Likewise. (__arm_vreinterpretq_s16_u64): Likewise. (__arm_vreinterpretq_s16_u8): Likewise. (__arm_vreinterpretq_s32_s16): Likewise. (__arm_vreinterpretq_s32_s64): Likewise. (__arm_vreinterpretq_s32_s8): Likewise. (__arm_vreinterpretq_s32_u16): Likewise. (__arm_vreinterpretq_s32_u32): Likewise. (__arm_vreinterpretq_s32_u64): Likewise. (__arm_vreinterpretq_s32_u8): Likewise. (__arm_vreinterpretq_s64_s16): Likewise. (__arm_vreinterpretq_s64_s32): Likewise. (__arm_vreinterpretq_s64_s8): Likewise. (__arm_vreinterpretq_s64_u16): Likewise. (__arm_vreinterpretq_s64_u32): Likewise. (__arm_vreinterpretq_s64_u64): Likewise. (__arm_vreinterpretq_s64_u8): Likewise. (__arm_vreinterpretq_s8_s16): Likewise. (__arm_vreinterpretq_s8_s32): Likewise. (__arm_vreinterpretq_s8_s64): Likewise. (__arm_vreinterpretq_s8_u16): Likewise. (__arm_vreinterpretq_s8_u32): Likewise. (__arm_vreinterpretq_s8_u64): Likewise. (__arm_vreinterpretq_s8_u8): Likewise. (__arm_vreinterpretq_u16_s16): Likewise. (__arm_vreinterpretq_u16_s32): Likewise. (__arm_vreinterpretq_u16_s64): Likewise. (__arm_vreinterpretq_u16_s8): Likewise. (__arm_vreinterpretq_u16_u32): Likewise. (__arm_vreinterpretq_u16_u64): Likewise. (__arm_vreinterpretq_u16_u8): Likewise. (__arm_vreinterpretq_u32_s16): Likewise. (__arm_vreinterpretq_u32_s32): Likewise. (__arm_vreinterpretq_u32_s64): Likewise. (__arm_vreinterpretq_u32_s8): Likewise. (__arm_vreinterpretq_u32_u16): Likewise. (__arm_vreinterpretq_u32_u64): Likewise. (__arm_vreinterpretq_u32_u8): Likewise. (__arm_vreinterpretq_u64_s16): Likewise. (__arm_vreinterpretq_u64_s32): Likewise. (__arm_vreinterpretq_u64_s64): Likewise. (__arm_vreinterpretq_u64_s8): Likewise. (__arm_vreinterpretq_u64_u16): Likewise. (__arm_vreinterpretq_u64_u32): Likewise. (__arm_vreinterpretq_u64_u8): Likewise. (__arm_vreinterpretq_u8_s16): Likewise. (__arm_vreinterpretq_u8_s32): Likewise. (__arm_vreinterpretq_u8_s64): Likewise. (__arm_vreinterpretq_u8_s8): Likewise. (__arm_vreinterpretq_u8_u16): Likewise. (__arm_vreinterpretq_u8_u32): Likewise. (__arm_vreinterpretq_u8_u64): Likewise. (__arm_vuninitializedq_f16): Likewise. (__arm_vuninitializedq_f32): Likewise. (__arm_vreinterpretq_s32_f16): Likewise. (__arm_vreinterpretq_s32_f32): Likewise. (__arm_vreinterpretq_s16_f16): Likewise. (__arm_vreinterpretq_s16_f32): Likewise. (__arm_vreinterpretq_s64_f16): Likewise. (__arm_vreinterpretq_s64_f32): Likewise. (__arm_vreinterpretq_s8_f16): Likewise. (__arm_vreinterpretq_s8_f32): Likewise. (__arm_vreinterpretq_u16_f16): Likewise. (__arm_vreinterpretq_u16_f32): Likewise. (__arm_vreinterpretq_u32_f16): Likewise. (__arm_vreinterpretq_u32_f32): Likewise. (__arm_vreinterpretq_u64_f16): Likewise. (__arm_vreinterpretq_u64_f32): Likewise. (__arm_vreinterpretq_u8_f16): Likewise. (__arm_vreinterpretq_u8_f32): Likewise. (__arm_vreinterpretq_f16_f32): Likewise. (__arm_vreinterpretq_f16_s16): Likewise. (__arm_vreinterpretq_f16_s32): Likewise. (__arm_vreinterpretq_f16_s64): Likewise. (__arm_vreinterpretq_f16_s8): Likewise. (__arm_vreinterpretq_f16_u16): Likewise. (__arm_vreinterpretq_f16_u32): Likewise. (__arm_vreinterpretq_f16_u64): Likewise. (__arm_vreinterpretq_f16_u8): Likewise. (__arm_vreinterpretq_f32_f16): Likewise. (__arm_vreinterpretq_f32_s16): Likewise. (__arm_vreinterpretq_f32_s32): Likewise. (__arm_vreinterpretq_f32_s64): Likewise. (__arm_vreinterpretq_f32_s8): Likewise. (__arm_vreinterpretq_f32_u16): Likewise. (__arm_vreinterpretq_f32_u32): Likewise. (__arm_vreinterpretq_f32_u64): Likewise. (__arm_vreinterpretq_f32_u8): Likewise. (vuninitializedq): Define polymorphic variant. (vreinterpretq_f16): Likewise. (vreinterpretq_f32): Likewise. (vreinterpretq_s16): Likewise. (vreinterpretq_s32): Likewise. (vreinterpretq_s64): Likewise. (vreinterpretq_s8): Likewise. (vreinterpretq_u16): Likewise. (vreinterpretq_u32): Likewise. (vreinterpretq_u64): Likewise. (vreinterpretq_u8): Likewise. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: New test. * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. --- gcc/ChangeLog | 214 ++++ gcc/config/arm/arm_mve.h | 1065 ++++++++++++++++++++ gcc/testsuite/ChangeLog | 21 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + 17 files changed, 1844 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b98f573..55b5b08 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,218 @@ 2020-03-20 Srinath Parvathaneni + + * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. + (vreinterpretq_s16_s64): Likewise. + (vreinterpretq_s16_s8): Likewise. + (vreinterpretq_s16_u16): Likewise. + (vreinterpretq_s16_u32): Likewise. + (vreinterpretq_s16_u64): Likewise. + (vreinterpretq_s16_u8): Likewise. + (vreinterpretq_s32_s16): Likewise. + (vreinterpretq_s32_s64): Likewise. + (vreinterpretq_s32_s8): Likewise. + (vreinterpretq_s32_u16): Likewise. + (vreinterpretq_s32_u32): Likewise. + (vreinterpretq_s32_u64): Likewise. + (vreinterpretq_s32_u8): Likewise. + (vreinterpretq_s64_s16): Likewise. + (vreinterpretq_s64_s32): Likewise. + (vreinterpretq_s64_s8): Likewise. + (vreinterpretq_s64_u16): Likewise. + (vreinterpretq_s64_u32): Likewise. + (vreinterpretq_s64_u64): Likewise. + (vreinterpretq_s64_u8): Likewise. + (vreinterpretq_s8_s16): Likewise. + (vreinterpretq_s8_s32): Likewise. + (vreinterpretq_s8_s64): Likewise. + (vreinterpretq_s8_u16): Likewise. + (vreinterpretq_s8_u32): Likewise. + (vreinterpretq_s8_u64): Likewise. + (vreinterpretq_s8_u8): Likewise. + (vreinterpretq_u16_s16): Likewise. + (vreinterpretq_u16_s32): Likewise. + (vreinterpretq_u16_s64): Likewise. + (vreinterpretq_u16_s8): Likewise. + (vreinterpretq_u16_u32): Likewise. + (vreinterpretq_u16_u64): Likewise. + (vreinterpretq_u16_u8): Likewise. + (vreinterpretq_u32_s16): Likewise. + (vreinterpretq_u32_s32): Likewise. + (vreinterpretq_u32_s64): Likewise. + (vreinterpretq_u32_s8): Likewise. + (vreinterpretq_u32_u16): Likewise. + (vreinterpretq_u32_u64): Likewise. + (vreinterpretq_u32_u8): Likewise. + (vreinterpretq_u64_s16): Likewise. + (vreinterpretq_u64_s32): Likewise. + (vreinterpretq_u64_s64): Likewise. + (vreinterpretq_u64_s8): Likewise. + (vreinterpretq_u64_u16): Likewise. + (vreinterpretq_u64_u32): Likewise. + (vreinterpretq_u64_u8): Likewise. + (vreinterpretq_u8_s16): Likewise. + (vreinterpretq_u8_s32): Likewise. + (vreinterpretq_u8_s64): Likewise. + (vreinterpretq_u8_s8): Likewise. + (vreinterpretq_u8_u16): Likewise. + (vreinterpretq_u8_u32): Likewise. + (vreinterpretq_u8_u64): Likewise. + (vreinterpretq_s32_f16): Likewise. + (vreinterpretq_s32_f32): Likewise. + (vreinterpretq_u16_f16): Likewise. + (vreinterpretq_u16_f32): Likewise. + (vreinterpretq_u32_f16): Likewise. + (vreinterpretq_u32_f32): Likewise. + (vreinterpretq_u64_f16): Likewise. + (vreinterpretq_u64_f32): Likewise. + (vreinterpretq_u8_f16): Likewise. + (vreinterpretq_u8_f32): Likewise. + (vreinterpretq_f16_f32): Likewise. + (vreinterpretq_f16_s16): Likewise. + (vreinterpretq_f16_s32): Likewise. + (vreinterpretq_f16_s64): Likewise. + (vreinterpretq_f16_s8): Likewise. + (vreinterpretq_f16_u16): Likewise. + (vreinterpretq_f16_u32): Likewise. + (vreinterpretq_f16_u64): Likewise. + (vreinterpretq_f16_u8): Likewise. + (vreinterpretq_f32_f16): Likewise. + (vreinterpretq_f32_s16): Likewise. + (vreinterpretq_f32_s32): Likewise. + (vreinterpretq_f32_s64): Likewise. + (vreinterpretq_f32_s8): Likewise. + (vreinterpretq_f32_u16): Likewise. + (vreinterpretq_f32_u32): Likewise. + (vreinterpretq_f32_u64): Likewise. + (vreinterpretq_f32_u8): Likewise. + (vreinterpretq_s16_f16): Likewise. + (vreinterpretq_s16_f32): Likewise. + (vreinterpretq_s64_f16): Likewise. + (vreinterpretq_s64_f32): Likewise. + (vreinterpretq_s8_f16): Likewise. + (vreinterpretq_s8_f32): Likewise. + (vuninitializedq_u8): Likewise. + (vuninitializedq_u16): Likewise. + (vuninitializedq_u32): Likewise. + (vuninitializedq_u64): Likewise. + (vuninitializedq_s8): Likewise. + (vuninitializedq_s16): Likewise. + (vuninitializedq_s32): Likewise. + (vuninitializedq_s64): Likewise. + (vuninitializedq_f16): Likewise. + (vuninitializedq_f32): Likewise. + (__arm_vuninitializedq_u8): Define intrinsic. + (__arm_vuninitializedq_u16): Likewise. + (__arm_vuninitializedq_u32): Likewise. + (__arm_vuninitializedq_u64): Likewise. + (__arm_vuninitializedq_s8): Likewise. + (__arm_vuninitializedq_s16): Likewise. + (__arm_vuninitializedq_s32): Likewise. + (__arm_vuninitializedq_s64): Likewise. + (__arm_vreinterpretq_s16_s32): Likewise. + (__arm_vreinterpretq_s16_s64): Likewise. + (__arm_vreinterpretq_s16_s8): Likewise. + (__arm_vreinterpretq_s16_u16): Likewise. + (__arm_vreinterpretq_s16_u32): Likewise. + (__arm_vreinterpretq_s16_u64): Likewise. + (__arm_vreinterpretq_s16_u8): Likewise. + (__arm_vreinterpretq_s32_s16): Likewise. + (__arm_vreinterpretq_s32_s64): Likewise. + (__arm_vreinterpretq_s32_s8): Likewise. + (__arm_vreinterpretq_s32_u16): Likewise. + (__arm_vreinterpretq_s32_u32): Likewise. + (__arm_vreinterpretq_s32_u64): Likewise. + (__arm_vreinterpretq_s32_u8): Likewise. + (__arm_vreinterpretq_s64_s16): Likewise. + (__arm_vreinterpretq_s64_s32): Likewise. + (__arm_vreinterpretq_s64_s8): Likewise. + (__arm_vreinterpretq_s64_u16): Likewise. + (__arm_vreinterpretq_s64_u32): Likewise. + (__arm_vreinterpretq_s64_u64): Likewise. + (__arm_vreinterpretq_s64_u8): Likewise. + (__arm_vreinterpretq_s8_s16): Likewise. + (__arm_vreinterpretq_s8_s32): Likewise. + (__arm_vreinterpretq_s8_s64): Likewise. + (__arm_vreinterpretq_s8_u16): Likewise. + (__arm_vreinterpretq_s8_u32): Likewise. + (__arm_vreinterpretq_s8_u64): Likewise. + (__arm_vreinterpretq_s8_u8): Likewise. + (__arm_vreinterpretq_u16_s16): Likewise. + (__arm_vreinterpretq_u16_s32): Likewise. + (__arm_vreinterpretq_u16_s64): Likewise. + (__arm_vreinterpretq_u16_s8): Likewise. + (__arm_vreinterpretq_u16_u32): Likewise. + (__arm_vreinterpretq_u16_u64): Likewise. + (__arm_vreinterpretq_u16_u8): Likewise. + (__arm_vreinterpretq_u32_s16): Likewise. + (__arm_vreinterpretq_u32_s32): Likewise. + (__arm_vreinterpretq_u32_s64): Likewise. + (__arm_vreinterpretq_u32_s8): Likewise. + (__arm_vreinterpretq_u32_u16): Likewise. + (__arm_vreinterpretq_u32_u64): Likewise. + (__arm_vreinterpretq_u32_u8): Likewise. + (__arm_vreinterpretq_u64_s16): Likewise. + (__arm_vreinterpretq_u64_s32): Likewise. + (__arm_vreinterpretq_u64_s64): Likewise. + (__arm_vreinterpretq_u64_s8): Likewise. + (__arm_vreinterpretq_u64_u16): Likewise. + (__arm_vreinterpretq_u64_u32): Likewise. + (__arm_vreinterpretq_u64_u8): Likewise. + (__arm_vreinterpretq_u8_s16): Likewise. + (__arm_vreinterpretq_u8_s32): Likewise. + (__arm_vreinterpretq_u8_s64): Likewise. + (__arm_vreinterpretq_u8_s8): Likewise. + (__arm_vreinterpretq_u8_u16): Likewise. + (__arm_vreinterpretq_u8_u32): Likewise. + (__arm_vreinterpretq_u8_u64): Likewise. + (__arm_vuninitializedq_f16): Likewise. + (__arm_vuninitializedq_f32): Likewise. + (__arm_vreinterpretq_s32_f16): Likewise. + (__arm_vreinterpretq_s32_f32): Likewise. + (__arm_vreinterpretq_s16_f16): Likewise. + (__arm_vreinterpretq_s16_f32): Likewise. + (__arm_vreinterpretq_s64_f16): Likewise. + (__arm_vreinterpretq_s64_f32): Likewise. + (__arm_vreinterpretq_s8_f16): Likewise. + (__arm_vreinterpretq_s8_f32): Likewise. + (__arm_vreinterpretq_u16_f16): Likewise. + (__arm_vreinterpretq_u16_f32): Likewise. + (__arm_vreinterpretq_u32_f16): Likewise. + (__arm_vreinterpretq_u32_f32): Likewise. + (__arm_vreinterpretq_u64_f16): Likewise. + (__arm_vreinterpretq_u64_f32): Likewise. + (__arm_vreinterpretq_u8_f16): Likewise. + (__arm_vreinterpretq_u8_f32): Likewise. + (__arm_vreinterpretq_f16_f32): Likewise. + (__arm_vreinterpretq_f16_s16): Likewise. + (__arm_vreinterpretq_f16_s32): Likewise. + (__arm_vreinterpretq_f16_s64): Likewise. + (__arm_vreinterpretq_f16_s8): Likewise. + (__arm_vreinterpretq_f16_u16): Likewise. + (__arm_vreinterpretq_f16_u32): Likewise. + (__arm_vreinterpretq_f16_u64): Likewise. + (__arm_vreinterpretq_f16_u8): Likewise. + (__arm_vreinterpretq_f32_f16): Likewise. + (__arm_vreinterpretq_f32_s16): Likewise. + (__arm_vreinterpretq_f32_s32): Likewise. + (__arm_vreinterpretq_f32_s64): Likewise. + (__arm_vreinterpretq_f32_s8): Likewise. + (__arm_vreinterpretq_f32_u16): Likewise. + (__arm_vreinterpretq_f32_u32): Likewise. + (__arm_vreinterpretq_f32_u64): Likewise. + (__arm_vreinterpretq_f32_u8): Likewise. + (vuninitializedq): Define polymorphic variant. + (vreinterpretq_f16): Likewise. + (vreinterpretq_f32): Likewise. + (vreinterpretq_s16): Likewise. + (vreinterpretq_s32): Likewise. + (vreinterpretq_s64): Likewise. + (vreinterpretq_s8): Likewise. + (vreinterpretq_u16): Likewise. + (vreinterpretq_u32): Likewise. + (vreinterpretq_u64): Likewise. + (vreinterpretq_u8): Likewise. + +2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 55c2569..916565c 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1906,6 +1906,106 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vaddq_u32(__a, __b) __arm_vaddq_u32(__a, __b) #define vaddq_f16(__a, __b) __arm_vaddq_f16(__a, __b) #define vaddq_f32(__a, __b) __arm_vaddq_f32(__a, __b) +#define vreinterpretq_s16_s32(__a) __arm_vreinterpretq_s16_s32(__a) +#define vreinterpretq_s16_s64(__a) __arm_vreinterpretq_s16_s64(__a) +#define vreinterpretq_s16_s8(__a) __arm_vreinterpretq_s16_s8(__a) +#define vreinterpretq_s16_u16(__a) __arm_vreinterpretq_s16_u16(__a) +#define vreinterpretq_s16_u32(__a) __arm_vreinterpretq_s16_u32(__a) +#define vreinterpretq_s16_u64(__a) __arm_vreinterpretq_s16_u64(__a) +#define vreinterpretq_s16_u8(__a) __arm_vreinterpretq_s16_u8(__a) +#define vreinterpretq_s32_s16(__a) __arm_vreinterpretq_s32_s16(__a) +#define vreinterpretq_s32_s64(__a) __arm_vreinterpretq_s32_s64(__a) +#define vreinterpretq_s32_s8(__a) __arm_vreinterpretq_s32_s8(__a) +#define vreinterpretq_s32_u16(__a) __arm_vreinterpretq_s32_u16(__a) +#define vreinterpretq_s32_u32(__a) __arm_vreinterpretq_s32_u32(__a) +#define vreinterpretq_s32_u64(__a) __arm_vreinterpretq_s32_u64(__a) +#define vreinterpretq_s32_u8(__a) __arm_vreinterpretq_s32_u8(__a) +#define vreinterpretq_s64_s16(__a) __arm_vreinterpretq_s64_s16(__a) +#define vreinterpretq_s64_s32(__a) __arm_vreinterpretq_s64_s32(__a) +#define vreinterpretq_s64_s8(__a) __arm_vreinterpretq_s64_s8(__a) +#define vreinterpretq_s64_u16(__a) __arm_vreinterpretq_s64_u16(__a) +#define vreinterpretq_s64_u32(__a) __arm_vreinterpretq_s64_u32(__a) +#define vreinterpretq_s64_u64(__a) __arm_vreinterpretq_s64_u64(__a) +#define vreinterpretq_s64_u8(__a) __arm_vreinterpretq_s64_u8(__a) +#define vreinterpretq_s8_s16(__a) __arm_vreinterpretq_s8_s16(__a) +#define vreinterpretq_s8_s32(__a) __arm_vreinterpretq_s8_s32(__a) +#define vreinterpretq_s8_s64(__a) __arm_vreinterpretq_s8_s64(__a) +#define vreinterpretq_s8_u16(__a) __arm_vreinterpretq_s8_u16(__a) +#define vreinterpretq_s8_u32(__a) __arm_vreinterpretq_s8_u32(__a) +#define vreinterpretq_s8_u64(__a) __arm_vreinterpretq_s8_u64(__a) +#define vreinterpretq_s8_u8(__a) __arm_vreinterpretq_s8_u8(__a) +#define vreinterpretq_u16_s16(__a) __arm_vreinterpretq_u16_s16(__a) +#define vreinterpretq_u16_s32(__a) __arm_vreinterpretq_u16_s32(__a) +#define vreinterpretq_u16_s64(__a) __arm_vreinterpretq_u16_s64(__a) +#define vreinterpretq_u16_s8(__a) __arm_vreinterpretq_u16_s8(__a) +#define vreinterpretq_u16_u32(__a) __arm_vreinterpretq_u16_u32(__a) +#define vreinterpretq_u16_u64(__a) __arm_vreinterpretq_u16_u64(__a) +#define vreinterpretq_u16_u8(__a) __arm_vreinterpretq_u16_u8(__a) +#define vreinterpretq_u32_s16(__a) __arm_vreinterpretq_u32_s16(__a) +#define vreinterpretq_u32_s32(__a) __arm_vreinterpretq_u32_s32(__a) +#define vreinterpretq_u32_s64(__a) __arm_vreinterpretq_u32_s64(__a) +#define vreinterpretq_u32_s8(__a) __arm_vreinterpretq_u32_s8(__a) +#define vreinterpretq_u32_u16(__a) __arm_vreinterpretq_u32_u16(__a) +#define vreinterpretq_u32_u64(__a) __arm_vreinterpretq_u32_u64(__a) +#define vreinterpretq_u32_u8(__a) __arm_vreinterpretq_u32_u8(__a) +#define vreinterpretq_u64_s16(__a) __arm_vreinterpretq_u64_s16(__a) +#define vreinterpretq_u64_s32(__a) __arm_vreinterpretq_u64_s32(__a) +#define vreinterpretq_u64_s64(__a) __arm_vreinterpretq_u64_s64(__a) +#define vreinterpretq_u64_s8(__a) __arm_vreinterpretq_u64_s8(__a) +#define vreinterpretq_u64_u16(__a) __arm_vreinterpretq_u64_u16(__a) +#define vreinterpretq_u64_u32(__a) __arm_vreinterpretq_u64_u32(__a) +#define vreinterpretq_u64_u8(__a) __arm_vreinterpretq_u64_u8(__a) +#define vreinterpretq_u8_s16(__a) __arm_vreinterpretq_u8_s16(__a) +#define vreinterpretq_u8_s32(__a) __arm_vreinterpretq_u8_s32(__a) +#define vreinterpretq_u8_s64(__a) __arm_vreinterpretq_u8_s64(__a) +#define vreinterpretq_u8_s8(__a) __arm_vreinterpretq_u8_s8(__a) +#define vreinterpretq_u8_u16(__a) __arm_vreinterpretq_u8_u16(__a) +#define vreinterpretq_u8_u32(__a) __arm_vreinterpretq_u8_u32(__a) +#define vreinterpretq_u8_u64(__a) __arm_vreinterpretq_u8_u64(__a) +#define vreinterpretq_s32_f16(__a) __arm_vreinterpretq_s32_f16(__a) +#define vreinterpretq_s32_f32(__a) __arm_vreinterpretq_s32_f32(__a) +#define vreinterpretq_u16_f16(__a) __arm_vreinterpretq_u16_f16(__a) +#define vreinterpretq_u16_f32(__a) __arm_vreinterpretq_u16_f32(__a) +#define vreinterpretq_u32_f16(__a) __arm_vreinterpretq_u32_f16(__a) +#define vreinterpretq_u32_f32(__a) __arm_vreinterpretq_u32_f32(__a) +#define vreinterpretq_u64_f16(__a) __arm_vreinterpretq_u64_f16(__a) +#define vreinterpretq_u64_f32(__a) __arm_vreinterpretq_u64_f32(__a) +#define vreinterpretq_u8_f16(__a) __arm_vreinterpretq_u8_f16(__a) +#define vreinterpretq_u8_f32(__a) __arm_vreinterpretq_u8_f32(__a) +#define vreinterpretq_f16_f32(__a) __arm_vreinterpretq_f16_f32(__a) +#define vreinterpretq_f16_s16(__a) __arm_vreinterpretq_f16_s16(__a) +#define vreinterpretq_f16_s32(__a) __arm_vreinterpretq_f16_s32(__a) +#define vreinterpretq_f16_s64(__a) __arm_vreinterpretq_f16_s64(__a) +#define vreinterpretq_f16_s8(__a) __arm_vreinterpretq_f16_s8(__a) +#define vreinterpretq_f16_u16(__a) __arm_vreinterpretq_f16_u16(__a) +#define vreinterpretq_f16_u32(__a) __arm_vreinterpretq_f16_u32(__a) +#define vreinterpretq_f16_u64(__a) __arm_vreinterpretq_f16_u64(__a) +#define vreinterpretq_f16_u8(__a) __arm_vreinterpretq_f16_u8(__a) +#define vreinterpretq_f32_f16(__a) __arm_vreinterpretq_f32_f16(__a) +#define vreinterpretq_f32_s16(__a) __arm_vreinterpretq_f32_s16(__a) +#define vreinterpretq_f32_s32(__a) __arm_vreinterpretq_f32_s32(__a) +#define vreinterpretq_f32_s64(__a) __arm_vreinterpretq_f32_s64(__a) +#define vreinterpretq_f32_s8(__a) __arm_vreinterpretq_f32_s8(__a) +#define vreinterpretq_f32_u16(__a) __arm_vreinterpretq_f32_u16(__a) +#define vreinterpretq_f32_u32(__a) __arm_vreinterpretq_f32_u32(__a) +#define vreinterpretq_f32_u64(__a) __arm_vreinterpretq_f32_u64(__a) +#define vreinterpretq_f32_u8(__a) __arm_vreinterpretq_f32_u8(__a) +#define vreinterpretq_s16_f16(__a) __arm_vreinterpretq_s16_f16(__a) +#define vreinterpretq_s16_f32(__a) __arm_vreinterpretq_s16_f32(__a) +#define vreinterpretq_s64_f16(__a) __arm_vreinterpretq_s64_f16(__a) +#define vreinterpretq_s64_f32(__a) __arm_vreinterpretq_s64_f32(__a) +#define vreinterpretq_s8_f16(__a) __arm_vreinterpretq_s8_f16(__a) +#define vreinterpretq_s8_f32(__a) __arm_vreinterpretq_s8_f32(__a) +#define vuninitializedq_u8(void) __arm_vuninitializedq_u8(void) +#define vuninitializedq_u16(void) __arm_vuninitializedq_u16(void) +#define vuninitializedq_u32(void) __arm_vuninitializedq_u32(void) +#define vuninitializedq_u64(void) __arm_vuninitializedq_u64(void) +#define vuninitializedq_s8(void) __arm_vuninitializedq_s8(void) +#define vuninitializedq_s16(void) __arm_vuninitializedq_s16(void) +#define vuninitializedq_s32(void) __arm_vuninitializedq_s32(void) +#define vuninitializedq_s64(void) __arm_vuninitializedq_s64(void) +#define vuninitializedq_f16(void) __arm_vuninitializedq_f16(void) +#define vuninitializedq_f32(void) __arm_vuninitializedq_f32(void) #endif __extension__ extern __inline void @@ -12391,6 +12491,471 @@ __arm_vaddq_u32 (uint32x4_t __a, uint32x4_t __b) return __a + __b; } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_u8 (void) +{ + uint8x16_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_u16 (void) +{ + uint16x8_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_u32 (void) +{ + uint32x4_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_u64 (void) +{ + uint64x2_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_s8 (void) +{ + int8x16_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_s16 (void) +{ + int16x8_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_s32 (void) +{ + int32x4_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_s64 (void) +{ + int64x2_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_s32 (int32x4_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_s64 (int64x2_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_s8 (int8x16_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_u16 (uint16x8_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_u32 (uint32x4_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_u64 (uint64x2_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_u8 (uint8x16_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_s16 (int16x8_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_s64 (int64x2_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_s8 (int8x16_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_u16 (uint16x8_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_u32 (uint32x4_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_u64 (uint64x2_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_u8 (uint8x16_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_s16 (int16x8_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_s32 (int32x4_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_s8 (int8x16_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_u16 (uint16x8_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_u32 (uint32x4_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_u64 (uint64x2_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_u8 (uint8x16_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_s16 (int16x8_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_s32 (int32x4_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_s64 (int64x2_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_u16 (uint16x8_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_u32 (uint32x4_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_u64 (uint64x2_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_u8 (uint8x16_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_s16 (int16x8_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_s32 (int32x4_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_s64 (int64x2_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_s8 (int8x16_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_u32 (uint32x4_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_u64 (uint64x2_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_u8 (uint8x16_t __a) +{ + return (uint16x8_t) __a; +} + + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_s16 (int16x8_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_s32 (int32x4_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_s64 (int64x2_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_s8 (int8x16_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_u16 (uint16x8_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_u64 (uint64x2_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_u8 (uint8x16_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_s16 (int16x8_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_s32 (int32x4_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_s64 (int64x2_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_s8 (int8x16_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_u16 (uint16x8_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_u32 (uint32x4_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_u8 (uint8x16_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_s16 (int16x8_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_s32 (int32x4_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_s64 (int64x2_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_s8 (int8x16_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_u16 (uint16x8_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_u32 (uint32x4_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_u64 (uint64x2_t __a) +{ + return (uint8x16_t) __a; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -14771,6 +15336,262 @@ __arm_vaddq_f32 (float32x4_t __a, float32x4_t __b) return __a + __b; } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_f16 (void) +{ + float16x8_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_f32 (void) +{ + float32x4_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_f16 (float16x8_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_f32 (float32x4_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_f16 (float16x8_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_f32 (float32x4_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_f16 (float16x8_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_f32 (float32x4_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_f16 (float16x8_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_f32 (float32x4_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_f16 (float16x8_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_f32 (float32x4_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_f16 (float16x8_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_f32 (float32x4_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_f16 (float16x8_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_f32 (float32x4_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_f16 (float16x8_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_f32 (float32x4_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_f32 (float32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s16 (int16x8_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s32 (int32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s64 (int64x2_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s8 (int8x16_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u16 (uint16x8_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u32 (uint32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u64 (uint64x2_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u8 (uint8x16_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_f16 (float16x8_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_s16 (int16x8_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_s32 (int32x4_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_s64 (int64x2_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_s8 (int8x16_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_u16 (uint16x8_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_u32 (uint32x4_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_u64 (uint64x2_t __a) +{ + return (float32x4_t) __a; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f32_u8 (uint8x16_t __a) +{ + return (float32x4_t) __a; +} + #endif enum { @@ -17543,6 +18364,150 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) +#define vuninitializedq(p0) __arm_vuninitializedq(p0) +#define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vuninitializedq_s8 (), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vuninitializedq_s16 (), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vuninitializedq_s32 (), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vuninitializedq_s64 (), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vuninitializedq_u8 (), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vuninitializedq_u16 (), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vuninitializedq_u32 (), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vuninitializedq_u64 (), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vuninitializedq_f16 (), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vuninitializedq_f32 ());}) + +#define vreinterpretq_f16(p0) __arm_vreinterpretq_f16(p0) +#define __arm_vreinterpretq_f16(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_f16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_f32(p0) __arm_vreinterpretq_f32(p0) +#define __arm_vreinterpretq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vreinterpretq_s16(p0) __arm_vreinterpretq_s16(p0) +#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_s32(p0) __arm_vreinterpretq_s32(p0) +#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_s64(p0) __arm_vreinterpretq_s64(p0) +#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_s8(p0) __arm_vreinterpretq_s8(p0) +#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_u16(p0) __arm_vreinterpretq_u16(p0) +#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_u32(p0) __arm_vreinterpretq_u32(p0) +#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_u64(p0) __arm_vreinterpretq_u64(p0) +#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vreinterpretq_u8(p0) __arm_vreinterpretq_u8(p0) +#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + #else /* MVE Integer. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -19925,6 +20890,106 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) +#define vuninitializedq(p0) __arm_vuninitializedq(p0) +#define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vuninitializedq_s8 (), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vuninitializedq_s16 (), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vuninitializedq_s32 (), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vuninitializedq_s64 (), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vuninitializedq_u8 (), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vuninitializedq_u16 (), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vuninitializedq_u32 (), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vuninitializedq_u64 ());}) + +#define vreinterpretq_s16(p0) __arm_vreinterpretq_s16(p0) +#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_s32(p0) __arm_vreinterpretq_s32(p0) +#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_s64(p0) __arm_vreinterpretq_s64(p0) +#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_s8(p0) __arm_vreinterpretq_s8(p0) +#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_u16(p0) __arm_vreinterpretq_u16(p0) +#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_u32(p0) __arm_vreinterpretq_u32(p0) +#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + +#define vreinterpretq_u64(p0) __arm_vreinterpretq_u64(p0) +#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)));}) + +#define vreinterpretq_u8(p0) __arm_vreinterpretq_u8(p0) +#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) + #endif /* MVE Integer. */ #define vldrdq_gather_offset(p0,p1) __arm_vldrdq_gather_offset(p0,p1) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e4aeb83..52008db 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,25 @@ 2020-03-20 Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: New test. + * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. + +2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c new file mode 100644 index 0000000..bc40440 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int8x16_t value1; +int64x2_t value2; +int32x4_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +int16x8_t value8; +float32x4_t value9; + +float16x8_t +foo () +{ + float16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_f16 (vreinterpretq_f16_s8 (value1), vreinterpretq_f16_s64 (value2)); + r2 = vaddq_f16 (r1, vreinterpretq_f16_s32 (value3)); + r3 = vaddq_f16 (r2, vreinterpretq_f16_u8 (value4)); + r4 = vaddq_f16 (r3, vreinterpretq_f16_u16 (value5)); + r5 = vaddq_f16 (r4, vreinterpretq_f16_u64 (value6)); + r6 = vaddq_f16 (r5, vreinterpretq_f16_u32 (value7)); + r7 = vaddq_f16 (r6, vreinterpretq_f16_s16 (value8)); + return vaddq_f16 (r7, vreinterpretq_f16_f32 (value9)); +} + +float16x8_t +foo1 () +{ + float16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_f16 (vreinterpretq_f16 (value1), vreinterpretq_f16 (value2)); + r2 = vaddq_f16 (r1, vreinterpretq_f16 (value3)); + r3 = vaddq_f16 (r2, vreinterpretq_f16 (value4)); + r4 = vaddq_f16 (r3, vreinterpretq_f16 (value5)); + r5 = vaddq_f16 (r4, vreinterpretq_f16 (value6)); + r6 = vaddq_f16 (r5, vreinterpretq_f16 (value7)); + r7 = vaddq_f16 (r6, vreinterpretq_f16 (value8)); + return vaddq_f16 (r7, vreinterpretq_f16 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.f16" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c new file mode 100644 index 0000000..d30818b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int64x2_t value2; +int8x16_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +int32x4_t value9; + +float32x4_t +foo () +{ + float32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_f32 (vreinterpretq_f32_s16 (value1), vreinterpretq_f32_s64 (value2)); + r2 = vaddq_f32 (r1, vreinterpretq_f32_s8 (value3)); + r3 = vaddq_f32 (r2, vreinterpretq_f32_u8 (value4)); + r4 = vaddq_f32 (r3, vreinterpretq_f32_u16 (value5)); + r5 = vaddq_f32 (r4, vreinterpretq_f32_u64 (value6)); + r6 = vaddq_f32 (r5, vreinterpretq_f32_u32 (value7)); + r7 = vaddq_f32 (r6, vreinterpretq_f32_f16 (value8)); + return vaddq_f32 (r7, vreinterpretq_f32_s32 (value9)); +} + +float32x4_t +foo1 () +{ + float32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_f32 (vreinterpretq_f32 (value1), vreinterpretq_f32 (value2)); + r2 = vaddq_f32 (r1, vreinterpretq_f32 (value3)); + r3 = vaddq_f32 (r2, vreinterpretq_f32 (value4)); + r4 = vaddq_f32 (r3, vreinterpretq_f32 (value5)); + r5 = vaddq_f32 (r4, vreinterpretq_f32 (value6)); + r6 = vaddq_f32 (r5, vreinterpretq_f32 (value7)); + r7 = vaddq_f32 (r6, vreinterpretq_f32 (value8)); + return vaddq_f32 (r7, vreinterpretq_f32 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.f32" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c new file mode 100644 index 0000000..627a9d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int8x16_t value1; +int64x2_t value2; +int32x4_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +int16x8_t +foo () +{ + int16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s16 (vreinterpretq_s16_s8 (value1), vreinterpretq_s16_s64 (value2)); + r2 = vaddq_s16 (r1, vreinterpretq_s16_s32 (value3)); + r3 = vaddq_s16 (r2, vreinterpretq_s16_u8 (value4)); + r4 = vaddq_s16 (r3, vreinterpretq_s16_u16 (value5)); + r5 = vaddq_s16 (r4, vreinterpretq_s16_u64 (value6)); + r6 = vaddq_s16 (r5, vreinterpretq_s16_u32 (value7)); + r7 = vaddq_s16 (r6, vreinterpretq_s16_f16 (value8)); + return vaddq_s16 (r7, vreinterpretq_s16_f32 (value9)); +} + +int16x8_t +foo1 () +{ + int16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s16 (vreinterpretq_s16 (value1), vreinterpretq_s16 (value2)); + r2 = vaddq_s16 (r1, vreinterpretq_s16 (value3)); + r3 = vaddq_s16 (r2, vreinterpretq_s16 (value4)); + r4 = vaddq_s16 (r3, vreinterpretq_s16 (value5)); + r5 = vaddq_s16 (r4, vreinterpretq_s16 (value6)); + r6 = vaddq_s16 (r5, vreinterpretq_s16 (value7)); + r7 = vaddq_s16 (r6, vreinterpretq_s16 (value8)); + return vaddq_s16 (r7, vreinterpretq_s16 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c new file mode 100644 index 0000000..1b905e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int64x2_t value2; +int8x16_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +int32x4_t +foo () +{ + int32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s32 (vreinterpretq_s32_s16 (value1), vreinterpretq_s32_s64 (value2)); + r2 = vaddq_s32 (r1, vreinterpretq_s32_s8 (value3)); + r3 = vaddq_s32 (r2, vreinterpretq_s32_u8 (value4)); + r4 = vaddq_s32 (r3, vreinterpretq_s32_u16 (value5)); + r5 = vaddq_s32 (r4, vreinterpretq_s32_u64 (value6)); + r6 = vaddq_s32 (r5, vreinterpretq_s32_u32 (value7)); + r7 = vaddq_s32 (r6, vreinterpretq_s32_f16 (value8)); + return vaddq_s32 (r7, vreinterpretq_s32_f32 (value9)); +} + +int32x4_t +foo1 () +{ + int32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s32 (vreinterpretq_s32 (value1), vreinterpretq_s32 (value2)); + r2 = vaddq_s32 (r1, vreinterpretq_s32 (value3)); + r3 = vaddq_s32 (r2, vreinterpretq_s32 (value4)); + r4 = vaddq_s32 (r3, vreinterpretq_s32 (value5)); + r5 = vaddq_s32 (r4, vreinterpretq_s32 (value6)); + r6 = vaddq_s32 (r5, vreinterpretq_s32 (value7)); + r7 = vaddq_s32 (r6, vreinterpretq_s32 (value8)); + return vaddq_s32 (r7, vreinterpretq_s32 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c new file mode 100644 index 0000000..3a9fa0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int8x16_t value2; +int32x4_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +int64x2_t +foo (mve_pred16_t __p) +{ + int64x2_t r1,r2,r3,r4,r5,r6,r7; + r1 = vpselq_s64 (vreinterpretq_s64_s16 (value1), vreinterpretq_s64_s8 (value2), + __p); + r2 = vpselq_s64 (r1, vreinterpretq_s64_s32 (value3), __p); + r3 = vpselq_s64 (r2, vreinterpretq_s64_u8 (value4), __p); + r4 = vpselq_s64 (r3, vreinterpretq_s64_u16 (value5), __p); + r5 = vpselq_s64 (r4, vreinterpretq_s64_u64 (value6), __p); + r6 = vpselq_s64 (r5, vreinterpretq_s64_u32 (value7), __p); + r7 = vpselq_s64 (r6, vreinterpretq_s64_f16 (value8), __p); + return vpselq_s64 (r7, vreinterpretq_s64_f32 (value9), __p); +} + +int64x2_t +foo1 (mve_pred16_t __p) +{ + int64x2_t r1,r2,r3,r4,r5,r6,r7; + r1 = vpselq_s64 (vreinterpretq_s64 (value1), vreinterpretq_s64 (value2), __p); + r2 = vpselq_s64 (r1, vreinterpretq_s64 (value3), __p); + r3 = vpselq_s64 (r2, vreinterpretq_s64 (value4), __p); + r4 = vpselq_s64 (r3, vreinterpretq_s64 (value5), __p); + r5 = vpselq_s64 (r4, vreinterpretq_s64 (value6), __p); + r6 = vpselq_s64 (r5, vreinterpretq_s64 (value7), __p); + r7 = vpselq_s64 (r6, vreinterpretq_s64 (value8), __p); + return vpselq_s64 (r7, vreinterpretq_s64 (value9), __p); +} + +/* { dg-final { scan-assembler-times "vpsel" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c new file mode 100644 index 0000000..522a935 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int64x2_t value2; +int32x4_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +int8x16_t +foo () +{ + int8x16_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s8 (vreinterpretq_s8_s16 (value1), vreinterpretq_s8_s64 (value2)); + r2 = vaddq_s8 (r1, vreinterpretq_s8_s32 (value3)); + r3 = vaddq_s8 (r2, vreinterpretq_s8_u8 (value4)); + r4 = vaddq_s8 (r3, vreinterpretq_s8_u16 (value5)); + r5 = vaddq_s8 (r4, vreinterpretq_s8_u64 (value6)); + r6 = vaddq_s8 (r5, vreinterpretq_s8_u32 (value7)); + r7 = vaddq_s8 (r6, vreinterpretq_s8_f16 (value8)); + return vaddq_s8 (r7, vreinterpretq_s8_f32 (value9)); +} + +int8x16_t +foo1 () +{ + int8x16_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_s8 (vreinterpretq_s8 (value1), vreinterpretq_s8 (value2)); + r2 = vaddq_s8 (r1, vreinterpretq_s8 (value3)); + r3 = vaddq_s8 (r2, vreinterpretq_s8 (value4)); + r4 = vaddq_s8 (r3, vreinterpretq_s8 (value5)); + r5 = vaddq_s8 (r4, vreinterpretq_s8 (value6)); + r6 = vaddq_s8 (r5, vreinterpretq_s8 (value7)); + r7 = vaddq_s8 (r6, vreinterpretq_s8 (value8)); + return vaddq_s8 (r7, vreinterpretq_s8 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c new file mode 100644 index 0000000..402c0ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int8x16_t value1; +int64x2_t value2; +int32x4_t value3; +uint8x16_t value4; +int16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +uint16x8_t +foo () +{ + uint16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u16 (vreinterpretq_u16_s8 (value1), vreinterpretq_u16_s64 (value2)); + r2 = vaddq_u16 (r1, vreinterpretq_u16_s32 (value3)); + r3 = vaddq_u16 (r2, vreinterpretq_u16_u8 (value4)); + r4 = vaddq_u16 (r3, vreinterpretq_u16_s16 (value5)); + r5 = vaddq_u16 (r4, vreinterpretq_u16_u64 (value6)); + r6 = vaddq_u16 (r5, vreinterpretq_u16_u32 (value7)); + r7 = vaddq_u16 (r6, vreinterpretq_u16_f16 (value8)); + return vaddq_u16 (r7, vreinterpretq_u16_f32 (value9)); +} + +uint16x8_t +foo1 () +{ + uint16x8_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u16 (vreinterpretq_u16 (value1), vreinterpretq_u16 (value2)); + r2 = vaddq_u16 (r1, vreinterpretq_u16 (value3)); + r3 = vaddq_u16 (r2, vreinterpretq_u16 (value4)); + r4 = vaddq_u16 (r3, vreinterpretq_u16 (value5)); + r5 = vaddq_u16 (r4, vreinterpretq_u16 (value6)); + r6 = vaddq_u16 (r5, vreinterpretq_u16 (value7)); + r7 = vaddq_u16 (r6, vreinterpretq_u16 (value8)); + return vaddq_u16 (r7, vreinterpretq_u16 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c new file mode 100644 index 0000000..985d776 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int64x2_t value2; +int8x16_t value3; +uint8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +int32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +uint32x4_t +foo () +{ + uint32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u32 (vreinterpretq_u32_s16 (value1), vreinterpretq_u32_s64 (value2)); + r2 = vaddq_u32 (r1, vreinterpretq_u32_s8 (value3)); + r3 = vaddq_u32 (r2, vreinterpretq_u32_u8 (value4)); + r4 = vaddq_u32 (r3, vreinterpretq_u32_u16 (value5)); + r5 = vaddq_u32 (r4, vreinterpretq_u32_u64 (value6)); + r6 = vaddq_u32 (r5, vreinterpretq_u32_s32 (value7)); + r7 = vaddq_u32 (r6, vreinterpretq_u32_f16 (value8)); + return vaddq_u32 (r7, vreinterpretq_u32_f32 (value9)); +} + +uint32x4_t +foo1 () +{ + uint32x4_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u32 (vreinterpretq_u32 (value1), vreinterpretq_u32 (value2)); + r2 = vaddq_u32 (r1, vreinterpretq_u32 (value3)); + r3 = vaddq_u32 (r2, vreinterpretq_u32 (value4)); + r4 = vaddq_u32 (r3, vreinterpretq_u32 (value5)); + r5 = vaddq_u32 (r4, vreinterpretq_u32 (value6)); + r6 = vaddq_u32 (r5, vreinterpretq_u32 (value7)); + r7 = vaddq_u32 (r6, vreinterpretq_u32 (value8)); + return vaddq_u32 (r7, vreinterpretq_u32 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c new file mode 100644 index 0000000..e77d253 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int8x16_t value2; +int32x4_t value3; +uint8x16_t value4; +uint16x8_t value5; +int64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +uint64x2_t +foo (mve_pred16_t __p) +{ + uint64x2_t r1,r2,r3,r4,r5,r6,r7; + r1 = vpselq_u64 (vreinterpretq_u64_s16 (value1), vreinterpretq_u64_s8 (value2), + __p); + r2 = vpselq_u64 (r1, vreinterpretq_u64_s32 (value3), __p); + r3 = vpselq_u64 (r2, vreinterpretq_u64_u8 (value4), __p); + r4 = vpselq_u64 (r3, vreinterpretq_u64_u16 (value5), __p); + r5 = vpselq_u64 (r4, vreinterpretq_u64_s64 (value6), __p); + r6 = vpselq_u64 (r5, vreinterpretq_u64_u32 (value7), __p); + r7 = vpselq_u64 (r6, vreinterpretq_u64_f16 (value8), __p); + return vpselq_u64 (r7, vreinterpretq_u64_f32 (value9), __p); +} + +uint64x2_t +foo1 (mve_pred16_t __p) +{ + uint64x2_t r1,r2,r3,r4,r5,r6,r7; + r1 = vpselq_u64 (vreinterpretq_u64 (value1), vreinterpretq_u64 (value2), __p); + r2 = vpselq_u64 (r1, vreinterpretq_u64 (value3), __p); + r3 = vpselq_u64 (r2, vreinterpretq_u64 (value4), __p); + r4 = vpselq_u64 (r3, vreinterpretq_u64 (value5), __p); + r5 = vpselq_u64 (r4, vreinterpretq_u64 (value6), __p); + r6 = vpselq_u64 (r5, vreinterpretq_u64 (value7), __p); + r7 = vpselq_u64 (r6, vreinterpretq_u64 (value8), __p); + return vpselq_u64 (r7, vreinterpretq_u64 (value9), __p); +} + +/* { dg-final { scan-assembler-times "vpsel" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c new file mode 100644 index 0000000..9075dea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" +int16x8_t value1; +int64x2_t value2; +int32x4_t value3; +int8x16_t value4; +uint16x8_t value5; +uint64x2_t value6; +uint32x4_t value7; +float16x8_t value8; +float32x4_t value9; + +uint8x16_t +foo () +{ + uint8x16_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u8 (vreinterpretq_u8_s16 (value1), vreinterpretq_u8_s64 (value2)); + r2 = vaddq_u8 (r1, vreinterpretq_u8_s32 (value3)); + r3 = vaddq_u8 (r2, vreinterpretq_u8_s8 (value4)); + r4 = vaddq_u8 (r3, vreinterpretq_u8_u16 (value5)); + r5 = vaddq_u8 (r4, vreinterpretq_u8_u64 (value6)); + r6 = vaddq_u8 (r5, vreinterpretq_u8_u32 (value7)); + r7 = vaddq_u8 (r6, vreinterpretq_u8_f16 (value8)); + return vaddq_u8 (r7, vreinterpretq_u8_f32 (value9)); +} + +uint8x16_t +foo1 () +{ + uint8x16_t r1,r2,r3,r4,r5,r6,r7; + r1 = vaddq_u8 (vreinterpretq_u8 (value1), vreinterpretq_u8 (value2)); + r2 = vaddq_u8 (r1, vreinterpretq_u8 (value3)); + r3 = vaddq_u8 (r2, vreinterpretq_u8 (value4)); + r4 = vaddq_u8 (r3, vreinterpretq_u8 (value5)); + r5 = vaddq_u8 (r4, vreinterpretq_u8 (value6)); + r6 = vaddq_u8 (r5, vreinterpretq_u8 (value7)); + r7 = vaddq_u8 (r6, vreinterpretq_u8 (value8)); + return vaddq_u8 (r7, vreinterpretq_u8 (value9)); +} + +/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c new file mode 100644 index 0000000..761d569 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O0" } */ + +#include "arm_mve.h" + +void +foo () +{ + float16x8_t fa; + float32x4_t fb; + fa = vuninitializedq_f16 (); + fb = vuninitializedq_f32 (); +} + +/* { dg-final { scan-assembler-times "vstrb.8" 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c new file mode 100644 index 0000000..173b978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O0" } */ + +#include "arm_mve.h" + +void +foo () +{ + float16x8_t fa, faa; + float32x4_t fb, fbb; + fa = vuninitializedq (faa); + fb = vuninitializedq (fbb); +} + +/* { dg-final { scan-assembler-times "vstrb.8" 4444} */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c new file mode 100644 index 0000000..2969f33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O0" } */ + +#include "arm_mve.h" + +void +foo () +{ + int8x16_t a; + int16x8_t b; + int32x4_t c; + int64x2_t d; + uint8x16_t ua; + uint16x8_t ub; + uint32x4_t uc; + uint64x2_t ud; + a = vuninitializedq_s8 (); + b = vuninitializedq_s16 (); + c = vuninitializedq_s32 (); + d = vuninitializedq_s64 (); + ua = vuninitializedq_u8 (); + ub = vuninitializedq_u16 (); + uc = vuninitializedq_u32 (); + ud = vuninitializedq_u64 (); +} + +/* { dg-final { scan-assembler-times "vstrb.8" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c new file mode 100644 index 0000000..5550190 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O0" } */ + +#include "arm_mve.h" + +void +foo () +{ + int8x16_t a, aa; + int16x8_t b, bb; + int32x4_t c, cc; + int64x2_t d, dd; + uint8x16_t ua, uaa; + uint16x8_t ub, ubb; + uint32x4_t uc, ucc; + uint64x2_t ud, udd; + a = vuninitializedq (aa); + b = vuninitializedq (bb); + c = vuninitializedq (cc); + d = vuninitializedq (dd); + ua = vuninitializedq (uaa); + ub = vuninitializedq (ubb); + uc = vuninitializedq (ucc); + ud = vuninitializedq (udd); +} + +/* { dg-final { scan-assembler-times "vstrb.8" 24 } } */ -- cgit v1.1 From 92f80065d10ece75327c30eed924c322f1e4b338 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 11:58:30 +0000 Subject: [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup intrinsics with writeback. This patch supports following MVE ACLE intrinsics with writeback. vddupq_m_n_u8, vddupq_m_n_u32, vddupq_m_n_u16, vddupq_m_wb_u8, vddupq_m_wb_u16, vddupq_m_wb_u32, vddupq_n_u8, vddupq_n_u32, vddupq_n_u16, vddupq_wb_u8, vddupq_wb_u16, vddupq_wb_u32, vdwdupq_m_n_u8, vdwdupq_m_n_u32, vdwdupq_m_n_u16, vdwdupq_m_wb_u8, vdwdupq_m_wb_u32, vdwdupq_m_wb_u16, vdwdupq_n_u8, vdwdupq_n_u32, vdwdupq_n_u16, vdwdupq_wb_u8, vdwdupq_wb_u32, vdwdupq_wb_u16, vidupq_m_n_u8, vidupq_m_n_u32, vidupq_m_n_u16, vidupq_m_wb_u8, vidupq_m_wb_u16, vidupq_m_wb_u32, vidupq_n_u8, vidupq_n_u32, vidupq_n_u16, vidupq_wb_u8, vidupq_wb_u16, vidupq_wb_u32, viwdupq_m_n_u8, viwdupq_m_n_u32, viwdupq_m_n_u16, viwdupq_m_wb_u8, viwdupq_m_wb_u32, viwdupq_m_wb_u16, viwdupq_n_u8, viwdupq_n_u32, viwdupq_n_u16, viwdupq_wb_u8, viwdupq_wb_u32, viwdupq_wb_u16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary builtin qualifier. * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro. (vddupq_m_n_u32): Likewise. (vddupq_m_n_u16): Likewise. (vddupq_m_wb_u8): Likewise. (vddupq_m_wb_u16): Likewise. (vddupq_m_wb_u32): Likewise. (vddupq_n_u8): Likewise. (vddupq_n_u32): Likewise. (vddupq_n_u16): Likewise. (vddupq_wb_u8): Likewise. (vddupq_wb_u16): Likewise. (vddupq_wb_u32): Likewise. (vdwdupq_m_n_u8): Likewise. (vdwdupq_m_n_u32): Likewise. (vdwdupq_m_n_u16): Likewise. (vdwdupq_m_wb_u8): Likewise. (vdwdupq_m_wb_u32): Likewise. (vdwdupq_m_wb_u16): Likewise. (vdwdupq_n_u8): Likewise. (vdwdupq_n_u32): Likewise. (vdwdupq_n_u16): Likewise. (vdwdupq_wb_u8): Likewise. (vdwdupq_wb_u32): Likewise. (vdwdupq_wb_u16): Likewise. (vidupq_m_n_u8): Likewise. (vidupq_m_n_u32): Likewise. (vidupq_m_n_u16): Likewise. (vidupq_m_wb_u8): Likewise. (vidupq_m_wb_u16): Likewise. (vidupq_m_wb_u32): Likewise. (vidupq_n_u8): Likewise. (vidupq_n_u32): Likewise. (vidupq_n_u16): Likewise. (vidupq_wb_u8): Likewise. (vidupq_wb_u16): Likewise. (vidupq_wb_u32): Likewise. (viwdupq_m_n_u8): Likewise. (viwdupq_m_n_u32): Likewise. (viwdupq_m_n_u16): Likewise. (viwdupq_m_wb_u8): Likewise. (viwdupq_m_wb_u32): Likewise. (viwdupq_m_wb_u16): Likewise. (viwdupq_n_u8): Likewise. (viwdupq_n_u32): Likewise. (viwdupq_n_u16): Likewise. (viwdupq_wb_u8): Likewise. (viwdupq_wb_u32): Likewise. (viwdupq_wb_u16): Likewise. (__arm_vddupq_m_n_u8): Define intrinsic. (__arm_vddupq_m_n_u32): Likewise. (__arm_vddupq_m_n_u16): Likewise. (__arm_vddupq_m_wb_u8): Likewise. (__arm_vddupq_m_wb_u16): Likewise. (__arm_vddupq_m_wb_u32): Likewise. (__arm_vddupq_n_u8): Likewise. (__arm_vddupq_n_u32): Likewise. (__arm_vddupq_n_u16): Likewise. (__arm_vdwdupq_m_n_u8): Likewise. (__arm_vdwdupq_m_n_u32): Likewise. (__arm_vdwdupq_m_n_u16): Likewise. (__arm_vdwdupq_m_wb_u8): Likewise. (__arm_vdwdupq_m_wb_u32): Likewise. (__arm_vdwdupq_m_wb_u16): Likewise. (__arm_vdwdupq_n_u8): Likewise. (__arm_vdwdupq_n_u32): Likewise. (__arm_vdwdupq_n_u16): Likewise. (__arm_vdwdupq_wb_u8): Likewise. (__arm_vdwdupq_wb_u32): Likewise. (__arm_vdwdupq_wb_u16): Likewise. (__arm_vidupq_m_n_u8): Likewise. (__arm_vidupq_m_n_u32): Likewise. (__arm_vidupq_m_n_u16): Likewise. (__arm_vidupq_n_u8): Likewise. (__arm_vidupq_m_wb_u8): Likewise. (__arm_vidupq_m_wb_u16): Likewise. (__arm_vidupq_m_wb_u32): Likewise. (__arm_vidupq_n_u32): Likewise. (__arm_vidupq_n_u16): Likewise. (__arm_vidupq_wb_u8): Likewise. (__arm_vidupq_wb_u16): Likewise. (__arm_vidupq_wb_u32): Likewise. (__arm_vddupq_wb_u8): Likewise. (__arm_vddupq_wb_u16): Likewise. (__arm_vddupq_wb_u32): Likewise. (__arm_viwdupq_m_n_u8): Likewise. (__arm_viwdupq_m_n_u32): Likewise. (__arm_viwdupq_m_n_u16): Likewise. (__arm_viwdupq_m_wb_u8): Likewise. (__arm_viwdupq_m_wb_u32): Likewise. (__arm_viwdupq_m_wb_u16): Likewise. (__arm_viwdupq_n_u8): Likewise. (__arm_viwdupq_n_u32): Likewise. (__arm_viwdupq_n_u16): Likewise. (__arm_viwdupq_wb_u8): Likewise. (__arm_viwdupq_wb_u32): Likewise. (__arm_viwdupq_wb_u16): Likewise. (vidupq_m): Define polymorphic variant. (vddupq_m): Likewise. (vidupq_u16): Likewise. (vidupq_u32): Likewise. (vidupq_u8): Likewise. (vddupq_u16): Likewise. (vddupq_u32): Likewise. (vddupq_u8): Likewise. (viwdupq_m): Likewise. (viwdupq_u16): Likewise. (viwdupq_u32): Likewise. (viwdupq_u8): Likewise. (vdwdupq_m): Likewise. (vdwdupq_u16): Likewise. (vdwdupq_u32): Likewise. (vdwdupq_u8): Likewise. * config/arm/arm_mve_builtins.def (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin qualifier. * config/arm/mve.md (mve_vidupq_n_u): Define RTL pattern. (mve_vidupq_u_insn): Likewise. (mve_vidupq_m_n_u): Likewise. (mve_vidupq_m_wb_u_insn): Likewise. (mve_vddupq_n_u): Likewise. (mve_vddupq_u_insn): Likewise. (mve_vddupq_m_n_u): Likewise. (mve_vddupq_m_wb_u_insn): Likewise. (mve_vdwdupq_n_u): Likewise. (mve_vdwdupq_wb_u): Likewise. (mve_vdwdupq_wb_u_insn): Likewise. (mve_vdwdupq_m_n_u): Likewise. (mve_vdwdupq_m_wb_u): Likewise. (mve_vdwdupq_m_wb_u_insn): Likewise. (mve_viwdupq_n_u): Likewise. (mve_viwdupq_wb_u): Likewise. (mve_viwdupq_wb_u_insn): Likewise. (mve_viwdupq_m_n_u): Likewise. (mve_viwdupq_m_wb_u): Likewise. (mve_viwdupq_m_wb_u_insn): Likewise. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: New test. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise. --- gcc/ChangeLog | 143 ++++++ gcc/config/arm/arm-builtins.c | 7 + gcc/config/arm/arm_mve.h | 548 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 12 + gcc/config/arm/mve.md | 373 +++++++++++++- gcc/testsuite/ChangeLog | 53 ++ .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + 54 files changed, 2239 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 55b5b08..22c9766 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,147 @@ 2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * config/arm/arm-builtins.c + (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary + builtin qualifier. + * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro. + (vddupq_m_n_u32): Likewise. + (vddupq_m_n_u16): Likewise. + (vddupq_m_wb_u8): Likewise. + (vddupq_m_wb_u16): Likewise. + (vddupq_m_wb_u32): Likewise. + (vddupq_n_u8): Likewise. + (vddupq_n_u32): Likewise. + (vddupq_n_u16): Likewise. + (vddupq_wb_u8): Likewise. + (vddupq_wb_u16): Likewise. + (vddupq_wb_u32): Likewise. + (vdwdupq_m_n_u8): Likewise. + (vdwdupq_m_n_u32): Likewise. + (vdwdupq_m_n_u16): Likewise. + (vdwdupq_m_wb_u8): Likewise. + (vdwdupq_m_wb_u32): Likewise. + (vdwdupq_m_wb_u16): Likewise. + (vdwdupq_n_u8): Likewise. + (vdwdupq_n_u32): Likewise. + (vdwdupq_n_u16): Likewise. + (vdwdupq_wb_u8): Likewise. + (vdwdupq_wb_u32): Likewise. + (vdwdupq_wb_u16): Likewise. + (vidupq_m_n_u8): Likewise. + (vidupq_m_n_u32): Likewise. + (vidupq_m_n_u16): Likewise. + (vidupq_m_wb_u8): Likewise. + (vidupq_m_wb_u16): Likewise. + (vidupq_m_wb_u32): Likewise. + (vidupq_n_u8): Likewise. + (vidupq_n_u32): Likewise. + (vidupq_n_u16): Likewise. + (vidupq_wb_u8): Likewise. + (vidupq_wb_u16): Likewise. + (vidupq_wb_u32): Likewise. + (viwdupq_m_n_u8): Likewise. + (viwdupq_m_n_u32): Likewise. + (viwdupq_m_n_u16): Likewise. + (viwdupq_m_wb_u8): Likewise. + (viwdupq_m_wb_u32): Likewise. + (viwdupq_m_wb_u16): Likewise. + (viwdupq_n_u8): Likewise. + (viwdupq_n_u32): Likewise. + (viwdupq_n_u16): Likewise. + (viwdupq_wb_u8): Likewise. + (viwdupq_wb_u32): Likewise. + (viwdupq_wb_u16): Likewise. + (__arm_vddupq_m_n_u8): Define intrinsic. + (__arm_vddupq_m_n_u32): Likewise. + (__arm_vddupq_m_n_u16): Likewise. + (__arm_vddupq_m_wb_u8): Likewise. + (__arm_vddupq_m_wb_u16): Likewise. + (__arm_vddupq_m_wb_u32): Likewise. + (__arm_vddupq_n_u8): Likewise. + (__arm_vddupq_n_u32): Likewise. + (__arm_vddupq_n_u16): Likewise. + (__arm_vdwdupq_m_n_u8): Likewise. + (__arm_vdwdupq_m_n_u32): Likewise. + (__arm_vdwdupq_m_n_u16): Likewise. + (__arm_vdwdupq_m_wb_u8): Likewise. + (__arm_vdwdupq_m_wb_u32): Likewise. + (__arm_vdwdupq_m_wb_u16): Likewise. + (__arm_vdwdupq_n_u8): Likewise. + (__arm_vdwdupq_n_u32): Likewise. + (__arm_vdwdupq_n_u16): Likewise. + (__arm_vdwdupq_wb_u8): Likewise. + (__arm_vdwdupq_wb_u32): Likewise. + (__arm_vdwdupq_wb_u16): Likewise. + (__arm_vidupq_m_n_u8): Likewise. + (__arm_vidupq_m_n_u32): Likewise. + (__arm_vidupq_m_n_u16): Likewise. + (__arm_vidupq_n_u8): Likewise. + (__arm_vidupq_m_wb_u8): Likewise. + (__arm_vidupq_m_wb_u16): Likewise. + (__arm_vidupq_m_wb_u32): Likewise. + (__arm_vidupq_n_u32): Likewise. + (__arm_vidupq_n_u16): Likewise. + (__arm_vidupq_wb_u8): Likewise. + (__arm_vidupq_wb_u16): Likewise. + (__arm_vidupq_wb_u32): Likewise. + (__arm_vddupq_wb_u8): Likewise. + (__arm_vddupq_wb_u16): Likewise. + (__arm_vddupq_wb_u32): Likewise. + (__arm_viwdupq_m_n_u8): Likewise. + (__arm_viwdupq_m_n_u32): Likewise. + (__arm_viwdupq_m_n_u16): Likewise. + (__arm_viwdupq_m_wb_u8): Likewise. + (__arm_viwdupq_m_wb_u32): Likewise. + (__arm_viwdupq_m_wb_u16): Likewise. + (__arm_viwdupq_n_u8): Likewise. + (__arm_viwdupq_n_u32): Likewise. + (__arm_viwdupq_n_u16): Likewise. + (__arm_viwdupq_wb_u8): Likewise. + (__arm_viwdupq_wb_u32): Likewise. + (__arm_viwdupq_wb_u16): Likewise. + (vidupq_m): Define polymorphic variant. + (vddupq_m): Likewise. + (vidupq_u16): Likewise. + (vidupq_u32): Likewise. + (vidupq_u8): Likewise. + (vddupq_u16): Likewise. + (vddupq_u32): Likewise. + (vddupq_u8): Likewise. + (viwdupq_m): Likewise. + (viwdupq_u16): Likewise. + (viwdupq_u32): Likewise. + (viwdupq_u8): Likewise. + (vdwdupq_m): Likewise. + (vdwdupq_u16): Likewise. + (vdwdupq_u32): Likewise. + (vdwdupq_u8): Likewise. + * config/arm/arm_mve_builtins.def + (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin + qualifier. + * config/arm/mve.md (mve_vidupq_n_u): Define RTL pattern. + (mve_vidupq_u_insn): Likewise. + (mve_vidupq_m_n_u): Likewise. + (mve_vidupq_m_wb_u_insn): Likewise. + (mve_vddupq_n_u): Likewise. + (mve_vddupq_u_insn): Likewise. + (mve_vddupq_m_n_u): Likewise. + (mve_vddupq_m_wb_u_insn): Likewise. + (mve_vdwdupq_n_u): Likewise. + (mve_vdwdupq_wb_u): Likewise. + (mve_vdwdupq_wb_u_insn): Likewise. + (mve_vdwdupq_m_n_u): Likewise. + (mve_vdwdupq_m_wb_u): Likewise. + (mve_vdwdupq_m_wb_u_insn): Likewise. + (mve_viwdupq_n_u): Likewise. + (mve_viwdupq_wb_u): Likewise. + (mve_viwdupq_wb_u_insn): Likewise. + (mve_viwdupq_m_n_u): Likewise. + (mve_viwdupq_m_wb_u): Likewise. + (mve_viwdupq_m_wb_u_insn): Likewise. + +2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. (vreinterpretq_s16_s64): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index c3deb9e..cefc144 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -711,6 +711,13 @@ arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) +static enum arm_type_qualifiers +arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned, qualifier_immediate, qualifier_unsigned }; +#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 916565c..00f2242 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2006,6 +2006,54 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vuninitializedq_s64(void) __arm_vuninitializedq_s64(void) #define vuninitializedq_f16(void) __arm_vuninitializedq_f16(void) #define vuninitializedq_f32(void) __arm_vuninitializedq_f32(void) +#define vddupq_m_n_u8(__inactive, __a, __imm, __p) __arm_vddupq_m_n_u8(__inactive, __a, __imm, __p) +#define vddupq_m_n_u32(__inactive, __a, __imm, __p) __arm_vddupq_m_n_u32(__inactive, __a, __imm, __p) +#define vddupq_m_n_u16(__inactive, __a, __imm, __p) __arm_vddupq_m_n_u16(__inactive, __a, __imm, __p) +#define vddupq_m_wb_u8(__inactive, __a, __imm, __p) __arm_vddupq_m_wb_u8(__inactive, __a, __imm, __p) +#define vddupq_m_wb_u16(__inactive, __a, __imm, __p) __arm_vddupq_m_wb_u16(__inactive, __a, __imm, __p) +#define vddupq_m_wb_u32(__inactive, __a, __imm, __p) __arm_vddupq_m_wb_u32(__inactive, __a, __imm, __p) +#define vddupq_n_u8(__a, __imm) __arm_vddupq_n_u8(__a, __imm) +#define vddupq_n_u32(__a, __imm) __arm_vddupq_n_u32(__a, __imm) +#define vddupq_n_u16(__a, __imm) __arm_vddupq_n_u16(__a, __imm) +#define vddupq_wb_u8( __a, __imm) __arm_vddupq_wb_u8( __a, __imm) +#define vddupq_wb_u16( __a, __imm) __arm_vddupq_wb_u16( __a, __imm) +#define vddupq_wb_u32( __a, __imm) __arm_vddupq_wb_u32( __a, __imm) +#define vdwdupq_m_n_u8(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_n_u8(__inactive, __a, __b, __imm, __p) +#define vdwdupq_m_n_u32(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_n_u32(__inactive, __a, __b, __imm, __p) +#define vdwdupq_m_n_u16(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_n_u16(__inactive, __a, __b, __imm, __p) +#define vdwdupq_m_wb_u8(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_wb_u8(__inactive, __a, __b, __imm, __p) +#define vdwdupq_m_wb_u32(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_wb_u32(__inactive, __a, __b, __imm, __p) +#define vdwdupq_m_wb_u16(__inactive, __a, __b, __imm, __p) __arm_vdwdupq_m_wb_u16(__inactive, __a, __b, __imm, __p) +#define vdwdupq_n_u8(__a, __b, __imm) __arm_vdwdupq_n_u8(__a, __b, __imm) +#define vdwdupq_n_u32(__a, __b, __imm) __arm_vdwdupq_n_u32(__a, __b, __imm) +#define vdwdupq_n_u16(__a, __b, __imm) __arm_vdwdupq_n_u16(__a, __b, __imm) +#define vdwdupq_wb_u8( __a, __b, __imm) __arm_vdwdupq_wb_u8( __a, __b, __imm) +#define vdwdupq_wb_u32( __a, __b, __imm) __arm_vdwdupq_wb_u32( __a, __b, __imm) +#define vdwdupq_wb_u16( __a, __b, __imm) __arm_vdwdupq_wb_u16( __a, __b, __imm) +#define vidupq_m_n_u8(__inactive, __a, __imm, __p) __arm_vidupq_m_n_u8(__inactive, __a, __imm, __p) +#define vidupq_m_n_u32(__inactive, __a, __imm, __p) __arm_vidupq_m_n_u32(__inactive, __a, __imm, __p) +#define vidupq_m_n_u16(__inactive, __a, __imm, __p) __arm_vidupq_m_n_u16(__inactive, __a, __imm, __p) +#define vidupq_m_wb_u8(__inactive, __a, __imm, __p) __arm_vidupq_m_wb_u8(__inactive, __a, __imm, __p) +#define vidupq_m_wb_u16(__inactive, __a, __imm, __p) __arm_vidupq_m_wb_u16(__inactive, __a, __imm, __p) +#define vidupq_m_wb_u32(__inactive, __a, __imm, __p) __arm_vidupq_m_wb_u32(__inactive, __a, __imm, __p) +#define vidupq_n_u8(__a, __imm) __arm_vidupq_n_u8(__a, __imm) +#define vidupq_n_u32(__a, __imm) __arm_vidupq_n_u32(__a, __imm) +#define vidupq_n_u16(__a, __imm) __arm_vidupq_n_u16(__a, __imm) +#define vidupq_wb_u8( __a, __imm) __arm_vidupq_wb_u8( __a, __imm) +#define vidupq_wb_u16( __a, __imm) __arm_vidupq_wb_u16( __a, __imm) +#define vidupq_wb_u32( __a, __imm) __arm_vidupq_wb_u32( __a, __imm) +#define viwdupq_m_n_u8(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_n_u8(__inactive, __a, __b, __imm, __p) +#define viwdupq_m_n_u32(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_n_u32(__inactive, __a, __b, __imm, __p) +#define viwdupq_m_n_u16(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_n_u16(__inactive, __a, __b, __imm, __p) +#define viwdupq_m_wb_u8(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_wb_u8(__inactive, __a, __b, __imm, __p) +#define viwdupq_m_wb_u32(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_wb_u32(__inactive, __a, __b, __imm, __p) +#define viwdupq_m_wb_u16(__inactive, __a, __b, __imm, __p) __arm_viwdupq_m_wb_u16(__inactive, __a, __b, __imm, __p) +#define viwdupq_n_u8(__a, __b, __imm) __arm_viwdupq_n_u8(__a, __b, __imm) +#define viwdupq_n_u32(__a, __b, __imm) __arm_viwdupq_n_u32(__a, __b, __imm) +#define viwdupq_n_u16(__a, __b, __imm) __arm_viwdupq_n_u16(__a, __b, __imm) +#define viwdupq_wb_u8( __a, __b, __imm) __arm_viwdupq_wb_u8( __a, __b, __imm) +#define viwdupq_wb_u32( __a, __b, __imm) __arm_viwdupq_wb_u32( __a, __b, __imm) +#define viwdupq_wb_u16( __a, __b, __imm) __arm_viwdupq_wb_u16( __a, __b, __imm) #endif __extension__ extern __inline void @@ -12956,6 +13004,390 @@ __arm_vreinterpretq_u8_u64 (uint64x2_t __a) return (uint8x16_t) __a; } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vddupq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vddupq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vddupq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint8x16_t __res = __builtin_mve_vddupq_m_n_uv16qi (__inactive, * __a, __imm, __p); + *__a -= __imm * 16u; + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint16x8_t __res = __builtin_mve_vddupq_m_n_uv8hi (__inactive, *__a, __imm, __p); + *__a -= __imm * 8u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_vddupq_m_n_uv4si (__inactive, *__a, __imm, __p); + *__a -= __imm * 4u; + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_n_u8 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vddupq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_n_u32 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vddupq_n_uv4si (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_n_u16 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vddupq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vdwdupq_m_n_uv4si (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv4si (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_n_u8 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_vdwdupq_n_uv16qi (__a, __b, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_n_u32 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_vdwdupq_n_uv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_n_u16 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_vdwdupq_n_uv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_wb_u8 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint8x16_t __res = __builtin_mve_vdwdupq_n_uv16qi (*__a, __b, __imm); + *__a = __builtin_mve_vdwdupq_wb_uv16qi (*__a, __b, __imm); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_wb_u32 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint32x4_t __res = __builtin_mve_vdwdupq_n_uv4si (*__a, __b, __imm); + *__a = __builtin_mve_vdwdupq_wb_uv4si (*__a, __b, __imm); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdwdupq_wb_u16 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint16x8_t __res = __builtin_mve_vdwdupq_n_uv8hi (*__a, __b, __imm); + *__a = __builtin_mve_vdwdupq_wb_uv8hi (*__a, __b, __imm); + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vidupq_m_n_uv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vidupq_m_n_uv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vidupq_m_n_uv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_n_u8 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vidupq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint8x16_t __res = __builtin_mve_vidupq_m_n_uv16qi (__inactive, *__a, __imm, __p); + *__a += __imm * 16u; + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint16x8_t __res = __builtin_mve_vidupq_m_n_uv8hi (__inactive, *__a, __imm, __p); + *__a += __imm * 8u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, const int __imm, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_vidupq_m_n_uv4si (__inactive, *__a, __imm, __p); + *__a += __imm * 4u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_n_u32 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vidupq_n_uv4si (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_n_u16 (uint32_t __a, const int __imm) +{ + return __builtin_mve_vidupq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_wb_u8 (uint32_t * __a, const int __imm) +{ + uint8x16_t __res = __builtin_mve_vidupq_n_uv16qi (*__a, __imm); + *__a += __imm * 16u; + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_wb_u16 (uint32_t * __a, const int __imm) +{ + uint16x8_t __res = __builtin_mve_vidupq_n_uv8hi (*__a, __imm); + *__a += __imm * 8u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vidupq_wb_u32 (uint32_t * __a, const int __imm) +{ + uint32x4_t __res = __builtin_mve_vidupq_n_uv4si (*__a, __imm); + *__a += __imm * 4u; + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_wb_u8 (uint32_t * __a, const int __imm) +{ + uint8x16_t __res = __builtin_mve_vddupq_n_uv16qi (*__a, __imm); + *__a -= __imm * 16u; + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_wb_u16 (uint32_t * __a, const int __imm) +{ + uint16x8_t __res = __builtin_mve_vddupq_n_uv8hi (*__a, __imm); + *__a -= __imm * 8u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_wb_u32 (uint32_t * __a, const int __imm) +{ + uint32x4_t __res = __builtin_mve_vddupq_n_uv4si (*__a, __imm); + *__a -= __imm * 4u; + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_viwdupq_m_n_uv16qi (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_viwdupq_m_n_uv4si (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_viwdupq_m_n_uv8hi (__inactive, __a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv16qi (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv4si (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p) +{ + uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__inactive, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv8hi (__inactive, *__a, __b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_n_u8 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_viwdupq_n_uv16qi (__a, __b, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_n_u32 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_viwdupq_n_uv4si (__a, __b, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_n_u16 (uint32_t __a, uint32_t __b, const int __imm) +{ + return __builtin_mve_viwdupq_n_uv8hi (__a, __b, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_wb_u8 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint8x16_t __res = __builtin_mve_viwdupq_n_uv16qi (*__a, __b, __imm); + *__a = __builtin_mve_viwdupq_wb_uv16qi (*__a, __b, __imm); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_wb_u32 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint32x4_t __res = __builtin_mve_viwdupq_n_uv4si (*__a, __b, __imm); + *__a = __builtin_mve_viwdupq_wb_uv4si (*__a, __b, __imm); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_viwdupq_wb_u16 (uint32_t * __a, uint32_t __b, const int __imm) +{ + uint16x8_t __res = __builtin_mve_viwdupq_n_uv8hi (*__a, __b, __imm); + *__a = __builtin_mve_viwdupq_wb_uv8hi (*__a, __b, __imm); + return __res; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -21764,6 +22196,122 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));}) +#define vidupq_m(p0,p1,p2,p3) __arm_vidupq_m(p0,p1,p2,p3) +#define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vddupq_m(p0,p1,p2,p3) __arm_vddupq_m(p0,p1,p2,p3) +#define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vidupq_u16(p0,p1) __arm_vidupq_u16(p0,p1) +#define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define vidupq_u32(p0,p1) __arm_vidupq_u32(p0,p1) +#define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define vidupq_u8(p0,p1) __arm_vidupq_u8(p0,p1) +#define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define vddupq_u16(p0,p1) __arm_vddupq_u16(p0,p1) +#define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define vddupq_u32(p0,p1) __arm_vddupq_u32(p0,p1) +#define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define vddupq_u8(p0,p1) __arm_vddupq_u8(p0,p1) +#define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) + +#define viwdupq_m(p0,p1,p2,p3,p4) __arm_viwdupq_m(p0,p1,p2,p3,p4) +#define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define viwdupq_u16(p0,p1,p2) __arm_viwdupq_u16(p0,p1,p2) +#define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + +#define viwdupq_u32(p0,p1,p2) __arm_viwdupq_u32(p0,p1,p2) +#define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + +#define viwdupq_u8(p0,p1,p2) __arm_viwdupq_u8(p0,p1,p2) +#define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + +#define vdwdupq_m(p0,p1,p2,p3,p4) __arm_vdwdupq_m(p0,p1,p2,p3,p4) +#define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define vdwdupq_u16(p0,p1,p2) __arm_vdwdupq_u16(p0,p1,p2) +#define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + +#define vdwdupq_u32(p0,p1,p2) __arm_vdwdupq_u32(p0,p1,p2) +#define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + +#define vdwdupq_u8(p0,p1,p2) __arm_vdwdupq_u8(p0,p1,p2) +#define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) + #ifdef __cplusplus } #endif diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 144547f..2ed7886 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -815,3 +815,15 @@ VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di) VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di) VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_wb_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_wb_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vddupq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_IMM, vidupq_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vddupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vidupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) +VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 77b36a7..b2702f5 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -207,7 +207,8 @@ VSTRDQSB_U VSTRDQSO_S VSTRDQSO_U VSTRDQSSO_S VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F - VSTRWQSO_F VSTRWQSSO_F]) + VSTRWQSO_F VSTRWQSSO_F VDDUPQ VDDUPQ_M VDWDUPQ + VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -9671,3 +9672,373 @@ "vadd.f%# %q0, %q1, %q2" [(set_attr "type" "mve_move") ]) + +;; +;; [vidupq_n_u]) +;; +(define_expand "mve_vidupq_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "mve_imm_selective_upto_8")] + "TARGET_HAVE_MVE" +{ + rtx temp = gen_reg_rtx (SImode); + emit_move_insn (temp, operands[1]); + rtx inc = gen_int_mode (INTVAL(operands[2]) * , SImode); + emit_insn (gen_mve_vidupq_u_insn (operands[0], temp, operands[1], + operands[2], inc)); + DONE; +}) + +;; +;; [vidupq_u_insn]) +;; +(define_insn "mve_vidupq_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] + VIDUPQ)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (plus:SI (match_dup 2) + (match_operand:SI 4 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" + "vidup.u%#\t%q0, %1, %3") + +;; +;; [vidupq_m_n_u]) +;; +(define_expand "mve_vidupq_m_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8") + (match_operand:HI 4 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx temp = gen_reg_rtx (SImode); + emit_move_insn (temp, operands[2]); + rtx inc = gen_int_mode (INTVAL(operands[3]) * , SImode); + emit_insn (gen_mve_vidupq_m_wb_u_insn(operands[0], operands[1], temp, + operands[2], operands[3], + operands[4], inc)); + DONE; +}) + +;; +;; [vidupq_m_wb_u_insn]) +;; +(define_insn "mve_vidupq_m_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 3 "s_register_operand" "2") + (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 5 "vpr_register_operand" "Up")] + VIDUPQ_M)) + (set (match_operand:SI 2 "s_register_operand" "=e") + (plus:SI (match_dup 3) + (match_operand:SI 6 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" + "vpst\;\tvidupt.u%#\t%q0, %2, %4" + [(set_attr "length""8")]) + +;; +;; [vddupq_n_u]) +;; +(define_expand "mve_vddupq_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "mve_imm_selective_upto_8")] + "TARGET_HAVE_MVE" +{ + rtx temp = gen_reg_rtx (SImode); + emit_move_insn (temp, operands[1]); + rtx inc = gen_int_mode (INTVAL(operands[2]) * , SImode); + emit_insn (gen_mve_vddupq_u_insn (operands[0], temp, operands[1], + operands[2], inc)); + DONE; +}) + +;; +;; [vddupq_u_insn]) +;; +(define_insn "mve_vddupq_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "immediate_operand" "i")] + VDDUPQ)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (minus:SI (match_dup 2) + (match_operand:SI 4 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" + "vddup.u%# %q0, %1, %3") + +;; +;; [vddupq_m_n_u]) +;; +(define_expand "mve_vddupq_m_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8") + (match_operand:HI 4 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx temp = gen_reg_rtx (SImode); + emit_move_insn (temp, operands[2]); + rtx inc = gen_int_mode (INTVAL(operands[3]) * , SImode); + emit_insn (gen_mve_vddupq_m_wb_u_insn(operands[0], operands[1], temp, + operands[2], operands[3], + operands[4], inc)); + DONE; +}) + +;; +;; [vddupq_m_wb_u_insn]) +;; +(define_insn "mve_vddupq_m_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:SI 3 "s_register_operand" "2") + (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 5 "vpr_register_operand" "Up")] + VDDUPQ_M)) + (set (match_operand:SI 2 "s_register_operand" "=e") + (minus:SI (match_dup 3) + (match_operand:SI 6 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" + "vpst\;\tvddupt.u%#\t%q0, %2, %4" + [(set_attr "length""8")]) + +;; +;; [vdwdupq_n_u]) +;; +(define_expand "mve_vdwdupq_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8")] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (SImode); + emit_insn (gen_mve_vdwdupq_wb_u_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [vdwdupq_wb_u]) +;; +(define_expand "mve_vdwdupq_wb_u" + [(match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8") + (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (mode); + emit_insn (gen_mve_vdwdupq_wb_u_insn (ignore_vec, operands[0], + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [vdwdupq_wb_u_insn]) +;; +(define_insn "mve_vdwdupq_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] + VDWDUPQ)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4)] + VDWDUPQ))] + "TARGET_HAVE_MVE" + "vdwdup.u%#\t%q0, %2, %3, %4" +) + +;; +;; [vdwdupq_m_n_u]) +;; +(define_expand "mve_vdwdupq_m_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "s_register_operand") + (match_operand:SI 4 "mve_imm_selective_upto_8") + (match_operand:HI 5 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (SImode); + emit_insn (gen_mve_vdwdupq_m_wb_u_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3], operands[4], + operands[5])); + DONE; +}) + +;; +;; [vdwdupq_m_wb_u]) +;; +(define_expand "mve_vdwdupq_m_wb_u" + [(match_operand:SI 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "s_register_operand") + (match_operand:SI 4 "mve_imm_selective_upto_8") + (match_operand:HI 5 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (mode); + emit_insn (gen_mve_vdwdupq_m_wb_u_insn (ignore_vec, operands[0], + operands[1], operands[2], + operands[3], operands[4], + operands[5])); + DONE; +}) + +;; +;; [vdwdupq_m_wb_u_insn]) +;; +(define_insn "mve_vdwdupq_m_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "s_register_operand" "1") + (match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 6 "vpr_register_operand" "Up")] + VDWDUPQ_M)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4) + (match_dup 5) + (match_dup 6)] + VDWDUPQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;\tvdwdupt.u%#\t%q2, %3, %4, %5" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [viwdupq_n_u]) +;; +(define_expand "mve_viwdupq_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8")] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (SImode); + emit_insn (gen_mve_viwdupq_wb_u_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [viwdupq_wb_u]) +;; +(define_expand "mve_viwdupq_wb_u" + [(match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_selective_upto_8") + (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (mode); + emit_insn (gen_mve_viwdupq_wb_u_insn (ignore_vec, operands[0], + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [viwdupq_wb_u_insn]) +;; +(define_insn "mve_viwdupq_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") + (match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] + VIWDUPQ)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4)] + VIWDUPQ))] + "TARGET_HAVE_MVE" + "viwdup.u%#\t%q0, %2, %3, %4" +) + +;; +;; [viwdupq_m_n_u]) +;; +(define_expand "mve_viwdupq_m_n_u" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "s_register_operand") + (match_operand:SI 4 "mve_imm_selective_upto_8") + (match_operand:HI 5 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (SImode); + emit_insn (gen_mve_viwdupq_m_wb_u_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3], operands[4], + operands[5])); + DONE; +}) + +;; +;; [viwdupq_m_wb_u]) +;; +(define_expand "mve_viwdupq_m_wb_u" + [(match_operand:SI 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "s_register_operand") + (match_operand:SI 4 "mve_imm_selective_upto_8") + (match_operand:HI 5 "vpr_register_operand")] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (mode); + emit_insn (gen_mve_viwdupq_m_wb_u_insn (ignore_vec, operands[0], + operands[1], operands[2], + operands[3], operands[4], + operands[5])); + DONE; +}) + +;; +;; [viwdupq_m_wb_u_insn]) +;; +(define_insn "mve_viwdupq_m_wb_u_insn" + [(set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "s_register_operand" "1") + (match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 6 "vpr_register_operand" "Up")] + VIWDUPQ_M)) + (set (match_operand:SI 1 "s_register_operand" "=e") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4) + (match_dup 5) + (match_dup 6)] + VIWDUPQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;\tviwdupt.u%#\t%q2, %3, %4, %5" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 52008db..4506849 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,57 @@ 2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: New test. + * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise. + +2020-03-20 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: New test. * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c new file mode 100644 index 0000000..ba875c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m_n_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c new file mode 100644 index 0000000..618a5e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m_n_u32 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c new file mode 100644 index 0000000..2ee01c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m_n_u8 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c new file mode 100644 index 0000000..08f6a55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m_wb_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c new file mode 100644 index 0000000..16b471e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m_wb_u32 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c new file mode 100644 index 0000000..ade9fb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m_wb_u8 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vddupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c new file mode 100644 index 0000000..b3d44f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a) +{ + return vddupq_n_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vddup.u16" } } */ + +uint16x8_t +foo1 (uint32_t a) +{ + return vddupq_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vddup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c new file mode 100644 index 0000000..163fc7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a) +{ + return vddupq_n_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u32" } } */ + +uint32x4_t +foo1 (uint32_t a) +{ + return vddupq_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c new file mode 100644 index 0000000..8309648 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a) +{ + return vddupq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u8" } } */ + +uint8x16_t +foo1 (uint32_t a) +{ + return vddupq_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c new file mode 100644 index 0000000..469daad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t *a) +{ + return vddupq_wb_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vddup.u16" } } */ + +uint16x8_t +foo1 (uint32_t *a) +{ + return vddupq_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vddup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c new file mode 100644 index 0000000..69f365b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t *a) +{ + return vddupq_wb_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u32" } } */ + +uint32x4_t +foo1 (uint32_t *a) +{ + return vddupq_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c new file mode 100644 index 0000000..8d7ceb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t *a) +{ + return vddupq_wb_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u8" } } */ + +uint8x16_t +foo1 (uint32_t *a) +{ + return vddupq_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vddup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c new file mode 100644 index 0000000..4479065 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c new file mode 100644 index 0000000..874e8642 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c new file mode 100644 index 0000000..7cb0780 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c new file mode 100644 index 0000000..bc8885f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c new file mode 100644 index 0000000..50ed948 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c new file mode 100644 index 0000000..839280e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_m (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c new file mode 100644 index 0000000..dfb75ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, uint32_t b) +{ + return vdwdupq_n_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "vdwdup.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, uint32_t b) +{ + return vdwdupq_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "vdwdup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c new file mode 100644 index 0000000..2597dbd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, uint32_t b) +{ + return vdwdupq_n_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "vdwdup.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, uint32_t b) +{ + return vdwdupq_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "vdwdup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c new file mode 100644 index 0000000..4a4bcb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, uint32_t b) +{ + return vdwdupq_n_u8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vdwdup.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, uint32_t b) +{ + return vdwdupq_u8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vdwdup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c new file mode 100644 index 0000000..9c4506a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t *a, uint32_t b) +{ + return vdwdupq_wb_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "vdwdup.u16" } } */ + +uint16x8_t +foo1 (uint32_t *a, uint32_t b) +{ + return vdwdupq_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "vdwdup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c new file mode 100644 index 0000000..782a6f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t *a, uint32_t b) +{ + return vdwdupq_wb_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "vdwdup.u32" } } */ + +uint32x4_t +foo1 (uint32_t *a, uint32_t b) +{ + return vdwdupq_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "vdwdup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c new file mode 100644 index 0000000..6a4e428 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t *a, uint32_t b) +{ + return vdwdupq_wb_u8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vdwdup.u8" } } */ + +uint8x16_t +foo1 (uint32_t *a, uint32_t b) +{ + return vdwdupq_u8 (a, b, 4); +} + +/* { dg-final { scan-assembler "vdwdup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c new file mode 100644 index 0000000..60449de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m_n_u16 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c new file mode 100644 index 0000000..1d358f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m_n_u32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c new file mode 100644 index 0000000..d32b8c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m_n_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c new file mode 100644 index 0000000..0b34b15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m_wb_u16 (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c new file mode 100644 index 0000000..cc6d6a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m_wb_u32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c new file mode 100644 index 0000000..d6ed263 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m_wb_u8 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) +{ + return vidupq_m (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c new file mode 100644 index 0000000..2bfecbb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a) +{ + return vidupq_n_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vidup.u16" } } */ + +uint16x8_t +foo1 (uint32_t a) +{ + return vidupq_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vidup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c new file mode 100644 index 0000000..f93aab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a) +{ + return vidupq_n_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u32" } } */ + +uint32x4_t +foo1 (uint32_t a) +{ + return vidupq_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c new file mode 100644 index 0000000..397d5e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a) +{ + return vidupq_n_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u8" } } */ + +uint8x16_t +foo1 (uint32_t a) +{ + return vidupq_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c new file mode 100644 index 0000000..d20b54d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t *a) +{ + return vidupq_wb_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vidup.u16" } } */ + +uint16x8_t +foo1 (uint32_t *a) +{ + return vidupq_u16 (a, 4); +} + +/* { dg-final { scan-assembler "vidup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c new file mode 100644 index 0000000..c751a7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t *a) +{ + return vidupq_wb_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u32" } } */ + +uint32x4_t +foo1 (uint32_t *a) +{ + return vidupq_u32 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c new file mode 100644 index 0000000..89c6da2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t *a) +{ + return vidupq_wb_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u8" } } */ + +uint8x16_t +foo1 (uint32_t *a) +{ + return vidupq_u8 (a, 1); +} + +/* { dg-final { scan-assembler "vidup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c new file mode 100644 index 0000000..b0317fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_n_u16 (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c new file mode 100644 index 0000000..2e0e0ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_n_u32 (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c new file mode 100644 index 0000000..1ce1fff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_n_u8 (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c new file mode 100644 index 0000000..834d3a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_wb_u16 (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c new file mode 100644 index 0000000..75fcd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_wb_u32 (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c new file mode 100644 index 0000000..a5ea588 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m_wb_u8 (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_m (inactive, a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c new file mode 100644 index 0000000..52536d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, uint32_t b) +{ + return viwdupq_n_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "viwdup.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, uint32_t b) +{ + return viwdupq_u16 (a, b, 2); +} + +/* { dg-final { scan-assembler "viwdup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c new file mode 100644 index 0000000..49b15be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, uint32_t b) +{ + return viwdupq_n_u32 (a, b, 4); +} + +/* { dg-final { scan-assembler "viwdup.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, uint32_t b) +{ + return viwdupq_u32 (a, b, 4); +} + +/* { dg-final { scan-assembler "viwdup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c new file mode 100644 index 0000000..4beff7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, uint32_t b) +{ + return viwdupq_n_u8 (a, b, 1); +} + +/* { dg-final { scan-assembler "viwdup.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, uint32_t b) +{ + return viwdupq_u8 (a, b, 1); +} + +/* { dg-final { scan-assembler "viwdup.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c new file mode 100644 index 0000000..0a88261 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t * a, uint32_t b) +{ + return viwdupq_wb_u16 (a, b, 4); +} + +/* { dg-final { scan-assembler "viwdup.u16" } } */ + +uint16x8_t +foo1 (uint32_t * a, uint32_t b) +{ + return viwdupq_u16 (a, b, 4); +} + +/* { dg-final { scan-assembler "viwdup.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c new file mode 100644 index 0000000..37e4f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t * a, uint32_t b) +{ + return viwdupq_wb_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "viwdup.u32" } } */ + +uint32x4_t +foo1 (uint32_t * a, uint32_t b) +{ + return viwdupq_u32 (a, b, 8); +} + +/* { dg-final { scan-assembler "viwdup.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c new file mode 100644 index 0000000..810bff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t * a, uint32_t b) +{ + return viwdupq_wb_u8 (a, b, 2); +} + +/* { dg-final { scan-assembler "viwdup.u8" } } */ + +uint8x16_t +foo1 (uint32_t * a, uint32_t b) +{ + return viwdupq_u8 (a, b, 2); +} + +/* { dg-final { scan-assembler "viwdup.u8" } } */ -- cgit v1.1 From 41e1a7ffae9e1e03dcfcad30b8d92561b44eb97b Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 12:06:26 +0000 Subject: [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store intrinsics with writeback. This patch supports following MVE ACLE intrinsics with writeback. vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, vldrwq_gather_base_wb_z_f32, vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, vstrdq_scatter_base_wb_p_s64, vstrdq_scatter_base_wb_p_u64, vstrdq_scatter_base_wb_s64, vstrdq_scatter_base_wb_u64, vstrwq_scatter_base_wb_p_s32, vstrwq_scatter_base_wb_p_f32, vstrwq_scatter_base_wb_p_u32, vstrwq_scatter_base_wb_s32, vstrwq_scatter_base_wb_u32, vstrwq_scatter_base_wb_f32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin qualifier. (LDRGBWBU_QUALIFIERS): Likewise. (LDRGBWBS_Z_QUALIFIERS): Likewise. (LDRGBWBU_Z_QUALIFIERS): Likewise. (STRSBWBS_QUALIFIERS): Likewise. (STRSBWBU_QUALIFIERS): Likewise. (STRSBWBS_P_QUALIFIERS): Likewise. (STRSBWBU_P_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro. (vldrdq_gather_base_wb_u64): Likewise. (vldrdq_gather_base_wb_z_s64): Likewise. (vldrdq_gather_base_wb_z_u64): Likewise. (vldrwq_gather_base_wb_f32): Likewise. (vldrwq_gather_base_wb_s32): Likewise. (vldrwq_gather_base_wb_u32): Likewise. (vldrwq_gather_base_wb_z_f32): Likewise. (vldrwq_gather_base_wb_z_s32): Likewise. (vldrwq_gather_base_wb_z_u32): Likewise. (vstrdq_scatter_base_wb_p_s64): Likewise. (vstrdq_scatter_base_wb_p_u64): Likewise. (vstrdq_scatter_base_wb_s64): Likewise. (vstrdq_scatter_base_wb_u64): Likewise. (vstrwq_scatter_base_wb_p_s32): Likewise. (vstrwq_scatter_base_wb_p_f32): Likewise. (vstrwq_scatter_base_wb_p_u32): Likewise. (vstrwq_scatter_base_wb_s32): Likewise. (vstrwq_scatter_base_wb_u32): Likewise. (vstrwq_scatter_base_wb_f32): Likewise. (__arm_vldrdq_gather_base_wb_s64): Define intrinsic. (__arm_vldrdq_gather_base_wb_u64): Likewise. (__arm_vldrdq_gather_base_wb_z_s64): Likewise. (__arm_vldrdq_gather_base_wb_z_u64): Likewise. (__arm_vldrwq_gather_base_wb_s32): Likewise. (__arm_vldrwq_gather_base_wb_u32): Likewise. (__arm_vldrwq_gather_base_wb_z_s32): Likewise. (__arm_vldrwq_gather_base_wb_z_u32): Likewise. (__arm_vstrdq_scatter_base_wb_s64): Likewise. (__arm_vstrdq_scatter_base_wb_u64): Likewise. (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. (__arm_vstrwq_scatter_base_wb_s32): Likewise. (__arm_vstrwq_scatter_base_wb_u32): Likewise. (__arm_vldrwq_gather_base_wb_f32): Likewise. (__arm_vldrwq_gather_base_wb_z_f32): Likewise. (__arm_vstrwq_scatter_base_wb_f32): Likewise. (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. (vstrwq_scatter_base_wb): Define polymorphic variant. (vstrwq_scatter_base_wb_p): Likewise. (vstrdq_scatter_base_wb_p): Likewise. (vstrdq_scatter_base_wb): Likewise. * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin qualifier. * config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Define RTL pattern. (mve_vstrwq_scatter_base_wb_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_v4si_insn): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si_insn): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise. (mve_vstrdq_scatter_base_wb_v2di): Likewise. (mve_vstrdq_scatter_base_wb_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_v2di_insn): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di_insn): Likewise. (mve_vldrwq_gather_base_wb_v4si): Likewise. (mve_vldrwq_gather_base_wb_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_z_v4si): Likewise. (mve_vldrwq_gather_base_wb_z_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. (mve_vldrdq_gather_base_wb_v2di): Likewise. (mve_vldrdq_gather_base_wb_v2di_insn): Likewise. (mve_vldrdq_gather_base_wb_z_v2di): Likewise. (mve_vldrdq_gather_base_wb_z_v2di_insn): Likewise. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: New test. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. --- gcc/ChangeLog | 91 ++++ gcc/config/arm/arm-builtins.c | 44 ++ gcc/config/arm/arm_mve.h | 238 +++++++++ gcc/config/arm/arm_mve_builtins.def | 30 ++ gcc/config/arm/mve.md | 583 ++++++++++++++++++++- gcc/testsuite/ChangeLog | 30 ++ .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + 26 files changed, 1370 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 22c9766..ab8d421 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,97 @@ Andre Vieira Mihail Ionescu + * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin + qualifier. + (LDRGBWBU_QUALIFIERS): Likewise. + (LDRGBWBS_Z_QUALIFIERS): Likewise. + (LDRGBWBU_Z_QUALIFIERS): Likewise. + (STRSBWBS_QUALIFIERS): Likewise. + (STRSBWBU_QUALIFIERS): Likewise. + (STRSBWBS_P_QUALIFIERS): Likewise. + (STRSBWBU_P_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro. + (vldrdq_gather_base_wb_u64): Likewise. + (vldrdq_gather_base_wb_z_s64): Likewise. + (vldrdq_gather_base_wb_z_u64): Likewise. + (vldrwq_gather_base_wb_f32): Likewise. + (vldrwq_gather_base_wb_s32): Likewise. + (vldrwq_gather_base_wb_u32): Likewise. + (vldrwq_gather_base_wb_z_f32): Likewise. + (vldrwq_gather_base_wb_z_s32): Likewise. + (vldrwq_gather_base_wb_z_u32): Likewise. + (vstrdq_scatter_base_wb_p_s64): Likewise. + (vstrdq_scatter_base_wb_p_u64): Likewise. + (vstrdq_scatter_base_wb_s64): Likewise. + (vstrdq_scatter_base_wb_u64): Likewise. + (vstrwq_scatter_base_wb_p_s32): Likewise. + (vstrwq_scatter_base_wb_p_f32): Likewise. + (vstrwq_scatter_base_wb_p_u32): Likewise. + (vstrwq_scatter_base_wb_s32): Likewise. + (vstrwq_scatter_base_wb_u32): Likewise. + (vstrwq_scatter_base_wb_f32): Likewise. + (__arm_vldrdq_gather_base_wb_s64): Define intrinsic. + (__arm_vldrdq_gather_base_wb_u64): Likewise. + (__arm_vldrdq_gather_base_wb_z_s64): Likewise. + (__arm_vldrdq_gather_base_wb_z_u64): Likewise. + (__arm_vldrwq_gather_base_wb_s32): Likewise. + (__arm_vldrwq_gather_base_wb_u32): Likewise. + (__arm_vldrwq_gather_base_wb_z_s32): Likewise. + (__arm_vldrwq_gather_base_wb_z_u32): Likewise. + (__arm_vstrdq_scatter_base_wb_s64): Likewise. + (__arm_vstrdq_scatter_base_wb_u64): Likewise. + (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. + (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. + (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. + (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. + (__arm_vstrwq_scatter_base_wb_s32): Likewise. + (__arm_vstrwq_scatter_base_wb_u32): Likewise. + (__arm_vldrwq_gather_base_wb_f32): Likewise. + (__arm_vldrwq_gather_base_wb_z_f32): Likewise. + (__arm_vstrwq_scatter_base_wb_f32): Likewise. + (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. + (vstrwq_scatter_base_wb): Define polymorphic variant. + (vstrwq_scatter_base_wb_p): Likewise. + (vstrdq_scatter_base_wb_p): Likewise. + (vstrdq_scatter_base_wb): Likewise. + * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin + qualifier. + * config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Define RTL + pattern. + (mve_vstrwq_scatter_base_wb_add_v4si): Likewise. + (mve_vstrwq_scatter_base_wb_v4si_insn): Likewise. + (mve_vstrwq_scatter_base_wb_p_v4si): Likewise. + (mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise. + (mve_vstrwq_scatter_base_wb_p_v4si_insn): Likewise. + (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise. + (mve_vstrdq_scatter_base_wb_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_add_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_v2di_insn): Likewise. + (mve_vstrdq_scatter_base_wb_p_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_p_v2di_insn): Likewise. + (mve_vldrwq_gather_base_wb_v4si): Likewise. + (mve_vldrwq_gather_base_wb_v4si_insn): Likewise. + (mve_vldrwq_gather_base_wb_z_v4si): Likewise. + (mve_vldrwq_gather_base_wb_z_v4si_insn): Likewise. + (mve_vldrwq_gather_base_wb_fv4sf): Likewise. + (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. + (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise. + (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. + (mve_vldrdq_gather_base_wb_v2di): Likewise. + (mve_vldrdq_gather_base_wb_v2di_insn): Likewise. + (mve_vldrdq_gather_base_wb_z_v2di): Likewise. + (mve_vldrdq_gather_base_wb_z_v2di_insn): Likewise. + +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + * config/arm/arm-builtins.c (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary builtin qualifier. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index cefc144..ecdd95f 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -718,6 +718,50 @@ arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ (arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers) +static enum arm_type_qualifiers +arm_ldrgbwbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_immediate}; +#define LDRGBWBS_QUALIFIERS (arm_ldrgbwbs_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; +#define LDRGBWBU_QUALIFIERS (arm_ldrgbwbu_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers) + +static enum arm_type_qualifiers +arm_strsbwbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_const, qualifier_none}; +#define STRSBWBS_QUALIFIERS (arm_strsbwbs_qualifiers) + +static enum arm_type_qualifiers +arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_const, qualifier_unsigned}; +#define STRSBWBU_QUALIFIERS (arm_strsbwbu_qualifiers) + +static enum arm_type_qualifiers +arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_const, + qualifier_none, qualifier_unsigned}; +#define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers) + +static enum arm_type_qualifiers +arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_const, + qualifier_unsigned, qualifier_unsigned}; +#define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 00f2242..969908b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2054,6 +2054,26 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define viwdupq_wb_u8( __a, __b, __imm) __arm_viwdupq_wb_u8( __a, __b, __imm) #define viwdupq_wb_u32( __a, __b, __imm) __arm_viwdupq_wb_u32( __a, __b, __imm) #define viwdupq_wb_u16( __a, __b, __imm) __arm_viwdupq_wb_u16( __a, __b, __imm) +#define vldrdq_gather_base_wb_s64(__addr, __offset) __arm_vldrdq_gather_base_wb_s64(__addr, __offset) +#define vldrdq_gather_base_wb_u64(__addr, __offset) __arm_vldrdq_gather_base_wb_u64(__addr, __offset) +#define vldrdq_gather_base_wb_z_s64(__addr, __offset, __p) __arm_vldrdq_gather_base_wb_z_s64(__addr, __offset, __p) +#define vldrdq_gather_base_wb_z_u64(__addr, __offset, __p) __arm_vldrdq_gather_base_wb_z_u64(__addr, __offset, __p) +#define vldrwq_gather_base_wb_f32(__addr, __offset) __arm_vldrwq_gather_base_wb_f32(__addr, __offset) +#define vldrwq_gather_base_wb_s32(__addr, __offset) __arm_vldrwq_gather_base_wb_s32(__addr, __offset) +#define vldrwq_gather_base_wb_u32(__addr, __offset) __arm_vldrwq_gather_base_wb_u32(__addr, __offset) +#define vldrwq_gather_base_wb_z_f32(__addr, __offset, __p) __arm_vldrwq_gather_base_wb_z_f32(__addr, __offset, __p) +#define vldrwq_gather_base_wb_z_s32(__addr, __offset, __p) __arm_vldrwq_gather_base_wb_z_s32(__addr, __offset, __p) +#define vldrwq_gather_base_wb_z_u32(__addr, __offset, __p) __arm_vldrwq_gather_base_wb_z_u32(__addr, __offset, __p) +#define vstrdq_scatter_base_wb_p_s64(__addr, __offset, __value, __p) __arm_vstrdq_scatter_base_wb_p_s64(__addr, __offset, __value, __p) +#define vstrdq_scatter_base_wb_p_u64(__addr, __offset, __value, __p) __arm_vstrdq_scatter_base_wb_p_u64(__addr, __offset, __value, __p) +#define vstrdq_scatter_base_wb_s64(__addr, __offset, __value) __arm_vstrdq_scatter_base_wb_s64(__addr, __offset, __value) +#define vstrdq_scatter_base_wb_u64(__addr, __offset, __value) __arm_vstrdq_scatter_base_wb_u64(__addr, __offset, __value) +#define vstrwq_scatter_base_wb_p_s32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_wb_p_s32(__addr, __offset, __value, __p) +#define vstrwq_scatter_base_wb_p_f32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_wb_p_f32(__addr, __offset, __value, __p) +#define vstrwq_scatter_base_wb_p_u32(__addr, __offset, __value, __p) __arm_vstrwq_scatter_base_wb_p_u32(__addr, __offset, __value, __p) +#define vstrwq_scatter_base_wb_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_s32(__addr, __offset, __value) +#define vstrwq_scatter_base_wb_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_u32(__addr, __offset, __value) +#define vstrwq_scatter_base_wb_f32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_f32(__addr, __offset, __value) #endif __extension__ extern __inline void @@ -13388,6 +13408,150 @@ __arm_viwdupq_wb_u16 (uint32_t * __a, uint32_t __b, const int __imm) return __res; } +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_wb_s64 (uint64x2_t * __addr, const int __offset) +{ + int64x2_t + result = __builtin_mve_vldrdq_gather_base_wb_sv2di (*__addr, __offset); + __addr += __offset; + return result; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_wb_u64 (uint64x2_t * __addr, const int __offset) +{ + uint64x2_t + result = __builtin_mve_vldrdq_gather_base_wb_uv2di (*__addr, __offset); + __addr += __offset; + return result; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_wb_z_s64 (uint64x2_t * __addr, const int __offset, mve_pred16_t __p) +{ + int64x2_t + result = __builtin_mve_vldrdq_gather_base_wb_z_sv2di (*__addr, __offset, __p); + __addr += __offset; + return result; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrdq_gather_base_wb_z_u64 (uint64x2_t * __addr, const int __offset, mve_pred16_t __p) +{ + uint64x2_t + result = __builtin_mve_vldrdq_gather_base_wb_z_uv2di (*__addr, __offset, __p); + __addr += __offset; + return result; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_s32 (uint32x4_t * __addr, const int __offset) +{ + int32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_sv4si (*__addr, __offset); + __addr += __offset; + return result; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_u32 (uint32x4_t * __addr, const int __offset) +{ + uint32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_uv4si (*__addr, __offset); + __addr += __offset; + return result; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_z_s32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p) +{ + int32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_z_sv4si (*__addr, __offset, __p); + __addr += __offset; + return result; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_z_u32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p) +{ + uint32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_z_uv4si (*__addr, __offset, __p); + __addr += __offset; + return result; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_wb_s64 (uint64x2_t * __addr, const int __offset, int64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_base_wb_sv2di (*__addr, __offset, __value); + __builtin_mve_vstrdq_scatter_base_wb_add_sv2di (*__addr, __offset, *__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_wb_u64 (uint64x2_t * __addr, const int __offset, uint64x2_t __value) +{ + __builtin_mve_vstrdq_scatter_base_wb_uv2di (*__addr, __offset, __value); + __builtin_mve_vstrdq_scatter_base_wb_add_uv2di (*__addr, __offset, *__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_wb_p_s64 (uint64x2_t * __addr, const int __offset, int64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_base_wb_p_sv2di (*__addr, __offset, __value, __p); + __builtin_mve_vstrdq_scatter_base_wb_p_add_sv2di (*__addr, __offset, *__addr, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrdq_scatter_base_wb_p_u64 (uint64x2_t * __addr, const int __offset, uint64x2_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrdq_scatter_base_wb_p_uv2di (*__addr, __offset, __value, __p); + __builtin_mve_vstrdq_scatter_base_wb_p_add_uv2di (*__addr, __offset, *__addr, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_p_s32 (uint32x4_t * __addr, const int __offset, int32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_wb_p_sv4si (*__addr, __offset, __value, __p); + __builtin_mve_vstrwq_scatter_base_wb_p_add_sv4si (*__addr, __offset, *__addr, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_p_u32 (uint32x4_t * __addr, const int __offset, uint32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_wb_p_uv4si (*__addr, __offset, __value, __p); + __builtin_mve_vstrwq_scatter_base_wb_p_add_uv4si (*__addr, __offset, *__addr, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_s32 (uint32x4_t * __addr, const int __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_wb_sv4si (*__addr, __offset, __value); + __builtin_mve_vstrwq_scatter_base_wb_add_sv4si (*__addr, __offset, *__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_u32 (uint32x4_t * __addr, const int __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_wb_uv4si (*__addr, __offset, __value); + __builtin_mve_vstrwq_scatter_base_wb_add_uv4si (*__addr, __offset, *__addr); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -16024,6 +16188,42 @@ __arm_vreinterpretq_f32_u8 (uint8x16_t __a) return (float32x4_t) __a; } +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset) +{ + float32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset); + __addr += __offset; + return result; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p) +{ + float32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p); + __addr += __offset; + return result; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value); + __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p); + __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p); +} + #endif enum { @@ -18940,8 +19140,34 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) +#define vstrwq_scatter_base_wb(p0,p1,p2) __arm_vstrwq_scatter_base_wb(p0,p1,p2) +#define __arm_vstrwq_scatter_base_wb(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_wb_f32 (p0, p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + +#define vstrwq_scatter_base_wb_p(p0,p1,p2,p3) __arm_vstrwq_scatter_base_wb_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_base_wb_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_wb_p_f32 (p0, p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + #else /* MVE Integer. */ +#define vstrwq_scatter_base_wb(p0,p1,p2) __arm_vstrwq_scatter_base_wb(p0,p1,p2) +#define __arm_vstrwq_scatter_base_wb(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_base_wb_p(p0,p1,p2,p3) __arm_vstrwq_scatter_base_wb_p(p0,p1,p2,p3) +#define __arm_vstrwq_scatter_base_wb_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + #define vst4q(p0,p1) __arm_vst4q(p0,p1) #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -21424,6 +21650,18 @@ extern void *__ARM_undef; #endif /* MVE Integer. */ +#define vstrdq_scatter_base_wb_p(p0,p1,p2,p3) __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3) +#define __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_base_wb_p_s64 (p0, p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_p_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + +#define vstrdq_scatter_base_wb(p0,p1,p2) __arm_vstrdq_scatter_base_wb(p0,p1,p2) +#define __arm_vstrdq_scatter_base_wb(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_base_wb_s64 (p0, p1, __ARM_mve_coerce(__p2, int64x2_t)), \ + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + #define vldrdq_gather_offset(p0,p1) __arm_vldrdq_gather_offset(p0,p1) #define __arm_vldrdq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 2ed7886..9fc0a8a 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -827,3 +827,33 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vddupq_m_n_u, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vidupq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) +VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) +VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_u, v4si) +VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_s, v4si) +VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_f, v4sf) +VAR1 (STRSBWBU, vstrdq_scatter_base_wb_u, v2di) +VAR1 (STRSBWBU, vstrdq_scatter_base_wb_add_u, v2di) +VAR1 (STRSBWBU, vstrdq_scatter_base_wb_add_s, v2di) +VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_u, v4si) +VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_u, v4si) +VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_s, v4si) +VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_f, v4sf) +VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_u, v2di) +VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_add_u, v2di) +VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_add_s, v2di) +VAR1 (STRSBWBS, vstrwq_scatter_base_wb_s, v4si) +VAR1 (STRSBWBS, vstrwq_scatter_base_wb_f, v4sf) +VAR1 (STRSBWBS, vstrdq_scatter_base_wb_s, v2di) +VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_s, v4si) +VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_f, v4sf) +VAR1 (STRSBWBS_P, vstrdq_scatter_base_wb_p_s, v2di) +VAR1 (LDRGBWBU_Z, vldrwq_gather_base_wb_z_u, v4si) +VAR1 (LDRGBWBU_Z, vldrdq_gather_base_wb_z_u, v2di) +VAR1 (LDRGBWBU, vldrwq_gather_base_wb_u, v4si) +VAR1 (LDRGBWBU, vldrdq_gather_base_wb_u, v2di) +VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_s, v4si) +VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_f, v4sf) +VAR1 (LDRGBWBS_Z, vldrdq_gather_base_wb_z_s, v2di) +VAR1 (LDRGBWBS, vldrwq_gather_base_wb_s, v4si) +VAR1 (LDRGBWBS, vldrwq_gather_base_wb_f, v4sf) +VAR1 (LDRGBWBS, vldrdq_gather_base_wb_s, v2di) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b2702f5..a22e752 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -208,7 +208,10 @@ VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F VSTRWQSO_F VSTRWQSSO_F VDDUPQ VDDUPQ_M VDWDUPQ - VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M]) + VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M + VSTRWQSBWB_S VSTRWQSBWB_U VLDRWQGBWB_S VLDRWQGBWB_U + VSTRWQSBWB_F VLDRWQGBWB_F VSTRDQSBWB_S VSTRDQSBWB_U + VLDRDQGBWB_S VLDRDQGBWB_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -377,7 +380,10 @@ (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s") (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u") (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u") - (VSTRWQSSO_S "s")]) + (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u") + (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s") + (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") + (VSTRDQSBWB_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -626,6 +632,10 @@ (define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U]) (define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U]) (define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U]) +(define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U]) +(define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U]) +(define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U]) +(define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -10042,3 +10052,572 @@ "vpst\;\tviwdupt.u%#\t%q2, %3, %4, %5" [(set_attr "type" "mve_move") (set_attr "length""8")]) +(define_expand "mve_vstrwq_scatter_base_wb_v4si" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "w") + (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_v4si_insn (ignore_wb, operands[0], + operands[1], operands[2])); + DONE; +}) + +(define_expand "mve_vstrwq_scatter_base_wb_add_v4si" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "0") + (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_v4si_insn (operands[0], operands[2], + operands[1], ignore_vec)); + DONE; +}) + +;; +;; [vstrwq_scatter_base_wb_s vstrdq_scatter_base_wb_u] +;; +(define_insn "mve_vstrwq_scatter_base_wb_v4si_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 3 "s_register_operand" "w")] + VSTRWSBWBQ)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] + VSTRWSBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vstrwq_scatter_base_wb_p_v4si" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_p_v4si_insn (ignore_wb, operands[0], + operands[1], operands[2], + operands[3])); + DONE; +}) + +(define_expand "mve_vstrwq_scatter_base_wb_p_add_v4si" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "0") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_p_v4si_insn (operands[0], operands[2], + operands[1], ignore_vec, + operands[3])); + DONE; +}) + +;; +;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] +;; +(define_insn "mve_vstrwq_scatter_base_wb_p_v4si_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand")] + VSTRWSBWBQ)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] + VSTRWSBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vstrwq_scatter_base_wb_fv4sf" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SF 2 "s_register_operand" "w") + (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (ignore_wb,operands[0], + operands[1], operands[2])); + DONE; +}) + +(define_expand "mve_vstrwq_scatter_base_wb_add_fv4sf" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "0") + (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_vec = gen_reg_rtx (V4SFmode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (operands[0], operands[2], + operands[1], ignore_vec)); + DONE; +}) + +;; +;; [vstrwq_scatter_base_wb_f] +;; +(define_insn "mve_vstrwq_scatter_base_wb_fv4sf_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SF 3 "s_register_operand" "w")] + VSTRWQSBWB_F)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] + VSTRWQSBWB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vstrwq_scatter_base_wb_p_fv4sf" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SF 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (ignore_wb, operands[0], + operands[1], operands[2], + operands[3])); + DONE; +}) + +(define_expand "mve_vstrwq_scatter_base_wb_p_add_fv4sf" + [(match_operand:V4SI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 2 "s_register_operand" "0") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_vec = gen_reg_rtx (V4SFmode); + emit_insn ( + gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (operands[0], operands[2], + operands[1], ignore_vec, + operands[3])); + DONE; +}) + +;; +;; [vstrwq_scatter_base_wb_p_f] +;; +(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SF 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand")] + VSTRWQSBWB_F)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] + VSTRWQSBWB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vstrdq_scatter_base_wb_v2di" + [(match_operand:V2DI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "w") + (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vstrdq_scatter_base_wb_v2di_insn (ignore_wb, operands[0], + operands[1], operands[2])); + DONE; +}) + +(define_expand "mve_vstrdq_scatter_base_wb_add_v2di" + [(match_operand:V2DI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "0") + (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vstrdq_scatter_base_wb_v2di_insn (operands[0], operands[2], + operands[1], ignore_vec)); + DONE; +}) + +;; +;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] +;; +(define_insn "mve_vstrdq_scatter_base_wb_v2di_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V2DI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 3 "s_register_operand" "w")] + VSTRDSBWBQ)) + (set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_dup 1) (match_dup 2)] + VSTRDSBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vstrdq_scatter_base_wb_p_v2di" + [(match_operand:V2DI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vstrdq_scatter_base_wb_p_v2di_insn (ignore_wb, operands[0], + operands[1], operands[2], + operands[3])); + DONE; +}) + +(define_expand "mve_vstrdq_scatter_base_wb_p_add_v2di" + [(match_operand:V2DI 0 "s_register_operand" "=w") + (match_operand:SI 1 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 2 "s_register_operand" "0") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vstrdq_scatter_base_wb_p_v2di_insn (operands[0], operands[2], + operands[1], ignore_vec, + operands[3])); + DONE; +}) + +;; +;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] +;; +(define_insn "mve_vstrdq_scatter_base_wb_p_v2di_insn" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V2DI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand")] + VSTRDSBWBQ)) + (set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_dup 1) (match_dup 2)] + VSTRDSBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]!",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vldrwq_gather_base_wb_v4si" + [(match_operand:V4SI 0 "s_register_operand") + (match_operand:V4SI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vldrwq_gather_base_wb_v4si_insn (operands[0], ignore_wb, + operands[1], operands[2])); + DONE; +}) + +;; +;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u] +;; +(define_insn "mve_vldrwq_gather_base_wb_v4si_insn" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (mem:BLK (scratch))] + VLDRWGBWBQ)) + (set (match_operand:V4SI 1 "s_register_operand" "=&w") + (unspec:V4SI [(match_dup 2) (match_dup 3)] + VLDRWGBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vldrwq_gather_base_wb_z_v4si" + [(match_operand:V4SI 0 "s_register_operand") + (match_operand:V4SI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vldrwq_gather_base_wb_z_v4si_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u] +;; +(define_insn "mve_vldrwq_gather_base_wb_z_v4si_insn" + [(set (match_operand:V4SI 0 "s_register_operand" "=&w") + (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (match_operand:HI 4 "vpr_register_operand" "Up") + (mem:BLK (scratch))] + VLDRWGBWBQ)) + (set (match_operand:V4SI 1 "s_register_operand" "=&w") + (unspec:V4SI [(match_dup 2) (match_dup 3)] + VLDRWGBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vldrwq_gather_base_wb_fv4sf" + [(match_operand:V4SF 0 "s_register_operand") + (match_operand:V4SI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb, + operands[1], operands[2])); + DONE; +}) + +;; +;; [vldrwq_gather_base_wb_f] +;; +(define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (mem:BLK (scratch))] + VLDRWQGBWB_F)) + (set (match_operand:V4SI 1 "s_register_operand" "=&w") + (unspec:V4SI [(match_dup 2) (match_dup 3)] + VLDRWQGBWB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" + [(match_operand:V4SF 0 "s_register_operand") + (match_operand:V4SI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ignore_wb = gen_reg_rtx (V4SImode); + emit_insn ( + gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [vldrwq_gather_base_wb_z_f] +;; +(define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" + [(set (match_operand:V4SF 0 "s_register_operand" "=&w") + (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (match_operand:HI 4 "vpr_register_operand" "Up") + (mem:BLK (scratch))] + VLDRWQGBWB_F)) + (set (match_operand:V4SI 1 "s_register_operand" "=&w") + (unspec:V4SI [(match_dup 2) (match_dup 3)] + VLDRWQGBWB_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vldrdq_gather_base_wb_v2di" + [(match_operand:V2DI 0 "s_register_operand") + (match_operand:V2DI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vldrdq_gather_base_wb_v2di_insn (operands[0], ignore_wb, + operands[1], operands[2])); + DONE; +}) + +;; +;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u] +;; +(define_insn "mve_vldrdq_gather_base_wb_v2di_insn" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (mem:BLK (scratch))] + VLDRDGBWBQ)) + (set (match_operand:V2DI 1 "s_register_operand" "=&w") + (unspec:V2DI [(match_dup 2) (match_dup 3)] + VLDRDGBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "4")]) + +(define_expand "mve_vldrdq_gather_base_wb_z_v2di" + [(match_operand:V2DI 0 "s_register_operand") + (match_operand:V2DI 1 "s_register_operand") + (match_operand:SI 2 "mve_vldrd_immediate") + (match_operand:HI 3 "vpr_register_operand") + (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb = gen_reg_rtx (V2DImode); + emit_insn ( + gen_mve_vldrdq_gather_base_wb_z_v2di_insn (operands[0], ignore_wb, + operands[1], operands[2], + operands[3])); + DONE; +}) + +;; +;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] +;; +(define_insn "mve_vldrdq_gather_base_wb_z_v2di_insn" + [(set (match_operand:V2DI 0 "s_register_operand" "=&w") + (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") + (match_operand:SI 3 "mve_vldrd_immediate" "Ri") + (match_operand:HI 4 "vpr_register_operand" "Up") + (mem:BLK (scratch))] + VLDRDGBWBQ)) + (set (match_operand:V2DI 1 "s_register_operand" "=&w") + (unspec:V2DI [(match_dup 2) (match_dup 3)] + VLDRDGBWBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[2]; + ops[2] = operands[3]; + output_asm_insn ("vpst\;\tvldrdt.u64\t%q0, [%q1, %2]!",ops); + return ""; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4506849..11b7afb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,36 @@ Andre Vieira Mihail Ionescu + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: New test. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. + +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: New test. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c new file mode 100644 index 0000000..763a72e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (uint64x2_t * addr) +{ + return vldrdq_gather_base_wb_s64 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c new file mode 100644 index 0000000..df719f9b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64x2_t * addr) +{ + return vldrdq_gather_base_wb_u64 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrd.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c new file mode 100644 index 0000000..c22adfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ +#include "arm_mve.h" + +int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) +{ + return vldrdq_gather_base_wb_z_s64 (addr, 1016, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c new file mode 100644 index 0000000..385c0d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ +#include "arm_mve.h" + +uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) +{ + return vldrdq_gather_base_wb_z_u64 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c new file mode 100644 index 0000000..12473c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t * addr) +{ + return vldrwq_gather_base_wb_f32 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c new file mode 100644 index 0000000..619e41a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t * addr) +{ + return vldrwq_gather_base_wb_s32 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c new file mode 100644 index 0000000..144e7f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t * addr) +{ + return vldrwq_gather_base_wb_u32 (addr, 8); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c new file mode 100644 index 0000000..d69f9bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t * addr, mve_pred16_t p) +{ + return vldrwq_gather_base_wb_z_f32 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c new file mode 100644 index 0000000..620dec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t * addr, mve_pred16_t p) +{ + return vldrwq_gather_base_wb_z_s32 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c new file mode 100644 index 0000000..409ecf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t * addr, mve_pred16_t p) +{ + return vldrwq_gather_base_wb_z_u32 (addr, 8, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c new file mode 100644 index 0000000..9fc4e34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ + +void +foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_wb_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c new file mode 100644 index 0000000..0434f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ + +void +foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) +{ + vstrdq_scatter_base_wb_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrdt.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c new file mode 100644 index 0000000..9989564 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t * addr, const int offset, int64x2_t value) +{ + vstrdq_scatter_base_wb_s64 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ + +void +foo1 (uint64x2_t * addr, const int offset, int64x2_t value) +{ + vstrdq_scatter_base_wb (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c new file mode 100644 index 0000000..60c71d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint64x2_t * addr, const int offset, uint64x2_t value) +{ + vstrdq_scatter_base_wb_u64 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ + +void +foo1 (uint64x2_t * addr, const int offset, uint64x2_t value) +{ + vstrdq_scatter_base_wb (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrd.u64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c new file mode 100644 index 0000000..2bae380 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, const int offset, float32x4_t value) +{ + vstrwq_scatter_base_wb_f32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t * addr, const int offset, float32x4_t value) +{ + vstrwq_scatter_base_wb (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c new file mode 100644 index 0000000..dee9413 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c new file mode 100644 index 0000000..3a0423a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c new file mode 100644 index 0000000..32eb757 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ + +void +foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +{ + vstrwq_scatter_base_wb_p (addr, 8, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c new file mode 100644 index 0000000..4c232e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, const int offset, int32x4_t value) +{ + vstrwq_scatter_base_wb_s32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t * addr, const int offset, int32x4_t value) +{ + vstrwq_scatter_base_wb (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c new file mode 100644 index 0000000..7171a9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t * addr, uint32x4_t value) +{ + vstrwq_scatter_base_wb_u32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t * addr, uint32x4_t value) +{ + vstrwq_scatter_base_wb (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ -- cgit v1.1 From 3d42842c07f4143042f3dcc39a050b262bcf1b55 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 20 Mar 2020 15:00:11 +0100 Subject: fix CTOR vectorization We failed to handle pattern stmts appropriately. 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts to vectorize for CTOR defs. --- gcc/ChangeLog | 5 +++++ gcc/tree-vect-slp.c | 1 + 2 files changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ab8d421..3623455 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-20 Richard Biener + + * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts + to vectorize for CTOR defs. + 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index 9d17e33..fb13af7 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -2257,6 +2257,7 @@ vect_analyze_slp_instance (vec_info *vinfo, /* Value is defined in another basic block. */ if (!def_info) return false; + def_info = vect_stmt_to_vectorize (def_info); scalar_stmts.safe_push (def_info); } else -- cgit v1.1 From 261014a1be433a27af75fb7eecc77231261d84f7 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 14:14:35 +0000 Subject: [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-care) variant. This patch supports following MVE ACLE predicated intrinsic with `_x` (dont-care) variant. * ``_x`` (dont-care) which indicates that the false-predicated lanes have undefined values. These are syntactic sugar for merge intrinsics with a ``vuninitializedq`` inactive parameter. vabdq_x_f16, vabdq_x_f32, vabdq_x_s16, vabdq_x_s32, vabdq_x_s8, vabdq_x_u16, vabdq_x_u32, vabdq_x_u8, vabsq_x_f16, vabsq_x_f32, vabsq_x_s16, vabsq_x_s32, vabsq_x_s8, vaddq_x_f16, vaddq_x_f32, vaddq_x_n_f16, vaddq_x_n_f32, vaddq_x_n_s16, vaddq_x_n_s32, vaddq_x_n_s8, vaddq_x_n_u16, vaddq_x_n_u32, vaddq_x_n_u8, vaddq_x_s16, vaddq_x_s32, vaddq_x_s8, vaddq_x_u16, vaddq_x_u32, vaddq_x_u8, vandq_x_f16, vandq_x_f32, vandq_x_s16, vandq_x_s32, vandq_x_s8, vandq_x_u16, vandq_x_u32, vandq_x_u8, vbicq_x_f16, vbicq_x_f32, vbicq_x_s16, vbicq_x_s32, vbicq_x_s8, vbicq_x_u16, vbicq_x_u32, vbicq_x_u8, vbrsrq_x_n_f16, vbrsrq_x_n_f32, vbrsrq_x_n_s16, vbrsrq_x_n_s32, vbrsrq_x_n_s8, vbrsrq_x_n_u16, vbrsrq_x_n_u32, vbrsrq_x_n_u8, vcaddq_rot270_x_f16, vcaddq_rot270_x_f32, vcaddq_rot270_x_s16, vcaddq_rot270_x_s32, vcaddq_rot270_x_s8, vcaddq_rot270_x_u16, vcaddq_rot270_x_u32, vcaddq_rot270_x_u8, vcaddq_rot90_x_f16, vcaddq_rot90_x_f32, vcaddq_rot90_x_s16, vcaddq_rot90_x_s32, vcaddq_rot90_x_s8, vcaddq_rot90_x_u16, vcaddq_rot90_x_u32, vcaddq_rot90_x_u8, vclsq_x_s16, vclsq_x_s32, vclsq_x_s8, vclzq_x_s16, vclzq_x_s32, vclzq_x_s8, vclzq_x_u16, vclzq_x_u32, vclzq_x_u8, vcmulq_rot180_x_f16, vcmulq_rot180_x_f32, vcmulq_rot270_x_f16, vcmulq_rot270_x_f32, vcmulq_rot90_x_f16, vcmulq_rot90_x_f32, vcmulq_x_f16, vcmulq_x_f32, vcvtaq_x_s16_f16, vcvtaq_x_s32_f32, vcvtaq_x_u16_f16, vcvtaq_x_u32_f32, vcvtbq_x_f32_f16, vcvtmq_x_s16_f16, vcvtmq_x_s32_f32, vcvtmq_x_u16_f16, vcvtmq_x_u32_f32, vcvtnq_x_s16_f16, vcvtnq_x_s32_f32, vcvtnq_x_u16_f16, vcvtnq_x_u32_f32, vcvtpq_x_s16_f16, vcvtpq_x_s32_f32, vcvtpq_x_u16_f16, vcvtpq_x_u32_f32, vcvtq_x_f16_s16, vcvtq_x_f16_u16, vcvtq_x_f32_s32, vcvtq_x_f32_u32, vcvtq_x_n_f16_s16, vcvtq_x_n_f16_u16, vcvtq_x_n_f32_s32, vcvtq_x_n_f32_u32, vcvtq_x_n_s16_f16, vcvtq_x_n_s32_f32, vcvtq_x_n_u16_f16, vcvtq_x_n_u32_f32, vcvtq_x_s16_f16, vcvtq_x_s32_f32, vcvtq_x_u16_f16, vcvtq_x_u32_f32, vcvttq_x_f32_f16, vddupq_x_n_u16, vddupq_x_n_u32, vddupq_x_n_u8, vddupq_x_wb_u16, vddupq_x_wb_u32, vddupq_x_wb_u8, vdupq_x_n_f16, vdupq_x_n_f32, vdupq_x_n_s16, vdupq_x_n_s32, vdupq_x_n_s8, vdupq_x_n_u16, vdupq_x_n_u32, vdupq_x_n_u8, vdwdupq_x_n_u16, vdwdupq_x_n_u32, vdwdupq_x_n_u8, vdwdupq_x_wb_u16, vdwdupq_x_wb_u32, vdwdupq_x_wb_u8, veorq_x_f16, veorq_x_f32, veorq_x_s16, veorq_x_s32, veorq_x_s8, veorq_x_u16, veorq_x_u32, veorq_x_u8, vhaddq_x_n_s16, vhaddq_x_n_s32, vhaddq_x_n_s8, vhaddq_x_n_u16, vhaddq_x_n_u32, vhaddq_x_n_u8, vhaddq_x_s16, vhaddq_x_s32, vhaddq_x_s8, vhaddq_x_u16, vhaddq_x_u32, vhaddq_x_u8, vhcaddq_rot270_x_s16, vhcaddq_rot270_x_s32, vhcaddq_rot270_x_s8, vhcaddq_rot90_x_s16, vhcaddq_rot90_x_s32, vhcaddq_rot90_x_s8, vhsubq_x_n_s16, vhsubq_x_n_s32, vhsubq_x_n_s8, vhsubq_x_n_u16, vhsubq_x_n_u32, vhsubq_x_n_u8, vhsubq_x_s16, vhsubq_x_s32, vhsubq_x_s8, vhsubq_x_u16, vhsubq_x_u32, vhsubq_x_u8, vidupq_x_n_u16, vidupq_x_n_u32, vidupq_x_n_u8, vidupq_x_wb_u16, vidupq_x_wb_u32, vidupq_x_wb_u8, viwdupq_x_n_u16, viwdupq_x_n_u32, viwdupq_x_n_u8, viwdupq_x_wb_u16, viwdupq_x_wb_u32, viwdupq_x_wb_u8, vmaxnmq_x_f16, vmaxnmq_x_f32, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vminnmq_x_f16, vminnmq_x_f32, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vmulq_x_f16, vmulq_x_f32, vmulq_x_n_f16, vmulq_x_n_f32, vmulq_x_n_s16, vmulq_x_n_s32, vmulq_x_n_s8, vmulq_x_n_u16, vmulq_x_n_u32, vmulq_x_n_u8, vmulq_x_s16, vmulq_x_s32, vmulq_x_s8, vmulq_x_u16, vmulq_x_u32, vmulq_x_u8, vmvnq_x_n_s16, vmvnq_x_n_s32, vmvnq_x_n_u16, vmvnq_x_n_u32, vmvnq_x_s16, vmvnq_x_s32, vmvnq_x_s8, vmvnq_x_u16, vmvnq_x_u32, vmvnq_x_u8, vnegq_x_f16, vnegq_x_f32, vnegq_x_s16, vnegq_x_s32, vnegq_x_s8, vornq_x_f16, vornq_x_f32, vornq_x_s16, vornq_x_s32, vornq_x_s8, vornq_x_u16, vornq_x_u32, vornq_x_u8, vorrq_x_f16, vorrq_x_f32, vorrq_x_s16, vorrq_x_s32, vorrq_x_s8, vorrq_x_u16, vorrq_x_u32, vorrq_x_u8, vrev16q_x_s8, vrev16q_x_u8, vrev32q_x_f16, vrev32q_x_s16, vrev32q_x_s8, vrev32q_x_u16, vrev32q_x_u8, vrev64q_x_f16, vrev64q_x_f32, vrev64q_x_s16, vrev64q_x_s32, vrev64q_x_s8, vrev64q_x_u16, vrev64q_x_u32, vrev64q_x_u8, vrhaddq_x_s16, vrhaddq_x_s32, vrhaddq_x_s8, vrhaddq_x_u16, vrhaddq_x_u32, vrhaddq_x_u8, vrmulhq_x_s16, vrmulhq_x_s32, vrmulhq_x_s8, vrmulhq_x_u16, vrmulhq_x_u32, vrmulhq_x_u8, vrndaq_x_f16, vrndaq_x_f32, vrndmq_x_f16, vrndmq_x_f32, vrndnq_x_f16, vrndnq_x_f32, vrndpq_x_f16, vrndpq_x_f32, vrndq_x_f16, vrndq_x_f32, vrndxq_x_f16, vrndxq_x_f32, vrshlq_x_s16, vrshlq_x_s32, vrshlq_x_s8, vrshlq_x_u16, vrshlq_x_u32, vrshlq_x_u8, vrshrq_x_n_s16, vrshrq_x_n_s32, vrshrq_x_n_s8, vrshrq_x_n_u16, vrshrq_x_n_u32, vrshrq_x_n_u8, vshllbq_x_n_s16, vshllbq_x_n_s8, vshllbq_x_n_u16, vshllbq_x_n_u8, vshlltq_x_n_s16, vshlltq_x_n_s8, vshlltq_x_n_u16, vshlltq_x_n_u8, vshlq_x_n_s16, vshlq_x_n_s32, vshlq_x_n_s8, vshlq_x_n_u16, vshlq_x_n_u32, vshlq_x_n_u8, vshlq_x_s16, vshlq_x_s32, vshlq_x_s8, vshlq_x_u16, vshlq_x_u32, vshlq_x_u8, vshrq_x_n_s16, vshrq_x_n_s32, vshrq_x_n_s8, vshrq_x_n_u16, vshrq_x_n_u32, vshrq_x_n_u8, vsubq_x_f16, vsubq_x_f32, vsubq_x_n_f16, vsubq_x_n_f32, vsubq_x_n_s16, vsubq_x_n_s32, vsubq_x_n_s8, vsubq_x_n_u16, vsubq_x_n_u32, vsubq_x_n_u8, vsubq_x_s16, vsubq_x_s32, vsubq_x_s8, vsubq_x_u16, vsubq_x_u32, vsubq_x_u8. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. (vddupq_x_n_u16): Likewise. (vddupq_x_n_u32): Likewise. (vddupq_x_wb_u8): Likewise. (vddupq_x_wb_u16): Likewise. (vddupq_x_wb_u32): Likewise. (vdwdupq_x_n_u8): Likewise. (vdwdupq_x_n_u16): Likewise. (vdwdupq_x_n_u32): Likewise. (vdwdupq_x_wb_u8): Likewise. (vdwdupq_x_wb_u16): Likewise. (vdwdupq_x_wb_u32): Likewise. (vidupq_x_n_u8): Likewise. (vidupq_x_n_u16): Likewise. (vidupq_x_n_u32): Likewise. (vidupq_x_wb_u8): Likewise. (vidupq_x_wb_u16): Likewise. (vidupq_x_wb_u32): Likewise. (viwdupq_x_n_u8): Likewise. (viwdupq_x_n_u16): Likewise. (viwdupq_x_n_u32): Likewise. (viwdupq_x_wb_u8): Likewise. (viwdupq_x_wb_u16): Likewise. (viwdupq_x_wb_u32): Likewise. (vdupq_x_n_s8): Likewise. (vdupq_x_n_s16): Likewise. (vdupq_x_n_s32): Likewise. (vdupq_x_n_u8): Likewise. (vdupq_x_n_u16): Likewise. (vdupq_x_n_u32): Likewise. (vminq_x_s8): Likewise. (vminq_x_s16): Likewise. (vminq_x_s32): Likewise. (vminq_x_u8): Likewise. (vminq_x_u16): Likewise. (vminq_x_u32): Likewise. (vmaxq_x_s8): Likewise. (vmaxq_x_s16): Likewise. (vmaxq_x_s32): Likewise. (vmaxq_x_u8): Likewise. (vmaxq_x_u16): Likewise. (vmaxq_x_u32): Likewise. (vabdq_x_s8): Likewise. (vabdq_x_s16): Likewise. (vabdq_x_s32): Likewise. (vabdq_x_u8): Likewise. (vabdq_x_u16): Likewise. (vabdq_x_u32): Likewise. (vabsq_x_s8): Likewise. (vabsq_x_s16): Likewise. (vabsq_x_s32): Likewise. (vaddq_x_s8): Likewise. (vaddq_x_s16): Likewise. (vaddq_x_s32): Likewise. (vaddq_x_n_s8): Likewise. (vaddq_x_n_s16): Likewise. (vaddq_x_n_s32): Likewise. (vaddq_x_u8): Likewise. (vaddq_x_u16): Likewise. (vaddq_x_u32): Likewise. (vaddq_x_n_u8): Likewise. (vaddq_x_n_u16): Likewise. (vaddq_x_n_u32): Likewise. (vclsq_x_s8): Likewise. (vclsq_x_s16): Likewise. (vclsq_x_s32): Likewise. (vclzq_x_s8): Likewise. (vclzq_x_s16): Likewise. (vclzq_x_s32): Likewise. (vclzq_x_u8): Likewise. (vclzq_x_u16): Likewise. (vclzq_x_u32): Likewise. (vnegq_x_s8): Likewise. (vnegq_x_s16): Likewise. (vnegq_x_s32): Likewise. (vmulhq_x_s8): Likewise. (vmulhq_x_s16): Likewise. (vmulhq_x_s32): Likewise. (vmulhq_x_u8): Likewise. (vmulhq_x_u16): Likewise. (vmulhq_x_u32): Likewise. (vmullbq_poly_x_p8): Likewise. (vmullbq_poly_x_p16): Likewise. (vmullbq_int_x_s8): Likewise. (vmullbq_int_x_s16): Likewise. (vmullbq_int_x_s32): Likewise. (vmullbq_int_x_u8): Likewise. (vmullbq_int_x_u16): Likewise. (vmullbq_int_x_u32): Likewise. (vmulltq_poly_x_p8): Likewise. (vmulltq_poly_x_p16): Likewise. (vmulltq_int_x_s8): Likewise. (vmulltq_int_x_s16): Likewise. (vmulltq_int_x_s32): Likewise. (vmulltq_int_x_u8): Likewise. (vmulltq_int_x_u16): Likewise. (vmulltq_int_x_u32): Likewise. (vmulq_x_s8): Likewise. (vmulq_x_s16): Likewise. (vmulq_x_s32): Likewise. (vmulq_x_n_s8): Likewise. (vmulq_x_n_s16): Likewise. (vmulq_x_n_s32): Likewise. (vmulq_x_u8): Likewise. (vmulq_x_u16): Likewise. (vmulq_x_u32): Likewise. (vmulq_x_n_u8): Likewise. (vmulq_x_n_u16): Likewise. (vmulq_x_n_u32): Likewise. (vsubq_x_s8): Likewise. (vsubq_x_s16): Likewise. (vsubq_x_s32): Likewise. (vsubq_x_n_s8): Likewise. (vsubq_x_n_s16): Likewise. (vsubq_x_n_s32): Likewise. (vsubq_x_u8): Likewise. (vsubq_x_u16): Likewise. (vsubq_x_u32): Likewise. (vsubq_x_n_u8): Likewise. (vsubq_x_n_u16): Likewise. (vsubq_x_n_u32): Likewise. (vcaddq_rot90_x_s8): Likewise. (vcaddq_rot90_x_s16): Likewise. (vcaddq_rot90_x_s32): Likewise. (vcaddq_rot90_x_u8): Likewise. (vcaddq_rot90_x_u16): Likewise. (vcaddq_rot90_x_u32): Likewise. (vcaddq_rot270_x_s8): Likewise. (vcaddq_rot270_x_s16): Likewise. (vcaddq_rot270_x_s32): Likewise. (vcaddq_rot270_x_u8): Likewise. (vcaddq_rot270_x_u16): Likewise. (vcaddq_rot270_x_u32): Likewise. (vhaddq_x_n_s8): Likewise. (vhaddq_x_n_s16): Likewise. (vhaddq_x_n_s32): Likewise. (vhaddq_x_n_u8): Likewise. (vhaddq_x_n_u16): Likewise. (vhaddq_x_n_u32): Likewise. (vhaddq_x_s8): Likewise. (vhaddq_x_s16): Likewise. (vhaddq_x_s32): Likewise. (vhaddq_x_u8): Likewise. (vhaddq_x_u16): Likewise. (vhaddq_x_u32): Likewise. (vhcaddq_rot90_x_s8): Likewise. (vhcaddq_rot90_x_s16): Likewise. (vhcaddq_rot90_x_s32): Likewise. (vhcaddq_rot270_x_s8): Likewise. (vhcaddq_rot270_x_s16): Likewise. (vhcaddq_rot270_x_s32): Likewise. (vhsubq_x_n_s8): Likewise. (vhsubq_x_n_s16): Likewise. (vhsubq_x_n_s32): Likewise. (vhsubq_x_n_u8): Likewise. (vhsubq_x_n_u16): Likewise. (vhsubq_x_n_u32): Likewise. (vhsubq_x_s8): Likewise. (vhsubq_x_s16): Likewise. (vhsubq_x_s32): Likewise. (vhsubq_x_u8): Likewise. (vhsubq_x_u16): Likewise. (vhsubq_x_u32): Likewise. (vrhaddq_x_s8): Likewise. (vrhaddq_x_s16): Likewise. (vrhaddq_x_s32): Likewise. (vrhaddq_x_u8): Likewise. (vrhaddq_x_u16): Likewise. (vrhaddq_x_u32): Likewise. (vrmulhq_x_s8): Likewise. (vrmulhq_x_s16): Likewise. (vrmulhq_x_s32): Likewise. (vrmulhq_x_u8): Likewise. (vrmulhq_x_u16): Likewise. (vrmulhq_x_u32): Likewise. (vandq_x_s8): Likewise. (vandq_x_s16): Likewise. (vandq_x_s32): Likewise. (vandq_x_u8): Likewise. (vandq_x_u16): Likewise. (vandq_x_u32): Likewise. (vbicq_x_s8): Likewise. (vbicq_x_s16): Likewise. (vbicq_x_s32): Likewise. (vbicq_x_u8): Likewise. (vbicq_x_u16): Likewise. (vbicq_x_u32): Likewise. (vbrsrq_x_n_s8): Likewise. (vbrsrq_x_n_s16): Likewise. (vbrsrq_x_n_s32): Likewise. (vbrsrq_x_n_u8): Likewise. (vbrsrq_x_n_u16): Likewise. (vbrsrq_x_n_u32): Likewise. (veorq_x_s8): Likewise. (veorq_x_s16): Likewise. (veorq_x_s32): Likewise. (veorq_x_u8): Likewise. (veorq_x_u16): Likewise. (veorq_x_u32): Likewise. (vmovlbq_x_s8): Likewise. (vmovlbq_x_s16): Likewise. (vmovlbq_x_u8): Likewise. (vmovlbq_x_u16): Likewise. (vmovltq_x_s8): Likewise. (vmovltq_x_s16): Likewise. (vmovltq_x_u8): Likewise. (vmovltq_x_u16): Likewise. (vmvnq_x_s8): Likewise. (vmvnq_x_s16): Likewise. (vmvnq_x_s32): Likewise. (vmvnq_x_u8): Likewise. (vmvnq_x_u16): Likewise. (vmvnq_x_u32): Likewise. (vmvnq_x_n_s16): Likewise. (vmvnq_x_n_s32): Likewise. (vmvnq_x_n_u16): Likewise. (vmvnq_x_n_u32): Likewise. (vornq_x_s8): Likewise. (vornq_x_s16): Likewise. (vornq_x_s32): Likewise. (vornq_x_u8): Likewise. (vornq_x_u16): Likewise. (vornq_x_u32): Likewise. (vorrq_x_s8): Likewise. (vorrq_x_s16): Likewise. (vorrq_x_s32): Likewise. (vorrq_x_u8): Likewise. (vorrq_x_u16): Likewise. (vorrq_x_u32): Likewise. (vrev16q_x_s8): Likewise. (vrev16q_x_u8): Likewise. (vrev32q_x_s8): Likewise. (vrev32q_x_s16): Likewise. (vrev32q_x_u8): Likewise. (vrev32q_x_u16): Likewise. (vrev64q_x_s8): Likewise. (vrev64q_x_s16): Likewise. (vrev64q_x_s32): Likewise. (vrev64q_x_u8): Likewise. (vrev64q_x_u16): Likewise. (vrev64q_x_u32): Likewise. (vrshlq_x_s8): Likewise. (vrshlq_x_s16): Likewise. (vrshlq_x_s32): Likewise. (vrshlq_x_u8): Likewise. (vrshlq_x_u16): Likewise. (vrshlq_x_u32): Likewise. (vshllbq_x_n_s8): Likewise. (vshllbq_x_n_s16): Likewise. (vshllbq_x_n_u8): Likewise. (vshllbq_x_n_u16): Likewise. (vshlltq_x_n_s8): Likewise. (vshlltq_x_n_s16): Likewise. (vshlltq_x_n_u8): Likewise. (vshlltq_x_n_u16): Likewise. (vshlq_x_s8): Likewise. (vshlq_x_s16): Likewise. (vshlq_x_s32): Likewise. (vshlq_x_u8): Likewise. (vshlq_x_u16): Likewise. (vshlq_x_u32): Likewise. (vshlq_x_n_s8): Likewise. (vshlq_x_n_s16): Likewise. (vshlq_x_n_s32): Likewise. (vshlq_x_n_u8): Likewise. (vshlq_x_n_u16): Likewise. (vshlq_x_n_u32): Likewise. (vrshrq_x_n_s8): Likewise. (vrshrq_x_n_s16): Likewise. (vrshrq_x_n_s32): Likewise. (vrshrq_x_n_u8): Likewise. (vrshrq_x_n_u16): Likewise. (vrshrq_x_n_u32): Likewise. (vshrq_x_n_s8): Likewise. (vshrq_x_n_s16): Likewise. (vshrq_x_n_s32): Likewise. (vshrq_x_n_u8): Likewise. (vshrq_x_n_u16): Likewise. (vshrq_x_n_u32): Likewise. (vdupq_x_n_f16): Likewise. (vdupq_x_n_f32): Likewise. (vminnmq_x_f16): Likewise. (vminnmq_x_f32): Likewise. (vmaxnmq_x_f16): Likewise. (vmaxnmq_x_f32): Likewise. (vabdq_x_f16): Likewise. (vabdq_x_f32): Likewise. (vabsq_x_f16): Likewise. (vabsq_x_f32): Likewise. (vaddq_x_f16): Likewise. (vaddq_x_f32): Likewise. (vaddq_x_n_f16): Likewise. (vaddq_x_n_f32): Likewise. (vnegq_x_f16): Likewise. (vnegq_x_f32): Likewise. (vmulq_x_f16): Likewise. (vmulq_x_f32): Likewise. (vmulq_x_n_f16): Likewise. (vmulq_x_n_f32): Likewise. (vsubq_x_f16): Likewise. (vsubq_x_f32): Likewise. (vsubq_x_n_f16): Likewise. (vsubq_x_n_f32): Likewise. (vcaddq_rot90_x_f16): Likewise. (vcaddq_rot90_x_f32): Likewise. (vcaddq_rot270_x_f16): Likewise. (vcaddq_rot270_x_f32): Likewise. (vcmulq_x_f16): Likewise. (vcmulq_x_f32): Likewise. (vcmulq_rot90_x_f16): Likewise. (vcmulq_rot90_x_f32): Likewise. (vcmulq_rot180_x_f16): Likewise. (vcmulq_rot180_x_f32): Likewise. (vcmulq_rot270_x_f16): Likewise. (vcmulq_rot270_x_f32): Likewise. (vcvtaq_x_s16_f16): Likewise. (vcvtaq_x_s32_f32): Likewise. (vcvtaq_x_u16_f16): Likewise. (vcvtaq_x_u32_f32): Likewise. (vcvtnq_x_s16_f16): Likewise. (vcvtnq_x_s32_f32): Likewise. (vcvtnq_x_u16_f16): Likewise. (vcvtnq_x_u32_f32): Likewise. (vcvtpq_x_s16_f16): Likewise. (vcvtpq_x_s32_f32): Likewise. (vcvtpq_x_u16_f16): Likewise. (vcvtpq_x_u32_f32): Likewise. (vcvtmq_x_s16_f16): Likewise. (vcvtmq_x_s32_f32): Likewise. (vcvtmq_x_u16_f16): Likewise. (vcvtmq_x_u32_f32): Likewise. (vcvtbq_x_f32_f16): Likewise. (vcvttq_x_f32_f16): Likewise. (vcvtq_x_f16_u16): Likewise. (vcvtq_x_f16_s16): Likewise. (vcvtq_x_f32_s32): Likewise. (vcvtq_x_f32_u32): Likewise. (vcvtq_x_n_f16_s16): Likewise. (vcvtq_x_n_f16_u16): Likewise. (vcvtq_x_n_f32_s32): Likewise. (vcvtq_x_n_f32_u32): Likewise. (vcvtq_x_s16_f16): Likewise. (vcvtq_x_s32_f32): Likewise. (vcvtq_x_u16_f16): Likewise. (vcvtq_x_u32_f32): Likewise. (vcvtq_x_n_s16_f16): Likewise. (vcvtq_x_n_s32_f32): Likewise. (vcvtq_x_n_u16_f16): Likewise. (vcvtq_x_n_u32_f32): Likewise. (vrndq_x_f16): Likewise. (vrndq_x_f32): Likewise. (vrndnq_x_f16): Likewise. (vrndnq_x_f32): Likewise. (vrndmq_x_f16): Likewise. (vrndmq_x_f32): Likewise. (vrndpq_x_f16): Likewise. (vrndpq_x_f32): Likewise. (vrndaq_x_f16): Likewise. (vrndaq_x_f32): Likewise. (vrndxq_x_f16): Likewise. (vrndxq_x_f32): Likewise. (vandq_x_f16): Likewise. (vandq_x_f32): Likewise. (vbicq_x_f16): Likewise. (vbicq_x_f32): Likewise. (vbrsrq_x_n_f16): Likewise. (vbrsrq_x_n_f32): Likewise. (veorq_x_f16): Likewise. (veorq_x_f32): Likewise. (vornq_x_f16): Likewise. (vornq_x_f32): Likewise. (vorrq_x_f16): Likewise. (vorrq_x_f32): Likewise. (vrev32q_x_f16): Likewise. (vrev64q_x_f16): Likewise. (vrev64q_x_f32): Likewise. (__arm_vddupq_x_n_u8): Define intrinsic. (__arm_vddupq_x_n_u16): Likewise. (__arm_vddupq_x_n_u32): Likewise. (__arm_vddupq_x_wb_u8): Likewise. (__arm_vddupq_x_wb_u16): Likewise. (__arm_vddupq_x_wb_u32): Likewise. (__arm_vdwdupq_x_n_u8): Likewise. (__arm_vdwdupq_x_n_u16): Likewise. (__arm_vdwdupq_x_n_u32): Likewise. (__arm_vdwdupq_x_wb_u8): Likewise. (__arm_vdwdupq_x_wb_u16): Likewise. (__arm_vdwdupq_x_wb_u32): Likewise. (__arm_vidupq_x_n_u8): Likewise. (__arm_vidupq_x_n_u16): Likewise. (__arm_vidupq_x_n_u32): Likewise. (__arm_vidupq_x_wb_u8): Likewise. (__arm_vidupq_x_wb_u16): Likewise. (__arm_vidupq_x_wb_u32): Likewise. (__arm_viwdupq_x_n_u8): Likewise. (__arm_viwdupq_x_n_u16): Likewise. (__arm_viwdupq_x_n_u32): Likewise. (__arm_viwdupq_x_wb_u8): Likewise. (__arm_viwdupq_x_wb_u16): Likewise. (__arm_viwdupq_x_wb_u32): Likewise. (__arm_vdupq_x_n_s8): Likewise. (__arm_vdupq_x_n_s16): Likewise. (__arm_vdupq_x_n_s32): Likewise. (__arm_vdupq_x_n_u8): Likewise. (__arm_vdupq_x_n_u16): Likewise. (__arm_vdupq_x_n_u32): Likewise. (__arm_vminq_x_s8): Likewise. (__arm_vminq_x_s16): Likewise. (__arm_vminq_x_s32): Likewise. (__arm_vminq_x_u8): Likewise. (__arm_vminq_x_u16): Likewise. (__arm_vminq_x_u32): Likewise. (__arm_vmaxq_x_s8): Likewise. (__arm_vmaxq_x_s16): Likewise. (__arm_vmaxq_x_s32): Likewise. (__arm_vmaxq_x_u8): Likewise. (__arm_vmaxq_x_u16): Likewise. (__arm_vmaxq_x_u32): Likewise. (__arm_vabdq_x_s8): Likewise. (__arm_vabdq_x_s16): Likewise. (__arm_vabdq_x_s32): Likewise. (__arm_vabdq_x_u8): Likewise. (__arm_vabdq_x_u16): Likewise. (__arm_vabdq_x_u32): Likewise. (__arm_vabsq_x_s8): Likewise. (__arm_vabsq_x_s16): Likewise. (__arm_vabsq_x_s32): Likewise. (__arm_vaddq_x_s8): Likewise. (__arm_vaddq_x_s16): Likewise. (__arm_vaddq_x_s32): Likewise. (__arm_vaddq_x_n_s8): Likewise. (__arm_vaddq_x_n_s16): Likewise. (__arm_vaddq_x_n_s32): Likewise. (__arm_vaddq_x_u8): Likewise. (__arm_vaddq_x_u16): Likewise. (__arm_vaddq_x_u32): Likewise. (__arm_vaddq_x_n_u8): Likewise. (__arm_vaddq_x_n_u16): Likewise. (__arm_vaddq_x_n_u32): Likewise. (__arm_vclsq_x_s8): Likewise. (__arm_vclsq_x_s16): Likewise. (__arm_vclsq_x_s32): Likewise. (__arm_vclzq_x_s8): Likewise. (__arm_vclzq_x_s16): Likewise. (__arm_vclzq_x_s32): Likewise. (__arm_vclzq_x_u8): Likewise. (__arm_vclzq_x_u16): Likewise. (__arm_vclzq_x_u32): Likewise. (__arm_vnegq_x_s8): Likewise. (__arm_vnegq_x_s16): Likewise. (__arm_vnegq_x_s32): Likewise. (__arm_vmulhq_x_s8): Likewise. (__arm_vmulhq_x_s16): Likewise. (__arm_vmulhq_x_s32): Likewise. (__arm_vmulhq_x_u8): Likewise. (__arm_vmulhq_x_u16): Likewise. (__arm_vmulhq_x_u32): Likewise. (__arm_vmullbq_poly_x_p8): Likewise. (__arm_vmullbq_poly_x_p16): Likewise. (__arm_vmullbq_int_x_s8): Likewise. (__arm_vmullbq_int_x_s16): Likewise. (__arm_vmullbq_int_x_s32): Likewise. (__arm_vmullbq_int_x_u8): Likewise. (__arm_vmullbq_int_x_u16): Likewise. (__arm_vmullbq_int_x_u32): Likewise. (__arm_vmulltq_poly_x_p8): Likewise. (__arm_vmulltq_poly_x_p16): Likewise. (__arm_vmulltq_int_x_s8): Likewise. (__arm_vmulltq_int_x_s16): Likewise. (__arm_vmulltq_int_x_s32): Likewise. (__arm_vmulltq_int_x_u8): Likewise. (__arm_vmulltq_int_x_u16): Likewise. (__arm_vmulltq_int_x_u32): Likewise. (__arm_vmulq_x_s8): Likewise. (__arm_vmulq_x_s16): Likewise. (__arm_vmulq_x_s32): Likewise. (__arm_vmulq_x_n_s8): Likewise. (__arm_vmulq_x_n_s16): Likewise. (__arm_vmulq_x_n_s32): Likewise. (__arm_vmulq_x_u8): Likewise. (__arm_vmulq_x_u16): Likewise. (__arm_vmulq_x_u32): Likewise. (__arm_vmulq_x_n_u8): Likewise. (__arm_vmulq_x_n_u16): Likewise. (__arm_vmulq_x_n_u32): Likewise. (__arm_vsubq_x_s8): Likewise. (__arm_vsubq_x_s16): Likewise. (__arm_vsubq_x_s32): Likewise. (__arm_vsubq_x_n_s8): Likewise. (__arm_vsubq_x_n_s16): Likewise. (__arm_vsubq_x_n_s32): Likewise. (__arm_vsubq_x_u8): Likewise. (__arm_vsubq_x_u16): Likewise. (__arm_vsubq_x_u32): Likewise. (__arm_vsubq_x_n_u8): Likewise. (__arm_vsubq_x_n_u16): Likewise. (__arm_vsubq_x_n_u32): Likewise. (__arm_vcaddq_rot90_x_s8): Likewise. (__arm_vcaddq_rot90_x_s16): Likewise. (__arm_vcaddq_rot90_x_s32): Likewise. (__arm_vcaddq_rot90_x_u8): Likewise. (__arm_vcaddq_rot90_x_u16): Likewise. (__arm_vcaddq_rot90_x_u32): Likewise. (__arm_vcaddq_rot270_x_s8): Likewise. (__arm_vcaddq_rot270_x_s16): Likewise. (__arm_vcaddq_rot270_x_s32): Likewise. (__arm_vcaddq_rot270_x_u8): Likewise. (__arm_vcaddq_rot270_x_u16): Likewise. (__arm_vcaddq_rot270_x_u32): Likewise. (__arm_vhaddq_x_n_s8): Likewise. (__arm_vhaddq_x_n_s16): Likewise. (__arm_vhaddq_x_n_s32): Likewise. (__arm_vhaddq_x_n_u8): Likewise. (__arm_vhaddq_x_n_u16): Likewise. (__arm_vhaddq_x_n_u32): Likewise. (__arm_vhaddq_x_s8): Likewise. (__arm_vhaddq_x_s16): Likewise. (__arm_vhaddq_x_s32): Likewise. (__arm_vhaddq_x_u8): Likewise. (__arm_vhaddq_x_u16): Likewise. (__arm_vhaddq_x_u32): Likewise. (__arm_vhcaddq_rot90_x_s8): Likewise. (__arm_vhcaddq_rot90_x_s16): Likewise. (__arm_vhcaddq_rot90_x_s32): Likewise. (__arm_vhcaddq_rot270_x_s8): Likewise. (__arm_vhcaddq_rot270_x_s16): Likewise. (__arm_vhcaddq_rot270_x_s32): Likewise. (__arm_vhsubq_x_n_s8): Likewise. (__arm_vhsubq_x_n_s16): Likewise. (__arm_vhsubq_x_n_s32): Likewise. (__arm_vhsubq_x_n_u8): Likewise. (__arm_vhsubq_x_n_u16): Likewise. (__arm_vhsubq_x_n_u32): Likewise. (__arm_vhsubq_x_s8): Likewise. (__arm_vhsubq_x_s16): Likewise. (__arm_vhsubq_x_s32): Likewise. (__arm_vhsubq_x_u8): Likewise. (__arm_vhsubq_x_u16): Likewise. (__arm_vhsubq_x_u32): Likewise. (__arm_vrhaddq_x_s8): Likewise. (__arm_vrhaddq_x_s16): Likewise. (__arm_vrhaddq_x_s32): Likewise. (__arm_vrhaddq_x_u8): Likewise. (__arm_vrhaddq_x_u16): Likewise. (__arm_vrhaddq_x_u32): Likewise. (__arm_vrmulhq_x_s8): Likewise. (__arm_vrmulhq_x_s16): Likewise. (__arm_vrmulhq_x_s32): Likewise. (__arm_vrmulhq_x_u8): Likewise. (__arm_vrmulhq_x_u16): Likewise. (__arm_vrmulhq_x_u32): Likewise. (__arm_vandq_x_s8): Likewise. (__arm_vandq_x_s16): Likewise. (__arm_vandq_x_s32): Likewise. (__arm_vandq_x_u8): Likewise. (__arm_vandq_x_u16): Likewise. (__arm_vandq_x_u32): Likewise. (__arm_vbicq_x_s8): Likewise. (__arm_vbicq_x_s16): Likewise. (__arm_vbicq_x_s32): Likewise. (__arm_vbicq_x_u8): Likewise. (__arm_vbicq_x_u16): Likewise. (__arm_vbicq_x_u32): Likewise. (__arm_vbrsrq_x_n_s8): Likewise. (__arm_vbrsrq_x_n_s16): Likewise. (__arm_vbrsrq_x_n_s32): Likewise. (__arm_vbrsrq_x_n_u8): Likewise. (__arm_vbrsrq_x_n_u16): Likewise. (__arm_vbrsrq_x_n_u32): Likewise. (__arm_veorq_x_s8): Likewise. (__arm_veorq_x_s16): Likewise. (__arm_veorq_x_s32): Likewise. (__arm_veorq_x_u8): Likewise. (__arm_veorq_x_u16): Likewise. (__arm_veorq_x_u32): Likewise. (__arm_vmovlbq_x_s8): Likewise. (__arm_vmovlbq_x_s16): Likewise. (__arm_vmovlbq_x_u8): Likewise. (__arm_vmovlbq_x_u16): Likewise. (__arm_vmovltq_x_s8): Likewise. (__arm_vmovltq_x_s16): Likewise. (__arm_vmovltq_x_u8): Likewise. (__arm_vmovltq_x_u16): Likewise. (__arm_vmvnq_x_s8): Likewise. (__arm_vmvnq_x_s16): Likewise. (__arm_vmvnq_x_s32): Likewise. (__arm_vmvnq_x_u8): Likewise. (__arm_vmvnq_x_u16): Likewise. (__arm_vmvnq_x_u32): Likewise. (__arm_vmvnq_x_n_s16): Likewise. (__arm_vmvnq_x_n_s32): Likewise. (__arm_vmvnq_x_n_u16): Likewise. (__arm_vmvnq_x_n_u32): Likewise. (__arm_vornq_x_s8): Likewise. (__arm_vornq_x_s16): Likewise. (__arm_vornq_x_s32): Likewise. (__arm_vornq_x_u8): Likewise. (__arm_vornq_x_u16): Likewise. (__arm_vornq_x_u32): Likewise. (__arm_vorrq_x_s8): Likewise. (__arm_vorrq_x_s16): Likewise. (__arm_vorrq_x_s32): Likewise. (__arm_vorrq_x_u8): Likewise. (__arm_vorrq_x_u16): Likewise. (__arm_vorrq_x_u32): Likewise. (__arm_vrev16q_x_s8): Likewise. (__arm_vrev16q_x_u8): Likewise. (__arm_vrev32q_x_s8): Likewise. (__arm_vrev32q_x_s16): Likewise. (__arm_vrev32q_x_u8): Likewise. (__arm_vrev32q_x_u16): Likewise. (__arm_vrev64q_x_s8): Likewise. (__arm_vrev64q_x_s16): Likewise. (__arm_vrev64q_x_s32): Likewise. (__arm_vrev64q_x_u8): Likewise. (__arm_vrev64q_x_u16): Likewise. (__arm_vrev64q_x_u32): Likewise. (__arm_vrshlq_x_s8): Likewise. (__arm_vrshlq_x_s16): Likewise. (__arm_vrshlq_x_s32): Likewise. (__arm_vrshlq_x_u8): Likewise. (__arm_vrshlq_x_u16): Likewise. (__arm_vrshlq_x_u32): Likewise. (__arm_vshllbq_x_n_s8): Likewise. (__arm_vshllbq_x_n_s16): Likewise. (__arm_vshllbq_x_n_u8): Likewise. (__arm_vshllbq_x_n_u16): Likewise. (__arm_vshlltq_x_n_s8): Likewise. (__arm_vshlltq_x_n_s16): Likewise. (__arm_vshlltq_x_n_u8): Likewise. (__arm_vshlltq_x_n_u16): Likewise. (__arm_vshlq_x_s8): Likewise. (__arm_vshlq_x_s16): Likewise. (__arm_vshlq_x_s32): Likewise. (__arm_vshlq_x_u8): Likewise. (__arm_vshlq_x_u16): Likewise. (__arm_vshlq_x_u32): Likewise. (__arm_vshlq_x_n_s8): Likewise. (__arm_vshlq_x_n_s16): Likewise. (__arm_vshlq_x_n_s32): Likewise. (__arm_vshlq_x_n_u8): Likewise. (__arm_vshlq_x_n_u16): Likewise. (__arm_vshlq_x_n_u32): Likewise. (__arm_vrshrq_x_n_s8): Likewise. (__arm_vrshrq_x_n_s16): Likewise. (__arm_vrshrq_x_n_s32): Likewise. (__arm_vrshrq_x_n_u8): Likewise. (__arm_vrshrq_x_n_u16): Likewise. (__arm_vrshrq_x_n_u32): Likewise. (__arm_vshrq_x_n_s8): Likewise. (__arm_vshrq_x_n_s16): Likewise. (__arm_vshrq_x_n_s32): Likewise. (__arm_vshrq_x_n_u8): Likewise. (__arm_vshrq_x_n_u16): Likewise. (__arm_vshrq_x_n_u32): Likewise. (__arm_vdupq_x_n_f16): Likewise. (__arm_vdupq_x_n_f32): Likewise. (__arm_vminnmq_x_f16): Likewise. (__arm_vminnmq_x_f32): Likewise. (__arm_vmaxnmq_x_f16): Likewise. (__arm_vmaxnmq_x_f32): Likewise. (__arm_vabdq_x_f16): Likewise. (__arm_vabdq_x_f32): Likewise. (__arm_vabsq_x_f16): Likewise. (__arm_vabsq_x_f32): Likewise. (__arm_vaddq_x_f16): Likewise. (__arm_vaddq_x_f32): Likewise. (__arm_vaddq_x_n_f16): Likewise. (__arm_vaddq_x_n_f32): Likewise. (__arm_vnegq_x_f16): Likewise. (__arm_vnegq_x_f32): Likewise. (__arm_vmulq_x_f16): Likewise. (__arm_vmulq_x_f32): Likewise. (__arm_vmulq_x_n_f16): Likewise. (__arm_vmulq_x_n_f32): Likewise. (__arm_vsubq_x_f16): Likewise. (__arm_vsubq_x_f32): Likewise. (__arm_vsubq_x_n_f16): Likewise. (__arm_vsubq_x_n_f32): Likewise. (__arm_vcaddq_rot90_x_f16): Likewise. (__arm_vcaddq_rot90_x_f32): Likewise. (__arm_vcaddq_rot270_x_f16): Likewise. (__arm_vcaddq_rot270_x_f32): Likewise. (__arm_vcmulq_x_f16): Likewise. (__arm_vcmulq_x_f32): Likewise. (__arm_vcmulq_rot90_x_f16): Likewise. (__arm_vcmulq_rot90_x_f32): Likewise. (__arm_vcmulq_rot180_x_f16): Likewise. (__arm_vcmulq_rot180_x_f32): Likewise. (__arm_vcmulq_rot270_x_f16): Likewise. (__arm_vcmulq_rot270_x_f32): Likewise. (__arm_vcvtaq_x_s16_f16): Likewise. (__arm_vcvtaq_x_s32_f32): Likewise. (__arm_vcvtaq_x_u16_f16): Likewise. (__arm_vcvtaq_x_u32_f32): Likewise. (__arm_vcvtnq_x_s16_f16): Likewise. (__arm_vcvtnq_x_s32_f32): Likewise. (__arm_vcvtnq_x_u16_f16): Likewise. (__arm_vcvtnq_x_u32_f32): Likewise. (__arm_vcvtpq_x_s16_f16): Likewise. (__arm_vcvtpq_x_s32_f32): Likewise. (__arm_vcvtpq_x_u16_f16): Likewise. (__arm_vcvtpq_x_u32_f32): Likewise. (__arm_vcvtmq_x_s16_f16): Likewise. (__arm_vcvtmq_x_s32_f32): Likewise. (__arm_vcvtmq_x_u16_f16): Likewise. (__arm_vcvtmq_x_u32_f32): Likewise. (__arm_vcvtbq_x_f32_f16): Likewise. (__arm_vcvttq_x_f32_f16): Likewise. (__arm_vcvtq_x_f16_u16): Likewise. (__arm_vcvtq_x_f16_s16): Likewise. (__arm_vcvtq_x_f32_s32): Likewise. (__arm_vcvtq_x_f32_u32): Likewise. (__arm_vcvtq_x_n_f16_s16): Likewise. (__arm_vcvtq_x_n_f16_u16): Likewise. (__arm_vcvtq_x_n_f32_s32): Likewise. (__arm_vcvtq_x_n_f32_u32): Likewise. (__arm_vcvtq_x_s16_f16): Likewise. (__arm_vcvtq_x_s32_f32): Likewise. (__arm_vcvtq_x_u16_f16): Likewise. (__arm_vcvtq_x_u32_f32): Likewise. (__arm_vcvtq_x_n_s16_f16): Likewise. (__arm_vcvtq_x_n_s32_f32): Likewise. (__arm_vcvtq_x_n_u16_f16): Likewise. (__arm_vcvtq_x_n_u32_f32): Likewise. (__arm_vrndq_x_f16): Likewise. (__arm_vrndq_x_f32): Likewise. (__arm_vrndnq_x_f16): Likewise. (__arm_vrndnq_x_f32): Likewise. (__arm_vrndmq_x_f16): Likewise. (__arm_vrndmq_x_f32): Likewise. (__arm_vrndpq_x_f16): Likewise. (__arm_vrndpq_x_f32): Likewise. (__arm_vrndaq_x_f16): Likewise. (__arm_vrndaq_x_f32): Likewise. (__arm_vrndxq_x_f16): Likewise. (__arm_vrndxq_x_f32): Likewise. (__arm_vandq_x_f16): Likewise. (__arm_vandq_x_f32): Likewise. (__arm_vbicq_x_f16): Likewise. (__arm_vbicq_x_f32): Likewise. (__arm_vbrsrq_x_n_f16): Likewise. (__arm_vbrsrq_x_n_f32): Likewise. (__arm_veorq_x_f16): Likewise. (__arm_veorq_x_f32): Likewise. (__arm_vornq_x_f16): Likewise. (__arm_vornq_x_f32): Likewise. (__arm_vorrq_x_f16): Likewise. (__arm_vorrq_x_f32): Likewise. (__arm_vrev32q_x_f16): Likewise. (__arm_vrev64q_x_f16): Likewise. (__arm_vrev64q_x_f32): Likewise. (vabdq_x): Define polymorphic variant. (vabsq_x): Likewise. (vaddq_x): Likewise. (vandq_x): Likewise. (vbicq_x): Likewise. (vbrsrq_x): Likewise. (vcaddq_rot270_x): Likewise. (vcaddq_rot90_x): Likewise. (vcmulq_rot180_x): Likewise. (vcmulq_rot270_x): Likewise. (vcmulq_x): Likewise. (vcvtq_x): Likewise. (vcvtq_x_n): Likewise. (vcvtnq_m): Likewise. (veorq_x): Likewise. (vmaxnmq_x): Likewise. (vminnmq_x): Likewise. (vmulq_x): Likewise. (vnegq_x): Likewise. (vornq_x): Likewise. (vorrq_x): Likewise. (vrev32q_x): Likewise. (vrev64q_x): Likewise. (vrndaq_x): Likewise. (vrndmq_x): Likewise. (vrndnq_x): Likewise. (vrndpq_x): Likewise. (vrndq_x): Likewise. (vrndxq_x): Likewise. (vsubq_x): Likewise. (vcmulq_rot90_x): Likewise. (vadciq): Likewise. (vclsq_x): Likewise. (vclzq_x): Likewise. (vhaddq_x): Likewise. (vhcaddq_rot270_x): Likewise. (vhcaddq_rot90_x): Likewise. (vhsubq_x): Likewise. (vmaxq_x): Likewise. (vminq_x): Likewise. (vmovlbq_x): Likewise. (vmovltq_x): Likewise. (vmulhq_x): Likewise. (vmullbq_int_x): Likewise. (vmullbq_poly_x): Likewise. (vmulltq_int_x): Likewise. (vmulltq_poly_x): Likewise. (vmvnq_x): Likewise. (vrev16q_x): Likewise. (vrhaddq_x): Likewise. (vrmulhq_x): Likewise. (vrshlq_x): Likewise. (vrshrq_x): Likewise. (vshllbq_x): Likewise. (vshlltq_x): Likewise. (vshlq_x_n): Likewise. (vshlq_x): Likewise. (vdwdupq_x_u8): Likewise. (vdwdupq_x_u16): Likewise. (vdwdupq_x_u32): Likewise. (viwdupq_x_u8): Likewise. (viwdupq_x_u16): Likewise. (viwdupq_x_u32): Likewise. (vidupq_x_u8): Likewise. (vddupq_x_u8): Likewise. (vidupq_x_u16): Likewise. (vddupq_x_u16): Likewise. (vidupq_x_u32): Likewise. (vddupq_x_u32): Likewise. (vshrq_x): Likewise. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. --- gcc/ChangeLog | 825 +++ gcc/config/arm/arm_mve.h | 6025 ++++++++++++++++---- gcc/testsuite/ChangeLog | 378 ++ .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + 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23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + 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16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + 382 files changed, 14292 insertions(+), 1097 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3623455..6bbdf06 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,828 @@ +2020-03-20 Srinath Parvathaneni + + * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. + (vddupq_x_n_u16): Likewise. + (vddupq_x_n_u32): Likewise. + (vddupq_x_wb_u8): Likewise. + (vddupq_x_wb_u16): Likewise. + (vddupq_x_wb_u32): Likewise. + (vdwdupq_x_n_u8): Likewise. + (vdwdupq_x_n_u16): Likewise. + (vdwdupq_x_n_u32): Likewise. + (vdwdupq_x_wb_u8): Likewise. + (vdwdupq_x_wb_u16): Likewise. + (vdwdupq_x_wb_u32): Likewise. + (vidupq_x_n_u8): Likewise. + (vidupq_x_n_u16): Likewise. + (vidupq_x_n_u32): Likewise. + (vidupq_x_wb_u8): Likewise. + (vidupq_x_wb_u16): Likewise. + (vidupq_x_wb_u32): Likewise. + (viwdupq_x_n_u8): Likewise. + (viwdupq_x_n_u16): Likewise. + (viwdupq_x_n_u32): Likewise. + (viwdupq_x_wb_u8): Likewise. + (viwdupq_x_wb_u16): Likewise. + (viwdupq_x_wb_u32): Likewise. + (vdupq_x_n_s8): Likewise. + (vdupq_x_n_s16): Likewise. + (vdupq_x_n_s32): Likewise. + (vdupq_x_n_u8): Likewise. + (vdupq_x_n_u16): Likewise. + (vdupq_x_n_u32): Likewise. + (vminq_x_s8): Likewise. + (vminq_x_s16): Likewise. + (vminq_x_s32): Likewise. + (vminq_x_u8): Likewise. + (vminq_x_u16): Likewise. + (vminq_x_u32): Likewise. + (vmaxq_x_s8): Likewise. + (vmaxq_x_s16): Likewise. + (vmaxq_x_s32): Likewise. + (vmaxq_x_u8): Likewise. + (vmaxq_x_u16): Likewise. + (vmaxq_x_u32): Likewise. + (vabdq_x_s8): Likewise. + (vabdq_x_s16): Likewise. + (vabdq_x_s32): Likewise. + (vabdq_x_u8): Likewise. + (vabdq_x_u16): Likewise. + (vabdq_x_u32): Likewise. + (vabsq_x_s8): Likewise. + (vabsq_x_s16): Likewise. + (vabsq_x_s32): Likewise. + (vaddq_x_s8): Likewise. + (vaddq_x_s16): Likewise. + (vaddq_x_s32): Likewise. + (vaddq_x_n_s8): Likewise. + (vaddq_x_n_s16): Likewise. + (vaddq_x_n_s32): Likewise. + (vaddq_x_u8): Likewise. + (vaddq_x_u16): Likewise. + (vaddq_x_u32): Likewise. + (vaddq_x_n_u8): Likewise. + (vaddq_x_n_u16): Likewise. + (vaddq_x_n_u32): Likewise. + (vclsq_x_s8): Likewise. + (vclsq_x_s16): Likewise. + (vclsq_x_s32): Likewise. + (vclzq_x_s8): Likewise. + (vclzq_x_s16): Likewise. + (vclzq_x_s32): Likewise. + (vclzq_x_u8): Likewise. + (vclzq_x_u16): Likewise. + (vclzq_x_u32): Likewise. + (vnegq_x_s8): Likewise. + (vnegq_x_s16): Likewise. + (vnegq_x_s32): Likewise. + (vmulhq_x_s8): Likewise. + (vmulhq_x_s16): Likewise. + (vmulhq_x_s32): Likewise. + (vmulhq_x_u8): Likewise. + (vmulhq_x_u16): Likewise. + (vmulhq_x_u32): Likewise. + (vmullbq_poly_x_p8): Likewise. + (vmullbq_poly_x_p16): Likewise. + (vmullbq_int_x_s8): Likewise. + (vmullbq_int_x_s16): Likewise. + (vmullbq_int_x_s32): Likewise. + (vmullbq_int_x_u8): Likewise. + (vmullbq_int_x_u16): Likewise. + (vmullbq_int_x_u32): Likewise. + (vmulltq_poly_x_p8): Likewise. + (vmulltq_poly_x_p16): Likewise. + (vmulltq_int_x_s8): Likewise. + (vmulltq_int_x_s16): Likewise. + (vmulltq_int_x_s32): Likewise. + (vmulltq_int_x_u8): Likewise. + (vmulltq_int_x_u16): Likewise. + (vmulltq_int_x_u32): Likewise. + (vmulq_x_s8): Likewise. + (vmulq_x_s16): Likewise. + (vmulq_x_s32): Likewise. + (vmulq_x_n_s8): Likewise. + (vmulq_x_n_s16): Likewise. + (vmulq_x_n_s32): Likewise. + (vmulq_x_u8): Likewise. + (vmulq_x_u16): Likewise. + (vmulq_x_u32): Likewise. + (vmulq_x_n_u8): Likewise. + (vmulq_x_n_u16): Likewise. + (vmulq_x_n_u32): Likewise. + (vsubq_x_s8): Likewise. + (vsubq_x_s16): Likewise. + (vsubq_x_s32): Likewise. + (vsubq_x_n_s8): Likewise. + (vsubq_x_n_s16): Likewise. + (vsubq_x_n_s32): Likewise. + (vsubq_x_u8): Likewise. + (vsubq_x_u16): Likewise. + (vsubq_x_u32): Likewise. + (vsubq_x_n_u8): Likewise. + (vsubq_x_n_u16): Likewise. + (vsubq_x_n_u32): Likewise. + (vcaddq_rot90_x_s8): Likewise. + (vcaddq_rot90_x_s16): Likewise. + (vcaddq_rot90_x_s32): Likewise. + (vcaddq_rot90_x_u8): Likewise. + (vcaddq_rot90_x_u16): Likewise. + (vcaddq_rot90_x_u32): Likewise. + (vcaddq_rot270_x_s8): Likewise. + (vcaddq_rot270_x_s16): Likewise. + (vcaddq_rot270_x_s32): Likewise. + (vcaddq_rot270_x_u8): Likewise. + (vcaddq_rot270_x_u16): Likewise. + (vcaddq_rot270_x_u32): Likewise. + (vhaddq_x_n_s8): Likewise. + (vhaddq_x_n_s16): Likewise. + (vhaddq_x_n_s32): Likewise. + (vhaddq_x_n_u8): Likewise. + (vhaddq_x_n_u16): Likewise. + (vhaddq_x_n_u32): Likewise. + (vhaddq_x_s8): Likewise. + (vhaddq_x_s16): Likewise. + (vhaddq_x_s32): Likewise. + (vhaddq_x_u8): Likewise. + (vhaddq_x_u16): Likewise. + (vhaddq_x_u32): Likewise. + (vhcaddq_rot90_x_s8): Likewise. + (vhcaddq_rot90_x_s16): Likewise. + (vhcaddq_rot90_x_s32): Likewise. + (vhcaddq_rot270_x_s8): Likewise. + (vhcaddq_rot270_x_s16): Likewise. + (vhcaddq_rot270_x_s32): Likewise. + (vhsubq_x_n_s8): Likewise. + (vhsubq_x_n_s16): Likewise. + (vhsubq_x_n_s32): Likewise. + (vhsubq_x_n_u8): Likewise. + (vhsubq_x_n_u16): Likewise. + (vhsubq_x_n_u32): Likewise. + (vhsubq_x_s8): Likewise. + (vhsubq_x_s16): Likewise. + (vhsubq_x_s32): Likewise. + (vhsubq_x_u8): Likewise. + (vhsubq_x_u16): Likewise. + (vhsubq_x_u32): Likewise. + (vrhaddq_x_s8): Likewise. + (vrhaddq_x_s16): Likewise. + (vrhaddq_x_s32): Likewise. + (vrhaddq_x_u8): Likewise. + (vrhaddq_x_u16): Likewise. + (vrhaddq_x_u32): Likewise. + (vrmulhq_x_s8): Likewise. + (vrmulhq_x_s16): Likewise. + (vrmulhq_x_s32): Likewise. + (vrmulhq_x_u8): Likewise. + (vrmulhq_x_u16): Likewise. + (vrmulhq_x_u32): Likewise. + (vandq_x_s8): Likewise. + (vandq_x_s16): Likewise. + (vandq_x_s32): Likewise. + (vandq_x_u8): Likewise. + (vandq_x_u16): Likewise. + (vandq_x_u32): Likewise. + (vbicq_x_s8): Likewise. + (vbicq_x_s16): Likewise. + (vbicq_x_s32): Likewise. + (vbicq_x_u8): Likewise. + (vbicq_x_u16): Likewise. + (vbicq_x_u32): Likewise. + (vbrsrq_x_n_s8): Likewise. + (vbrsrq_x_n_s16): Likewise. + (vbrsrq_x_n_s32): Likewise. + (vbrsrq_x_n_u8): Likewise. + (vbrsrq_x_n_u16): Likewise. + (vbrsrq_x_n_u32): Likewise. + (veorq_x_s8): Likewise. + (veorq_x_s16): Likewise. + (veorq_x_s32): Likewise. + (veorq_x_u8): Likewise. + (veorq_x_u16): Likewise. + (veorq_x_u32): Likewise. + (vmovlbq_x_s8): Likewise. + (vmovlbq_x_s16): Likewise. + (vmovlbq_x_u8): Likewise. + (vmovlbq_x_u16): Likewise. + (vmovltq_x_s8): Likewise. + (vmovltq_x_s16): Likewise. + (vmovltq_x_u8): Likewise. + (vmovltq_x_u16): Likewise. + (vmvnq_x_s8): Likewise. + (vmvnq_x_s16): Likewise. + (vmvnq_x_s32): Likewise. + (vmvnq_x_u8): Likewise. + (vmvnq_x_u16): Likewise. + (vmvnq_x_u32): Likewise. + (vmvnq_x_n_s16): Likewise. + (vmvnq_x_n_s32): Likewise. + (vmvnq_x_n_u16): Likewise. + (vmvnq_x_n_u32): Likewise. + (vornq_x_s8): Likewise. + (vornq_x_s16): Likewise. + (vornq_x_s32): Likewise. + (vornq_x_u8): Likewise. + (vornq_x_u16): Likewise. + (vornq_x_u32): Likewise. + (vorrq_x_s8): Likewise. + (vorrq_x_s16): Likewise. + (vorrq_x_s32): Likewise. + (vorrq_x_u8): Likewise. + (vorrq_x_u16): Likewise. + (vorrq_x_u32): Likewise. + (vrev16q_x_s8): Likewise. + (vrev16q_x_u8): Likewise. + (vrev32q_x_s8): Likewise. + (vrev32q_x_s16): Likewise. + (vrev32q_x_u8): Likewise. + (vrev32q_x_u16): Likewise. + (vrev64q_x_s8): Likewise. + (vrev64q_x_s16): Likewise. + (vrev64q_x_s32): Likewise. + (vrev64q_x_u8): Likewise. + (vrev64q_x_u16): Likewise. + (vrev64q_x_u32): Likewise. + (vrshlq_x_s8): Likewise. + (vrshlq_x_s16): Likewise. + (vrshlq_x_s32): Likewise. + (vrshlq_x_u8): Likewise. + (vrshlq_x_u16): Likewise. + (vrshlq_x_u32): Likewise. + (vshllbq_x_n_s8): Likewise. + (vshllbq_x_n_s16): Likewise. + (vshllbq_x_n_u8): Likewise. + (vshllbq_x_n_u16): Likewise. + (vshlltq_x_n_s8): Likewise. + (vshlltq_x_n_s16): Likewise. + (vshlltq_x_n_u8): Likewise. + (vshlltq_x_n_u16): Likewise. + (vshlq_x_s8): Likewise. + (vshlq_x_s16): Likewise. + (vshlq_x_s32): Likewise. + (vshlq_x_u8): Likewise. + (vshlq_x_u16): Likewise. + (vshlq_x_u32): Likewise. + (vshlq_x_n_s8): Likewise. + (vshlq_x_n_s16): Likewise. + (vshlq_x_n_s32): Likewise. + (vshlq_x_n_u8): Likewise. + (vshlq_x_n_u16): Likewise. + (vshlq_x_n_u32): Likewise. + (vrshrq_x_n_s8): Likewise. + (vrshrq_x_n_s16): Likewise. + (vrshrq_x_n_s32): Likewise. + (vrshrq_x_n_u8): Likewise. + (vrshrq_x_n_u16): Likewise. + (vrshrq_x_n_u32): Likewise. + (vshrq_x_n_s8): Likewise. + (vshrq_x_n_s16): Likewise. + (vshrq_x_n_s32): Likewise. + (vshrq_x_n_u8): Likewise. + (vshrq_x_n_u16): Likewise. + (vshrq_x_n_u32): Likewise. + (vdupq_x_n_f16): Likewise. + (vdupq_x_n_f32): Likewise. + (vminnmq_x_f16): Likewise. + (vminnmq_x_f32): Likewise. + (vmaxnmq_x_f16): Likewise. + (vmaxnmq_x_f32): Likewise. + (vabdq_x_f16): Likewise. + (vabdq_x_f32): Likewise. + (vabsq_x_f16): Likewise. + (vabsq_x_f32): Likewise. + (vaddq_x_f16): Likewise. + (vaddq_x_f32): Likewise. + (vaddq_x_n_f16): Likewise. + (vaddq_x_n_f32): Likewise. + (vnegq_x_f16): Likewise. + (vnegq_x_f32): Likewise. + (vmulq_x_f16): Likewise. + (vmulq_x_f32): Likewise. + (vmulq_x_n_f16): Likewise. + (vmulq_x_n_f32): Likewise. + (vsubq_x_f16): Likewise. + (vsubq_x_f32): Likewise. + (vsubq_x_n_f16): Likewise. + (vsubq_x_n_f32): Likewise. + (vcaddq_rot90_x_f16): Likewise. + (vcaddq_rot90_x_f32): Likewise. + (vcaddq_rot270_x_f16): Likewise. + (vcaddq_rot270_x_f32): Likewise. + (vcmulq_x_f16): Likewise. + (vcmulq_x_f32): Likewise. + (vcmulq_rot90_x_f16): Likewise. + (vcmulq_rot90_x_f32): Likewise. + (vcmulq_rot180_x_f16): Likewise. + (vcmulq_rot180_x_f32): Likewise. + (vcmulq_rot270_x_f16): Likewise. + (vcmulq_rot270_x_f32): Likewise. + (vcvtaq_x_s16_f16): Likewise. + (vcvtaq_x_s32_f32): Likewise. + (vcvtaq_x_u16_f16): Likewise. + (vcvtaq_x_u32_f32): Likewise. + (vcvtnq_x_s16_f16): Likewise. + (vcvtnq_x_s32_f32): Likewise. + (vcvtnq_x_u16_f16): Likewise. + (vcvtnq_x_u32_f32): Likewise. + (vcvtpq_x_s16_f16): Likewise. + (vcvtpq_x_s32_f32): Likewise. + (vcvtpq_x_u16_f16): Likewise. + (vcvtpq_x_u32_f32): Likewise. + (vcvtmq_x_s16_f16): Likewise. + (vcvtmq_x_s32_f32): Likewise. + (vcvtmq_x_u16_f16): Likewise. + (vcvtmq_x_u32_f32): Likewise. + (vcvtbq_x_f32_f16): Likewise. + (vcvttq_x_f32_f16): Likewise. + (vcvtq_x_f16_u16): Likewise. + (vcvtq_x_f16_s16): Likewise. + (vcvtq_x_f32_s32): Likewise. + (vcvtq_x_f32_u32): Likewise. + (vcvtq_x_n_f16_s16): Likewise. + (vcvtq_x_n_f16_u16): Likewise. + (vcvtq_x_n_f32_s32): Likewise. + (vcvtq_x_n_f32_u32): Likewise. + (vcvtq_x_s16_f16): Likewise. + (vcvtq_x_s32_f32): Likewise. + (vcvtq_x_u16_f16): Likewise. + (vcvtq_x_u32_f32): Likewise. + (vcvtq_x_n_s16_f16): Likewise. + (vcvtq_x_n_s32_f32): Likewise. + (vcvtq_x_n_u16_f16): Likewise. + (vcvtq_x_n_u32_f32): Likewise. + (vrndq_x_f16): Likewise. + (vrndq_x_f32): Likewise. + (vrndnq_x_f16): Likewise. + (vrndnq_x_f32): Likewise. + (vrndmq_x_f16): Likewise. + (vrndmq_x_f32): Likewise. + (vrndpq_x_f16): Likewise. + (vrndpq_x_f32): Likewise. + (vrndaq_x_f16): Likewise. + (vrndaq_x_f32): Likewise. + (vrndxq_x_f16): Likewise. + (vrndxq_x_f32): Likewise. + (vandq_x_f16): Likewise. + (vandq_x_f32): Likewise. + (vbicq_x_f16): Likewise. + (vbicq_x_f32): Likewise. + (vbrsrq_x_n_f16): Likewise. + (vbrsrq_x_n_f32): Likewise. + (veorq_x_f16): Likewise. + (veorq_x_f32): Likewise. + (vornq_x_f16): Likewise. + (vornq_x_f32): Likewise. + (vorrq_x_f16): Likewise. + (vorrq_x_f32): Likewise. + (vrev32q_x_f16): Likewise. + (vrev64q_x_f16): Likewise. + (vrev64q_x_f32): Likewise. + (__arm_vddupq_x_n_u8): Define intrinsic. + (__arm_vddupq_x_n_u16): Likewise. + (__arm_vddupq_x_n_u32): Likewise. + (__arm_vddupq_x_wb_u8): Likewise. + (__arm_vddupq_x_wb_u16): Likewise. + (__arm_vddupq_x_wb_u32): Likewise. + (__arm_vdwdupq_x_n_u8): Likewise. + (__arm_vdwdupq_x_n_u16): Likewise. + (__arm_vdwdupq_x_n_u32): Likewise. + (__arm_vdwdupq_x_wb_u8): Likewise. + (__arm_vdwdupq_x_wb_u16): Likewise. + (__arm_vdwdupq_x_wb_u32): Likewise. + (__arm_vidupq_x_n_u8): Likewise. + (__arm_vidupq_x_n_u16): Likewise. + (__arm_vidupq_x_n_u32): Likewise. + (__arm_vidupq_x_wb_u8): Likewise. + (__arm_vidupq_x_wb_u16): Likewise. + (__arm_vidupq_x_wb_u32): Likewise. + (__arm_viwdupq_x_n_u8): Likewise. + (__arm_viwdupq_x_n_u16): Likewise. + (__arm_viwdupq_x_n_u32): Likewise. + (__arm_viwdupq_x_wb_u8): Likewise. + (__arm_viwdupq_x_wb_u16): Likewise. + (__arm_viwdupq_x_wb_u32): Likewise. + (__arm_vdupq_x_n_s8): Likewise. + (__arm_vdupq_x_n_s16): Likewise. + (__arm_vdupq_x_n_s32): Likewise. + (__arm_vdupq_x_n_u8): Likewise. + (__arm_vdupq_x_n_u16): Likewise. + (__arm_vdupq_x_n_u32): Likewise. + (__arm_vminq_x_s8): Likewise. + (__arm_vminq_x_s16): Likewise. + (__arm_vminq_x_s32): Likewise. + (__arm_vminq_x_u8): Likewise. + (__arm_vminq_x_u16): Likewise. + (__arm_vminq_x_u32): Likewise. + (__arm_vmaxq_x_s8): Likewise. + (__arm_vmaxq_x_s16): Likewise. + (__arm_vmaxq_x_s32): Likewise. + (__arm_vmaxq_x_u8): Likewise. + (__arm_vmaxq_x_u16): Likewise. + (__arm_vmaxq_x_u32): Likewise. + (__arm_vabdq_x_s8): Likewise. + (__arm_vabdq_x_s16): Likewise. + (__arm_vabdq_x_s32): Likewise. + (__arm_vabdq_x_u8): Likewise. + (__arm_vabdq_x_u16): Likewise. + (__arm_vabdq_x_u32): Likewise. + (__arm_vabsq_x_s8): Likewise. + (__arm_vabsq_x_s16): Likewise. + (__arm_vabsq_x_s32): Likewise. + (__arm_vaddq_x_s8): Likewise. + (__arm_vaddq_x_s16): Likewise. + (__arm_vaddq_x_s32): Likewise. + (__arm_vaddq_x_n_s8): Likewise. + (__arm_vaddq_x_n_s16): Likewise. + (__arm_vaddq_x_n_s32): Likewise. + (__arm_vaddq_x_u8): Likewise. + (__arm_vaddq_x_u16): Likewise. + (__arm_vaddq_x_u32): Likewise. + (__arm_vaddq_x_n_u8): Likewise. + (__arm_vaddq_x_n_u16): Likewise. + (__arm_vaddq_x_n_u32): Likewise. + (__arm_vclsq_x_s8): Likewise. + (__arm_vclsq_x_s16): Likewise. + (__arm_vclsq_x_s32): Likewise. + (__arm_vclzq_x_s8): Likewise. + (__arm_vclzq_x_s16): Likewise. + (__arm_vclzq_x_s32): Likewise. + (__arm_vclzq_x_u8): Likewise. + (__arm_vclzq_x_u16): Likewise. + (__arm_vclzq_x_u32): Likewise. + (__arm_vnegq_x_s8): Likewise. + (__arm_vnegq_x_s16): Likewise. + (__arm_vnegq_x_s32): Likewise. + (__arm_vmulhq_x_s8): Likewise. + (__arm_vmulhq_x_s16): Likewise. + (__arm_vmulhq_x_s32): Likewise. + (__arm_vmulhq_x_u8): Likewise. + (__arm_vmulhq_x_u16): Likewise. + (__arm_vmulhq_x_u32): Likewise. + (__arm_vmullbq_poly_x_p8): Likewise. + (__arm_vmullbq_poly_x_p16): Likewise. + (__arm_vmullbq_int_x_s8): Likewise. + (__arm_vmullbq_int_x_s16): Likewise. + (__arm_vmullbq_int_x_s32): Likewise. + (__arm_vmullbq_int_x_u8): Likewise. + (__arm_vmullbq_int_x_u16): Likewise. + (__arm_vmullbq_int_x_u32): Likewise. + (__arm_vmulltq_poly_x_p8): Likewise. + (__arm_vmulltq_poly_x_p16): Likewise. + (__arm_vmulltq_int_x_s8): Likewise. + (__arm_vmulltq_int_x_s16): Likewise. + (__arm_vmulltq_int_x_s32): Likewise. + (__arm_vmulltq_int_x_u8): Likewise. + (__arm_vmulltq_int_x_u16): Likewise. + (__arm_vmulltq_int_x_u32): Likewise. + (__arm_vmulq_x_s8): Likewise. + (__arm_vmulq_x_s16): Likewise. + (__arm_vmulq_x_s32): Likewise. + (__arm_vmulq_x_n_s8): Likewise. + (__arm_vmulq_x_n_s16): Likewise. + (__arm_vmulq_x_n_s32): Likewise. + (__arm_vmulq_x_u8): Likewise. + (__arm_vmulq_x_u16): Likewise. + (__arm_vmulq_x_u32): Likewise. + (__arm_vmulq_x_n_u8): Likewise. + (__arm_vmulq_x_n_u16): Likewise. + (__arm_vmulq_x_n_u32): Likewise. + (__arm_vsubq_x_s8): Likewise. + (__arm_vsubq_x_s16): Likewise. + (__arm_vsubq_x_s32): Likewise. + (__arm_vsubq_x_n_s8): Likewise. + (__arm_vsubq_x_n_s16): Likewise. + (__arm_vsubq_x_n_s32): Likewise. + (__arm_vsubq_x_u8): Likewise. + (__arm_vsubq_x_u16): Likewise. + (__arm_vsubq_x_u32): Likewise. + (__arm_vsubq_x_n_u8): Likewise. + (__arm_vsubq_x_n_u16): Likewise. + (__arm_vsubq_x_n_u32): Likewise. + (__arm_vcaddq_rot90_x_s8): Likewise. + (__arm_vcaddq_rot90_x_s16): Likewise. + (__arm_vcaddq_rot90_x_s32): Likewise. + (__arm_vcaddq_rot90_x_u8): Likewise. + (__arm_vcaddq_rot90_x_u16): Likewise. + (__arm_vcaddq_rot90_x_u32): Likewise. + (__arm_vcaddq_rot270_x_s8): Likewise. + (__arm_vcaddq_rot270_x_s16): Likewise. + (__arm_vcaddq_rot270_x_s32): Likewise. + (__arm_vcaddq_rot270_x_u8): Likewise. + (__arm_vcaddq_rot270_x_u16): Likewise. + (__arm_vcaddq_rot270_x_u32): Likewise. + (__arm_vhaddq_x_n_s8): Likewise. + (__arm_vhaddq_x_n_s16): Likewise. + (__arm_vhaddq_x_n_s32): Likewise. + (__arm_vhaddq_x_n_u8): Likewise. + (__arm_vhaddq_x_n_u16): Likewise. + (__arm_vhaddq_x_n_u32): Likewise. + (__arm_vhaddq_x_s8): Likewise. + (__arm_vhaddq_x_s16): Likewise. + (__arm_vhaddq_x_s32): Likewise. + (__arm_vhaddq_x_u8): Likewise. + (__arm_vhaddq_x_u16): Likewise. + (__arm_vhaddq_x_u32): Likewise. + (__arm_vhcaddq_rot90_x_s8): Likewise. + (__arm_vhcaddq_rot90_x_s16): Likewise. + (__arm_vhcaddq_rot90_x_s32): Likewise. + (__arm_vhcaddq_rot270_x_s8): Likewise. + (__arm_vhcaddq_rot270_x_s16): Likewise. + (__arm_vhcaddq_rot270_x_s32): Likewise. + (__arm_vhsubq_x_n_s8): Likewise. + (__arm_vhsubq_x_n_s16): Likewise. + (__arm_vhsubq_x_n_s32): Likewise. + (__arm_vhsubq_x_n_u8): Likewise. + (__arm_vhsubq_x_n_u16): Likewise. + (__arm_vhsubq_x_n_u32): Likewise. + (__arm_vhsubq_x_s8): Likewise. + (__arm_vhsubq_x_s16): Likewise. + (__arm_vhsubq_x_s32): Likewise. + (__arm_vhsubq_x_u8): Likewise. + (__arm_vhsubq_x_u16): Likewise. + (__arm_vhsubq_x_u32): Likewise. + (__arm_vrhaddq_x_s8): Likewise. + (__arm_vrhaddq_x_s16): Likewise. + (__arm_vrhaddq_x_s32): Likewise. + (__arm_vrhaddq_x_u8): Likewise. + (__arm_vrhaddq_x_u16): Likewise. + (__arm_vrhaddq_x_u32): Likewise. + (__arm_vrmulhq_x_s8): Likewise. + (__arm_vrmulhq_x_s16): Likewise. + (__arm_vrmulhq_x_s32): Likewise. + (__arm_vrmulhq_x_u8): Likewise. + (__arm_vrmulhq_x_u16): Likewise. + (__arm_vrmulhq_x_u32): Likewise. + (__arm_vandq_x_s8): Likewise. + (__arm_vandq_x_s16): Likewise. + (__arm_vandq_x_s32): Likewise. + (__arm_vandq_x_u8): Likewise. + (__arm_vandq_x_u16): Likewise. + (__arm_vandq_x_u32): Likewise. + (__arm_vbicq_x_s8): Likewise. + (__arm_vbicq_x_s16): Likewise. + (__arm_vbicq_x_s32): Likewise. + (__arm_vbicq_x_u8): Likewise. + (__arm_vbicq_x_u16): Likewise. + (__arm_vbicq_x_u32): Likewise. + (__arm_vbrsrq_x_n_s8): Likewise. + (__arm_vbrsrq_x_n_s16): Likewise. + (__arm_vbrsrq_x_n_s32): Likewise. + (__arm_vbrsrq_x_n_u8): Likewise. + (__arm_vbrsrq_x_n_u16): Likewise. + (__arm_vbrsrq_x_n_u32): Likewise. + (__arm_veorq_x_s8): Likewise. + (__arm_veorq_x_s16): Likewise. + (__arm_veorq_x_s32): Likewise. + (__arm_veorq_x_u8): Likewise. + (__arm_veorq_x_u16): Likewise. + (__arm_veorq_x_u32): Likewise. + (__arm_vmovlbq_x_s8): Likewise. + (__arm_vmovlbq_x_s16): Likewise. + (__arm_vmovlbq_x_u8): Likewise. + (__arm_vmovlbq_x_u16): Likewise. + (__arm_vmovltq_x_s8): Likewise. + (__arm_vmovltq_x_s16): Likewise. + (__arm_vmovltq_x_u8): Likewise. + (__arm_vmovltq_x_u16): Likewise. + (__arm_vmvnq_x_s8): Likewise. + (__arm_vmvnq_x_s16): Likewise. + (__arm_vmvnq_x_s32): Likewise. + (__arm_vmvnq_x_u8): Likewise. + (__arm_vmvnq_x_u16): Likewise. + (__arm_vmvnq_x_u32): Likewise. + (__arm_vmvnq_x_n_s16): Likewise. + (__arm_vmvnq_x_n_s32): Likewise. + (__arm_vmvnq_x_n_u16): Likewise. + (__arm_vmvnq_x_n_u32): Likewise. + (__arm_vornq_x_s8): Likewise. + (__arm_vornq_x_s16): Likewise. + (__arm_vornq_x_s32): Likewise. + (__arm_vornq_x_u8): Likewise. + (__arm_vornq_x_u16): Likewise. + (__arm_vornq_x_u32): Likewise. + (__arm_vorrq_x_s8): Likewise. + (__arm_vorrq_x_s16): Likewise. + (__arm_vorrq_x_s32): Likewise. + (__arm_vorrq_x_u8): Likewise. + (__arm_vorrq_x_u16): Likewise. + (__arm_vorrq_x_u32): Likewise. + (__arm_vrev16q_x_s8): Likewise. + (__arm_vrev16q_x_u8): Likewise. + (__arm_vrev32q_x_s8): Likewise. + (__arm_vrev32q_x_s16): Likewise. + (__arm_vrev32q_x_u8): Likewise. + (__arm_vrev32q_x_u16): Likewise. + (__arm_vrev64q_x_s8): Likewise. + (__arm_vrev64q_x_s16): Likewise. + (__arm_vrev64q_x_s32): Likewise. + (__arm_vrev64q_x_u8): Likewise. + (__arm_vrev64q_x_u16): Likewise. + (__arm_vrev64q_x_u32): Likewise. + (__arm_vrshlq_x_s8): Likewise. + (__arm_vrshlq_x_s16): Likewise. + (__arm_vrshlq_x_s32): Likewise. + (__arm_vrshlq_x_u8): Likewise. + (__arm_vrshlq_x_u16): Likewise. + (__arm_vrshlq_x_u32): Likewise. + (__arm_vshllbq_x_n_s8): Likewise. + (__arm_vshllbq_x_n_s16): Likewise. + (__arm_vshllbq_x_n_u8): Likewise. + (__arm_vshllbq_x_n_u16): Likewise. + (__arm_vshlltq_x_n_s8): Likewise. + (__arm_vshlltq_x_n_s16): Likewise. + (__arm_vshlltq_x_n_u8): Likewise. + (__arm_vshlltq_x_n_u16): Likewise. + (__arm_vshlq_x_s8): Likewise. + (__arm_vshlq_x_s16): Likewise. + (__arm_vshlq_x_s32): Likewise. + (__arm_vshlq_x_u8): Likewise. + (__arm_vshlq_x_u16): Likewise. + (__arm_vshlq_x_u32): Likewise. + (__arm_vshlq_x_n_s8): Likewise. + (__arm_vshlq_x_n_s16): Likewise. + (__arm_vshlq_x_n_s32): Likewise. + (__arm_vshlq_x_n_u8): Likewise. + (__arm_vshlq_x_n_u16): Likewise. + (__arm_vshlq_x_n_u32): Likewise. + (__arm_vrshrq_x_n_s8): Likewise. + (__arm_vrshrq_x_n_s16): Likewise. + (__arm_vrshrq_x_n_s32): Likewise. + (__arm_vrshrq_x_n_u8): Likewise. + (__arm_vrshrq_x_n_u16): Likewise. + (__arm_vrshrq_x_n_u32): Likewise. + (__arm_vshrq_x_n_s8): Likewise. + (__arm_vshrq_x_n_s16): Likewise. + (__arm_vshrq_x_n_s32): Likewise. + (__arm_vshrq_x_n_u8): Likewise. + (__arm_vshrq_x_n_u16): Likewise. + (__arm_vshrq_x_n_u32): Likewise. + (__arm_vdupq_x_n_f16): Likewise. + (__arm_vdupq_x_n_f32): Likewise. + (__arm_vminnmq_x_f16): Likewise. + (__arm_vminnmq_x_f32): Likewise. + (__arm_vmaxnmq_x_f16): Likewise. + (__arm_vmaxnmq_x_f32): Likewise. + (__arm_vabdq_x_f16): Likewise. + (__arm_vabdq_x_f32): Likewise. + (__arm_vabsq_x_f16): Likewise. + (__arm_vabsq_x_f32): Likewise. + (__arm_vaddq_x_f16): Likewise. + (__arm_vaddq_x_f32): Likewise. + (__arm_vaddq_x_n_f16): Likewise. + (__arm_vaddq_x_n_f32): Likewise. + (__arm_vnegq_x_f16): Likewise. + (__arm_vnegq_x_f32): Likewise. + (__arm_vmulq_x_f16): Likewise. + (__arm_vmulq_x_f32): Likewise. + (__arm_vmulq_x_n_f16): Likewise. + (__arm_vmulq_x_n_f32): Likewise. + (__arm_vsubq_x_f16): Likewise. + (__arm_vsubq_x_f32): Likewise. + (__arm_vsubq_x_n_f16): Likewise. + (__arm_vsubq_x_n_f32): Likewise. + (__arm_vcaddq_rot90_x_f16): Likewise. + (__arm_vcaddq_rot90_x_f32): Likewise. + (__arm_vcaddq_rot270_x_f16): Likewise. + (__arm_vcaddq_rot270_x_f32): Likewise. + (__arm_vcmulq_x_f16): Likewise. + (__arm_vcmulq_x_f32): Likewise. + (__arm_vcmulq_rot90_x_f16): Likewise. + (__arm_vcmulq_rot90_x_f32): Likewise. + (__arm_vcmulq_rot180_x_f16): Likewise. + (__arm_vcmulq_rot180_x_f32): Likewise. + (__arm_vcmulq_rot270_x_f16): Likewise. + (__arm_vcmulq_rot270_x_f32): Likewise. + (__arm_vcvtaq_x_s16_f16): Likewise. + (__arm_vcvtaq_x_s32_f32): Likewise. + (__arm_vcvtaq_x_u16_f16): Likewise. + (__arm_vcvtaq_x_u32_f32): Likewise. + (__arm_vcvtnq_x_s16_f16): Likewise. + (__arm_vcvtnq_x_s32_f32): Likewise. + (__arm_vcvtnq_x_u16_f16): Likewise. + (__arm_vcvtnq_x_u32_f32): Likewise. + (__arm_vcvtpq_x_s16_f16): Likewise. + (__arm_vcvtpq_x_s32_f32): Likewise. + (__arm_vcvtpq_x_u16_f16): Likewise. + (__arm_vcvtpq_x_u32_f32): Likewise. + (__arm_vcvtmq_x_s16_f16): Likewise. + (__arm_vcvtmq_x_s32_f32): Likewise. + (__arm_vcvtmq_x_u16_f16): Likewise. + (__arm_vcvtmq_x_u32_f32): Likewise. + (__arm_vcvtbq_x_f32_f16): Likewise. + (__arm_vcvttq_x_f32_f16): Likewise. + (__arm_vcvtq_x_f16_u16): Likewise. + (__arm_vcvtq_x_f16_s16): Likewise. + (__arm_vcvtq_x_f32_s32): Likewise. + (__arm_vcvtq_x_f32_u32): Likewise. + (__arm_vcvtq_x_n_f16_s16): Likewise. + (__arm_vcvtq_x_n_f16_u16): Likewise. + (__arm_vcvtq_x_n_f32_s32): Likewise. + (__arm_vcvtq_x_n_f32_u32): Likewise. + (__arm_vcvtq_x_s16_f16): Likewise. + (__arm_vcvtq_x_s32_f32): Likewise. + (__arm_vcvtq_x_u16_f16): Likewise. + (__arm_vcvtq_x_u32_f32): Likewise. + (__arm_vcvtq_x_n_s16_f16): Likewise. + (__arm_vcvtq_x_n_s32_f32): Likewise. + (__arm_vcvtq_x_n_u16_f16): Likewise. + (__arm_vcvtq_x_n_u32_f32): Likewise. + (__arm_vrndq_x_f16): Likewise. + (__arm_vrndq_x_f32): Likewise. + (__arm_vrndnq_x_f16): Likewise. + (__arm_vrndnq_x_f32): Likewise. + (__arm_vrndmq_x_f16): Likewise. + (__arm_vrndmq_x_f32): Likewise. + (__arm_vrndpq_x_f16): Likewise. + (__arm_vrndpq_x_f32): Likewise. + (__arm_vrndaq_x_f16): Likewise. + (__arm_vrndaq_x_f32): Likewise. + (__arm_vrndxq_x_f16): Likewise. + (__arm_vrndxq_x_f32): Likewise. + (__arm_vandq_x_f16): Likewise. + (__arm_vandq_x_f32): Likewise. + (__arm_vbicq_x_f16): Likewise. + (__arm_vbicq_x_f32): Likewise. + (__arm_vbrsrq_x_n_f16): Likewise. + (__arm_vbrsrq_x_n_f32): Likewise. + (__arm_veorq_x_f16): Likewise. + (__arm_veorq_x_f32): Likewise. + (__arm_vornq_x_f16): Likewise. + (__arm_vornq_x_f32): Likewise. + (__arm_vorrq_x_f16): Likewise. + (__arm_vorrq_x_f32): Likewise. + (__arm_vrev32q_x_f16): Likewise. + (__arm_vrev64q_x_f16): Likewise. + (__arm_vrev64q_x_f32): Likewise. + (vabdq_x): Define polymorphic variant. + (vabsq_x): Likewise. + (vaddq_x): Likewise. + (vandq_x): Likewise. + (vbicq_x): Likewise. + (vbrsrq_x): Likewise. + (vcaddq_rot270_x): Likewise. + (vcaddq_rot90_x): Likewise. + (vcmulq_rot180_x): Likewise. + (vcmulq_rot270_x): Likewise. + (vcmulq_x): Likewise. + (vcvtq_x): Likewise. + (vcvtq_x_n): Likewise. + (vcvtnq_m): Likewise. + (veorq_x): Likewise. + (vmaxnmq_x): Likewise. + (vminnmq_x): Likewise. + (vmulq_x): Likewise. + (vnegq_x): Likewise. + (vornq_x): Likewise. + (vorrq_x): Likewise. + (vrev32q_x): Likewise. + (vrev64q_x): Likewise. + (vrndaq_x): Likewise. + (vrndmq_x): Likewise. + (vrndnq_x): Likewise. + (vrndpq_x): Likewise. + (vrndq_x): Likewise. + (vrndxq_x): Likewise. + (vsubq_x): Likewise. + (vcmulq_rot90_x): Likewise. + (vadciq): Likewise. + (vclsq_x): Likewise. + (vclzq_x): Likewise. + (vhaddq_x): Likewise. + (vhcaddq_rot270_x): Likewise. + (vhcaddq_rot90_x): Likewise. + (vhsubq_x): Likewise. + (vmaxq_x): Likewise. + (vminq_x): Likewise. + (vmovlbq_x): Likewise. + (vmovltq_x): Likewise. + (vmulhq_x): Likewise. + (vmullbq_int_x): Likewise. + (vmullbq_poly_x): Likewise. + (vmulltq_int_x): Likewise. + (vmulltq_poly_x): Likewise. + (vmvnq_x): Likewise. + (vrev16q_x): Likewise. + (vrhaddq_x): Likewise. + (vrmulhq_x): Likewise. + (vrshlq_x): Likewise. + (vrshrq_x): Likewise. + (vshllbq_x): Likewise. + (vshlltq_x): Likewise. + (vshlq_x_n): Likewise. + (vshlq_x): Likewise. + (vdwdupq_x_u8): Likewise. + (vdwdupq_x_u16): Likewise. + (vdwdupq_x_u32): Likewise. + (viwdupq_x_u8): Likewise. + (viwdupq_x_u16): Likewise. + (viwdupq_x_u32): Likewise. + (vidupq_x_u8): Likewise. + (vddupq_x_u8): Likewise. + (vidupq_x_u16): Likewise. + (vddupq_x_u16): Likewise. + (vidupq_x_u32): Likewise. + (vddupq_x_u32): Likewise. + (vshrq_x): Likewise. + 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 969908b..77df7c7 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2074,6 +2074,382 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrwq_scatter_base_wb_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_s32(__addr, __offset, __value) #define vstrwq_scatter_base_wb_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_u32(__addr, __offset, __value) #define vstrwq_scatter_base_wb_f32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_f32(__addr, __offset, __value) +#define vddupq_x_n_u8(__a, __imm, __p) __arm_vddupq_x_n_u8(__a, __imm, __p) +#define vddupq_x_n_u16(__a, __imm, __p) __arm_vddupq_x_n_u16(__a, __imm, __p) +#define vddupq_x_n_u32(__a, __imm, __p) __arm_vddupq_x_n_u32(__a, __imm, __p) +#define vddupq_x_wb_u8(__a, __imm, __p) __arm_vddupq_x_wb_u8(__a, __imm, __p) +#define vddupq_x_wb_u16(__a, __imm, __p) __arm_vddupq_x_wb_u16(__a, __imm, __p) +#define vddupq_x_wb_u32(__a, __imm, __p) __arm_vddupq_x_wb_u32(__a, __imm, __p) +#define vdwdupq_x_n_u8(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u8(__a, __b, __imm, __p) +#define vdwdupq_x_n_u16(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u16(__a, __b, __imm, __p) +#define vdwdupq_x_n_u32(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u32(__a, __b, __imm, __p) +#define vdwdupq_x_wb_u8(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u8(__a, __b, __imm, __p) +#define vdwdupq_x_wb_u16(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u16(__a, __b, __imm, __p) +#define vdwdupq_x_wb_u32(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u32(__a, __b, __imm, __p) +#define vidupq_x_n_u8(__a, __imm, __p) __arm_vidupq_x_n_u8(__a, __imm, __p) +#define vidupq_x_n_u16(__a, __imm, __p) __arm_vidupq_x_n_u16(__a, __imm, __p) +#define vidupq_x_n_u32(__a, __imm, __p) __arm_vidupq_x_n_u32(__a, __imm, __p) +#define vidupq_x_wb_u8(__a, __imm, __p) __arm_vidupq_x_wb_u8(__a, __imm, __p) +#define vidupq_x_wb_u16(__a, __imm, __p) __arm_vidupq_x_wb_u16(__a, __imm, __p) +#define vidupq_x_wb_u32(__a, __imm, __p) __arm_vidupq_x_wb_u32(__a, __imm, __p) +#define viwdupq_x_n_u8(__a, __b, __imm, __p) __arm_viwdupq_x_n_u8(__a, __b, __imm, __p) +#define viwdupq_x_n_u16(__a, __b, __imm, __p) __arm_viwdupq_x_n_u16(__a, __b, __imm, __p) +#define viwdupq_x_n_u32(__a, __b, __imm, __p) __arm_viwdupq_x_n_u32(__a, __b, __imm, __p) +#define viwdupq_x_wb_u8(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u8(__a, __b, __imm, __p) +#define viwdupq_x_wb_u16(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u16(__a, __b, __imm, __p) +#define viwdupq_x_wb_u32(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u32(__a, __b, __imm, __p) +#define vdupq_x_n_s8(__a, __p) __arm_vdupq_x_n_s8(__a, __p) +#define vdupq_x_n_s16(__a, __p) __arm_vdupq_x_n_s16(__a, __p) +#define vdupq_x_n_s32(__a, __p) __arm_vdupq_x_n_s32(__a, __p) +#define vdupq_x_n_u8(__a, __p) __arm_vdupq_x_n_u8(__a, __p) +#define vdupq_x_n_u16(__a, __p) __arm_vdupq_x_n_u16(__a, __p) +#define vdupq_x_n_u32(__a, __p) __arm_vdupq_x_n_u32(__a, __p) +#define vminq_x_s8(__a, __b, __p) __arm_vminq_x_s8(__a, __b, __p) +#define vminq_x_s16(__a, __b, __p) __arm_vminq_x_s16(__a, __b, __p) +#define vminq_x_s32(__a, __b, __p) __arm_vminq_x_s32(__a, __b, __p) +#define vminq_x_u8(__a, __b, __p) __arm_vminq_x_u8(__a, __b, __p) +#define vminq_x_u16(__a, __b, __p) __arm_vminq_x_u16(__a, __b, __p) +#define vminq_x_u32(__a, __b, __p) __arm_vminq_x_u32(__a, __b, __p) +#define vmaxq_x_s8(__a, __b, __p) __arm_vmaxq_x_s8(__a, __b, __p) +#define vmaxq_x_s16(__a, __b, __p) __arm_vmaxq_x_s16(__a, __b, __p) +#define vmaxq_x_s32(__a, __b, __p) __arm_vmaxq_x_s32(__a, __b, __p) +#define vmaxq_x_u8(__a, __b, __p) __arm_vmaxq_x_u8(__a, __b, __p) +#define vmaxq_x_u16(__a, __b, __p) __arm_vmaxq_x_u16(__a, __b, __p) +#define vmaxq_x_u32(__a, __b, __p) __arm_vmaxq_x_u32(__a, __b, __p) +#define vabdq_x_s8(__a, __b, __p) __arm_vabdq_x_s8(__a, __b, __p) +#define vabdq_x_s16(__a, __b, __p) __arm_vabdq_x_s16(__a, __b, __p) +#define vabdq_x_s32(__a, __b, __p) __arm_vabdq_x_s32(__a, __b, __p) +#define vabdq_x_u8(__a, __b, __p) __arm_vabdq_x_u8(__a, __b, __p) +#define vabdq_x_u16(__a, __b, __p) __arm_vabdq_x_u16(__a, __b, __p) +#define vabdq_x_u32(__a, __b, __p) __arm_vabdq_x_u32(__a, __b, __p) +#define vabsq_x_s8(__a, __p) __arm_vabsq_x_s8(__a, __p) +#define vabsq_x_s16(__a, __p) __arm_vabsq_x_s16(__a, __p) +#define vabsq_x_s32(__a, __p) __arm_vabsq_x_s32(__a, __p) +#define vaddq_x_s8(__a, __b, __p) __arm_vaddq_x_s8(__a, __b, __p) +#define vaddq_x_s16(__a, __b, __p) __arm_vaddq_x_s16(__a, __b, __p) +#define vaddq_x_s32(__a, __b, __p) __arm_vaddq_x_s32(__a, __b, __p) +#define vaddq_x_n_s8(__a, __b, __p) __arm_vaddq_x_n_s8(__a, __b, __p) +#define vaddq_x_n_s16(__a, __b, __p) __arm_vaddq_x_n_s16(__a, __b, __p) +#define vaddq_x_n_s32(__a, __b, __p) __arm_vaddq_x_n_s32(__a, __b, __p) +#define vaddq_x_u8(__a, __b, __p) __arm_vaddq_x_u8(__a, __b, __p) +#define vaddq_x_u16(__a, __b, __p) __arm_vaddq_x_u16(__a, __b, __p) +#define vaddq_x_u32(__a, __b, __p) __arm_vaddq_x_u32(__a, __b, __p) +#define vaddq_x_n_u8(__a, __b, __p) __arm_vaddq_x_n_u8(__a, __b, __p) +#define vaddq_x_n_u16(__a, __b, __p) __arm_vaddq_x_n_u16(__a, __b, __p) +#define vaddq_x_n_u32(__a, __b, __p) __arm_vaddq_x_n_u32(__a, __b, __p) +#define vclsq_x_s8(__a, __p) __arm_vclsq_x_s8(__a, __p) +#define vclsq_x_s16(__a, __p) __arm_vclsq_x_s16(__a, __p) +#define vclsq_x_s32(__a, __p) __arm_vclsq_x_s32(__a, __p) +#define vclzq_x_s8(__a, __p) __arm_vclzq_x_s8(__a, __p) +#define vclzq_x_s16(__a, __p) __arm_vclzq_x_s16(__a, __p) +#define vclzq_x_s32(__a, __p) __arm_vclzq_x_s32(__a, __p) +#define vclzq_x_u8(__a, __p) __arm_vclzq_x_u8(__a, __p) +#define vclzq_x_u16(__a, __p) __arm_vclzq_x_u16(__a, __p) +#define vclzq_x_u32(__a, __p) __arm_vclzq_x_u32(__a, __p) +#define vnegq_x_s8(__a, __p) __arm_vnegq_x_s8(__a, __p) +#define vnegq_x_s16(__a, __p) __arm_vnegq_x_s16(__a, __p) +#define vnegq_x_s32(__a, __p) __arm_vnegq_x_s32(__a, __p) +#define vmulhq_x_s8(__a, __b, __p) __arm_vmulhq_x_s8(__a, __b, __p) +#define vmulhq_x_s16(__a, __b, __p) __arm_vmulhq_x_s16(__a, __b, __p) +#define vmulhq_x_s32(__a, __b, __p) __arm_vmulhq_x_s32(__a, __b, __p) +#define vmulhq_x_u8(__a, __b, __p) __arm_vmulhq_x_u8(__a, __b, __p) +#define vmulhq_x_u16(__a, __b, __p) __arm_vmulhq_x_u16(__a, __b, __p) +#define vmulhq_x_u32(__a, __b, __p) __arm_vmulhq_x_u32(__a, __b, __p) +#define vmullbq_poly_x_p8(__a, __b, __p) __arm_vmullbq_poly_x_p8(__a, __b, __p) +#define vmullbq_poly_x_p16(__a, __b, __p) __arm_vmullbq_poly_x_p16(__a, __b, __p) +#define vmullbq_int_x_s8(__a, __b, __p) __arm_vmullbq_int_x_s8(__a, __b, __p) +#define vmullbq_int_x_s16(__a, __b, __p) __arm_vmullbq_int_x_s16(__a, __b, __p) +#define vmullbq_int_x_s32(__a, __b, __p) __arm_vmullbq_int_x_s32(__a, __b, __p) +#define vmullbq_int_x_u8(__a, __b, __p) __arm_vmullbq_int_x_u8(__a, __b, __p) +#define vmullbq_int_x_u16(__a, __b, __p) __arm_vmullbq_int_x_u16(__a, __b, __p) +#define vmullbq_int_x_u32(__a, __b, __p) __arm_vmullbq_int_x_u32(__a, __b, __p) +#define vmulltq_poly_x_p8(__a, __b, __p) __arm_vmulltq_poly_x_p8(__a, __b, __p) +#define vmulltq_poly_x_p16(__a, __b, __p) __arm_vmulltq_poly_x_p16(__a, __b, __p) +#define vmulltq_int_x_s8(__a, __b, __p) __arm_vmulltq_int_x_s8(__a, __b, __p) +#define vmulltq_int_x_s16(__a, __b, __p) __arm_vmulltq_int_x_s16(__a, __b, __p) +#define vmulltq_int_x_s32(__a, __b, __p) __arm_vmulltq_int_x_s32(__a, __b, __p) +#define vmulltq_int_x_u8(__a, __b, __p) __arm_vmulltq_int_x_u8(__a, __b, __p) +#define vmulltq_int_x_u16(__a, __b, __p) __arm_vmulltq_int_x_u16(__a, __b, __p) +#define vmulltq_int_x_u32(__a, __b, __p) __arm_vmulltq_int_x_u32(__a, __b, __p) +#define vmulq_x_s8(__a, __b, __p) __arm_vmulq_x_s8(__a, __b, __p) +#define vmulq_x_s16(__a, __b, __p) __arm_vmulq_x_s16(__a, __b, __p) +#define vmulq_x_s32(__a, __b, __p) __arm_vmulq_x_s32(__a, __b, __p) +#define vmulq_x_n_s8(__a, __b, __p) __arm_vmulq_x_n_s8(__a, __b, __p) +#define vmulq_x_n_s16(__a, __b, __p) __arm_vmulq_x_n_s16(__a, __b, __p) +#define vmulq_x_n_s32(__a, __b, __p) __arm_vmulq_x_n_s32(__a, __b, __p) +#define vmulq_x_u8(__a, __b, __p) __arm_vmulq_x_u8(__a, __b, __p) +#define vmulq_x_u16(__a, __b, __p) __arm_vmulq_x_u16(__a, __b, __p) +#define vmulq_x_u32(__a, __b, __p) __arm_vmulq_x_u32(__a, __b, __p) +#define vmulq_x_n_u8(__a, __b, __p) __arm_vmulq_x_n_u8(__a, __b, __p) +#define vmulq_x_n_u16(__a, __b, __p) __arm_vmulq_x_n_u16(__a, __b, __p) +#define vmulq_x_n_u32(__a, __b, __p) __arm_vmulq_x_n_u32(__a, __b, __p) +#define vsubq_x_s8(__a, __b, __p) __arm_vsubq_x_s8(__a, __b, __p) +#define vsubq_x_s16(__a, __b, __p) __arm_vsubq_x_s16(__a, __b, __p) +#define vsubq_x_s32(__a, __b, __p) __arm_vsubq_x_s32(__a, __b, __p) +#define vsubq_x_n_s8(__a, __b, __p) __arm_vsubq_x_n_s8(__a, __b, __p) +#define vsubq_x_n_s16(__a, __b, __p) __arm_vsubq_x_n_s16(__a, __b, __p) +#define vsubq_x_n_s32(__a, __b, __p) __arm_vsubq_x_n_s32(__a, __b, __p) +#define vsubq_x_u8(__a, __b, __p) __arm_vsubq_x_u8(__a, __b, __p) +#define vsubq_x_u16(__a, __b, __p) __arm_vsubq_x_u16(__a, __b, __p) +#define vsubq_x_u32(__a, __b, __p) __arm_vsubq_x_u32(__a, __b, __p) +#define vsubq_x_n_u8(__a, __b, __p) __arm_vsubq_x_n_u8(__a, __b, __p) +#define vsubq_x_n_u16(__a, __b, __p) __arm_vsubq_x_n_u16(__a, __b, __p) +#define vsubq_x_n_u32(__a, __b, __p) __arm_vsubq_x_n_u32(__a, __b, __p) +#define vcaddq_rot90_x_s8(__a, __b, __p) __arm_vcaddq_rot90_x_s8(__a, __b, __p) +#define vcaddq_rot90_x_s16(__a, __b, __p) __arm_vcaddq_rot90_x_s16(__a, __b, __p) +#define vcaddq_rot90_x_s32(__a, __b, __p) __arm_vcaddq_rot90_x_s32(__a, __b, __p) +#define vcaddq_rot90_x_u8(__a, __b, __p) __arm_vcaddq_rot90_x_u8(__a, __b, __p) +#define vcaddq_rot90_x_u16(__a, __b, __p) __arm_vcaddq_rot90_x_u16(__a, __b, __p) +#define vcaddq_rot90_x_u32(__a, __b, __p) __arm_vcaddq_rot90_x_u32(__a, __b, __p) +#define vcaddq_rot270_x_s8(__a, __b, __p) __arm_vcaddq_rot270_x_s8(__a, __b, __p) +#define vcaddq_rot270_x_s16(__a, __b, __p) __arm_vcaddq_rot270_x_s16(__a, __b, __p) +#define vcaddq_rot270_x_s32(__a, __b, __p) __arm_vcaddq_rot270_x_s32(__a, __b, __p) +#define vcaddq_rot270_x_u8(__a, __b, __p) __arm_vcaddq_rot270_x_u8(__a, __b, __p) +#define vcaddq_rot270_x_u16(__a, __b, __p) __arm_vcaddq_rot270_x_u16(__a, __b, __p) +#define vcaddq_rot270_x_u32(__a, __b, __p) __arm_vcaddq_rot270_x_u32(__a, __b, __p) +#define vhaddq_x_n_s8(__a, __b, __p) __arm_vhaddq_x_n_s8(__a, __b, __p) +#define vhaddq_x_n_s16(__a, __b, __p) __arm_vhaddq_x_n_s16(__a, __b, __p) +#define vhaddq_x_n_s32(__a, __b, __p) __arm_vhaddq_x_n_s32(__a, __b, __p) +#define vhaddq_x_n_u8(__a, __b, __p) __arm_vhaddq_x_n_u8(__a, __b, __p) +#define vhaddq_x_n_u16(__a, __b, __p) __arm_vhaddq_x_n_u16(__a, __b, __p) +#define vhaddq_x_n_u32(__a, __b, __p) __arm_vhaddq_x_n_u32(__a, __b, __p) +#define vhaddq_x_s8(__a, __b, __p) __arm_vhaddq_x_s8(__a, __b, __p) +#define vhaddq_x_s16(__a, __b, __p) __arm_vhaddq_x_s16(__a, __b, __p) +#define vhaddq_x_s32(__a, __b, __p) __arm_vhaddq_x_s32(__a, __b, __p) +#define vhaddq_x_u8(__a, __b, __p) __arm_vhaddq_x_u8(__a, __b, __p) +#define vhaddq_x_u16(__a, __b, __p) __arm_vhaddq_x_u16(__a, __b, __p) +#define vhaddq_x_u32(__a, __b, __p) __arm_vhaddq_x_u32(__a, __b, __p) +#define vhcaddq_rot90_x_s8(__a, __b, __p) __arm_vhcaddq_rot90_x_s8(__a, __b, __p) +#define vhcaddq_rot90_x_s16(__a, __b, __p) __arm_vhcaddq_rot90_x_s16(__a, __b, __p) +#define vhcaddq_rot90_x_s32(__a, __b, __p) __arm_vhcaddq_rot90_x_s32(__a, __b, __p) +#define vhcaddq_rot270_x_s8(__a, __b, __p) __arm_vhcaddq_rot270_x_s8(__a, __b, __p) +#define vhcaddq_rot270_x_s16(__a, __b, __p) __arm_vhcaddq_rot270_x_s16(__a, __b, __p) +#define vhcaddq_rot270_x_s32(__a, __b, __p) __arm_vhcaddq_rot270_x_s32(__a, __b, __p) +#define vhsubq_x_n_s8(__a, __b, __p) __arm_vhsubq_x_n_s8(__a, __b, __p) +#define vhsubq_x_n_s16(__a, __b, __p) __arm_vhsubq_x_n_s16(__a, __b, __p) +#define vhsubq_x_n_s32(__a, __b, __p) __arm_vhsubq_x_n_s32(__a, __b, __p) +#define vhsubq_x_n_u8(__a, __b, __p) __arm_vhsubq_x_n_u8(__a, __b, __p) +#define vhsubq_x_n_u16(__a, __b, __p) __arm_vhsubq_x_n_u16(__a, __b, __p) +#define vhsubq_x_n_u32(__a, __b, __p) __arm_vhsubq_x_n_u32(__a, __b, __p) +#define vhsubq_x_s8(__a, __b, __p) __arm_vhsubq_x_s8(__a, __b, __p) +#define vhsubq_x_s16(__a, __b, __p) __arm_vhsubq_x_s16(__a, __b, __p) +#define vhsubq_x_s32(__a, __b, __p) __arm_vhsubq_x_s32(__a, __b, __p) +#define vhsubq_x_u8(__a, __b, __p) __arm_vhsubq_x_u8(__a, __b, __p) +#define vhsubq_x_u16(__a, __b, __p) __arm_vhsubq_x_u16(__a, __b, __p) +#define vhsubq_x_u32(__a, __b, __p) __arm_vhsubq_x_u32(__a, __b, __p) +#define vrhaddq_x_s8(__a, __b, __p) __arm_vrhaddq_x_s8(__a, __b, __p) +#define vrhaddq_x_s16(__a, __b, __p) __arm_vrhaddq_x_s16(__a, __b, __p) +#define vrhaddq_x_s32(__a, __b, __p) __arm_vrhaddq_x_s32(__a, __b, __p) +#define vrhaddq_x_u8(__a, __b, __p) __arm_vrhaddq_x_u8(__a, __b, __p) +#define vrhaddq_x_u16(__a, __b, __p) __arm_vrhaddq_x_u16(__a, __b, __p) +#define vrhaddq_x_u32(__a, __b, __p) __arm_vrhaddq_x_u32(__a, __b, __p) +#define vrmulhq_x_s8(__a, __b, __p) __arm_vrmulhq_x_s8(__a, __b, __p) +#define vrmulhq_x_s16(__a, __b, __p) __arm_vrmulhq_x_s16(__a, __b, __p) +#define vrmulhq_x_s32(__a, __b, __p) __arm_vrmulhq_x_s32(__a, __b, __p) +#define vrmulhq_x_u8(__a, __b, __p) __arm_vrmulhq_x_u8(__a, __b, __p) +#define vrmulhq_x_u16(__a, __b, __p) __arm_vrmulhq_x_u16(__a, __b, __p) +#define vrmulhq_x_u32(__a, __b, __p) __arm_vrmulhq_x_u32(__a, __b, __p) +#define vandq_x_s8(__a, __b, __p) __arm_vandq_x_s8(__a, __b, __p) +#define vandq_x_s16(__a, __b, __p) __arm_vandq_x_s16(__a, __b, __p) +#define vandq_x_s32(__a, __b, __p) __arm_vandq_x_s32(__a, __b, __p) +#define vandq_x_u8(__a, __b, __p) __arm_vandq_x_u8(__a, __b, __p) +#define vandq_x_u16(__a, __b, __p) __arm_vandq_x_u16(__a, __b, __p) +#define vandq_x_u32(__a, __b, __p) __arm_vandq_x_u32(__a, __b, __p) +#define vbicq_x_s8(__a, __b, __p) __arm_vbicq_x_s8(__a, __b, __p) +#define vbicq_x_s16(__a, __b, __p) __arm_vbicq_x_s16(__a, __b, __p) +#define vbicq_x_s32(__a, __b, __p) __arm_vbicq_x_s32(__a, __b, __p) +#define vbicq_x_u8(__a, __b, __p) __arm_vbicq_x_u8(__a, __b, __p) +#define vbicq_x_u16(__a, __b, __p) __arm_vbicq_x_u16(__a, __b, __p) +#define vbicq_x_u32(__a, __b, __p) __arm_vbicq_x_u32(__a, __b, __p) +#define vbrsrq_x_n_s8(__a, __b, __p) __arm_vbrsrq_x_n_s8(__a, __b, __p) +#define vbrsrq_x_n_s16(__a, __b, __p) __arm_vbrsrq_x_n_s16(__a, __b, __p) +#define vbrsrq_x_n_s32(__a, __b, __p) __arm_vbrsrq_x_n_s32(__a, __b, __p) +#define vbrsrq_x_n_u8(__a, __b, __p) __arm_vbrsrq_x_n_u8(__a, __b, __p) +#define vbrsrq_x_n_u16(__a, __b, __p) __arm_vbrsrq_x_n_u16(__a, __b, __p) +#define vbrsrq_x_n_u32(__a, __b, __p) __arm_vbrsrq_x_n_u32(__a, __b, __p) +#define veorq_x_s8(__a, __b, __p) __arm_veorq_x_s8(__a, __b, __p) +#define veorq_x_s16(__a, __b, __p) __arm_veorq_x_s16(__a, __b, __p) +#define veorq_x_s32(__a, __b, __p) __arm_veorq_x_s32(__a, __b, __p) +#define veorq_x_u8(__a, __b, __p) __arm_veorq_x_u8(__a, __b, __p) +#define veorq_x_u16(__a, __b, __p) __arm_veorq_x_u16(__a, __b, __p) +#define veorq_x_u32(__a, __b, __p) __arm_veorq_x_u32(__a, __b, __p) +#define vmovlbq_x_s8(__a, __p) __arm_vmovlbq_x_s8(__a, __p) +#define vmovlbq_x_s16(__a, __p) __arm_vmovlbq_x_s16(__a, __p) +#define vmovlbq_x_u8(__a, __p) __arm_vmovlbq_x_u8(__a, __p) +#define vmovlbq_x_u16(__a, __p) __arm_vmovlbq_x_u16(__a, __p) +#define vmovltq_x_s8(__a, __p) __arm_vmovltq_x_s8(__a, __p) +#define vmovltq_x_s16(__a, __p) __arm_vmovltq_x_s16(__a, __p) +#define vmovltq_x_u8(__a, __p) __arm_vmovltq_x_u8(__a, __p) +#define vmovltq_x_u16(__a, __p) __arm_vmovltq_x_u16(__a, __p) +#define vmvnq_x_s8(__a, __p) __arm_vmvnq_x_s8(__a, __p) +#define vmvnq_x_s16(__a, __p) __arm_vmvnq_x_s16(__a, __p) +#define vmvnq_x_s32(__a, __p) __arm_vmvnq_x_s32(__a, __p) +#define vmvnq_x_u8(__a, __p) __arm_vmvnq_x_u8(__a, __p) +#define vmvnq_x_u16(__a, __p) __arm_vmvnq_x_u16(__a, __p) +#define vmvnq_x_u32(__a, __p) __arm_vmvnq_x_u32(__a, __p) +#define vmvnq_x_n_s16( __imm, __p) __arm_vmvnq_x_n_s16( __imm, __p) +#define vmvnq_x_n_s32( __imm, __p) __arm_vmvnq_x_n_s32( __imm, __p) +#define vmvnq_x_n_u16( __imm, __p) __arm_vmvnq_x_n_u16( __imm, __p) +#define vmvnq_x_n_u32( __imm, __p) __arm_vmvnq_x_n_u32( __imm, __p) +#define vornq_x_s8(__a, __b, __p) __arm_vornq_x_s8(__a, __b, __p) +#define vornq_x_s16(__a, __b, __p) __arm_vornq_x_s16(__a, __b, __p) +#define vornq_x_s32(__a, __b, __p) __arm_vornq_x_s32(__a, __b, __p) +#define vornq_x_u8(__a, __b, __p) __arm_vornq_x_u8(__a, __b, __p) +#define vornq_x_u16(__a, __b, __p) __arm_vornq_x_u16(__a, __b, __p) +#define vornq_x_u32(__a, __b, __p) __arm_vornq_x_u32(__a, __b, __p) +#define vorrq_x_s8(__a, __b, __p) __arm_vorrq_x_s8(__a, __b, __p) +#define vorrq_x_s16(__a, __b, __p) __arm_vorrq_x_s16(__a, __b, __p) +#define vorrq_x_s32(__a, __b, __p) __arm_vorrq_x_s32(__a, __b, __p) +#define vorrq_x_u8(__a, __b, __p) __arm_vorrq_x_u8(__a, __b, __p) +#define vorrq_x_u16(__a, __b, __p) __arm_vorrq_x_u16(__a, __b, __p) +#define vorrq_x_u32(__a, __b, __p) __arm_vorrq_x_u32(__a, __b, __p) +#define vrev16q_x_s8(__a, __p) __arm_vrev16q_x_s8(__a, __p) +#define vrev16q_x_u8(__a, __p) __arm_vrev16q_x_u8(__a, __p) +#define vrev32q_x_s8(__a, __p) __arm_vrev32q_x_s8(__a, __p) +#define vrev32q_x_s16(__a, __p) __arm_vrev32q_x_s16(__a, __p) +#define vrev32q_x_u8(__a, __p) __arm_vrev32q_x_u8(__a, __p) +#define vrev32q_x_u16(__a, __p) __arm_vrev32q_x_u16(__a, __p) +#define vrev64q_x_s8(__a, __p) __arm_vrev64q_x_s8(__a, __p) +#define vrev64q_x_s16(__a, __p) __arm_vrev64q_x_s16(__a, __p) +#define vrev64q_x_s32(__a, __p) __arm_vrev64q_x_s32(__a, __p) +#define vrev64q_x_u8(__a, __p) __arm_vrev64q_x_u8(__a, __p) +#define vrev64q_x_u16(__a, __p) __arm_vrev64q_x_u16(__a, __p) +#define vrev64q_x_u32(__a, __p) __arm_vrev64q_x_u32(__a, __p) +#define vrshlq_x_s8(__a, __b, __p) __arm_vrshlq_x_s8(__a, __b, __p) +#define vrshlq_x_s16(__a, __b, __p) __arm_vrshlq_x_s16(__a, __b, __p) +#define vrshlq_x_s32(__a, __b, __p) __arm_vrshlq_x_s32(__a, __b, __p) +#define vrshlq_x_u8(__a, __b, __p) __arm_vrshlq_x_u8(__a, __b, __p) +#define vrshlq_x_u16(__a, __b, __p) __arm_vrshlq_x_u16(__a, __b, __p) +#define vrshlq_x_u32(__a, __b, __p) __arm_vrshlq_x_u32(__a, __b, __p) +#define vshllbq_x_n_s8(__a, __imm, __p) __arm_vshllbq_x_n_s8(__a, __imm, __p) +#define vshllbq_x_n_s16(__a, __imm, __p) __arm_vshllbq_x_n_s16(__a, __imm, __p) +#define vshllbq_x_n_u8(__a, __imm, __p) __arm_vshllbq_x_n_u8(__a, __imm, __p) +#define vshllbq_x_n_u16(__a, __imm, __p) __arm_vshllbq_x_n_u16(__a, __imm, __p) +#define vshlltq_x_n_s8(__a, __imm, __p) __arm_vshlltq_x_n_s8(__a, __imm, __p) +#define vshlltq_x_n_s16(__a, __imm, __p) __arm_vshlltq_x_n_s16(__a, __imm, __p) +#define vshlltq_x_n_u8(__a, __imm, __p) __arm_vshlltq_x_n_u8(__a, __imm, __p) +#define vshlltq_x_n_u16(__a, __imm, __p) __arm_vshlltq_x_n_u16(__a, __imm, __p) +#define vshlq_x_s8(__a, __b, __p) __arm_vshlq_x_s8(__a, __b, __p) +#define vshlq_x_s16(__a, __b, __p) __arm_vshlq_x_s16(__a, __b, __p) +#define vshlq_x_s32(__a, __b, __p) __arm_vshlq_x_s32(__a, __b, __p) +#define vshlq_x_u8(__a, __b, __p) __arm_vshlq_x_u8(__a, __b, __p) +#define vshlq_x_u16(__a, __b, __p) __arm_vshlq_x_u16(__a, __b, __p) +#define vshlq_x_u32(__a, __b, __p) __arm_vshlq_x_u32(__a, __b, __p) +#define vshlq_x_n_s8(__a, __imm, __p) __arm_vshlq_x_n_s8(__a, __imm, __p) +#define vshlq_x_n_s16(__a, __imm, __p) __arm_vshlq_x_n_s16(__a, __imm, __p) +#define vshlq_x_n_s32(__a, __imm, __p) __arm_vshlq_x_n_s32(__a, __imm, __p) +#define vshlq_x_n_u8(__a, __imm, __p) __arm_vshlq_x_n_u8(__a, __imm, __p) +#define vshlq_x_n_u16(__a, __imm, __p) __arm_vshlq_x_n_u16(__a, __imm, __p) +#define vshlq_x_n_u32(__a, __imm, __p) __arm_vshlq_x_n_u32(__a, __imm, __p) +#define vrshrq_x_n_s8(__a, __imm, __p) __arm_vrshrq_x_n_s8(__a, __imm, __p) +#define vrshrq_x_n_s16(__a, __imm, __p) __arm_vrshrq_x_n_s16(__a, __imm, __p) +#define vrshrq_x_n_s32(__a, __imm, __p) __arm_vrshrq_x_n_s32(__a, __imm, __p) +#define vrshrq_x_n_u8(__a, __imm, __p) __arm_vrshrq_x_n_u8(__a, __imm, __p) +#define vrshrq_x_n_u16(__a, __imm, __p) __arm_vrshrq_x_n_u16(__a, __imm, __p) +#define vrshrq_x_n_u32(__a, __imm, __p) __arm_vrshrq_x_n_u32(__a, __imm, __p) +#define vshrq_x_n_s8(__a, __imm, __p) __arm_vshrq_x_n_s8(__a, __imm, __p) +#define vshrq_x_n_s16(__a, __imm, __p) __arm_vshrq_x_n_s16(__a, __imm, __p) +#define vshrq_x_n_s32(__a, __imm, __p) __arm_vshrq_x_n_s32(__a, __imm, __p) +#define vshrq_x_n_u8(__a, __imm, __p) __arm_vshrq_x_n_u8(__a, __imm, __p) +#define vshrq_x_n_u16(__a, __imm, __p) __arm_vshrq_x_n_u16(__a, __imm, __p) +#define vshrq_x_n_u32(__a, __imm, __p) __arm_vshrq_x_n_u32(__a, __imm, __p) +#define vdupq_x_n_f16(__a, __p) __arm_vdupq_x_n_f16(__a, __p) +#define vdupq_x_n_f32(__a, __p) __arm_vdupq_x_n_f32(__a, __p) +#define vminnmq_x_f16(__a, __b, __p) __arm_vminnmq_x_f16(__a, __b, __p) +#define vminnmq_x_f32(__a, __b, __p) __arm_vminnmq_x_f32(__a, __b, __p) +#define vmaxnmq_x_f16(__a, __b, __p) __arm_vmaxnmq_x_f16(__a, __b, __p) +#define vmaxnmq_x_f32(__a, __b, __p) __arm_vmaxnmq_x_f32(__a, __b, __p) +#define vabdq_x_f16(__a, __b, __p) __arm_vabdq_x_f16(__a, __b, __p) +#define vabdq_x_f32(__a, __b, __p) __arm_vabdq_x_f32(__a, __b, __p) +#define vabsq_x_f16(__a, __p) __arm_vabsq_x_f16(__a, __p) +#define vabsq_x_f32(__a, __p) __arm_vabsq_x_f32(__a, __p) +#define vaddq_x_f16(__a, __b, __p) __arm_vaddq_x_f16(__a, __b, __p) +#define vaddq_x_f32(__a, __b, __p) __arm_vaddq_x_f32(__a, __b, __p) +#define vaddq_x_n_f16(__a, __b, __p) __arm_vaddq_x_n_f16(__a, __b, __p) +#define vaddq_x_n_f32(__a, __b, __p) __arm_vaddq_x_n_f32(__a, __b, __p) +#define vnegq_x_f16(__a, __p) __arm_vnegq_x_f16(__a, __p) +#define vnegq_x_f32(__a, __p) __arm_vnegq_x_f32(__a, __p) +#define vmulq_x_f16(__a, __b, __p) __arm_vmulq_x_f16(__a, __b, __p) +#define vmulq_x_f32(__a, __b, __p) __arm_vmulq_x_f32(__a, __b, __p) +#define vmulq_x_n_f16(__a, __b, __p) __arm_vmulq_x_n_f16(__a, __b, __p) +#define vmulq_x_n_f32(__a, __b, __p) __arm_vmulq_x_n_f32(__a, __b, __p) +#define vsubq_x_f16(__a, __b, __p) __arm_vsubq_x_f16(__a, __b, __p) +#define vsubq_x_f32(__a, __b, __p) __arm_vsubq_x_f32(__a, __b, __p) +#define vsubq_x_n_f16(__a, __b, __p) __arm_vsubq_x_n_f16(__a, __b, __p) +#define vsubq_x_n_f32(__a, __b, __p) __arm_vsubq_x_n_f32(__a, __b, __p) +#define vcaddq_rot90_x_f16(__a, __b, __p) __arm_vcaddq_rot90_x_f16(__a, __b, __p) +#define vcaddq_rot90_x_f32(__a, __b, __p) __arm_vcaddq_rot90_x_f32(__a, __b, __p) +#define vcaddq_rot270_x_f16(__a, __b, __p) __arm_vcaddq_rot270_x_f16(__a, __b, __p) +#define vcaddq_rot270_x_f32(__a, __b, __p) __arm_vcaddq_rot270_x_f32(__a, __b, __p) +#define vcmulq_x_f16(__a, __b, __p) __arm_vcmulq_x_f16(__a, __b, __p) +#define vcmulq_x_f32(__a, __b, __p) __arm_vcmulq_x_f32(__a, __b, __p) +#define vcmulq_rot90_x_f16(__a, __b, __p) __arm_vcmulq_rot90_x_f16(__a, __b, __p) +#define vcmulq_rot90_x_f32(__a, __b, __p) __arm_vcmulq_rot90_x_f32(__a, __b, __p) +#define vcmulq_rot180_x_f16(__a, __b, __p) __arm_vcmulq_rot180_x_f16(__a, __b, __p) +#define vcmulq_rot180_x_f32(__a, __b, __p) __arm_vcmulq_rot180_x_f32(__a, __b, __p) +#define vcmulq_rot270_x_f16(__a, __b, __p) __arm_vcmulq_rot270_x_f16(__a, __b, __p) +#define vcmulq_rot270_x_f32(__a, __b, __p) __arm_vcmulq_rot270_x_f32(__a, __b, __p) +#define vcvtaq_x_s16_f16(__a, __p) __arm_vcvtaq_x_s16_f16(__a, __p) +#define vcvtaq_x_s32_f32(__a, __p) __arm_vcvtaq_x_s32_f32(__a, __p) +#define vcvtaq_x_u16_f16(__a, __p) __arm_vcvtaq_x_u16_f16(__a, __p) +#define vcvtaq_x_u32_f32(__a, __p) __arm_vcvtaq_x_u32_f32(__a, __p) +#define vcvtnq_x_s16_f16(__a, __p) __arm_vcvtnq_x_s16_f16(__a, __p) +#define vcvtnq_x_s32_f32(__a, __p) __arm_vcvtnq_x_s32_f32(__a, __p) +#define vcvtnq_x_u16_f16(__a, __p) __arm_vcvtnq_x_u16_f16(__a, __p) +#define vcvtnq_x_u32_f32(__a, __p) __arm_vcvtnq_x_u32_f32(__a, __p) +#define vcvtpq_x_s16_f16(__a, __p) __arm_vcvtpq_x_s16_f16(__a, __p) +#define vcvtpq_x_s32_f32(__a, __p) __arm_vcvtpq_x_s32_f32(__a, __p) +#define vcvtpq_x_u16_f16(__a, __p) __arm_vcvtpq_x_u16_f16(__a, __p) +#define vcvtpq_x_u32_f32(__a, __p) __arm_vcvtpq_x_u32_f32(__a, __p) +#define vcvtmq_x_s16_f16(__a, __p) __arm_vcvtmq_x_s16_f16(__a, __p) +#define vcvtmq_x_s32_f32(__a, __p) __arm_vcvtmq_x_s32_f32(__a, __p) +#define vcvtmq_x_u16_f16(__a, __p) __arm_vcvtmq_x_u16_f16(__a, __p) +#define vcvtmq_x_u32_f32(__a, __p) __arm_vcvtmq_x_u32_f32(__a, __p) +#define vcvtbq_x_f32_f16(__a, __p) __arm_vcvtbq_x_f32_f16(__a, __p) +#define vcvttq_x_f32_f16(__a, __p) __arm_vcvttq_x_f32_f16(__a, __p) +#define vcvtq_x_f16_u16(__a, __p) __arm_vcvtq_x_f16_u16(__a, __p) +#define vcvtq_x_f16_s16(__a, __p) __arm_vcvtq_x_f16_s16(__a, __p) +#define vcvtq_x_f32_s32(__a, __p) __arm_vcvtq_x_f32_s32(__a, __p) +#define vcvtq_x_f32_u32(__a, __p) __arm_vcvtq_x_f32_u32(__a, __p) +#define vcvtq_x_n_f16_s16(__a, __imm6, __p) __arm_vcvtq_x_n_f16_s16(__a, __imm6, __p) +#define vcvtq_x_n_f16_u16(__a, __imm6, __p) __arm_vcvtq_x_n_f16_u16(__a, __imm6, __p) +#define vcvtq_x_n_f32_s32(__a, __imm6, __p) __arm_vcvtq_x_n_f32_s32(__a, __imm6, __p) +#define vcvtq_x_n_f32_u32(__a, __imm6, __p) __arm_vcvtq_x_n_f32_u32(__a, __imm6, __p) +#define vcvtq_x_s16_f16(__a, __p) __arm_vcvtq_x_s16_f16(__a, __p) +#define vcvtq_x_s32_f32(__a, __p) __arm_vcvtq_x_s32_f32(__a, __p) +#define vcvtq_x_u16_f16(__a, __p) __arm_vcvtq_x_u16_f16(__a, __p) +#define vcvtq_x_u32_f32(__a, __p) __arm_vcvtq_x_u32_f32(__a, __p) +#define vcvtq_x_n_s16_f16(__a, __imm6, __p) __arm_vcvtq_x_n_s16_f16(__a, __imm6, __p) +#define vcvtq_x_n_s32_f32(__a, __imm6, __p) __arm_vcvtq_x_n_s32_f32(__a, __imm6, __p) +#define vcvtq_x_n_u16_f16(__a, __imm6, __p) __arm_vcvtq_x_n_u16_f16(__a, __imm6, __p) +#define vcvtq_x_n_u32_f32(__a, __imm6, __p) __arm_vcvtq_x_n_u32_f32(__a, __imm6, __p) +#define vrndq_x_f16(__a, __p) __arm_vrndq_x_f16(__a, __p) +#define vrndq_x_f32(__a, __p) __arm_vrndq_x_f32(__a, __p) +#define vrndnq_x_f16(__a, __p) __arm_vrndnq_x_f16(__a, __p) +#define vrndnq_x_f32(__a, __p) __arm_vrndnq_x_f32(__a, __p) +#define vrndmq_x_f16(__a, __p) __arm_vrndmq_x_f16(__a, __p) +#define vrndmq_x_f32(__a, __p) __arm_vrndmq_x_f32(__a, __p) +#define vrndpq_x_f16(__a, __p) __arm_vrndpq_x_f16(__a, __p) +#define vrndpq_x_f32(__a, __p) __arm_vrndpq_x_f32(__a, __p) +#define vrndaq_x_f16(__a, __p) __arm_vrndaq_x_f16(__a, __p) +#define vrndaq_x_f32(__a, __p) __arm_vrndaq_x_f32(__a, __p) +#define vrndxq_x_f16(__a, __p) __arm_vrndxq_x_f16(__a, __p) +#define vrndxq_x_f32(__a, __p) __arm_vrndxq_x_f32(__a, __p) +#define vandq_x_f16(__a, __b, __p) __arm_vandq_x_f16(__a, __b, __p) +#define vandq_x_f32(__a, __b, __p) __arm_vandq_x_f32(__a, __b, __p) +#define vbicq_x_f16(__a, __b, __p) __arm_vbicq_x_f16(__a, __b, __p) +#define vbicq_x_f32(__a, __b, __p) __arm_vbicq_x_f32(__a, __b, __p) +#define vbrsrq_x_n_f16(__a, __b, __p) __arm_vbrsrq_x_n_f16(__a, __b, __p) +#define vbrsrq_x_n_f32(__a, __b, __p) __arm_vbrsrq_x_n_f32(__a, __b, __p) +#define veorq_x_f16(__a, __b, __p) __arm_veorq_x_f16(__a, __b, __p) +#define veorq_x_f32(__a, __b, __p) __arm_veorq_x_f32(__a, __b, __p) +#define vornq_x_f16(__a, __b, __p) __arm_vornq_x_f16(__a, __b, __p) +#define vornq_x_f32(__a, __b, __p) __arm_vornq_x_f32(__a, __b, __p) +#define vorrq_x_f16(__a, __b, __p) __arm_vorrq_x_f16(__a, __b, __p) +#define vorrq_x_f32(__a, __b, __p) __arm_vorrq_x_f32(__a, __b, __p) +#define vrev32q_x_f16(__a, __p) __arm_vrev32q_x_f16(__a, __p) +#define vrev64q_x_f16(__a, __p) __arm_vrev64q_x_f16(__a, __p) +#define vrev64q_x_f32(__a, __p) __arm_vrev64q_x_f32(__a, __p) #endif __extension__ extern __inline void @@ -13552,2676 +13928,5344 @@ __arm_vstrwq_scatter_base_wb_u32 (uint32x4_t * __addr, const int __offset, uint3 __builtin_mve_vstrwq_scatter_base_wb_add_uv4si (*__addr, __offset, *__addr); } -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vddupq_x_n_u8 (uint32_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vddupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p); +} -__extension__ extern __inline void +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +__arm_vddupq_x_n_u16 (uint32_t __a, const int __imm, mve_pred16_t __p) { - union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv8hf (__addr, __rv.__o); + return __builtin_mve_vddupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +__arm_vddupq_x_n_u32 (uint32_t __a, const int __imm, mve_pred16_t __p) { - union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; - __rv.__i = __value; - __builtin_mve_vst4qv4sf (__addr, __rv.__o); + return __builtin_mve_vddupq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f16 (float16x8_t __a) +__arm_vddupq_x_wb_u8 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndxq_fv8hf (__a); + uint8x16_t __arg1 = vuninitializedq_u8 (); + uint8x16_t __res = __builtin_mve_vddupq_m_n_uv16qi (__arg1, * __a, __imm, __p); + *__a -= __imm * 16u; + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_f32 (float32x4_t __a) +__arm_vddupq_x_wb_u16 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndxq_fv4sf (__a); + uint16x8_t __arg1 = vuninitializedq_u16 (); + uint16x8_t __res = __builtin_mve_vddupq_m_n_uv8hi (__arg1, *__a, __imm, __p); + *__a -= __imm * 8u; + return __res; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f16 (float16x8_t __a) +__arm_vddupq_x_wb_u32 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndq_fv8hf (__a); + uint32x4_t __arg1 = vuninitializedq_u32 (); + uint32x4_t __res = __builtin_mve_vddupq_m_n_uv4si (__arg1, *__a, __imm, __p); + *__a -= __imm * 4u; + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_f32 (float32x4_t __a) +__arm_vdwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndq_fv4sf (__a); + return __builtin_mve_vdwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f16 (float16x8_t __a) +__arm_vdwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndpq_fv8hf (__a); + return __builtin_mve_vdwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_f32 (float32x4_t __a) +__arm_vdwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndpq_fv4sf (__a); + return __builtin_mve_vdwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f16 (float16x8_t __a) +__arm_vdwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndnq_fv8hf (__a); + uint8x16_t __arg1 = vuninitializedq_u8 (); + uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_f32 (float32x4_t __a) +__arm_vdwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndnq_fv4sf (__a); + uint16x8_t __arg1 = vuninitializedq_u16 (); + uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f16 (float16x8_t __a) +__arm_vdwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndmq_fv8hf (__a); + uint32x4_t __arg1 = vuninitializedq_u32 (); + uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_vdwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_f32 (float32x4_t __a) +__arm_vidupq_x_n_u8 (uint32_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndmq_fv4sf (__a); + return __builtin_mve_vidupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f16 (float16x8_t __a) +__arm_vidupq_x_n_u16 (uint32_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndaq_fv8hf (__a); + return __builtin_mve_vidupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_f32 (float32x4_t __a) +__arm_vidupq_x_n_u32 (uint32_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrndaq_fv4sf (__a); + return __builtin_mve_vidupq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f16 (float16x8_t __a) +__arm_vidupq_x_wb_u8 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrev64q_fv8hf (__a); + uint8x16_t __arg1 = vuninitializedq_u8 (); + uint8x16_t __res = __builtin_mve_vidupq_m_n_uv16qi (__arg1, *__a, __imm, __p); + *__a += __imm * 16u; + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_f32 (float32x4_t __a) +__arm_vidupq_x_wb_u16 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrev64q_fv4sf (__a); + uint16x8_t __arg1 = vuninitializedq_u16 (); + uint16x8_t __res = __builtin_mve_vidupq_m_n_uv8hi (__arg1, *__a, __imm, __p); + *__a += __imm * 8u; + return __res; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f16 (float16x8_t __a) +__arm_vidupq_x_wb_u32 (uint32_t *__a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vnegq_fv8hf (__a); + uint32x4_t __arg1 = vuninitializedq_u32 (); + uint32x4_t __res = __builtin_mve_vidupq_m_n_uv4si (__arg1, *__a, __imm, __p); + *__a += __imm * 4u; + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_f32 (float32x4_t __a) +__arm_viwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vnegq_fv4sf (__a); + return __builtin_mve_viwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f16 (float16_t __a) +__arm_viwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vdupq_n_fv8hf (__a); + return __builtin_mve_viwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_n_f32 (float32_t __a) +__arm_viwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vdupq_n_fv4sf (__a); + return __builtin_mve_viwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f16 (float16x8_t __a) +__arm_viwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vabsq_fv8hf (__a); + uint8x16_t __arg1 = vuninitializedq_u8 (); + uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_f32 (float32x4_t __a) +__arm_viwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vabsq_fv4sf (__a); + uint16x8_t __arg1 = vuninitializedq_u16 (); + uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_f16 (float16x8_t __a) +__arm_viwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vrev32q_fv8hf (__a); + uint32x4_t __arg1 = vuninitializedq_u32 (); + uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p); + *__a = __builtin_mve_viwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p); + return __res; } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_f32_f16 (float16x8_t __a) +__arm_vdupq_x_n_s8 (int8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvttq_f32_f16v4sf (__a); + return __builtin_mve_vdupq_m_n_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_f32_f16 (float16x8_t __a) +__arm_vdupq_x_n_s16 (int16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtbq_f32_f16v4sf (__a); + return __builtin_mve_vdupq_m_n_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_s16 (int16x8_t __a) +__arm_vdupq_x_n_s32 (int32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_sv8hf (__a); + return __builtin_mve_vdupq_m_n_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_s32 (int32x4_t __a) +__arm_vdupq_x_n_u8 (uint8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_sv4sf (__a); + return __builtin_mve_vdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f16_u16 (uint16x8_t __a) +__arm_vdupq_x_n_u16 (uint16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_uv8hf (__a); + return __builtin_mve_vdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_f32_u32 (uint32x4_t __a) +__arm_vdupq_x_n_u32 (uint32_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_to_f_uv4sf (__a); + return __builtin_mve_vdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s16_f16 (float16x8_t __a) +__arm_vminq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_sv8hi (__a); + return __builtin_mve_vminq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_s32_f32 (float32x4_t __a) +__arm_vminq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_sv4si (__a); + return __builtin_mve_vminq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u16_f16 (float16x8_t __a) +__arm_vminq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_uv8hi (__a); + return __builtin_mve_vminq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_u32_f32 (float32x4_t __a) +__arm_vminq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_from_f_uv4si (__a); + return __builtin_mve_vminq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u16_f16 (float16x8_t __a) +__arm_vminq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_uv8hi (__a); + return __builtin_mve_vminq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_u32_f32 (float32x4_t __a) +__arm_vminq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_uv4si (__a); + return __builtin_mve_vminq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_u16_f16 (float16x8_t __a) +__arm_vmaxq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_uv8hi (__a); + return __builtin_mve_vmaxq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u16_f16 (float16x8_t __a) +__arm_vmaxq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_uv8hi (__a); + return __builtin_mve_vmaxq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_u32_f32 (float32x4_t __a) +__arm_vmaxq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_uv4si (__a); + return __builtin_mve_vmaxq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u16_f16 (float16x8_t __a) +__arm_vmaxq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_uv8hi (__a); + return __builtin_mve_vmaxq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_u32_f32 (float32x4_t __a) +__arm_vmaxq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_uv4si (__a); + return __builtin_mve_vmaxq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s16_f16 (float16x8_t __a) +__arm_vabdq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_sv8hi (__a); + return __builtin_mve_vabdq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_s32_f32 (float32x4_t __a) +__arm_vabdq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_sv4si (__a); + return __builtin_mve_vabdq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s16_f16 (float16x8_t __a) +__arm_vabdq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_sv8hi (__a); + return __builtin_mve_vabdq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_s32_f32 (float32x4_t __a) +__arm_vabdq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_sv4si (__a); + return __builtin_mve_vabdq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s16_f16 (float16x8_t __a) +__arm_vabdq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_sv8hi (__a); + return __builtin_mve_vabdq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_s32_f32 (float32x4_t __a) +__arm_vabsq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_sv4si (__a); + return __builtin_mve_vabsq_m_sv16qi (vuninitializedq_s8 (), __a, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s16_f16 (float16x8_t __a) +__arm_vabsq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_sv8hi (__a); + return __builtin_mve_vabsq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_s32_f32 (float32x4_t __a) +__arm_vabsq_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_sv4si (__a); + return __builtin_mve_vabsq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_n_fv8hf (__a, __b); + return __builtin_mve_vaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_n_fv4sf (__a, __b); + return __builtin_mve_vaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +__arm_vaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); + return __builtin_mve_vaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +__arm_vaddq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) { - return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); + return __builtin_mve_vaddq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +__arm_vaddq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); + return __builtin_mve_vaddq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +__arm_vaddq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); + return __builtin_mve_vaddq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +__arm_vaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); + return __builtin_mve_vaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +__arm_vaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); + return __builtin_mve_vaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +__arm_vaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcreateq_fv8hf (__a, __b); + return __builtin_mve_vaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +__arm_vaddq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcreateq_fv4sf (__a, __b); + return __builtin_mve_vaddq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +__arm_vaddq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); + return __builtin_mve_vaddq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +__arm_vaddq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); + return __builtin_mve_vaddq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +__arm_vclsq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); + return __builtin_mve_vclsq_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +__arm_vclsq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); + return __builtin_mve_vclsq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vclsq_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_n_fv8hf (__a, __b); + return __builtin_mve_vclsq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vclzq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vclzq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_n_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vclzq_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vclzq_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_n_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vclzq_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vclzq_x_u32 (uint32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b); + return __builtin_mve_vclzq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vnegq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_fv8hf (__a, __b); + return __builtin_mve_vnegq_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vnegq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b); + return __builtin_mve_vnegq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vnegq_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_fv8hf (__a, __b); + return __builtin_mve_vnegq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmulhq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulhq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulhq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulhq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vorrq_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulhq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vornq_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmulhq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_n_fv8hf (__a, __b); + return __builtin_mve_vmulhq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmullbq_poly_x_p8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_poly_m_pv16qi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b) +__arm_vmullbq_poly_x_p16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmvq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_poly_m_pv8hi (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmullbq_int_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_sv16qi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b) +__arm_vmullbq_int_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmavq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_sv8hi (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmullbq_int_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmaq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_sv4si (vuninitializedq_s64 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b) +__arm_vmullbq_int_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmvq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_uv16qi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmullbq_int_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_uv8hi (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b) +__arm_vmullbq_int_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmavq_fv8hf (__a, __b); + return __builtin_mve_vmullbq_int_m_uv4si (vuninitializedq_u64 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_poly_x_p8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmaq_fv8hf (__a, __b); + return __builtin_mve_vmulltq_poly_m_pv16qi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_poly_x_p16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_veorq_fv8hf (__a, __b); + return __builtin_mve_vmulltq_poly_m_pv8hi (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_sv16qi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_sv8hi (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_sv4si (vuninitializedq_s64 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_uv16qi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_uv8hi (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulltq_int_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); + return __builtin_mve_vmulltq_int_m_uv4si (vuninitializedq_u64 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vbicq_fv8hf (__a, __b); + return __builtin_mve_vmulq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vandq_fv8hf (__a, __b); + return __builtin_mve_vmulq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b) +__arm_vmulq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vaddq_n_fv8hf (__a, __b); + return __builtin_mve_vmulq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vmulq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) { - return __builtin_mve_vabdq_fv8hf (__a, __b); + return __builtin_mve_vmulq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmulq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_n_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmulq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmulq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_n_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmulq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmulq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_n_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmulq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vmulq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vmulq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_fv4sf (__a, __b); + return __builtin_mve_vmulq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vsubq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vsubq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vorrq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vornq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vsubq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_n_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b) +__arm_vsubq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmvq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vsubq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b) +__arm_vsubq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmavq_fv4sf (__a, __b); + return __builtin_mve_vsubq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmaq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmvq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmavq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmaq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot90_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_veorq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmulq_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcaddq_rot270_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vhaddq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) { - return __builtin_mve_vbicq_fv4sf (__a, __b); + return __builtin_mve_vhaddq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vhaddq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) { - return __builtin_mve_vandq_fv4sf (__a, __b); + return __builtin_mve_vhaddq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b) +__arm_vhaddq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vaddq_n_fv4sf (__a, __b); + return __builtin_mve_vhaddq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vhaddq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { - return __builtin_mve_vabdq_fv4sf (__a, __b); + return __builtin_mve_vhaddq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b) +__arm_vhaddq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b); + return __builtin_mve_vhaddq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) +__arm_vhaddq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); + return __builtin_mve_vhaddq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vhaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vhaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vhaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vhaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p); + return __builtin_mve_vhaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p); + return __builtin_mve_vhaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vhaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p); + return __builtin_mve_vhaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vhaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p); + return __builtin_mve_vhaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +__arm_vhcaddq_rot90_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p); + return __builtin_mve_vhcaddq_rot90_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +__arm_vhcaddq_rot90_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p); + return __builtin_mve_vhcaddq_rot90_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +__arm_vhcaddq_rot90_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p); + return __builtin_mve_vhcaddq_rot90_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +__arm_vhcaddq_rot270_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p); + return __builtin_mve_vhcaddq_rot270_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } - -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vhcaddq_rot270_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtbq_m_f16_f32v8hf (__a, __b, __p); + return __builtin_mve_vhcaddq_rot270_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtbq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhcaddq_rot270_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtbq_m_f32_f16v4sf (__inactive, __a, __p); + return __builtin_mve_vhcaddq_rot270_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vhsubq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvttq_m_f16_f32v8hf (__a, __b, __p); + return __builtin_mve_vhsubq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhsubq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p); + return __builtin_mve_vhsubq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhsubq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vhsubq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmaq_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +__arm_vhsubq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmaq_n_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmasq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +__arm_vhsubq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmasq_n_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +__arm_vhsubq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmsq_fv8hf (__a, __b, __c); + return __builtin_mve_vhsubq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vhsubq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vabsq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vhsubq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vrhaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_m_sv8hi (__inactive, __a, __p); + return __builtin_mve_vrhaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vrhaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_m_sv8hi (__inactive, __a, __p); + return __builtin_mve_vrhaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vrhaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_m_sv8hi (__inactive, __a, __p); + return __builtin_mve_vrhaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vrhaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_from_f_sv8hi (__inactive, __a, __p); + return __builtin_mve_vrhaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p) +__arm_vrhaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p); + return __builtin_mve_vrhaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrhaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vrhaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrmulhq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p); + return __builtin_mve_vrmulhq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrmulhq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p); + return __builtin_mve_vrmulhq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrmulhq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vrmulhq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrmulhq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p); + return __builtin_mve_vrmulhq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrmulhq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p); + return __builtin_mve_vrmulhq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vrmulhq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vnegq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vrmulhq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vandq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vpselq_fv8hf (__a, __b, __p); + return __builtin_mve_vandq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vandq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vandq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vandq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndaq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vandq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vandq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndmq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vandq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vandq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndnq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vandq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vandq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndpq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vandq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vbicq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vbicq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_vbicq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndxq_m_fv8hf (__inactive, __a, __p); + return __builtin_mve_vbicq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vbicq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_vbicq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vbicq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vbicq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vbicq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_vbicq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vbicq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vbicq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vbrsrq_x_n_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_m_fv8hf (__a, __b, __p); + return __builtin_mve_vbrsrq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_veorq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_m_n_fv8hf (__a, __b, __p); + return __builtin_mve_veorq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_veorq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_m_uv8hi (__inactive, __a, __p); + return __builtin_mve_veorq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_veorq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_m_uv8hi (__inactive, __a, __p); + return __builtin_mve_veorq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_veorq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_m_uv8hi (__inactive, __a, __p); + return __builtin_mve_veorq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +__arm_veorq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_from_f_uv8hi (__inactive, __a, __p); + return __builtin_mve_veorq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_veorq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c); + return __builtin_mve_veorq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_vmovlbq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c); + return __builtin_mve_vmovlbq_m_sv16qi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_vmovlbq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c); + return __builtin_mve_vmovlbq_m_sv8hi (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_vmovlbq_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c); + return __builtin_mve_vmovlbq_m_uv16qi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_vmovlbq_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmaq_fv4sf (__a, __b, __c); + return __builtin_mve_vmovlbq_m_uv8hi (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +__arm_vmovltq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmaq_n_fv4sf (__a, __b, __c); + return __builtin_mve_vmovltq_m_sv16qi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmasq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +__arm_vmovltq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmasq_n_fv4sf (__a, __b, __c); + return __builtin_mve_vmovltq_m_sv8hi (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +__arm_vmovltq_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmsq_fv4sf (__a, __b, __c); + return __builtin_mve_vmovltq_m_uv16qi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabsq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vmovltq_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vabsq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vmovltq_m_uv8hi (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vmvnq_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_m_sv4si (__inactive, __a, __p); + return __builtin_mve_vmvnq_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vmvnq_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_m_sv4si (__inactive, __a, __p); + return __builtin_mve_vmvnq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vmvnq_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_m_sv4si (__inactive, __a, __p); + return __builtin_mve_vmvnq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vmvnq_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_from_f_sv4si (__inactive, __a, __p); + return __builtin_mve_vmvnq_m_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p) +__arm_vmvnq_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p); + return __builtin_mve_vmvnq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmvnq_x_u32 (uint32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vmvnq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmvnq_x_n_s16 (const int __imm, mve_pred16_t __p) { - return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p); + return __builtin_mve_vmvnq_m_n_sv8hi (vuninitializedq_s16 (), __imm, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmvnq_x_n_s32 (const int __imm, mve_pred16_t __p) { - return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p); + return __builtin_mve_vmvnq_m_n_sv4si (vuninitializedq_s32 (), __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmvnq_x_n_u16 (const int __imm, mve_pred16_t __p) { - return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vmvnq_m_n_uv8hi (vuninitializedq_u16 (), __imm, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmvnq_x_n_u32 (const int __imm, mve_pred16_t __p) { - return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p); + return __builtin_mve_vmvnq_m_n_uv4si (vuninitializedq_u32 (), __imm, __p); } -__extension__ extern __inline float32_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vornq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p); + return __builtin_mve_vornq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vnegq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vornq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vnegq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vornq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vornq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vpselq_fv4sf (__a, __b, __p); + return __builtin_mve_vornq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vornq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vornq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndaq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vornq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndaq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vornq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndmq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vornq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndmq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vornq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndnq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vorrq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndnq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vorrq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndpq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vorrq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndpq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vorrq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vorrq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vorrq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vrndxq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vorrq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vrndxq_m_fv4sf (__inactive, __a, __p); + return __builtin_mve_vorrq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpeqq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vorrq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpeqq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vorrq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vorrq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vorrq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgeq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vrev16q_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgeq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vrev16q_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrev16q_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vrev16q_m_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpgtq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vrev32q_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpgtq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vrev32q_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrev32q_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vrev32q_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpleq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vrev32q_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpleq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vrev32q_m_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrev32q_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vrev32q_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpltq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vrev64q_x_s8 (int8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpltq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vrev64q_m_sv16qi (vuninitializedq_s8 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrev64q_x_s16 (int16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_m_fv4sf (__a, __b, __p); + return __builtin_mve_vrev64q_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline mve_pred16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmpneq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vrev64q_x_s32 (int32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcmpneq_m_n_fv4sf (__a, __b, __p); + return __builtin_mve_vrev64q_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vrev64q_x_u8 (uint8x16_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtmq_m_uv4si (__inactive, __a, __p); + return __builtin_mve_vrev64q_m_uv16qi (vuninitializedq_u8 (), __a, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtnq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vrev64q_x_u16 (uint16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtnq_m_uv4si (__inactive, __a, __p); + return __builtin_mve_vrev64q_m_uv8hi (vuninitializedq_u16 (), __a, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtpq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vrev64q_x_u32 (uint32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vcvtpq_m_uv4si (__inactive, __a, __p); + return __builtin_mve_vrev64q_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +__arm_vrshlq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p); + return __builtin_mve_vrshlq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p) +__arm_vrshlq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p); + return __builtin_mve_vrshlq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p) +__arm_vrshlq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p); + return __builtin_mve_vrshlq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p) +__arm_vrshlq_x_u8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p); + return __builtin_mve_vrshlq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p) +__arm_vrshlq_x_u16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p); + return __builtin_mve_vrshlq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrshlq_x_u32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vabdq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vrshlq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vabdq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vshllbq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vabdq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vshllbq_m_n_sv16qi (vuninitializedq_s16 (), __a, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vshllbq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vaddq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vshllbq_m_n_sv8hi (vuninitializedq_s32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vshllbq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vaddq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vshllbq_m_n_uv16qi (vuninitializedq_u16 (), __a, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vshllbq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vaddq_m_n_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vshllbq_m_n_uv8hi (vuninitializedq_u32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vshlltq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vaddq_m_n_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vshlltq_m_n_sv16qi (vuninitializedq_s16 (), __a, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vshlltq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vandq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vshlltq_m_n_sv8hi (vuninitializedq_s32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vandq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vshlltq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vandq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vshlltq_m_n_uv16qi (vuninitializedq_u16 (), __a, __imm, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vshlltq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) { - return __builtin_mve_vbicq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vshlltq_m_n_uv8hi (vuninitializedq_u32 (), __a, __imm, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbicq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vshlq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p) { - return __builtin_mve_vbicq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vshlq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_u8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_u16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_u32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrshrq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vrshrq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vshrq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); +} + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst4qv4sf (__addr, __rv.__o); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, int32_t __b, mve_pred16_t __p) +__arm_vrndxq_f32 (float32x4_t __a) { - return __builtin_mve_vbrsrq_m_n_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vrndxq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vbrsrq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, int32_t __b, mve_pred16_t __p) +__arm_vrndq_f16 (float16x8_t __a) { - return __builtin_mve_vbrsrq_m_n_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vrndq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrndq_f32 (float32x4_t __a) { - return __builtin_mve_vcaddq_rot270_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vrndq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrndpq_f16 (float16x8_t __a) { - return __builtin_mve_vcaddq_rot270_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vrndpq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vrndpq_f32 (float32x4_t __a) { - return __builtin_mve_vcaddq_rot90_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vrndpq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcaddq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vrndnq_f16 (float16x8_t __a) { - return __builtin_mve_vcaddq_rot90_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vrndnq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vrndnq_f32 (float32x4_t __a) { - return __builtin_mve_vcmlaq_m_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vrndnq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vrndmq_f16 (float16x8_t __a) { - return __builtin_mve_vcmlaq_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vrndmq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot180_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vrndmq_f32 (float32x4_t __a) { - return __builtin_mve_vcmlaq_rot180_m_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vrndmq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot180_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vrndaq_f16 (float16x8_t __a) { - return __builtin_mve_vcmlaq_rot180_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vrndaq_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot270_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vrndaq_f32 (float32x4_t __a) { - return __builtin_mve_vcmlaq_rot270_m_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vrndaq_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot270_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vrev64q_f16 (float16x8_t __a) { - return __builtin_mve_vcmlaq_rot270_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vrev64q_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot90_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vrev64q_f32 (float32x4_t __a) { - return __builtin_mve_vcmlaq_rot90_m_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vrev64q_fv4sf (__a); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmlaq_rot90_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vnegq_f16 (float16x8_t __a) { - return __builtin_mve_vcmlaq_rot90_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_sv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtq_from_f_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_uv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtnq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_sv4si (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vsubq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vsubq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b) +{ + return __builtin_mve_vbrsrq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv8hf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_f32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_fv4sf (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpneq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpneq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpltq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpltq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpleq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpleq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgtq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpgeq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmpeqq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vsubq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vorrq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vornq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vmulq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vminnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmvq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmavq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vmaxnmaq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_veorq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcmulq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vbicq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vandq_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b) +{ + return __builtin_mve_vaddq_n_fv8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __builtin_mve_vabdq_fv8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpneq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpneq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpltq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpltq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpleq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpleq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgtq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpgeq_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmpeqq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vsubq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vorrq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vornq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vmulq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vminnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmvq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmavq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vmaxnmaq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_veorq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcmulq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vbicq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vandq_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b) +{ + return __builtin_mve_vaddq_n_fv4sf (__a, __b); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_mve_vabdq_fv4sf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b) +{ + return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p); +} + + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcvtbq_m_f16_f32v8hf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtbq_m_f32_f16v4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcvttq_m_f16_f32v8hf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vfmaq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +{ + return __builtin_mve_vfmaq_n_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c) +{ + return __builtin_mve_vfmasq_n_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) +{ + return __builtin_mve_vfmsq_fv8hf (__a, __b, __c); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_sv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndaq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndmq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndnq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndpq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndxq_m_fv8hf (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_fv8hf (__a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_uv8hi (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vfmaq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return __builtin_mve_vfmaq_n_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) +{ + return __builtin_mve_vfmasq_n_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) +{ + return __builtin_mve_vfmsq_fv4sf (__a, __b, __c); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vabsq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_sv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vnegq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vpselq_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndaq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndmq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndnq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndpq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vrndxq_m_fv4sf (__inactive, __a, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpeqq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpeqq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgeq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgeq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpgtq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpgtq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpleq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpleq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpltq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpltq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmpneq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmpneq_m_n_fv4sf (__a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtmq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtnq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtpq_m_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabdq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vabdq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vaddq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vandq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vandq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbicq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbicq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vbrsrq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, int32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vbrsrq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot270_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcaddq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcaddq_rot90_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot180_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot180_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot180_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot270_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot270_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot270_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot90_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmlaq_rot90_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vcmlaq_rot90_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot180_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot180_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot180_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot270_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot270_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot90_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcmulq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vcmulq_rot90_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_s32_f32 (int32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_sv4si (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_s16_f16 (int16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_sv8hi (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_u32_f32 (uint32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_uv4si (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_u16_f16 (uint16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_from_f_uv8hi (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_veorq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_veorq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_n_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmaq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmaq_m_n_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmasq_m_n_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmasq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmasq_m_n_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmsq_m_fv4sf (__a, __b, __c, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmulq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vmulq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vornq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vornq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vorrq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vorrq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_fv4sf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f32 (float32_t const * __base) +{ + return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f16 (float16_t const * __base) +{ + return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_f32 (float32_t const * __base) +{ + return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_f16 (float16_t const * __base) +{ + return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_f16 (float16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_offset_fv8hf((__builtin_neon_hi *) __base, __offset); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_fv8hf((__builtin_neon_hi *) __base, __offset, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_f16 (float16_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_fv8hf (__base, __offset); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_fv8hf (__base, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_f32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_fv4sf (__addr, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_f32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_fv4sf (__addr, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_f32 (float32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_offset_fv4sf((__builtin_neon_si *) __base, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_offset_z_fv4sf((__builtin_neon_si *) __base, __offset, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_f32 (float32_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_fv4sf (__base, __offset); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_p_fv4sf (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_f32 (float32_t * __addr, float32x4_t __value) +{ + __builtin_mve_vstrwq_fv4sf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_f32 (float32_t * __addr, float32x4_t __value) +{ + __builtin_mve_vst1q_fv4sf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_f16 (float16_t * __addr, float16x8_t __value) +{ + __builtin_mve_vst1q_fv8hf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_f16 (float16_t * __addr, float16x8_t __value) +{ + __builtin_mve_vstrhq_fv8hf (__addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_offset_fv8hf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_offset_p_fv8hf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_fv8hf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrhq_scatter_shifted_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrhq_scatter_shifted_offset_p_fv8hf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_fv4sf (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_p_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_base_p_fv4sf (__addr, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_offset_fv4sf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_offset_p_fv4sf (__base, __offset, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_fv4sf (__base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +{ + __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_f16 (float16x8_t __a, float16x8_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __a + __b; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_f16 (void) +{ + float16x8_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vuninitializedq_f32 (void) +{ + float32x4_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_f16 (float16x8_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s32_f32 (float32x4_t __a) +{ + return (int32x4_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_f16 (float16x8_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s16_f32 (float32x4_t __a) +{ + return (int16x8_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_f16 (float16x8_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s64_f32 (float32x4_t __a) +{ + return (int64x2_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_f16 (float16x8_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_s8_f32 (float32x4_t __a) +{ + return (int8x16_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_f16 (float16x8_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u16_f32 (float32x4_t __a) +{ + return (uint16x8_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_f16 (float16x8_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u32_f32 (float32x4_t __a) +{ + return (uint32x4_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_f16 (float16x8_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u64_f32 (float32x4_t __a) +{ + return (uint64x2_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_f16 (float16x8_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_u8_f32 (float32x4_t __a) +{ + return (uint8x16_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_f32 (float32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s16 (int16x8_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s32 (int32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s64 (int64x2_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_s8 (int8x16_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u16 (uint16x8_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u32 (uint32x4_t __a) +{ + return (float16x8_t) __a; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vreinterpretq_f16_u64 (uint64x2_t __a) { - return __builtin_mve_vcmulq_m_fv4sf (__inactive, __a, __b, __p); + return (float16x8_t) __a; } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f16_u8 (uint8x16_t __a) { - return __builtin_mve_vcmulq_m_fv8hf (__inactive, __a, __b, __p); + return (float16x8_t) __a; } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_f16 (float16x8_t __a) { - return __builtin_mve_vcmulq_rot180_m_fv4sf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot180_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_s16 (int16x8_t __a) { - return __builtin_mve_vcmulq_rot180_m_fv8hf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_s32 (int32x4_t __a) { - return __builtin_mve_vcmulq_rot270_m_fv4sf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_s64 (int64x2_t __a) { - return __builtin_mve_vcmulq_rot270_m_fv8hf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_s8 (int8x16_t __a) { - return __builtin_mve_vcmulq_rot90_m_fv4sf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcmulq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vreinterpretq_f32_u16 (uint16x8_t __a) { - return __builtin_mve_vcmulq_rot90_m_fv8hf (__inactive, __a, __b, __p); + return (float32x4_t) __a; } -__extension__ extern __inline int32x4_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_s32_f32 (int32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +__arm_vreinterpretq_f32_u32 (uint32x4_t __a) { - return __builtin_mve_vcvtq_m_n_from_f_sv4si (__inactive, __a, __imm6, __p); + return (float32x4_t) __a; } -__extension__ extern __inline int16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_s16_f16 (int16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +__arm_vreinterpretq_f32_u64 (uint64x2_t __a) { - return __builtin_mve_vcvtq_m_n_from_f_sv8hi (__inactive, __a, __imm6, __p); + return (float32x4_t) __a; } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_u32_f32 (uint32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p) +__arm_vreinterpretq_f32_u8 (uint8x16_t __a) { - return __builtin_mve_vcvtq_m_n_from_f_uv4si (__inactive, __a, __imm6, __p); + return (float32x4_t) __a; } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vcvtq_m_n_u16_f16 (uint16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p) +__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset) { - return __builtin_mve_vcvtq_m_n_from_f_uv8hi (__inactive, __a, __imm6, __p); + float32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset); + __addr += __offset; + return result; } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p) { - return __builtin_mve_veorq_m_fv4sf (__inactive, __a, __b, __p); + float32x4_t + result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p); + __addr += __offset; + return result; } -__extension__ extern __inline float16x8_t +__extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_veorq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value) { - return __builtin_mve_veorq_m_fv8hf (__inactive, __a, __b, __p); + __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value); + __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) { - return __builtin_mve_vfmaq_m_fv4sf (__a, __b, __c, __p); + __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p); + __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vdupq_x_n_f16 (float16_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmaq_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vdupq_m_n_fv8hf (vuninitializedq_f16 (), __a, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +__arm_vdupq_x_n_f32 (float32_t __a, mve_pred16_t __p) { - return __builtin_mve_vfmaq_m_n_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vdupq_m_n_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmaq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +__arm_vminnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmaq_m_n_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vminnmq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmasq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p) +__arm_vminnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmasq_m_n_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vminnmq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmasq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p) +__arm_vmaxnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmasq_m_n_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vmaxnmq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmsq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p) +__arm_vmaxnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmsq_m_fv4sf (__a, __b, __c, __p); + return __builtin_mve_vmaxnmq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p) +__arm_vabdq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p); + return __builtin_mve_vabdq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vabdq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vabdq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vabsq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vabsq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vabsq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vabsq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vaddq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vaddq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vaddq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vaddq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vaddq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vaddq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vaddq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) { - return __builtin_mve_vmulq_m_n_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vaddq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vmulq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vnegq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vmulq_m_n_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vnegq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vnegq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vornq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vnegq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vornq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vmulq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vornq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vmulq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmulq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vorrq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vmulq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vorrq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vmulq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) { - return __builtin_mve_vorrq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vmulq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p) +__arm_vmulq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_m_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vmulq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p) +__arm_vsubq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_m_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vsubq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p) +__arm_vsubq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_m_n_fv4sf (__inactive, __a, __b, __p); + return __builtin_mve_vsubq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p) +__arm_vsubq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p) { - return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); + return __builtin_mve_vsubq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vld1q_f32 (float32_t const * __base) +__arm_vsubq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p) { - return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base); + return __builtin_mve_vsubq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vld1q_f16 (float16_t const * __base) +__arm_vcaddq_rot90_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base); + return __builtin_mve_vcaddq_rot90_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_f32 (float32_t const * __base) +__arm_vcaddq_rot90_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base); + return __builtin_mve_vcaddq_rot90_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p) +__arm_vcaddq_rot270_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p); + return __builtin_mve_vcaddq_rot270_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p) +__arm_vcaddq_rot270_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p); + return __builtin_mve_vcaddq_rot270_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_f16 (float16_t const * __base) +__arm_vcmulq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base); + return __builtin_mve_vcmulq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_gather_offset_f16 (float16_t const * __base, uint16x8_t __offset) +__arm_vcmulq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_gather_offset_fv8hf((__builtin_neon_hi *) __base, __offset); + return __builtin_mve_vcmulq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_gather_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +__arm_vcmulq_rot90_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_gather_offset_z_fv8hf((__builtin_neon_hi *) __base, __offset, __p); + return __builtin_mve_vcmulq_rot90_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_gather_shifted_offset_f16 (float16_t const * __base, uint16x8_t __offset) +__arm_vcmulq_rot90_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_gather_shifted_offset_fv8hf (__base, __offset); + return __builtin_mve_vcmulq_rot90_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrhq_gather_shifted_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p) +__arm_vcmulq_rot180_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrhq_gather_shifted_offset_z_fv8hf (__base, __offset, __p); + return __builtin_mve_vcmulq_rot180_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_base_f32 (uint32x4_t __addr, const int __offset) +__arm_vcmulq_rot180_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_base_fv4sf (__addr, __offset); + return __builtin_mve_vcmulq_rot180_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_base_z_f32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p) +__arm_vcmulq_rot270_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_base_z_fv4sf (__addr, __offset, __p); + return __builtin_mve_vcmulq_rot270_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_offset_f32 (float32_t const * __base, uint32x4_t __offset) +__arm_vcmulq_rot270_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_offset_fv4sf((__builtin_neon_si *) __base, __offset); + return __builtin_mve_vcmulq_rot270_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +__arm_vcvtaq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_offset_z_fv4sf((__builtin_neon_si *) __base, __offset, __p); + return __builtin_mve_vcvtaq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_shifted_offset_f32 (float32_t const * __base, uint32x4_t __offset) +__arm_vcvtaq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_shifted_offset_fv4sf (__base, __offset); + return __builtin_mve_vcvtaq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p) +__arm_vcvtaq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p) { - return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p); + return __builtin_mve_vcvtaq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p) +__arm_vcvtaq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_p_fv4sf (__addr, __value, __p); + return __builtin_mve_vcvtaq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_f32 (float32_t * __addr, float32x4_t __value) +__arm_vcvtnq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_fv4sf (__addr, __value); + return __builtin_mve_vcvtnq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst1q_f32 (float32_t * __addr, float32x4_t __value) +__arm_vcvtnq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vst1q_fv4sf (__addr, __value); + return __builtin_mve_vcvtnq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vst1q_f16 (float16_t * __addr, float16x8_t __value) +__arm_vcvtnq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vst1q_fv8hf (__addr, __value); + return __builtin_mve_vcvtnq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_f16 (float16_t * __addr, float16x8_t __value) +__arm_vcvtnq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_fv8hf (__addr, __value); + return __builtin_mve_vcvtnq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) +__arm_vcvtpq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p); + return __builtin_mve_vcvtpq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_scatter_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +__arm_vcvtpq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_scatter_offset_fv8hf (__base, __offset, __value); + return __builtin_mve_vcvtpq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_scatter_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +__arm_vcvtpq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_scatter_offset_p_fv8hf (__base, __offset, __value, __p); + return __builtin_mve_vcvtpq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_scatter_shifted_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value) +__arm_vcvtpq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_scatter_shifted_offset_fv8hf (__base, __offset, __value); + return __builtin_mve_vcvtpq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrhq_scatter_shifted_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p) +__arm_vcvtmq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrhq_scatter_shifted_offset_p_fv8hf (__base, __offset, __value, __p); + return __builtin_mve_vcvtmq_m_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_base_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value) +__arm_vcvtmq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_fv4sf (__addr, __offset, __value); + return __builtin_mve_vcvtmq_m_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_base_p_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) +__arm_vcvtmq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_p_fv4sf (__addr, __offset, __value, __p); + return __builtin_mve_vcvtmq_m_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +__arm_vcvtmq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_offset_fv4sf (__base, __offset, __value); + return __builtin_mve_vcvtmq_m_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +__arm_vcvtbq_x_f32_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_offset_p_fv4sf (__base, __offset, __value, __p); + return __builtin_mve_vcvtbq_m_f32_f16v4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_shifted_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value) +__arm_vcvttq_x_f32_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_shifted_offset_fv4sf (__base, __offset, __value); + return __builtin_mve_vcvttq_m_f32_f16v4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p) +__arm_vcvtq_x_f16_u16 (uint16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p); + return __builtin_mve_vcvtq_m_to_f_uv8hf (vuninitializedq_f16 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_f16 (float16x8_t __a, float16x8_t __b) +__arm_vcvtq_x_f16_s16 (int16x8_t __a, mve_pred16_t __p) { - return __a + __b; + return __builtin_mve_vcvtq_m_to_f_sv8hf (vuninitializedq_f16 (), __a, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_f32 (float32x4_t __a, float32x4_t __b) +__arm_vcvtq_x_f32_s32 (int32x4_t __a, mve_pred16_t __p) { - return __a + __b; + return __builtin_mve_vcvtq_m_to_f_sv4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_f16 (void) +__arm_vcvtq_x_f32_u32 (uint32x4_t __a, mve_pred16_t __p) { - float16x8_t __uninit; - __asm__ ("": "=w" (__uninit)); - return __uninit; + return __builtin_mve_vcvtq_m_to_f_uv4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_f32 (void) +__arm_vcvtq_x_n_f16_s16 (int16x8_t __a, const int __imm6, mve_pred16_t __p) { - float32x4_t __uninit; - __asm__ ("": "=w" (__uninit)); - return __uninit; + return __builtin_mve_vcvtq_m_n_to_f_sv8hf (vuninitializedq_f16 (), __a, __imm6, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_f16 (float16x8_t __a) +__arm_vcvtq_x_n_f16_u16 (uint16x8_t __a, const int __imm6, mve_pred16_t __p) { - return (int32x4_t) __a; + return __builtin_mve_vcvtq_m_n_to_f_uv8hf (vuninitializedq_f16 (), __a, __imm6, __p); } -__extension__ extern __inline int32x4_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_f32 (float32x4_t __a) +__arm_vcvtq_x_n_f32_s32 (int32x4_t __a, const int __imm6, mve_pred16_t __p) { - return (int32x4_t) __a; + return __builtin_mve_vcvtq_m_n_to_f_sv4sf (vuninitializedq_f32 (), __a, __imm6, __p); } -__extension__ extern __inline int16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_f16 (float16x8_t __a) +__arm_vcvtq_x_n_f32_u32 (uint32x4_t __a, const int __imm6, mve_pred16_t __p) { - return (int16x8_t) __a; + return __builtin_mve_vcvtq_m_n_to_f_uv4sf (vuninitializedq_f32 (), __a, __imm6, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_f32 (float32x4_t __a) +__arm_vcvtq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p) { - return (int16x8_t) __a; + return __builtin_mve_vcvtq_m_from_f_sv8hi (vuninitializedq_s16 (), __a, __p); } -__extension__ extern __inline int64x2_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_f16 (float16x8_t __a) +__arm_vcvtq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p) { - return (int64x2_t) __a; + return __builtin_mve_vcvtq_m_from_f_sv4si (vuninitializedq_s32 (), __a, __p); } -__extension__ extern __inline int64x2_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_f32 (float32x4_t __a) +__arm_vcvtq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p) { - return (int64x2_t) __a; + return __builtin_mve_vcvtq_m_from_f_uv8hi (vuninitializedq_u16 (), __a, __p); } -__extension__ extern __inline int8x16_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_f16 (float16x8_t __a) +__arm_vcvtq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p) { - return (int8x16_t) __a; + return __builtin_mve_vcvtq_m_from_f_uv4si (vuninitializedq_u32 (), __a, __p); } -__extension__ extern __inline int8x16_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_f32 (float32x4_t __a) +__arm_vcvtq_x_n_s16_f16 (float16x8_t __a, const int __imm6, mve_pred16_t __p) { - return (int8x16_t) __a; + return __builtin_mve_vcvtq_m_n_from_f_sv8hi (vuninitializedq_s16 (), __a, __imm6, __p); } -__extension__ extern __inline uint16x8_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_f16 (float16x8_t __a) +__arm_vcvtq_x_n_s32_f32 (float32x4_t __a, const int __imm6, mve_pred16_t __p) { - return (uint16x8_t) __a; + return __builtin_mve_vcvtq_m_n_from_f_sv4si (vuninitializedq_s32 (), __a, __imm6, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_f32 (float32x4_t __a) +__arm_vcvtq_x_n_u16_f16 (float16x8_t __a, const int __imm6, mve_pred16_t __p) { - return (uint16x8_t) __a; + return __builtin_mve_vcvtq_m_n_from_f_uv8hi (vuninitializedq_u16 (), __a, __imm6, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_f16 (float16x8_t __a) +__arm_vcvtq_x_n_u32_f32 (float32x4_t __a, const int __imm6, mve_pred16_t __p) { - return (uint32x4_t) __a; + return __builtin_mve_vcvtq_m_n_from_f_uv4si (vuninitializedq_u32 (), __a, __imm6, __p); } -__extension__ extern __inline uint32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_f32 (float32x4_t __a) +__arm_vrndq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (uint32x4_t) __a; + return __builtin_mve_vrndq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_f16 (float16x8_t __a) +__arm_vrndq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (uint64x2_t) __a; + return __builtin_mve_vrndq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_f32 (float32x4_t __a) +__arm_vrndnq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (uint64x2_t) __a; + return __builtin_mve_vrndnq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline uint8x16_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_f16 (float16x8_t __a) +__arm_vrndnq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (uint8x16_t) __a; + return __builtin_mve_vrndnq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } -__extension__ extern __inline uint8x16_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_f32 (float32x4_t __a) +__arm_vrndmq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (uint8x16_t) __a; + return __builtin_mve_vrndmq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_f32 (float32x4_t __a) +__arm_vrndmq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndmq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s16 (int16x8_t __a) +__arm_vrndpq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndpq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s32 (int32x4_t __a) +__arm_vrndpq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndpq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s64 (int64x2_t __a) +__arm_vrndaq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndaq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s8 (int8x16_t __a) +__arm_vrndaq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndaq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u16 (uint16x8_t __a) +__arm_vrndxq_x_f16 (float16x8_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndxq_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u32 (uint32x4_t __a) +__arm_vrndxq_x_f32 (float32x4_t __a, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vrndxq_m_fv4sf (vuninitializedq_f32 (), __a, __p); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u64 (uint64x2_t __a) +__arm_vandq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vandq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } -__extension__ extern __inline float16x8_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u8 (uint8x16_t __a) +__arm_vandq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return (float16x8_t) __a; + return __builtin_mve_vandq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_f16 (float16x8_t __a) +__arm_vbicq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vbicq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s16 (int16x8_t __a) +__arm_vbicq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vbicq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s32 (int32x4_t __a) +__arm_vbrsrq_x_n_f16 (float16x8_t __a, int32_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vbrsrq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s64 (int64x2_t __a) +__arm_vbrsrq_x_n_f32 (float32x4_t __a, int32_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vbrsrq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s8 (int8x16_t __a) +__arm_veorq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_veorq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u16 (uint16x8_t __a) +__arm_veorq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_veorq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u32 (uint32x4_t __a) +__arm_vornq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vornq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u64 (uint64x2_t __a) +__arm_vornq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vornq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u8 (uint8x16_t __a) +__arm_vorrq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p) { - return (float32x4_t) __a; + return __builtin_mve_vorrq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset) +__arm_vorrq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p) { - float32x4_t - result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset); - __addr += __offset; - return result; + return __builtin_mve_vorrq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p); } -__extension__ extern __inline float32x4_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p) +__arm_vrev32q_x_f16 (float16x8_t __a, mve_pred16_t __p) { - float32x4_t - result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p); - __addr += __offset; - return result; + return __builtin_mve_vrev32q_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value) +__arm_vrev64q_x_f16 (float16x8_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value); - __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr); + return __builtin_mve_vrev64q_m_fv8hf (vuninitializedq_f16 (), __a, __p); } -__extension__ extern __inline void +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) +__arm_vrev64q_x_f32 (float32x4_t __a, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p); - __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p); + return __builtin_mve_vrev64q_m_fv4sf (vuninitializedq_f32 (), __a, __p); } #endif @@ -18069,30 +21113,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vdupq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vdupq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) -#define vfmaq_n(p0,p1,p2) __arm_vfmaq_n(p0,p1,p2) -#define __arm_vfmaq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));}) - #define vfmaq(p0,p1,p2) __arm_vfmaq(p0,p1,p2) #define __arm_vfmaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) -#define vfmasq_n(p0,p1,p2) __arm_vfmasq_n(p0,p1,p2) -#define __arm_vfmasq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - __typeof(p2) __p2 = (p2); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));}) - #define vfmsq(p0,p1,p2) __arm_vfmsq(p0,p1,p2) #define __arm_vfmsq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -18101,6 +21131,14 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmsq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmsq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) +#define vfmasq(p0,p1,p2) __arm_vfmasq(p0,p1,p2) +#define __arm_vfmasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));}) + #define vmaxnmaq_m(p0,p1,p2) __arm_vmaxnmaq_m(p0,p1,p2) #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -19154,6 +22192,306 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_wb_p_f32 (p0, p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) +#define vabdq_x(p1,p2,p3) __arm_vabdq_x(p1,p2,p3) +#define __arm_vabdq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vabsq_x(p1,p2) __arm_vabsq_x(p1,p2) +#define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vaddq_x(p1,p2,p3) __arm_vaddq_x(p1,p2,p3) +#define __arm_vaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) + +#define vandq_x(p1,p2,p3) __arm_vandq_x(p1,p2,p3) +#define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vbicq_x(p1,p2,p3) __arm_vbicq_x(p1,p2,p3) +#define __arm_vbicq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vbrsrq_x(p1,p2,p3) __arm_vbrsrq_x(p1,p2,p3) +#define __arm_vbrsrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2, p3));}) + +#define vcaddq_rot270_x(p1,p2,p3) __arm_vcaddq_rot270_x(p1,p2,p3) +#define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcaddq_rot90_x(p1,p2,p3) __arm_vcaddq_rot90_x(p1,p2,p3) +#define __arm_vcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmulq_rot180_x(p1,p2,p3) __arm_vcmulq_rot180_x(p1,p2,p3) +#define __arm_vcmulq_rot180_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmulq_rot270_x(p1,p2,p3) __arm_vcmulq_rot270_x(p1,p2,p3) +#define __arm_vcmulq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcmulq_x(p1,p2,p3) __arm_vcmulq_x(p1,p2,p3) +#define __arm_vcmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vcvtq_x(p1,p2) __arm_vcvtq_x(p1,p2) +#define __arm_vcvtq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_x_f16_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_x_f32_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_x_f16_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_x_f32_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vcvtq_x_n(p1,p2,p3) __arm_vcvtq_x_n(p1,p2,p3) +#define __arm_vcvtq_x_n(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_x_n_f16_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_x_n_f32_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_x_n_f16_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_x_n_f32_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define veorq_x(p1,p2,p3) __arm_veorq_x(p1,p2,p3) +#define __arm_veorq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_x_s8(__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_x_s16(__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_x_s32(__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vmaxnmq_x(p1,p2,p3) __arm_vmaxnmq_x(p1,p2,p3) +#define __arm_vmaxnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vminnmq_x(p1,p2,p3) __arm_vminnmq_x(p1,p2,p3) +#define __arm_vminnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vmulq_x(p1,p2,p3) __arm_vmulq_x(p1,p2,p3) +#define __arm_vmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) + +#define vnegq_x(p1,p2) __arm_vnegq_x(p1,p2) +#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vornq_x(p1,p2,p3) __arm_vornq_x(p1,p2,p3) +#define __arm_vornq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vorrq_x(p1,p2,p3) __arm_vorrq_x(p1,p2,p3) +#define __arm_vorrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + +#define vrev32q_x(p1,p2) __arm_vrev32q_x(p1,p2) +#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2));}) + +#define vrev64q_x(p1,p2) __arm_vrev64q_x(p1,p2) +#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndaq_x(p1,p2) __arm_vrndaq_x(p1,p2) +#define __arm_vrndaq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndmq_x(p1,p2) __arm_vrndmq_x(p1,p2) +#define __arm_vrndmq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndnq_x(p1,p2) __arm_vrndnq_x(p1,p2) +#define __arm_vrndnq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndpq_x(p1,p2) __arm_vrndpq_x(p1,p2) +#define __arm_vrndpq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndq_x(p1,p2) __arm_vrndq_x(p1,p2) +#define __arm_vrndq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vrndxq_x(p1,p2) __arm_vrndxq_x(p1,p2) +#define __arm_vrndxq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vsubq_x(p1,p2,p3) __arm_vsubq_x(p1,p2,p3) +#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));}) + +#define vcmulq_rot90_x(p1,p2,p3) __arm_vcmulq_rot90_x(p1,p2,p3) +#define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));}) + #else /* MVE Integer. */ #define vstrwq_scatter_base_wb(p0,p1,p2) __arm_vstrwq_scatter_base_wb(p0,p1,p2) @@ -21648,8 +24986,509 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) +#define vabsq_x(p1,p2) __arm_vabsq_x(p1,p2) +#define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vaddq_x(p1,p2,p3) __arm_vaddq_x(p1,p2,p3) +#define __arm_vaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + +#define vcaddq_rot270_x(p1,p2,p3) __arm_vcaddq_rot270_x(p1,p2,p3) +#define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vcaddq_rot90_x(p1,p2,p3) __arm_vcaddq_rot90_x(p1,p2,p3) +#define __arm_vcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define veorq_x(p1,p2,p3) __arm_veorq_x(p1,p2,p3) +#define __arm_veorq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_x_s8(__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_x_s16(__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_x_s32(__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmaxq_x(p1,p2,p3) __arm_vmaxq_x(p1,p2,p3) +#define __arm_vmaxq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vminq_x(p1,p2,p3) __arm_vminq_x(p1,p2,p3) +#define __arm_vminq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmovlbq_x(p1,p2) __arm_vmovlbq_x(p1,p2) +#define __arm_vmovlbq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vmovltq_x(p1,p2) __arm_vmovltq_x(p1,p2) +#define __arm_vmovltq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vmulhq_x(p1,p2,p3) __arm_vmulhq_x(p1,p2,p3) +#define __arm_vmulhq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmullbq_int_x(p1,p2,p3) __arm_vmullbq_int_x(p1,p2,p3) +#define __arm_vmullbq_int_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmullbq_poly_x(p1,p2,p3) __arm_vmullbq_poly_x(p1,p2,p3) +#define __arm_vmullbq_poly_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_x_p8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_x_p16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + +#define vmulltq_int_x(p1,p2,p3) __arm_vmulltq_int_x(p1,p2,p3) +#define __arm_vmulltq_int_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vmulltq_poly_x(p1,p2,p3) __arm_vmulltq_poly_x(p1,p2,p3) +#define __arm_vmulltq_poly_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_x_p8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_x_p16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));}) + +#define vmulq_x(p1,p2,p3) __arm_vmulq_x(p1,p2,p3) +#define __arm_vmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + +#define vnegq_x(p1,p2) __arm_vnegq_x(p1,p2) +#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vornq_x(p1,p2,p3) __arm_vornq_x(p1,p2,p3) +#define __arm_vornq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vorrq_x(p1,p2,p3) __arm_vorrq_x(p1,p2,p3) +#define __arm_vorrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrev32q_x(p1,p2) __arm_vrev32q_x(p1,p2) +#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));}) + +#define vrev64q_x(p1,p2) __arm_vrev64q_x(p1,p2) +#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vabdq_x(p1,p2,p3) __arm_vabdq_x(p1,p2,p3) +#define __arm_vabdq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vandq_x(p1,p2,p3) __arm_vandq_x(p1,p2,p3) +#define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vbicq_x(p1,p2,p3) __arm_vbicq_x(p1,p2,p3) +#define __arm_vbicq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vbrsrq_x(p1,p2,p3) __arm_vbrsrq_x(p1,p2,p3) +#define __arm_vbrsrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + #endif /* MVE Integer. */ +#define vmvnq_x(p1,p2) __arm_vmvnq_x(p1,p2) +#define __arm_vmvnq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vrev16q_x(p1,p2) __arm_vrev16q_x(p1,p2) +#define __arm_vrev16q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2));}) + +#define vrhaddq_x(p1,p2,p3) __arm_vrhaddq_x(p1,p2,p3) +#define __arm_vrhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vshlq_x(p0,p1,p2,p3) __arm_vshlq_x(p0,p1,p2,p3) +#define __arm_vshlq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vrmulhq_x(p1,p2,p3) __arm_vrmulhq_x(p1,p2,p3) +#define __arm_vrmulhq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vrshlq_x(p1,p2,p3) __arm_vrshlq_x(p1,p2,p3) +#define __arm_vrshlq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vrshrq_x(p1,p2,p3) __arm_vrshrq_x(p1,p2,p3) +#define __arm_vrshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vshllbq_x(p1,p2,p3) __arm_vshllbq_x(p1,p2,p3) +#define __arm_vshllbq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vshlltq_x(p1,p2,p3) __arm_vshlltq_x(p1,p2,p3) +#define __arm_vshlltq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) + +#define vshlq_x_n(p1,p2,p3) __arm_vshlq_x_n(p1,p2,p3) +#define __arm_vshlq_x_n(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vdwdupq_x_u8(p1,p2,p3,p4) __arm_vdwdupq_x_u8(p1,p2,p3,p4) +#define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define vdwdupq_x_u16(p1,p2,p3,p4) __arm_vdwdupq_x_u16(p1,p2,p3,p4) +#define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define vdwdupq_x_u32(p1,p2,p3,p4) __arm_vdwdupq_x_u32(p1,p2,p3,p4) +#define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define viwdupq_x_u8(p1,p2,p3,p4) __arm_viwdupq_x_u8(p1,p2,p3,p4) +#define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define viwdupq_x_u16(p1,p2,p3,p4) __arm_viwdupq_x_u16(p1,p2,p3,p4) +#define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define viwdupq_x_u32(p1,p2,p3,p4) __arm_viwdupq_x_u32(p1,p2,p3,p4) +#define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) + +#define vidupq_x_u8(p1,p2,p3) __arm_vidupq_x_u8(p1,p2,p3) +#define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vddupq_x_u8(p1,p2,p3) __arm_vddupq_x_u8(p1,p2,p3) +#define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vidupq_x_u16(p1,p2,p3) __arm_vidupq_x_u16(p1,p2,p3) +#define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vddupq_x_u16(p1,p2,p3) __arm_vddupq_x_u16(p1,p2,p3) +#define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vidupq_x_u32(p1,p2,p3) __arm_vidupq_x_u32(p1,p2,p3) +#define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vddupq_x_u32(p1,p2,p3) __arm_vddupq_x_u32(p1,p2,p3) +#define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) + +#define vhaddq_x(p1,p2,p3) __arm_vhaddq_x(p1,p2,p3) +#define vshrq_x(p1,p2,p3) __arm_vshrq_x(p1,p2,p3) +#define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vhcaddq_rot270_x(p1,p2,p3) __arm_vhcaddq_rot270_x(p1,p2,p3) +#define __arm_vhcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vhcaddq_rot90_x(p1,p2,p3) __arm_vhcaddq_rot90_x(p1,p2,p3) +#define __arm_vhcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vhsubq_x(p1,p2,p3) __arm_vhsubq_x(p1,p2,p3) +#define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vclsq_x(p1,p2) __arm_vclsq_x(p1,p2) +#define __arm_vclsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));}) + +#define vclzq_x(p1,p2) __arm_vclzq_x(p1,p2) +#define __arm_vclzq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vadciq(p0,p1,p2) __arm_vadciq(p0,p1,p2) +#define __arm_vadciq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadciq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadciq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #define vstrdq_scatter_base_wb_p(p0,p1,p2,p3) __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3) #define __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 11b7afb..adf53b3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,382 @@ 2020-03-20 Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. + +2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c new file mode 100644 index 0000000..2663db2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vabdq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c new file mode 100644 index 0000000..0a5eb5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vabdq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c new file mode 100644 index 0000000..3dd5e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vabdq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c new file mode 100644 index 0000000..9b1f30f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vabdq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c new file mode 100644 index 0000000..0e386b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vabdq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c new file mode 100644 index 0000000..ff7599a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vabdq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c new file mode 100644 index 0000000..d93c080 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vabdq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c new file mode 100644 index 0000000..73f89e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vabdq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabdt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vabdq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c new file mode 100644 index 0000000..4fb74a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vabsq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vabsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c new file mode 100644 index 0000000..2bad3c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vabsq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vabsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c new file mode 100644 index 0000000..84c0a8a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vabsq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vabsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c new file mode 100644 index 0000000..cf427a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vabsq_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vabsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c new file mode 100644 index 0000000..a3fa974 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vabsq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vabst.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vabsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c new file mode 100644 index 0000000..ec3a85d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vaddq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c new file mode 100644 index 0000000..b9b216c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vaddq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c new file mode 100644 index 0000000..2e65cbf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vaddq_x_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c new file mode 100644 index 0000000..11243a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vaddq_x_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c new file mode 100644 index 0000000..0ef9afd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vaddq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c new file mode 100644 index 0000000..20b88a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vaddq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c new file mode 100644 index 0000000..2bc9072 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vaddq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c new file mode 100644 index 0000000..9e3ffb4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vaddq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c new file mode 100644 index 0000000..ab5140e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vaddq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c new file mode 100644 index 0000000..0bdc00d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vaddq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c new file mode 100644 index 0000000..c33c5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c new file mode 100644 index 0000000..4581190 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c new file mode 100644 index 0000000..1aa65c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c new file mode 100644 index 0000000..eef9acc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c new file mode 100644 index 0000000..e8e430b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c new file mode 100644 index 0000000..1b77145 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vaddt.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c new file mode 100644 index 0000000..357e4b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vandq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c new file mode 100644 index 0000000..0e6cdf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vandq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c new file mode 100644 index 0000000..c18a19e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vandq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c new file mode 100644 index 0000000..3509dc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vandq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c new file mode 100644 index 0000000..a4f0eec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vandq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c new file mode 100644 index 0000000..e85c5bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vandq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c new file mode 100644 index 0000000..89430be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vandq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c new file mode 100644 index 0000000..ab074c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vandq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vandt" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vandq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c new file mode 100644 index 0000000..12036af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vbicq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c new file mode 100644 index 0000000..784653f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vbicq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c new file mode 100644 index 0000000..b0b34ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vbicq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c new file mode 100644 index 0000000..c023cfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vbicq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c new file mode 100644 index 0000000..3355dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vbicq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c new file mode 100644 index 0000000..abdcf00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vbicq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c new file mode 100644 index 0000000..2aa34c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vbicq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c new file mode 100644 index 0000000..26c9e2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vbicq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbict" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vbicq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c new file mode 100644 index 0000000..282837a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +float16x8_t +foo1 (float16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c new file mode 100644 index 0000000..74ef4e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +float32x4_t +foo1 (float32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c new file mode 100644 index 0000000..7f9dc4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c new file mode 100644 index 0000000..4a4ffde --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c new file mode 100644 index 0000000..db1f6ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c new file mode 100644 index 0000000..1bce070 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c new file mode 100644 index 0000000..6e059c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c new file mode 100644 index 0000000..aed3136 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) +{ + return vbrsrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vbrsrt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c new file mode 100644 index 0000000..60a96ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c new file mode 100644 index 0000000..b79e7d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c new file mode 100644 index 0000000..efc5820 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c new file mode 100644 index 0000000..25cf2ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c new file mode 100644 index 0000000..8dbdf13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c new file mode 100644 index 0000000..13d9aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c new file mode 100644 index 0000000..887133e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c new file mode 100644 index 0000000..e23cbab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c new file mode 100644 index 0000000..2c96c2a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c new file mode 100644 index 0000000..6ed2793 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c new file mode 100644 index 0000000..9983bae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c new file mode 100644 index 0000000..658763c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c new file mode 100644 index 0000000..a63dbe6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c new file mode 100644 index 0000000..e256cba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c new file mode 100644 index 0000000..9361a98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c new file mode 100644 index 0000000..0664c6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcaddt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c new file mode 100644 index 0000000..e956fe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vclsq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vclsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c new file mode 100644 index 0000000..cc00379 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vclsq_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vclsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c new file mode 100644 index 0000000..262e04c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vclsq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclst.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vclsq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c new file mode 100644 index 0000000..782d385 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vclzq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c new file mode 100644 index 0000000..cb96176 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vclzq_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c new file mode 100644 index 0000000..ee7ab8f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vclzq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c new file mode 100644 index 0000000..d4074ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vclzq_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c new file mode 100644 index 0000000..9711269 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vclzq_x_u32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c new file mode 100644 index 0000000..baa8eddc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vclzq_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vclzt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vclzq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c new file mode 100644 index 0000000..caed477 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot180_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot180_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c new file mode 100644 index 0000000..21814ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot180_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot180_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c new file mode 100644 index 0000000..14f9391 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot270_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c new file mode 100644 index 0000000..af20dfc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot270_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c new file mode 100644 index 0000000..a7fd380 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot90_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c new file mode 100644 index 0000000..6730cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot90_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c new file mode 100644 index 0000000..18d3217 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vcmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c new file mode 100644 index 0000000..7162f49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vcmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c new file mode 100644 index 0000000..ed4a0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_x_s16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c new file mode 100644 index 0000000..be969ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_x_s32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c new file mode 100644 index 0000000..93038e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtaq_x_u16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c new file mode 100644 index 0000000..421f238 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtaq_x_u32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c new file mode 100644 index 0000000..98e15cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtbq_x_f32_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c new file mode 100644 index 0000000..b017c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_x_s16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c new file mode 100644 index 0000000..8e5e73c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_x_s32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c new file mode 100644 index 0000000..a747745 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtmq_x_u16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c new file mode 100644 index 0000000..7863427 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtmq_x_u32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c new file mode 100644 index 0000000..b2b7230 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_x_s16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c new file mode 100644 index 0000000..e9f2fad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_x_s32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c new file mode 100644 index 0000000..0556618 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtnq_x_u16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c new file mode 100644 index 0000000..967bfb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtnq_x_u32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c new file mode 100644 index 0000000..7ffe464 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_x_s16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c new file mode 100644 index 0000000..0fe3380 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_x_s32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c new file mode 100644 index 0000000..77fd34c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtpq_x_u16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c new file mode 100644 index 0000000..369c941 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtpq_x_u32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c new file mode 100644 index 0000000..3c97d6e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_f16_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + +float16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vcvtq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c new file mode 100644 index 0000000..14ca8c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_f16_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + +float16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c new file mode 100644 index 0000000..b851d91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_f32_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + +float32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vcvtq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c new file mode 100644 index 0000000..4c44257 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_f32_u32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + +float32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c new file mode 100644 index 0000000..63d6cc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n_f16_s16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + +float16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c new file mode 100644 index 0000000..13cf17d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n_f16_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + +float16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c new file mode 100644 index 0000000..630d3bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n_f32_s32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + +float32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c new file mode 100644 index 0000000..5d64fec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n_f32_u32 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + +float32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c new file mode 100644 index 0000000..1b053fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n_s16_f16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c new file mode 100644 index 0000000..2cc8f74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n_s32_f32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c new file mode 100644 index 0000000..a555791 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_n_u16_f16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c new file mode 100644 index 0000000..5a8c22d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_n_u32_f32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c new file mode 100644 index 0000000..de29fce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_s16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c new file mode 100644 index 0000000..312254e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_s32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c new file mode 100644 index 0000000..de6305e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvtq_x_u16_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c new file mode 100644 index 0000000..1e1ab55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vcvtq_x_u32_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c new file mode 100644 index 0000000..1409012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vcvttq_x_f32_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c new file mode 100644 index 0000000..e110510 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c new file mode 100644 index 0000000..5915ab8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_n_u32 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_u32 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c new file mode 100644 index 0000000..7973f45 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_n_u8 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vddupq_x_u8 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c new file mode 100644 index 0000000..348cd58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t *a; + +uint16x8_t +foo (mve_pred16_t p) +{ + return vddupq_x_wb_u16 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ + +uint16x8_t +foo1 (mve_pred16_t p) +{ + return vddupq_x_u16 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c new file mode 100644 index 0000000..c8d664d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t *a; + +uint32x4_t +foo (mve_pred16_t p) +{ + return vddupq_x_wb_u32 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ + +uint32x4_t +foo1 (mve_pred16_t p) +{ + return vddupq_x_u32 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c new file mode 100644 index 0000000..74fea79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t *a; + +uint8x16_t +foo (mve_pred16_t p) +{ + return vddupq_x_wb_u8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ + +uint8x16_t +foo1 (mve_pred16_t p) +{ + return vddupq_x_u8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vddupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c new file mode 100644 index 0000000..b738c2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t a, mve_pred16_t p) +{ + return vdupq_x_n_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c new file mode 100644 index 0000000..2c7e49c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t a, mve_pred16_t p) +{ + return vdupq_x_n_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c new file mode 100644 index 0000000..43cda91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t a, mve_pred16_t p) +{ + return vdupq_x_n_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c new file mode 100644 index 0000000..b57fe6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t a, mve_pred16_t p) +{ + return vdupq_x_n_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c new file mode 100644 index 0000000..89c13c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t a, mve_pred16_t p) +{ + return vdupq_x_n_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c new file mode 100644 index 0000000..edadfca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t a, mve_pred16_t p) +{ + return vdupq_x_n_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c new file mode 100644 index 0000000..a4b4874 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, mve_pred16_t p) +{ + return vdupq_x_n_u32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c new file mode 100644 index 0000000..cfbf97d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t a, mve_pred16_t p) +{ + return vdupq_x_n_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdupt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c new file mode 100644 index 0000000..9969ae3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_n_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c new file mode 100644 index 0000000..ae56387 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_n_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c new file mode 100644 index 0000000..ee29159 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_n_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c new file mode 100644 index 0000000..4e3c1bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_wb_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c new file mode 100644 index 0000000..0988b07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_wb_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c new file mode 100644 index 0000000..5708947 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_wb_u8 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return vdwdupq_x_u8 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vdwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c new file mode 100644 index 0000000..bbabc07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return veorq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c new file mode 100644 index 0000000..577df0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return veorq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c new file mode 100644 index 0000000..88ba5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return veorq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c new file mode 100644 index 0000000..bea7870 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return veorq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c new file mode 100644 index 0000000..23bb971 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return veorq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c new file mode 100644 index 0000000..30f5268 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return veorq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c new file mode 100644 index 0000000..9122574 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return veorq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c new file mode 100644 index 0000000..c5babd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return veorq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return veorq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "veort" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c index 09c927a..3af3d61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c @@ -16,7 +16,7 @@ foo (float16x8_t a, float16x8_t b, float16_t c) float16x8_t foo1 (float16x8_t a, float16x8_t b, float16_t c) { - return vfmaq_n (a, b, c); + return vfmaq (a, b, c); } /* { dg-final { scan-assembler "vfma.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c index ad3b7c4..b6a9205 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c @@ -16,7 +16,7 @@ foo (float32x4_t a, float32x4_t b, float32_t c) float32x4_t foo1 (float32x4_t a, float32x4_t b, float32_t c) { - return vfmaq_n (a, b, c); + return vfmaq (a, b, c); } /* { dg-final { scan-assembler "vfma.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c index 30e797e..358faf6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c @@ -16,7 +16,7 @@ foo (float16x8_t a, float16x8_t b, float16_t c) float16x8_t foo1 (float16x8_t a, float16x8_t b, float16_t c) { - return vfmasq_n (a, b, c); + return vfmasq (a, b, c); } /* { dg-final { scan-assembler "vfmas.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c index 14a45a6..02ca854 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c @@ -16,7 +16,7 @@ foo (float32x4_t a, float32x4_t b, float32_t c) float32x4_t foo1 (float32x4_t a, float32x4_t b, float32_t c) { - return vfmasq_n (a, b, c); + return vfmasq (a, b, c); } /* { dg-final { scan-assembler "vfmas.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c new file mode 100644 index 0000000..3e27bf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhaddq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c new file mode 100644 index 0000000..8ae4f7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhaddq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c new file mode 100644 index 0000000..0c46b82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhaddq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c new file mode 100644 index 0000000..c4814d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhaddq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c new file mode 100644 index 0000000..f8658e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhaddq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c new file mode 100644 index 0000000..b69445b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhaddq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c new file mode 100644 index 0000000..1c54a33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhaddq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c new file mode 100644 index 0000000..9fd4305 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhaddq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c new file mode 100644 index 0000000..69f14a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhaddq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c new file mode 100644 index 0000000..010bfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhaddq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c new file mode 100644 index 0000000..a593126 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhaddq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c new file mode 100644 index 0000000..28784b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhaddq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c new file mode 100644 index 0000000..bfb3549 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c new file mode 100644 index 0000000..cbbcd41 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c new file mode 100644 index 0000000..0a06cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot270_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c new file mode 100644 index 0000000..d7807cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c new file mode 100644 index 0000000..a55e53c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c new file mode 100644 index 0000000..438c9da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhcaddq_rot90_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c new file mode 100644 index 0000000..d6d0458 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhsubq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c new file mode 100644 index 0000000..ff949c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhsubq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c new file mode 100644 index 0000000..c322cd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhsubq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c new file mode 100644 index 0000000..d43080b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhsubq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c new file mode 100644 index 0000000..c814784 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhsubq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c new file mode 100644 index 0000000..b2597470 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhsubq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c new file mode 100644 index 0000000..fff5b54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhsubq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c new file mode 100644 index 0000000..811548f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhsubq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c new file mode 100644 index 0000000..a8e05be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhsubq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c new file mode 100644 index 0000000..c01cfe0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhsubq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c new file mode 100644 index 0000000..21d5a1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhsubq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c new file mode 100644 index 0000000..51811e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhsubq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vhsubt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vhsubq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c new file mode 100644 index 0000000..f1bd060 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_n_u16 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_u16 (a, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c new file mode 100644 index 0000000..497f932 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_n_u32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_u32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c new file mode 100644 index 0000000..eafe983 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_n_u8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, mve_pred16_t p) +{ + return vidupq_x_u8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c new file mode 100644 index 0000000..97dc350 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t *a; + +uint16x8_t +foo (mve_pred16_t p) +{ + return vidupq_x_wb_u16 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ + +uint16x8_t +foo1 (mve_pred16_t p) +{ + return vidupq_x_u16 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c new file mode 100644 index 0000000..b21be73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t *a; + +uint32x4_t +foo (mve_pred16_t p) +{ + return vidupq_x_wb_u32 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ + +uint32x4_t +foo1 (mve_pred16_t p) +{ + return vidupq_x_u32 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c new file mode 100644 index 0000000..239d04e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t * a; + +uint8x16_t +foo (mve_pred16_t p) +{ + return vidupq_x_wb_u8 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ + +uint8x16_t +foo1 (mve_pred16_t p) +{ + return vidupq_x_u8 (a, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vidupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c new file mode 100644 index 0000000..2503927 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_n_u16 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u16 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c new file mode 100644 index 0000000..26d0e09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_n_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c new file mode 100644 index 0000000..97f47a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_n_u8 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u8 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c new file mode 100644 index 0000000..bbb2fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_wb_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ + +uint16x8_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u16 (a, b, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c new file mode 100644 index 0000000..8b9a2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_wb_u32 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ + +uint32x4_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u32 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c new file mode 100644 index 0000000..012343b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_wb_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ + +uint8x16_t +foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +{ + return viwdupq_x_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "viwdupt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c new file mode 100644 index 0000000..5ffedb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmaxnmq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c new file mode 100644 index 0000000..223681a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmaxnmq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c new file mode 100644 index 0000000..caba15a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c new file mode 100644 index 0000000..24e0edb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c new file mode 100644 index 0000000..12e99b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c new file mode 100644 index 0000000..4d158f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c new file mode 100644 index 0000000..2a28b3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c new file mode 100644 index 0000000..6a8bc6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmaxt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmaxq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c new file mode 100644 index 0000000..59ef96f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vminnmq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c new file mode 100644 index 0000000..6225aa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vminnmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vminnmq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c new file mode 100644 index 0000000..0f29965 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c new file mode 100644 index 0000000..f2b20f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c new file mode 100644 index 0000000..a4b172f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c new file mode 100644 index 0000000..e4643ad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c new file mode 100644 index 0000000..a042749 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c new file mode 100644 index 0000000..cb578ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmint.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vminq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c new file mode 100644 index 0000000..a55e093 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vmovlbq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vmovlbq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c new file mode 100644 index 0000000..8462ca4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vmovlbq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vmovlbq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c new file mode 100644 index 0000000..d51eae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vmovlbq_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vmovlbq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c new file mode 100644 index 0000000..f9040cd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vmovlbq_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vmovlbq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c new file mode 100644 index 0000000..6168454 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vmovltq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vmovltq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c new file mode 100644 index 0000000..3a8c081 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vmovltq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vmovltq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c new file mode 100644 index 0000000..9858305 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vmovltq_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vmovltq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c new file mode 100644 index 0000000..9072372 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vmovltq_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmovltt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vmovltq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c new file mode 100644 index 0000000..d8d5b01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulhq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c new file mode 100644 index 0000000..ca46762 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulhq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c new file mode 100644 index 0000000..9e154a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulhq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c new file mode 100644 index 0000000..9cee31a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulhq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c new file mode 100644 index 0000000..0bc19e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulhq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c new file mode 100644 index 0000000..feb2fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulhq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulht.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c new file mode 100644 index 0000000..f24ec82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c new file mode 100644 index 0000000..ffc77b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c new file mode 100644 index 0000000..4952690 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c new file mode 100644 index 0000000..58cd666 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c new file mode 100644 index 0000000..7029df8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u32" } } */ + +uint64x2_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c new file mode 100644 index 0000000..7b7efc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c new file mode 100644 index 0000000..b18fb29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_poly_x_p16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmullbq_poly_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c new file mode 100644 index 0000000..4e5a5e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_poly_x_p8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmullbt.p8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmullbq_poly_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c new file mode 100644 index 0000000..0aa2ebd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c new file mode 100644 index 0000000..491d050 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64x2_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s32" } } */ + +int64x2_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c new file mode 100644 index 0000000..f0e1aaf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c new file mode 100644 index 0000000..21d094d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c new file mode 100644 index 0000000..5ec93e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u32" } } */ + +uint64x2_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c new file mode 100644 index 0000000..be9d922 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_int_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c new file mode 100644 index 0000000..5a5dec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_poly_x_p16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p16" } } */ + +uint32x4_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulltq_poly_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c new file mode 100644 index 0000000..ff8eccd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_poly_x_p8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmulltt.p8" } } */ + +uint16x8_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulltq_poly_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c new file mode 100644 index 0000000..2a44a45 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmulq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c new file mode 100644 index 0000000..f33f085 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmulq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c new file mode 100644 index 0000000..2995890 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vmulq_x_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c new file mode 100644 index 0000000..53aa6b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vmulq_x_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c new file mode 100644 index 0000000..fc64cc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vmulq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c new file mode 100644 index 0000000..28a5d0b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vmulq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c new file mode 100644 index 0000000..b3d2419 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vmulq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c new file mode 100644 index 0000000..7864a13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vmulq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c new file mode 100644 index 0000000..29bec64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vmulq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c new file mode 100644 index 0000000..88afbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vmulq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c new file mode 100644 index 0000000..5ca463a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c new file mode 100644 index 0000000..2d29ff0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c new file mode 100644 index 0000000..3c37227 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c new file mode 100644 index 0000000..34461fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c new file mode 100644 index 0000000..b8c46c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c new file mode 100644 index 0000000..d37f305 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vmulq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmult.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c new file mode 100644 index 0000000..47e306d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (mve_pred16_t p) +{ + return vmvnq_x_n_s16 (2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c new file mode 100644 index 0000000..e93f4c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (mve_pred16_t p) +{ + return vmvnq_x_n_s32 (2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c new file mode 100644 index 0000000..3839645 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (mve_pred16_t p) +{ + return vmvnq_x_n_u16 (4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c new file mode 100644 index 0000000..885f61c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (mve_pred16_t p) +{ + return vmvnq_x_n_u32 (4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c new file mode 100644 index 0000000..0ba4d74 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vmvnq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c new file mode 100644 index 0000000..e040d3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vmvnq_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c new file mode 100644 index 0000000..0205103 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vmvnq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c new file mode 100644 index 0000000..1f55d61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vmvnq_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c new file mode 100644 index 0000000..c5fb84d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vmvnq_x_u32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c new file mode 100644 index 0000000..0b46308 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vmvnq_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vmvnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vmvnt" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c new file mode 100644 index 0000000..6719f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vnegq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vnegq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c new file mode 100644 index 0000000..0b5fc01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vnegq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vnegq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c new file mode 100644 index 0000000..c1e5130 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vnegq_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vnegq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c new file mode 100644 index 0000000..cdd0b8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vnegq_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vnegq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c new file mode 100644 index 0000000..5308961 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vnegq_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vnegt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vnegq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c new file mode 100644 index 0000000..061e7bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vornq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c new file mode 100644 index 0000000..e481083 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vornq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c new file mode 100644 index 0000000..176061e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vornq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c new file mode 100644 index 0000000..7c1562e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vornq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c new file mode 100644 index 0000000..017359b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vornq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c new file mode 100644 index 0000000..f5ae555 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vornq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c new file mode 100644 index 0000000..5e28447 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vornq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c new file mode 100644 index 0000000..7e19d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vornq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vornt" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vornq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c new file mode 100644 index 0000000..df93d29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vorrq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +float16x8_t +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c new file mode 100644 index 0000000..356d991 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vorrq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +float32x4_t +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c new file mode 100644 index 0000000..01a2b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vorrq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c new file mode 100644 index 0000000..b332474 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vorrq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c new file mode 100644 index 0000000..a62b24e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vorrq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c new file mode 100644 index 0000000..2054d47 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vorrq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c new file mode 100644 index 0000000..37e828b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vorrq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c new file mode 100644 index 0000000..2a6a273 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vorrq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vorrt" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vorrq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c new file mode 100644 index 0000000..917012f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vrev16q_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev16t.8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vrev16q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c new file mode 100644 index 0000000..e91ef20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vrev16q_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev16t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vrev16q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c new file mode 100644 index 0000000..7f0eafc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrev32q_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrev32q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c new file mode 100644 index 0000000..24613a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vrev32q_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vrev32q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c new file mode 100644 index 0000000..29eb483 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vrev32q_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vrev32q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c new file mode 100644 index 0000000..0d4ad70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vrev32q_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vrev32q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c new file mode 100644 index 0000000..9dfad95 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vrev32q_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev32t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vrev32q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c new file mode 100644 index 0000000..b866979 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrev64q_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c new file mode 100644 index 0000000..986efeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrev64q_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c new file mode 100644 index 0000000..51165f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vrev64q_x_s16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c new file mode 100644 index 0000000..8297d72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vrev64q_x_s32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c new file mode 100644 index 0000000..b9763c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vrev64q_x_s8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c new file mode 100644 index 0000000..f57373a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vrev64q_x_u16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c new file mode 100644 index 0000000..17cdd87 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vrev64q_x_u32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c new file mode 100644 index 0000000..4c9ce6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vrev64q_x_u8 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrev64t.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vrev64q_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c new file mode 100644 index 0000000..cc51dc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrhaddq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c new file mode 100644 index 0000000..24264716 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrhaddq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c new file mode 100644 index 0000000..2fd551f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrhaddq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c new file mode 100644 index 0000000..0565390 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrhaddq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c new file mode 100644 index 0000000..81ad0b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrhaddq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c new file mode 100644 index 0000000..cad187a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrhaddq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrhaddq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c new file mode 100644 index 0000000..2b57a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrmulhq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c new file mode 100644 index 0000000..ac8e286 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmulhq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c new file mode 100644 index 0000000..01b704d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrmulhq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c new file mode 100644 index 0000000..a944fcd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrmulhq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c new file mode 100644 index 0000000..7720f7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmulhq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c new file mode 100644 index 0000000..0dfa015 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrmulhq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrmulht.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vrmulhq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c new file mode 100644 index 0000000..1af1699 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndaq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintat.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndaq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c new file mode 100644 index 0000000..c641902 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndaq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintat.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndaq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c new file mode 100644 index 0000000..8e77f94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndmq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintmt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndmq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c new file mode 100644 index 0000000..a8e232f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndmq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintmt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndmq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c new file mode 100644 index 0000000..3be1ac8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndnq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintnt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c new file mode 100644 index 0000000..d2c4f58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndnq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintnt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndnq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c new file mode 100644 index 0000000..41623ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndpq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintpt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndpq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c new file mode 100644 index 0000000..7ce7cda --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndpq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintpt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndpq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c new file mode 100644 index 0000000..dfb04bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintzt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c new file mode 100644 index 0000000..2b695f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintzt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c new file mode 100644 index 0000000..c3efca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, mve_pred16_t p) +{ + return vrndxq_x_f16 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintxt.f16" } } */ + +float16x8_t +foo1 (float16x8_t a, mve_pred16_t p) +{ + return vrndxq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c new file mode 100644 index 0000000..0c78ce5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, mve_pred16_t p) +{ + return vrndxq_x_f32 (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrintxt.f32" } } */ + +float32x4_t +foo1 (float32x4_t a, mve_pred16_t p) +{ + return vrndxq_x (a, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c new file mode 100644 index 0000000..a31adc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c new file mode 100644 index 0000000..98a90fb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c new file mode 100644 index 0000000..8fcf7f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c new file mode 100644 index 0000000..d8a5b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c new file mode 100644 index 0000000..39af58b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c new file mode 100644 index 0000000..323d4ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vrshlq_x (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c new file mode 100644 index 0000000..c8dc5fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vrshrq_x_n_s16 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s16" } } */ + +int16x8_t +foo1 (int16x8_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c new file mode 100644 index 0000000..c8f4978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vrshrq_x_n_s32 (a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s32" } } */ + +int32x4_t +foo1 (int32x4_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c new file mode 100644 index 0000000..eb94ccb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vrshrq_x_n_s8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s8" } } */ + +int8x16_t +foo1 (int8x16_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c new file mode 100644 index 0000000..bb18df6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vrshrq_x_n_u16 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c new file mode 100644 index 0000000..19d1a8d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vrshrq_x_n_u32 (a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c new file mode 100644 index 0000000..25bf957 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vrshrq_x_n_u8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, mve_pred16_t p) +{ + return vrshrq_x (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vrshrt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c new file mode 100644 index 0000000..60fa99e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vshllbq_x_n_s16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c new file mode 100644 index 0000000..ae817df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vshllbq_x_n_s8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.s8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c new file mode 100644 index 0000000..07c85d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vshllbq_x_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c new file mode 100644 index 0000000..0ac6383 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vshllbq_x_n_u8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshllbt.u8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c new file mode 100644 index 0000000..e89fb56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vshlltq_x_n_s16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c new file mode 100644 index 0000000..5822014 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vshlltq_x_n_s8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.s8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c new file mode 100644 index 0000000..7b01bc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vshlltq_x_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c new file mode 100644 index 0000000..1716771 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vshlltq_x_n_u8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlltt.u8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c new file mode 100644 index 0000000..b14f188 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vshlq_x_n_s16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c new file mode 100644 index 0000000..aa50f08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vshlq_x_n_s32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c new file mode 100644 index 0000000..4fb36fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vshlq_x_n_s8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c new file mode 100644 index 0000000..2222300 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vshlq_x_n_u16 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c new file mode 100644 index 0000000..fc63fa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, mve_pred16_t p) +{ + return vshlq_x_n_u32 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c new file mode 100644 index 0000000..85af514 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vshlq_x_n_u8 (a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c new file mode 100644 index 0000000..a4ccdec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c new file mode 100644 index 0000000..b9db0ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c new file mode 100644 index 0000000..410adeb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c new file mode 100644 index 0000000..c40e854 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c new file mode 100644 index 0000000..49533dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c new file mode 100644 index 0000000..e5c2500 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c new file mode 100644 index 0000000..864f8db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vshrq_x_n_s16 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c new file mode 100644 index 0000000..62efb79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, mve_pred16_t p) +{ + return vshrq_x_n_s32 (a, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c new file mode 100644 index 0000000..666319f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, mve_pred16_t p) +{ + return vshrq_x_n_s8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.s8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c new file mode 100644 index 0000000..cbeaca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, mve_pred16_t p) +{ + return vshrq_x_n_u16 (a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c new file mode 100644 index 0000000..09de106 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, mve_pred16_t p) +{ + return vshrq_x_n_u8 (a, 8, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshrt.u8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c new file mode 100644 index 0000000..885563e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16x8_t b, mve_pred16_t p) +{ + return vsubq_x_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c new file mode 100644 index 0000000..caaef42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32x4_t b, mve_pred16_t p) +{ + return vsubq_x_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c new file mode 100644 index 0000000..8dc8661 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a, float16_t b, mve_pred16_t p) +{ + return vsubq_x_n_f16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c new file mode 100644 index 0000000..546662e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a, float32_t b, mve_pred16_t p) +{ + return vsubq_x_n_f32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.f32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c new file mode 100644 index 0000000..e8715e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16_t b, mve_pred16_t p) +{ + return vsubq_x_n_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c new file mode 100644 index 0000000..5ae1b46 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32_t b, mve_pred16_t p) +{ + return vsubq_x_n_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c new file mode 100644 index 0000000..1c39f5e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8_t b, mve_pred16_t p) +{ + return vsubq_x_n_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c new file mode 100644 index 0000000..9047fd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16_t b, mve_pred16_t p) +{ + return vsubq_x_n_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c new file mode 100644 index 0000000..d74b0e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t b, mve_pred16_t p) +{ + return vsubq_x_n_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c new file mode 100644 index 0000000..e14d55d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8_t b, mve_pred16_t p) +{ + return vsubq_x_n_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c new file mode 100644 index 0000000..370ef71 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsubq_x_s16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c new file mode 100644 index 0000000..f4af97c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsubq_x_s32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c new file mode 100644 index 0000000..e1ac508 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsubq_x_s8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c new file mode 100644 index 0000000..f9a951a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsubq_x_u16 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c new file mode 100644 index 0000000..593b8a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsubq_x_u32 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c new file mode 100644 index 0000000..5e194b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsubq_x_u8 (a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + -- cgit v1.1 From 828878c35c8585978e3ac22deddbf10f33c0a576 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Wed, 18 Mar 2020 13:57:24 -0400 Subject: c++: Include the constraint parameter mapping in diagnostic constraint contexts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When diagnosing a constraint error, we currently try to print the constraint inside a diagnostic constraint context with its template arguments substituted in. If substitution fails, then we instead just print the dependent form, as in the test case below: .../diagnostic6.C:14:15: error: static assertion failed 14 | static_assert(E); // { dg-error "static assertion failed|not a class" } | ^~~~~~ .../diagnostic6.C:14:15: note: constraints not satisfied .../diagnostic6.C:4:11: required for the satisfaction of ‘C’ .../diagnostic6.C:8:11: required for the satisfaction of ‘D’ .../diagnostic6.C:14:15: error: ‘int’ is not a class, struct, or union type But printing just the dependent form sometimes makes it difficult to understand the underlying failure. In the above example, for instance, there's no indication of how the template argument 'int' relates to either of the 'T's. This patch improves the situation by changing these diagnostics to always print the dependent form of the constraint, and alongside it the (preferably substituted) constraint parameter mapping. So with the same test case below we now get: .../diagnostic6.C:14:15: error: static assertion failed 14 | static_assert(E); // { dg-error "static assertion failed|not a class" } | ^~~~~~ .../diagnostic6.C:14:15: note: constraints not satisfied .../diagnostic6.C:4:11: required for the satisfaction of ‘C’ [with T = typename T::type] .../diagnostic6.C:8:11: required for the satisfaction of ‘D’ [with T = int] .../diagnostic6.C:14:15: error: ‘int’ is not a class, struct, or union type This change arguably makes it easier to figure out what's going on whenever a constraint fails due to substitution creating an invalid type rather than failing due to the constraint evaluating to false. gcc/cp/ChangeLog: * cxx-pretty-print.c (pp_cxx_parameter_mapping): Make extern. Move the "[with ]" bits to here from ... (pp_cxx_atomic_constraint): ... here. * cxx-pretty-print.h (pp_cxx_parameter_mapping): Declare. * error.c (rebuild_concept_check): Delete. (print_concept_check_info): Print the dependent form of the constraint and the preferably substituted parameter mapping alongside it. gcc/testsuite/ChangeLog: * g++.dg/concepts/diagnostic6.C: New test. --- gcc/cp/ChangeLog | 10 +++++++++ gcc/cp/cxx-pretty-print.c | 18 +++++++-------- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +++++++++-------------------- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 ++++++++++++ 6 files changed, 48 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 929e709..0e01056a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2020-03-20 Patrick Palka + + * cxx-pretty-print.c (pp_cxx_parameter_mapping): Make extern. Move + the "[with ]" bits to here from ... + (pp_cxx_atomic_constraint): ... here. + * cxx-pretty-print.h (pp_cxx_parameter_mapping): Declare. + * error.c (rebuild_concept_check): Delete. + (print_concept_check_info): Print the dependent form of the constraint and the + preferably substituted parameter mapping alongside it. + 2020-03-19 Jason Merrill PR c++/94175 diff --git a/gcc/cp/cxx-pretty-print.c b/gcc/cp/cxx-pretty-print.c index 100154e..840b5a8 100644 --- a/gcc/cp/cxx-pretty-print.c +++ b/gcc/cp/cxx-pretty-print.c @@ -2878,9 +2878,14 @@ pp_cxx_check_constraint (cxx_pretty_printer *pp, tree t) /* Output the "[with ...]" clause for a parameter mapping of an atomic constraint. */ -static void +void pp_cxx_parameter_mapping (cxx_pretty_printer *pp, tree map) { + pp_cxx_whitespace (pp); + pp_cxx_left_bracket (pp); + pp->translate_string ("with"); + pp_cxx_whitespace (pp); + for (tree p = map; p; p = TREE_CHAIN (p)) { tree parm = TREE_VALUE (p); @@ -2903,6 +2908,8 @@ pp_cxx_parameter_mapping (cxx_pretty_printer *pp, tree map) if (TREE_CHAIN (p) != NULL_TREE) pp_cxx_separate_with (pp, ';'); } + + pp_cxx_right_bracket (pp); } void @@ -2914,14 +2921,7 @@ pp_cxx_atomic_constraint (cxx_pretty_printer *pp, tree t) /* Emit the parameter mapping. */ tree map = ATOMIC_CONSTR_MAP (t); if (map && map != error_mark_node) - { - pp_cxx_whitespace (pp); - pp_cxx_left_bracket (pp); - pp->translate_string ("with"); - pp_cxx_whitespace (pp); - pp_cxx_parameter_mapping (pp, map); - pp_cxx_right_bracket (pp); - } + pp_cxx_parameter_mapping (pp, map); } void diff --git a/gcc/cp/cxx-pretty-print.h b/gcc/cp/cxx-pretty-print.h index 7c7347f..494f3fd 100644 --- a/gcc/cp/cxx-pretty-print.h +++ b/gcc/cp/cxx-pretty-print.h @@ -112,5 +112,6 @@ void pp_cxx_conjunction (cxx_pretty_printer *, tree); void pp_cxx_disjunction (cxx_pretty_printer *, tree); void pp_cxx_constraint (cxx_pretty_printer *, tree); void pp_cxx_constrained_type_spec (cxx_pretty_printer *, tree); +void pp_cxx_parameter_mapping (cxx_pretty_printer *, tree); #endif /* GCC_CXX_PRETTY_PRINT_H */ diff --git a/gcc/cp/error.c b/gcc/cp/error.c index cc51b6f..61d1218 100644 --- a/gcc/cp/error.c +++ b/gcc/cp/error.c @@ -3680,27 +3680,6 @@ print_location (diagnostic_context *context, location_t loc) "locus", xloc.file, xloc.line); } -/* Instantiate the concept check for the purpose of diagnosing an error. */ - -static tree -rebuild_concept_check (tree expr, tree map, tree args) -{ - /* Instantiate the parameter mapping for the template-id. */ - map = tsubst_parameter_mapping (map, args, tf_none, NULL_TREE); - if (map == error_mark_node) - return error_mark_node; - args = get_mapped_args (map); - - /* Rebuild the template id using substituted arguments. Substituting - directly through the expression will trigger recursive satisfaction, - so don't do that. */ - tree id = unpack_concept_check (expr); - args = tsubst_template_args (TREE_OPERAND (id, 1), args, tf_none, NULL_TREE); - if (args == error_mark_node) - return error_mark_node; - return build_nt (TEMPLATE_ID_EXPR, TREE_OPERAND (id, 0), args); -} - static void print_constrained_decl_info (diagnostic_context *context, tree decl) { @@ -3717,12 +3696,18 @@ print_concept_check_info (diagnostic_context *context, tree expr, tree map, tree tree tmpl = TREE_OPERAND (id, 0); if (OVL_P (tmpl)) tmpl = OVL_FIRST (tmpl); - tree check = rebuild_concept_check (expr, map, args); - if (check == error_mark_node) - check = expr; print_location (context, DECL_SOURCE_LOCATION (tmpl)); - pp_verbatim (context->printer, "required for the satisfaction of %qE\n", check); + + cxx_pretty_printer *pp = (cxx_pretty_printer *)context->printer; + pp_verbatim (pp, "required for the satisfaction of %qE", expr); + if (map && map != error_mark_node) + { + tree subst_map = tsubst_parameter_mapping (map, args, tf_none, NULL_TREE); + pp_cxx_parameter_mapping (pp, (subst_map != error_mark_node + ? subst_map : map)); + } + pp_newline (pp); } /* Diagnose the entry point into the satisfaction error. Returns the next diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index adf53b3..12076d5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-20 Patrick Palka + + * g++.dg/concepts/diagnostic6.C: New test. + 2020-03-20 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: New test. diff --git a/gcc/testsuite/g++.dg/concepts/diagnostic6.C b/gcc/testsuite/g++.dg/concepts/diagnostic6.C new file mode 100644 index 0000000..06b17ca --- /dev/null +++ b/gcc/testsuite/g++.dg/concepts/diagnostic6.C @@ -0,0 +1,14 @@ +// { dg-do compile { target c++2a } } + +template + concept C = requires (T t) { t + 0; }; +// { dg-message "satisfaction of .C. .with T = typename T::type." "" { target *-*-* } .-1 } + +template + concept D = C; +// { dg-message "satisfaction of .D. .with T = int." "" { target *-*-* } .-1 } + +template + concept E = D; + +static_assert(E); // { dg-error "static assertion failed|not a class" } -- cgit v1.1 From c3562f81042e05d9bc82d6834cac761c9d9db0c8 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 16:06:58 +0000 Subject: [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across beats" and "beat-wise substract". This patch supports following MVE ACLE "add with carry across beats" intrinsics and "beat-wise substract" intrinsics. vadciq_s32, vadciq_u32, vadciq_m_s32, vadciq_m_u32, vadcq_s32, vadcq_u32, vadcq_m_s32, vadcq_m_u32, vsbciq_s32, vsbciq_u32, vsbciq_m_s32, vsbciq_m_u32, vsbcq_s32, vsbcq_u32, vsbcq_m_s32, vsbcq_m_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array. (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC and ARM_BUILTIN_SET_FPSCR_NZCVQC. * config/arm/arm_mve.h (vadciq_s32): Define macro. (vadciq_u32): Likewise. (vadciq_m_s32): Likewise. (vadciq_m_u32): Likewise. (vadcq_s32): Likewise. (vadcq_u32): Likewise. (vadcq_m_s32): Likewise. (vadcq_m_u32): Likewise. (vsbciq_s32): Likewise. (vsbciq_u32): Likewise. (vsbciq_m_s32): Likewise. (vsbciq_m_u32): Likewise. (vsbcq_s32): Likewise. (vsbcq_u32): Likewise. (vsbcq_m_s32): Likewise. (vsbcq_m_u32): Likewise. (__arm_vadciq_s32): Define intrinsic. (__arm_vadciq_u32): Likewise. (__arm_vadciq_m_s32): Likewise. (__arm_vadciq_m_u32): Likewise. (__arm_vadcq_s32): Likewise. (__arm_vadcq_u32): Likewise. (__arm_vadcq_m_s32): Likewise. (__arm_vadcq_m_u32): Likewise. (__arm_vsbciq_s32): Likewise. (__arm_vsbciq_u32): Likewise. (__arm_vsbciq_m_s32): Likewise. (__arm_vsbciq_m_u32): Likewise. (__arm_vsbcq_s32): Likewise. (__arm_vsbcq_u32): Likewise. (__arm_vsbcq_m_s32): Likewise. (__arm_vsbcq_m_u32): Likewise. (vadciq_m): Define polymorphic variant. (vadciq): Likewise. (vadcq_m): Likewise. (vadcq): Likewise. (vsbciq_m): Likewise. (vsbciq): Likewise. (vsbcq_m): Likewise. (vsbcq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin qualifier. (BINOP_UNONE_UNONE_UNONE): Likewise. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VADCIQ): Define iterator. (VADCIQ_M): Likewise. (VSBCQ): Likewise. (VSBCQ_M): Likewise. (VSBCIQ): Likewise. (VSBCIQ_M): Likewise. (VADCQ): Likewise. (VADCQ_M): Likewise. (mve_vadciq_m_v4si): Define RTL pattern. (mve_vadciq_v4si): Likewise. (mve_vadcq_m_v4si): Likewise. (mve_vadcq_v4si): Likewise. (mve_vsbciq_m_v4si): Likewise. (mve_vsbciq_v4si): Likewise. (mve_vsbcq_m_v4si): Likewise. (mve_vsbcq_v4si): Likewise. (get_fpscr_nzcvqc): Define isns. (set_fpscr_nzcvqc): Define isns. * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define. (UNSPEC_SET_FPSCR_NZCVQC): Define. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: New test. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise. --- gcc/ChangeLog | 76 +++++++ gcc/config/arm/arm-builtins.c | 35 ++++ gcc/config/arm/arm_mve.h | 227 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 16 ++ gcc/config/arm/mve.md | 182 ++++++++++++++++- gcc/config/arm/unspecs.md | 2 + gcc/testsuite/ChangeLog | 21 ++ .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 24 +++ .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 23 +++ .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 22 ++ .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 22 ++ 23 files changed, 923 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6bbdf06..44888ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,80 @@ 2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. + (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. + (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and + "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array. + (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC + and ARM_BUILTIN_SET_FPSCR_NZCVQC. + * config/arm/arm_mve.h (vadciq_s32): Define macro. + (vadciq_u32): Likewise. + (vadciq_m_s32): Likewise. + (vadciq_m_u32): Likewise. + (vadcq_s32): Likewise. + (vadcq_u32): Likewise. + (vadcq_m_s32): Likewise. + (vadcq_m_u32): Likewise. + (vsbciq_s32): Likewise. + (vsbciq_u32): Likewise. + (vsbciq_m_s32): Likewise. + (vsbciq_m_u32): Likewise. + (vsbcq_s32): Likewise. + (vsbcq_u32): Likewise. + (vsbcq_m_s32): Likewise. + (vsbcq_m_u32): Likewise. + (__arm_vadciq_s32): Define intrinsic. + (__arm_vadciq_u32): Likewise. + (__arm_vadciq_m_s32): Likewise. + (__arm_vadciq_m_u32): Likewise. + (__arm_vadcq_s32): Likewise. + (__arm_vadcq_u32): Likewise. + (__arm_vadcq_m_s32): Likewise. + (__arm_vadcq_m_u32): Likewise. + (__arm_vsbciq_s32): Likewise. + (__arm_vsbciq_u32): Likewise. + (__arm_vsbciq_m_s32): Likewise. + (__arm_vsbciq_m_u32): Likewise. + (__arm_vsbcq_s32): Likewise. + (__arm_vsbcq_u32): Likewise. + (__arm_vsbcq_m_s32): Likewise. + (__arm_vsbcq_m_u32): Likewise. + (vadciq_m): Define polymorphic variant. + (vadciq): Likewise. + (vadcq_m): Likewise. + (vadcq): Likewise. + (vsbciq_m): Likewise. + (vsbciq): Likewise. + (vsbcq_m): Likewise. + (vsbcq): Likewise. + * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin + qualifier. + (BINOP_UNONE_UNONE_UNONE): Likewise. + (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. + * config/arm/mve.md (VADCIQ): Define iterator. + (VADCIQ_M): Likewise. + (VSBCQ): Likewise. + (VSBCQ_M): Likewise. + (VSBCIQ): Likewise. + (VSBCIQ_M): Likewise. + (VADCQ): Likewise. + (VADCQ_M): Likewise. + (mve_vadciq_m_v4si): Define RTL pattern. + (mve_vadciq_v4si): Likewise. + (mve_vadcq_m_v4si): Likewise. + (mve_vadcq_v4si): Likewise. + (mve_vsbciq_m_v4si): Likewise. + (mve_vsbciq_v4si): Likewise. + (mve_vsbcq_m_v4si): Likewise. + (mve_vsbcq_v4si): Likewise. + (get_fpscr_nzcvqc): Define isns. + (set_fpscr_nzcvqc): Define isns. + * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define. + (UNSPEC_SET_FPSCR_NZCVQC): Define. + +2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. (vddupq_x_n_u16): Likewise. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index ecdd95f..96d8adc 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1151,6 +1151,8 @@ enum arm_builtins ARM_BUILTIN_GET_FPSCR, ARM_BUILTIN_SET_FPSCR, + ARM_BUILTIN_GET_FPSCR_NZCVQC, + ARM_BUILTIN_SET_FPSCR_NZCVQC, ARM_BUILTIN_CMSE_NONSECURE_CALLER, ARM_BUILTIN_SIMD_LANE_CHECK, @@ -1752,6 +1754,22 @@ arm_init_mve_builtins (void) arm_init_simd_builtin_scalar_types (); arm_init_simd_builtin_types (); + /* Add support for __builtin_{get,set}_fpscr_nzcvqc, used by MVE intrinsics + that read and/or write the carry bit. */ + tree get_fpscr_nzcvqc = build_function_type_list (intSI_type_node, + NULL); + tree set_fpscr_nzcvqc = build_function_type_list (void_type_node, + intSI_type_node, + NULL); + arm_builtin_decls[ARM_BUILTIN_GET_FPSCR_NZCVQC] + = add_builtin_function ("__builtin_arm_get_fpscr_nzcvqc", get_fpscr_nzcvqc, + ARM_BUILTIN_GET_FPSCR_NZCVQC, BUILT_IN_MD, NULL, + NULL_TREE); + arm_builtin_decls[ARM_BUILTIN_SET_FPSCR_NZCVQC] + = add_builtin_function ("__builtin_arm_set_fpscr_nzcvqc", set_fpscr_nzcvqc, + ARM_BUILTIN_SET_FPSCR_NZCVQC, BUILT_IN_MD, NULL, + NULL_TREE); + for (i = 0; i < ARRAY_SIZE (mve_builtin_data); i++, fcode++) { arm_builtin_datum *d = &mve_builtin_data[i]; @@ -3289,6 +3307,23 @@ arm_expand_builtin (tree exp, switch (fcode) { + case ARM_BUILTIN_GET_FPSCR_NZCVQC: + case ARM_BUILTIN_SET_FPSCR_NZCVQC: + if (fcode == ARM_BUILTIN_GET_FPSCR_NZCVQC) + { + icode = CODE_FOR_get_fpscr_nzcvqc; + target = gen_reg_rtx (SImode); + emit_insn (GEN_FCN (icode) (target)); + return target; + } + else + { + icode = CODE_FOR_set_fpscr_nzcvqc; + op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + emit_insn (GEN_FCN (icode) (force_reg (SImode, op0))); + return NULL_RTX; + } + case ARM_BUILTIN_GET_FPSCR: case ARM_BUILTIN_SET_FPSCR: if (fcode == ARM_BUILTIN_GET_FPSCR) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 77df7c7..220319c 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2450,6 +2450,22 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vrev32q_x_f16(__a, __p) __arm_vrev32q_x_f16(__a, __p) #define vrev64q_x_f16(__a, __p) __arm_vrev64q_x_f16(__a, __p) #define vrev64q_x_f32(__a, __p) __arm_vrev64q_x_f32(__a, __p) +#define vadciq_s32(__a, __b, __carry_out) __arm_vadciq_s32(__a, __b, __carry_out) +#define vadciq_u32(__a, __b, __carry_out) __arm_vadciq_u32(__a, __b, __carry_out) +#define vadciq_m_s32(__inactive, __a, __b, __carry_out, __p) __arm_vadciq_m_s32(__inactive, __a, __b, __carry_out, __p) +#define vadciq_m_u32(__inactive, __a, __b, __carry_out, __p) __arm_vadciq_m_u32(__inactive, __a, __b, __carry_out, __p) +#define vadcq_s32(__a, __b, __carry) __arm_vadcq_s32(__a, __b, __carry) +#define vadcq_u32(__a, __b, __carry) __arm_vadcq_u32(__a, __b, __carry) +#define vadcq_m_s32(__inactive, __a, __b, __carry, __p) __arm_vadcq_m_s32(__inactive, __a, __b, __carry, __p) +#define vadcq_m_u32(__inactive, __a, __b, __carry, __p) __arm_vadcq_m_u32(__inactive, __a, __b, __carry, __p) +#define vsbciq_s32(__a, __b, __carry_out) __arm_vsbciq_s32(__a, __b, __carry_out) +#define vsbciq_u32(__a, __b, __carry_out) __arm_vsbciq_u32(__a, __b, __carry_out) +#define vsbciq_m_s32(__inactive, __a, __b, __carry_out, __p) __arm_vsbciq_m_s32(__inactive, __a, __b, __carry_out, __p) +#define vsbciq_m_u32(__inactive, __a, __b, __carry_out, __p) __arm_vsbciq_m_u32(__inactive, __a, __b, __carry_out, __p) +#define vsbcq_s32(__a, __b, __carry) __arm_vsbcq_s32(__a, __b, __carry) +#define vsbcq_u32(__a, __b, __carry) __arm_vsbcq_u32(__a, __b, __carry) +#define vsbcq_m_s32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_s32(__inactive, __a, __b, __carry, __p) +#define vsbcq_m_u32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_u32(__inactive, __a, __b, __carry, __p) #endif __extension__ extern __inline void @@ -15917,6 +15933,158 @@ __arm_vshrq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) return __builtin_mve_vshrq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p); } +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadciq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) +{ + int32x4_t __res = __builtin_mve_vadciq_sv4si (__a, __b); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadciq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry_out) +{ + uint32x4_t __res = __builtin_mve_vadciq_uv4si (__a, __b); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadciq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry_out, mve_pred16_t __p) +{ + int32x4_t __res = __builtin_mve_vadciq_m_sv4si (__inactive, __a, __b, __p); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadciq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry_out, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_vadciq_m_uv4si (__inactive, __a, __b, __p); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbciq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry_out) +{ + int32x4_t __res = __builtin_mve_vsbciq_sv4si (__a, __b); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbciq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry_out) +{ + uint32x4_t __res = __builtin_mve_vsbciq_uv4si (__a, __b); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbciq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry_out, mve_pred16_t __p) +{ + int32x4_t __res = __builtin_mve_vsbciq_m_sv4si (__inactive, __a, __b, __p); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbciq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry_out, mve_pred16_t __p) +{ + uint32x4_t __res = __builtin_mve_vsbciq_m_uv4si (__inactive, __a, __b, __p); + *__carry_out = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) +{ + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -25525,6 +25693,65 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce(__p0, int64_t const *), p1, p2), \ int (*)[__ARM_mve_type_uint64_t_const_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce(__p0, uint64_t const *), p1, p2));}) +#define vadciq_m(p0,p1,p2,p3,p4) __arm_vadciq_m(p0,p1,p2,p3,p4) +#define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadciq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadciq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3, p4));}) + +#define vadciq(p0,p1,p2) __arm_vadciq(p0,p1,p2) +#define __arm_vadciq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadciq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadciq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vadcq_m(p0,p1,p2,p3,p4) __arm_vadcq_m(p0,p1,p2,p3,p4) +#define __arm_vadcq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadcq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadcq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3, p4));}) + +#define vadcq(p0,p1,p2) __arm_vadcq(p0,p1,p2) +#define __arm_vadcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vsbciq_m(p0,p1,p2,p3,p4) __arm_vsbciq_m(p0,p1,p2,p3,p4) +#define __arm_vsbciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsbciq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsbciq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3, p4));}) + +#define vsbciq(p0,p1,p2) __arm_vsbciq(p0,p1,p2) +#define __arm_vsbciq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsbciq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsbciq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vsbcq_m(p0,p1,p2,p3,p4) __arm_vsbcq_m(p0,p1,p2,p3,p4) +#define __arm_vsbcq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsbcq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3, p4), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsbcq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3, p4));}) + +#define vsbcq(p0,p1,p2) __arm_vsbcq(p0,p1,p2) +#define __arm_vsbcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsbcq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsbcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2) #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 9fc0a8a..38f46be 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -857,3 +857,19 @@ VAR1 (LDRGBWBS_Z, vldrdq_gather_base_wb_z_s, v2di) VAR1 (LDRGBWBS, vldrwq_gather_base_wb_s, v4si) VAR1 (LDRGBWBS, vldrwq_gather_base_wb_f, v4sf) VAR1 (LDRGBWBS, vldrdq_gather_base_wb_s, v2di) +VAR1 (BINOP_NONE_NONE_NONE, vadciq_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vadciq_u, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vadcq_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vadcq_u, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vsbciq_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vsbciq_u, v4si) +VAR1 (BINOP_NONE_NONE_NONE, vsbcq_s, v4si) +VAR1 (BINOP_UNONE_UNONE_UNONE, vsbcq_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadciq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadciq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadcq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadcq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index a22e752..25b5973 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -211,7 +211,10 @@ VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M VSTRWQSBWB_S VSTRWQSBWB_U VLDRWQGBWB_S VLDRWQGBWB_U VSTRWQSBWB_F VLDRWQGBWB_F VSTRDQSBWB_S VSTRDQSBWB_U - VLDRDQGBWB_S VLDRDQGBWB_U]) + VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S + VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S + VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U + VADCIQ_S VADCIQ_M_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -382,8 +385,13 @@ (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u") (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u") (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s") - (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") - (VSTRDQSBWB_U "u")]) + (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s") + (VSTRDQSBWB_U "u") (VSBCQ_U "u") (VSBCQ_M_U "u") + (VSBCQ_S "s") (VSBCQ_M_S "s") (VSBCIQ_U "u") + (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s") + (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s") + (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s") + (VADCIQ_M_S "s")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -636,6 +644,15 @@ (define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U]) (define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U]) (define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U]) +(define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S]) +(define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S]) +(define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S]) +(define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S]) +(define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S]) +(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S]) +(define_int_iterator VADCQ [VADCQ_U VADCQ_S]) +(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S]) + (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -10597,6 +10614,21 @@ DONE; }) +(define_insn "get_fpscr_nzcvqc" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] + "TARGET_HAVE_MVE" + "vmrs\\t%0, FPSCR_nzcvqc" + [(set_attr "type" "mve_move")]) + +(define_insn "set_fpscr_nzcvqc" + [(set (reg:SI VFPCC_REGNUM) + (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] + VUNSPEC_SET_FPSCR_NZCVQC))] + "TARGET_HAVE_MVE" + "vmsr\\tFPSCR_nzcvqc, %0" + [(set_attr "type" "mve_move")]) + ;; ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] ;; @@ -10621,3 +10653,147 @@ return ""; } [(set_attr "length" "8")]) +;; +;; [vadciq_m_s, vadciq_m_u]) +;; +(define_insn "mve_vadciq_m_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADCIQ_M)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(const_int 0)] + VADCIQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vadcit.i32\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length" "8")]) + +;; +;; [vadciq_u, vadciq_s]) +;; +(define_insn "mve_vadciq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VADCIQ)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(const_int 0)] + VADCIQ)) + ] + "TARGET_HAVE_MVE" + "vadci.i32\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length" "4")]) + +;; +;; [vadcq_m_s, vadcq_m_u]) +;; +(define_insn "mve_vadcq_m_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VADCQ_M)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(reg:SI VFPCC_REGNUM)] + VADCQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vadct.i32\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length" "8")]) + +;; +;; [vadcq_u, vadcq_s]) +;; +(define_insn "mve_vadcq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VADCQ)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(reg:SI VFPCC_REGNUM)] + VADCQ)) + ] + "TARGET_HAVE_MVE" + "vadc.i32\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length" "4") + (set_attr "conds" "set")]) + +;; +;; [vsbciq_m_u, vsbciq_m_s]) +;; +(define_insn "mve_vsbciq_m_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSBCIQ_M)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(const_int 0)] + VSBCIQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsbcit.i32\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length" "8")]) + +;; +;; [vsbciq_s, vsbciq_u]) +;; +(define_insn "mve_vsbciq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSBCIQ)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(const_int 0)] + VSBCIQ)) + ] + "TARGET_HAVE_MVE" + "vsbci.i32\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length" "4")]) + +;; +;; [vsbcq_m_u, vsbcq_m_s]) +;; +(define_insn "mve_vsbcq_m_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w") + (match_operand:V4SI 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSBCQ_M)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(reg:SI VFPCC_REGNUM)] + VSBCQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsbct.i32\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length" "8")]) + +;; +;; [vsbcq_s, vsbcq_u]) +;; +(define_insn "mve_vsbcq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSBCQ)) + (set (reg:SI VFPCC_REGNUM) + (unspec:SI [(reg:SI VFPCC_REGNUM)] + VSBCQ)) + ] + "TARGET_HAVE_MVE" + "vsbc.i32\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length" "4")]) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index f0b1f46..a757587 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,6 +170,7 @@ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. + UNSPEC_GET_FPSCR_NZCVQC ; Represent fetch of FPSCR_nzcvqc content. ]) @@ -218,6 +219,7 @@ VUNSPEC_STL ; Represent a store-register-release. VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. + VUNSPEC_SET_FPSCR_NZCVQC ; Represent assign of FPSCR_nzcvqc content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 12076d5..540ec67 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: New test. + * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise. + 2020-03-20 Patrick Palka * g++.dg/concepts/diagnostic6.C: New test. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c new file mode 100644 index 0000000..3b4019b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vadciq_m_s32 (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadcit.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vadciq_m (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadcit.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c new file mode 100644 index 0000000..a69039d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vadciq_m_u32 (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadcit.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vadciq_m (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadcit.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c new file mode 100644 index 0000000..3b7623c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, unsigned * carry_out) +{ + return vadciq_s32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vadci.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) +{ + return vadciq (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vadci.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c new file mode 100644 index 0000000..07eb9d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) +{ + return vadciq_u32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vadci.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) +{ + return vadciq (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vadci.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c new file mode 100644 index 0000000..8c6f231 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vadcq_m_s32 (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadct.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vadcq_m (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadct.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c new file mode 100644 index 0000000..0747fee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vadcq_m_u32 (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadct.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vadcq_m (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vadct.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c new file mode 100644 index 0000000..0783007 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, unsigned * carry) +{ + return vadcq_s32 (a, b, carry); +} + +/* { dg-final { scan-assembler "vadc.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, unsigned * carry) +{ + return vadcq (a, b, carry); +} + +/* { dg-final { scan-assembler "vadc.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c new file mode 100644 index 0000000..479db3a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, unsigned * carry) +{ + return vadcq_u32 (a, b, carry); +} + +/* { dg-final { scan-assembler "vadc.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) +{ + return vadcq (a, b, carry); +} + +/* { dg-final { scan-assembler "vadc.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c new file mode 100644 index 0000000..11e5b40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vsbciq_m_s32 (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbcit.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vsbciq_m (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbcit.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c new file mode 100644 index 0000000..df638bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vsbciq_m_u32 (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbcit.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) +{ + return vsbciq_m (inactive, a, b, carry_out, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbcit.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c new file mode 100644 index 0000000..6f0f4dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, unsigned * carry_out) +{ + return vsbciq_s32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vsbci.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) +{ + return vsbciq_s32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vsbci.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c new file mode 100644 index 0000000..e68eaa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) +{ + return vsbciq_u32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vsbci.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) +{ + return vsbciq_u32 (a, b, carry_out); +} + +/* { dg-final { scan-assembler "vsbci.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c new file mode 100644 index 0000000..0f9b9b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vsbcq_m_s32 (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbct.i32" } } */ + +int32x4_t +foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vsbcq_m (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbct.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c new file mode 100644 index 0000000..fb62c26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vsbcq_m_u32 (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbct.i32" } } */ +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) +{ + return vsbcq_m (inactive, a, b, carry, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsbct.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c new file mode 100644 index 0000000..fbbda5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, unsigned * carry) +{ + return vsbcq_s32 (a, b, carry); +} + +/* { dg-final { scan-assembler "vsbc.i32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, unsigned * carry) +{ + return vsbcq (a, b, carry); +} + +/* { dg-final { scan-assembler "vsbc.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c new file mode 100644 index 0000000..2863453 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, unsigned * carry) +{ + return vsbcq_u32 (a, b, carry); +} + +/* { dg-final { scan-assembler "vsbc.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) +{ + return vsbcq (a, b, carry); +} + +/* { dg-final { scan-assembler "vsbc.i32" } } */ -- cgit v1.1 From 1aa22b1916a493ac46453d96e0c78ca47bcaeda3 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 17 Mar 2020 14:43:08 +0000 Subject: c-family: Tighten vector handling in type_for_mode [PR94072] In this PR we had a 512-bit VECTOR_TYPE whose mode is XImode (an integer mode used for four 128-bit vectors). When trying to expand a zero constant for it, we hit code in expand_expr_real_1 that tries to use the associated integer type instead. The code used type_for_mode (XImode, 1) to get this integer type. However, the c-family implementation of type_for_mode checks for any registered built-in type that matches the mode and has the right signedness. This meant that it could return a built-in vector type when given an integer mode (particularly if, as here, the vector type isn't supported by the current subtarget and so TYPE_MODE != TYPE_MODE_RAW). The expand code would then cycle endlessly trying to use this "new" type instead of the original vector type. 2020-03-20 Richard Sandiford gcc/c-family/ PR middle-end/94072 * c-common.c (c_common_type_for_mode): Before using a registered built-in type, check that the vectorness of the type matches the vectorness of the mode. gcc/testsuite/ PR middle-end/94072 * gcc.target/aarch64/pr94072.c: New test. --- gcc/c-family/ChangeLog | 7 +++++++ gcc/c-family/c-common.c | 11 +++++++---- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 +++++++++ 4 files changed, 28 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c (limited to 'gcc') diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 59661ef..3f195eb 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,10 @@ +2020-03-20 Richard Sandiford + + PR middle-end/94072 + * c-common.c (c_common_type_for_mode): Before using a registered + built-in type, check that the vectorness of the type matches + the vectorness of the mode. + 2020-03-17 Jakub Jelinek * c-common.c (resolve_overloaded_builtin): Fix up duplicated word diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 25020bf14..8e5a924 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -2387,10 +2387,13 @@ c_common_type_for_mode (machine_mode mode, int unsignedp) } for (t = registered_builtin_types; t; t = TREE_CHAIN (t)) - if (TYPE_MODE (TREE_VALUE (t)) == mode - && !!unsignedp == !!TYPE_UNSIGNED (TREE_VALUE (t))) - return TREE_VALUE (t); - + { + tree type = TREE_VALUE (t); + if (TYPE_MODE (type) == mode + && VECTOR_TYPE_P (type) == VECTOR_MODE_P (mode) + && !!unsignedp == !!TYPE_UNSIGNED (type)) + return type; + } return NULL_TREE; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 540ec67..2408590 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-20 Richard Sandiford + + PR middle-end/94072 + * gcc.target/aarch64/pr94072.c: New test. + 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/testsuite/gcc.target/aarch64/pr94072.c b/gcc/testsuite/gcc.target/aarch64/pr94072.c new file mode 100644 index 0000000..2aa72eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr94072.c @@ -0,0 +1,9 @@ +/* { dg-options "-msve-vector-bits=512" } */ + +#pragma GCC target "+nosve" + +void +foo (void) +{ + (int __attribute__ ((__vector_size__ (64)))){}; +} -- cgit v1.1 From b5446d0cc09e6a931065b98101d799711fd5b035 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Fri, 20 Mar 2020 17:26:29 +0100 Subject: d: Fix SEGV in hash_table::find_slot_with_hash This patch fixes LTO bug with the D front-end. As DECL_ASSEMBLER_NAME is set on the TYPE_DECL, so TYPE_CXX_ODR_P must also be set on the type. The addition of merge_aggregate_types is not strictly needed now, but it fixes a problem introduced in newer versions of the dmd front-end where templated types could be sent more than once to the D code generator. gcc/d/ChangeLog: 2020-03-20 Iain Buclaw PR lto/91027 * d-tree.h (struct GTY): Add daggregate field. (IDENTIFIER_DAGGREGATE): Define. (d_mangle_decl): Add declaration. * decl.cc (mangle_decl): Remove static linkage, rename to... (d_mangle_decl): ...this, update all callers. * types.cc (merge_aggregate_types): New function. (TypeVisitor::visit (TypeStruct *)): Call merge_aggregate_types, set IDENTIFIER_DAGGREGATE and TYPE_CXX_ODR_P. (TypeVisitor::visit (TypeClass *)): Likewise. --- gcc/d/ChangeLog | 13 +++++++++++++ gcc/d/d-tree.h | 5 +++++ gcc/d/decl.cc | 10 +++++----- gcc/d/types.cc | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 32856f1..407dc14 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,16 @@ +2020-03-20 Iain Buclaw + + PR lto/91027 + * d-tree.h (struct GTY): Add daggregate field. + (IDENTIFIER_DAGGREGATE): Define. + (d_mangle_decl): Add declaration. + * decl.cc (mangle_decl): Remove static linkage, rename to... + (d_mangle_decl): ...this, update all callers. + * types.cc (merge_aggregate_types): New function. + (TypeVisitor::visit (TypeStruct *)): Call merge_aggregate_types, set + IDENTIFIER_DAGGREGATE and TYPE_CXX_ODR_P. + (TypeVisitor::visit (TypeClass *)): Likewise. + 2020-03-18 Jakub Jelinek * expr.cc (ExprVisitor::visit (CatAssignExp *)): Fix up duplicated diff --git a/gcc/d/d-tree.h b/gcc/d/d-tree.h index 4e9c0b7..0f831c7 100644 --- a/gcc/d/d-tree.h +++ b/gcc/d/d-tree.h @@ -204,6 +204,7 @@ struct GTY(()) lang_identifier /* The frontend Declaration associated with this identifier. */ Declaration * GTY((skip)) dsymbol; + AggregateDeclaration * GTY((skip)) daggregate; }; #define IDENTIFIER_LANG_SPECIFIC(NODE) \ @@ -218,6 +219,9 @@ struct GTY(()) lang_identifier #define IDENTIFIER_DSYMBOL(NODE) \ (IDENTIFIER_LANG_SPECIFIC (NODE)->dsymbol) +#define IDENTIFIER_DAGGREGATE(NODE) \ + (IDENTIFIER_LANG_SPECIFIC (NODE)->daggregate) + /* Global state pertinent to the current function. */ struct GTY(()) language_function @@ -600,6 +604,7 @@ extern tree d_signed_type (tree); extern void d_keep (tree); /* In decl.cc. */ +extern const char *d_mangle_decl (Dsymbol *); extern tree mangle_internal_decl (Dsymbol *, const char *, const char *); extern void build_decl_tree (Dsymbol *); extern tree get_symbol_decl (Declaration *); diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc index 7afb1aa..053d553 100644 --- a/gcc/d/decl.cc +++ b/gcc/d/decl.cc @@ -59,8 +59,8 @@ along with GCC; see the file COPYING3. If not see /* Return identifier for the external mangled name of DECL. */ -static const char * -mangle_decl (Dsymbol *decl) +const char * +d_mangle_decl (Dsymbol *decl) { if (decl->isFuncDeclaration ()) return mangleExact ((FuncDeclaration *)decl); @@ -78,7 +78,7 @@ mangle_decl (Dsymbol *decl) tree mangle_internal_decl (Dsymbol *decl, const char *name, const char *suffix) { - const char *prefix = mangle_decl (decl); + const char *prefix = d_mangle_decl (decl); unsigned namelen = strlen (name); unsigned buflen = (2 + strlen (prefix) + namelen + strlen (suffix)) * 2; char *buf = (char *) alloca (buflen); @@ -1145,7 +1145,7 @@ get_symbol_decl (Declaration *decl) if (decl->mangleOverride) mangled_name = get_identifier (decl->mangleOverride); else - mangled_name = get_identifier (mangle_decl (decl)); + mangled_name = get_identifier (d_mangle_decl (decl)); mangled_name = targetm.mangle_decl_assembler_name (decl->csym, mangled_name); @@ -2333,7 +2333,7 @@ build_type_decl (tree type, Dsymbol *dsym) tree decl = build_decl (make_location_t (dsym->loc), TYPE_DECL, get_identifier (name), type); - SET_DECL_ASSEMBLER_NAME (decl, get_identifier (mangle_decl (dsym))); + SET_DECL_ASSEMBLER_NAME (decl, get_identifier (d_mangle_decl (dsym))); TREE_PUBLIC (decl) = 1; DECL_ARTIFICIAL (decl) = 1; DECL_CONTEXT (decl) = d_decl_context (dsym); diff --git a/gcc/d/types.cc b/gcc/d/types.cc index 866da96..0252852 100644 --- a/gcc/d/types.cc +++ b/gcc/d/types.cc @@ -498,6 +498,40 @@ finish_aggregate_type (unsigned structsize, unsigned alignsize, } } +/* Returns true if the class or struct type TYPE has already been layed out by + the lowering of another front-end AST type. In which case, there will either + be a reuse of the back-end type, or a multiple definition error. + DECO is the uniquely mangled decoration for the type. */ + +static bool +merge_aggregate_types (Type *type, tree deco) +{ + AggregateDeclaration *sym; + + if (type->ty == Tstruct) + sym = ((TypeStruct *) type)->sym; + else if (type->ty == Tclass) + sym = ((TypeClass *) type)->sym; + else + gcc_unreachable (); + + if (IDENTIFIER_DAGGREGATE (deco)) + { + AggregateDeclaration *ad = IDENTIFIER_DAGGREGATE (deco); + /* There should never be a class/struct mismatch in mangled names. */ + gcc_assert ((sym->isStructDeclaration () && ad->isStructDeclaration ()) + || (sym->isClassDeclaration () && ad->isClassDeclaration ())); + + /* Non-templated variables shouldn't be defined twice. */ + if (!sym->isInstantiated ()) + ScopeDsymbol::multiplyDefined (sym->loc, sym, ad); + + type->ctype = build_ctype (ad->type); + return true; + } + + return false; +} /* Implements the visitor interface to build the GCC trees of all Type AST classes emitted from the D Front-end, where CTYPE holds @@ -857,12 +891,19 @@ public: void visit (TypeStruct *t) { + /* Merge types in the back-end if the front-end did not itself do so. */ + tree deco = get_identifier (d_mangle_decl (t->sym)); + if (merge_aggregate_types (t, deco)) + return; + /* Need to set this right away in case of self-references. */ t->ctype = make_node (t->sym->isUnionDeclaration () ? UNION_TYPE : RECORD_TYPE); d_keep (t->ctype); + IDENTIFIER_DAGGREGATE (deco) = t->sym; TYPE_LANG_SPECIFIC (t->ctype) = build_lang_type (t); + TYPE_CXX_ODR_P (t->ctype) = 1; if (t->sym->members) { @@ -903,17 +944,24 @@ public: void visit (TypeClass *t) { + /* Merge types in the back-end if the front-end did not itself do so. */ + tree deco = get_identifier (d_mangle_decl (t->sym)); + if (merge_aggregate_types (t, deco)) + return; + /* Need to set ctype right away in case of self-references to the type during this call. */ tree basetype = make_node (RECORD_TYPE); t->ctype = build_pointer_type (basetype); d_keep (t->ctype); + IDENTIFIER_DAGGREGATE (deco) = t->sym; /* Note that lang_specific data is assigned to both the reference and the underlying record type. */ TYPE_LANG_SPECIFIC (t->ctype) = build_lang_type (t); TYPE_LANG_SPECIFIC (basetype) = TYPE_LANG_SPECIFIC (t->ctype); CLASS_TYPE_P (basetype) = 1; + TYPE_CXX_ODR_P (basetype) = 1; /* Put out all fields, including from each base class. */ layout_aggregate_type (t->sym, basetype, t->sym); -- cgit v1.1 From 1dfcc3b541c52174e0d7d7f30e7e092d02000a7f Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 20 Mar 2020 16:56:23 +0000 Subject: [ARM][GCC][11x]: MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliases to vstr and vldr intrinsics. This patch supports following MVE ACLE intrinsics which are aliases of vstr and vldr intrinsics. vst1q_p_u8, vst1q_p_s8, vld1q_z_u8, vld1q_z_s8, vst1q_p_u16, vst1q_p_s16, vld1q_z_u16, vld1q_z_s16, vst1q_p_u32, vst1q_p_s32, vld1q_z_u32, vld1q_z_s32, vld1q_z_f16, vst1q_p_f16, vld1q_z_f32, vst1q_p_f32. This patch also supports following MVE ACLE vector deinterleaving loads and vector interleaving stores. vst2q_s8, vst2q_u8, vld2q_s8, vld2q_u8, vld4q_s8, vld4q_u8, vst2q_s16, vst2q_u16, vld2q_s16, vld2q_u16, vld4q_s16, vld4q_u16, vst2q_s32, vst2q_u32, vld2q_s32, vld2q_u32, vld4q_s32, vld4q_u32, vld4q_f16, vld2q_f16, vst2q_f16, vld4q_f32, vld2q_f32, vst2q_f32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vst1q_p_u8): Define macro. (vst1q_p_s8): Likewise. (vst2q_s8): Likewise. (vst2q_u8): Likewise. (vld1q_z_u8): Likewise. (vld1q_z_s8): Likewise. (vld2q_s8): Likewise. (vld2q_u8): Likewise. (vld4q_s8): Likewise. (vld4q_u8): Likewise. (vst1q_p_u16): Likewise. (vst1q_p_s16): Likewise. (vst2q_s16): Likewise. (vst2q_u16): Likewise. (vld1q_z_u16): Likewise. (vld1q_z_s16): Likewise. (vld2q_s16): Likewise. (vld2q_u16): Likewise. (vld4q_s16): Likewise. (vld4q_u16): Likewise. (vst1q_p_u32): Likewise. (vst1q_p_s32): Likewise. (vst2q_s32): Likewise. (vst2q_u32): Likewise. (vld1q_z_u32): Likewise. (vld1q_z_s32): Likewise. (vld2q_s32): Likewise. (vld2q_u32): Likewise. (vld4q_s32): Likewise. (vld4q_u32): Likewise. (vld4q_f16): Likewise. (vld2q_f16): Likewise. (vld1q_z_f16): Likewise. (vst2q_f16): Likewise. (vst1q_p_f16): Likewise. (vld4q_f32): Likewise. (vld2q_f32): Likewise. (vld1q_z_f32): Likewise. (vst2q_f32): Likewise. (vst1q_p_f32): Likewise. (__arm_vst1q_p_u8): Define intrinsic. (__arm_vst1q_p_s8): Likewise. (__arm_vst2q_s8): Likewise. (__arm_vst2q_u8): Likewise. (__arm_vld1q_z_u8): Likewise. (__arm_vld1q_z_s8): Likewise. (__arm_vld2q_s8): Likewise. (__arm_vld2q_u8): Likewise. (__arm_vld4q_s8): Likewise. (__arm_vld4q_u8): Likewise. (__arm_vst1q_p_u16): Likewise. (__arm_vst1q_p_s16): Likewise. (__arm_vst2q_s16): Likewise. (__arm_vst2q_u16): Likewise. (__arm_vld1q_z_u16): Likewise. (__arm_vld1q_z_s16): Likewise. (__arm_vld2q_s16): Likewise. (__arm_vld2q_u16): Likewise. (__arm_vld4q_s16): Likewise. (__arm_vld4q_u16): Likewise. (__arm_vst1q_p_u32): Likewise. (__arm_vst1q_p_s32): Likewise. (__arm_vst2q_s32): Likewise. (__arm_vst2q_u32): Likewise. (__arm_vld1q_z_u32): Likewise. (__arm_vld1q_z_s32): Likewise. (__arm_vld2q_s32): Likewise. (__arm_vld2q_u32): Likewise. (__arm_vld4q_s32): Likewise. (__arm_vld4q_u32): Likewise. (__arm_vld4q_f16): Likewise. (__arm_vld2q_f16): Likewise. (__arm_vld1q_z_f16): Likewise. (__arm_vst2q_f16): Likewise. (__arm_vst1q_p_f16): Likewise. (__arm_vld4q_f32): Likewise. (__arm_vld2q_f32): Likewise. (__arm_vld1q_z_f32): Likewise. (__arm_vst2q_f32): Likewise. (__arm_vst1q_p_f32): Likewise. (vld1q_z): Define polymorphic variant. (vld2q): Likewise. (vld4q): Likewise. (vst1q_p): Likewise. (vst2q): Likewise. * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. (LOAD1): Likewise. * config/arm/mve.md (mve_vst2q): Define RTL pattern. (mve_vld2q): Likewise. (mve_vld4q): Likewise. gcc/testsuite/ChangeLog: 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. --- gcc/ChangeLog | 95 ++++ gcc/config/arm/arm_mve.h | 482 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 3 + gcc/config/arm/mve.md | 90 +++- gcc/testsuite/ChangeLog | 45 ++ .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + 45 files changed, 1634 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44888ca..9f50e43 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,101 @@ Andre Vieira Mihail Ionescu + * config/arm/arm_mve.h (vst1q_p_u8): Define macro. + (vst1q_p_s8): Likewise. + (vst2q_s8): Likewise. + (vst2q_u8): Likewise. + (vld1q_z_u8): Likewise. + (vld1q_z_s8): Likewise. + (vld2q_s8): Likewise. + (vld2q_u8): Likewise. + (vld4q_s8): Likewise. + (vld4q_u8): Likewise. + (vst1q_p_u16): Likewise. + (vst1q_p_s16): Likewise. + (vst2q_s16): Likewise. + (vst2q_u16): Likewise. + (vld1q_z_u16): Likewise. + (vld1q_z_s16): Likewise. + (vld2q_s16): Likewise. + (vld2q_u16): Likewise. + (vld4q_s16): Likewise. + (vld4q_u16): Likewise. + (vst1q_p_u32): Likewise. + (vst1q_p_s32): Likewise. + (vst2q_s32): Likewise. + (vst2q_u32): Likewise. + (vld1q_z_u32): Likewise. + (vld1q_z_s32): Likewise. + (vld2q_s32): Likewise. + (vld2q_u32): Likewise. + (vld4q_s32): Likewise. + (vld4q_u32): Likewise. + (vld4q_f16): Likewise. + (vld2q_f16): Likewise. + (vld1q_z_f16): Likewise. + (vst2q_f16): Likewise. + (vst1q_p_f16): Likewise. + (vld4q_f32): Likewise. + (vld2q_f32): Likewise. + (vld1q_z_f32): Likewise. + (vst2q_f32): Likewise. + (vst1q_p_f32): Likewise. + (__arm_vst1q_p_u8): Define intrinsic. + (__arm_vst1q_p_s8): Likewise. + (__arm_vst2q_s8): Likewise. + (__arm_vst2q_u8): Likewise. + (__arm_vld1q_z_u8): Likewise. + (__arm_vld1q_z_s8): Likewise. + (__arm_vld2q_s8): Likewise. + (__arm_vld2q_u8): Likewise. + (__arm_vld4q_s8): Likewise. + (__arm_vld4q_u8): Likewise. + (__arm_vst1q_p_u16): Likewise. + (__arm_vst1q_p_s16): Likewise. + (__arm_vst2q_s16): Likewise. + (__arm_vst2q_u16): Likewise. + (__arm_vld1q_z_u16): Likewise. + (__arm_vld1q_z_s16): Likewise. + (__arm_vld2q_s16): Likewise. + (__arm_vld2q_u16): Likewise. + (__arm_vld4q_s16): Likewise. + (__arm_vld4q_u16): Likewise. + (__arm_vst1q_p_u32): Likewise. + (__arm_vst1q_p_s32): Likewise. + (__arm_vst2q_s32): Likewise. + (__arm_vst2q_u32): Likewise. + (__arm_vld1q_z_u32): Likewise. + (__arm_vld1q_z_s32): Likewise. + (__arm_vld2q_s32): Likewise. + (__arm_vld2q_u32): Likewise. + (__arm_vld4q_s32): Likewise. + (__arm_vld4q_u32): Likewise. + (__arm_vld4q_f16): Likewise. + (__arm_vld2q_f16): Likewise. + (__arm_vld1q_z_f16): Likewise. + (__arm_vst2q_f16): Likewise. + (__arm_vst1q_p_f16): Likewise. + (__arm_vld4q_f32): Likewise. + (__arm_vld2q_f32): Likewise. + (__arm_vld1q_z_f32): Likewise. + (__arm_vst2q_f32): Likewise. + (__arm_vst1q_p_f32): Likewise. + (vld1q_z): Define polymorphic variant. + (vld2q): Likewise. + (vld4q): Likewise. + (vst1q_p): Likewise. + (vst2q): Likewise. + * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. + (LOAD1): Likewise. + * config/arm/mve.md (mve_vst2q): Define RTL pattern. + (mve_vld2q): Likewise. + (mve_vld4q): Likewise. + +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 220319c..f6810dd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2466,6 +2466,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsbcq_u32(__a, __b, __carry) __arm_vsbcq_u32(__a, __b, __carry) #define vsbcq_m_s32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_s32(__inactive, __a, __b, __carry, __p) #define vsbcq_m_u32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_u32(__inactive, __a, __b, __carry, __p) +#define vst1q_p_u8(__addr, __value, __p) __arm_vst1q_p_u8(__addr, __value, __p) +#define vst1q_p_s8(__addr, __value, __p) __arm_vst1q_p_s8(__addr, __value, __p) +#define vst2q_s8(__addr, __value) __arm_vst2q_s8(__addr, __value) +#define vst2q_u8(__addr, __value) __arm_vst2q_u8(__addr, __value) +#define vld1q_z_u8(__base, __p) __arm_vld1q_z_u8(__base, __p) +#define vld1q_z_s8(__base, __p) __arm_vld1q_z_s8(__base, __p) +#define vld2q_s8(__addr) __arm_vld2q_s8(__addr) +#define vld2q_u8(__addr) __arm_vld2q_u8(__addr) +#define vld4q_s8(__addr) __arm_vld4q_s8(__addr) +#define vld4q_u8(__addr) __arm_vld4q_u8(__addr) +#define vst1q_p_u16(__addr, __value, __p) __arm_vst1q_p_u16(__addr, __value, __p) +#define vst1q_p_s16(__addr, __value, __p) __arm_vst1q_p_s16(__addr, __value, __p) +#define vst2q_s16(__addr, __value) __arm_vst2q_s16(__addr, __value) +#define vst2q_u16(__addr, __value) __arm_vst2q_u16(__addr, __value) +#define vld1q_z_u16(__base, __p) __arm_vld1q_z_u16(__base, __p) +#define vld1q_z_s16(__base, __p) __arm_vld1q_z_s16(__base, __p) +#define vld2q_s16(__addr) __arm_vld2q_s16(__addr) +#define vld2q_u16(__addr) __arm_vld2q_u16(__addr) +#define vld4q_s16(__addr) __arm_vld4q_s16(__addr) +#define vld4q_u16(__addr) __arm_vld4q_u16(__addr) +#define vst1q_p_u32(__addr, __value, __p) __arm_vst1q_p_u32(__addr, __value, __p) +#define vst1q_p_s32(__addr, __value, __p) __arm_vst1q_p_s32(__addr, __value, __p) +#define vst2q_s32(__addr, __value) __arm_vst2q_s32(__addr, __value) +#define vst2q_u32(__addr, __value) __arm_vst2q_u32(__addr, __value) +#define vld1q_z_u32(__base, __p) __arm_vld1q_z_u32(__base, __p) +#define vld1q_z_s32(__base, __p) __arm_vld1q_z_s32(__base, __p) +#define vld2q_s32(__addr) __arm_vld2q_s32(__addr) +#define vld2q_u32(__addr) __arm_vld2q_u32(__addr) +#define vld4q_s32(__addr) __arm_vld4q_s32(__addr) +#define vld4q_u32(__addr) __arm_vld4q_u32(__addr) +#define vld4q_f16(__addr) __arm_vld4q_f16(__addr) +#define vld2q_f16(__addr) __arm_vld2q_f16(__addr) +#define vld1q_z_f16(__base, __p) __arm_vld1q_z_f16(__base, __p) +#define vst2q_f16(__addr, __value) __arm_vst2q_f16(__addr, __value) +#define vst1q_p_f16(__addr, __value, __p) __arm_vst1q_p_f16(__addr, __value, __p) +#define vld4q_f32(__addr) __arm_vld4q_f32(__addr) +#define vld2q_f32(__addr) __arm_vld2q_f32(__addr) +#define vld1q_z_f32(__base, __p) __arm_vld1q_z_f32(__base, __p) +#define vst2q_f32(__addr, __value) __arm_vst2q_f32(__addr, __value) +#define vst1q_p_f32(__addr, __value, __p) __arm_vst1q_p_f32(__addr, __value, __p) #endif __extension__ extern __inline void @@ -16085,6 +16125,252 @@ __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsign return __res; } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p) +{ + return vstrbq_p_u8 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p) +{ + return vstrbq_p_s8 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s8 (int8_t * __addr, int8x16x2_t __value) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u8 (uint8_t * __addr, uint8x16x2_t __value) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u8 (uint8_t const *__base, mve_pred16_t __p) +{ + return vldrbq_z_u8 ( __base, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s8 (int8_t const *__base, mve_pred16_t __p) +{ + return vldrbq_z_s8 ( __base, __p); +} + +__extension__ extern __inline int8x16x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s8 (int8_t const * __addr) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint8x16x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u8 (uint8_t const * __addr) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int8x16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s8 (int8_t const * __addr) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint8x16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u8 (uint8_t const * __addr) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p) +{ + return vstrhq_p_u16 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p) +{ + return vstrhq_p_s16 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s16 (int16_t * __addr, int16x8x2_t __value) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u16 (uint16_t * __addr, uint16x8x2_t __value) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u16 (uint16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_u16 ( __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s16 (int16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_s16 ( __base, __p); +} + +__extension__ extern __inline int16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s16 (int16_t const * __addr) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u16 (uint16_t const * __addr) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s16 (int16_t const * __addr) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u16 (uint16_t const * __addr) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p) +{ + return vstrwq_p_u32 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p) +{ + return vstrwq_p_s32 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s32 (int32_t * __addr, int32x4x2_t __value) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u32 (uint32_t * __addr, uint32x4x2_t __value) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u32 (uint32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_u32 ( __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s32 (int32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_s32 ( __base, __p); +} + +__extension__ extern __inline int32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s32 (int32_t const * __addr) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u32 (uint32_t const * __addr) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s32 (int32_t const * __addr) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u32 (uint32_t const * __addr) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -19436,6 +19722,88 @@ __arm_vrev64q_x_f32 (float32x4_t __a, mve_pred16_t __p) return __builtin_mve_vrev64q_m_fv4sf (vuninitializedq_f32 (), __a, __p); } +__extension__ extern __inline float16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_f16 (float16_t const * __addr) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv8hf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_f16 (float16_t const * __addr) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv8hf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_f16 (float16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_f16 ( __base, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_f16 (float16_t * __addr, float16x8x2_t __value) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) +{ + return vstrhq_p_f16 (__addr, __value, __p); +} + +__extension__ extern __inline float32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_f32 (float32_t const * __addr) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o = __builtin_mve_vld4qv4sf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_f32 (float32_t const * __addr) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_mve_vld2qv4sf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_f32 (float32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_f32 ( __base, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_f32 (float32_t * __addr, float32x4x2_t __value) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i = __value; + __builtin_mve_vst2qv4sf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p) +{ + return vstrwq_p_f32 (__addr, __value, __p); +} + #endif enum { @@ -21911,6 +22279,42 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));}) +#define vld1q_z(p0,p1) __arm_vld1q_z(p0, p1) +#define __arm_vld1q_z(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce(__p0, int8_t const *), p1), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), p1), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce(__p0, uint8_t const *), p1), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce(__p0, float16_t const *), p1), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1));}) + +#define vld2q(p0) __arm_vld2q(p0) +#define __arm_vld2q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));}) + +#define vld4q(p0) __arm_vld4q(p0) +#define __arm_vld4q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));}) + #define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1) #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -21979,6 +22383,32 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1, p2));}) +#define vst1q_p(p0,p1,p2) __arm_vst1q_p(p0,p1,p2) +#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +#define vst2q(p0,p1) __arm_vst2q(p0,p1) +#define __arm_vst2q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) + #define vst1q(p0,p1) __arm_vst1q(p0,p1) #define __arm_vst1q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -24849,6 +25279,28 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) +#define vst1q_p(p0,p1,p2) __arm_vst1q_p(p0,p1,p2) +#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vst2q(p0,p1) __arm_vst2q(p0,p1) +#define __arm_vst2q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) + #define vstrhq(p0,p1) __arm_vstrhq(p0,p1) #define __arm_vstrhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -25403,6 +25855,36 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) +#define vld1q_z(p0,p1) __arm_vld1q_z(p0, p1) +#define __arm_vld1q_z(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce(__p0, int8_t const *), p1), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), p1), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce(__p0, uint8_t const *), p1), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1));}) + +#define vld2q(p0) __arm_vld2q(p0) +#define __arm_vld2q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)));}) + +#define vld4q(p0) __arm_vld4q(p0) +#define __arm_vld4q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)));}) + #endif /* MVE Integer. */ #define vmvnq_x(p1,p2) __arm_vmvnq_x(p1,p2) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 38f46be..a60650c 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -873,3 +873,6 @@ VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si) VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si) VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) +VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 25b5973..2e28d9d 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -214,7 +214,7 @@ VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U - VADCIQ_S VADCIQ_M_S]) + VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -10797,3 +10797,91 @@ "vsbc.i32\t%q0, %q1, %q2" [(set_attr "type" "mve_move") (set_attr "length" "4")]) + +;; +;; [vst2q]) +;; +(define_insn "mve_vst2q" + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VST2Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[4]; + int regno = REGNO (operands[1]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = gen_rtx_REG (TImode, regno + 4); + rtx reg = operands[0]; + while (reg && !REG_P (reg)) + reg = XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[2] = reg; + ops[3] = operands[0]; + output_asm_insn ("vst20.\t{%q0, %q1}, [%2]\n\t" + "vst21.\t{%q0, %q1}, %3", ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vld2q]) +;; +(define_insn "mve_vld2q" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VLD2Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[4]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = gen_rtx_REG (TImode, regno + 4); + rtx reg = operands[1]; + while (reg && !REG_P (reg)) + reg = XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[2] = reg; + ops[3] = operands[1]; + output_asm_insn ("vld20.\t{%q0, %q1}, [%2]\n\t" + "vld21.\t{%q0, %q1}, %3", ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vld4q]) +;; +(define_insn "mve_vld4q" + [(set (match_operand:XI 0 "s_register_operand" "=w") + (unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VLD4Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[6]; + int regno = REGNO (operands[0]); + ops[0] = gen_rtx_REG (TImode, regno); + ops[1] = gen_rtx_REG (TImode, regno+4); + ops[2] = gen_rtx_REG (TImode, regno+8); + ops[3] = gen_rtx_REG (TImode, regno + 12); + rtx reg = operands[1]; + while (reg && !REG_P (reg)) + reg = XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[4] = reg; + ops[5] = operands[1]; + output_asm_insn ("vld40.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld41.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld42.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld43.\t{%q0, %q1, %q2, %q3}, %5", ops); + return ""; +} + [(set_attr "length" "16")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2408590..c9fff88 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,48 @@ +2020-03-20 Srinath Parvathaneni + Andre Vieira + Mihail Ionescu + + * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. + 2020-03-20 Richard Sandiford PR middle-end/94072 diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c new file mode 100644 index 0000000..830d817 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, mve_pred16_t p) +{ + return vld1q_z_f16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c new file mode 100644 index 0000000..84f976a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, mve_pred16_t p) +{ + return vld1q_z_f32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ + +float32x4_t +foo1 (float32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c new file mode 100644 index 0000000..8bb7ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vld1q_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ + +int16x8_t +foo1 (int16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c new file mode 100644 index 0000000..f5d7cc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, mve_pred16_t p) +{ + return vld1q_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ + +int32x4_t +foo1 (int32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c new file mode 100644 index 0000000..a3999e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vld1q_z_s8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ + +int8x16_t +foo1 (int8_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c new file mode 100644 index 0000000..ada9c2f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vld1q_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c new file mode 100644 index 0000000..c96be7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, mve_pred16_t p) +{ + return vld1q_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c new file mode 100644 index 0000000..faca38d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vld1q_z_u8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c new file mode 100644 index 0000000..cb2bc6f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8x2_t +foo (float16_t const * addr) +{ + return vld2q_f16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +float16x8x2_t +foo1 (float16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c new file mode 100644 index 0000000..f701d3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4x2_t +foo (float32_t const * addr) +{ + return vld2q_f32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +float32x4x2_t +foo1 (float32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c new file mode 100644 index 0000000..85e844c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8x2_t +foo (int16_t const * addr) +{ + return vld2q_s16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +int16x8x2_t +foo1 (int16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c new file mode 100644 index 0000000..f46a9d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4x2_t +foo (int32_t const * addr) +{ + return vld2q_s32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +int32x4x2_t +foo1 (int32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c new file mode 100644 index 0000000..29dc288 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16x2_t +foo (int8_t const * addr) +{ + return vld2q_s8 (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ +/* { dg-final { scan-assembler "vld21.8" } } */ + +int8x16x2_t +foo1 (int8_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c new file mode 100644 index 0000000..7d867b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8x2_t +foo (uint16_t const * addr) +{ + return vld2q_u16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +uint16x8x2_t +foo1 (uint16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c new file mode 100644 index 0000000..6c9d12e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4x2_t +foo (uint32_t const * addr) +{ + return vld2q_u32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +uint32x4x2_t +foo1 (uint32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c new file mode 100644 index 0000000..002a645 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16x2_t +foo (uint8_t const * addr) +{ + return vld2q_u8 (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ +/* { dg-final { scan-assembler "vld21.8" } } */ + +uint8x16x2_t +foo1 (uint8_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c new file mode 100644 index 0000000..386b71b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8x4_t +foo (float16_t const * addr) +{ + return vld4q_f16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +float16x8x4_t +foo1 (float16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c new file mode 100644 index 0000000..c38bb54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4x4_t +foo (float32_t const * addr) +{ + return vld4q_f32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +float32x4x4_t +foo1 (float32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c new file mode 100644 index 0000000..68e6b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8x4_t +foo (int16_t const * addr) +{ + return vld4q_s16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +int16x8x4_t +foo1 (int16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c new file mode 100644 index 0000000..db0ba20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4x4_t +foo (int32_t const * addr) +{ + return vld4q_s32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +int32x4x4_t +foo1 (int32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c new file mode 100644 index 0000000..e38bdea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16x4_t +foo (int8_t const * addr) +{ + return vld4q_s8 (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ +/* { dg-final { scan-assembler "vld41.8" } } */ +/* { dg-final { scan-assembler "vld42.8" } } */ +/* { dg-final { scan-assembler "vld43.8" } } */ + +int8x16x4_t +foo1 (int8_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c new file mode 100644 index 0000000..7f6a783 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8x4_t +foo (uint16_t const * addr) +{ + return vld4q_u16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +uint16x8x4_t +foo1 (uint16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c new file mode 100644 index 0000000..29af573 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4x4_t +foo (uint32_t const * addr) +{ + return vld4q_u32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +uint32x4x4_t +foo1 (uint32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c new file mode 100644 index 0000000..f540362 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16x4_t +foo (uint8_t const * addr) +{ + return vld4q_u8 (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ +/* { dg-final { scan-assembler "vld41.8" } } */ +/* { dg-final { scan-assembler "vld42.8" } } */ +/* { dg-final { scan-assembler "vld43.8" } } */ + +uint8x16x4_t +foo1 (uint8_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c new file mode 100644 index 0000000..7ef5cce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vst1q_p_f16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c new file mode 100644 index 0000000..2cd7221 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vst1q_p_f32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c new file mode 100644 index 0000000..ca56f73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vst1q_p_s16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c new file mode 100644 index 0000000..782496f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vst1q_p_s32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c new file mode 100644 index 0000000..92bbc0a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vst1q_p_s8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c new file mode 100644 index 0000000..12c50f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vst1q_p_u16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c new file mode 100644 index 0000000..2f7ef61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vst1q_p_u32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c new file mode 100644 index 0000000..56fde60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vst1q_p_u8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c new file mode 100644 index 0000000..79e1b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8x2_t value) +{ + vst2q_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (float16_t * addr, float16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c new file mode 100644 index 0000000..7d256aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4x2_t value) +{ + vst2q_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (float32_t * addr, float32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c new file mode 100644 index 0000000..f2fd867 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8x2_t value) +{ + vst2q_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (int16_t * addr, int16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c new file mode 100644 index 0000000..85e36df --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4x2_t value) +{ + vst2q_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (int32_t * addr, int32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c new file mode 100644 index 0000000..57e9efc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16x2_t value) +{ + vst2q_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler "vst21.8" } } */ + +void +foo1 (int8_t * addr, int8x16x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c new file mode 100644 index 0000000..b54c791 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8x2_t value) +{ + vst2q_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c new file mode 100644 index 0000000..167f8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4x2_t value) +{ + vst2q_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c new file mode 100644 index 0000000..9f7a5f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16x2_t value) +{ + vst2q_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler "vst21.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ -- cgit v1.1 From a23eff1bd04ebdca503376ae6198d95c737dc3de Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Fri, 20 Mar 2020 13:06:21 -0400 Subject: c++: Add testcases from PR c++/69694 These testcases are compiling successfully since 7.1. gcc/testsuite/ChangeLog: PR c++/69694 * g++.dg/cpp0x/decltype74.C: New test. * g++.dg/cpp0x/decltype75.C: New test. --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 ++++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 ++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c9fff88..76b93b5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-20 Patrick Palka + + PR c++/69694 + * g++.dg/cpp0x/decltype74.C: New test. + * g++.dg/cpp0x/decltype75.C: New test. + 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/testsuite/g++.dg/cpp0x/decltype74.C b/gcc/testsuite/g++.dg/cpp0x/decltype74.C new file mode 100644 index 0000000..9ddd1c1 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/decltype74.C @@ -0,0 +1,30 @@ +// PR c++/69694 +// { dg-do compile { target c++11 } } + +// n3911: TransformationTrait Alias `void_t` +template struct make_void { using type = void; }; +template using void_t = typename make_void::type; + +// std::declval +void*& declval_void(); + +template struct Fun; +template + struct Fun +{ + void fun(); +}; +template + struct Fun> + : Fun +{ +}; + +struct Tag { static constexpr void* name = 0; }; + +template void a() +{ + Fun{}.fun(); +} + +void b() { a(); } diff --git a/gcc/testsuite/g++.dg/cpp0x/decltype75.C b/gcc/testsuite/g++.dg/cpp0x/decltype75.C new file mode 100644 index 0000000..0e97411 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/decltype75.C @@ -0,0 +1,24 @@ +// PR c++/69694 +// This is a reduced version of decltype74.C. +// { dg-do compile { target c++11 } } + +template using void_t = void; + +extern void *declval_void; + +template struct Fun { }; + +template +struct Fun> +{ + void fun(); +}; + +struct Tag { static constexpr void* name = 0; }; + +template void a() +{ + Fun{}.fun(); +} + +void b() { a(); } -- cgit v1.1 From a89349e664ff420f33612d47e486954de5848e49 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 20 Mar 2020 18:57:30 +0100 Subject: adjust SLP tree dumping This also dumps the root node we eventually smuggle in. 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree from the possibly modified root. --- gcc/ChangeLog | 5 +++++ gcc/tree-vect-slp.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9f50e43..967e454 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-03-20 Richard Biener + + * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree + from the possibly modified root. + 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index fb13af7..e43d03b 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -2435,7 +2435,8 @@ vect_analyze_slp_instance (vec_info *vinfo, { dump_printf_loc (MSG_NOTE, vect_location, "Final SLP tree for instance:\n"); - vect_print_slp_tree (MSG_NOTE, vect_location, node); + vect_print_slp_tree (MSG_NOTE, vect_location, + SLP_INSTANCE_TREE (new_instance)); } return true; -- cgit v1.1 From 72b3bc895f023bf451357659cfe96c966945bdf9 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 20 Mar 2020 22:06:24 +0100 Subject: Fix verifier ICE on wrong comdat local flag [PR93347] gcc/ChangeLog: 2020-03-20 Jan Hubicka PR ipa/93347 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag. (cgraph_edge::redirect_callee): Move here; likewise. (cgraph_node::remove_callees): Update calls_comdat_local flag. (cgraph_node::verify_node): Verify that calls_comdat_local flag match reality. (cgraph_node::check_calls_comdat_local_p): New member function. * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare. (cgraph_edge::redirect_callee): Move offline. * ipa-fnsummary.c (compute_fn_summary): Do not compute calls_comdat_local flag here. * ipa-inline-transform.c (inline_call): Fix updating of calls_comdat_local flag. * ipa-split.c (split_function): Use true instead of 1 to set the flag. * symtab.c (symtab_node::add_to_same_comdat_group): Update calls_comdat_local flag. gcc/testsuite/ChangeLog: 2020-03-20 Jan Hubicka * g++.dg/torture/pr93347.C: New test. --- gcc/ChangeLog | 19 ++ gcc/cgraph.c | 64 ++++++- gcc/cgraph.h | 17 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/symtab.c | 11 ++ gcc/testsuite/ChangeLog | 5 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 +++++++++++++++++++++++++++++++++ 9 files changed, 407 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 967e454..7f00a13 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2020-03-20 Jan Hubicka + + PR ipa/93347 + * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag. + (cgraph_edge::redirect_callee): Move here; likewise. + (cgraph_node::remove_callees): Update calls_comdat_local flag. + (cgraph_node::verify_node): Verify that calls_comdat_local flag match + reality. + (cgraph_node::check_calls_comdat_local_p): New member function. + * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare. + (cgraph_edge::redirect_callee): Move offline. + * ipa-fnsummary.c (compute_fn_summary): Do not compute + calls_comdat_local flag here. + * ipa-inline-transform.c (inline_call): Fix updating of + calls_comdat_local flag. + * ipa-split.c (split_function): Use true instead of 1 to set the flag. + * symtab.c (symtab_node::add_to_same_comdat_group): Update + calls_comdat_local flag. + 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree diff --git a/gcc/cgraph.c b/gcc/cgraph.c index b41dea1..6b780f8 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -557,7 +557,8 @@ cgraph_node::get_create (tree decl) } /* Mark ALIAS as an alias to DECL. DECL_NODE is cgraph node representing - the function body is associated with (not necessarily cgraph_node (DECL). */ + the function body is associated with + (not necessarily cgraph_node (DECL)). */ cgraph_node * cgraph_node::create_alias (tree alias, tree target) @@ -914,6 +915,10 @@ symbol_table::create_edge (cgraph_node *caller, cgraph_node *callee, else edge->in_polymorphic_cdtor = caller->thunk.thunk_p; + if (callee && symtab->state != LTO_STREAMING + && edge->callee->comdat_local_p ()) + edge->caller->calls_comdat_local = true; + return edge; } @@ -1341,6 +1346,34 @@ cgraph_edge::make_direct (cgraph_edge *edge, cgraph_node *callee) return edge; } +/* Redirect callee of the edge to N. The function does not update underlying + call expression. */ + +void +cgraph_edge::redirect_callee (cgraph_node *n) +{ + bool loc = callee->comdat_local_p (); + /* Remove from callers list of the current callee. */ + remove_callee (); + + /* Insert to callers list of the new callee. */ + set_callee (n); + + if (!inline_failed) + return; + if (!loc && n->comdat_local_p ()) + { + cgraph_node *to = caller->inlined_to ? caller->inlined_to : caller; + to->calls_comdat_local = true; + } + else if (loc && !n->comdat_local_p ()) + { + cgraph_node *to = caller->inlined_to ? caller->inlined_to : caller; + gcc_checking_assert (to->calls_comdat_local); + to->calls_comdat_local = to->check_calls_comdat_local_p (); + } +} + /* If necessary, change the function declaration in the call statement associated with E so that it corresponds to the edge callee. Speculations can be resolved in the process and EDGE can be removed and deallocated. @@ -1674,6 +1707,8 @@ cgraph_node::remove_callees (void) { cgraph_edge *e, *f; + calls_comdat_local = false; + /* It is sufficient to remove the edges from the lists of callers of the callees. The callee list of the node can be zapped with one assignment. */ @@ -3369,10 +3404,18 @@ cgraph_node::verify_node (void) error ("inline clone is forced to output"); error_found = true; } - if (calls_comdat_local && !same_comdat_group) + if (symtab->state != LTO_STREAMING) { - error ("calls_comdat_local is set outside of a comdat group"); - error_found = true; + if (calls_comdat_local && !same_comdat_group) + { + error ("calls_comdat_local is set outside of a comdat group"); + error_found = true; + } + if (!inlined_to && calls_comdat_local != check_calls_comdat_local_p ()) + { + error ("invalid calls_comdat_local flag"); + error_found = true; + } } if (DECL_IS_MALLOC (decl) && !POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (decl)))) @@ -4044,6 +4087,19 @@ cgraph_edge::num_speculative_call_targets_p (void) return indirect_info ? indirect_info->num_speculative_call_targets : 0; } +/* Check if function calls comdat local. This is used to recompute + calls_comdat_local flag after function transformations. */ +bool +cgraph_node::check_calls_comdat_local_p () +{ + for (cgraph_edge *e = callees; e; e = e->next_callee) + if (e->inline_failed + ? e->callee->comdat_local_p () + : e->callee->check_calls_comdat_local_p ()) + return true; + return false; +} + /* A stashed copy of "symtab" for use by selftest::symbol_table_test. This needs to be a global so that it can be a GC root, and thus prevent the stashed copy from being garbage-collected if the GC runs diff --git a/gcc/cgraph.h b/gcc/cgraph.h index aa4cdc9..43de3b4 100644 --- a/gcc/cgraph.h +++ b/gcc/cgraph.h @@ -1326,6 +1326,10 @@ struct GTY((tag ("SYMTAB_FUNCTION"))) cgraph_node : public symtab_node /* Return true if this node represents a former, i.e. an expanded, thunk. */ inline bool former_thunk_p (void); + /* Check if function calls comdat local. This is used to recompute + calls_comdat_local flag after function transformations. */ + bool check_calls_comdat_local_p (); + /* Return true if function should be optimized for size. */ bool optimize_for_size_p (void); @@ -3298,19 +3302,6 @@ cgraph_edge::set_callee (cgraph_node *n) callee = n; } -/* Redirect callee of the edge to N. The function does not update underlying - call expression. */ - -inline void -cgraph_edge::redirect_callee (cgraph_node *n) -{ - /* Remove from callers list of the current callee. */ - remove_callee (); - - /* Insert to callers list of the new callee. */ - set_callee (n); -} - /* Return true when the edge represents a direct recursion. */ inline bool diff --git a/gcc/ipa-fnsummary.c b/gcc/ipa-fnsummary.c index 059ea74..b411bc4 100644 --- a/gcc/ipa-fnsummary.c +++ b/gcc/ipa-fnsummary.c @@ -2944,10 +2944,6 @@ compute_fn_summary (struct cgraph_node *node, bool early) analyze_function_body (node, early); pop_cfun (); } - for (e = node->callees; e; e = e->next_callee) - if (e->callee->comdat_local_p ()) - break; - node->calls_comdat_local = (e != NULL); /* Inlining characteristics are maintained by the cgraph_mark_inline. */ size_info->size = size_info->self_size; diff --git a/gcc/ipa-inline-transform.c b/gcc/ipa-inline-transform.c index fa5015d..eed992d 100644 --- a/gcc/ipa-inline-transform.c +++ b/gcc/ipa-inline-transform.c @@ -504,14 +504,7 @@ inline_call (struct cgraph_edge *e, bool update_original, if (callee->calls_comdat_local) to->calls_comdat_local = true; else if (to->calls_comdat_local && comdat_local) - { - struct cgraph_edge *se = to->callees; - for (; se; se = se->next_callee) - if (se->inline_failed && se->callee->comdat_local_p ()) - break; - if (se == NULL) - to->calls_comdat_local = false; - } + to->calls_comdat_local = to->check_calls_comdat_local_p (); /* FIXME: This assert suffers from roundoff errors, disable it for GCC 5 and revisit it after conversion to sreals in GCC 6. diff --git a/gcc/ipa-split.c b/gcc/ipa-split.c index 87a0989..973e72c 100644 --- a/gcc/ipa-split.c +++ b/gcc/ipa-split.c @@ -1363,7 +1363,7 @@ split_function (basic_block return_bb, class split_point *split_point, { /* TODO: call is versionable if we make sure that all callers are inside of a comdat group. */ - cur_node->calls_comdat_local = 1; + cur_node->calls_comdat_local = true; node->add_to_same_comdat_group (cur_node); } diff --git a/gcc/symtab.c b/gcc/symtab.c index a879c09..3022acf 100644 --- a/gcc/symtab.c +++ b/gcc/symtab.c @@ -473,6 +473,17 @@ symtab_node::add_to_same_comdat_group (symtab_node *old_node) ; n->same_comdat_group = this; } + + cgraph_node *n; + if (comdat_local_p () + && (n = dyn_cast (this)) != NULL) + { + for (cgraph_edge *e = n->callers; e; e = e->next_caller) + if (e->caller->inlined_to) + e->caller->inlined_to->calls_comdat_local = true; + else + e->caller->calls_comdat_local = true; + } } /* Dissolve the same_comdat_group list in which NODE resides. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 76b93b5..50c42e2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-03-20 Jan Hubicka + + PR ipa/93347 + * g++.dg/torture/pr93347.C: New test. + 2020-03-20 Patrick Palka PR c++/69694 diff --git a/gcc/testsuite/g++.dg/torture/pr93347.C b/gcc/testsuite/g++.dg/torture/pr93347.C new file mode 100644 index 0000000..3b5cc26 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr93347.C @@ -0,0 +1,306 @@ +// { dg-additional-options "--param early-inlining-insns=3 --param ipa-cp-eval-threshold=100" } + +namespace Test1 { + struct A { + virtual int f() final; + }; + + // CHECK-LABEL: define i32 @_ZN5Test11fEPNS_1AE + int f(A *a) { + // CHECK: call i32 @_ZN5Test11A1fEv + return a->f(); + } +} + +namespace Test2 { + struct A final { + virtual int f(); + }; + + // CHECK-LABEL: define i32 @_ZN5Test21fEPNS_1AE + int f(A *a) { + // CHECK: call i32 @_ZN5Test21A1fEv + return a->f(); + } +} + +namespace Test2a { + struct A { + virtual ~A() final {} + virtual int f(); + }; + + // CHECK-LABEL: define i32 @_ZN6Test2a1fEPNS_1AE + int f(A *a) { + // CHECK: call i32 @_ZN6Test2a1A1fEv + return a->f(); + } +} + + +namespace Test3 { + struct A { + virtual int f(); }; + + struct B final : A { }; + + // CHECK-LABEL: define i32 @_ZN5Test31fEPNS_1BE + int f(B *b) { + // CHECK: call i32 @_ZN5Test31A1fEv + return b->f(); + } + + // CHECK-LABEL: define i32 @_ZN5Test31fERNS_1BE + int f(B &b) { + // CHECK: call i32 @_ZN5Test31A1fEv + return b.f(); + } + + // CHECK-LABEL: define i32 @_ZN5Test31fEPv + int f(void *v) { + // CHECK: call i32 @_ZN5Test31A1fEv + return static_cast(v)->f(); + } +} + +namespace Test4 { + struct A { + virtual void f(); + virtual int operator-(); + }; + + struct B final : A { + virtual void f(); + virtual int operator-(); + }; + + // CHECK-LABEL: define void @_ZN5Test41fEPNS_1BE + void f(B* d) { + // CHECK: call void @_ZN5Test41B1fEv + static_cast(d)->f(); + // CHECK: call i32 @_ZN5Test41BngEv + -static_cast(*d); + } +} + +namespace Test5 { + struct A { + virtual void f(); + virtual int operator-(); + }; + + struct B : A { + virtual void f(); + virtual int operator-(); + }; + + struct C final : B { + }; + + // CHECK-LABEL: define void @_ZN5Test51fEPNS_1CE + void f(C* d) { + // FIXME: It should be possible to devirtualize this case, but that is + // not implemented yet. + // CHECK: getelementptr + // CHECK-NEXT: %[[FUNC:.*]] = load + // CHECK-NEXT: call void %[[FUNC]] + static_cast(d)->f(); + } + // CHECK-LABEL: define void @_ZN5Test53fopEPNS_1CE + void fop(C* d) { + // FIXME: It should be possible to devirtualize this case, but that is + // not implemented yet. + // CHECK: getelementptr + // CHECK-NEXT: %[[FUNC:.*]] = load + // CHECK-NEXT: call i32 %[[FUNC]] + -static_cast(*d); + } +} + +namespace Test6 { + struct A { + virtual ~A(); + }; + + struct B : public A { + virtual ~B(); + }; + + struct C { + virtual ~C(); + }; + + struct D final : public C, public B { + }; + + // CHECK-LABEL: define void @_ZN5Test61fEPNS_1DE + void f(D* d) { + // CHECK: call void @_ZN5Test61DD1Ev + static_cast(d)->~A(); + } +} + +namespace Test7 { + struct foo { + virtual void g() {} + }; + + struct bar { + virtual int f() { return 0; } + }; + + struct zed final : public foo, public bar { + int z; + virtual int f() {return z;} + }; + + // CHECK-LABEL: define i32 @_ZN5Test71fEPNS_3zedE + int f(zed *z) { + // CHECK: alloca + // CHECK-NEXT: store + // CHECK-NEXT: load + // CHECK-NEXT: call i32 @_ZN5Test73zed1fEv + // CHECK-NEXT: ret + return static_cast(z)->f(); + } +} + +namespace Test8 { + struct A { virtual ~A() {} }; + struct B { + int b; + virtual int foo() { return b; } + }; + struct C final : A, B { }; + // CHECK-LABEL: define i32 @_ZN5Test84testEPNS_1CE + int test(C *c) { + // CHECK: %[[THIS:.*]] = phi + // CHECK-NEXT: call i32 @_ZN5Test81B3fooEv(%"struct.Test8::B"* %[[THIS]]) + return static_cast(c)->foo(); + } +} + +namespace Test9 { + struct A { + int a; + }; + struct B { + int b; + }; + struct C : public B, public A { + }; + struct RA { + virtual A *f() { + return 0; + } + virtual A *operator-() { + return 0; + } + }; + struct RC final : public RA { + virtual C *f() { + C *x = new C(); + x->a = 1; + x->b = 2; + return x; + } + virtual C *operator-() { + C *x = new C(); + x->a = 1; + x->b = 2; + return x; + } + }; + // CHECK: define {{.*}} @_ZN5Test91fEPNS_2RCE + A *f(RC *x) { + // FIXME: It should be possible to devirtualize this case, but that is + // not implemented yet. + // CHECK: load + // CHECK: bitcast + // CHECK: [[F_PTR_RA:%.+]] = bitcast + // CHECK: [[VTABLE:%.+]] = load {{.+}} [[F_PTR_RA]] + // CHECK: [[VFN:%.+]] = getelementptr inbounds {{.+}} [[VTABLE]], i{{[0-9]+}} 0 + // CHECK-NEXT: %[[FUNC:.*]] = load {{.+}} [[VFN]] + // CHECK-NEXT: = call {{.*}} %[[FUNC]] + return static_cast(x)->f(); + } + // CHECK: define {{.*}} @_ZN5Test93fopEPNS_2RCE + A *fop(RC *x) { + // FIXME: It should be possible to devirtualize this case, but that is + // not implemented yet. + // CHECK: load + // CHECK: bitcast + // CHECK: [[F_PTR_RA:%.+]] = bitcast + // CHECK: [[VTABLE:%.+]] = load {{.+}} [[F_PTR_RA]] + // CHECK: [[VFN:%.+]] = getelementptr inbounds {{.+}} [[VTABLE]], i{{[0-9]+}} 1 + // CHECK-NEXT: %[[FUNC:.*]] = load {{.+}} [[VFN]] + // CHECK-NEXT: = call {{.*}} %[[FUNC]] + return -static_cast(*x); + } +} + +namespace Test10 { + struct A { + virtual int f(); + }; + + struct B : A { + int f() final; + }; + + // CHECK-LABEL: define i32 @_ZN6Test101fEPNS_1BE + int f(B *b) { + // CHECK: call i32 @_ZN6Test101B1fEv + return static_cast(b)->f(); + } +} + +namespace Test11 { + // Check that the definitions of Derived's operators are emitted. + + // CHECK-LABEL: define linkonce_odr void @_ZN6Test111SIiE4foo1Ev( + // CHECK: call void @_ZN6Test111SIiE7DerivedclEv( + // CHECK: call zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( + // CHECK: call zeroext i1 @_ZN6Test111SIiE7DerivedntEv( + // CHECK: call dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( + // CHECK: define linkonce_odr void @_ZN6Test111SIiE7DerivedclEv( + // CHECK: define linkonce_odr zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( + // CHECK: define linkonce_odr zeroext i1 @_ZN6Test111SIiE7DerivedntEv( + // CHECK: define linkonce_odr dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( + class Base { + public: + virtual void operator()() {} + virtual bool operator==(const Base &other) { return false; } + virtual bool operator!() { return false; } + virtual Base &operator[](int i) { return *this; } + }; + + template + struct S { + class Derived final : public Base { + public: + void operator()() override {} + bool operator==(const Base &other) override { return true; } + bool operator!() override { return true; } + Base &operator[](int i) override { return *this; } + }; + + Derived *ptr = nullptr, *ptr2 = nullptr; + + void foo1() { + if (ptr && ptr2) { + // These calls get devirtualized. Linkage fails if the definitions of + // the called functions are not emitted. + (*ptr)(); + (void)(*ptr == *ptr2); + (void)(!(*ptr)); + (void)((*ptr)[1]); + } + } + }; + + void foo2() { + S *s = new S; + s->foo1(); + } +} -- cgit v1.1 From 68dd57808f7c0147acdb5ca72c88ff655afcb0ce Mon Sep 17 00:00:00 2001 From: Carl Love Date: Fri, 20 Mar 2020 18:15:05 -0500 Subject: rs6000: Add command line and builtin compatibility check 2020-03-20 Carl Love PR/target 87583 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): Add check for TARGET_FPRND for Power 7 or newer. --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7f00a13..2bb7ccc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-20 Carl Love + + PR/target 87583 + * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): + Add check for TARGET_FPRND for Power 7 or newer. + 2020-03-20 Jan Hubicka PR ipa/93347 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4ecf972..07f7cf5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3714,6 +3714,14 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_CRYPTO; } + if (!TARGET_FPRND && TARGET_VSX) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND) + /* TARGET_VSX = 1 implies Power 7 and newer */ + error ("%qs requires %qs", "-mvsx", "-mfprnd"); + rs6000_isa_flags &= ~OPTION_MASK_FPRND; + } + if (TARGET_DIRECT_MOVE && !TARGET_VSX) { if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE) -- cgit v1.1 From cc3afc9db0710fe40e3d9a5e941e5e4efe7227f2 Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Fri, 20 Mar 2020 23:19:02 +0000 Subject: Regenerate gcc.pot. * gcc.pot: Regenerate. --- gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 ++++++++++++++++++++++++++++++++--------------------- 2 files changed, 9168 insertions(+), 6075 deletions(-) (limited to 'gcc') diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index 22e630a..304f796 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2020-03-20 Joseph Myers + + * gcc.pot: Regenerate. + 2020-03-17 Joseph Myers * sv.po: Update. diff --git a/gcc/po/gcc.pot b/gcc/po/gcc.pot index dda77fa..4bf8920 100644 --- a/gcc/po/gcc.pot +++ b/gcc/po/gcc.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" -"POT-Creation-Date: 2020-02-07 22:33+0000\n" +"POT-Creation-Date: 2020-03-20 23:17+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -39,45 +39,45 @@ msgstr "" msgid "[cannot find %s]" msgstr "" -#: collect2.c:1657 +#: collect2.c:1569 #, c-format msgid "collect2 version %s\n" msgstr "" -#: collect2.c:1762 +#: collect2.c:1674 #, c-format msgid "%d constructor found\n" msgid_plural "%d constructors found\n" msgstr[0] "" msgstr[1] "" -#: collect2.c:1766 +#: collect2.c:1678 #, c-format msgid "%d destructor found\n" msgid_plural "%d destructors found\n" msgstr[0] "" msgstr[1] "" -#: collect2.c:1770 +#: collect2.c:1682 #, c-format msgid "%d frame table found\n" msgid_plural "%d frame tables found\n" msgstr[0] "" msgstr[1] "" -#: collect2.c:1935 +#: collect2.c:1837 #, c-format msgid "[Leaving %s]\n" msgstr "" -#: collect2.c:2165 +#: collect2.c:2067 #, c-format msgid "" "\n" "write_c_file - output name is %s, prefix is %s\n" msgstr "" -#: collect2.c:2670 +#: collect2.c:2572 #, c-format msgid "" "\n" @@ -98,52 +98,52 @@ msgstr "" msgid "%s: some warnings being treated as errors" msgstr "" -#: diagnostic.c:371 input.c:225 input.c:1874 c-family/c-opts.c:1427 +#: diagnostic.c:386 input.c:225 input.c:1874 c-family/c-opts.c:1427 #: fortran/cpp.c:577 fortran/error.c:1049 fortran/error.c:1069 msgid "" msgstr "" -#: diagnostic.c:524 +#: diagnostic.c:539 #, c-format msgid "compilation terminated due to -fmax-errors=%u.\n" msgstr "" -#: diagnostic.c:552 +#: diagnostic.c:567 #, c-format msgid "compilation terminated due to -Wfatal-errors.\n" msgstr "" -#: diagnostic.c:572 +#: diagnostic.c:587 #, c-format msgid "" "Please submit a full bug report,\n" "with preprocessed source if appropriate.\n" msgstr "" -#: diagnostic.c:578 +#: diagnostic.c:593 #, c-format msgid "See %s for instructions.\n" msgstr "" -#: diagnostic.c:587 +#: diagnostic.c:602 #, c-format msgid "compilation terminated.\n" msgstr "" -#: diagnostic.c:648 +#: diagnostic.c:663 msgid "In file included from" msgstr "" -#: diagnostic.c:649 +#: diagnostic.c:664 msgid " from" msgstr "" -#: diagnostic.c:1115 +#: diagnostic.c:1135 #, c-format msgid "%s:%d: confused by earlier errors, bailing out\n" msgstr "" -#: diagnostic.c:1740 +#: diagnostic.c:1760 #, c-format msgid "Internal compiler error: Error reporting routines re-entered.\n" msgstr "" @@ -194,13 +194,13 @@ msgstr "" #. PRINT_OPERAND must handle them. #. We can't handle floating point constants; #. TARGET_PRINT_OPERAND must handle them. -#: final.c:4148 config/arc/arc.c:6392 config/i386/i386.c:11497 +#: final.c:4148 config/arc/arc.c:6404 config/i386/i386.c:11740 #, c-format msgid "floating constant misused" msgstr "" -#: final.c:4206 config/arc/arc.c:6489 config/i386/i386.c:11588 -#: config/pdp11/pdp11.c:1873 +#: final.c:4206 config/arc/arc.c:6501 config/i386/i386.c:11831 +#: config/pdp11/pdp11.c:1874 #, c-format msgid "invalid expression as operand" msgstr "" @@ -500,103 +500,103 @@ msgid "" " other options on to these processes the -W options must be used.\n" msgstr "" -#: gcc.c:6031 +#: gcc.c:6059 #, c-format msgid "Processing spec (%s), which is '%s'\n" msgstr "" -#: gcc.c:6781 +#: gcc.c:6809 #, c-format msgid "Target: %s\n" msgstr "" -#: gcc.c:6782 +#: gcc.c:6810 #, c-format msgid "Configured with: %s\n" msgstr "" -#: gcc.c:6796 +#: gcc.c:6824 #, c-format msgid "Thread model: %s\n" msgstr "" -#: gcc.c:6797 +#: gcc.c:6825 #, c-format msgid "Supported LTO compression algorithms: zlib" msgstr "" -#: gcc.c:6799 +#: gcc.c:6827 #, c-format msgid " zstd" msgstr "" -#: gcc.c:6801 gcov.c:1408 gcov.c:1476 gcov.c:2813 +#: gcc.c:6829 gcov.c:1408 gcov.c:1476 gcov.c:2813 #, c-format msgid "\n" msgstr "" -#: gcc.c:6812 +#: gcc.c:6840 #, c-format msgid "gcc version %s %s\n" msgstr "" -#: gcc.c:6815 +#: gcc.c:6843 #, c-format msgid "gcc driver version %s %sexecuting gcc version %s\n" msgstr "" -#: gcc.c:6888 gcc.c:7098 +#: gcc.c:6916 gcc.c:7126 #, c-format msgid "" "The bug is not reproducible, so it is likely a hardware or OS problem.\n" msgstr "" -#: gcc.c:7022 +#: gcc.c:7050 #, c-format msgid "" "Preprocessed source stored into %s file, please attach this to your " "bugreport.\n" msgstr "" -#: gcc.c:7871 +#: gcc.c:7900 #, c-format msgid "install: %s%s\n" msgstr "" -#: gcc.c:7874 +#: gcc.c:7903 #, c-format msgid "programs: %s\n" msgstr "" -#: gcc.c:7876 +#: gcc.c:7905 #, c-format msgid "libraries: %s\n" msgstr "" -#: gcc.c:7993 +#: gcc.c:8022 #, c-format msgid "" "\n" "For bug reporting instructions, please see:\n" msgstr "" -#: gcc.c:8009 gcov-tool.c:527 +#: gcc.c:8038 gcov-tool.c:527 #, c-format msgid "%s %s%s\n" msgstr "" -#: gcc.c:8012 gcov-tool.c:529 gcov.c:927 fortran/gfortranspec.c:282 +#: gcc.c:8041 gcov-tool.c:529 gcov.c:927 fortran/gfortranspec.c:282 msgid "(C)" msgstr "" -#: gcc.c:8013 fortran/gfortranspec.c:283 +#: gcc.c:8042 fortran/gfortranspec.c:283 msgid "" "This is free software; see the source for copying conditions. There is NO\n" "warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n" "\n" msgstr "" -#: gcc.c:8322 +#: gcc.c:8351 #, c-format msgid "" "\n" @@ -605,14 +605,14 @@ msgid "" "\n" msgstr "" -#: gcc.c:8323 +#: gcc.c:8352 #, c-format msgid "" "Use \"-Wl,OPTION\" to pass \"OPTION\" to the linker.\n" "\n" msgstr "" -#: gcc.c:9671 +#: gcc.c:9700 #, c-format msgid "" "Assembler options\n" @@ -620,7 +620,7 @@ msgid "" "\n" msgstr "" -#: gcc.c:9672 +#: gcc.c:9701 #, c-format msgid "" "Use \"-Wa,OPTION\" to pass \"OPTION\" to the assembler.\n" @@ -1178,25 +1178,25 @@ msgstr "" msgid "At top level:" msgstr "" -#: langhooks.c:397 cp/error.c:3480 +#: langhooks.c:397 cp/error.c:3478 #, c-format msgid "In member function %qs" msgstr "" -#: langhooks.c:401 cp/error.c:3483 +#: langhooks.c:401 cp/error.c:3481 #, c-format msgid "In function %qs" msgstr "" -#: langhooks.c:446 cp/error.c:3433 +#: langhooks.c:446 cp/error.c:3431 msgid " inlined from %qs at %r%s:%d:%d%R" msgstr "" -#: langhooks.c:451 cp/error.c:3438 +#: langhooks.c:451 cp/error.c:3436 msgid " inlined from %qs at %r%s:%d%R" msgstr "" -#: langhooks.c:457 cp/error.c:3444 +#: langhooks.c:457 cp/error.c:3442 #, c-format msgid " inlined from %qs" msgstr "" @@ -1222,12 +1222,12 @@ msgstr "" msgid "Uses of this option are diagnosed." msgstr "" -#: opts.c:1321 +#: opts.c:1324 #, c-format msgid "Same as %s. Use the latter option instead." msgstr "" -#: opts.c:1329 +#: opts.c:1332 #, c-format msgid "%s Same as %s." msgstr "" @@ -1322,12 +1322,12 @@ msgstr "" msgid "The following options are language-related" msgstr "" -#: passes.c:1783 +#: passes.c:1785 #, c-format msgid "during %s pass: %s\n" msgstr "" -#: passes.c:1788 +#: passes.c:1790 #, c-format msgid "dump file: %s\n" msgstr "" @@ -1427,7 +1427,7 @@ msgstr "" msgid "options enabled: " msgstr "" -#: tree-diagnostic.c:299 c/c-decl.c:5724 c/c-typeck.c:7637 cp/error.c:1074 +#: tree-diagnostic.c:299 c/c-decl.c:5758 c/c-typeck.c:7658 cp/error.c:1073 #: tree-diagnostic-path.cc:261 c-family/c-pretty-print.c:413 #, gcc-internal-format msgid "" @@ -1873,79 +1873,79 @@ msgstr "" msgid "" msgstr "" -#: config/aarch64/aarch64.c:9428 +#: config/aarch64/aarch64.c:9459 #, c-format msgid "unsupported operand for code '%c'" msgstr "" -#: config/aarch64/aarch64.c:9437 config/aarch64/aarch64.c:9450 -#: config/aarch64/aarch64.c:9462 config/aarch64/aarch64.c:9473 -#: config/aarch64/aarch64.c:9489 config/aarch64/aarch64.c:9503 -#: config/aarch64/aarch64.c:9523 config/aarch64/aarch64.c:9597 -#: config/aarch64/aarch64.c:9608 config/aarch64/aarch64.c:9622 -#: config/aarch64/aarch64.c:9844 config/aarch64/aarch64.c:9862 +#: config/aarch64/aarch64.c:9468 config/aarch64/aarch64.c:9481 +#: config/aarch64/aarch64.c:9493 config/aarch64/aarch64.c:9504 +#: config/aarch64/aarch64.c:9520 config/aarch64/aarch64.c:9534 +#: config/aarch64/aarch64.c:9554 config/aarch64/aarch64.c:9628 +#: config/aarch64/aarch64.c:9639 config/aarch64/aarch64.c:9653 +#: config/aarch64/aarch64.c:9875 config/aarch64/aarch64.c:9893 #: config/pru/pru.c:1700 config/pru/pru.c:1710 config/pru/pru.c:1741 #: config/pru/pru.c:1752 config/pru/pru.c:1824 #, c-format msgid "invalid operand for '%%%c'" msgstr "" -#: config/aarch64/aarch64.c:9541 config/aarch64/aarch64.c:9552 -#: config/aarch64/aarch64.c:9704 config/aarch64/aarch64.c:9715 +#: config/aarch64/aarch64.c:9572 config/aarch64/aarch64.c:9583 +#: config/aarch64/aarch64.c:9735 config/aarch64/aarch64.c:9746 #, c-format msgid "invalid vector constant" msgstr "" -#: config/aarch64/aarch64.c:9564 config/aarch64/aarch64.c:9576 +#: config/aarch64/aarch64.c:9595 config/aarch64/aarch64.c:9607 #, c-format msgid "incompatible floating point / vector register operand for '%%%c'" msgstr "" -#: config/aarch64/aarch64.c:9590 +#: config/aarch64/aarch64.c:9621 #, c-format msgid "incompatible register operand for '%%%c'" msgstr "" -#: config/aarch64/aarch64.c:9656 config/arm/arm.c:23933 +#: config/aarch64/aarch64.c:9687 config/arm/arm.c:24031 #, c-format msgid "missing operand" msgstr "" -#: config/aarch64/aarch64.c:9741 +#: config/aarch64/aarch64.c:9772 #, c-format msgid "invalid constant" msgstr "" -#: config/aarch64/aarch64.c:9744 +#: config/aarch64/aarch64.c:9775 #, c-format msgid "invalid operand" msgstr "" -#: config/aarch64/aarch64.c:9870 config/aarch64/aarch64.c:9875 +#: config/aarch64/aarch64.c:9901 config/aarch64/aarch64.c:9906 #, c-format msgid "invalid operand prefix '%%%c'" msgstr "" -#: config/aarch64/aarch64.c:9895 +#: config/aarch64/aarch64.c:9926 #, c-format msgid "invalid address mode" msgstr "" -#: config/aarch64/aarch64.c:21877 config/arm/arm.c:32832 +#: config/aarch64/aarch64.c:21967 config/arm/arm.c:33015 msgid "invalid conversion from type %" msgstr "" -#: config/aarch64/aarch64.c:21879 config/arm/arm.c:32834 +#: config/aarch64/aarch64.c:21969 config/arm/arm.c:33017 msgid "invalid conversion to type %" msgstr "" -#: config/aarch64/aarch64.c:21894 config/aarch64/aarch64.c:21910 -#: config/arm/arm.c:32849 config/arm/arm.c:32865 +#: config/aarch64/aarch64.c:21984 config/aarch64/aarch64.c:22000 +#: config/arm/arm.c:33032 config/arm/arm.c:33048 msgid "operation not permitted on type %" msgstr "" -#: config/alpha/alpha.c:5076 config/i386/i386.c:12789 -#: config/rs6000/rs6000.c:13261 config/sparc/sparc.c:9354 +#: config/alpha/alpha.c:5076 config/i386/i386.c:13032 +#: config/rs6000/rs6000.c:13258 config/sparc/sparc.c:9351 #, c-format msgid "'%%&' used without any local dynamic TLS references" msgstr "" @@ -1961,18 +1961,18 @@ msgid "invalid %%r value" msgstr "" #: config/alpha/alpha.c:5174 config/ia64/ia64.c:5531 -#: config/rs6000/rs6000.c:12955 config/xtensa/xtensa.c:2428 +#: config/rs6000/rs6000.c:12952 config/xtensa/xtensa.c:2428 #, c-format msgid "invalid %%R value" msgstr "" -#: config/alpha/alpha.c:5180 config/rs6000/rs6000.c:12875 +#: config/alpha/alpha.c:5180 config/rs6000/rs6000.c:12872 #: config/xtensa/xtensa.c:2395 #, c-format msgid "invalid %%N value" msgstr "" -#: config/alpha/alpha.c:5188 config/rs6000/rs6000.c:12903 +#: config/alpha/alpha.c:5188 config/rs6000/rs6000.c:12900 #, c-format msgid "invalid %%P value" msgstr "" @@ -2002,7 +2002,7 @@ msgstr "" msgid "invalid %%U value" msgstr "" -#: config/alpha/alpha.c:5274 config/rs6000/rs6000.c:12963 +#: config/alpha/alpha.c:5274 config/rs6000/rs6000.c:12960 #, c-format msgid "invalid %%s value" msgstr "" @@ -2012,7 +2012,7 @@ msgstr "" msgid "invalid %%C value" msgstr "" -#: config/alpha/alpha.c:5322 config/rs6000/rs6000.c:12739 +#: config/alpha/alpha.c:5322 config/rs6000/rs6000.c:12736 #, c-format msgid "invalid %%E value" msgstr "" @@ -2022,10 +2022,10 @@ msgstr "" msgid "unknown relocation unspec" msgstr "" -#: config/alpha/alpha.c:5356 config/cr16/cr16.c:1570 config/gcn/gcn.c:5678 -#: config/gcn/gcn.c:5687 config/gcn/gcn.c:5747 config/gcn/gcn.c:5755 -#: config/gcn/gcn.c:5771 config/gcn/gcn.c:5789 config/gcn/gcn.c:5840 -#: config/gcn/gcn.c:5944 config/gcn/gcn.c:6055 config/rs6000/rs6000.c:13266 +#: config/alpha/alpha.c:5356 config/cr16/cr16.c:1570 config/gcn/gcn.c:5748 +#: config/gcn/gcn.c:5757 config/gcn/gcn.c:5817 config/gcn/gcn.c:5825 +#: config/gcn/gcn.c:5841 config/gcn/gcn.c:5859 config/gcn/gcn.c:5910 +#: config/gcn/gcn.c:6014 config/gcn/gcn.c:6125 config/rs6000/rs6000.c:13263 #, c-format msgid "invalid %%xn code" msgstr "" @@ -2035,107 +2035,107 @@ msgstr "" msgid "invalid operand address" msgstr "" -#: config/arc/arc.c:4507 +#: config/arc/arc.c:4519 #, c-format msgid "invalid operand to %%Z code" msgstr "" -#: config/arc/arc.c:4515 +#: config/arc/arc.c:4527 #, c-format msgid "invalid operand to %%z code" msgstr "" -#: config/arc/arc.c:4523 +#: config/arc/arc.c:4535 #, c-format msgid "invalid operands to %%c code" msgstr "" -#: config/arc/arc.c:4531 +#: config/arc/arc.c:4543 #, c-format msgid "invalid operand to %%M code" msgstr "" -#: config/arc/arc.c:4539 config/m32r/m32r.c:2085 +#: config/arc/arc.c:4551 config/m32r/m32r.c:2085 #, c-format msgid "invalid operand to %%p code" msgstr "" -#: config/arc/arc.c:4550 config/m32r/m32r.c:2078 +#: config/arc/arc.c:4562 config/m32r/m32r.c:2078 #, c-format msgid "invalid operand to %%s code" msgstr "" -#: config/arc/arc.c:4698 config/m32r/m32r.c:2111 +#: config/arc/arc.c:4710 config/m32r/m32r.c:2111 #, c-format msgid "invalid operand to %%R code" msgstr "" -#: config/arc/arc.c:4774 config/m32r/m32r.c:2134 +#: config/arc/arc.c:4786 config/m32r/m32r.c:2134 #, c-format msgid "invalid operand to %%H/%%L code" msgstr "" -#: config/arc/arc.c:4842 config/m32r/m32r.c:2205 +#: config/arc/arc.c:4854 config/m32r/m32r.c:2205 #, c-format msgid "invalid operand to %%U code" msgstr "" -#: config/arc/arc.c:4854 +#: config/arc/arc.c:4866 #, c-format msgid "invalid operand to %%V code" msgstr "" -#: config/arc/arc.c:4911 +#: config/arc/arc.c:4923 #, c-format msgid "invalid operand to %%O code" msgstr "" #. Unknown flag. #. Undocumented flag. -#: config/arc/arc.c:4937 config/epiphany/epiphany.c:1307 -#: config/m32r/m32r.c:2232 config/nds32/nds32.c:3517 config/sparc/sparc.c:9633 +#: config/arc/arc.c:4949 config/epiphany/epiphany.c:1307 +#: config/m32r/m32r.c:2232 config/nds32/nds32.c:3517 config/sparc/sparc.c:9630 #, c-format msgid "invalid operand output code" msgstr "" -#: config/arc/arc.c:6477 +#: config/arc/arc.c:6489 #, c-format msgid "invalid UNSPEC as operand: %d" msgstr "" -#: config/arc/arc.c:6693 config/cris/cris.c:2571 +#: config/arc/arc.c:6705 config/cris/cris.c:2571 msgid "unrecognized supposed constant" msgstr "" -#: config/arm/arm.c:20348 config/arm/arm.c:20373 config/arm/arm.c:20383 -#: config/arm/arm.c:20392 config/arm/arm.c:20401 +#: config/arm/arm.c:20399 config/arm/arm.c:20424 config/arm/arm.c:20434 +#: config/arm/arm.c:20443 config/arm/arm.c:20452 #, c-format msgid "invalid shift operand" msgstr "" -#: config/arm/arm.c:23264 config/arm/arm.c:23282 +#: config/arm/arm.c:23315 config/arm/arm.c:23333 #, c-format msgid "predicated Thumb instruction" msgstr "" -#: config/arm/arm.c:23270 +#: config/arm/arm.c:23321 #, c-format msgid "predicated instruction in conditional sequence" msgstr "" -#: config/arm/arm.c:23388 config/arm/arm.c:23401 config/arm/arm.c:23426 +#: config/arm/arm.c:23439 config/arm/arm.c:23452 config/arm/arm.c:23477 #: config/nios2/nios2.c:3086 #, c-format msgid "Unsupported operand for code '%c'" msgstr "" -#: config/arm/arm.c:23503 config/arm/arm.c:23525 config/arm/arm.c:23535 -#: config/arm/arm.c:23545 config/arm/arm.c:23555 config/arm/arm.c:23594 -#: config/arm/arm.c:23612 config/arm/arm.c:23637 config/arm/arm.c:23652 -#: config/arm/arm.c:23679 config/arm/arm.c:23686 config/arm/arm.c:23704 -#: config/arm/arm.c:23711 config/arm/arm.c:23719 config/arm/arm.c:23740 -#: config/arm/arm.c:23747 config/arm/arm.c:23880 config/arm/arm.c:23887 -#: config/arm/arm.c:23914 config/arm/arm.c:23921 config/bfin/bfin.c:1440 +#: config/arm/arm.c:23554 config/arm/arm.c:23576 config/arm/arm.c:23586 +#: config/arm/arm.c:23596 config/arm/arm.c:23606 config/arm/arm.c:23645 +#: config/arm/arm.c:23663 config/arm/arm.c:23688 config/arm/arm.c:23703 +#: config/arm/arm.c:23730 config/arm/arm.c:23737 config/arm/arm.c:23755 +#: config/arm/arm.c:23762 config/arm/arm.c:23770 config/arm/arm.c:23791 +#: config/arm/arm.c:23798 config/arm/arm.c:23978 config/arm/arm.c:23985 +#: config/arm/arm.c:24012 config/arm/arm.c:24019 config/bfin/bfin.c:1440 #: config/bfin/bfin.c:1447 config/bfin/bfin.c:1454 config/bfin/bfin.c:1461 #: config/bfin/bfin.c:1470 config/bfin/bfin.c:1477 config/bfin/bfin.c:1484 #: config/bfin/bfin.c:1491 config/nds32/nds32.c:3543 @@ -2143,13 +2143,13 @@ msgstr "" msgid "invalid operand for code '%c'" msgstr "" -#: config/arm/arm.c:23607 +#: config/arm/arm.c:23658 #, c-format msgid "instruction never executed" msgstr "" #. Former Maverick support, removed after GCC-4.7. -#: config/arm/arm.c:23628 +#: config/arm/arm.c:23679 #, c-format msgid "obsolete Maverick format code '%c'" msgstr "" @@ -2268,8 +2268,8 @@ msgid "unsupported operand" msgstr "" #: config/cris/cris.c:625 config/ft32/ft32.c:110 config/moxie/moxie.c:108 -#: final.c:3607 final.c:3609 fold-const.c:266 gcc.c:5395 gcc.c:5409 -#: rtl-error.c:101 toplev.c:328 vr-values.c:2486 cp/typeck.c:6739 +#: final.c:3607 final.c:3609 fold-const.c:266 gcc.c:5423 gcc.c:5437 +#: rtl-error.c:101 toplev.c:328 vr-values.c:2486 cp/typeck.c:6747 #: lto/lto-object.c:184 lto/lto-object.c:281 lto/lto-object.c:338 #: lto/lto-object.c:362 #, gcc-internal-format, gfc-internal-format @@ -2353,11 +2353,11 @@ msgid "unexpected side-effects in address" msgstr "" #. Can't possibly get anything else for a function-call, right? -#: config/cris/cris.c:3862 +#: config/cris/cris.c:3919 msgid "unidentifiable call op" msgstr "" -#: config/cris/cris.c:3924 +#: config/cris/cris.c:3981 #, c-format msgid "PIC register isn't set up" msgstr "" @@ -2486,25 +2486,25 @@ msgstr "" msgid "bad output_condmove_single operand" msgstr "" -#: config/gcn/gcn.c:5368 config/gcn/gcn.c:5392 config/gcn/gcn.c:5396 -#: config/gcn/gcn.c:5720 config/gcn/gcn.c:5731 config/gcn/gcn.c:5734 +#: config/gcn/gcn.c:5418 config/gcn/gcn.c:5442 config/gcn/gcn.c:5446 +#: config/gcn/gcn.c:5790 config/gcn/gcn.c:5801 config/gcn/gcn.c:5804 #, c-format msgid "bad ADDR_SPACE_GLOBAL address" msgstr "" -#: config/gcn/gcn.c:5506 config/gcn/gcn.c:5529 config/gcn/gcn.c:5558 -#: config/gcn/gcn.c:5574 config/gcn/gcn.c:5593 config/gcn/gcn.c:5669 -#: config/gcn/gcn.c:5865 config/gcn/gcn.c:5965 +#: config/gcn/gcn.c:5558 config/gcn/gcn.c:5581 config/gcn/gcn.c:5613 +#: config/gcn/gcn.c:5629 config/gcn/gcn.c:5644 config/gcn/gcn.c:5663 +#: config/gcn/gcn.c:5739 config/gcn/gcn.c:5935 config/gcn/gcn.c:6035 #, c-format msgid "invalid operand %%xn code" msgstr "" -#: config/gcn/gcn.c:5953 +#: config/gcn/gcn.c:6023 #, c-format msgid "operand %%xn code invalid for QImode" msgstr "" -#: config/gcn/gcn.c:6035 +#: config/gcn/gcn.c:6105 #, c-format msgid "invalid fp constant" msgstr "" @@ -2516,103 +2516,103 @@ msgstr "" msgid "Expected register or constant integer." msgstr "" -#: config/i386/i386.c:11582 +#: config/i386/i386.c:11825 #, c-format msgid "invalid UNSPEC as operand" msgstr "" -#: config/i386/i386.c:12121 +#: config/i386/i386.c:12364 #, c-format msgid "invalid use of register '%s'" msgstr "" -#: config/i386/i386.c:12126 +#: config/i386/i386.c:12369 #, c-format msgid "invalid use of asm flag output" msgstr "" -#: config/i386/i386.c:12357 +#: config/i386/i386.c:12600 #, c-format msgid "invalid operand size for operand code 'O'" msgstr "" -#: config/i386/i386.c:12392 +#: config/i386/i386.c:12635 #, c-format msgid "invalid operand size for operand code 'z'" msgstr "" -#: config/i386/i386.c:12461 +#: config/i386/i386.c:12704 #, c-format msgid "invalid operand type used with operand code 'Z'" msgstr "" -#: config/i386/i386.c:12466 +#: config/i386/i386.c:12709 #, c-format msgid "invalid operand size for operand code 'Z'" msgstr "" -#: config/i386/i386.c:12521 +#: config/i386/i386.c:12764 #, c-format msgid "operand is not a condition code, invalid operand code 'I'" msgstr "" -#: config/i386/i386.c:12577 +#: config/i386/i386.c:12820 #, c-format msgid "operand is not a condition code, invalid operand code 'Y'" msgstr "" -#: config/i386/i386.c:12656 +#: config/i386/i386.c:12899 #, c-format msgid "operand is not a condition code, invalid operand code 'D'" msgstr "" -#: config/i386/i386.c:12674 +#: config/i386/i386.c:12917 #, c-format msgid "operand is not a condition code, invalid operand code '%c'" msgstr "" -#: config/i386/i386.c:12687 +#: config/i386/i386.c:12930 #, c-format msgid "" "operand is not an offsettable memory reference, invalid operand code 'H'" msgstr "" -#: config/i386/i386.c:12702 +#: config/i386/i386.c:12945 #, c-format msgid "operand is not an integer, invalid operand code 'K'" msgstr "" -#: config/i386/i386.c:12730 +#: config/i386/i386.c:12973 #, c-format msgid "operand is not a specific integer, invalid operand code 'r'" msgstr "" -#: config/i386/i386.c:12748 +#: config/i386/i386.c:12991 #, c-format msgid "operand is not an integer, invalid operand code 'R'" msgstr "" -#: config/i386/i386.c:12771 +#: config/i386/i386.c:13014 #, c-format msgid "operand is not a specific integer, invalid operand code 'R'" msgstr "" -#: config/i386/i386.c:12875 +#: config/i386/i386.c:13118 #, c-format msgid "invalid operand code '%c'" msgstr "" -#: config/i386/i386.c:12937 +#: config/i386/i386.c:13180 #, c-format msgid "invalid constraints for operand" msgstr "" -#: config/i386/i386.c:12987 +#: config/i386/i386.c:13230 #, c-format msgid "invalid vector immediate" msgstr "" -#: config/i386/i386.c:15915 +#: config/i386/i386.c:16158 msgid "unknown insn mode" msgstr "" @@ -2649,7 +2649,7 @@ msgstr "" msgid "invalid %%P operand" msgstr "" -#: config/iq2000/iq2000.c:3134 config/rs6000/rs6000.c:12893 +#: config/iq2000/iq2000.c:3134 config/rs6000/rs6000.c:12890 #, c-format msgid "invalid %%p value" msgstr "" @@ -2702,7 +2702,7 @@ msgstr "" msgid "post-increment address is not a register" msgstr "" -#: config/m32r/m32r.c:2335 config/m32r/m32r.c:2350 config/rs6000/rs6000.c:19557 +#: config/m32r/m32r.c:2335 config/m32r/m32r.c:2350 config/rs6000/rs6000.c:19558 msgid "bad address" msgstr "" @@ -2754,8 +2754,8 @@ msgstr "" #: config/mips/mips.c:9084 config/mips/mips.c:9087 config/mips/mips.c:9099 #: config/mips/mips.c:9102 config/mips/mips.c:9162 config/mips/mips.c:9169 #: config/mips/mips.c:9190 config/mips/mips.c:9205 config/mips/mips.c:9224 -#: config/mips/mips.c:9233 config/riscv/riscv.c:3197 config/riscv/riscv.c:3312 -#: config/riscv/riscv.c:3318 config/riscv/riscv.c:3327 +#: config/mips/mips.c:9233 config/riscv/riscv.c:3209 config/riscv/riscv.c:3324 +#: config/riscv/riscv.c:3330 config/riscv/riscv.c:3339 #, c-format msgid "invalid use of '%%%c'" msgstr "" @@ -2886,257 +2886,257 @@ msgstr "" msgid "Try running '%s' in the shell to raise its limit.\n" msgstr "" -#: config/rs6000/rs6000.c:3623 +#: config/rs6000/rs6000.c:3622 msgid "%<-mvsx%> requires hardware floating point" msgstr "" -#: config/rs6000/rs6000.c:3631 +#: config/rs6000/rs6000.c:3630 msgid "%<-mvsx%> needs indexed addressing" msgstr "" -#: config/rs6000/rs6000.c:3636 +#: config/rs6000/rs6000.c:3635 msgid "%<-mvsx%> and %<-mno-altivec%> are incompatible" msgstr "" -#: config/rs6000/rs6000.c:3638 +#: config/rs6000/rs6000.c:3637 msgid "%<-mno-altivec%> disables vsx" msgstr "" -#: config/rs6000/rs6000.c:3764 +#: config/rs6000/rs6000.c:3763 msgid "%<-mquad-memory%> requires 64-bit mode" msgstr "" -#: config/rs6000/rs6000.c:3767 +#: config/rs6000/rs6000.c:3766 msgid "%<-mquad-memory-atomic%> requires 64-bit mode" msgstr "" -#: config/rs6000/rs6000.c:3779 +#: config/rs6000/rs6000.c:3778 msgid "%<-mquad-memory%> is not available in little endian mode" msgstr "" -#: config/rs6000/rs6000.c:9988 +#: config/rs6000/rs6000.c:9985 msgid "bad move" msgstr "" -#: config/rs6000/rs6000.c:12531 +#: config/rs6000/rs6000.c:12528 msgid "Bad 128-bit move" msgstr "" -#: config/rs6000/rs6000.c:12712 config/xtensa/xtensa.c:2371 +#: config/rs6000/rs6000.c:12709 config/xtensa/xtensa.c:2371 #, c-format msgid "invalid %%D value" msgstr "" -#: config/rs6000/rs6000.c:12727 +#: config/rs6000/rs6000.c:12724 #, c-format msgid "invalid %%e value" msgstr "" -#: config/rs6000/rs6000.c:12748 +#: config/rs6000/rs6000.c:12745 #, c-format msgid "invalid %%f value" msgstr "" -#: config/rs6000/rs6000.c:12757 +#: config/rs6000/rs6000.c:12754 #, c-format msgid "invalid %%F value" msgstr "" -#: config/rs6000/rs6000.c:12766 +#: config/rs6000/rs6000.c:12763 #, c-format msgid "invalid %%G value" msgstr "" -#: config/rs6000/rs6000.c:12801 +#: config/rs6000/rs6000.c:12798 #, c-format msgid "invalid %%j code" msgstr "" -#: config/rs6000/rs6000.c:12811 +#: config/rs6000/rs6000.c:12808 #, c-format msgid "invalid %%J code" msgstr "" -#: config/rs6000/rs6000.c:12821 +#: config/rs6000/rs6000.c:12818 #, c-format msgid "invalid %%k value" msgstr "" -#: config/rs6000/rs6000.c:12836 config/xtensa/xtensa.c:2414 +#: config/rs6000/rs6000.c:12833 config/xtensa/xtensa.c:2414 #, c-format msgid "invalid %%K value" msgstr "" -#: config/rs6000/rs6000.c:12883 +#: config/rs6000/rs6000.c:12880 #, c-format msgid "invalid %%O value" msgstr "" -#: config/rs6000/rs6000.c:12930 +#: config/rs6000/rs6000.c:12927 #, c-format msgid "invalid %%q value" msgstr "" -#: config/rs6000/rs6000.c:12972 +#: config/rs6000/rs6000.c:12969 #, c-format msgid "invalid %%t value" msgstr "" -#: config/rs6000/rs6000.c:12989 +#: config/rs6000/rs6000.c:12986 #, c-format msgid "invalid %%T value" msgstr "" -#: config/rs6000/rs6000.c:13001 +#: config/rs6000/rs6000.c:12998 #, c-format msgid "invalid %%u value" msgstr "" -#: config/rs6000/rs6000.c:13015 config/xtensa/xtensa.c:2383 +#: config/rs6000/rs6000.c:13012 config/xtensa/xtensa.c:2383 #, c-format msgid "invalid %%v value" msgstr "" -#: config/rs6000/rs6000.c:13065 +#: config/rs6000/rs6000.c:13062 #, c-format msgid "invalid %%V value" msgstr "" -#: config/rs6000/rs6000.c:13082 config/xtensa/xtensa.c:2435 +#: config/rs6000/rs6000.c:13079 config/xtensa/xtensa.c:2435 #, c-format msgid "invalid %%x value" msgstr "" -#: config/rs6000/rs6000.c:13139 +#: config/rs6000/rs6000.c:13136 #, c-format msgid "invalid %%z value" msgstr "" -#: config/rs6000/rs6000.c:13208 +#: config/rs6000/rs6000.c:13205 #, c-format msgid "invalid %%y value, try using the 'Z' constraint" msgstr "" -#: config/rs6000/rs6000.c:14052 +#: config/rs6000/rs6000.c:14049 msgid "__float128 and __ibm128 cannot be used in the same expression" msgstr "" -#: config/rs6000/rs6000.c:14058 +#: config/rs6000/rs6000.c:14055 msgid "__ibm128 and long double cannot be used in the same expression" msgstr "" -#: config/rs6000/rs6000.c:14064 +#: config/rs6000/rs6000.c:14061 msgid "__float128 and long double cannot be used in the same expression" msgstr "" -#: config/rs6000/rs6000.c:22816 +#: config/rs6000/rs6000.c:22817 msgid "AltiVec argument passed to unprototyped function" msgstr "" -#: config/rs6000/rs6000.c:25739 +#: config/rs6000/rs6000.c:25741 msgid "Could not generate addis value for fusion" msgstr "" -#: config/rs6000/rs6000.c:25808 +#: config/rs6000/rs6000.c:25810 msgid "Unable to generate load/store offset for fusion" msgstr "" -#: config/rs6000/rs6000.c:25884 +#: config/rs6000/rs6000.c:25886 msgid "Bad GPR fusion" msgstr "" -#: config/s390/s390.c:7786 +#: config/s390/s390.c:7787 #, c-format msgid "symbolic memory references are only supported on z10 or later" msgstr "" -#: config/s390/s390.c:7797 +#: config/s390/s390.c:7798 #, c-format msgid "cannot decompose address" msgstr "" -#: config/s390/s390.c:7879 +#: config/s390/s390.c:7880 #, c-format msgid "invalid comparison operator for 'E' output modifier" msgstr "" -#: config/s390/s390.c:7902 +#: config/s390/s390.c:7903 #, c-format msgid "invalid reference for 'J' output modifier" msgstr "" -#: config/s390/s390.c:7920 +#: config/s390/s390.c:7921 #, c-format msgid "invalid address for 'O' output modifier" msgstr "" -#: config/s390/s390.c:7942 +#: config/s390/s390.c:7943 #, c-format msgid "invalid address for 'R' output modifier" msgstr "" -#: config/s390/s390.c:7960 +#: config/s390/s390.c:7961 #, c-format msgid "memory reference expected for 'S' output modifier" msgstr "" -#: config/s390/s390.c:7970 +#: config/s390/s390.c:7971 #, c-format msgid "invalid address for 'S' output modifier" msgstr "" -#: config/s390/s390.c:7991 +#: config/s390/s390.c:7992 #, c-format msgid "register or memory expression expected for 'N' output modifier" msgstr "" -#: config/s390/s390.c:8002 +#: config/s390/s390.c:8003 #, c-format msgid "register or memory expression expected for 'M' output modifier" msgstr "" -#: config/s390/s390.c:8088 config/s390/s390.c:8109 +#: config/s390/s390.c:8089 config/s390/s390.c:8110 #, c-format msgid "invalid constant for output modifier '%c'" msgstr "" -#: config/s390/s390.c:8106 +#: config/s390/s390.c:8107 #, c-format msgid "invalid constant - try using an output modifier" msgstr "" -#: config/s390/s390.c:8143 +#: config/s390/s390.c:8144 #, c-format msgid "invalid constant vector for output modifier '%c'" msgstr "" -#: config/s390/s390.c:8150 +#: config/s390/s390.c:8151 #, c-format msgid "invalid expression - try using an output modifier" msgstr "" -#: config/s390/s390.c:8153 +#: config/s390/s390.c:8154 #, c-format msgid "invalid expression for output modifier '%c'" msgstr "" -#: config/s390/s390.c:11865 +#: config/s390/s390.c:11873 msgid "vector argument passed to unprototyped function" msgstr "" -#: config/s390/s390.c:16142 +#: config/s390/s390.c:16170 msgid "types differ in signedness" msgstr "" -#: config/s390/s390.c:16152 +#: config/s390/s390.c:16180 msgid "binary operator does not support two vector bool operands" msgstr "" -#: config/s390/s390.c:16155 +#: config/s390/s390.c:16183 msgid "binary operator does not support vector bool operand" msgstr "" -#: config/s390/s390.c:16163 +#: config/s390/s390.c:16191 msgid "" "binary operator does not support mixing vector bool with floating point " "vector operands" @@ -3164,43 +3164,43 @@ msgstr "" msgid "created and used with different endianness" msgstr "" -#: config/sparc/sparc.c:9363 config/sparc/sparc.c:9369 +#: config/sparc/sparc.c:9360 config/sparc/sparc.c:9366 #, c-format msgid "invalid %%Y operand" msgstr "" -#: config/sparc/sparc.c:9456 +#: config/sparc/sparc.c:9453 #, c-format msgid "invalid %%A operand" msgstr "" -#: config/sparc/sparc.c:9476 +#: config/sparc/sparc.c:9473 #, c-format msgid "invalid %%B operand" msgstr "" -#: config/sparc/sparc.c:9556 config/tilegx/tilegx.c:5090 +#: config/sparc/sparc.c:9553 config/tilegx/tilegx.c:5090 #: config/tilepro/tilepro.c:4499 #, c-format msgid "invalid %%C operand" msgstr "" -#: config/sparc/sparc.c:9588 config/tilegx/tilegx.c:5123 +#: config/sparc/sparc.c:9585 config/tilegx/tilegx.c:5123 #, c-format msgid "invalid %%D operand" msgstr "" -#: config/sparc/sparc.c:9607 +#: config/sparc/sparc.c:9604 #, c-format msgid "invalid %%f operand" msgstr "" -#: config/sparc/sparc.c:9619 +#: config/sparc/sparc.c:9616 #, c-format msgid "invalid %%s operand" msgstr "" -#: config/sparc/sparc.c:9664 +#: config/sparc/sparc.c:9661 #, c-format msgid "floating-point constant not a valid immediate operand" msgstr "" @@ -3391,180 +3391,180 @@ msgstr "" #. ; #. <~~~~~~~~~ declaration ~~~~~~~~~~> #. Use c_parser_require to get an error with a fix-it hint. -#: c/c-parser.c:2429 c/c-parser.c:2546 c/c-parser.c:2560 c/c-parser.c:5668 -#: c/c-parser.c:6296 c/c-parser.c:6746 c/c-parser.c:6925 c/c-parser.c:6959 -#: c/c-parser.c:7216 c/c-parser.c:11002 c/c-parser.c:11037 c/c-parser.c:11068 -#: c/c-parser.c:11115 c/c-parser.c:11296 c/c-parser.c:12082 c/c-parser.c:12152 -#: c/c-parser.c:12195 c/c-parser.c:17629 c/c-parser.c:17653 c/c-parser.c:17671 -#: c/c-parser.c:18093 c/c-parser.c:18143 c/gimple-parser.c:391 -#: c/gimple-parser.c:432 c/gimple-parser.c:441 c/gimple-parser.c:649 -#: c/gimple-parser.c:2192 c/gimple-parser.c:2229 c/gimple-parser.c:2308 -#: c/gimple-parser.c:2335 c/c-parser.c:3239 c/c-parser.c:3426 c/c-parser.c:3459 -#: c/c-parser.c:11289 c/gimple-parser.c:2026 c/gimple-parser.c:2065 -#: cp/parser.c:29886 cp/parser.c:30479 +#: c/c-parser.c:2428 c/c-parser.c:2548 c/c-parser.c:2562 c/c-parser.c:5673 +#: c/c-parser.c:6304 c/c-parser.c:6754 c/c-parser.c:6933 c/c-parser.c:6967 +#: c/c-parser.c:7224 c/c-parser.c:11010 c/c-parser.c:11045 c/c-parser.c:11076 +#: c/c-parser.c:11123 c/c-parser.c:11304 c/c-parser.c:12090 c/c-parser.c:12160 +#: c/c-parser.c:12203 c/c-parser.c:17637 c/c-parser.c:17661 c/c-parser.c:17679 +#: c/c-parser.c:18101 c/c-parser.c:18151 c/gimple-parser.c:392 +#: c/gimple-parser.c:433 c/gimple-parser.c:442 c/gimple-parser.c:650 +#: c/gimple-parser.c:2193 c/gimple-parser.c:2230 c/gimple-parser.c:2309 +#: c/gimple-parser.c:2336 c/c-parser.c:3241 c/c-parser.c:3428 c/c-parser.c:3461 +#: c/c-parser.c:11297 c/gimple-parser.c:2027 c/gimple-parser.c:2066 +#: cp/parser.c:29893 cp/parser.c:30486 #, gcc-internal-format msgid "expected %<;%>" msgstr "" -#: c/c-parser.c:3009 c/c-parser.c:3984 c/c-parser.c:4179 c/c-parser.c:4244 -#: c/c-parser.c:4302 c/c-parser.c:4664 c/c-parser.c:4685 c/c-parser.c:4694 -#: c/c-parser.c:4745 c/c-parser.c:4754 c/c-parser.c:8544 c/c-parser.c:8610 -#: c/c-parser.c:9109 c/c-parser.c:9131 c/c-parser.c:9165 c/c-parser.c:9274 -#: c/c-parser.c:10057 c/c-parser.c:10468 c/c-parser.c:11403 c/c-parser.c:13599 -#: c/c-parser.c:14242 c/c-parser.c:14301 c/c-parser.c:14356 c/c-parser.c:15615 -#: c/c-parser.c:15713 c/c-parser.c:16946 c/c-parser.c:17713 c/c-parser.c:18101 -#: c/c-parser.c:20875 c/c-parser.c:20953 c/gimple-parser.c:194 -#: c/gimple-parser.c:197 c/gimple-parser.c:526 c/gimple-parser.c:560 -#: c/gimple-parser.c:565 c/gimple-parser.c:733 c/gimple-parser.c:830 -#: c/gimple-parser.c:1023 c/gimple-parser.c:1049 c/gimple-parser.c:1052 -#: c/gimple-parser.c:1183 c/gimple-parser.c:1313 c/gimple-parser.c:1439 -#: c/gimple-parser.c:1455 c/gimple-parser.c:1471 c/gimple-parser.c:1493 -#: c/gimple-parser.c:1523 c/gimple-parser.c:1549 c/gimple-parser.c:1755 -#: c/gimple-parser.c:1948 c/gimple-parser.c:1968 c/gimple-parser.c:2102 -#: c/gimple-parser.c:2265 c/c-parser.c:7165 cp/parser.c:30527 +#: c/c-parser.c:3011 c/c-parser.c:3986 c/c-parser.c:4181 c/c-parser.c:4246 +#: c/c-parser.c:4304 c/c-parser.c:4666 c/c-parser.c:4687 c/c-parser.c:4696 +#: c/c-parser.c:4747 c/c-parser.c:4756 c/c-parser.c:8552 c/c-parser.c:8618 +#: c/c-parser.c:9117 c/c-parser.c:9139 c/c-parser.c:9173 c/c-parser.c:9282 +#: c/c-parser.c:10065 c/c-parser.c:10476 c/c-parser.c:11411 c/c-parser.c:13607 +#: c/c-parser.c:14250 c/c-parser.c:14309 c/c-parser.c:14364 c/c-parser.c:15623 +#: c/c-parser.c:15721 c/c-parser.c:16954 c/c-parser.c:17721 c/c-parser.c:18109 +#: c/c-parser.c:20883 c/c-parser.c:20961 c/gimple-parser.c:195 +#: c/gimple-parser.c:198 c/gimple-parser.c:527 c/gimple-parser.c:561 +#: c/gimple-parser.c:566 c/gimple-parser.c:734 c/gimple-parser.c:831 +#: c/gimple-parser.c:1024 c/gimple-parser.c:1050 c/gimple-parser.c:1053 +#: c/gimple-parser.c:1184 c/gimple-parser.c:1314 c/gimple-parser.c:1440 +#: c/gimple-parser.c:1456 c/gimple-parser.c:1472 c/gimple-parser.c:1494 +#: c/gimple-parser.c:1524 c/gimple-parser.c:1550 c/gimple-parser.c:1756 +#: c/gimple-parser.c:1949 c/gimple-parser.c:1969 c/gimple-parser.c:2103 +#: c/gimple-parser.c:2266 c/c-parser.c:7173 cp/parser.c:30534 #, gcc-internal-format msgid "expected %<)%>" msgstr "" -#: c/c-parser.c:4073 c/c-parser.c:4805 c/c-parser.c:4949 c/c-parser.c:5022 -#: c/c-parser.c:5023 c/c-parser.c:5437 c/c-parser.c:5473 c/c-parser.c:7267 -#: c/c-parser.c:9265 c/c-parser.c:10155 c/c-parser.c:10444 c/c-parser.c:13046 -#: c/gimple-parser.c:1732 cp/parser.c:30491 +#: c/c-parser.c:4075 c/c-parser.c:4807 c/c-parser.c:4951 c/c-parser.c:5024 +#: c/c-parser.c:5025 c/c-parser.c:5439 c/c-parser.c:5475 c/c-parser.c:7275 +#: c/c-parser.c:9273 c/c-parser.c:10163 c/c-parser.c:10452 c/c-parser.c:13054 +#: c/gimple-parser.c:1733 cp/parser.c:30498 #, gcc-internal-format msgid "expected %<]%>" msgstr "" -#: c/c-parser.c:4282 +#: c/c-parser.c:4284 msgid "expected %<;%>, %<,%> or %<)%>" msgstr "" #. Look for the two `(' tokens. -#: c/c-parser.c:4714 c/c-parser.c:4719 c/c-parser.c:13582 c/c-parser.c:14331 -#: c/c-parser.c:20236 c/c-parser.c:20683 c/c-parser.c:20896 -#: c/gimple-parser.c:179 c/gimple-parser.c:473 c/gimple-parser.c:512 -#: c/gimple-parser.c:544 c/gimple-parser.c:800 c/gimple-parser.c:1017 -#: c/gimple-parser.c:1043 c/gimple-parser.c:1170 c/gimple-parser.c:1308 -#: c/gimple-parser.c:1429 c/gimple-parser.c:1489 c/gimple-parser.c:1507 -#: c/gimple-parser.c:1542 c/gimple-parser.c:1917 c/gimple-parser.c:1928 -#: c/gimple-parser.c:1934 c/gimple-parser.c:2099 c/gimple-parser.c:2262 -#: c/c-parser.c:13404 cp/parser.c:30482 +#: c/c-parser.c:4716 c/c-parser.c:4721 c/c-parser.c:13590 c/c-parser.c:14339 +#: c/c-parser.c:20244 c/c-parser.c:20691 c/c-parser.c:20904 +#: c/gimple-parser.c:180 c/gimple-parser.c:474 c/gimple-parser.c:513 +#: c/gimple-parser.c:545 c/gimple-parser.c:801 c/gimple-parser.c:1018 +#: c/gimple-parser.c:1044 c/gimple-parser.c:1171 c/gimple-parser.c:1309 +#: c/gimple-parser.c:1430 c/gimple-parser.c:1490 c/gimple-parser.c:1508 +#: c/gimple-parser.c:1543 c/gimple-parser.c:1918 c/gimple-parser.c:1929 +#: c/gimple-parser.c:1935 c/gimple-parser.c:2100 c/gimple-parser.c:2263 +#: c/c-parser.c:13412 cp/parser.c:30489 #, gcc-internal-format msgid "expected %<(%>" msgstr "" -#: c/c-parser.c:4945 c/c-parser.c:4947 c/c-parser.c:12974 cp/parser.c:30494 -#: cp/parser.c:34026 +#: c/c-parser.c:4947 c/c-parser.c:4949 c/c-parser.c:12982 cp/parser.c:30501 +#: cp/parser.c:34075 #, gcc-internal-format msgid "expected %<[%>" msgstr "" -#: c/c-parser.c:5607 c/c-parser.c:11632 c/c-parser.c:17906 c/c-parser.c:18689 -#: c/c-parser.c:21731 c/gimple-parser.c:384 c/gimple-parser.c:2268 -#: c/c-parser.c:3227 c/c-parser.c:3449 c/c-parser.c:11184 cp/parser.c:19135 -#: cp/parser.c:30488 +#: c/c-parser.c:5609 c/c-parser.c:11640 c/c-parser.c:17914 c/c-parser.c:18697 +#: c/c-parser.c:21739 c/gimple-parser.c:385 c/gimple-parser.c:2269 +#: c/c-parser.c:3229 c/c-parser.c:3451 c/c-parser.c:11192 cp/parser.c:19143 +#: cp/parser.c:30495 #, gcc-internal-format msgid "expected %<{%>" msgstr "" -#: c/c-parser.c:5879 c/c-parser.c:5888 c/c-parser.c:7695 c/c-parser.c:8746 -#: c/c-parser.c:11396 c/c-parser.c:11782 c/c-parser.c:11843 c/c-parser.c:13028 -#: c/c-parser.c:13943 c/c-parser.c:14159 c/c-parser.c:14649 c/c-parser.c:14745 -#: c/c-parser.c:15367 c/c-parser.c:15494 c/c-parser.c:20098 c/c-parser.c:20740 -#: c/c-parser.c:20799 c/gimple-parser.c:567 c/gimple-parser.c:870 -#: c/gimple-parser.c:2316 c/gimple-parser.c:2343 c/c-parser.c:7172 -#: c/c-parser.c:13507 cp/parser.c:30521 cp/parser.c:32041 cp/parser.c:34817 +#: c/c-parser.c:5887 c/c-parser.c:5896 c/c-parser.c:7703 c/c-parser.c:8754 +#: c/c-parser.c:11404 c/c-parser.c:11790 c/c-parser.c:11851 c/c-parser.c:13036 +#: c/c-parser.c:13951 c/c-parser.c:14167 c/c-parser.c:14657 c/c-parser.c:14753 +#: c/c-parser.c:15375 c/c-parser.c:15502 c/c-parser.c:20106 c/c-parser.c:20748 +#: c/c-parser.c:20807 c/gimple-parser.c:568 c/gimple-parser.c:871 +#: c/gimple-parser.c:2317 c/gimple-parser.c:2344 c/c-parser.c:7180 +#: c/c-parser.c:13515 cp/parser.c:30528 cp/parser.c:32088 cp/parser.c:34866 #, gcc-internal-format msgid "expected %<:%>" msgstr "" -#: c/c-parser.c:6729 cp/parser.c:30408 +#: c/c-parser.c:6737 cp/parser.c:30415 #, gcc-internal-format msgid "expected %" msgstr "" -#: c/c-parser.c:8508 c/c-parser.c:8697 c/c-parser.c:9155 c/c-parser.c:9198 -#: c/c-parser.c:9336 c/c-parser.c:10047 c/c-parser.c:14336 c/c-parser.c:15450 -#: c/gimple-parser.c:1020 c/gimple-parser.c:1046 c/gimple-parser.c:1174 -#: c/gimple-parser.c:1177 c/gimple-parser.c:1511 c/gimple-parser.c:1517 -#: cp/parser.c:29884 cp/parser.c:30497 +#: c/c-parser.c:8516 c/c-parser.c:8705 c/c-parser.c:9163 c/c-parser.c:9206 +#: c/c-parser.c:9344 c/c-parser.c:10055 c/c-parser.c:14344 c/c-parser.c:15458 +#: c/gimple-parser.c:1021 c/gimple-parser.c:1047 c/gimple-parser.c:1175 +#: c/gimple-parser.c:1178 c/gimple-parser.c:1512 c/gimple-parser.c:1518 +#: cp/parser.c:29891 cp/parser.c:30504 #, gcc-internal-format msgid "expected %<,%>" msgstr "" -#: c/c-parser.c:9055 +#: c/c-parser.c:9063 msgid "expected %<.%>" msgstr "" -#: c/c-parser.c:10855 c/c-parser.c:10887 c/c-parser.c:11127 cp/parser.c:32615 -#: cp/parser.c:32689 +#: c/c-parser.c:10863 c/c-parser.c:10895 c/c-parser.c:11135 cp/parser.c:32662 +#: cp/parser.c:32736 #, gcc-internal-format msgid "expected %<@end%>" msgstr "" -#: c/c-parser.c:11545 c/gimple-parser.c:1347 cp/parser.c:30506 +#: c/c-parser.c:11553 c/gimple-parser.c:1348 cp/parser.c:30513 #, gcc-internal-format msgid "expected %<>%>" msgstr "" -#: c/c-parser.c:14837 c/c-parser.c:15731 cp/parser.c:30530 +#: c/c-parser.c:14845 c/c-parser.c:15739 cp/parser.c:30537 #, gcc-internal-format msgid "expected %<,%> or %<)%>" msgstr "" #. All following cases are statements with LHS. -#: c/c-parser.c:15359 c/c-parser.c:17362 c/c-parser.c:17406 c/c-parser.c:17638 -#: c/c-parser.c:18082 c/c-parser.c:20305 c/c-parser.c:20937 -#: c/gimple-parser.c:724 c/c-parser.c:5496 cp/parser.c:30509 +#: c/c-parser.c:15367 c/c-parser.c:17370 c/c-parser.c:17414 c/c-parser.c:17646 +#: c/c-parser.c:18090 c/c-parser.c:20313 c/c-parser.c:20945 +#: c/gimple-parser.c:725 c/c-parser.c:5498 cp/parser.c:30516 #, gcc-internal-format msgid "expected %<=%>" msgstr "" -#: c/c-parser.c:17654 c/c-parser.c:17954 c/gimple-parser.c:1565 -#: c/gimple-parser.c:1597 c/gimple-parser.c:1607 c/gimple-parser.c:2353 -#: cp/parser.c:30485 cp/parser.c:32834 +#: c/c-parser.c:17662 c/c-parser.c:17962 c/gimple-parser.c:1566 +#: c/gimple-parser.c:1598 c/gimple-parser.c:1608 c/gimple-parser.c:2354 +#: cp/parser.c:30492 cp/parser.c:32881 #, gcc-internal-format msgid "expected %<}%>" msgstr "" -#: c/c-parser.c:18732 c/c-parser.c:18722 cp/parser.c:39443 +#: c/c-parser.c:18740 c/c-parser.c:18730 cp/parser.c:39492 #, gcc-internal-format msgid "expected %<#pragma omp section%> or %<}%>" msgstr "" -#: c/c-typeck.c:8224 +#: c/c-typeck.c:8245 msgid "(anonymous)" msgstr "" -#: c/gimple-parser.c:1336 cp/parser.c:16583 cp/parser.c:30503 +#: c/gimple-parser.c:1337 cp/parser.c:16591 cp/parser.c:30510 #, gcc-internal-format msgid "expected %<<%>" msgstr "" -#: c/gimple-parser.c:2312 c/gimple-parser.c:2339 c/gimple-parser.c:2178 -#: c/gimple-parser.c:2215 +#: c/gimple-parser.c:2313 c/gimple-parser.c:2340 c/gimple-parser.c:2179 +#: c/gimple-parser.c:2216 #, gcc-internal-format msgid "expected label" msgstr "" -#: cp/call.c:3847 +#: cp/call.c:3851 msgid "candidate:" msgstr "" -#: cp/call.c:7193 +#: cp/call.c:7202 msgid " after user-defined conversion:" msgstr "" -#: cp/call.c:7327 cp/pt.c:2004 cp/pt.c:24476 +#: cp/call.c:7336 cp/pt.c:2004 cp/pt.c:24462 msgid "candidate is:" msgid_plural "candidates are:" msgstr[0] "" msgstr[1] "" -#: cp/call.c:11626 +#: cp/call.c:11663 msgid "candidate 1:" msgstr "" -#: cp/call.c:11627 +#: cp/call.c:11664 msgid "candidate 2:" msgstr "" @@ -3621,169 +3621,169 @@ msgstr "" msgid "(static destructors for %s)" msgstr "" -#: cp/error.c:1072 +#: cp/error.c:1071 msgid "" msgstr "" -#: cp/error.c:1175 +#: cp/error.c:1174 msgid "vtable for " msgstr "" -#: cp/error.c:1199 +#: cp/error.c:1198 msgid " " msgstr "" -#: cp/error.c:1214 +#: cp/error.c:1213 msgid "{anonymous}" msgstr "" -#: cp/error.c:1216 +#: cp/error.c:1215 msgid "(anonymous namespace)" msgstr "" -#: cp/error.c:1317 +#: cp/error.c:1315 msgid "