From 3522082b2fc6caf52267ee34af0d360ad64076d2 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Sat, 2 Jun 2001 14:07:58 +0200 Subject: i386.md (all uses of ext_register_operand): Make sure they are VOIDmode; replace all uses outside zero_extend. * i386.md (all uses of ext_register_operand): Make sure they are VOIDmode; replace all uses outside zero_extend. (and?i splitters): Use ext_register_operands. (test?i peep2): Remove ignored constraints. * i386.c (ext_register_operand): Check that operand is eighter pseudo or hard or 'Q' register. From-SVN: r42798 --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/i386.c | 9 ++++++++- gcc/config/i386/i386.md | 47 ++++++++++++++++++++--------------------------- 3 files changed, 37 insertions(+), 28 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fad7c99..1b0c0e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +Sat Jun 2 12:23:51 CEST 2001 Jan Hubicka + + * i386.md (all uses of ext_register_operand): Make sure they are + VOIDmode; replace all uses outside zero_extend. + (and?i splitters): Use ext_register_operands. + (test?i peep2): Remove ignored constraints. + * i386.c (ext_register_operand): Check that operand is + eighter pseudo or hard or 'Q' register. + Sat Jun 2 06:53:50 2001 Richard Kenner * tree.h (struct record_layout_info_s): New field unpadded_align. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 2fb8b28..4027019 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1694,10 +1694,17 @@ ext_register_operand (op, mode) register rtx op; enum machine_mode mode ATTRIBUTE_UNUSED; { + int regno; if ((!TARGET_64BIT || GET_MODE (op) != DImode) && GET_MODE (op) != SImode && GET_MODE (op) != HImode) return 0; - return register_operand (op, VOIDmode); + + if (!register_operand (op, VOIDmode)) + return 0; + + /* Be curefull to accept only registers having upper parts. */ + regno = REG_P (op) ? REGNO (op) : REGNO (SUBREG_REG (op)); + return (regno > LAST_VIRTUAL_REGISTER || regno < 4); } /* Return 1 if this is a valid binary floating-point operation. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 615120f..dcd205b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1220,7 +1220,7 @@ (define_insn "*cmpqi_ext_1_rex64" [(set (reg 17) (compare - (match_operand:QI 0 "ext_register_operand" "Q") + (match_operand:QI 0 "register_operand" "Q") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") @@ -2142,7 +2142,7 @@ (define_insn "*movsi_extv_1" [(set (match_operand:SI 0 "register_operand" "=R") - (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q") + (sign_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)))] "" @@ -2152,7 +2152,7 @@ (define_insn "*movhi_extv_1" [(set (match_operand:HI 0 "register_operand" "=R") - (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q") + (sign_extract:HI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8)))] "" @@ -2162,7 +2162,7 @@ (define_insn "*movqi_extv_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r") - (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q") + (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)))] "!TARGET_64BIT" @@ -2190,7 +2190,7 @@ (define_insn "*movqi_extv_1_rex64" [(set (match_operand:QI 0 "register_operand" "=Q,?R") - (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q") + (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)))] "TARGET_64BIT" @@ -2327,7 +2327,7 @@ [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) - (match_operand:SI 1 "ext_register_operand" "Q"))] + (match_operand:SI 1 "register_operand" "Q"))] "TARGET_64BIT" "mov{b}\\t{%b1, %h0|%h0, %b1}" [(set_attr "type" "imov") @@ -2337,7 +2337,7 @@ [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) - (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q") + (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q") (const_int 8)) (const_int 255)))] "" @@ -6777,7 +6777,7 @@ (define_insn "addqi_ext_1" - [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q") + [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") (const_int 8) (const_int 8)) (plus:SI @@ -6785,7 +6785,7 @@ (match_operand 1 "ext_register_operand" "0") (const_int 8) (const_int 8)) - (match_operand:QI 2 "general_operand" "qmn"))) + (match_operand:QI 2 "general_operand" "Qmn"))) (clobber (reg:CC 17))] "!TARGET_64BIT" "* @@ -8055,7 +8055,7 @@ (const_int 8) (const_int 8)) (zero_extend:SI - (match_operand:QI 1 "ext_register_operand" "Q"))) + (match_operand:QI 1 "register_operand" "Q"))) (const_int 0)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" "test{b}\\t{%1, %h0|%h0, %1}" @@ -8271,36 +8271,29 @@ (set_attr "mode" "SI")]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "ext_register_operand" "") (and (match_dup 0) (const_int -65536))) (clobber (reg:CC 17))] - "optimize_size - && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode - || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))" + "optimize_size" [(set (strict_low_part (match_dup 1)) (const_int 0))] "operands[1] = gen_lowpart (HImode, operands[0]);") (define_split - [(set (match_operand 0 "q_regs_operand" "") + [(set (match_operand 0 "ext_register_operand" "") (and (match_dup 0) (const_int -256))) (clobber (reg:CC 17))] - "(optimize_size || !TARGET_PARTIAL_REG_STALL) - && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode - || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))" + "(optimize_size || !TARGET_PARTIAL_REG_STALL)" [(set (strict_low_part (match_dup 1)) (const_int 0))] "operands[1] = gen_lowpart (QImode, operands[0]);") (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "ext_register_operand" "") (and (match_dup 0) (const_int -65281))) (clobber (reg:CC 17))] - "(optimize_size || !TARGET_PARTIAL_REG_STALL) - && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode - || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)) - && (! reload_completed || ANY_QI_REG_P (operands[0]))" + "(optimize_size || !TARGET_PARTIAL_REG_STALL)" [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) @@ -8501,7 +8494,7 @@ (and:SI (zero_extract:SI (match_operand 1 "ext_register_operand" "0") - (const_int 8) + (const_int 8) (const_int 8)) (match_operand 2 "const_int_operand" "n")) (const_int 0))) @@ -8549,7 +8542,7 @@ (const_int 8) (const_int 8)) (zero_extend:SI - (match_operand:QI 2 "ext_register_operand" "Q")))) + (match_operand 2 "ext_register_operand" "Q")))) (clobber (reg:CC 17))] "TARGET_64BIT" "and{b}\\t{%2, %h0|%h0, %2}" @@ -16835,10 +16828,10 @@ (compare (and:SI (zero_extract:SI - (match_operand 0 "ext_register_operand" "q") + (match_operand 0 "ext_register_operand" "") (const_int 8) (const_int 8)) - (match_operand 1 "const_int_operand" "n")) + (match_operand 1 "const_int_operand" "")) (const_int 0)))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) -- cgit v1.1