From 244448f2624e2e31a59405e7443cf1dba94c06f0 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Thu, 21 Nov 2024 14:30:43 +0800 Subject: RISC-V: Rearrange the test files for vector SAT_SUB [NFC] The test files of vector SAT_SUB only has numbers as the suffix. Rearrange the file name to -{form number}-{target-type}. For example, test form 3 for uint32_t SAT_SUB will have -3-u32.c for asm check and -run-3-u32.c for the run test. Meanwhile, moved all related test files to riscv/rvv/autovec/sat/. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c: ...here. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-1.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-10.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-11.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-12.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-13.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-14.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-15.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-16.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-17.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-18.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-19.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-2.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-20.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-21.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-22.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-23.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-24.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-25.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-26.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-27.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-28.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-29.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-3.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-30.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-31.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-32.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-33.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-34.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-35.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-36.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-37.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-38.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-39.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-4.c | 9 --- .../riscv/rvv/autovec/binop/vec_sat_u_sub-40.c | 9 --- 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--- .../rvv/autovec/binop/vec_sat_u_sub_trunc-2.c | 10 --- .../rvv/autovec/binop/vec_sat_u_sub_trunc-3.c | 10 --- .../rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c | 74 --------------------- .../rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c | 74 --------------------- .../rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c | 74 --------------------- .../riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c | 9 +++ .../riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c | 9 +++ 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a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c deleted file mode 100644 index b989cb6..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_1(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c deleted file mode 100644 index b2fc988..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_3(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c deleted file mode 100644 index 944b197..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_3(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c deleted file mode 100644 index 862fd41..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_3(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c deleted file mode 100644 index edadbf0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_4(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c deleted file mode 100644 index d3eadae..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_4(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c deleted file mode 100644 index b9f61fd..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_4(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c deleted file mode 100644 index 8171a3e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_4(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c deleted file mode 100644 index 4e1f655..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_5(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c deleted file mode 100644 index d259675..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_5(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c deleted file mode 100644 index 19aaa7e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_5(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c deleted file mode 100644 index 5ed44d9..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_1(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c deleted file mode 100644 index ea95a37..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_5(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c deleted file mode 100644 index 9fee795..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_6(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c deleted file mode 100644 index de8defc..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_6(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c deleted file mode 100644 index aed21c7..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_6(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c deleted file mode 100644 index 8bfe35d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_6(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c deleted file mode 100644 index 7554929..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_7(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c deleted file mode 100644 index 7994bbb..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_7(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c deleted file mode 100644 index 2f2665d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_7(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c deleted file mode 100644 index 0c181e1..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_7(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c deleted file mode 100644 index b1fd6f9..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_8(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c deleted file mode 100644 index e67da17..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_1(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c deleted file mode 100644 index ca18727..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_8(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c deleted file mode 100644 index 203776e9..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_8(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c deleted file mode 100644 index 6aed879..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_8(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c deleted file mode 100644 index b5caadb..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_9(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c deleted file mode 100644 index eaa7b33..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_9(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c deleted file mode 100644 index f885b2c..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_9(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c deleted file mode 100644 index 4f5ab41..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_9(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c deleted file mode 100644 index aa90e04..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_10(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c deleted file mode 100644 index becaa6b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_10(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c deleted file mode 100644 index e104793..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_10(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c deleted file mode 100644 index 0efdf65..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_1(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c deleted file mode 100644 index c73b98e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_10(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c deleted file mode 100644 index 6c42573..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_2(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c deleted file mode 100644 index cde2465..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_2(uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c deleted file mode 100644 index 5399519..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_2(uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c deleted file mode 100644 index ade479e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_2(uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c deleted file mode 100644 index 6221f18a..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_FMT_3(uint8_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c deleted file mode 100644 index ea7a537..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 - -DEF_VEC_SAT_U_SUB_FMT_1(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c deleted file mode 100644 index 7a9d5d0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 - -DEF_VEC_SAT_U_SUB_FMT_3(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c deleted file mode 100644 index a1e4be2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 - -DEF_VEC_SAT_U_SUB_FMT_3(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c deleted file mode 100644 index a55e1c4..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 - -DEF_VEC_SAT_U_SUB_FMT_3(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c deleted file mode 100644 index 4bbf15c..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 - -DEF_VEC_SAT_U_SUB_FMT_4(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c deleted file mode 100644 index 50f9aeb..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 - -DEF_VEC_SAT_U_SUB_FMT_4(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c deleted file mode 100644 index 66b5008..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 - -DEF_VEC_SAT_U_SUB_FMT_4(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c deleted file mode 100644 index 90c7798..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 - -DEF_VEC_SAT_U_SUB_FMT_4(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c deleted file mode 100644 index 9204400..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 - -DEF_VEC_SAT_U_SUB_FMT_5(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c deleted file mode 100644 index 9926a6f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 - -DEF_VEC_SAT_U_SUB_FMT_5(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c deleted file mode 100644 index 3aef3cf..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 - -DEF_VEC_SAT_U_SUB_FMT_5(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c deleted file mode 100644 index 1288c61..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 - -DEF_VEC_SAT_U_SUB_FMT_1(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c deleted file mode 100644 index 9694211..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 - -DEF_VEC_SAT_U_SUB_FMT_5(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c deleted file mode 100644 index 1d3f2ca..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 - -DEF_VEC_SAT_U_SUB_FMT_6(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c deleted file mode 100644 index c4e933b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 - -DEF_VEC_SAT_U_SUB_FMT_6(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c deleted file mode 100644 index 4930eb1..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 - -DEF_VEC_SAT_U_SUB_FMT_6(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c deleted file mode 100644 index 0b0f38f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 - -DEF_VEC_SAT_U_SUB_FMT_6(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c deleted file mode 100644 index 56decee..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 - -DEF_VEC_SAT_U_SUB_FMT_7(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c deleted file mode 100644 index 4e49247..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 - -DEF_VEC_SAT_U_SUB_FMT_7(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c deleted file mode 100644 index ea4be4a..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 - -DEF_VEC_SAT_U_SUB_FMT_7(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c deleted file mode 100644 index f44fb7ac..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 - -DEF_VEC_SAT_U_SUB_FMT_7(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c deleted file mode 100644 index ab3e945..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 - -DEF_VEC_SAT_U_SUB_FMT_8(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c deleted file mode 100644 index f584c2d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 - -DEF_VEC_SAT_U_SUB_FMT_1(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c deleted file mode 100644 index 66110a4..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 - -DEF_VEC_SAT_U_SUB_FMT_8(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c deleted file mode 100644 index bae4e85..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 - -DEF_VEC_SAT_U_SUB_FMT_8(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c deleted file mode 100644 index d3924bf..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 - -DEF_VEC_SAT_U_SUB_FMT_8(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c deleted file mode 100644 index 0f20e46..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 - -DEF_VEC_SAT_U_SUB_FMT_9(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c deleted file mode 100644 index dbfcd8b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 - -DEF_VEC_SAT_U_SUB_FMT_9(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c deleted file mode 100644 index 636ba08..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 - -DEF_VEC_SAT_U_SUB_FMT_9(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c deleted file mode 100644 index ccf4087..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 - -DEF_VEC_SAT_U_SUB_FMT_9(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c deleted file mode 100644 index cabf501..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 - -DEF_VEC_SAT_U_SUB_FMT_10(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c deleted file mode 100644 index 3856cb0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 - -DEF_VEC_SAT_U_SUB_FMT_10(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c deleted file mode 100644 index 5c4683e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 - -DEF_VEC_SAT_U_SUB_FMT_10(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c deleted file mode 100644 index e469cf2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 - -DEF_VEC_SAT_U_SUB_FMT_1(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c deleted file mode 100644 index 8436c64..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 - -DEF_VEC_SAT_U_SUB_FMT_10(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c deleted file mode 100644 index 1c0a673..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 - -DEF_VEC_SAT_U_SUB_FMT_2(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c deleted file mode 100644 index 8aac565..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 - -DEF_VEC_SAT_U_SUB_FMT_2(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c deleted file mode 100644 index 4b88f77..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 - -DEF_VEC_SAT_U_SUB_FMT_2(T) - -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c deleted file mode 100644 index d4df48d..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 - -DEF_VEC_SAT_U_SUB_FMT_2(T) - -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c deleted file mode 100644 index 248a805..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c +++ /dev/null @@ -1,75 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 - -DEF_VEC_SAT_U_SUB_FMT_3(T) - -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; - -#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c deleted file mode 100644 index 52192d7..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c deleted file mode 100644 index b161ff0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c deleted file mode 100644 index 13c8cf5..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c deleted file mode 100644 index 5ed237b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c deleted file mode 100644 index 19d3bb0..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" -#include "vec_sat_data.h" - -#define T uint8_t -#define RUN(T, out, in, expect, IMM, N) \ - RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) - -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 254) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 255) - -int -main () -{ - T out[N]; - T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); - - RUN (T, out, d[0][0], d[0][1], 0, N); - RUN (T, out, d[1][0], d[1][1], 1, N); - RUN (T, out, d[2][0], d[2][1], 254, N); - RUN (T, out, d[3][0], d[3][1], 255, N); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c deleted file mode 100644 index f304d82..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" -#include "vec_sat_data.h" - -#define T uint16_t -#define RUN(T, out, in, expect, IMM, N) \ - RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) - -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65534) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65535) - -int -main () -{ - T out[N]; - T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); - - RUN (T, out, d[0][0], d[0][1], 0, N); - RUN (T, out, d[1][0], d[1][1], 1, N); - RUN (T, out, d[2][0], d[2][1], 65534, N); - RUN (T, out, d[3][0], d[3][1], 65535, N); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c deleted file mode 100644 index 283d37f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" -#include "vec_sat_data.h" - -#define T uint32_t -#define RUN(T, out, in, expect, IMM, N) \ - RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) - -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967294) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967295) - -int -main () -{ - T out[N]; - T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); - - RUN (T, out, d[0][0], d[0][1], 0, N); - RUN (T, out, d[1][0], d[1][1], 1, N); - RUN (T, out, d[2][0], d[2][1], 4294967294, N); - RUN (T, out, d[3][0], d[3][1], 4294967295, N); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c deleted file mode 100644 index 2512975..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" -#include "vec_sat_data.h" - -#define T uint64_t -#define RUN(T, out, in, expect, IMM, N) \ - RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) - -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551614u) -DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551615u) - -int -main () -{ - T out[N]; - T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); - - RUN (T, out, d[0][0], d[0][1], 0, N); - RUN (T, out, d[1][0], d[1][1], 1, N); - RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N); - RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c deleted file mode 100644 index 674206b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c deleted file mode 100644 index 32e828c..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c deleted file mode 100644 index 72afd08..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ - -#include "../vec_sat_arith.h" - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t) - -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c deleted file mode 100644 index d85a783..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c +++ /dev/null @@ -1,74 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define OUT_T uint8_t -#define IN_T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) - -OUT_T expect_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 254, 255, 4, 0, - 254, 255, 4, 0, - 254, 255, 4, 0, - 254, 255, 4, 0, - }, - { - 23, 0, 0, 2, - 23, 0, 0, 2, - 23, 0, 0, 2, - 23, 0, 0, 2, - }, - { - 254, 43, 0, 255, - 254, 43, 0, 255, - 254, 43, 0, 255, - 254, 43, 0, 255, - }, -}; - -IN_T op_1_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 65535, 256, 5, 0, - 65535, 256, 5, 0, - 65535, 256, 5, 0, - 65535, 256, 5, 0, - }, - { - 65535, 1024, 5, 65002, - 65535, 1024, 5, 65002, - 65535, 1024, 5, 65002, - 65535, 1024, 5, 65002, - }, - { - 65535, 300, 256, 512, - 65535, 300, 256, 512, - 65535, 300, 256, 512, - 65535, 300, 256, 512, - }, -}; - -IN_T op_2_data[] = { - 0, - 1, - 65000, - 257, -}; - -#include "vec_sat_binary_vvx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c deleted file mode 100644 index 9652c92..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c +++ /dev/null @@ -1,74 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define OUT_T uint16_t -#define IN_T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) - -OUT_T expect_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 65534, 65535, 4, 0, - 65534, 65535, 4, 0, - 65534, 65535, 4, 0, - 65534, 65535, 4, 0, - }, - { - 43, 0, 0, 2, - 43, 0, 0, 2, - 43, 0, 0, 2, - 43, 0, 0, 2, - }, - { - 65532, 34484, 0, 65535, - 65532, 34484, 0, 65535, - 65532, 34484, 0, 65535, - 65532, 34484, 0, 65535, - }, -}; - -IN_T op_1_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 4294967295, 65536, 5, 0, - 4294967295, 65536, 5, 0, - 4294967295, 65536, 5, 0, - 4294967295, 65536, 5, 0, - }, - { - 4294967295, 1024, 5, 4294967254, - 4294967295, 1024, 5, 4294967254, - 4294967295, 1024, 5, 4294967254, - 4294967295, 1024, 5, 4294967254, - }, - { - 4294967295, 100023, 65536, 131074, - 4294967295, 100023, 65536, 131074, - 4294967295, 100023, 65536, 131074, - 4294967295, 100023, 65536, 131074, - }, -}; - -IN_T op_2_data[] = { - 0, - 1, - 4294967252, - 65539, -}; - -#include "vec_sat_binary_vvx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c deleted file mode 100644 index d73cfa2..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c +++ /dev/null @@ -1,74 +0,0 @@ -/* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99" } */ - -#include "../vec_sat_arith.h" - -#define OUT_T uint32_t -#define IN_T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 - -DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) - -OUT_T expect_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 4294967294, 4294967295, 4, 0, - 4294967294, 4294967295, 4, 0, - 4294967294, 4294967295, 4, 0, - 4294967294, 4294967295, 4, 0, - }, - { - 10, 0, 0, 2, - 10, 0, 0, 2, - 10, 0, 0, 2, - 10, 0, 0, 2, - }, - { - 4294967288, 99995992, 0, 1, - 4294967288, 99995992, 0, 1, - 4294967288, 99995992, 0, 1, - 4294967288, 99995992, 0, 1, - }, -}; - -IN_T op_1_data[][N] = { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, - { - 18446744073709551615u, 4294967296, 5, 0, - 18446744073709551615u, 4294967296, 5, 0, - 18446744073709551615u, 4294967296, 5, 0, - 18446744073709551615u, 4294967296, 5, 0, - }, - { - 18446744073709551615u, 1024, 5, 18446744073709551607u, - 18446744073709551615u, 1024, 5, 18446744073709551607u, - 18446744073709551615u, 1024, 5, 18446744073709551607u, - 18446744073709551615u, 1024, 5, 18446744073709551607u, - }, - { - 18446744073709551615u, 4394963295, 65536, 4294967304, - 18446744073709551615u, 4394963295, 65536, 4294967304, - 18446744073709551615u, 4394963295, 65536, 4294967304, - 18446744073709551615u, 4394963295, 65536, 4294967304, - }, -}; - -IN_T op_2_data[] = { - 0, - 1, - 18446744073709551605u, - 4294967303, -}; - -#include "vec_sat_binary_vvx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c new file mode 100644 index 0000000..5ed44d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_1(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c new file mode 100644 index 0000000..e67da17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_1(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c new file mode 100644 index 0000000..0efdf65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_1(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c new file mode 100644 index 0000000..b989cb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_1(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c new file mode 100644 index 0000000..becaa6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_10(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c new file mode 100644 index 0000000..e104793 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_10(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c new file mode 100644 index 0000000..c73b98e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_10(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c new file mode 100644 index 0000000..aa90e04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_10(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c new file mode 100644 index 0000000..cde2465 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_2(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c new file mode 100644 index 0000000..5399519 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_2(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c new file mode 100644 index 0000000..ade479e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_2(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c new file mode 100644 index 0000000..6c42573 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_2(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c new file mode 100644 index 0000000..b2fc988 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_3(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c new file mode 100644 index 0000000..944b197 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_3(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c new file mode 100644 index 0000000..862fd41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_3(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c new file mode 100644 index 0000000..6221f18a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_3(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c new file mode 100644 index 0000000..d3eadae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_4(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c new file mode 100644 index 0000000..b9f61fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_4(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c new file mode 100644 index 0000000..8171a3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_4(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c new file mode 100644 index 0000000..edadbf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_4(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c new file mode 100644 index 0000000..d259675 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c new file mode 100644 index 0000000..19aaa7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c new file mode 100644 index 0000000..ea95a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c new file mode 100644 index 0000000..4e1f655 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c new file mode 100644 index 0000000..de8defc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_6(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c new file mode 100644 index 0000000..aed21c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_6(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c new file mode 100644 index 0000000..8bfe35d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_6(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c new file mode 100644 index 0000000..9fee795 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_6(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c new file mode 100644 index 0000000..7994bbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_7(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c new file mode 100644 index 0000000..2f2665d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_7(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c new file mode 100644 index 0000000..0c181e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_7(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c new file mode 100644 index 0000000..7554929 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_7(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c new file mode 100644 index 0000000..ca18727 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_8(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c new file mode 100644 index 0000000..203776e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_8(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c new file mode 100644 index 0000000..6aed879 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_8(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c new file mode 100644 index 0000000..b1fd6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_8(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c new file mode 100644 index 0000000..eaa7b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_9(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c new file mode 100644 index 0000000..f885b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_9(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c new file mode 100644 index 0000000..4f5ab41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_9(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c new file mode 100644 index 0000000..b5caadb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_9(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c new file mode 100644 index 0000000..1288c61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 + +DEF_VEC_SAT_U_SUB_FMT_1(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c new file mode 100644 index 0000000..f584c2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 + +DEF_VEC_SAT_U_SUB_FMT_1(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c new file mode 100644 index 0000000..e469cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 + +DEF_VEC_SAT_U_SUB_FMT_1(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c new file mode 100644 index 0000000..ea7a537 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 + +DEF_VEC_SAT_U_SUB_FMT_1(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c new file mode 100644 index 0000000..3856cb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c new file mode 100644 index 0000000..5c4683e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c new file mode 100644 index 0000000..8436c64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c new file mode 100644 index 0000000..cabf501 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c new file mode 100644 index 0000000..8aac565 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 + +DEF_VEC_SAT_U_SUB_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c new file mode 100644 index 0000000..4b88f77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 + +DEF_VEC_SAT_U_SUB_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c new file mode 100644 index 0000000..d4df48d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 + +DEF_VEC_SAT_U_SUB_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c new file mode 100644 index 0000000..1c0a673 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 + +DEF_VEC_SAT_U_SUB_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c new file mode 100644 index 0000000..7a9d5d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c new file mode 100644 index 0000000..a1e4be2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c new file mode 100644 index 0000000..a55e1c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c new file mode 100644 index 0000000..248a805 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c new file mode 100644 index 0000000..50f9aeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c new file mode 100644 index 0000000..66b5008 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c new file mode 100644 index 0000000..90c7798 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c new file mode 100644 index 0000000..4bbf15c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c new file mode 100644 index 0000000..9926a6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c new file mode 100644 index 0000000..3aef3cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c new file mode 100644 index 0000000..9694211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c new file mode 100644 index 0000000..9204400 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c new file mode 100644 index 0000000..c4e933b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c new file mode 100644 index 0000000..4930eb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c new file mode 100644 index 0000000..0b0f38f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c new file mode 100644 index 0000000..1d3f2ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c new file mode 100644 index 0000000..4e49247 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c new file mode 100644 index 0000000..ea4be4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c new file mode 100644 index 0000000..f44fb7ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c new file mode 100644 index 0000000..56decee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c new file mode 100644 index 0000000..66110a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c new file mode 100644 index 0000000..bae4e85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c new file mode 100644 index 0000000..d3924bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c new file mode 100644 index 0000000..ab3e945 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c new file mode 100644 index 0000000..dbfcd8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c new file mode 100644 index 0000000..636ba08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c new file mode 100644 index 0000000..ccf4087 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c new file mode 100644 index 0000000..0f20e46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c new file mode 100644 index 0000000..b161ff0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c new file mode 100644 index 0000000..13c8cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c new file mode 100644 index 0000000..5ed237b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c new file mode 100644 index 0000000..52192d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c new file mode 100644 index 0000000..f304d82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65534) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65535) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 65534, N); + RUN (T, out, d[3][0], d[3][1], 65535, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c new file mode 100644 index 0000000..283d37f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967294) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967295) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 4294967294, N); + RUN (T, out, d[3][0], d[3][1], 4294967295, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c new file mode 100644 index 0000000..2512975 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551614u) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551615u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N); + RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c new file mode 100644 index 0000000..19d3bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 254) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 255) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 254, N); + RUN (T, out, d[3][0], d[3][1], 255, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c new file mode 100644 index 0000000..32e828c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c new file mode 100644 index 0000000..72afd08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c new file mode 100644 index 0000000..674206b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c new file mode 100644 index 0000000..9652c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c @@ -0,0 +1,74 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define OUT_T uint16_t +#define IN_T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) + +OUT_T expect_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 65534, 65535, 4, 0, + 65534, 65535, 4, 0, + 65534, 65535, 4, 0, + 65534, 65535, 4, 0, + }, + { + 43, 0, 0, 2, + 43, 0, 0, 2, + 43, 0, 0, 2, + 43, 0, 0, 2, + }, + { + 65532, 34484, 0, 65535, + 65532, 34484, 0, 65535, + 65532, 34484, 0, 65535, + 65532, 34484, 0, 65535, + }, +}; + +IN_T op_1_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 4294967295, 65536, 5, 0, + 4294967295, 65536, 5, 0, + 4294967295, 65536, 5, 0, + 4294967295, 65536, 5, 0, + }, + { + 4294967295, 1024, 5, 4294967254, + 4294967295, 1024, 5, 4294967254, + 4294967295, 1024, 5, 4294967254, + 4294967295, 1024, 5, 4294967254, + }, + { + 4294967295, 100023, 65536, 131074, + 4294967295, 100023, 65536, 131074, + 4294967295, 100023, 65536, 131074, + 4294967295, 100023, 65536, 131074, + }, +}; + +IN_T op_2_data[] = { + 0, + 1, + 4294967252, + 65539, +}; + +#include "vec_sat_binary_vvx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c new file mode 100644 index 0000000..d73cfa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c @@ -0,0 +1,74 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define OUT_T uint32_t +#define IN_T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) + +OUT_T expect_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 4294967294, 4294967295, 4, 0, + 4294967294, 4294967295, 4, 0, + 4294967294, 4294967295, 4, 0, + 4294967294, 4294967295, 4, 0, + }, + { + 10, 0, 0, 2, + 10, 0, 0, 2, + 10, 0, 0, 2, + 10, 0, 0, 2, + }, + { + 4294967288, 99995992, 0, 1, + 4294967288, 99995992, 0, 1, + 4294967288, 99995992, 0, 1, + 4294967288, 99995992, 0, 1, + }, +}; + +IN_T op_1_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 18446744073709551615u, 4294967296, 5, 0, + 18446744073709551615u, 4294967296, 5, 0, + 18446744073709551615u, 4294967296, 5, 0, + 18446744073709551615u, 4294967296, 5, 0, + }, + { + 18446744073709551615u, 1024, 5, 18446744073709551607u, + 18446744073709551615u, 1024, 5, 18446744073709551607u, + 18446744073709551615u, 1024, 5, 18446744073709551607u, + 18446744073709551615u, 1024, 5, 18446744073709551607u, + }, + { + 18446744073709551615u, 4394963295, 65536, 4294967304, + 18446744073709551615u, 4394963295, 65536, 4294967304, + 18446744073709551615u, 4394963295, 65536, 4294967304, + 18446744073709551615u, 4394963295, 65536, 4294967304, + }, +}; + +IN_T op_2_data[] = { + 0, + 1, + 18446744073709551605u, + 4294967303, +}; + +#include "vec_sat_binary_vvx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c new file mode 100644 index 0000000..d85a783 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c @@ -0,0 +1,74 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" + +#define OUT_T uint8_t +#define IN_T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 + +DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) + +OUT_T expect_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 254, 255, 4, 0, + 254, 255, 4, 0, + 254, 255, 4, 0, + 254, 255, 4, 0, + }, + { + 23, 0, 0, 2, + 23, 0, 0, 2, + 23, 0, 0, 2, + 23, 0, 0, 2, + }, + { + 254, 43, 0, 255, + 254, 43, 0, 255, + 254, 43, 0, 255, + 254, 43, 0, 255, + }, +}; + +IN_T op_1_data[][N] = { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + { + 65535, 256, 5, 0, + 65535, 256, 5, 0, + 65535, 256, 5, 0, + 65535, 256, 5, 0, + }, + { + 65535, 1024, 5, 65002, + 65535, 1024, 5, 65002, + 65535, 1024, 5, 65002, + 65535, 1024, 5, 65002, + }, + { + 65535, 300, 256, 512, + 65535, 300, 256, 512, + 65535, 300, 256, 512, + 65535, 300, 256, 512, + }, +}; + +IN_T op_2_data[] = { + 0, + 1, + 65000, + 257, +}; + +#include "vec_sat_binary_vvx_run.h" -- cgit v1.1