From 1ec01ab2fb1dcf2cf71e1926be459935474fe68e Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 29 Sep 2011 07:35:16 +0000 Subject: Add sparc 3D array addressing VIS intrinsics. gcc/ * config/sparc/sparc.md (UNSPEC_ARRAY8, UNSPEC_ARRAY16, UNSPEC_ARRAY32): New unspec. (define_attr type): New type 'array'. (array{8,16,32}_vis): New patterns. * config/sparc/ultra1_2.md: Add reservations for 'array'. * config/sparc/ultra3.md: Likewise. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/sparc.c (sparc_vis_init_builtins): Build new array builtins. * config/sparc/visintrin.h (__vis_array8, __vis_array16, __vis_array32): New. * doc/extend.texi: Document new VIS builtins. gcc/testsuite/ * gcc.target/sparc/array.c: New test. From-SVN: r179334 --- gcc/ChangeLog | 16 ++++++++++++++++ gcc/config/sparc/niagara.md | 2 +- gcc/config/sparc/niagara2.md | 4 ++-- gcc/config/sparc/sparc.c | 23 +++++++++++++++++++++++ gcc/config/sparc/sparc.md | 32 +++++++++++++++++++++++++++++++- gcc/config/sparc/ultra1_2.md | 2 +- gcc/config/sparc/ultra3.md | 5 +++++ gcc/config/sparc/visintrin.h | 21 +++++++++++++++++++++ gcc/doc/extend.texi | 4 ++++ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/sparc/array.c | 21 +++++++++++++++++++++ 11 files changed, 129 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/sparc/array.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42c50e8..f4b9c8a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2011-09-29 David S. Miller + + * config/sparc/sparc.md (UNSPEC_ARRAY8, UNSPEC_ARRAY16, + UNSPEC_ARRAY32): New unspec. + (define_attr type): New type 'array'. + (array{8,16,32}_vis): New patterns. + * config/sparc/ultra1_2.md: Add reservations for 'array'. + * config/sparc/ultra3.md: Likewise. + * config/sparc/niagara.md: Likewise. + * config/sparc/niagara2.md: Likewise. + * config/sparc/sparc.c (sparc_vis_init_builtins): Build new + array builtins. + * config/sparc/visintrin.h (__vis_array8, __vis_array16, + __vis_array32): New. + * doc/extend.texi: Document new VIS builtins. + 2011-09-29 Iain Sandoe * config/darwin9.h (STACK_CHECK_STATIC_BUILTIN): Enable for diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index 3e5a3e5..a75088b 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -114,5 +114,5 @@ */ (define_insn_reservation "niag_vis" 8 (and (eq_attr "cpu" "niagara") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,gsr")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,gsr,array")) "niag_pipe*8") diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index 9ea6b04..f261ac1 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -111,10 +111,10 @@ (define_insn_reservation "niag2_vis" 6 (and (eq_attr "cpu" "niagara2") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,gsr")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,array,gsr")) "niag2_pipe*6") (define_insn_reservation "niag3_vis" 9 (and (eq_attr "cpu" "niagara3") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,gsr")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,array,gsr")) "niag2_pipe*9") diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 44d7f20..c8c0677 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -9195,6 +9195,9 @@ sparc_vis_init_builtins (void) tree di_ftype_di_di = build_function_type_list (intDI_type_node, intDI_type_node, intDI_type_node, 0); + tree si_ftype_si_si = build_function_type_list (intSI_type_node, + intSI_type_node, + intSI_type_node, 0); tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node, ptr_type_node, intSI_type_node, 0); @@ -9371,6 +9374,26 @@ sparc_vis_init_builtins (void) v2si_ftype_v2si_v2si); def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subsi3, v1si_ftype_v1si_v1si); + + /* Three-dimensional array addressing. */ + if (TARGET_ARCH64) + { + def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis, + di_ftype_di_di); + def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis, + di_ftype_di_di); + def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis, + di_ftype_di_di); + } + else + { + def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis, + si_ftype_si_si); + def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis, + si_ftype_si_si); + def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis, + si_ftype_si_si); + } } /* Handle TARGET_EXPAND_BUILTIN target hook. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index dfc5559..ee772d6 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -66,6 +66,9 @@ (UNSPEC_EDGE16L 54) (UNSPEC_EDGE32 55) (UNSPEC_EDGE32L 56) + (UNSPEC_ARRAY8 57) + (UNSPEC_ARRAY16 58) + (UNSPEC_ARRAY32 59) (UNSPEC_SP_SET 60) (UNSPEC_SP_TEST 61) @@ -237,7 +240,7 @@ fpcmp, fpmul,fpdivs,fpdivd, fpsqrts,fpsqrtd, - fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,edge,gsr, + fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,edge,gsr,array, cmove, ialuX, multi,savew,flushw,iflush,trap" @@ -8159,4 +8162,31 @@ [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) +(define_insn "array8_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "register_operand" "rJ") + (match_operand:P 2 "register_operand" "rJ")] + UNSPEC_ARRAY8))] + "TARGET_VIS" + "array8\t%r1, %r2, %0" + [(set_attr "type" "array")]) + +(define_insn "array16_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "register_operand" "rJ") + (match_operand:P 2 "register_operand" "rJ")] + UNSPEC_ARRAY16))] + "TARGET_VIS" + "array16\t%r1, %r2, %0" + [(set_attr "type" "array")]) + +(define_insn "array32_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "register_operand" "rJ") + (match_operand:P 2 "register_operand" "rJ")] + UNSPEC_ARRAY32))] + "TARGET_VIS" + "array32\t%r1, %r2, %0" + [(set_attr "type" "array")]) + (include "sync.md") diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 7f6e8b6..4600205 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -94,7 +94,7 @@ (define_insn_reservation "us1_simple_ieu1" 1 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "compare,edge")) + (eq_attr "type" "compare,edge,array")) "us1_ieu1 + us1_slot012") (define_insn_reservation "us1_ialuX" 1 diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index ac97099..c6a9f89 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -54,6 +54,11 @@ (eq_attr "type" "cmove")) "us3_ms + us3_br + us3_slotany, nothing") +(define_insn_reservation "us3_array" 2 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "array")) + "us3_ms + us3_slotany, nothing") + ;; ??? Not entirely accurate. ;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe ;; ??? is needed, and the instruction group is broken right after diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h index eb2b4ec..3bef099 100644 --- a/gcc/config/sparc/visintrin.h +++ b/gcc/config/sparc/visintrin.h @@ -333,4 +333,25 @@ __vis_fpsub32s (__v1si __A, __v1si __B) return __builtin_vis_fpsub32s (__A, __B); } +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_array8 (long __A, long __B) +{ + return __builtin_vis_array8 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_array16 (long __A, long __B) +{ + return __builtin_vis_array16 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_array32 (long __A, long __B) +{ + return __builtin_vis_array32 (__A, __B); +} + #endif /* _VISINTRIN_H_INCLUDED */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 195fa8c..f59333c 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -12987,6 +12987,10 @@ v4hi __builtin_vis_fpsub16 (v4hi, v4hi); v2hi __builtin_vis_fpsub16s (v2hi, v2hi); v2si __builtin_vis_fpsub32 (v2si, v2si); v1si __builtin_vis_fpsub32s (v1si, v1si); + +long __builtin_vis_array8 (long, long); +long __builtin_vis_array16 (long, long); +long __builtin_vis_array32 (long, long); @end smallexample @node SPU Built-in Functions diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4cf04b2..887ce8f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2011-09-29 David S. Miller + + * gcc.target/sparc/array.c: New test. + 2011-09-29 Jiangning Liu * gcc/testsuite/gcc.dg/tree-ssa/predcom-1.c: Explicitly turn on diff --git a/gcc/testsuite/gcc.target/sparc/array.c b/gcc/testsuite/gcc.target/sparc/array.c new file mode 100644 index 0000000..e382e22 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/array.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=ultrasparc -mvis" } */ + +long test_array8 (long a, long b) +{ + return __builtin_vis_array8 (a, b); +} + +long test_array16 (long a, long b) +{ + return __builtin_vis_array16 (a, b); +} + +long test_array32 (long a, long b) +{ + return __builtin_vis_array32 (a, b); +} + +/* { dg-final { scan-assembler "array8\t%" } } */ +/* { dg-final { scan-assembler "array16\t%" } } */ +/* { dg-final { scan-assembler "array32\t%" } } */ -- cgit v1.1