From 12fae1f7fbe4df554bb257f805d9d324e276ab57 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Wed, 3 May 2023 11:17:28 +0100 Subject: aarch64: PR target/99195 annotate HADDSUB patterns for vec-concat with zero Further straightforward patch for the various halving intrinsics with or without rounding, plus tests. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_h): Rename to... (aarch64_h): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for halving and rounding add/sub intrinsics. --- gcc/config/aarch64/aarch64-simd.md | 2 +- gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 16 ++++++++++------ 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9ba435f..b9473e0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4943,7 +4943,7 @@ "TARGET_SIMD" ) -(define_insn "aarch64_h" +(define_insn "aarch64_h" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (unspec:VDQ_BHSI [(match_operand:VDQ_BHSI 1 "register_operand" "w") (match_operand:VDQ_BHSI 2 "register_operand" "w")] diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 29a2e90..7354a0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -53,13 +53,17 @@ OPFIVE (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10) OPFIVE (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5) \ OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11) -OPELEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPELEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPELEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +#define OPFOURTEEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11,OP12,OP13,OP14) \ +OPSEVEN (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5, OP6, OP7) \ +OPSEVEN (T, IS, OS, S, OP8, OP9, OP10, OP11, OP12, OP13, OP14) -OPELEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPELEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPELEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPFOURTEEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +OPFOURTEEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +OPFOURTEEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) + +OPFOURTEEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +OPFOURTEEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +OPFOURTEEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) OPEIGHT (float32, 2, 4, f32, add, sub, mul, div, max, maxnm, min, minnm) -- cgit v1.1