From 11171cb98098e0a6438a5c2f964f5d45f2127b76 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 8 Sep 2025 07:36:39 -0600 Subject: RISC-V: Adjust tt-ascalon-d8 branch cost If-conversion isn't being applied to this nbench code: #include #define INTERNAL_FPF_PRECISION 4 typedef uint16_t u16; void ShiftMantLeft1(u16 *carry, u16 *mantissa) { int i; int new_carry; u16 accum; for(i=INTERNAL_FPF_PRECISION-1;i>=0;i--) { accum=mantissa[i]; new_carry=accum & 0x8000; accum=accum<<1; if(*carry) accum|=1; *carry=new_carry; mantissa[i]=accum; } return; } Bumping branch_cost from 3 to 4 triggers if-conversion, improving the nbench FP EMULATION result on Ascalon significantly. There's a risk that more aggressive use of conditional zero instructions will negatively impact workloads that predict well, but we haven't seen anything obvious. gcc/ChangeLog: * config/riscv/riscv.cc (tt_ascalon_d8_tune_info): Increase branch_cost from 3 to 4. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 07d40f4..bfd43fb 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -659,7 +659,7 @@ static const struct riscv_tune_param tt_ascalon_d8_tune_info = { {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */ {COSTS_N_INSNS (13), COSTS_N_INSNS (13)}, /* int_div */ 8, /* issue_rate */ - 3, /* branch_cost */ + 4, /* branch_cost */ 4, /* memory_cost */ 4, /* fmv_cost */ false, /* slow_unaligned_access */ -- cgit v1.1