From 06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 Mon Sep 17 00:00:00 2001
From: Pan Li <pan2.li@intel.com>
Date: Sat, 17 Aug 2024 09:25:58 -0600
Subject: RISC-V: Bugfix incorrect operand for vwsll auto-vect

This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.

void vwsll_vv_test (short *restrict dst, char *restrict a,
                    int *restrict b, int n)
{
  for (int i = 0; i < n; i++)
    dst[i] = a[i] << b[i];
}

It will hit the vwsll pattern with following operands.
operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])

According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above.  Thus,  add
quad truncation for operand 2 before emit vwsll.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

	PR target/116280

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add quad truncation to
	align the mode requirement for vwsll.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr116280-1.c: New test.
	* gcc.target/riscv/rvv/base/pr116280-2.c: New test.
---
 gcc/config/riscv/autovec-opt.md                      |  4 ++++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c | 10 ++++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c

(limited to 'gcc')

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d7a3cfd..4b33a14 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1546,6 +1546,10 @@
   "&& 1"
   [(const_int 0)]
   {
+    rtx truncated = gen_reg_rtx (<V_QUAD_TRUNC>mode);
+    emit_insn (gen_trunc<mode><v_quad_trunc>2 (truncated, operands[2]));
+    operands[2] = truncated;
+
     insn_code icode = code_for_pred_vwsll (<V_DOUBLE_TRUNC>mode);
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
     DONE;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
new file mode 100644
index 0000000..8b8547e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
@@ -0,0 +1,14 @@
+/* Test there is no ICE when compile.  */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+short a;
+char b;
+
+void
+test (int e[][1][1], char f[][1][1][1][1]) {
+  for (int g; b;)
+    for (;;)
+      for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
+        a = f[2][2][1][4073709551612][1] << e[1][1][g];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
new file mode 100644
index 0000000..02f2de6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
@@ -0,0 +1,10 @@
+/* Test there is no ICE when compile.  */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+void
+test (short *restrict dst, char *restrict a, int *restrict b, int n)
+{
+  for (int i = 0; i < n; i++)
+    dst[i] = a[i] << b[i];
+}
-- 
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