From ef310a95a934d0f38bed0dfdf988373a6b367e16 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 28 Jan 2019 08:15:42 +0000 Subject: re PR tree-optimization/88739 (Big-endian union bug) 2019-01-28 Richard Biener PR tree-optimization/88739 * tree-cfg.c (verify_types_in_gimple_reference): Verify BIT_FIELD_REFs only are applied to mode-precision operands when they are integral. (verify_gimple_assign_ternary): Likewise for BIT_INSERT_EXPR. * tree-ssa-sccvn.c (vn_reference_lookup_3): Avoid generating BIT_FIELD_REFs of non-mode-precision integral operands. From-SVN: r268332 --- gcc/tree-ssa-sccvn.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'gcc/tree-ssa-sccvn.c') diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index 7e8e05e..81604d2 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -2298,6 +2298,7 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *vr_, base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt), &offset2, &size2, &maxsize2, &reverse); + tree def_rhs = gimple_assign_rhs1 (def_stmt); if (!reverse && known_size_p (maxsize2) && known_eq (maxsize2, size2) @@ -2309,11 +2310,13 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *vr_, according to endianness. */ && (! INTEGRAL_TYPE_P (vr->type) || known_eq (ref->size, TYPE_PRECISION (vr->type))) - && multiple_p (ref->size, BITS_PER_UNIT)) + && multiple_p (ref->size, BITS_PER_UNIT) + && (! INTEGRAL_TYPE_P (TREE_TYPE (def_rhs)) + || type_has_mode_precision_p (TREE_TYPE (def_rhs)))) { gimple_match_op op (gimple_match_cond::UNCOND, BIT_FIELD_REF, vr->type, - vn_valueize (gimple_assign_rhs1 (def_stmt)), + vn_valueize (def_rhs), bitsize_int (ref->size), bitsize_int (offset - offset2)); tree val = vn_nary_build_or_lookup (&op); -- cgit v1.1