From 48ff383f0d9e917bcb7bcc091af413bcae07b440 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 12 Mar 2021 00:16:29 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7ed0052..4a59263 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,59 @@ +2021-03-11 David Malcolm + + PR analyzer/96374 + * gcc.dg/analyzer/dot-output.c: Add -fdump-analyzer-feasibility + to options. + * gcc.dg/analyzer/feasibility-1.c (test_6): Remove xfail. + (test_7): New. + * gcc.dg/analyzer/pr93355-localealias-feasibility-2.c: Remove xfail. + * gcc.dg/analyzer/pr93355-localealias-feasibility-3.c: Remove xfails. + * gcc.dg/analyzer/pr93355-localealias-feasibility.c: Remove + -fno-analyzer-feasibility from options. + * gcc.dg/analyzer/pr93355-localealias.c: Likewise. + * gcc.dg/analyzer/unknown-fns-4.c: Remove xfail. + +2021-03-11 Nathan Sidwell + + PR c++/99248 + * g++.dg/modules/pr99248.h: New. + * g++.dg/modules/pr99248_a.H: New. + * g++.dg/modules/pr99248_b.H: New. + +2021-03-11 Nathan Sidwell + + PR c++/99528 + * g++.dg/modules/pr99528.h: New. + * g++.dg/modules/pr99528_a.H: New. + * g++.dg/modules/pr99528_b.H: New. + * g++.dg/modules/pr99528_c.C: New. + +2021-03-11 Richard Biener + + PR testsuite/98245 + * gcc.dg/vect/bb-slp-46.c: Scan for the scalar compute + instead of verifying the total number of adds. + +2021-03-11 Richard Biener + + PR testsuite/97494 + * gcc.dg/vect/pr97428.c: XFAIL on !vect_hw_misalign. + +2021-03-11 Richard Biener + + PR testsuite/97494 + * gcc.dg/vect/vect-complex-5.c: XFAIL on !vect_hw_misalign. + +2021-03-11 Richard Biener + + PR testsuite/97494 + * gcc.dg/vect/slp-21.c: Adjust for powerpc64*-*-*. + +2021-03-11 Jakub Jelinek + + PR ipa/99517 + * gcc.target/i386/avx2-pr99517-1.c: New test. + * gcc.target/i386/avx2-pr99517-2.c: New test. + 2021-03-10 David Edelsohn PR target/99492 -- cgit v1.1 From 425afe1f0c907e6469cef1672160c9c95177e71a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 12 Mar 2021 10:11:24 +0100 Subject: c++: Fix up calls to immediate functions returning reference [PR99507] build_cxx_call calls convert_from_reference at the end, so if an immediate function returns a reference, we were constant evaluating not just that call, but that call wrapped in an INDIRECT_REF. That unfortunately means it can constant evaluate to something non-addressable, so if code later needs to take its address it will fail. The following patch fixes that by undoing the convert_from_reference wrapping for the cxx_constant_value evaluation and readdding it ad the end. 2021-03-12 Jakub Jelinek PR c++/99507 * call.c (build_over_call): For immediate evaluation of functions that return references, undo convert_from_reference effects before calling cxx_constant_value and call convert_from_reference afterwards. * g++.dg/cpp2a/consteval19.C: New test. --- gcc/testsuite/g++.dg/cpp2a/consteval19.C | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp2a/consteval19.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/cpp2a/consteval19.C b/gcc/testsuite/g++.dg/cpp2a/consteval19.C new file mode 100644 index 0000000..d742f59 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/consteval19.C @@ -0,0 +1,6 @@ +// PR c++/99507 +// { dg-do compile { target c++20 } } + +constexpr int i{0}; +consteval const int &iref () { return i; } +const int *a{&iref ()}; -- cgit v1.1 From 3bb345c9313ad8f6a6c24abd7d5eaa11413bbe22 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 12 Mar 2021 14:34:32 +0100 Subject: i386: Hopefully last set of -mavx512vl -mno-avx512bw fixes [PR99321] This is the final patch of the series started with https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566139.html and continued with https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566356.html This time, I went through all the remaining instructions marked by gas as requiring both AVX512BW and AVX512VL and for each checked tmp-mddump.md, figure out if it ever could be a problem (e.g. instructions that require AVX512BW+AVX512VL, but didn't exist before AVX512F are usually fine, the patterns have the right conditions, the bugs are typically on pre-AVX512F patterns where we have just blindly added v while they actually can't access those unless AVX512BW+AVX512VL), added test where possible (the test doesn't cover MMX though)and fixed md bugs. For mmx pextr[bw]/pinsr[bw] patterns it introduces per discussions a new YW constraint that only requires AVX512BW and not AVX512VL, because those instructions only require the former and not latter when using EVEX encoding. There are some other interesting details, e.g. most of the 8 interleave patterns (vpunck[hl]{bw,wd}) had correctly && && in the conditions because for masking it needs to be always EVEX encoded and then it needs both VL+BW, but 2 of those 8 had just && and so again would run into the -mavx512vl -mno-avx512bw problems. Another problem different from others was mmx eq/gt comparisons, that was using Yv constraints, so would happily accept %xmm16+ registers for -mavx512vl, but there actually are no such EVEX encoded instructions, as AVX512 comparisons work with %k* registers instead. The newly added testcase without the patch fails with: /tmp/ccVROLo2.s: Assembler messages: /tmp/ccVROLo2.s:9: Error: unsupported instruction `vpabsb' /tmp/ccVROLo2.s:20: Error: unsupported instruction `vpabsb' /tmp/ccVROLo2.s:31: Error: unsupported instruction `vpabsw' /tmp/ccVROLo2.s:42: Error: unsupported instruction `vpabsw' /tmp/ccVROLo2.s:53: Error: unsupported instruction `vpaddsb' /tmp/ccVROLo2.s:64: Error: unsupported instruction `vpaddsb' /tmp/ccVROLo2.s:75: Error: unsupported instruction `vpaddsw' /tmp/ccVROLo2.s:86: Error: unsupported instruction `vpaddsw' /tmp/ccVROLo2.s:97: Error: unsupported instruction `vpsubsb' /tmp/ccVROLo2.s:108: Error: unsupported instruction `vpsubsb' /tmp/ccVROLo2.s:119: Error: unsupported instruction `vpsubsw' /tmp/ccVROLo2.s:130: Error: unsupported instruction `vpsubsw' /tmp/ccVROLo2.s:141: Error: unsupported instruction `vpaddusb' /tmp/ccVROLo2.s:152: Error: unsupported instruction `vpaddusb' /tmp/ccVROLo2.s:163: Error: unsupported instruction `vpaddusw' /tmp/ccVROLo2.s:174: Error: unsupported instruction `vpaddusw' /tmp/ccVROLo2.s:185: Error: unsupported instruction `vpsubusb' /tmp/ccVROLo2.s:196: Error: unsupported instruction `vpsubusb' /tmp/ccVROLo2.s:207: Error: unsupported instruction `vpsubusw' /tmp/ccVROLo2.s:218: Error: unsupported instruction `vpsubusw' /tmp/ccVROLo2.s:258: Error: unsupported instruction `vpaddusw' /tmp/ccVROLo2.s:269: Error: unsupported instruction `vpavgb' /tmp/ccVROLo2.s:280: Error: unsupported instruction `vpavgb' /tmp/ccVROLo2.s:291: Error: unsupported instruction `vpavgw' /tmp/ccVROLo2.s:302: Error: unsupported instruction `vpavgw' /tmp/ccVROLo2.s:475: Error: unsupported instruction `vpmovsxbw' /tmp/ccVROLo2.s:486: Error: unsupported instruction `vpmovsxbw' /tmp/ccVROLo2.s:497: Error: unsupported instruction `vpmovzxbw' /tmp/ccVROLo2.s:508: Error: unsupported instruction `vpmovzxbw' /tmp/ccVROLo2.s:548: Error: unsupported instruction `vpmulhuw' /tmp/ccVROLo2.s:559: Error: unsupported instruction `vpmulhuw' /tmp/ccVROLo2.s:570: Error: unsupported instruction `vpmulhw' /tmp/ccVROLo2.s:581: Error: unsupported instruction `vpmulhw' /tmp/ccVROLo2.s:592: Error: unsupported instruction `vpsadbw' /tmp/ccVROLo2.s:603: Error: unsupported instruction `vpsadbw' /tmp/ccVROLo2.s:643: Error: unsupported instruction `vpshufhw' /tmp/ccVROLo2.s:654: Error: unsupported instruction `vpshufhw' /tmp/ccVROLo2.s:665: Error: unsupported instruction `vpshuflw' /tmp/ccVROLo2.s:676: Error: unsupported instruction `vpshuflw' /tmp/ccVROLo2.s:687: Error: unsupported instruction `vpslldq' /tmp/ccVROLo2.s:698: Error: unsupported instruction `vpslldq' /tmp/ccVROLo2.s:709: Error: unsupported instruction `vpsrldq' /tmp/ccVROLo2.s:720: Error: unsupported instruction `vpsrldq' /tmp/ccVROLo2.s:899: Error: unsupported instruction `vpunpckhbw' /tmp/ccVROLo2.s:910: Error: unsupported instruction `vpunpckhbw' /tmp/ccVROLo2.s:921: Error: unsupported instruction `vpunpckhwd' /tmp/ccVROLo2.s:932: Error: unsupported instruction `vpunpckhwd' /tmp/ccVROLo2.s:943: Error: unsupported instruction `vpunpcklbw' /tmp/ccVROLo2.s:954: Error: unsupported instruction `vpunpcklbw' /tmp/ccVROLo2.s:965: Error: unsupported instruction `vpunpcklwd' /tmp/ccVROLo2.s:976: Error: unsupported instruction `vpunpcklwd' 2021-03-12 Jakub Jelinek PR target/99321 * config/i386/constraints.md (YW): New internal constraint. * config/i386/sse.md (v_Yw): Add V4TI, V2TI, V1TI and TI cases. (*_3, *_uavg3, *abs2, *mul3_highpart): Use instead of v in constraints. (_psadbw): Use YW instead of v in constraints. (*avx2_pmaddwd, *sse2_pmaddwd, *v8hi3, *v16qi3, avx2_pmaddubsw256, ssse3_pmaddubsw128): Merge last two alternatives into one, use Yw instead of former x,v. (ashr3, 3): Use instead of x in constraints of the last alternative. (_packsswb, _packssdw, _packuswb, _packusdw, *_pmulhrsw3, _palignr, _pshufb3): Merge last two alternatives into one, use instead of former x,v. (avx2_interleave_highv32qi, vec_interleave_highv16qi): Use Yw instead of v in constraints. Add && to condition. (avx2_interleave_lowv32qi, vec_interleave_lowv16qi, avx2_interleave_highv16hi, vec_interleave_highv8hi, avx2_interleave_lowv16hi, vec_interleave_lowv8hi, avx2_pshuflw_1, sse2_pshuflw_1, avx2_pshufhw_1, sse2_pshufhw_1, avx2_v16qiv16hi2, sse4_1_v8qiv8hi2, *sse4_1_v8qiv8hi2_1, _3): Use Yw instead of v in constraints. * config/i386/mmx.md (Yv_Yw): New define_mode_attr. (*mmx_3, mmx_ashr3, mmx_3): Use instead of Yv in constraints. (*mmx_3, *mmx_mulv4hi3, *mmx_smulv4hi3_highpart, *mmx_umulv4hi3_highpart, *mmx_pmaddwd, *mmx_v4hi3, *mmx_v8qi3, mmx_packswb, mmx_packssdw, mmx_punpckhbw, mmx_punpcklbw, mmx_punpckhwd, mmx_punpcklwd, *mmx_uavgv8qi3, *mmx_uavgv4hi3, mmx_psadbw): Use Yw instead of Yv in constraints. (*mmx_pinsrw, *mmx_pinsrb, *mmx_pextrw, *mmx_pextrw_zext, *mmx_pextrb, *mmx_pextrb_zext): Use YW instead of Yv in constraints. (*mmx_eq3, mmx_gt3): Use x instead of Yv in constraints. (mmx_andnot3, *mmx_3): Split last alternative into two, one with just x, another isa avx512vl with v. * gcc.target/i386/avx512vl-pr99321-2.c: New test. --- gcc/testsuite/gcc.target/i386/avx512vl-pr99321-2.c | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr99321-2.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr99321-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr99321-2.c new file mode 100644 index 0000000..8bb3a03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr99321-2.c @@ -0,0 +1,94 @@ +/* PR target/99321 */ +/* { dg-do assemble { target lp64 } } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target assembler_march_noavx512bw } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw -Wa,-march=+noavx512bw" } */ + +#include + +typedef unsigned char V1 __attribute__((vector_size (16))); +typedef unsigned char V2 __attribute__((vector_size (32))); +typedef unsigned short V3 __attribute__((vector_size (16))); +typedef unsigned short V4 __attribute__((vector_size (32))); + +void f1 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_abs_epi8 ((__m128i) b); __asm ("" : : "v" (a)); } +void f2 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_abs_epi8 ((__m256i) b); __asm ("" : : "v" (a)); } +void f3 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_abs_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f4 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_abs_epi16 ((__m256i) b); __asm ("" : : "v" (a)); } +void f5 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_adds_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f6 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_adds_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f7 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_adds_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f8 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_adds_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f9 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_subs_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f10 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_subs_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f11 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_subs_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f12 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_subs_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f13 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_adds_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f14 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_adds_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f15 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_adds_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f16 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_adds_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f17 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_subs_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f18 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_subs_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f19 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_subs_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f20 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_subs_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f21 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_alignr_epi8 ((__m128i) a, (__m128i) b, 5); __asm ("" : : "v" (a)); } +void f22 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_alignr_epi8 ((__m256i) a, (__m256i) b, 5); __asm ("" : : "v" (a)); } +void f23 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_adds_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f24 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_avg_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f25 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_avg_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f26 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_avg_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f27 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_avg_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f28 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_broadcastb_epi8 ((__m128i) b); __asm ("" : : "v" (a)); } +void f29 (void) { register V2 a __asm ("%xmm16"); register V1 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_broadcastb_epi8 ((__m128i) b); __asm ("" : : "v" (a)); } +void f30 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_broadcastw_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f31 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_broadcastw_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +int f32 (void) { register V1 a __asm ("%xmm16"); __asm ("" : "=v" (a)); return _mm_extract_epi8 ((__m128i) a, 3); } +int f33 (void) { register V3 a __asm ("%xmm16"); __asm ("" : "=v" (a)); return _mm_extract_epi16 ((__m128i) a, 3); } +void f34 (int c) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_insert_epi8 ((__m128i) b, c, 5); __asm ("" : : "v" (a)); } +void f35 (int c) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_insert_epi16 ((__m128i) b, c, 5); __asm ("" : : "v" (a)); } +void f36 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_maddubs_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f37 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_maddubs_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f38 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_madd_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f39 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_madd_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f40 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_cvtepi8_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f41 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_cvtepi8_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f42 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_cvtepu8_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f43 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_cvtepu8_epi16 ((__m128i) b); __asm ("" : : "v" (a)); } +void f44 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_mulhrs_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f45 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_mulhrs_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f46 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_mulhi_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f47 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_mulhi_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f48 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_mulhi_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f49 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_mulhi_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f50 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_sad_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f51 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_sad_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f52 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_shuffle_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f53 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_shuffle_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f54 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_shufflehi_epi16 ((__m128i) b, 0x5b); __asm ("" : : "v" (a)); } +void f55 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_shufflehi_epi16 ((__m256i) b, 0x5b); __asm ("" : : "v" (a)); } +void f56 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_shufflelo_epi16 ((__m128i) b, 0x5b); __asm ("" : : "v" (a)); } +void f57 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_shufflelo_epi16 ((__m256i) b, 0x5b); __asm ("" : : "v" (a)); } +void f58 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_slli_si128 ((__m128i) b, 3); __asm ("" : : "v" (a)); } +void f59 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_slli_si256 ((__m256i) b, 3); __asm ("" : : "v" (a)); } +void f60 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_srli_si128 ((__m128i) b, 3); __asm ("" : : "v" (a)); } +void f61 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_srli_si256 ((__m256i) b, 3); __asm ("" : : "v" (a)); } +void f62 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_sll_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f63 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_sll_epi16 ((__m256i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f64 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_slli_epi16 ((__m128i) b, 7); __asm ("" : : "v" (a)); } +void f65 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_slli_epi16 ((__m256i) b, 7); __asm ("" : : "v" (a)); } +void f66 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_srl_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f67 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_srl_epi16 ((__m256i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f68 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_srli_epi16 ((__m128i) b, 7); __asm ("" : : "v" (a)); } +void f69 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_srli_epi16 ((__m256i) b, 7); __asm ("" : : "v" (a)); } +void f70 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_sra_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f71 (void) { register V4 a __asm ("%xmm16"); register V3 b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_sra_epi16 ((__m256i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f72 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_srai_epi16 ((__m128i) b, 7); __asm ("" : : "v" (a)); } +void f73 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_srai_epi16 ((__m256i) b, 7); __asm ("" : : "v" (a)); } +void f74 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_unpackhi_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f75 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_unpackhi_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f76 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_unpackhi_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f77 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_unpackhi_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f78 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_unpacklo_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f79 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_unpacklo_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } +void f80 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_unpacklo_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); } +void f81 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_unpacklo_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); } -- cgit v1.1 From d0655763483008a421608d059cf26c93077621a9 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Fri, 12 Mar 2021 16:34:10 +0100 Subject: Fortran/OpenMP: Accept implicit-save DATA vars for threadprivate [PR99514] gcc/fortran/ChangeLog: PR fortran/99514 * resolve.c (resolve_symbol): Accept vars which are in DATA and hence (either) implicit SAVE (or in common). gcc/testsuite/ChangeLog: PR fortran/99514 * gfortran.dg/gomp/threadprivate-1.f90: New test. --- gcc/testsuite/gfortran.dg/gomp/threadprivate-1.f90 | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/gomp/threadprivate-1.f90 (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gfortran.dg/gomp/threadprivate-1.f90 b/gcc/testsuite/gfortran.dg/gomp/threadprivate-1.f90 new file mode 100644 index 0000000..59656c2 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/threadprivate-1.f90 @@ -0,0 +1,11 @@ +! PR fortran/99514 +! +! NTest in DATA is implicitly SAVE, unless in COMMON +! Was failing before as the implicit SAVE was not +! honoured by the threadprivate check. +! + +program main + DATA NTest /1/ + !$omp threadprivate(Ntest) +end program main -- cgit v1.1 From 6e885ad3287388192e52e9b524dbaa408507c0a4 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 12 Mar 2021 09:02:41 -0800 Subject: c++: ICE with using-decl [PR 99238] This ICE was caused by a stray TREE_VISITED marker. The lookup machinery was leaving it there due to the way I'd arranged for it to be cleared. That was presuming the name_lookup::value field didn't change, and that wasn't always true in the using-decl processing. I took the opportunity to break out a helper, and then call it immediately after lookups, rather than wait until destructor time. Added some asserts the module machinery to catch further cases of this. PR c++/99238 gcc/cp/ * module.cc (depset::hash::add_binding_entity): Assert not visited. (depset::add::add_specializations): Likewise. * name-lookup.c (name_lookup::dedup): New. (name_lookup::~name_lookup): Assert not deduping. (name_lookup::restore_state): Likewise. (name_lookup::add_overload): Replace outlined code with dedup call. (name_lookup::add_value): Likewise. (name_lookup::search_namespace_only): Likewise. (name_lookup::adl_namespace_fns): Likewise. (name_lookup::adl_class_fns): Likewise. (name_lookup::search_adl): Likewise. Add clearing dedup call. (name_lookup::search_qualified): Likewise. (name_lookup::search_unqualified): Likewise. gcc/testsuite/ * g++.dg/modules/pr99238.h: New. * g++.dg/modules/pr99238_a.H: New. * g++.dg/modules/pr99238_b.H: New. --- gcc/testsuite/g++.dg/modules/pr99238.h | 1 + gcc/testsuite/g++.dg/modules/pr99238_a.H | 4 ++++ gcc/testsuite/g++.dg/modules/pr99238_b.H | 8 ++++++++ 3 files changed, 13 insertions(+) create mode 100644 gcc/testsuite/g++.dg/modules/pr99238.h create mode 100644 gcc/testsuite/g++.dg/modules/pr99238_a.H create mode 100644 gcc/testsuite/g++.dg/modules/pr99238_b.H (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/modules/pr99238.h b/gcc/testsuite/g++.dg/modules/pr99238.h new file mode 100644 index 0000000..312641f --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr99238.h @@ -0,0 +1 @@ +struct tm; diff --git a/gcc/testsuite/g++.dg/modules/pr99238_a.H b/gcc/testsuite/g++.dg/modules/pr99238_a.H new file mode 100644 index 0000000..b594c09 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr99238_a.H @@ -0,0 +1,4 @@ +// PR 99238 ICE with using decl +// { dg-additional-options -fmodule-header } +// { dg-module-cmi {} } +#include "pr99238.h" diff --git a/gcc/testsuite/g++.dg/modules/pr99238_b.H b/gcc/testsuite/g++.dg/modules/pr99238_b.H new file mode 100644 index 0000000..070ee36 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr99238_b.H @@ -0,0 +1,8 @@ +// { dg-additional-options -fmodule-header } +// { dg-module-cmi {} } +#include "pr99238.h" +import "pr99238_a.H"; +namespace std +{ + using ::tm; +} -- cgit v1.1 From 6da2762a3b1c496bebe8334f6e68a834fe6a1055 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 13 Mar 2021 00:16:20 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4a59263..e13d752 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,25 @@ +2021-03-12 Nathan Sidwell + + PR c++/99238 + * g++.dg/modules/pr99238.h: New. + * g++.dg/modules/pr99238_a.H: New. + * g++.dg/modules/pr99238_b.H: New. + +2021-03-12 Tobias Burnus + + PR fortran/99514 + * gfortran.dg/gomp/threadprivate-1.f90: New test. + +2021-03-12 Jakub Jelinek + + PR target/99321 + * gcc.target/i386/avx512vl-pr99321-2.c: New test. + +2021-03-12 Jakub Jelinek + + PR c++/99507 + * g++.dg/cpp2a/consteval19.C: New test. + 2021-03-11 David Malcolm PR analyzer/96374 -- cgit v1.1 From bbdf59fdbc2ce41ccfac807b15cf3fac7b465a56 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sat, 13 Mar 2021 08:56:15 +0100 Subject: match.pd: Don't optimize vector X + (X << C) -> X * (1 + (1 << C)) if there is no mult support [PR99544] E.g. on aarch64, the target has V2DImode addition and shift by scalar optabs, but doesn't have V2DImode multiply. The following testcase ICEs because this simplification is done after last lowering, but generally, even if it is done before that, turning it into a multiplication will not be an improvement because that means scalarization, while the former can be done in vectors. It would be nice if we added expansion support for vector multiplication by uniform constants using shifts and additions like we have for scalar multiplication, but that is something that can be done in stage1. 2021-03-13 Jakub Jelinek PR tree-optimization/99544 * match.pd (X + (X << C) -> X * (1 + (1 << C))): Don't simplify if for vector types multiplication can't be done in type's mode. * gcc.dg/gomp/pr99544.c: New test. --- gcc/testsuite/gcc.dg/gomp/pr99544.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/gomp/pr99544.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.dg/gomp/pr99544.c b/gcc/testsuite/gcc.dg/gomp/pr99544.c new file mode 100644 index 0000000..4ea07cf --- /dev/null +++ b/gcc/testsuite/gcc.dg/gomp/pr99544.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/99544 */ +/* { dg-do compile } */ +/* { dg-options "-Os -fopenmp" } */ + +long +foo (long a, long b, long c) +{ + long d, e; + #pragma omp teams distribute parallel for simd firstprivate (a, b, c) lastprivate(e) + for (d = a; d < b; d++) + e = c + d * 5; + return e; +} -- cgit v1.1 From 7987beec679898cfa75839551d55ae5234a216bd Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Sat, 13 Mar 2021 11:39:57 +0000 Subject: Fortran: Fix for class defined operators [PR99125]. 2021-03-13 Paul Thomas gcc/fortran PR fortran/99125 * trans-array.c (gfc_conv_expr_descriptor): For deferred length length components use the ss_info string length instead of gfc_get_expr_charlen. Make sure that the deferred string length is a variable before assigning to it. Otherwise use the expr. * trans-expr.c (gfc_conv_string_length): Make sure that the deferred string length is a variable before assigning to it. gcc/testsuite/ PR fortran/99125 * gfortran.dg/alloc_deferred_comp_1.f90: New test. --- gcc/testsuite/gfortran.dg/alloc_deferred_comp_1.f90 | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/alloc_deferred_comp_1.f90 (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gfortran.dg/alloc_deferred_comp_1.f90 b/gcc/testsuite/gfortran.dg/alloc_deferred_comp_1.f90 new file mode 100644 index 0000000..0fc54d5 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/alloc_deferred_comp_1.f90 @@ -0,0 +1,18 @@ +! { dg-do run } +! +! Test the fix for PR99125, where the array reference in the print +! statement caused an ICE because the gimplifier complained about '0' +! being used as an lvalue. +! +! Contributed by Gerhard Steinmetz +! +program p + type t + character(:), allocatable :: a(:) + end type + type(t) :: x + character(8) :: c(3) = ['12 45 78','23 56 89','34 67 90'] + x%a = c + if (any (x%a(2:3) .ne. ['23 56 89','34 67 90'])) stop 1 + if (any (x%a(2:3)(4:5) .ne. ['56','67'])) stop 2 ! Bizarrely this worked. +end -- cgit v1.1 From 77643ac4bbd0ff758edc182a12cb622b74a3c38a Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Tue, 9 Mar 2021 15:02:35 -0700 Subject: PR tree-optimization/99489 - ICE calling strncat after strcat gcc/ChangeLog: PR tree-optimization/99489 * builtins.c (gimple_call_alloc_size): Fail gracefully when argument is not a call statement. gcc/testsuite/ChangeLog: PR tree-optimization/99489 * gcc.dg/Wstringop-truncation-9.c: New test. --- gcc/testsuite/gcc.dg/Wstringop-truncation-9.c | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/Wstringop-truncation-9.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.dg/Wstringop-truncation-9.c b/gcc/testsuite/gcc.dg/Wstringop-truncation-9.c new file mode 100644 index 0000000..6361480 --- /dev/null +++ b/gcc/testsuite/gcc.dg/Wstringop-truncation-9.c @@ -0,0 +1,41 @@ +/* PR tree-optimization/99489 - ICE calling strncat after strncat + { dg-do compile } + { dg-options "-O2 -Wall" } */ + +// Important -- see pr82429. +char *stpcpy (char *, const char *); + +void fchar (char *d, char c, char *s) +{ + __builtin_strcat (d, s); + __builtin_strncat (d, &c, 1); +} + +void fcstchar (char *d, char *s) +{ + __builtin_strcat (d, s); + + const char c = 'x'; + __builtin_strncat (d, &c, 1); // { dg-warning "-Wstringop-truncation" } +} + +void fstr (char *d, char *s) +{ + __builtin_strcat (d, s); + __builtin_strncat (d, s, 1); +} + +void farr (char *d, char *s) +{ + __builtin_strcat (d, s); + + char a[] = "x"; + __builtin_strncat (d, a, 1); // { dg-warning "-Wstringop-truncation" } +} + +void flit (char *d, char *s) +{ + __builtin_strcat (d, s); + __builtin_strncat (d, "x", 1); // { dg-warning "-Wstringop-truncation" "pr?????" { xfail *-*-*} } + // { dg-warning "-Wstringop-overflow" "actual" { target *-*-*} .-1 } +} -- cgit v1.1 From 5e93c2f08f35883376695506c3aaa9235174c00c Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 14 Mar 2021 00:16:18 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e13d752..31117eb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2021-03-13 Martin Sebor + + PR tree-optimization/99489 + * gcc.dg/Wstringop-truncation-9.c: New test. + +2021-03-13 Paul Thomas + + PR fortran/99125 + * gfortran.dg/alloc_deferred_comp_1.f90: New test. + +2021-03-13 Jakub Jelinek + + PR tree-optimization/99544 + * gcc.dg/gomp/pr99544.c: New test. + 2021-03-12 Nathan Sidwell PR c++/99238 -- cgit v1.1 From c2d7c39fcb8a3cb67600cdb6fde49ecb0e951589 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Sun, 14 Mar 2021 20:39:58 +0100 Subject: PR fortran/99112 - ICE with runtime diagnostics for SIZE intrinsic function Add/fix handling of runtime checks for CLASS arguments with ALLOCATABLE or POINTER attribute. gcc/fortran/ChangeLog: * trans-expr.c (gfc_conv_procedure_call): Fix runtime checks for CLASS arguments. * trans-intrinsic.c (gfc_conv_intrinsic_size): Likewise. gcc/testsuite/ChangeLog: * gfortran.dg/pr99112.f90: New test. Co-authored-by: Paul Thomas --- gcc/testsuite/gfortran.dg/pr99112.f90 | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/pr99112.f90 (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gfortran.dg/pr99112.f90 b/gcc/testsuite/gfortran.dg/pr99112.f90 new file mode 100644 index 0000000..9401061 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr99112.f90 @@ -0,0 +1,27 @@ +! { dg-do compile } +! { dg-options "-fcheck=pointer -fdump-tree-original" } +! PR99112 - ICE with runtime diagnostics for SIZE intrinsic function + +module m + type t + end type +contains + function f (x, y) result(z) + class(t) :: x(:) + class(t) :: y(size(x)) + type(t) :: z(size(x)) + end + function g (x) result(z) + class(*) :: x(:) + type(t) :: z(size(x)) + end + subroutine s () + class(t), allocatable :: a(:), b(:), c(:), d(:) + class(t), pointer :: p(:) + c = f (a, b) + d = g (p) + end +end +! { dg-final { scan-tree-dump-times "_gfortran_runtime_error_at" 3 "original" } } +! { dg-final { scan-tree-dump-times "Allocatable actual argument" 2 "original" } } +! { dg-final { scan-tree-dump-times "Pointer actual argument" 1 "original" } } -- cgit v1.1 From 9844eeff5abd129fab5a4cbd004b814c073a95a1 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 15 Mar 2021 00:16:26 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 31117eb..2c7b81b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2021-03-14 Harald Anlauf + Paul Thomas + + * gfortran.dg/pr99112.f90: New test. + 2021-03-13 Martin Sebor PR tree-optimization/99489 -- cgit v1.1 From 52b67943d1dc713712c8afd09b64a2eddfd731fe Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Sun, 14 Mar 2021 20:29:14 -0400 Subject: testsuite: fix typo in testcase pr99492.c gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr99492.c: Fix typo. --- gcc/testsuite/gcc.target/powerpc/pr99492.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/powerpc/pr99492.c b/gcc/testsuite/gcc.target/powerpc/pr99492.c index ae36cb3..37a1d07 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr99492.c +++ b/gcc/testsuite/gcc.target/powerpc/pr99492.c @@ -1,7 +1,7 @@ /* { dg-do run { target { powerpc*-ibm-aix* } } } */ /* { dg-options "" } */ -void abort (void); +extern void abort (void); struct A { double _Complex a[64]; @@ -26,10 +26,10 @@ int main() { abort(); if (__alignof(struct A) != 8) - abort; + abort(); if (__alignof(struct C) != 4) - abort; + abort(); if (__builtin_offsetof(struct C, c2) != 4) abort(); -- cgit v1.1 From 21ced2776a117924e52f6aab8b41afb613fef0e7 Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Mon, 15 Mar 2021 09:32:52 +0000 Subject: Fortran: Fix problem with allocate initialization [PR99545]. 2021-03-15 Paul Thomas gcc/fortran/ChangeLog PR fortran/99545 * trans-stmt.c (gfc_trans_allocate): Mark the initialization assignment by setting init_flag. gcc/testsuite/ChangeLog PR fortran/99545 * gfortran.dg/pr99545.f90: New test. --- gcc/testsuite/gfortran.dg/pr99545.f90 | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/pr99545.f90 (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gfortran.dg/pr99545.f90 b/gcc/testsuite/gfortran.dg/pr99545.f90 new file mode 100644 index 0000000..1b5ed5d --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr99545.f90 @@ -0,0 +1,40 @@ +! { dg-do compile } +! { dg-options "-fcheck=mem" } +! +! Test the fix for PR99545, in which the allocate statements caused an ICE. +! +! Contributed by Juergen Reuter +! +module commands + implicit none + private + + type, abstract :: range_t + integer :: step_mode = 0 + integer :: n_step = 0 + end type range_t + + type, extends (range_t) :: range_int_t + integer :: i_step = 0 + end type range_int_t + + type, extends (range_t) :: range_real_t + real :: lr_step = 0 +end type range_real_t + + type :: cmd_scan_t + private + class(range_t), dimension(:), allocatable :: range + contains + procedure :: compile => cmd_scan_compile + end type cmd_scan_t + +contains + + subroutine cmd_scan_compile (cmd) + class(cmd_scan_t), intent(inout) :: cmd + allocate (range_int_t :: cmd%range (3)) + allocate (range_real_t :: cmd%range (3)) + end subroutine cmd_scan_compile + +end module commands -- cgit v1.1 From 52654036a544389fb66855bf3972f2a8013bec59 Mon Sep 17 00:00:00 2001 From: Thomas Koenig Date: Mon, 15 Mar 2021 11:02:02 +0100 Subject: Handle EXEC_IOLENGTH in doloop_contained_procedure_code. This rather obvious patch fixes an ICE on valid which came about because I did not handle EXEC_IOLENGTH as start of an I/O statement when checking for the DO loop variable. This is an 11 regression. gcc/fortran/ChangeLog: PR fortran/99345 * frontend-passes.c (doloop_contained_procedure_code): Properly handle EXEC_IOLENGTH. gcc/testsuite/ChangeLog: PR fortran/99345 * gfortran.dg/do_check_16.f90: New test. * gfortran.dg/do_check_17.f90: New test. --- gcc/testsuite/gfortran.dg/do_check_16.f90 | 13 +++++++++++++ gcc/testsuite/gfortran.dg/do_check_17.f90 | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/do_check_16.f90 create mode 100644 gcc/testsuite/gfortran.dg/do_check_17.f90 (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gfortran.dg/do_check_16.f90 b/gcc/testsuite/gfortran.dg/do_check_16.f90 new file mode 100644 index 0000000..db0d45c --- /dev/null +++ b/gcc/testsuite/gfortran.dg/do_check_16.f90 @@ -0,0 +1,13 @@ +! { dg-do compile } +program main + implicit none + integer :: iq,nq,recl + DO iq = 1, nq + call foobar ! { dg-error "redefined" } + ENDDO +CONTAINS + + subroutine foobar + inquire (iolength=nq) iq ! { dg-error "redefined" } + end subroutine foobar +END program main diff --git a/gcc/testsuite/gfortran.dg/do_check_17.f90 b/gcc/testsuite/gfortran.dg/do_check_17.f90 new file mode 100644 index 0000000..02b8993 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/do_check_17.f90 @@ -0,0 +1,16 @@ +! { dg-do compile } +! PR 99345 - this used to cause an ICE. +! Original test case by Matthias Klose +program main + implicit none + integer :: iq,nq,recl + DO iq = 1, nq + CALL calc_upper_fan (iq) + ENDDO +CONTAINS + SUBROUTINE calc_upper_fan (iq) + INTEGER :: iq + INTEGER :: recl + INQUIRE(IOLENGTH=recl) iq + END SUBROUTINE calc_upper_fan +END -- cgit v1.1 From 99415d0f18716deeaa8d80e929b1337968cdfa23 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 15 Mar 2021 13:44:07 +0100 Subject: tree-optimization/98834 - fix optimization regression with _b_c_p The following makes FRE optimize a load we formerly required SRA + CCP for which now run after we get rid of all __builtin_constant_p calls. 2021-03-15 Richard Biener PR tree-optimization/98834 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle missing subsetting by truncating the access size. * g++.dg/opt/pr98834.C: New testcase. --- gcc/testsuite/g++.dg/opt/pr98834.C | 71 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 gcc/testsuite/g++.dg/opt/pr98834.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/opt/pr98834.C b/gcc/testsuite/g++.dg/opt/pr98834.C new file mode 100644 index 0000000..fafd322 --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/pr98834.C @@ -0,0 +1,71 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target c++17 } */ +/* { dg-options "-O2 -fdump-tree-fre3" } */ + +struct _Base +{ + int _M_data = 0; +}; + +struct _Wrapper : _Base +{ + _Wrapper(int) {} + + bool _M_is_constprop() { return __builtin_constant_p(_M_data); } +}; + +struct _Impl +{ + _Wrapper _S_multiplies(_Wrapper __x, _Wrapper __y) + { + if (__x._M_is_constprop() || __y._M_is_constprop()) + return __y; + return 0; + } +}; + +struct _TupleData +{ + _Wrapper first; + int second; +}; + +struct _Tuple : _TupleData +{ + template + _Tuple _M_apply_per_chunk(_Fp __fun, _Tuple __y) + { + return {__fun(first, __y.first), second}; + } +}; + +struct _ImplFixed +{ + static _Tuple _S_multiplies(_Tuple __x, _Tuple __y) + { + return __x._M_apply_per_chunk( + []( auto __xx, auto __yy) { + return _Impl()._S_multiplies(__xx, __yy); + }, + __y); + } +}; + +class simd +{ +public: + [[__gnu__::__always_inline__]] friend simd operator*(simd __x, simd __y) + { return _ImplFixed::_S_multiplies(__x._M_data, __y._M_data); } + + simd(_Tuple __init) : _M_data(__init) {} + + _Tuple _M_data; +}; + +int main() +{ + simd({0, 0}) * simd({0, 0}); +} + +/* FRE3 should elide all conditionals in the remaining main. */ +/* { dg-final { scan-tree-dump-times " Date: Tue, 2 Mar 2021 10:12:58 +0000 Subject: coroutines : Avoid generating empty statements [PR96749]. In the compiler-only idiom: " a = (target expr creats temp, op uses temp) " the target expression variable needs to be promoted to a frame one (if the expression has a suspend point). However, the only uses of the var are in the second part of the compound expression - and we were creating an empty statement corresponding to the (now unused) first arm. This then produces the spurious warnings noted. Fixed by avoiding generation of a separate variable nest for isolated target expressions (or similarly isolated co_awaits used in a function call). gcc/cp/ChangeLog: PR c++/96749 * coroutines.cc (flatten_await_stmt): Allow for the case where a target expression variable only has uses in the second part of a compound expression. (maybe_promote_temps): Avoid emiting empty statements. gcc/testsuite/ChangeLog: PR c++/96749 * g++.dg/coroutines/pr96749-1.C: New test. * g++.dg/coroutines/pr96749-2.C: New test. --- gcc/testsuite/g++.dg/coroutines/pr96749-1.C | 42 +++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/coroutines/pr96749-2.C | 37 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 gcc/testsuite/g++.dg/coroutines/pr96749-1.C create mode 100644 gcc/testsuite/g++.dg/coroutines/pr96749-2.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/coroutines/pr96749-1.C b/gcc/testsuite/g++.dg/coroutines/pr96749-1.C new file mode 100644 index 0000000..941a64e --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr96749-1.C @@ -0,0 +1,42 @@ +// { dg-additional-options "-Wall" } + +#include + +template struct promise; +template struct task { + using promise_type = promise<_Tp>; + bool await_ready() noexcept { return false; } + void await_suspend(std::coroutine_handle<> awaiter) noexcept { m_a = awaiter; } + auto await_resume() { return _Tp(); } + std::coroutine_handle<> m_a; +}; + +template struct promise { + auto get_return_object() noexcept { return task<_Tp>(); } + auto initial_suspend() noexcept { return std::suspend_always(); } + auto final_suspend() noexcept { return std::suspend_always(); } + void return_value(_Tp value) noexcept { m_v = value; } + void unhandled_exception() noexcept {} + _Tp m_v; +}; + +task test_coro(void) { + int r = 0; +#if 1 + // this code causes the unexpected warning below + r += co_await task(); +#else + // this code causes no warning + auto b = co_await task(); + r += b; +#endif + co_return r; + // test1.cpp: In function ‘task test_coro(int)’: + // test1.cpp:36:1: warning: statement has no effect [-Wunused-value] + // 36 | } + // | ^ +} + +int main(void) { + return 0; +} diff --git a/gcc/testsuite/g++.dg/coroutines/pr96749-2.C b/gcc/testsuite/g++.dg/coroutines/pr96749-2.C new file mode 100644 index 0000000..43052b5 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr96749-2.C @@ -0,0 +1,37 @@ +// { dg-additional-options "-Wall" } + +#include + +#if 1 +// with a struct, GCC emits "statement has no effect" +struct S {}; +#else +// no warning with built-in types +using S = int; +#endif + +S Func1(int); + +struct C { + auto operator co_await() { + struct Awaitable final { + bool await_ready() const { return true; } + std::coroutine_handle<> await_suspend(std::coroutine_handle<>) { return {}; } + int await_resume() { return 42; } + }; + return Awaitable{}; + } +}; + +struct Task { + struct promise_type { + auto initial_suspend() { return std::suspend_always{}; } + auto final_suspend() noexcept { return std::suspend_always{}; } + void get_return_object() {} + void unhandled_exception() {} + }; +}; + +Task Func2() { + Func1(co_await C()); +} -- cgit v1.1 From 26e0eb1071e318728bcd33f28d055729ac48792c Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Thu, 11 Mar 2021 14:22:37 +0000 Subject: coroutines : Handle for await expressions in for stmts [PR98480]. The handling of await expressions in the init, condition and iteration expressions of for loops had been omitted. Fixed thus. gcc/cp/ChangeLog: PR c++/98480 * coroutines.cc (replace_continue): Rewrite continue into 'goto label'. (await_statement_walker): Handle await expressions in the initializer, condition and iteration expressions of for loops. gcc/testsuite/ChangeLog: PR c++/98480 * g++.dg/coroutines/pr98480.C: New test. * g++.dg/coroutines/torture/co-await-24-for-init.C: New test. * g++.dg/coroutines/torture/co-await-25-for-condition.C: New test. * g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C: New test. --- gcc/testsuite/g++.dg/coroutines/pr98480.C | 20 ++++ .../coroutines/torture/co-await-24-for-init.C | 101 +++++++++++++++++++++ .../coroutines/torture/co-await-25-for-condition.C | 94 +++++++++++++++++++ .../torture/co-await-26-for-iteration-expr.C | 87 ++++++++++++++++++ 4 files changed, 302 insertions(+) create mode 100644 gcc/testsuite/g++.dg/coroutines/pr98480.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-24-for-init.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-25-for-condition.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/coroutines/pr98480.C b/gcc/testsuite/g++.dg/coroutines/pr98480.C new file mode 100644 index 0000000..2d87261 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr98480.C @@ -0,0 +1,20 @@ +#include + +struct future { + struct promise_type { + void return_value(int) {} + auto initial_suspend() { return std::suspend_never{}; } + auto final_suspend() noexcept { return std::suspend_never{}; } + void unhandled_exception() {} + future get_return_object() { return {}; } + }; + bool await_ready() { return true; } + void await_suspend(std::coroutine_handle<>) {} + int await_resume() { return 0; } +}; + +future co_foo() { + for( int i = 0; i < co_await future{}; ++i ); + // ICE -------------^ + co_return 0; +} diff --git a/gcc/testsuite/g++.dg/coroutines/torture/co-await-24-for-init.C b/gcc/testsuite/g++.dg/coroutines/torture/co-await-24-for-init.C new file mode 100644 index 0000000..1bf2f6d --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/co-await-24-for-init.C @@ -0,0 +1,101 @@ +// { dg-do run } + +// Test co-await in while condition. + +#include "../coro.h" + +// boiler-plate for tests of codegen +#include "../coro1-ret-int-yield-int.h" + +/* An awaiter that suspends always and returns an int as the + await_resume output. */ +struct IntAwaiter { + int v; + IntAwaiter (int _v) : v(_v) {} + bool await_ready () { return false; } + void await_suspend (coro::coroutine_handle<>) {} + int await_resume () { return v; } +}; + +struct coro1 +coro_a (bool t) +{ + int accum = 0; + for (int x = co_await IntAwaiter (3); x < 10; x++) + accum += x; + + co_return accum; +} + +struct coro1 +coro_b (bool t) +{ + int accum = 0; + int x; + for (x = co_await IntAwaiter (3); x < 10; x++) + accum += x; + + co_return accum; +} + +struct coro1 +coro_c (bool t) +{ + int accum = 0; + int x = 3; + for (co_await IntAwaiter (3); x < 10; x++) + accum += x; + + co_return accum; +} + +void +check_a_coro (struct coro1& x) +{ + if (x.handle.done()) + { + PRINT ("check_a_coro: apparently done when we shouldn't be..."); + abort (); + } + + PRINT ("check_a_coro: resume initial suspend"); + x.handle.resume(); + + // will be false - so no yield expected. + PRINT ("check_a_coro: resume for init"); + x.handle.resume(); + + int y = x.handle.promise().get_value(); + if ( y != 42 ) + { + PRINTF ("check_a_coro: apparently wrong value : %d\n", y); + abort (); + } + + if (!x.handle.done()) + { + PRINT ("check_a_coro: apparently not done..."); + abort (); + } +} + +int main () +{ + { + struct coro1 x = coro_a (false); + check_a_coro (x); + } + + { + struct coro1 x = coro_b (false); + check_a_coro (x); + } + + { + struct coro1 x = coro_c (false); + check_a_coro (x); + } + + PRINT ("main: done"); + return 0; +} diff --git a/gcc/testsuite/g++.dg/coroutines/torture/co-await-25-for-condition.C b/gcc/testsuite/g++.dg/coroutines/torture/co-await-25-for-condition.C new file mode 100644 index 0000000..2208e34 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/co-await-25-for-condition.C @@ -0,0 +1,94 @@ +// { dg-do run } + +// Test co-await in while condition. + +#include "../coro.h" + +// boiler-plate for tests of codegen +#include "../coro1-ret-int-yield-int.h" + +/* An awaiter that suspends always and returns an int as the + await_resume output. */ +struct IntAwaiter { + int v; + IntAwaiter (int _v) : v(_v) {} + bool await_ready () { return false; } + void await_suspend (coro::coroutine_handle<>) {} + int await_resume () { return v; } +}; + +struct coro1 +coro_a (bool t) +{ + int accum = 0; + for (int x = 3; x < co_await IntAwaiter (10); x++) + accum += x; + + co_return accum; +} + +/* An awaiter that suspends always and returns an int as the + await_resume output. */ +struct TenAwaiter { + int v; + TenAwaiter (int _v) : v(_v) {} + bool await_ready () { return false; } + void await_suspend (coro::coroutine_handle<>) {} + bool await_resume () { return v < 10; } +}; + +struct coro1 +coro_b (bool t) +{ + int accum = 0; + for (int x = 3; co_await TenAwaiter (x); x++) + accum += x; + + co_return accum; +} + +void +check_a_coro (struct coro1& x) +{ + if (x.handle.done()) + { + PRINT ("check_a_coro: apparently done when we shouldn't be..."); + abort (); + } + + PRINT ("check_a_coro: resume initial suspend"); + x.handle.resume(); + + // will be false - so no yield expected. + PRINT ("check_a_coro: resume loops"); + while (!x.handle.done()) + x.handle.resume(); + + int y = x.handle.promise().get_value(); + if ( y != 42 ) + { + PRINTF ("check_a_coro: apparently wrong value : %d\n", y); + abort (); + } + + if (!x.handle.done()) + { + PRINT ("check_a_coro: apparently not done..."); + abort (); + } +} + +int main () +{ + { + struct coro1 x = coro_a (false); + check_a_coro (x); + } + { + struct coro1 x = coro_b (false); + check_a_coro (x); + } + + PRINT ("main: returning"); + return 0; +} diff --git a/gcc/testsuite/g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C b/gcc/testsuite/g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C new file mode 100644 index 0000000..f361fb5 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C @@ -0,0 +1,87 @@ +// { dg-do run } + +// Test co-await in while condition. + +#include "../coro.h" + +// boiler-plate for tests of codegen +#include "../coro1-ret-int-yield-int.h" + +/* An awaiter that suspends always and returns an int as the + await_resume output. */ +struct IntAwaiter { + int v; + IntAwaiter (int _v) : v(_v) {} + bool await_ready () { return false; } + void await_suspend (coro::coroutine_handle<>) {} + int await_resume () { return v; } +}; + +coro1 +coro_a (bool t) +{ + int accum = 0; + for (int x = 3; x < 10; x += co_await IntAwaiter (1)) + accum += x; + + co_return accum; +} + +coro1 +coro_b (bool t) +{ + int accum = 0; + for (int x = 3; x < 10; x += co_await IntAwaiter (1)) + { + if (x & 1) + continue; + accum += x; + } + + co_return accum; +} + +void check_a_coro (coro1& x, int expected_answer) +{ + if (x.handle.done()) + { + PRINT ("check_a_coro: apparently done when we shouldn't be..."); + abort (); + } + + PRINT ("check_a_coro: resume initial suspend"); + x.handle.resume(); + + // will be false - so no yield expected. + PRINT ("check_a_coro: resume for init"); + while (!x.handle.done()) + x.handle.resume(); + + int y = x.handle.promise().get_value(); + if ( y != expected_answer ) + { + PRINTF ("check_a_coro: apparently wrong value : %d\n", y); + abort (); + } + + if (!x.handle.done()) + { + PRINT ("check_a_coro: apparently not done..."); + abort (); + } +} + +int main () +{ + { + coro1 x = coro_a (false); + check_a_coro (x, 42); + } + { + coro1 x = coro_b (false); + check_a_coro (x, 18); + } + + PRINT ("main: done"); + return 0; +} -- cgit v1.1 From 020b286c769f4dc8a6b45491351f6bc2e69d7a7f Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Thu, 11 Mar 2021 17:04:14 +0000 Subject: coroutines : Handle rethrow from unhandled_exception [PR98704]. Although there is still some discussion in CWG 2451 on this, the implementors are agreed on the intent. When promise.unhandled_exception () is entered, the coroutine is considered to be still running - returning from the method will cause the final await expression to be evaluated. If the method throws, that action is considered to make the coroutine suspend (since, otherwise, it would be impossible to reclaim its resources, since one cannot destroy a running coro). The wording issue is to do with how to represent the place at which the coroutine should be considered suspended. For the implementation here, that place is immediately before the promise life-time ends. A handler for the rethrown exception, can thus call xxxx.destroy() which will run DTORs for the promise and any parameter copies [as needed] then the coroutine frame will be deallocated. At present, we also set "done=true" in this case (for compatibility with other current implementations). One might consider 'done()' to be misleading in the case of an abnormal termination - that is also part of the CWG 2451 discussion. gcc/cp/ChangeLog: PR c++/98704 * coroutines.cc (build_actor_fn): Make destroy index 1 correspond to the abnormal unhandled_exception() exit. Substitute the proxy for the resume index. (coro_rewrite_function_body): Arrange to reset the resume index and make done = true for a rethrown exception from unhandled_exception (). (morph_fn_to_coro): Adjust calls to build_actor_fn and coro_rewrite_function_body. gcc/testsuite/ChangeLog: PR c++/98704 * g++.dg/coroutines/torture/pr98704.C: New test. --- gcc/testsuite/g++.dg/coroutines/torture/pr98704.C | 91 +++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/pr98704.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/coroutines/torture/pr98704.C b/gcc/testsuite/g++.dg/coroutines/torture/pr98704.C new file mode 100644 index 0000000..15db250 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/pr98704.C @@ -0,0 +1,91 @@ +// { dg-do run } +#include "../coro.h" + +#include + +int frame_live = 0; +int promise_live = 0; +int task_live = 0; + +struct Task +{ + struct promise_type; + using handle = std::coroutine_handle; + + struct promise_type + { + promise_type () { promise_live++; PRINT ("promise_type ()"); } + ~promise_type () { promise_live--; PRINT ("~promise_type ()"); } + void* operator new(size_t sz) { + PRINT("operator new()"); + frame_live++; + return ::operator new(sz); + } + void operator delete(void* p, size_t sz) { + PRINT("operator delete"); + frame_live--; + return ::operator delete(p, sz); + } + + Task get_return_object() { return handle::from_promise(*this); } + auto initial_suspend() noexcept { return std::suspend_always{}; } + auto final_suspend() noexcept { return std::suspend_always{}; } + void return_void() noexcept {} + + auto yield_value(int x) noexcept + { + PRINTF ("yield_value(%d)\n", x); + return std::suspend_always{}; + } + + void unhandled_exception() + { + PRINT ("unhandled_exception()"); + throw; + } + }; + + Task(handle h) : coro(h) { task_live++; PRINT ("Task(handle h)"); } + ~Task() { task_live--; PRINT ("~Task()"); if (coro) coro.destroy(); } + + handle coro; +}; + +Task myco() +{ + co_yield 42; + throw std::out_of_range("TEST EXCEPTION"); +} + +int main() +{ + { + Task task = myco(); + PRINT ("START"); + try { + PRINTF ("done #0 = %d\n", task.coro.done()); + if (task.coro.done()) + abort(); + task.coro.resume(); // will yield 42 + PRINTF ("done #1 = %d\n", task.coro.done()); + if (task.coro.done()) + abort(); + task.coro.resume(); // will throw exception + PRINT ("should not be reached"); + abort (); + } + catch (const std::exception&) { + PRINTF ("done exc = %d\n", task.coro.done()); + if (!task.coro.done()) + abort(); + } + if (!task.coro.done()) + abort(); + } // should cause cause the destroy () to run. + if (task_live || promise_live || frame_live) + { + PRINTF ("task_live = %d, promise_live = %d, frame_live = %d\n", + task_live, promise_live, frame_live); + abort (); + } +} -- cgit v1.1 From 541840b891d61ea70cddd046c96698bb70d7f52c Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Sun, 14 Mar 2021 14:42:52 +0000 Subject: coroutines : Convert await_ready () expressions to bool [PR99047]. The awaiter.await_ready() should be converted per [expr.await]/3 (3.6) await-ready is the expression e.await_ready(), contextually converted to bool. gcc/cp/ChangeLog: PR c++/99047 * coroutines.cc (expand_one_await_expression): If the await_ready() expression is not a boolean then convert it as required. gcc/testsuite/ChangeLog: PR c++/99047 * g++.dg/coroutines/pr99047.C: New test. --- gcc/testsuite/g++.dg/coroutines/pr99047.C | 83 +++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 gcc/testsuite/g++.dg/coroutines/pr99047.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/coroutines/pr99047.C b/gcc/testsuite/g++.dg/coroutines/pr99047.C new file mode 100644 index 0000000..124633a --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr99047.C @@ -0,0 +1,83 @@ +#include +#include + +template +struct [[nodiscard]] task { + struct promise_type { + std::suspend_always initial_suspend() { + return {}; + } + auto final_suspend() noexcept { + struct awaiter { +#if 1 + std::false_type await_ready() noexcept { + return {}; + } +#else + bool await_ready() noexcept { + return false; + } +#endif + std::coroutine_handle<> await_suspend(std::coroutine_handle<>) noexcept { + return next; + } + void await_resume() noexcept { + } + std::coroutine_handle<> next; + }; + return awaiter{next}; + } + + void unhandled_exception() noexcept { + std::terminate(); + } + auto get_return_object() { + return task(this); + } + auto coro() { + return std::coroutine_handle::from_promise(*this); + } + void return_value(T val) { + result.emplace(std::move(val)); + } + + std::coroutine_handle<> next; + std::optional result; + }; + + task(task&& source) : p(std::exchange(source.p, nullptr)) {} + explicit task(promise_type* p) : p(p) {} + ~task() { + if (p) + p->coro().destroy(); + } + + bool await_ready() noexcept { + return p->coro().done(); + } + std::coroutine_handle<> await_suspend(std::coroutine_handle<> next) noexcept { + p->next = next; + return p->coro(); + } + const T& await_resume() const& noexcept { + return *p->result; + } + + promise_type* p; +}; + +task five() { + co_return 5; +} + +task six() { + co_return co_await five() + 1; +} + + +int main() { + auto task = six(); + task.p->next = std::noop_coroutine(); + task.p->coro().resume(); + return *task.p->result; +} -- cgit v1.1 From 770d3487ef18a71f65626c182625889eee29f580 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 15 Mar 2021 15:25:32 -0400 Subject: c++: Fix 2 testcases [PR 99601] I'd failed to correctly restrict some checks to lp64 x86 targets. PR c++/99601 gcc/testsuite/ * g++.dg/modules/builtin-3_a.C: Fix lp64 x86 detection. * g++.dg/modules/builtin-3_b.C: Fix lp64 x86 detection. --- gcc/testsuite/g++.dg/modules/builtin-3_a.C | 4 ++-- gcc/testsuite/g++.dg/modules/builtin-3_b.C | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/modules/builtin-3_a.C b/gcc/testsuite/g++.dg/modules/builtin-3_a.C index ad30ccf..5f61fa4 100644 --- a/gcc/testsuite/g++.dg/modules/builtin-3_a.C +++ b/gcc/testsuite/g++.dg/modules/builtin-3_a.C @@ -30,8 +30,8 @@ export inline int count (int a, ...) // The implementation details of va_list's are target-specific. // Usually one of two patterns though // { dg-final { scan-lang-dump-not { Cluster members:\n \[0\]=decl declaration '::__builtin_va_list'\n \[1\]=binding '::__builtin_va_list'\n} module { target i?86-*-linux* x86_64-*-linux* } } } -// { dg-final { scan-lang-dump {Wrote GMF:-[0-9]* type_decl:'::__builtin_va_list'@builtins} module { target x86_64-*-linux* } } } -// { dg-final { scan-lang-dump {Writing:-[0-9]*'s named merge key \(decl\) type_decl:'::__builtin_va_list'} module { target x86_64-*-linux* } } } +// { dg-final { scan-lang-dump {Wrote GMF:-[0-9]* type_decl:'::__builtin_va_list'@builtins} module { { target x86_64-*-linux* i>86-*-linux* } && lp64 } } +// { dg-final { scan-lang-dump {Writing:-[0-9]*'s named merge key \(decl\) type_decl:'::__builtin_va_list'} module { target { x86_64-*-linux* i?86-*-linux* } && lp64 } } } // { dg-final { scan-lang-dump {Writing:-1's named merge key \(decl\) type_decl:'::__gnuc_va_list'} module { target i?86-*-linux* *-*-darwin* } } } // { dg-final { scan-lang-dump {Wrote GMF:-3 type_decl:'::__gnuc_va_list'@builtins} module { target i?86-*-linux* *-*-darwin* } } } diff --git a/gcc/testsuite/g++.dg/modules/builtin-3_b.C b/gcc/testsuite/g++.dg/modules/builtin-3_b.C index 93489bd..5c94890 100644 --- a/gcc/testsuite/g++.dg/modules/builtin-3_b.C +++ b/gcc/testsuite/g++.dg/modules/builtin-3_b.C @@ -8,6 +8,6 @@ int main () } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) function_decl:'::__builtin_strlen'} module } } -// { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) type_decl:'::__builtin_va_list'} module { target { x86_64-*-linux* } } } } +// { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) type_decl:'::__builtin_va_list'} module { target { { x86_64-*-linux* i?86-*-linux* } && lp64 } } } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(new\) type_decl:'::va_list'} module } } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(new\) type_decl:'::__gnuc_va_list'} module } } -- cgit v1.1 From 1973beaf92c629f26df98eff33ab1bce7f3ea4ef Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 16 Mar 2021 00:24:15 +0100 Subject: testsuite: Fix up target selector syntax errors in modules/builtin-3*.C [PR99601] Without this patch I'm seeing: ERROR: tcl error sourcing /home/jakub/src/gcc/gcc/testsuite/g++.dg/modules/modules.exp. ERROR: unmatched open brace in list while executing "foreach op $tmp { switch [lindex $op 0] { "dg-options" { set std_prefix "-std=gnu++" if { [string match "*-std=*" [lindex $op 2]] } { ..." (procedure "module-init" line 7) invoked from within "module-init $src" invoked from within "if [runtest_file_p $runtests $src] { set tests [lsort [find [file dirname $src] [regsub {_a.[CHX]$} [file tail $src] {_[a-z].[CHX]}]]] set std_lis..." ("foreach" body line 3) invoked from within "foreach src [lsort [find $srcdir/$subdir {*_a.[CHX}]] { # use the FOO_a.C name as the parallelization key if [runtest_file_p $runtests $src] {..." (file "/home/jakub/src/gcc/gcc/testsuite/g++.dg/modules/modules.exp" line 304) invoked from within "source /home/jakub/src/gcc/gcc/testsuite/g++.dg/modules/modules.exp" ("uplevel" body line 1) invoked from within "uplevel #0 source /home/jakub/src/gcc/gcc/testsuite/g++.dg/modules/modules.exp" invoked from within "catch "uplevel #0 source $test_file_name"" 2021-03-16 Jakub Jelinek PR c++/99601 * g++.dg/modules/builtin-3_a.C: Fix target selector syntax errors. * g++.dg/modules/builtin-3_b.C: Likewise. --- gcc/testsuite/g++.dg/modules/builtin-3_a.C | 4 ++-- gcc/testsuite/g++.dg/modules/builtin-3_b.C | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/modules/builtin-3_a.C b/gcc/testsuite/g++.dg/modules/builtin-3_a.C index 5f61fa4..fb7da61 100644 --- a/gcc/testsuite/g++.dg/modules/builtin-3_a.C +++ b/gcc/testsuite/g++.dg/modules/builtin-3_a.C @@ -30,8 +30,8 @@ export inline int count (int a, ...) // The implementation details of va_list's are target-specific. // Usually one of two patterns though // { dg-final { scan-lang-dump-not { Cluster members:\n \[0\]=decl declaration '::__builtin_va_list'\n \[1\]=binding '::__builtin_va_list'\n} module { target i?86-*-linux* x86_64-*-linux* } } } -// { dg-final { scan-lang-dump {Wrote GMF:-[0-9]* type_decl:'::__builtin_va_list'@builtins} module { { target x86_64-*-linux* i>86-*-linux* } && lp64 } } -// { dg-final { scan-lang-dump {Writing:-[0-9]*'s named merge key \(decl\) type_decl:'::__builtin_va_list'} module { target { x86_64-*-linux* i?86-*-linux* } && lp64 } } } +// { dg-final { scan-lang-dump {Wrote GMF:-[0-9]* type_decl:'::__builtin_va_list'@builtins} module { target { { x86_64-*-linux* i?86-*-linux* } && lp64 } } } } +// { dg-final { scan-lang-dump {Writing:-[0-9]*'s named merge key \(decl\) type_decl:'::__builtin_va_list'} module { target { { x86_64-*-linux* i?86-*-linux* } && lp64 } } } } // { dg-final { scan-lang-dump {Writing:-1's named merge key \(decl\) type_decl:'::__gnuc_va_list'} module { target i?86-*-linux* *-*-darwin* } } } // { dg-final { scan-lang-dump {Wrote GMF:-3 type_decl:'::__gnuc_va_list'@builtins} module { target i?86-*-linux* *-*-darwin* } } } diff --git a/gcc/testsuite/g++.dg/modules/builtin-3_b.C b/gcc/testsuite/g++.dg/modules/builtin-3_b.C index 5c94890..e0e6306 100644 --- a/gcc/testsuite/g++.dg/modules/builtin-3_b.C +++ b/gcc/testsuite/g++.dg/modules/builtin-3_b.C @@ -8,6 +8,6 @@ int main () } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) function_decl:'::__builtin_strlen'} module } } -// { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) type_decl:'::__builtin_va_list'} module { target { { x86_64-*-linux* i?86-*-linux* } && lp64 } } } +// { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(matched\) type_decl:'::__builtin_va_list'} module { target { { x86_64-*-linux* i?86-*-linux* } && lp64 } } } } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(new\) type_decl:'::va_list'} module } } // { dg-final { scan-lang-dump {Read:-[0-9]*'s named merge key \(new\) type_decl:'::__gnuc_va_list'} module } } -- cgit v1.1 From fcefc59befd396267b824c170b6a37acaf10874e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 16 Mar 2021 10:34:44 +0100 Subject: aarch64: Fix up aarch64_simd_clone_compute_vecsize_and_simdlen [PR99542] As the patch shows, there are several bugs in aarch64_simd_clone_compute_vecsize_and_simdlen. One is that unlike for function declarations that aren't definitions it completely ignores argument types. Such decls don't have DECL_ARGUMENTS, but we can walk TYPE_ARG_TYPES instead, like the i386 backend does or like the simd cloning code in the middle end does too. Another problem is that it checks types of uniform arguments. That is unnecessary, uniform arguments are passed the way it normally is, it is a scalar argument rather than vector, so there is no reason not to support uniform argument of different size, or long double, structure etc. 2021-03-16 Jakub Jelinek PR target/99542 * config/aarch64/aarch64.c (aarch64_simd_clone_compute_vecsize_and_simdlen): If not a function definition, walk TYPE_ARG_TYPES list if non-NULL for argument types instead of DECL_ARGUMENTS. Ignore types for uniform arguments. * gcc.dg/gomp/pr99542.c: New test. * gcc.dg/gomp/pr59669-2.c (bar): Don't expect a warning on aarch64. * gcc.dg/gomp/simd-clones-2.c (setArray): Likewise. * g++.dg/vect/simd-clone-7.cc (bar): Likewise. * g++.dg/gomp/declare-simd-1.C (f37): Expect a different warning on aarch64. * gcc.dg/declare-simd.c (fn2): Expect a new warning on aarch64. --- gcc/testsuite/g++.dg/gomp/declare-simd-1.C | 2 +- gcc/testsuite/g++.dg/vect/simd-clone-7.cc | 2 -- gcc/testsuite/gcc.dg/declare-simd.c | 1 + gcc/testsuite/gcc.dg/gomp/pr59669-2.c | 1 - gcc/testsuite/gcc.dg/gomp/pr99542.c | 17 +++++++++++++++++ gcc/testsuite/gcc.dg/gomp/simd-clones-2.c | 1 - 6 files changed, 19 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/gomp/pr99542.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C index dcffaec..00996b6 100644 --- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C +++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C @@ -287,7 +287,7 @@ struct D int f37 (int a); int e; }; -// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-3 } +// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-3 } void f38 (D &d) diff --git a/gcc/testsuite/g++.dg/vect/simd-clone-7.cc b/gcc/testsuite/g++.dg/vect/simd-clone-7.cc index 527bbd9..fd5751b 100644 --- a/gcc/testsuite/g++.dg/vect/simd-clone-7.cc +++ b/gcc/testsuite/g++.dg/vect/simd-clone-7.cc @@ -8,5 +8,3 @@ bar (float x, float *y, int) { return y[0] + y[1] * x; } -// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target { { aarch64*-*-* } && lp64 } } .-4 } - diff --git a/gcc/testsuite/gcc.dg/declare-simd.c b/gcc/testsuite/gcc.dg/declare-simd.c index 1c71b60..52796f6 100644 --- a/gcc/testsuite/gcc.dg/declare-simd.c +++ b/gcc/testsuite/gcc.dg/declare-simd.c @@ -3,6 +3,7 @@ #pragma omp declare simd linear (p2, p3) extern void fn2 (float p1, float *p2, float *p3); +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-1 } */ float *a, *b; void fn1 (float *p1) diff --git a/gcc/testsuite/gcc.dg/gomp/pr59669-2.c b/gcc/testsuite/gcc.dg/gomp/pr59669-2.c index 26a30f4..f6aad89 100644 --- a/gcc/testsuite/gcc.dg/gomp/pr59669-2.c +++ b/gcc/testsuite/gcc.dg/gomp/pr59669-2.c @@ -7,4 +7,3 @@ void bar (int *a) { } -/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-3 } */ diff --git a/gcc/testsuite/gcc.dg/gomp/pr99542.c b/gcc/testsuite/gcc.dg/gomp/pr99542.c new file mode 100644 index 0000000..b67ff5a --- /dev/null +++ b/gcc/testsuite/gcc.dg/gomp/pr99542.c @@ -0,0 +1,17 @@ +/* PR middle-end/89246 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O0 -fopenmp-simd" } */ + +#pragma omp declare simd +extern int foo (__int128 x); /* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } } */ +/* { dg-warning "unsupported argument type '__int128' for simd" "" { target i?86-*-* x86_64-*-* } .-1 } */ + +#pragma omp declare simd uniform (x) +extern int baz (__int128 x); + +#pragma omp declare simd +int +bar (int x) +{ + return x + foo (0) + baz (0); +} diff --git a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c index 844b80b..75554de 100644 --- a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c +++ b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c @@ -15,7 +15,6 @@ float setArray(float *a, float x, int k) return a[k]; } -/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-6 } */ /* { dg-final { scan-tree-dump "_ZGVbN4ua32vl_setArray" "optimized" { target i?86-*-* x86_64-*-* } } } */ /* { dg-final { scan-tree-dump "_ZGVbN4vvva32_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */ /* { dg-final { scan-tree-dump "_ZGVbM4vl66u_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */ -- cgit v1.1 From 82085eb3d44833bd1557fdd932c4738d987f559d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 16 Mar 2021 11:16:15 +0100 Subject: i386: Fix up _mm256_vzeroupper() handling [PR99563] My r10-6451-gb7b3378f91c0641f2ef4d88db22af62a571c9359 fix for vzeroupper vs. ms ABI apparently broke the explicit vzeroupper handling when the implicit vzeroupper handling is disabled. The epilogue_completed splitter for vzeroupper now adds clobbers for all registers which don't have explicit sets in the pattern and the sets are added during vzeroupper pass. Before my changes, for explicit user vzeroupper, we just weren't modelling its effects at all, it was just unspec that didn't tell that it clobbers the upper parts of all XMM < %xmm16 registers. But now the splitter will even for those add clobbers and as it has no sets, it will add clobbers for all registers, which means we optimize away anything that lived across that vzeroupper. The vzeroupper pass has two parts, one is the mode switching that computes where to put the implicit vzeroupper calls and puts them there, and then another that uses df to figure out what sets to add to all the vzeroupper. The former part should be done only under the conditions we have in the gate, but the latter as this PR shows needs to happen either if we perform the implicit vzeroupper additions, or if there are (or could be) any explicit vzeroupper instructions. As that function does df_analyze and walks the whole IL, I think it would be too expensive to run it always whenever TARGET_AVX, so this patch remembers if we've expanded at least one __builtin_ia32_vzeroupper in the function and runs that part of the vzeroupper pass both when the old condition is true or when this new flag is set. 2021-03-16 Jakub Jelinek PR target/99563 * config/i386/i386.h (struct machine_function): Add has_explicit_vzeroupper bitfield. * config/i386/i386-expand.c (ix86_expand_builtin): Set cfun->machine->has_explicit_vzeroupper when expanding IX86_BUILTIN_VZEROUPPER. * config/i386/i386-features.c (rest_of_handle_insert_vzeroupper): Do the mode switching only when TARGET_VZEROUPPER, expensive optimizations turned on and not optimizing for size. (pass_insert_vzeroupper::gate): Enable even when cfun->machine->has_explicit_vzeroupper is set. * gcc.target/i386/avx-pr99563.c: New test. --- gcc/testsuite/gcc.target/i386/avx-pr99563.c | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx-pr99563.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/i386/avx-pr99563.c b/gcc/testsuite/gcc.target/i386/avx-pr99563.c new file mode 100644 index 0000000..e2e863b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr99563.c @@ -0,0 +1,38 @@ +/* PR target/99563 */ +/* { dg-do run { target avx } } */ +/* { dg-options "-O2 -mavx -mno-vzeroupper" } */ + +#include "avx-check.h" +#include + + +__attribute__((noipa)) float +compute_generic (void) +{ + return 0.0f; +} + +static inline __attribute__((always_inline)) +float compute_avx (unsigned long block_count) +{ + __m128d mm_res = _mm_set1_pd (256.0); + float res = (float) (_mm_cvtsd_f64 (mm_res) / (double) block_count); + _mm256_zeroupper (); + return res; +} + +__attribute__((noipa)) float +compute (unsigned long block_count) +{ + if (block_count >= 64) + return compute_avx (block_count); + else + return compute_generic (); +} + +static void +avx_test (void) +{ + if (compute (128) != 2.0f || compute (32) != 0.0f) + abort (); +} -- cgit v1.1 From 3c5b6d24e664f951c6b4e42738aa1ef5489e5f66 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 16 Mar 2021 10:55:35 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 72 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2c7b81b..5ce7c1c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,75 @@ +2021-03-16 Jakub Jelinek + + PR target/99563 + * gcc.target/i386/avx-pr99563.c: New test. + +2021-03-16 Jakub Jelinek + + PR target/99542 + * gcc.dg/gomp/pr99542.c: New test. + * gcc.dg/gomp/pr59669-2.c (bar): Don't expect a warning on aarch64. + * gcc.dg/gomp/simd-clones-2.c (setArray): Likewise. + * g++.dg/vect/simd-clone-7.cc (bar): Likewise. + * g++.dg/gomp/declare-simd-1.C (f37): Expect a different warning + on aarch64. + * gcc.dg/declare-simd.c (fn2): Expect a new warning on aarch64. + +2021-03-15 Jakub Jelinek + + PR c++/99601 + * g++.dg/modules/builtin-3_a.C: Fix target selector syntax errors. + * g++.dg/modules/builtin-3_b.C: Likewise. + +2021-03-15 Nathan Sidwell + + PR c++/99601 + * g++.dg/modules/builtin-3_a.C: Fix lp64 x86 detection. + * g++.dg/modules/builtin-3_b.C: Fix lp64 x86 detection. + +2021-03-15 Iain Sandoe + + PR c++/99047 + * g++.dg/coroutines/pr99047.C: New test. + +2021-03-15 Iain Sandoe + + PR c++/98704 + * g++.dg/coroutines/torture/pr98704.C: New test. + +2021-03-15 Iain Sandoe + + PR c++/98480 + * g++.dg/coroutines/pr98480.C: New test. + * g++.dg/coroutines/torture/co-await-24-for-init.C: New test. + * g++.dg/coroutines/torture/co-await-25-for-condition.C: New test. + * g++.dg/coroutines/torture/co-await-26-for-iteration-expr.C: New test. + +2021-03-15 Iain Sandoe + + PR c++/96749 + * g++.dg/coroutines/pr96749-1.C: New test. + * g++.dg/coroutines/pr96749-2.C: New test. + +2021-03-15 Richard Biener + + PR tree-optimization/98834 + * g++.dg/opt/pr98834.C: New testcase. + +2021-03-15 Thomas Koenig + + PR fortran/99345 + * gfortran.dg/do_check_16.f90: New test. + * gfortran.dg/do_check_17.f90: New test. + +2021-03-15 Paul Thomas + + PR fortran/99545 + * gfortran.dg/pr99545.f90: New test. + +2021-03-15 David Edelsohn + + * gcc.target/powerpc/pr99492.c: Fix typo. + 2021-03-14 Harald Anlauf Paul Thomas -- cgit v1.1 From 7b900dca607dceaae2db372365f682a4979c7826 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 15 Mar 2021 11:25:46 -0700 Subject: c++: Incorrect type equivalence [PR 99496] This bug was caused by not marking dependent template aliases correctly -- these things look like typedefs, but are not (necessarily) equivalent to the canonical type. We need to record that. PR c++/99496 gcc/cp/ * module.cc (trees_out::decl_value): Adjust typedef streaming, indicate whether it is a dependent alias. (trees_in::decl_value): Likewise. Set as dependent alias, if it is one. gcc/testsuite/ * g++.dg/modules/pr99496_a.H: New. * g++.dg/modules/pr99496_b.C: New. --- gcc/testsuite/g++.dg/modules/pr99496_a.H | 17 +++++++++++++++++ gcc/testsuite/g++.dg/modules/pr99496_b.C | 3 +++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/g++.dg/modules/pr99496_a.H create mode 100644 gcc/testsuite/g++.dg/modules/pr99496_b.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/modules/pr99496_a.H b/gcc/testsuite/g++.dg/modules/pr99496_a.H new file mode 100644 index 0000000..71b77fb --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr99496_a.H @@ -0,0 +1,17 @@ +// PR 99496 different types with same canonical +// (requires spec hasher to be a constant, so we get collisions) +// { dg-additional-options -fmodule-header } +// { dg-module-cmi {} } + +template using __void_t = void; + +template +struct __is_referenceable +{ }; + +template +struct __is_referenceable<_Tp, __void_t<_Tp&>> +{ }; + +template::value> +struct __is_copy_constructible_impl; diff --git a/gcc/testsuite/g++.dg/modules/pr99496_b.C b/gcc/testsuite/g++.dg/modules/pr99496_b.C new file mode 100644 index 0000000..57b71d1 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr99496_b.C @@ -0,0 +1,3 @@ +// { dg-additional-options {-fmodules-ts -fno-module-lazy} } + +import "pr99496_a.H"; -- cgit v1.1 From 4073a09e23944b17cd1afce77025b1ea19b28ced Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Thu, 10 Dec 2020 15:43:59 +0100 Subject: IBM Z: Fix "+fvm" constraint with long doubles When a long double is passed to an asm statement with a "+fvm" constraint, a LRA loop occurs. This happens, because LRA chooses the widest register class in this case (VEC_REGS), but the code generated by s390_md_asm_adjust() always wants FP_REGS. Mismatching register classes cause infinite reloading. Fix by treating "fv" constraints as "v" in s390_md_asm_adjust(). gcc/ChangeLog: * config/s390/s390.c (f_constraint_p): Treat "fv" constraints as "v". gcc/testsuite/ChangeLog: * gcc.target/s390/vector/long-double-asm-fprvrmem.c: New test. --- .../gcc.target/s390/vector/long-double-asm-fprvrmem.c | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/vector/long-double-asm-fprvrmem.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/s390/vector/long-double-asm-fprvrmem.c b/gcc/testsuite/gcc.target/s390/vector/long-double-asm-fprvrmem.c new file mode 100644 index 0000000..f95656c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/long-double-asm-fprvrmem.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzarch" } */ + +long double +foo (long double x) +{ + x = x * x; + asm("# %0" : "+fvm"(x)); + x = x + x; + return x; +} -- cgit v1.1 From 408d137027b1c39546d39fdbca7347b3dddba8ea Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Tue, 16 Mar 2021 14:42:01 +0100 Subject: options: ignore flag_ipa_ra in cl_optimization_compare gcc/ChangeLog: PR target/99592 * optc-save-gen.awk: Add flag_ipa_ra to exceptions for cl_optimization_compare function. gcc/testsuite/ChangeLog: PR target/99592 * gcc.target/arm/pr99592.c: New test. --- gcc/testsuite/gcc.target/arm/pr99592.c | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/pr99592.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/arm/pr99592.c b/gcc/testsuite/gcc.target/arm/pr99592.c new file mode 100644 index 0000000..23d6591 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr99592.c @@ -0,0 +1,7 @@ +/* PR target/99592 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -pg" } */ + +#pragma GCC push_options +#pragma GCC target "" +#pragma GCC pop_options -- cgit v1.1 From 1c7bec8bfbc5457c1b57d0e3b67f5d6bc8812e57 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Wed, 3 Mar 2021 09:38:55 +0100 Subject: c++: support target attr for DECL_LOCAL_DECL_P fns [PR99108] We crash when target attribute get_function_versions_dispatcher is called for a function that is not registered in call graph. This was happening because we were calling it for the function-local decls that aren't in the symbol table, instead of the corresponding namespace-scope decls that are. gcc/cp/ChangeLog: PR c++/99108 * call.c (get_function_version_dispatcher): Handle DECL_LOCAL_DECL_P. * decl.c (maybe_version_functions): Likewise. (maybe_mark_function_versioned): New. * name-lookup.c (push_local_extern_decl_alias): No longer static. * name-lookup.h (push_local_extern_decl_alias): Adjust. gcc/testsuite/ChangeLog: PR c++/99108 * g++.target/i386/pr99108.C: New test. Co-authored-by: Jason Merrill --- gcc/testsuite/g++.target/i386/pr99108.C | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 gcc/testsuite/g++.target/i386/pr99108.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.target/i386/pr99108.C b/gcc/testsuite/g++.target/i386/pr99108.C new file mode 100644 index 0000000..b1f0a71 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr99108.C @@ -0,0 +1,19 @@ +/* PR c++/99108 */ +/* { dg-require-ifunc "" } */ + +struct A { + template + void foo(T); +}; +template +void A::foo(T) +{ + int f(void) __attribute__((target("default"))); + int f(void) __attribute__((target("arch=atom"))); + int b = f(); +} +void bar(void) +{ + A c; + c.foo(7); +} -- cgit v1.1 From d55ce33a34a8e33d17285228b32cf1e564241a70 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 16 Mar 2021 18:46:20 +0100 Subject: i386: Avoid mutual recursion between two peephole2s [PR99600] As the testcase shows, the compiler hangs and eats all memory when compiling it. This is because in r11-7274-gdecd8fb0128870d0d768ba53dae626913d6d9c54 I have changed the ix86_avoid_lea_for_addr splitting from a splitter into a peephole2 (because during splitting passes we don't have guaranteed df, while during peephole2 we do). The problem is we have another peephole2 that works in the opposite way, when seeing split lea (in particular ASHIFT followed by PLUS) it attempts to turn it back into a lea. In the past, they were fighting against each other, but as they were in different passes, simply the last one won. So, split after reload split the lea into shift left and plus, peephole2 reverted that (but, note not perfectly, the peephole2 doesn't understand that something can be placed into lea disp; to be fixed for GCC12) and then another split pass split the lea appart again. But my changes and the way peephole2 works means that we endlessly iterate over those two, the first peephole2 splits the lea, the second one reverts it, the first peephole2 splits the new lea back into new 2 insns and so forth forever. So, we need to break the cycle somehow. This patch does that by not emitting an ASHIFT insn from ix86_split_lea_for_addr but emitting a corresponding MULT by constant instead, and splitting that later back into ASHIFT. 2021-03-16 Jakub Jelinek PR target/99600 * config/i386/i386-expand.c (ix86_split_lea_for_addr): Emit a MULT rather than ASHIFT. * config/i386/i386.md (mult by 1248 into ashift): New splitter. * gcc.target/i386/pr99600.c: New test. --- gcc/testsuite/gcc.target/i386/pr99600.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr99600.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/i386/pr99600.c b/gcc/testsuite/gcc.target/i386/pr99600.c new file mode 100644 index 0000000..c2f2b22 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99600.c @@ -0,0 +1,16 @@ +/* PR target/99600 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=atom" } */ + +char a, b; +long c; + +long +foo (void) +{ + if (a) + c = b == 1 ? 1 << 3 : 1 << 2; + else + c = 0; + return 0; +} -- cgit v1.1 From a0b5843a9b2b3e93bd119d5aef583f53ad2ef0bc Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 16 Mar 2021 18:29:11 +0000 Subject: rs6000: Workaround for PR98092 The bcdinvalid_ RTL instruction uses the "unordered" comparison, which cannot be used if we have -ffinite-math-only. We really need CCMODEs that describe what bits in a CR field are set by other insns than just comparisons, but that is a lot more surgery, and it is stage 4 now. This patch does a simple workaround. 2021-03-16 Segher Boessenkool PR target/98092 * config/rs6000/predicates.md (branch_comparison_operator): Allow ordered and unordered for CCFPmode, if flag_finite_math_only. gcc/testsuite/ PR target/98092 * gcc.target/powerpc/pr98092.c: New. --- gcc/testsuite/gcc.target/powerpc/pr98092.c | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr98092.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/powerpc/pr98092.c b/gcc/testsuite/gcc.target/powerpc/pr98092.c new file mode 100644 index 0000000..03eab5a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr98092.c @@ -0,0 +1,7 @@ +/* { dg-options "-mdejagnu-cpu=power9 -ffinite-math-only" } */ + +int +h9 (__attribute__ ((altivec (vector__))) char un) +{ + return (__builtin_vec_bcdinvalid (un)); +} -- cgit v1.1 From a4101e5aafc512dc32b8d529b2bafb116a3612de Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 16 Mar 2021 16:06:27 -0400 Subject: c++: Fix NaN as C++20 template argument C++20 allows floating-point types for non-type template parameters; floating-point values are considered to be equivalent template arguments if they are "identical", which conveniently seems to map onto an existing GCC predicate. gcc/cp/ChangeLog: * tree.c (cp_tree_equal): Use real_identical. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/nontype-float1.C: New test. --- gcc/testsuite/g++.dg/cpp2a/nontype-float1.C | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp2a/nontype-float1.C (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/g++.dg/cpp2a/nontype-float1.C b/gcc/testsuite/g++.dg/cpp2a/nontype-float1.C new file mode 100644 index 0000000..4fafac1 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/nontype-float1.C @@ -0,0 +1,12 @@ +// { dg-do compile { target c++20 } } + +#include + +template class MyClass { }; + +static_assert(__is_same(MyClass, MyClass)); + +constexpr auto mynan = NAN; +static_assert(__is_same(MyClass, MyClass)); + +static_assert(__is_same(MyClass, MyClass)); -- cgit v1.1 From a2a6e9214e27b32d4582c670faf9cdb74e54c2c6 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 16 Mar 2021 21:48:10 +0000 Subject: aarch64: Fix up aarch64_simd_clone_compute_vecsize_and_simdlen [PR99542] The gcc.dg/declare-simd.c test does not emit a warning with -mabi=ilp32. 2021-03-16 Christophe Lyon PR target/99542 gcc/testsuite/ * gcc.dg/declare-simd.c (fn2): Expect a warning only under lp64. --- gcc/testsuite/gcc.dg/declare-simd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.dg/declare-simd.c b/gcc/testsuite/gcc.dg/declare-simd.c index 52796f6..2c8c1b7 100644 --- a/gcc/testsuite/gcc.dg/declare-simd.c +++ b/gcc/testsuite/gcc.dg/declare-simd.c @@ -3,7 +3,7 @@ #pragma omp declare simd linear (p2, p3) extern void fn2 (float p1, float *p2, float *p3); -/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-1 } */ +/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target { { aarch64*-*-* } && lp64 } } .-1 } */ float *a, *b; void fn1 (float *p1) -- cgit v1.1 From bc2127767a0076afdbc9075fda29f97f82ef7ec6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 17 Mar 2021 00:16:25 +0000 Subject: Daily bump. --- gcc/testsuite/ChangeLog | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5ce7c1c..5e6b536 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,44 @@ +2021-03-16 Christophe Lyon + + PR target/99542 + * gcc.dg/declare-simd.c (fn2): Expect a warning only under lp64. + +2021-03-16 Jason Merrill + + * g++.dg/cpp2a/nontype-float1.C: New test. + +2021-03-16 Segher Boessenkool + + PR target/98092 + PR target/98092 + * gcc.target/powerpc/pr98092.c: New. + +2021-03-16 Jakub Jelinek + + PR target/99600 + * gcc.target/i386/pr99600.c: New test. + +2021-03-16 Martin Liska + Jason Merrill + + PR c++/99108 + * g++.target/i386/pr99108.C: New test. + +2021-03-16 Martin Liska + + PR target/99592 + * gcc.target/arm/pr99592.c: New test. + +2021-03-16 Ilya Leoshkevich + + * gcc.target/s390/vector/long-double-asm-fprvrmem.c: New test. + +2021-03-16 Nathan Sidwell + + PR c++/99496 + * g++.dg/modules/pr99496_a.H: New. + * g++.dg/modules/pr99496_b.C: New. + 2021-03-16 Jakub Jelinek PR target/99563 -- cgit v1.1 From adf14bdbc10d4114865a08cf20020a2616039057 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 11 Mar 2021 06:48:24 -0800 Subject: x86: Update 'P' operand modifier for -fno-plt Update 'P' operand modifier for -fno-plt to support inline assembly statements. In 64-bit, we can always load function address with @GOTPCREL. In 32-bit, we load function address with @GOT only for non-PIC since PIC register may not be available at call site. gcc/ PR target/99504 * config/i386/i386.c (ix86_force_load_from_GOT_p): Support inline assembly statements. (ix86_print_operand): Update 'P' handling for -fno-plt. gcc/testsuite/ PR target/99504 * gcc.target/i386/pr99530-1.c: New test. * gcc.target/i386/pr99530-2.c: Likewise. * gcc.target/i386/pr99530-3.c: Likewise. * gcc.target/i386/pr99530-4.c: Likewise. * gcc.target/i386/pr99530-5.c: Likewise. * gcc.target/i386/pr99530-6.c: Likewise. --- gcc/testsuite/gcc.target/i386/pr99530-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr99530-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr99530-3.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr99530-4.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr99530-5.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr99530-6.c | 11 +++++++++++ 6 files changed, 66 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-5.c create mode 100644 gcc/testsuite/gcc.target/i386/pr99530-6.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/i386/pr99530-1.c b/gcc/testsuite/gcc.target/i386/pr99530-1.c new file mode 100644 index 0000000..080d7cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -fpic -mcmodel=large -fno-plt" } */ +/* { dg-final { scan-assembler-not "foo@GOTPCREL" } } */ + +extern void foo (void); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr99530-2.c b/gcc/testsuite/gcc.target/i386/pr99530-2.c new file mode 100644 index 0000000..9808957 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -fno-pic -mcmodel=large -fno-plt" } */ +/* { dg-final { scan-assembler-not "foo@GOTPCREL" } } */ + +extern void foo (void); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr99530-3.c b/gcc/testsuite/gcc.target/i386/pr99530-3.c new file mode 100644 index 0000000..22fe81b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-options "-O2 -fno-pic -fno-plt" } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOT" { target { ia32 && got32x_reloc } } } } */ + +extern void foo (void); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr99530-4.c b/gcc/testsuite/gcc.target/i386/pr99530-4.c new file mode 100644 index 0000000..aba0b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-options "-O2 -fpic -fno-plt" } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "foo@GOT" { target { ia32 } } } } */ + +extern void foo (void); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr99530-5.c b/gcc/testsuite/gcc.target/i386/pr99530-5.c new file mode 100644 index 0000000..02c5799 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-options "-O2 -fno-pic" } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOT" { target { ia32 && got32x_reloc } } } } */ + +extern void foo (void) __attribute__ ((noplt)); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr99530-6.c b/gcc/testsuite/gcc.target/i386/pr99530-6.c new file mode 100644 index 0000000..0dfdd37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99530-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */ +/* { dg-options "-O2 -fpic" } */ +/* { dg-final { scan-assembler "call\[ \t\]+\[*\]foo@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "foo@GOT" { target { ia32 } } } } */ + +extern void foo (void) __attribute__ ((noplt)); +void +bar (void) +{ + asm ("call %P0" : : "X" (foo)); +} -- cgit v1.1 From f7581eb38eeaa8af64f3cdfe2faf764f5883f16f Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Wed, 17 Mar 2021 18:21:05 +0000 Subject: aarch64: Fix status return logic in RNG intrinsics There is a bug with the RNG intrinsics in their return code. The definition says: "Stores a 64-bit random number into the object pointed to by the argument and returns zero. If the implementation could not generate a random number within a reasonable period of time the object pointed to by the input is set to zero and a non-zero value is returned." This means we should be testing whether to return non-zero with: CSET W0, EQ rather than NE. This patch fixes that. gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (aarch64_expand_rng_builtin): Use EQ to compare against CC_REG rather than NE. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/rng_2.c: New test. --- gcc/testsuite/gcc.target/aarch64/acle/rng_2.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rng_2.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rng_2.c b/gcc/testsuite/gcc.target/aarch64/acle/rng_2.c new file mode 100644 index 0000000..206136c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/rng_2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.5-a+rng" } */ + +#include + +int test_rndr (uint64_t *addr) +{ + return __rndr (addr); +} + +/* { dg-final { scan-assembler-times {cset\t...?, eq} 1 } } */ + -- cgit v1.1 From 9c4d77fc1cc363342b5963b07e837d2b017cac43 Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Wed, 17 Mar 2021 12:56:49 +0000 Subject: testsuite, Darwin : Fix match output for asan/memcmp-1.c. The Darwin part of libasan produces different output for memcmp cases from other ports. The GCC implementation does produce the same output for this test as the clang one (modulo the two points below). 1. To be more compatible with Linux, Darwin testcases that include string.h should set _FORTIFY_SOURCE=0 since, otherwise, it will be defaulted on and the _chk versions of the string builtins will be used. 2. The system tool that handles symbolization (atos) is not reliable with GCC's DWARF-2 output but, fortunately, all the platform versions that support the current sanitizers are able to handle dwarf-3 for this testcase. gcc/testsuite/ChangeLog: * c-c++-common/asan/memcmp-1.c: Add _FORTIFY_SOURCE=0 and -gdwarf-3 to the command line options. Provide Darwin- specific match lines for the expected output. --- gcc/testsuite/c-c++-common/asan/memcmp-1.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/c-c++-common/asan/memcmp-1.c b/gcc/testsuite/c-c++-common/asan/memcmp-1.c index 0403ad7..0d08c09 100644 --- a/gcc/testsuite/c-c++-common/asan/memcmp-1.c +++ b/gcc/testsuite/c-c++-common/asan/memcmp-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-fno-builtin-memcmp" } */ +/* { dg-additional-options "-D_FORTIFY_SOURCE=0 -gdwarf-3" { target *-*-darwin* } } */ /* { dg-shouldfail "asan" } */ #include @@ -16,5 +17,8 @@ main () } /* { dg-output "ERROR: AddressSanitizer: stack-buffer-overflow.*(\n|\r\n|\r)" } */ -/* { dg-output " #\[1-9\] 0x\[0-9a-f\]+ +(in _*(interceptor_|wrap_|)memcmp|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ -/* { dg-output " #\[2-9\] 0x\[0-9a-f\]+ +(in _*main|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output " #\[1-9\] 0x\[0-9a-f\]+ +(in _*(interceptor_|wrap_|)memcmp|\[(\])\[^\n\r]*(\n|\r\n|\r)" { target { ! *-*-darwin* } } } */ +/* { dg-output " #\[2-9\] 0x\[0-9a-f\]+ +(in _*main|\[(\])\[^\n\r]*(\n|\r\n|\r)" { target { ! *-*-darwin* } } } */ + +/* { dg-output " #\[0-9\] 0x\[0-9a-f\]+ +(in MemcmpInterceptorCommon|\[(\])\[^\n\r]*(\n|\r\n|\r)" { target *-*-darwin* } } */ +/* { dg-output " #\[1-9\] 0x\[0-9a-f\]+ +(in wrap_(memcmp|bcmp)|\[(\])\[^\n\r]*(\n|\r\n|\r)" { target *-*-darwin* } } */ -- cgit v1.1 From c86c5195c8c02f5891a222f498c074b373aa946c Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Wed, 17 Mar 2021 13:05:47 +0000 Subject: testsuite, Darwin : Fix the asan/strncpy-overflow-1 test. 1. To be more compatible with Linux, Darwin testcases that include string.h should set _FORTIFY_SOURCE=0 since, otherwise, it will be defaulted on and the _chk versions of the string builtins will be used. This testcase fails otherwise because there's no convenient way to disable the _chk builtins. 2. The system tool that handles symbolization (atos) is not reliable with GCC's DWARF-2 output but, fortunately, all the platform versions that support the current sanitizers are able to handle dwarf-3 for this testcase. gcc/testsuite/ChangeLog: * c-c++-common/asan/strncpy-overflow-1.c: Add _FORTIFY_SOURCE=0 and -gdwarf-3 to the command line options. Adjust the expected line numbers for the revised options header. --- gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c b/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c index a9c9b18..3d43916 100644 --- a/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c +++ b/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-fno-builtin-malloc -fno-builtin-strncpy" } */ +/* { dg-additional-options "-D_FORTIFY_SOURCE=0 -gdwarf-3" { target *-*-darwin* } } */ /* { dg-shouldfail "asan" } */ #include @@ -14,8 +15,8 @@ int main(int argc, char **argv) { /* { dg-output "WRITE of size \[0-9\]* at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ /* { dg-output " #0 0x\[0-9a-f\]+ +(in _*(interceptor_|wrap_|)strncpy|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ -/* { dg-output " #1 0x\[0-9a-f\]+ +(in _*main (\[^\n\r]*strncpy-overflow-1.c:11|\[^\n\r]*:0|\[^\n\r]*\\+0x\[0-9a-z\]*)|\[(\]).*(\n|\r\n|\r)" } */ +/* { dg-output " #1 0x\[0-9a-f\]+ +(in _*main (\[^\n\r]*strncpy-overflow-1.c:12|\[^\n\r]*:0|\[^\n\r]*\\+0x\[0-9a-z\]*)|\[(\]).*(\n|\r\n|\r)" } */ /* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ /* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ /* { dg-output " #0 0x\[0-9a-f\]+ +(in _*(interceptor_|wrap_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ -/* { dg-output " #1 0x\[0-9a-f\]+ +(in _*main (\[^\n\r]*strncpy-overflow-1.c:10|\[^\n\r]*:0|\[^\n\r]*\\+0x\[0-9a-z\]*)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output " #1 0x\[0-9a-f\]+ +(in _*main (\[^\n\r]*strncpy-overflow-1.c:11|\[^\n\r]*:0|\[^\n\r]*\\+0x\[0-9a-z\]*)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ -- cgit v1.1