From 62e7c496696eb68186616a2fa3654a876d21d695 Mon Sep 17 00:00:00 2001 From: Dimitar Dimitrov Date: Mon, 25 Nov 2024 20:48:00 +0200 Subject: testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E ABIs Some tests add options for V and Zvbb extensions, but those extensions are not compatible with the E ABI variants. This leads to spurious test failures when toolchain's default ABI is ILP32E or ILP64E: spawn ... -march=rv32ecv_zvbb ... cc1: error: ILP32E ABI does not support the 'D' extension cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension Fix by skipping the tests when toolchain's default ABI is E variant. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Skip if default is E ABI. * gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-1.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-2.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-3.c: Ditto. * gcc.target/riscv/rvv/base/movmem-1.c: Ditto. * gcc.target/riscv/rvv/base/pr115068.c: Ditto. * gcc.target/riscv/rvv/base/setmem-1.c: Ditto. * gcc.target/riscv/rvv/base/setmem-2.c: Ditto. * gcc.target/riscv/rvv/base/setmem-3.c: Ditto. * gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto. Signed-off-by: Dimitar Dimitrov --- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h | 2 +- .../riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c index 3bb5bf8..dfdc64b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c index 55dac27..1c5f6e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c index a2e5b4f..0a67db7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h index 376cbae..89b7624 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c index 1fd3644..de5a5ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c index c27d9d3..483b58f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c index d5989bd..2425dc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c index 1396e46..12324f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c index 116cc304..7e68803 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c index 00b87a0..6bf8909 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c index 6bc8b07..9edd6cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c index 5ca31af..82aa307 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c index 5860b27..e2dd6a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 81d14d8..654c800 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c index 7b6a429..3d79b59 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c index f07078b..2b75b31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c index 1f148bc..03e633b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c index 8359e81..af2cba6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-std=gnu99" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c index 22844ff..a22d366 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c index 838fbeb..a108868 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c index 4493381..460a8f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 196215a..6e027a5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -- cgit v1.1