From 927fb0bc9b915bbe32b4d137adbbcdd3375e119a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 16 Mar 2018 22:01:16 +0100 Subject: re PR target/84899 (ICE: in final_scan_insn_1, at final.c:3139 (error: could not split insn)) PR target/84899 * postreload.c (reload_combine_recognize_pattern): Perform INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and truncate_int_for_mode the result for the destination's mode. * gcc.dg/pr84899.c: New test. From-SVN: r258610 --- gcc/postreload.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'gcc/postreload.c') diff --git a/gcc/postreload.c b/gcc/postreload.c index af9ad82..0638709 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -1157,11 +1157,13 @@ reload_combine_recognize_pattern (rtx_insn *insn) value in PREV, the constant loading instruction. */ validate_change (prev, &SET_DEST (prev_set), index_reg, 1); if (reg_state[regno].offset != const0_rtx) - validate_change (prev, - &SET_SRC (prev_set), - GEN_INT (INTVAL (SET_SRC (prev_set)) - + INTVAL (reg_state[regno].offset)), - 1); + { + HOST_WIDE_INT c + = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set)) + + UINTVAL (reg_state[regno].offset), + GET_MODE (index_reg)); + validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1); + } /* Now for every use of REG that we have recorded, replace REG with REG_SUM. */ -- cgit v1.1