From ef339d6e2e846ba7ff544def1d79f10762da223d Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 1 Nov 2017 11:22:35 +0000 Subject: Add a VEC_SERIES rtl code This patch adds an rtl representation of a vector linear series of the form: a[I] = BASE + I * STEP Like vec_duplicate; - the new rtx can be used for both constant and non-constant vectors - when used for constant vectors it is wrapped in a (const ...) - the constant form is only used for variable-length vectors; fixed-length vectors still use CONST_VECTOR At the moment the code is restricted to integer elements, to avoid concerns over floating-point rounding. 2017-11-01 Richard Sandiford Alan Hayward David Sherwood gcc/ * doc/rtl.texi (vec_series): Document. (const): Say that the operand can be a vec_series. * rtl.def (VEC_SERIES): New rtx code. * rtl.h (const_vec_series_p_1): Declare. (const_vec_series_p): New function. * emit-rtl.h (gen_const_vec_series): Declare. (gen_vec_series): Likewise. * emit-rtl.c (const_vec_series_p_1, gen_const_vec_series) (gen_vec_series): Likewise. * optabs.c (expand_mult_highpart): Use gen_const_vec_series. * simplify-rtx.c (simplify_unary_operation): Handle negations of vector series. (simplify_binary_operation_series): New function. (simplify_binary_operation_1): Use it. Handle VEC_SERIES. (test_vector_ops_series): New function. (test_vector_ops): Call it. * config/powerpcspe/altivec.md (altivec_lvsl): Use gen_const_vec_series. (altivec_lvsr): Likewise. * config/rs6000/altivec.md (altivec_lvsl, altivec_lvsr): Likewise. Co-Authored-By: Alan Hayward Co-Authored-By: David Sherwood From-SVN: r254297 --- gcc/optabs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc/optabs.c') diff --git a/gcc/optabs.c b/gcc/optabs.c index 6f7848d..7b3d595 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -5785,13 +5785,13 @@ expand_mult_highpart (machine_mode mode, rtx op0, rtx op1, for (i = 0; i < nunits; ++i) RTVEC_ELT (v, i) = GEN_INT (!BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0)); + perm = gen_rtx_CONST_VECTOR (mode, v); } else { - for (i = 0; i < nunits; ++i) - RTVEC_ELT (v, i) = GEN_INT (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); + int base = BYTES_BIG_ENDIAN ? 0 : 1; + perm = gen_const_vec_series (mode, GEN_INT (base), GEN_INT (2)); } - perm = gen_rtx_CONST_VECTOR (mode, v); return expand_vec_perm (mode, m1, m2, perm, target); } -- cgit v1.1