From fb1bf66d61d4ca57367230000babd5ab9c50b6c1 Mon Sep 17 00:00:00 2001 From: Gavin Romig-Koch Date: Tue, 16 Mar 1999 07:25:31 +0000 Subject: iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP, [...]): Use Pmode == DImode rather than TARGET_LONG64. * config/mips/iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP, dtors_section): Use Pmode == DImode rather than TARGET_LONG64. * config/mips/mips.c (override_options): Allow -mlong64 and -mint64 with -mips2 or less. * config/mips/mips.h (MASK_LONG64): Fix comment. (POINTER_SIZE): Use Pmode == DImode rather than TARGET_LONG64. (Pmode): Make Pmode the smaller of longs or gp registers. * invoke.texi: Note the new size for pointers. From-SVN: r25798 --- gcc/invoke.texi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'gcc/invoke.texi') diff --git a/gcc/invoke.texi b/gcc/invoke.texi index e63b499..d05ef37 100644 --- a/gcc/invoke.texi +++ b/gcc/invoke.texi @@ -4766,7 +4766,6 @@ ISA level. @item -mips3 Issue instructions from level 3 of the MIPS ISA (64 bit instructions). @samp{r4000} is the default @var{cpu type} at this ISA level. -This option does not change the sizes of any of the C data types. @item -mips4 Issue instructions from level 4 of the MIPS ISA. @samp{r8000} is the @@ -4789,12 +4788,14 @@ Assume that 32 64-bit general purpose registers are available. This is the default when the @samp{-mips3} option is used. @item -mint64 -Types long, int, and pointer are 64 bits. This works only if @samp{-mips3} -is also specified. +Force int and long types to be 64 bits wide. See @samp{-mlong64} for an +explanation of the width of pointers. @item -mlong64 -Types long and pointer are 64 bits, and type int is 32 bits. -This works only if @samp{-mips3} is also specified. +Force long types to be 64 bits wide. + +The width of pointer types is the smaller of the width of longs +or the width of general purpose registers. @itemx -mabi=32 @itemx -mabi=n32 -- cgit v1.1