From ae78a89f5210015ef21d107ad57d10bcb7ac852c Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Mon, 12 Nov 2018 14:58:39 +0000 Subject: [GCC, ARM] Enable armv8.5-a and add +sb and +predres for previous ARMv8-a in ARM This patch adds -march=armv8.5-a to the Arm backend. Armv8.5-A also adds two new security features: - Speculation Barrier instruction - Execution and Data Prediction Restriction Instructions These are made optional to all older Armv8-A versions. Thus we are adding two new options "+sb" and "+predres" to all older Armv8-A. These are passed on to the assembler and have no code generation effects and have already gone in the trunk of binutils. *** gcc/ChangeLog *** 2018-11-12 Sudakshina Das * config/arm/arm-cpus.in (armv8_5, sb, predres): New features. (ARMv8_5a): New fgroup. (armv8.5-a): New arch. (armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a): New options sb and predres. * config/arm/arm-tables.opt: Regenerate. * config/arm/t-aprofile: Add matching rules for -march=armv8.5-a * config/arm/t-arm-elf (all_v8_archs): Add armv8.5-a. * config/arm/t-multilib (v8_5_a_simd_variants): New variable. Add matching rules for -march=armv8.5-a and extensions. * doc/invoke.texi (ARM options): Document -march=armv8.5-a. Add sb and predres to all armv8-a except armv8.5-a. *** gcc/testsuite/ChangeLog *** 2018-11-12 Sudakshina Das * gcc.target/arm/multilib.exp: Add some -march=armv8.5-a combination tests. From-SVN: r266031 --- gcc/doc/invoke.texi | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'gcc/doc') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e016dce..5eef746 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16500,6 +16500,7 @@ Permissible names are: @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a}, +@samp{armv8.5-a}, @samp{armv7-r}, @samp{armv8-r}, @samp{armv6-m}, @samp{armv6s-m}, @@ -16676,6 +16677,10 @@ The cryptographic instructions. Disable the cryptographic instructions. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. +@item +sb +Speculation Barrier Instruction. +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.1-a @@ -16692,6 +16697,12 @@ Disable the cryptographic instructions. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.2-a @@ -16721,6 +16732,12 @@ Disable the cryptographic extension. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. @end table @item armv8.4-a @@ -16744,6 +16761,35 @@ Disable the cryptographic extension. @item +nofp Disable the floating-point, Advanced SIMD and cryptographic instructions. + +@item +sb +Speculation Barrier Instruction. + +@item +predres +Execution and Data Prediction Restriction Instructions. +@end table + +@item armv8.5-a +@table @samp +@item +fp16 +The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. + +@item +simd +The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the +Dot Product extension. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions as well as the Dot Product extension. + +@item +nocrypto +Disable the cryptographic extension. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. @end table @item armv7-r -- cgit v1.1