From 7c190f93cd53a8391d78da2ba39d98dba9211faa Mon Sep 17 00:00:00 2001 From: Monk Chiang Date: Fri, 2 Feb 2024 11:58:44 +0800 Subject: RISC-V: Support scheduling for sifive p400 series Add sifive p400 series scheduler module. For more information see https://www.sifive.com/cores/performance-p450-470. gcc/ChangeLog: * config/riscv/riscv.md: Include sifive-p400.md. * config/riscv/sifive-p400.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p400. * config/riscv/riscv.cc (sifive_p400_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p400-series --- gcc/doc/invoke.texi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc/doc') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e9c691d..f864582 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30714,8 +30714,8 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, Optimize the output for the given processor, specified by microarchitecture or particular CPU name. Permissible values for this option are: @samp{rocket}, @samp{sifive-3-series}, @samp{sifive-5-series}, @samp{sifive-7-series}, -@samp{thead-c906}, @samp{size}, @samp{sifive-p600-series}, -and all valid options for @option{-mcpu=}. +@samp{thead-c906}, @samp{size}, @samp{sifive-p400-series}, +@samp{sifive-p600-series}, and all valid options for @option{-mcpu=}. When @option{-mtune=} is not specified, use the setting from @option{-mcpu}, the default is @samp{rocket} if both are not specified. -- cgit v1.1