From e9ab41b79933d42410126f0eb7b29f820745276c Mon Sep 17 00:00:00 2001
From: "Hu, Lin1" <lin1.hu@intel.com>
Date: Fri, 1 Nov 2024 10:04:40 +0800
Subject: Support Intel MOVRS

gcc/ChangeLog:

	* builtins.cc (expand_builtin_prefetch): Expand for
	prefetchrst2.
	* common/config/i386/cpuinfo.h (get_available_features): Detect movrs.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_MOVRS_SET): New.
	(OPTION_MASK_ISA2_MOVRS_UNSET): Ditto.
	(ix86_handle_option): Handle -mmovrs.
	* common/config/i386/i386-cpuinfo.h
	(enum processor_features): Add FEATURE_MOVRS.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for movrs.
	* config.gcc: Add movrsintrin.h
	* config/i386/cpuid.h (bit_MOVRS): New.
	* config/i386/i386-builtin-types.def:
	Add DEF_FUNCTION_TYPE (CHAR, PCCHAR), (SHORT, PCSHORT), (INT, PCINT),
	(INT64, PCINT64).
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Add
	__MOVRS__.
	* config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Define
	__MOVRS__.
	* config/i386/i386-isa.def (MOVRS): Add DEF_PTA(MOVRS)
	* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
	Handle movrs.
	* config/i386/i386.md (movrs<mode>): New.
	* config/i386/i386.opt: Add option -mmovrs.
	* config/i386/i386.opt.urls: Regenerated.
	* config/i386/immintrin.h: Include movrsintrin.h
	* config/i386/sse.md (unspecv): Add UNSPEC_VMOVRS.
	(VI1248_AVX10_2): New.
	(avx10_2_movrs_vmovrs<ssemodesuffix><mode><mask_name>): New define_insn.
	* config/i386/xmmintrin.h: Add prefetchrst2.
	* doc/extend.texi: Document movrs.
	* doc/invoke.texi: Document -mmovrs.
	* doc/rtl.texi: Document extension of prefetchrst2.
	* doc/sourcebuild.texi: Document target movrs.
	* config/i386/movrsintrin.h: New.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -mmovrs.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.c-torture/execute/builtin-prefetch-1.c: Expand rws.
	* gcc.dg/builtin-prefetch-1.c: Ditto.
	* gcc.target/i386/avx-1.c: Ditto.
	* gcc.target/i386/avx-2.c: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-12.c: Add -mmovrs.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add movrs.
	* gcc.target/i386/sse-23.c: Ditto
	* gcc.target/i386/avx10_2-512-movrs-1.c: New test.
	* gcc.target/i386/avx10_2-movrs-1.c: Ditto.
	* gcc.target/i386/movrs-1.c: Ditto.

Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
---
 gcc/doc/rtl.texi | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'gcc/doc/rtl.texi')

diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 0cb36aa..5debd62 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -3472,11 +3472,12 @@ position of @var{base}, @var{min} and @var{max} to the containing insn
 and of @var{min} and @var{max} to @var{base}.  See rtl.def for details.
 
 @findex prefetch
-@item (prefetch:@var{m} @var{addr} @var{rw} @var{locality})
+@item (prefetch:@var{m} @var{addr} @var{rws} @var{locality} @var{cache})
 Represents prefetch of memory at address @var{addr}.
-Operand @var{rw} is 1 if the prefetch is for data to be written, 0 otherwise;
-targets that do not support write prefetches should treat this as a normal
-prefetch.
+Operand @var{rws} is 0 if the prefetch is for data to be read, 1 for being
+written; 2 if read shared;
+targets that do not support write or read shared prefetches should treat this
+as a normal prefetch.
 Operand @var{locality} specifies the amount of temporal locality; 0 if there
 is none or 1, 2, or 3 for increasing levels of temporal locality;
 targets that do not support locality hints should ignore this.
-- 
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