From 46d096a3c7a69f3a8c88c88a3dcaa6925d242513 Mon Sep 17 00:00:00 2001 From: Steven Bosscher Date: Wed, 5 Jan 2005 23:19:23 +0000 Subject: combine.c (expand_compound_operation): Add comment that we fall through after case. * combine.c (expand_compound_operation) : Add comment that we fall through after case. (mark_used_regs_combine): Don't expect a SIGN_EXTRACT in a SET_DEST. (distribute_links): Likewise. * cse.c (cse_insn): Likewise. * cselib.c (cselib_invalidate_mem): Likewise. * df.c: Update comments at the top of the file. (read_modify_subreg_p): Update comments here too. (df_def_record_1): Don't expect a SIGN_EXTRACT in a SET_DEST. * flow.c (mark_set_1): Likewise. (mark_used_regs): Likewise. * gcse.c (mems_conflict_for_gcse_p): Likewise. (canon_list_insert): Likewise. (mark_set): Likewise. (try_replace_reg): Likewise. (store_killed_in_insn): Likewise. * loop.c (count_one_set): Likewise. (basic_induction_var): Likewise. * postreload-gcse.c (find_mem_conflicts): Likewise. * postreload.c (reload_combine_note_store): Likewise. (move2add_note_store): Likewise. * reload.c (find_equiv_reg): Likewise. (mark_referenced_resources): Likewise. * rtlanal.c (set_noop_p): Likewise. (note_stores): Likewise. (note_uses): Likewise. * sched-deps.c (sched_analyze_1): Likewise. * sched-rgn.c (check_live_1): Likewise. (update_live_1): Likewise. * config/i860/i860.c: Likewise. * rtl.dec (SIGN_EXTRACT): Document that this cannot appear as an lvalue. (ZERO_EXTRACT): Mention that this one can be an lvalue. * doc/rtl.texi: Update documentation for bit-fields and SET. From-SVN: r92974 --- gcc/doc/rtl.texi | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'gcc/doc/rtl.texi') diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index e82d0c0..6068516 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -2132,9 +2132,6 @@ for insn attributes. @xref{Insn Attributes}. @cindex bit-fields Special expression codes exist to represent bit-field instructions. -These types of expressions are lvalues in RTL; they may appear -on the left side of an assignment, indicating insertion of a value -into the specified bit-field. @table @code @findex sign_extract @@ -2158,11 +2155,18 @@ in the @code{insv} or @code{extv} pattern. The mode @var{m} is the same as the mode that would be used for @var{loc} if it were a register. +A @code{sign_extract} can not appear as an lvalue, or part thereof, +in RTL. + @findex zero_extract @item (zero_extract:@var{m} @var{loc} @var{size} @var{pos}) Like @code{sign_extract} but refers to an unsigned or zero-extended bit-field. The same sequence of bits are extracted, but they are filled to an entire word with zeros instead of by sign-extension. + +Unlike @code{sign_extract}, this type of expressions can be lvalues +in RTL; they may appear on the left side of an assignment, indicating +insertion of a value into the specified bit-field. @end table @node Vector Operations @@ -2365,10 +2369,15 @@ rest of the register receives an undefined value. Likewise, if the mode of the register, the rest of the register can be changed in an undefined way. -If @var{lval} is a @code{strict_low_part} or @code{zero_extract} -of a @code{subreg}, then the part of the register specified by the -machine mode of the @code{subreg} is given the value @var{x} and -the rest of the register is not changed. +If @var{lval} is a @code{strict_low_part} of a subreg, then the part +of the register specified by the machine mode of the @code{subreg} is +given the value @var{x} and the rest of the register is not changed. + +If @var{lval} is a @code{zero_extract}, then the referenced part of +the bit-field (a memory or register reference) specified by the +@code{zero_extract} is given the value @var{x} and the rest of the +bit-field is not changed. Note that @code{sign_extract} can not +appear in @var{lval}. If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may be either a @code{compare} expression or a value that may have any mode. -- cgit v1.1