From c7314bc17b9dde51f1eac83dc399d411f5fdd4a0 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Tue, 9 May 2017 16:19:35 +0200 Subject: [ARC]Fast interrupts support. When a processor enters a fast interrupts handler, and duplicate register banks are configured, the processor saves the user context by saving the registers in the main register bank to these additional registers in the duplicate register bank. In this fast interrupt context, when you specify the rgf_banked_regs option,the compiler does not save the registers duplicated in the additional register bank are not saved. gcc/ 2017-05-09 Claudiu Zissulescu Andrew Burgess * config/arc/arc.c (ARC_AUTOBLINK_IRQ_P): Consider fast interrupts case also. (ARC_AUTOFP_IRQ_P): Likewise. (ARC_AUTO_IRQ_P): Likewise. (rgf_banked_register_count): New variable. (parse_mrgf_banked_regs_option): New function. (arc_override_options): Handle rgf_banked_regs option. (arc_handle_interrupt_attribute): Add firq option. (arc_compute_function_type): Return fast irq type when required. (arc_must_save_register): Handle fast interrupts. (arc_expand_prologue): Do not emit dwarf info for fast interrupts. (arc_return_address_regs): Update. * config/arc/arc.h (arc_return_address_regs): Update. (arc_function_type): Add fast interrupt type. (ARC_INTERRUPT_P): Update. (RC_FAST_INTERRUPT_P): Define. * config/arc/arc.md (simple_return): Update for fast interrupts. (p_return_i): Likewise. * config/arc/arc.opt (mrgf-banked-regs): New option. * doc/invoke.texi (mrgf-banked-regs): Document. testsuite/ 2017-05-09 Claudiu Zissulescu Andrew Burgess * gcc.target/arc/firq-1.c: New file. * gcc.target/arc/firq-2.c: Likewise. * gcc.target/arc/firq-3.c: Likewise. * gcc.target/arc/firq-4.c: Likewise. * gcc.target/arc/firq-5.c: Likewise. * gcc.target/arc/firq-6.c: Likewise. Co-Authored-By: Andrew Burgess From-SVN: r247796 --- gcc/doc/invoke.texi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'gcc/doc/invoke.texi') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6f82e24..5360255 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -607,6 +607,7 @@ Objective-C and Objective-C++ Dialects}. -mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape @gol -mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof @gol -mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved @gol +-mrgf-banked-regs @gol -mvolatile-cache -mtp-regno=@var{regno} @gol -malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol -mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol @@ -14556,6 +14557,15 @@ always starts with @code{r0}, the upper limit is @code{fp} register. @var{blink} and @var{lp_count} are optional. This option is only valid for ARC EM and ARC HS cores. +@item -mrgf-banked-regs=@var{number} +@opindex mrgf-banked-regs +Specifies the number of registers replicated in second register bank +on entry to fast interrupt. Fast interrupts are interrupts with the +highest priority level P0. These interrupts save only PC and STATUS32 +registers to avoid memory transactions during interrupt entry and exit +sequences. Use this option when you are using fast interrupts in an +ARC V2 family processor. Permitted values are 4, 8, 16, and 32. + @end table The following options are passed through to the assembler, and also -- cgit v1.1