From 9eeca7753670d7bccd82e6ed7e4fe97cabd9a362 Mon Sep 17 00:00:00 2001 From: Mary Bennett Date: Mon, 18 Mar 2024 21:32:56 -0600 Subject: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Create XCVbi extension support. * config/riscv/riscv.opt: Likewise. * config/riscv/corev.md: Implement cv_branch pattern for cv.beqimm and cv.bneimm. * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V branch instruction pattern. * config/riscv/constraints.md: Implement constraints cv_bi_s5 - signed 5-bit immediate. * config/riscv/predicates.md: Implement predicate const_int5s_operand - signed 5 bit immediate. * doc/sourcebuild.texi: Add XCVbi documentation. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test. * lib/target-supports.exp: Add proc for XCVbi. --- gcc/config/riscv/constraints.md | 6 ++++++ gcc/config/riscv/corev.md | 37 +++++++++++++++++++++++++++++++++++++ gcc/config/riscv/predicates.md | 4 ++++ gcc/config/riscv/riscv.md | 2 +- gcc/config/riscv/riscv.opt | 2 ++ 5 files changed, 50 insertions(+), 1 deletion(-) (limited to 'gcc/config') diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 41acaea..972e884 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -268,6 +268,12 @@ (and (match_test "IN_RANGE (ival, 0, 1073741823)") (match_test "exact_log2 (ival + 1) != -1")))) +(define_constraint "CV_bi_sign5" + "@internal + A 5-bit signed immediate for CORE-V Immediate Branch." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -16, 15)"))) + (define_constraint "CV_simd_si6" "A 6-bit signed immediate for SIMD." (and (match_code "const_int") diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index 3857c53..e2db8f3 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -2614,3 +2614,40 @@ cv.subrotmj.div8\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) + +;; XCVBI Instructions +(define_insn "*cv_branch" + [(set (pc) + (if_then_else + (match_operator 1 "equality_operator" + [(match_operand:X 2 "register_operand" "r") + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")]) + (label_ref (match_operand 0 "" "")) + (pc)))] + "TARGET_XCVBI" +{ + if (get_attr_length (insn) == 12) + return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:"; + + return "cv.b%C1imm\t%2,%3,%0"; +} + [(set_attr "type" "branch") + (set_attr "mode" "none")]) + +(define_insn "*branch" + [(set (pc) + (if_then_else + (match_operator 1 "ordered_comparison_operator" + [(match_operand:X 2 "register_operand" "r") + (match_operand:X 3 "reg_or_0_operand" "rJ")]) + (label_ref (match_operand 0 "" "")) + (pc)))] + "TARGET_XCVBI" +{ + if (get_attr_length (insn) == 12) + return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:"; + + return "b%C1\t%2,%z3,%l0"; +} + [(set_attr "type" "branch") + (set_attr "mode" "none")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 6c87a7b..539e0f7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -445,6 +445,10 @@ (ior (match_operand 0 "const_int6_operand") (match_operand 0 "register_operand"))) +(define_predicate "const_int5s_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -16, 15)"))) + ;; Predicates for the V extension. (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f433b038..0346cc3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2756,7 +2756,7 @@ (match_operand:X 3 "reg_or_0_operand" "rJ")]) (label_ref (match_operand 0 "" "")) (pc)))] - "" + "!TARGET_XCVBI" { if (get_attr_length (insn) == 12) return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:"; diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 45a9517..710c0a4 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -430,6 +430,8 @@ Mask(ZCMP) Var(riscv_zc_subext) Mask(ZCMT) Var(riscv_zc_subext) +Mask(XCVBI) Var(riscv_xcv_subext) + TargetVariable int riscv_sv_subext -- cgit v1.1