From 8f921393e339090566c1589d81009caa954de90d Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Fri, 24 Dec 2021 17:09:36 +0100 Subject: i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use V4SFmode "DIVPS X,Y" with [y0, y1, 1.0f, 1.0f] as a divisor to avoid division by zero. 2021-12-24 Uroš Bizjak gcc/ChangeLog: PR target/95046 PR target/103797 * config/i386/mmx.md (divv2sf3): New instruction pattern. gcc/testsuite/ChangeLog: PR target/95046 PR target/103797 * gcc.target/i386/pr95046-1.c (test_div): Add. (dg-options): Add -mno-recip. --- gcc/config/i386/mmx.md | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'gcc/config') diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 6c5cbcf..5a57556 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -523,6 +523,26 @@ (set_attr "prefix" "*,orig,vex") (set_attr "mode" "V2SF,V4SF,V4SF")]) +(define_expand "divv2sf3" + [(set (match_operand:V2SF 0 "register_operand") + (div:V2SF (match_operand:V2SF 1 "register_operand") + (match_operand:V2SF 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" +{ + rtx op0 = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V4SFmode, operands[1], + GET_MODE (operands[1])); + rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], + force_reg (V2SFmode, CONST1_RTX (V2SFmode))); + rtx tmp = gen_reg_rtx (V4SFmode); + + emit_insn (gen_rtx_SET (tmp, op2)); + + emit_insn (gen_divv4sf3 (op0, op1, tmp)); + DONE; +}) + (define_expand "mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand") (smaxmin:V2SF -- cgit v1.1