From 2e886eef7f2b5aadb00171af868f0895b647c3a4 Mon Sep 17 00:00:00 2001 From: Raphael Moreira Zinsly Date: Tue, 27 Dec 2022 18:29:25 -0500 Subject: RISC-V: Produce better code with complex constants [PR95632] [PR106602] gcc/Changelog: PR target/95632 PR target/106602 * config/riscv/riscv.md: New pattern to simulate complex const_int loads. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr95632.c: New test. * gcc.target/riscv/pr106602.c: New test. --- gcc/config/riscv/riscv.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'gcc/config') diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a8bb331..020833b 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1670,6 +1670,23 @@ MAX_MACHINE_MODE, &operands[3], TRUE); }) +;; Pretend to have the ability to load complex const_int in order to get +;; better code generation around them. +;; +;; But avoid constants that are special cased elsewhere. +(define_insn_and_split "*mvconst_internal" + [(set (match_operand:GPR 0 "register_operand" "=r") + (match_operand:GPR 1 "splittable_const_int_operand" "i"))] + "!(p2m1_shift_operand (operands[1]) || high_mask_shift_operand (operands[1]))" + "#" + "&& 1" + [(const_int 0)] +{ + riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]), + mode, TRUE); + DONE; +}) + ;; 64-bit integer moves (define_expand "movdi" -- cgit v1.1