From 24a7980d0f48671ea13da18c9162a43420b5af58 Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Fri, 23 Dec 2022 09:50:18 +0000 Subject: PR target/106933: Limit TImode STV to SSA-like def-use chains on x86. With many thanks to H.J. for doing all the hard work, this patch resolves two P1 regressions; PR target/106933 and PR target/106959. Although superficially similar, the i386 backend's two scalar-to-vector (STV) passes perform their transformations in importantly different ways. The original pass converting SImode and DImode operations to V4SImode or V2DImode operations is "soft", allowing values to be maintained in both integer and vector hard registers. The newer pass converting TImode operations to V1TImode is "hard" (all or nothing) that converts all uses of a pseudo to vector form. To implement this it invokes powerful ju-ju calling SET_MODE on a reg_rtx, which due to RTL sharing, often updates this pseudo's mode everywhere in the RTL chain. Hence, TImode STV can only be performed when all uses of a pseudo are convertible to V1TImode form. To ensure this the STV passes currently use data-flow analysis to inspect all DEFs and USEs in a chain. This works fine for chains that are in the usual single assignment form, but the occurrence of uninitialized variables, or multiple assignments that split a pseudo's usage into several independent chains (lifetimes) can lead to situations where some but not all of a pseudo's occurrences need to be updated. This is safe for the SImode/DImode pass, but leads to the above bugs during the TImode pass. My one minor tweak to HJ's patch from comment #4 of bugzilla PR106959 is to only perform the new single_def_chain_p check for TImode STV; it turns out that STV of SImode/DImode min/max operates safely on multiple-def chains, and prohibiting this leads to testsuite regressions. We don't (yet) support V1TImode min/max, so this idiom isn't an issue during the TImode STV pass. For the record, the two alternate possible fixes are (i) make the TImode STV pass "soft", by eliminating use of SET_MODE, instead using replace_rtx with a new pseudo, or (ii) merging "chains" so that multiple DFA chains/lifetimes are considered a single STV chain. 2022-12-23 H.J. Lu Roger Sayle gcc/ChangeLog PR target/106933 PR target/106959 * config/i386/i386-features.cc (single_def_chain_p): New predicate function to check that a pseudo's use-def chain is in SSA form. (timode_scalar_to_vector_candidate_p): Check that TImode regs that are SET_DEST or SET_SRC of an insn match/are single_def_chain_p. gcc/testsuite/ChangeLog PR target/106933 PR target/106959 * gcc.target/i386/pr106933-1.c: New test case. * gcc.target/i386/pr106933-2.c: Likewise. * gcc.target/i386/pr106959-1.c: Likewise. * gcc.target/i386/pr106959-2.c: Likewise. * gcc.target/i386/pr106959-3.c: Likewise. --- gcc/config/i386/i386-features.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'gcc/config') diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index fd212262..4bf8bb3 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -1756,6 +1756,19 @@ pseudo_reg_set (rtx_insn *insn) return set; } +/* Return true if the register REG is defined in a single DEF chain. + If it is defined in more than one DEF chains, we may not be able + to convert it in all chains. */ + +static bool +single_def_chain_p (rtx reg) +{ + df_ref ref = DF_REG_DEF_CHAIN (REGNO (reg)); + if (!ref) + return false; + return DF_REF_NEXT_REG (ref) == nullptr; +} + /* Check if comparison INSN may be transformed into vector comparison. Currently we transform equality/inequality checks which look like: (set (reg:CCZ 17 flags) (compare:CCZ (reg:TI x) (reg:TI y))) */ @@ -1972,9 +1985,14 @@ timode_scalar_to_vector_candidate_p (rtx_insn *insn) && !TARGET_SSE_UNALIGNED_STORE_OPTIMAL) return false; + if (REG_P (dst) && !single_def_chain_p (dst)) + return false; + switch (GET_CODE (src)) { case REG: + return single_def_chain_p (src); + case CONST_WIDE_INT: return true; -- cgit v1.1