From f83e76c3f998c8708fe2ddca16ae3f317c39c37a Mon Sep 17 00:00:00 2001 From: Takayuki 'January June' Suwa Date: Sat, 18 Feb 2023 13:43:34 +0900 Subject: xtensa: Eliminate unnecessary general-purpose reg-reg moves Register-register move instructions that can be easily seen as unnecessary by the human eye may remain in the compiled result. For example: /* example */ double test(double a, double b) { return __builtin_copysign(a, b); } test: add.n a3, a3, a3 extui a5, a5, 31, 1 ssai 1 ;; Be in the same BB src a7, a5, a3 ;; Replacing the destination doesn't ;; violate any constraints of the ;; operands ;; No CALL insns in this span ;; Both A3 and A7 are irrelevant to ;; insns in this span mov.n a3, a7 ;; An unnecessary reg-reg move ;; A7 is not used after this ret.n The last two instructions above, excluding the return instruction, could be done like this: src a3, a5, a3 This symptom often occurs when handling DI/DFmode values with SImode instructions. This patch solves the above problem using peephole2 pattern. gcc/ChangeLog: * config/xtensa/xtensa.md: New peephole2 pattern that eliminates the occurrence of general-purpose register used only once and for transferring intermediate value. gcc/testsuite/ChangeLog: * gcc.target/xtensa/elim_GP_regmove_0.c: New test. * gcc.target/xtensa/elim_GP_regmove_1.c: New test. --- gcc/config/xtensa/xtensa.md | 46 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'gcc/config/xtensa') diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index d6116d6..cf25beb 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -3050,3 +3050,49 @@ FALLTHRU:; operands[1] = GEN_INT (imm0); operands[2] = GEN_INT (imm1); }) + +(define_peephole2 + [(set (match_operand 0 "register_operand") + (match_operand 1 "register_operand"))] + "REG_NREGS (operands[0]) == 1 && GP_REG_P (REGNO (operands[0])) + && REG_NREGS (operands[1]) == 1 && GP_REG_P (REGNO (operands[1])) + && peep2_reg_dead_p (1, operands[1])" + [(const_int 0)] +{ + basic_block bb = BLOCK_FOR_INSN (curr_insn); + rtx_insn *head = BB_HEAD (bb), *insn; + rtx dest = operands[0], src = operands[1], pattern, t_dest, dest_orig; + for (insn = PREV_INSN (curr_insn); + insn && insn != head; + insn = PREV_INSN (insn)) + if (CALL_P (insn)) + break; + else if (INSN_P (insn)) + { + if (GET_CODE (pattern = PATTERN (insn)) == SET + && REG_P (t_dest = SET_DEST (pattern)) + && REG_NREGS (t_dest) == 1 + && REGNO (t_dest) == REGNO (src)) + { + dest_orig = SET_DEST (pattern); + SET_DEST (pattern) = gen_rtx_REG (GET_MODE (t_dest), + REGNO (dest)); + extract_insn (insn); + if (!constrain_operands (true, get_enabled_alternatives (insn))) + { + SET_DEST (pattern) = dest_orig; + goto ABORT; + } + df_insn_rescan (insn); + goto FALLTHRU; + } + if (reg_overlap_mentioned_p (dest, pattern) + || reg_overlap_mentioned_p (src, pattern) + || set_of (dest, insn) + || set_of (src, insn)) + break; + } +ABORT: + FAIL; +FALLTHRU:; +}) -- cgit v1.1