From 1352d4dd09293faf170072269fcef3aa6694d6ae Mon Sep 17 00:00:00 2001 From: yulong <shiyulong@iscas.ac.cn> Date: Mon, 2 Dec 2024 09:31:53 +0800 Subject: RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. This commit adds intrinsics support for XXsfvfnrclipxfqf. We also redefine the enum type frm_op_type in riscv-vector-builtins-bases.h file, because it be used in sifive-vector-builtins-bases.cc file. Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn> gcc/ChangeLog: * config/riscv/generic-vector-ooo.md: New reservation. * config/riscv/genrvv-type-indexer.cc (main): New type. * config/riscv/riscv-vector-builtins-bases.cc (enum frm_op_type): Delete it. * config/riscv/riscv-vector-builtins-bases.h (enum frm_op_type): Redefine in h file. * config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vfnrclip_def): New function. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE_INDEX): New builtins def. * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX): New base def. (signed_eew8_index): Ditto. * config/riscv/riscv-vector-builtins.h (enum required_ext): New extension. (required_ext_to_isa_name): Ditto. (required_extensions_specified): Ditto. (struct function_group_info): Ditto. * config/riscv/riscv.md: New attr. * config/riscv/sifive-vector-builtins-bases.cc (class sf_vfnrclip_x_f_qf): New function. (class sf_vfnrclip_xu_f_qf): Ditto. (BASE): New base_name. * config/riscv/sifive-vector-builtins-bases.h: New function_base. * config/riscv/sifive-vector-builtins-functions.def (REQUIRED_EXTENSIONS): New intrinsics def. (sf_vfnrclip_x_f_qf): Ditto. (sf_vfnrclip_xu_f_qf): Ditto. * config/riscv/sifive-vector.md (@pred_sf_vfnrclip<v_su><mode>_x_f_qf): New RTL mode. * config/riscv/vector-iterators.md: New iterator. --- gcc/config/riscv/riscv-vector-builtins-bases.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.h') diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index af1cb1a..c337cba 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -23,6 +23,12 @@ namespace riscv_vector { +enum frm_op_type +{ + NO_FRM, + HAS_FRM, +}; + namespace bases { extern const function_base *const vsetvl; extern const function_base *const vsetvlmax; -- cgit v1.1