From 146456c108b2c395c524f14d08b3c5d3af65e971 Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Tue, 28 Sep 2010 18:01:54 -0400 Subject: re PR target/45800 ([M32C] compile error on increment volatile long var) PR target/45800 * config/m32c/m32c.c (m32c_subreg): Force adjustment of subregs of volatile MEMs. From-SVN: r164705 --- gcc/config/m32c/m32c.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'gcc/config/m32c/m32c.c') diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 066d1a8..d62b4f2 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -3317,7 +3317,19 @@ m32c_subreg (enum machine_mode outer, return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0)); if (GET_CODE (x) != REG) - return simplify_gen_subreg (outer, x, inner, byte); + { + rtx r = simplify_gen_subreg (outer, x, inner, byte); + if (GET_CODE (r) == SUBREG + && GET_CODE (x) == MEM + && MEM_VOLATILE_P (x)) + { + /* Volatile MEMs don't get simplified, but we need them to + be. We are little endian, so the subreg byte is the + offset. */ + r = adjust_address (x, outer, byte); + } + return r; + } r = REGNO (x); if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO) -- cgit v1.1