From 13ef00fa08169669d0d995c80962f1fb43138f0f Mon Sep 17 00:00:00 2001
From: Jan Hubicka <jh@suse.cz>
Date: Thu, 10 Oct 2013 19:52:40 +0200
Subject: x86-tune.def: Enable X86_TUNE_SSE_TYPELESS_STORES for generic...

	* config/i386/x86-tune.def: Enable X86_TUNE_SSE_TYPELESS_STORES
	for generic, enable X86_TUNE_SSE_LOAD0_BY_PXOR for Bulldozer,
	Bobcat and generic.

	* gcc.target/i386/avx256-unaligned-store-3.c: Update template for
	tuning change.
	* gcc.target/i386/avx256-unaligned-store-1.c: Likewise.
	* gcc.target/i386/pr49168-1.c: Likewise.
	* gcc.target/i386/pr49002-2.c: Likewise.

From-SVN: r203387
---
 gcc/config/i386/x86-tune.def | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'gcc/config/i386/x86-tune.def')

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 6b0a593..34484a2 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -221,16 +221,14 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim
    upper part undefined.  */
 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
 
-/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. 
-   FIXME: Shall we enable it for generic?  */
+/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
-	  m_AMD_MULTIPLE | m_CORE_ALL)
+	  m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
 
 /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
-   xorps/xorpd and other variants.
-   FIXME: Shall we enable it buldozers and for generic?  */
+   xorps/xorpd and other variants.  */
 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
-	  m_PPRO | m_P4_NOCONA | m_CORE_ALL)
+	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_GENERIC)
 
 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
    full sized loads.  */
-- 
cgit v1.1

