From cd1e2f632532d04c67a17820cb25826f8b0febac Mon Sep 17 00:00:00 2001 From: Marcus Comstedt Date: Fri, 19 Mar 2021 20:49:04 +0100 Subject: RISC-V: Add riscv{32,64}be with big endian as default gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default endianness. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro. --- gcc/common/config/riscv/riscv-common.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 6bbe25d..34b74e5 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -32,6 +32,11 @@ along with GCC; see the file COPYING3. If not see #include "config/riscv/riscv-protos.h" #include "config/riscv/riscv-subset.h" +#ifdef TARGET_BIG_ENDIAN_DEFAULT +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) +#endif + /* Type for implied ISA info. */ struct riscv_implied_info_t { -- cgit v1.1 From 4f00c4d40a539360938607561460904663c64cda Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Wed, 24 Mar 2021 15:58:03 +0100 Subject: i386: fix -march=amd crash It started with g:3e2ae3ee285a57455d5a23bd352a68c289130186 where new entry was added to processor_alias_table after generic node: + {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0, + M_CPU_TYPE (AMDFAM19H), P_NONE}, and then the following is violated: /* NB: processor_alias_table stops at the "generic" entry. */ gcc/ChangeLog: PR target/99753 * common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one error. * config/i386/i386-options.c (ix86_option_override_internal): Add run-time assert. gcc/testsuite/ChangeLog: PR target/99753 * gcc.target/i386/pr99753.c: New test. --- gcc/common/config/i386/i386-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index eea8af1..b89183b 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -2051,7 +2051,7 @@ const pta processor_alias_table[] = }; /* NB: processor_alias_table stops at the "generic" entry. */ -unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 6; +unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7; unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table); /* Provide valid option values for -march and -mtune options. */ -- cgit v1.1 From f2be08339b77d3495e210d6b5d9cea927f437720 Mon Sep 17 00:00:00 2001 From: "Cui,Lili" Date: Mon, 12 Apr 2021 09:59:25 +0800 Subject: Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Alder Lake Intel Hybrid Technology will not support Intel® AVX-512. ISA features such as Intel® AVX, AVX-VNNI, Intel® AVX2, and UMONITOR/UMWAIT/TPAUSE are supported. gcc/ChangeLog * config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list. * config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE. * common/config/i386/cpuinfo.h (get_intel_cpu): Add AlderLake model. * doc/invoke.texi: Change alderlake ISA list. --- gcc/common/config/i386/cpuinfo.h | 1 + 1 file changed, 1 insertion(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index dbce022..c1ee7a1 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -476,6 +476,7 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE; break; case 0x97: + case 0x9a: /* Alder Lake. */ cpu = "alderlake"; CHECK___builtin_cpu_is ("corei7"); -- cgit v1.1 From c02c39fad02c386f6e687e28282973f580fc95ac Mon Sep 17 00:00:00 2001 From: "Cui,Lili" Date: Mon, 12 Apr 2021 09:59:25 +0800 Subject: Add rocketlake to gcc. gcc/ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle rocketlake. * common/config/i386/i386-common.c (processor_names): Add rocketlake. (processor_alias_table): Add rocketlake. * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ROCKETLAKE. * config.gcc: Add -march=rocketlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle rocketlake. * config/i386/i386-options.c (m_ROCKETLAKE) : Define. (processor_cost_table): Add rocketlake cost. * config/i386/i386.h (ix86_size_cost) : Define TARGET_ROCKETLAKE. (processor_type) : Add PROCESSOR_ROCKETLAKE. (PTA_ROCKETLAKE): Ditto. * doc/extend.texi: Add rocketlake. * doc/invoke.texi: Add rocketlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march --- gcc/common/config/i386/cpuinfo.h | 10 ++++++++-- gcc/common/config/i386/i386-common.c | 4 ++++ gcc/common/config/i386/i386-cpuinfo.h | 1 + 3 files changed, 13 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index c1ee7a1..458f41d 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -404,14 +404,20 @@ get_intel_cpu (struct __processor_model *cpu_model, case 0xa5: case 0xa6: /* Comet Lake. */ - case 0xa7: - /* Rocket Lake. */ cpu = "skylake"; CHECK___builtin_cpu_is ("corei7"); CHECK___builtin_cpu_is ("skylake"); cpu_model->__cpu_type = INTEL_COREI7; cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE; break; + case 0xa7: + /* Rocket Lake. */ + cpu = "rocketlake"; + CHECK___builtin_cpu_is ("corei7"); + CHECK___builtin_cpu_is ("rocketlake"); + cpu_model->__cpu_type = INTEL_COREI7; + cpu_model->__cpu_subtype = INTEL_COREI7_ROCKETLAKE; + break; case 0x55: CHECK___builtin_cpu_is ("corei7"); cpu_model->__cpu_type = INTEL_COREI7; diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index b89183b..1e6c159 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -1743,6 +1743,7 @@ const char *const processor_names[] = "skylake-avx512", "cannonlake", "icelake-client", + "rocketlake", "icelake-server", "cascadelake", "tigerlake", @@ -1845,6 +1846,9 @@ const pta processor_alias_table[] = {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL, PTA_ICELAKE_CLIENT, M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F}, + {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL, + PTA_ROCKETLAKE, + M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F}, {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, PTA_ICELAKE_SERVER, M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F}, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 869115c..e68dd65 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -88,6 +88,7 @@ enum processor_subtypes INTEL_COREI7_SAPPHIRERAPIDS, INTEL_COREI7_ALDERLAKE, AMDFAM19H_ZNVER3, + INTEL_COREI7_ROCKETLAKE, CPU_SUBTYPE_MAX }; -- cgit v1.1 From d8c6cc2ca35489bc41bb58ec96c1195928826922 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 15 Apr 2021 11:19:32 -0700 Subject: x86: Add -mmwait for -mgeneral-regs-only Add -mmwait so that the MWAIT and MONITOR intrinsics can be used with -mgeneral-regs-only and make -msse3 to imply -mmwait. gcc/ * config.gcc: Install mwaitintrin.h for i[34567]86-*-* and x86_64-*-* targets. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_MWAIT_SET): New. (OPTION_MASK_ISA2_MWAIT_UNSET): Likewise. (ix86_handle_option): Handle -mmwait. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Replace OPTION_MASK_ISA_SSE3 with OPTION_MASK_ISA2_MWAIT on __builtin_ia32_monitor and __builtin_ia32_mwait. * config/i386/i386-options.c (isa2_opts): Add -mmwait. (ix86_valid_target_attribute_inner_p): Likewise. (ix86_option_override_internal): Enable mwait/monitor instructions for -msse3. * config/i386/i386.h (TARGET_MWAIT): New. (TARGET_MWAIT_P): Likewise. * config/i386/i386.opt: Add -mmwait. * config/i386/mwaitintrin.h: New file. * config/i386/pmmintrin.h: Include . * config/i386/sse.md (sse3_mwait): Replace TARGET_SSE3 with TARGET_MWAIT. (@sse3_monitor_): Likewise. * config/i386/x86gprintrin.h: Include . * doc/extend.texi: Document mwait target attribute. * doc/invoke.texi: Document -mmwait. gcc/testsuite/ * gcc.target/i386/monitor-2.c: New test. --- gcc/common/config/i386/i386-common.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 1e6c159..af3f387 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -150,6 +150,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_F16C_SET \ (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID @@ -245,6 +246,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID @@ -1546,6 +1548,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mmwait: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET; + } + return true; + case OPT_mclzero: if (value) { -- cgit v1.1 From 2cde2d620fc5ff60264ee825fd6eea457d7c51d9 Mon Sep 17 00:00:00 2001 From: "Cui,Lili" Date: Sat, 24 Apr 2021 11:52:17 +0800 Subject: Synchronize Rocket Lake's processor_names and processor_cost_table with processor_type gcc/ChangeLog * common/config/i386/i386-common.c (processor_names): Sync processor_names with processor_type. * config/i386/i386-options.c (processor_cost_table): Sync processor_cost_table with processor_type. --- gcc/common/config/i386/i386-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index af3f387..e156cc3 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -1758,13 +1758,13 @@ const char *const processor_names[] = "skylake-avx512", "cannonlake", "icelake-client", - "rocketlake", "icelake-server", "cascadelake", "tigerlake", "cooperlake", "sapphirerapids", "alderlake", + "rocketlake", "intel", "geode", "k6", -- cgit v1.1 From 89c94716241e2ba9cb42f512103528d0df6b0f3f Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Mon, 10 May 2021 09:03:41 +0300 Subject: arc: Fix compilation warnings. gcc/ 2021-05-10 Claudiu Zissulescu * common/config/arc/arc-common.c (arc_handle_option): Remove dot from string. * config/arc/arc.c (arc_reorg): Remove underscore from string. Signed-off-by: Claudiu Zissulescu --- gcc/common/config/arc/arc-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index d5229ae..86674dd 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -84,7 +84,7 @@ arc_handle_option (struct gcc_options *opts, our caller, so comparing arc_cpu with PROCESSOR_NONE is pointless. */ if (mcpu_seen != PROCESSOR_NONE && mcpu_seen != value) - warning_at (loc, 0, "multiple %<-mcpu=%> options specified."); + warning_at (loc, 0, "multiple %<-mcpu=%> options specified"); mcpu_seen = value; break; -- cgit v1.1 From c0129e2d489cc0ab419c58c4f8451898c2b5e3ae Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 19 Mar 2021 10:21:35 +0100 Subject: Use startswith in targets. gcc/ChangeLog: * common/config/aarch64/aarch64-common.c (aarch64_parse_extension): Use startswith function instead of strncmp. * common/config/bfin/bfin-common.c (bfin_handle_option): Likewise. * common/config/riscv/riscv-common.c (riscv_subset_list::parse): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_type): Likewise. * config/aarch64/aarch64.c (aarch64_process_one_target_attr): Likewise. * config/alpha/alpha.c (alpha_elf_section_type_flags): Likewise. * config/arm/aarch-common.c (arm_md_asm_adjust): Likewise. * config/arm/arm.c (arm_file_start): Likewise. (arm_valid_target_attribute_rec): Likewise. (thumb1_md_asm_adjust): Likewise. * config/arm/driver-arm.c (host_detect_local_cpu): Likewise. * config/avr/avr.c (STR_PREFIX_P): Likewise. (avr_set_current_function): Likewise. (avr_handle_addr_attribute): Likewise. (avr_asm_output_aligned_decl_common): Likewise. (avr_asm_named_section): Likewise. (avr_section_type_flags): Likewise. (avr_asm_select_section): Likewise. * config/c6x/c6x.c (c6x_in_small_data_p): Likewise. (c6x_section_type_flags): Likewise. * config/darwin-c.c (darwin_cfstring_ref_p): Likewise. (darwin_objc_declare_unresolved_class_reference): Likewise. (darwin_objc_declare_class_definition): Likewise. * config/darwin.c (indirect_data): Likewise. (darwin_encode_section_info): Likewise. (darwin_objc2_section): Likewise. (darwin_objc1_section): Likewise. (machopic_select_section): Likewise. (darwin_globalize_label): Likewise. (darwin_label_is_anonymous_local_objc_name): Likewise. (darwin_asm_named_section): Likewise. (darwin_asm_output_dwarf_offset): Likewise. * config/frv/frv.c (frv_string_begins_with): Likewise. (frv_in_small_data_p): Likewise. * config/gcn/mkoffload.c (STR): Likewise. (main): Likewise. * config/i386/i386-builtins.c (get_builtin_code_for_version): Likewise. * config/i386/i386-options.c (ix86_option_override_internal): Likewise. * config/i386/i386.c (x86_64_elf_section_type_flags): Likewise. (ix86_md_asm_adjust): Likewise. * config/i386/intelmic-mkoffload.c (STR): Likewise. * config/i386/winnt.c (i386_pe_asm_named_section): Likewise. (i386_pe_file_end): Likewise. * config/ia64/ia64.c (ia64_in_small_data_p): Likewise. (ia64_section_type_flags): Likewise. * config/mips/driver-native.c (host_detect_local_cpu): Likewise. * config/mips/mips.c (mips_handle_interrupt_attr): Likewise. (mips16_stub_function_p): Likewise. (mips_function_rodata_section): Likewise. * config/msp430/msp430.c (msp430_mcu_name): Likewise. (msp430_function_section): Likewise. (msp430_section_type_flags): Likewise. (msp430_expand_helper): Likewise. * config/nios2/nios2.c (nios2_small_section_name_p): Likewise. (nios2_valid_target_attribute_rec): Likewise. * config/nvptx/mkoffload.c (process): Likewise. (STR): Likewise. * config/pa/som.h: Likewise. * config/pdp11/pdp11.c (pdp11_output_ident): Likewise. * config/riscv/riscv.c (riscv_elf_select_rtx_section): Likewise. * config/rs6000/rs6000.c (VTABLE_NAME_P): Likewise. (rs6000_inner_target_options): Likewise. * config/s390/driver-native.c (s390_host_detect_local_cpu): Likewise. * config/sparc/driver-sparc.c (host_detect_local_cpu): Likewise. * config/vax/vax.c (vax_output_int_move): Likewise. * config/vms/vms-ld.c (startswith): Likewise. (process_args): Likewise. (main): Likewise. * config/vms/vms.c: Likewise. --- gcc/common/config/aarch64/aarch64-common.c | 2 +- gcc/common/config/bfin/bfin-common.c | 2 +- gcc/common/config/riscv/riscv-common.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c index 6763191..6d200a1 100644 --- a/gcc/common/config/aarch64/aarch64-common.c +++ b/gcc/common/config/aarch64/aarch64-common.c @@ -219,7 +219,7 @@ aarch64_parse_extension (const char *str, uint64_t *isa_flags, else len = strlen (str); - if (len >= 2 && strncmp (str, "no", 2) == 0) + if (len >= 2 && startswith (str, "no")) { adding_ext = 0; len -= 2; diff --git a/gcc/common/config/bfin/bfin-common.c b/gcc/common/config/bfin/bfin-common.c index 48a6fe8..a3ee4b5 100644 --- a/gcc/common/config/bfin/bfin-common.c +++ b/gcc/common/config/bfin/bfin-common.c @@ -313,7 +313,7 @@ bfin_handle_option (struct gcc_options *opts, i = 0; while ((p = bfin_cpus[i].name) != NULL) { - if (strncmp (arg, p, strlen (p)) == 0) + if (startswith (arg, p)) break; i++; } diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 34b74e5..d17bea6 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -804,12 +804,12 @@ riscv_subset_list::parse (const char *arch, location_t loc) riscv_subset_list *subset_list = new riscv_subset_list (arch, loc); riscv_subset_t *itr; const char *p = arch; - if (strncmp (p, "rv32", 4) == 0) + if (startswith (p, "rv32")) { subset_list->m_xlen = 32; p += 4; } - else if (strncmp (p, "rv64", 4) == 0) + else if (startswith (p, "rv64")) { subset_list->m_xlen = 64; p += 4; -- cgit v1.1 From 1e6648076498a4644aabbfe3ec74b3b2a5b67772 Mon Sep 17 00:00:00 2001 From: Geng Qi Date: Tue, 18 May 2021 11:16:14 +0800 Subject: RISC-V: Properly parse the letter 'p' in '-march'. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_subset_list::parsing_subset_version): Properly parse the letter 'p' in '-march'. (riscv_subset_list::parse_std_ext, riscv_subset_list::parse_multiletter_ext): To handle errors generated in riscv_subset_list::parsing_subset_version. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-12.c: New. * gcc.target/riscv/attribute-19.c: New. --- gcc/common/config/riscv/riscv-common.c | 68 +++++++++++++++++----------------- 1 file changed, 35 insertions(+), 33 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index d17bea6..10868fd4 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -518,40 +518,39 @@ riscv_subset_list::parsing_subset_version (const char *ext, unsigned version = 0; unsigned major = 0; unsigned minor = 0; - char np; *explicit_version_p = false; - for (; *p; ++p) - { - if (*p == 'p') - { - np = *(p + 1); - - if (!ISDIGIT (np)) - { - /* Might be beginning of `p` extension. */ - if (std_ext_p) - { - get_default_version (ext, major_version, minor_version); - return p; - } - else - { - error_at (m_loc, "%<-march=%s%>: Expect number " - "after %<%dp%>.", m_arch, version); - return NULL; - } - } - - major = version; - major_p = false; - version = 0; - } - else if (ISDIGIT (*p)) - version = (version * 10) + (*p - '0'); - else - break; - } + /* If we got `p`, that means we are still parsing standard extension. */ + gcc_assert (std_ext_p || *p != 'p'); + + if (*p != 'p') { + for (; *p; ++p) + { + if (*p == 'p') + { + if (!ISDIGIT (*(p+1))) + { + error_at (m_loc, "%<-march=%s%>: Expect number " + "after %<%dp%>.", m_arch, version); + return NULL; + } + if (!major_p) + { + error_at (m_loc, "%<-march=%s%>: For %<%s%dp%dp?%>, version " + "number with more than 2 level is not supported.", + m_arch, ext, major, version); + return NULL; + } + major = version; + major_p = false; + version = 0; + } + else if (ISDIGIT (*p)) + version = (version * 10) + (*p - '0'); + else + break; + } + } if (major_p) major = version; @@ -643,7 +642,7 @@ riscv_subset_list::parse_std_ext (const char *p) return NULL; } - while (*p) + while (p != NULL && *p) { char subset[2] = {0, 0}; @@ -771,6 +770,9 @@ riscv_subset_list::parse_multiletter_ext (const char *p, /* std_ext_p= */ false, &explicit_version_p); free (ext); + if (end_of_version == NULL) + return NULL; + *q = '\0'; if (strlen (subset) == 1) -- cgit v1.1 From 592ed7db12ed0d6c71bca0cbfef6dcdf383bc24f Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Thu, 3 Jun 2021 13:44:53 +0300 Subject: arc: Remove obsolete options Remove the following obsolete options: - munalign-prob-threshold - malign-call - mmixed-code The ARC's options are marked as obsolete and ignored for backwards compatibility. gcc/ 2021-06-03 Claudiu Zissulescu * common/config/arc/arc-common.c (arc_option_optimization_table): Remove malign-call. * config/arc/arc.c (arc_unalign_branch_p): Remove unused function. * config/arc/arc.h (TARGET_MIXED_CODE): Remove macro. (INDEX_REG_CLASS): Only refer to GENERAL_REGS. * config/arc/arc.md (abssi2_mixed): Remove pattern. * config/arc/arc.opt (munalign-prob-threshold): Mark it obsolete. (malign-call): Likewise. (mmixed-code): Likewise. * doc/invoke.texi (ARC): Update doc. Signed-off-by: Claudiu Zissulescu --- gcc/common/config/arc/arc-common.c | 1 - 1 file changed, 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 86674dd..6a11902 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -62,7 +62,6 @@ static const struct default_options arc_option_optimization_table[] = { OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 }, { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 }, - { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 }, { OPT_LEVELS_NONE, 0, NULL, 0 } }; -- cgit v1.1 From 4d3907c222646174ec7e405491435aefc50bf1bb Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 4 Jun 2021 14:28:11 +0200 Subject: Reformat target.def for better parsing. gcc/c-family/ChangeLog: * c-target.def: Split long lines and replace them with '\n\'. gcc/ChangeLog: * common/common-target.def: Split long lines and replace them with '\n\'. * target.def: Likewise. * doc/tm.texi: Re-generated. --- gcc/common/common-target.def | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def index 1e10d4f..f54590a 100644 --- a/gcc/common/common-target.def +++ b/gcc/common/common-target.def @@ -64,23 +64,23 @@ DEFHOOK DEFHOOK (supports_split_stack, - "Whether this target supports splitting the stack when the options\ - described in @var{opts} have been passed. This is called\ - after options have been parsed, so the target may reject splitting\ - the stack in some configurations. The default version of this hook\ - returns false. If @var{report} is true, this function may issue a warning\ - or error; if @var{report} is false, it must simply return a value", + "Whether this target supports splitting the stack when the options\n\ +described in @var{opts} have been passed. This is called\n\ +after options have been parsed, so the target may reject splitting\n\ +the stack in some configurations. The default version of this hook\n\ +returns false. If @var{report} is true, this function may issue a warning\n\ +or error; if @var{report} is false, it must simply return a value", bool, (bool report, struct gcc_options *opts), hook_bool_bool_gcc_optionsp_false) DEFHOOK (get_valid_option_values, -"The hook is used for options that have a non-trivial list of\ - possible option values. OPTION_CODE is option code of opt_code\ - enum type. PREFIX is used for bash completion and allows an implementation\ - to return more specific completion based on the prefix. All string values\ - should be allocated from heap memory and consumers should release them. \ - The result will be pruned to cases with PREFIX if not NULL.", +"The hook is used for options that have a non-trivial list of\n\ +possible option values. OPTION_CODE is option code of opt_code\n\ +enum type. PREFIX is used for bash completion and allows an implementation\n\ +to return more specific completion based on the prefix. All string values\n\ +should be allocated from heap memory and consumers should release them.\n\ +The result will be pruned to cases with PREFIX if not NULL.", vec, (int option_code, const char *prefix), default_get_valid_option_values) @@ -100,10 +100,10 @@ DEFHOOKPOD DEFHOOKPOD (always_strip_dotdot, - "True if @file{..} components should always be removed from directory names\ - computed relative to GCC's internal directories, false (default) if such\ - components should be preserved and directory names containing them passed\ - to other tools such as the linker.", + "True if @file{..} components should always be removed from directory names\n\ +computed relative to GCC's internal directories, false (default) if such\n\ +components should be preserved and directory names containing them passed\n\ +to other tools such as the linker.", bool, false) HOOK_VECTOR_END (C90_EMPTY_HACK) -- cgit v1.1 From f58d03b5df25f9eab06b7eacea8da780fc2e0219 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 18 Jun 2021 13:21:51 +0100 Subject: arm: Fix multilib mapping for CDE extensions [PR100856]. On passing +cdecp[0-7] extension to the -march string in command line options, multilib linking is failing as mentioned in PR100856. This patch fixes this issue by generating a separate canonical string by removing compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function derived from arm_canon_arch. (arm_canon_arch_option): Call it. (arm_canon_arch_multilib_option): New function. * config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup. * config/arm/arm.h (arm_canon_arch_multilib_option): New prototype. (CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro. (MULTILIB_ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS. * config/arm/arm.opt (mlibarch): New option. * config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use of march on RHS with mlibarch. gcc/testsuite/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856 * gcc.target/arm/acle/pr100856.c: New test. * gcc.target/arm/multilib.exp: Add tests for cde options. --- gcc/common/config/arm/arm-common.c | 47 +++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 9980af6..481aa9e 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -627,9 +627,15 @@ public: The options array consists of couplets of information where the first item in each couplet is the string describing which option name was selected (arch, cpu, fpu) and the second is the value - passed for that option. */ -const char * -arm_canon_arch_option (int argc, const char **argv) + passed for that option. + + arch_for_multilib is boolean variable taking value true or false. + arch_for_multilib is false when the canonical representation is for -march + option and it is true when canonical representation is for -mlibarch option. + On passing arch_for_multilib true the canonical string generated will be + without the compiler options which are not required for multilib linking. */ +static const char * +arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib) { const char *arch = NULL; const char *cpu = NULL; @@ -694,8 +700,8 @@ arm_canon_arch_option (int argc, const char **argv) /* First build up a bitmap describing the target architecture. */ if (arch) { - selected_arch = arm_parse_arch_option_name (all_architectures, - "-march", arch); + selected_arch = arm_parse_arch_option_name (all_architectures, "-march", + arch, !arch_for_multilib); if (selected_arch == NULL) return ""; @@ -703,6 +709,15 @@ arm_canon_arch_option (int argc, const char **argv) arm_initialize_isa (target_isa, selected_arch->common.isa_bits); arm_parse_option_features (target_isa, &selected_arch->common, strchr (arch, '+')); + if (arch_for_multilib) + { + const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB, + isa_nobit}; + sbitmap isa_bits = sbitmap_alloc (isa_num_bits); + arm_initialize_isa (isa_bits, removable_bits); + bitmap_and_compl (target_isa, target_isa, isa_bits); + } + if (fpu && strcmp (fpu, "auto") != 0) { /* We assume that architectures do not have any FPU bits @@ -719,7 +734,8 @@ arm_canon_arch_option (int argc, const char **argv) else if (cpu) { const cpu_option *selected_cpu - = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu); + = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu, + !arch_for_multilib); if (selected_cpu == NULL) return ""; @@ -1069,3 +1085,22 @@ arm_asm_auto_mfpu (int argc, const char **argv) #define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; + +/* Returns a canonical representation of the -march option from the current + -march string (if given) and other options on the command line that might + affect the architecture. */ +const char * +arm_canon_arch_option (int argc, const char **argv) +{ + return arm_canon_arch_option_1 (argc, argv, false); +} + +/* Returns a canonical representation of the -mlibarch option from the current + -march string (if given) and other options on the command line that might + affect the architecture after removing the compiler extension options which + are not required for multilib linking. */ +const char * +arm_canon_arch_multilib_option (int argc, const char **argv) +{ + return arm_canon_arch_option_1 (argc, argv, true); +} -- cgit v1.1 From 22f201e4b32a4f8bc1e6462ee19643edae5d25a3 Mon Sep 17 00:00:00 2001 From: Hafiz Abid Qadeer Date: Mon, 21 Jun 2021 22:47:58 +0100 Subject: [amdgcn] Use frame pointer for CFA expressions. As size of address is bigger than registers in amdgcn, we are forced to use DW_CFA_def_cfa_expression to make an expression that concatenates multiple registers for the value of the CFA. This then prohibits us from using many of the dwarf ops which expect CFA rule to be a single regsiter plus an offset. Using frame pointer in the CFA rule is only real possibility as it is saved in every frame and it is easy to unwind its value. So unless user gives fomit-frame-pointer, we use frame pointer for the cfi information. This options also has a different default now. gcc/ * common/config/gcn/gcn-common.c (gcn_option_optimization_table): Change OPT_fomit_frame_pointer to -O3. * config/gcn/gcn.c (gcn_expand_prologue): Prefer the frame pointer when emitting CFI. (gcn_expand_prologue): Prefer the frame pointer when emitting CFI. (gcn_frame_pointer_rqd): New function. (TARGET_FRAME_POINTER_REQUIRED): New hook. --- gcc/common/config/gcn/gcn-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/gcn/gcn-common.c b/gcc/common/config/gcn/gcn-common.c index 305c310..695eb46 100644 --- a/gcc/common/config/gcn/gcn-common.c +++ b/gcc/common/config/gcn/gcn-common.c @@ -27,7 +27,7 @@ /* Set default optimization options. */ static const struct default_options gcn_option_optimization_table[] = { - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, + { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_NONE, 0, NULL, 0 } }; -- cgit v1.1 From 6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sat, 17 Jul 2021 14:38:39 -0700 Subject: x86: Enable the GPR only instructions for -mgeneral-regs-only For -mgeneral-regs-only, enable the GPR only instructions which are enabled implicitly by SSE ISAs unless they have been disabled explicitly. gcc/ PR target/101492 * common/config/i386/i386-common.c (ix86_handle_option): For -mgeneral-regs-only, enable the GPR only instructions which are enabled implicitly by SSE ISAs unless they have been disabled explicitly. gcc/testsuite/ PR target/101492 * gcc.target/i386/pr101492-1.c: New test. * gcc.target/i386/pr101492-2.c: Likewise. * gcc.target/i386/pr101492-3.c: Likewise. * gcc.target/i386/pr101492-4.c: Likewise. --- gcc/common/config/i386/i386-common.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index e156cc3..76ab1a1 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -354,16 +354,39 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mgeneral_regs_only: if (value) { + HOST_WIDE_INT general_regs_only_flags = 0; + HOST_WIDE_INT general_regs_only_flags2 = 0; + + /* NB: Enable the GPR only instructions which are enabled + implicitly by SSE ISAs unless they have been disabled + explicitly. */ + if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)) + { + if (!TARGET_EXPLICIT_CRC32_P (opts)) + general_regs_only_flags |= OPTION_MASK_ISA_CRC32; + if (!TARGET_EXPLICIT_POPCNT_P (opts)) + general_regs_only_flags |= OPTION_MASK_ISA_POPCNT; + } + if (TARGET_SSE3_P (opts->x_ix86_isa_flags)) + { + if (!TARGET_EXPLICIT_MWAIT_P (opts)) + general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT; + } + /* Disable MMX, SSE and x87 instructions if only general registers are allowed. */ opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; + opts->x_ix86_isa_flags |= general_regs_only_flags; + opts->x_ix86_isa_flags2 |= general_regs_only_flags2; opts->x_ix86_isa_flags_explicit - |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; + |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET + | general_regs_only_flags); opts->x_ix86_isa_flags2_explicit - |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; + |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET + | general_regs_only_flags2); opts->x_target_flags &= ~MASK_80387; } -- cgit v1.1 From 2d7967a10c2f3b4652f77a1a2119ba03b3472266 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Thu, 12 Aug 2021 14:21:22 +0300 Subject: arc: Small data doesn't need fcommon option ARC backend is defaulting to -fcommon. This is not anylonger needed, remove it. gcc/ 2021-08-12 Claudiu Zissulescu * common/config/arc/arc-common.c (arc_option_init_struct): Remove fno-common reference. * config/arc/arc.c (arc_override_options): Remove overriding of flag_no_common. Signed-off-by: Claudiu Zissulescu --- gcc/common/config/arc/arc-common.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 6a11902..3b36d09 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -30,10 +30,8 @@ along with GCC; see the file COPYING3. If not see #include "flags.h" static void -arc_option_init_struct (struct gcc_options *opts) +arc_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED) { - opts->x_flag_no_common = 255; /* Mark as not user-initialized. */ - /* Which cpu we're compiling for (ARC600, ARC601, ARC700, ARCv2). */ arc_cpu = PROCESSOR_NONE; } -- cgit v1.1 From a68412117fa47786bd82ab79b009ec7933aef476 Mon Sep 17 00:00:00 2001 From: "Guo, Xuepeng" Date: Mon, 24 Dec 2018 19:39:26 -0800 Subject: AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 instructions. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect FEATURE_AVX512FP16. * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512FP16_SET, OPTION_MASK_ISA_AVX512FP16_UNSET, OPTION_MASK_ISA2_AVX512FP16_SET, OPTION_MASK_ISA2_AVX512FP16_UNSET): New. (OPTION_MASK_ISA2_AVX512BW_UNSET, OPTION_MASK_ISA2_AVX512BF16_UNSET): Add AVX512FP16. (ix86_handle_option): Handle -mavx512fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX512FP16. * common/config/i386/i386-isas.h: Add entry for AVX512FP16. * config.gcc: Add avx512fp16intrin.h. * config/i386/avx512fp16intrin.h: New intrinsic header. * config/i386/cpuid.h: Add bit_AVX512FP16. * config/i386/i386-builtin-types.def: (FLOAT16): New primitive type. * config/i386/i386-builtins.c: Support _Float16 type for i386 backend. (ix86_register_float16_builtin_type): New function. (ix86_float16_type_node): New. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512FP16__. * config/i386/i386-expand.c (ix86_expand_branch): Support HFmode. (ix86_prepare_fp_compare_args): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_expand_fp_movcc): Ditto. * config/i386/i386-isa.def: Add PTA define for AVX512FP16. * config/i386/i386-options.c (isa2_opts): Add -mavx512fp16. (ix86_valid_target_attribute_inner_p): Add avx512fp16 attribute. * config/i386/i386.c (ix86_get_ssemov): Use vmovdqu16/vmovw/vmovsh for HFmode/HImode scalar or vector. (ix86_get_excess_precision): Use FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 when TARGET_AVX512FP16 existed. (sse_store_index): Use SFmode cost for HFmode cost. (inline_memory_move_cost): Add HFmode, and perfer SSE cost over GPR cost for HFmode. (ix86_hard_regno_mode_ok): Allow HImode in sse register. (ix86_mangle_type): Add manlging for _Float16 type. (inline_secondary_memory_needed): No memory is needed for 16bit movement between gpr and sse reg under TARGET_AVX512FP16. (ix86_multiplication_cost): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_division_cost): Ditto. (ix86_rtx_costs): Ditto. (ix86_add_stmt_cost): Ditto. (ix86_optab_supported_p): Ditto. * config/i386/i386.h (VALID_AVX512F_SCALAR_MODE): Add HFmode. (SSE_FLOAT_MODE_SSEMATH_OR_HF_P): Add HFmode. (PTA_SAPPHIRERAPIDS): Add PTA_AVX512FP16. * config/i386/i386.md (mode): Add HFmode. (MODE_SIZE): Add HFmode. (isa): Add avx512fp16. (enabled): Handle avx512fp16. (ssemodesuffix): Add sh suffix for HFmode. (comm): Add mult, div. (plusminusmultdiv): New code iterator. (insn): Add mult, div. (*movhf_internal): Adjust for avx512fp16 instruction. (*movhi_internal): Ditto. (*cmpihf): New define_insn for HFmode. (*ieee_shf3): Likewise. (extendhf2): Likewise. (trunchf2): Likewise. (floathf2): Likewise. (*hf): Likewise. (cbranchhf4): New expander. (movhfcc): Likewise. (hf3): Likewise. (mulhf3): Likewise. (divhf3): Likewise. * config/i386/i386.opt: Add mavx512fp16. * config/i386/immintrin.h: Include avx512fp16intrin.h. * doc/invoke.texi: Add mavx512fp16. * doc/extend.texi: Add avx512fp16 Usage Notes. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add -mavx512fp16 in dg-options. * gcc.target/i386/avx-2.c: Ditto. * gcc.target/i386/avx512-check.h: Check cpuid for AVX512FP16. * gcc.target/i386/funcspec-56.inc: Add new target attribute check. * gcc.target/i386/sse-13.c: Add -mavx512fp16. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_avx512fp16): New. * g++.target/i386/float16-1.C: New test. * g++.target/i386/float16-2.C: Ditto. * g++.target/i386/float16-3.C: Ditto. * gcc.target/i386/avx512fp16-12a.c: Ditto. * gcc.target/i386/avx512fp16-12b.c: Ditto. * gcc.target/i386/float16-3a.c: Ditto. * gcc.target/i386/float16-3b.c: Ditto. * gcc.target/i386/float16-4a.c: Ditto. * gcc.target/i386/float16-4b.c: Ditto. * gcc.target/i386/pr54855-12.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. Co-Authored-By: H.J. Lu Co-Authored-By: Liu Hongtao Co-Authored-By: Wang Hongyu Co-Authored-By: Xu Dianhong --- gcc/common/config/i386/cpuinfo.h | 2 ++ gcc/common/config/i386/i386-common.c | 26 ++++++++++++++++++++++++-- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + 4 files changed, 28 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 458f41d..1835ac6 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -731,6 +731,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVX5124FMAPS); if (edx & bit_AVX512VP2INTERSECT) set_feature (FEATURE_AVX512VP2INTERSECT); + if (edx & bit_AVX512FP16) + set_feature (FEATURE_AVX512FP16); } __cpuid_count (7, 1, eax, ebx, ecx, edx); diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 76ab1a1..00c65ba 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_SET \ (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET +#define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16 #define OPTION_MASK_ISA_AVX512VNNI_SET \ (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI @@ -231,6 +233,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 +#define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET +#define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ @@ -313,7 +317,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_AVX512BF16_UNSET \ | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ + | OPTION_MASK_ISA2_AVX512FP16_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ (OPTION_MASK_ISA2_AVX512F_UNSET) #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET @@ -326,7 +331,9 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET -#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET +#define OPTION_MASK_ISA2_AVX512BW_UNSET \ + (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + | OPTION_MASK_ISA2_AVX512FP16_UNSET) /* Set 1 << value as value of -malign-FLAG option. */ @@ -853,6 +860,21 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx512fp16: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET; + } + return true; + case OPT_mavx512vnni: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index e68dd65..4e0659f 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -228,6 +228,7 @@ enum processor_features FEATURE_AESKLE, FEATURE_WIDEKL, FEATURE_AVXVNNI, + FEATURE_AVX512FP16, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 898c18f..a678366 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -169,4 +169,5 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("aeskle", FEATURE_AESKLE, P_NONE, NULL) ISA_NAMES_TABLE_ENTRY("widekl", FEATURE_WIDEKL, P_NONE, "-mwidekl") ISA_NAMES_TABLE_ENTRY("avxvnni", FEATURE_AVXVNNI, P_NONE, "-mavxvnni") + ISA_NAMES_TABLE_ENTRY("avx512fp16", FEATURE_AVX512FP16, P_NONE, "-mavx512fp16") ISA_NAMES_TABLE_END -- cgit v1.1 From 8ea292591e42aa4d52b4b7a00b86335bfd2e2e85 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Thu, 12 Aug 2021 15:20:43 +0200 Subject: i386: support micro-levels in target{,_clone} attrs [PR101696] As mentioned in the PR, we do miss supports target micro-architectures in target and target_clone attribute. While the levels x86-64 x86-64-v2 x86-64-v3 x86-64-v4 are supported values by -march option, they are actually only aliases for k8 CPU. That said, they are more closer to __builtin_cpu_supports function and we decided to implement it there. PR target/101696 gcc/ChangeLog: * common/config/i386/cpuinfo.h (cpu_indicator_init): Add support for x86-64 micro levels for __builtin_cpu_supports. * common/config/i386/i386-cpuinfo.h (enum feature_priority): Add priorities for the micro-arch levels. (enum processor_features): Add new features. * common/config/i386/i386-isas.h: Add micro-arch features. * config/i386/i386-builtins.c (get_builtin_code_for_version): Support the micro-arch levels by callsing __builtin_cpu_supports. * doc/extend.texi: Document that the levels are support by __builtin_cpu_supports. gcc/testsuite/ChangeLog: * g++.target/i386/mv30.C: New test. * gcc.target/i386/mvc16.c: New test. * gcc.target/i386/builtin_target.c (CHECK___builtin_cpu_supports): New. Co-Authored-By: H.J. Lu --- gcc/common/config/i386/cpuinfo.h | 48 +++++++++++++++++++++++++++++++++++ gcc/common/config/i386/i386-cpuinfo.h | 8 ++++++ gcc/common/config/i386/i386-isas.h | 5 ++++ 3 files changed, 61 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 1835ac6..bbf29bdb 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -46,6 +46,10 @@ struct __processor_model2 # define CHECK___builtin_cpu_is(cpu) #endif +#ifndef CHECK___builtin_cpu_supports +# define CHECK___builtin_cpu_supports(isa) +#endif + /* Return non-zero if the processor has feature F. */ static inline int @@ -933,6 +937,50 @@ cpu_indicator_init (struct __processor_model *cpu_model, else cpu_model->__cpu_vendor = VENDOR_OTHER; + if (has_cpu_feature (cpu_model, cpu_features2, FEATURE_LM) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_SSE2)) + { + CHECK___builtin_cpu_supports ("x86-64"); + set_cpu_feature (cpu_model, cpu_features2, + FEATURE_X86_64_BASELINE); + if (has_cpu_feature (cpu_model, cpu_features2, FEATURE_CMPXCHG16B) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_POPCNT) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_LAHF_LM) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_SSE4_2)) + { + CHECK___builtin_cpu_supports ("x86-64-v2"); + set_cpu_feature (cpu_model, cpu_features2, + FEATURE_X86_64_V2); + if (has_cpu_feature (cpu_model, cpu_features2, FEATURE_AVX2) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_BMI) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_BMI2) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_F16C) + && has_cpu_feature (cpu_model, cpu_features2, FEATURE_FMA) + && has_cpu_feature (cpu_model, cpu_features2, + FEATURE_LZCNT) + && has_cpu_feature (cpu_model, cpu_features2, + FEATURE_MOVBE)) + { + CHECK___builtin_cpu_supports ("x86-64-v3"); + set_cpu_feature (cpu_model, cpu_features2, + FEATURE_X86_64_V3); + if (has_cpu_feature (cpu_model, cpu_features2, + FEATURE_AVX512BW) + && has_cpu_feature (cpu_model, cpu_features2, + FEATURE_AVX512CD) + && has_cpu_feature (cpu_model, cpu_features2, + FEATURE_AVX512DQ) + && has_cpu_feature (cpu_model, cpu_features2, + FEATURE_AVX512VL)) + { + CHECK___builtin_cpu_supports ("x86-64-v4"); + set_cpu_feature (cpu_model, cpu_features2, + FEATURE_X86_64_V4); + } + } + } + } + gcc_assert (cpu_model->__cpu_vendor < VENDOR_MAX); gcc_assert (cpu_model->__cpu_type < CPU_TYPE_MAX); gcc_assert (cpu_model->__cpu_subtype < CPU_SUBTYPE_MAX); diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 4e0659f..dc1a9fa 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -102,6 +102,7 @@ enum feature_priority P_MMX, P_SSE, P_SSE2, + P_X86_64_BASELINE, P_SSE3, P_SSSE3, P_PROC_SSSE3, @@ -111,6 +112,7 @@ enum feature_priority P_SSE4_2, P_PROC_SSE4_2, P_POPCNT, + P_X86_64_V2, P_AES, P_PCLMUL, P_AVX, @@ -125,8 +127,10 @@ enum feature_priority P_BMI2, P_AVX2, P_PROC_AVX2, + P_X86_64_V3, P_AVX512F, P_PROC_AVX512F, + P_X86_64_V4, P_PROC_DYNAMIC }; @@ -229,6 +233,10 @@ enum processor_features FEATURE_WIDEKL, FEATURE_AVXVNNI, FEATURE_AVX512FP16, + FEATURE_X86_64_BASELINE, + FEATURE_X86_64_V2, + FEATURE_X86_64_V3, + FEATURE_X86_64_V4, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index a678366..7784010 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -170,4 +170,9 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("widekl", FEATURE_WIDEKL, P_NONE, "-mwidekl") ISA_NAMES_TABLE_ENTRY("avxvnni", FEATURE_AVXVNNI, P_NONE, "-mavxvnni") ISA_NAMES_TABLE_ENTRY("avx512fp16", FEATURE_AVX512FP16, P_NONE, "-mavx512fp16") + ISA_NAMES_TABLE_ENTRY("x86-64", FEATURE_X86_64_BASELINE, P_X86_64_BASELINE, + NULL) + ISA_NAMES_TABLE_ENTRY("x86-64-v2", FEATURE_X86_64_V2, P_X86_64_V2, NULL) + ISA_NAMES_TABLE_ENTRY("x86-64-v3", FEATURE_X86_64_V3, P_X86_64_V3, NULL) + ISA_NAMES_TABLE_ENTRY("x86-64-v4", FEATURE_X86_64_V4, P_X86_64_V4, NULL) ISA_NAMES_TABLE_END -- cgit v1.1