From 708b3600d043e5885ed25464189a88590feeaac9 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 16 Aug 2020 06:14:25 -0700 Subject: x86: Detect Rocket Lake and Alder Lake From arch/x86/include/asm/intel-family.h on Linux kernel master branch: #define INTEL_FAM6_ROCKETLAKE 0xA7 #define INTEL_FAM6_ALDERLAKE 0x97 * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Rocket Lake and Alder Lake. --- gcc/common/config/i386/cpuinfo.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index b14c7c6..12237e2 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -387,6 +387,8 @@ get_intel_cpu (struct __processor_model *cpu_model, case 0xa5: case 0xa6: /* Comet Lake. */ + case 0xa7: + /* Rocket Lake. */ cpu = "skylake"; CHECK___builtin_cpu_is ("corei7"); CHECK___builtin_cpu_is ("skylake"); @@ -456,6 +458,14 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_type = INTEL_COREI7; cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE; break; + case 0x97: + /* Alder Lake. */ + cpu = "alderlake"; + CHECK___builtin_cpu_is ("corei7"); + CHECK___builtin_cpu_is ("alderlake"); + cpu_model->__cpu_type = INTEL_COREI7; + cpu_model->__cpu_subtype = INTEL_COREI7_ALDERLAKE; + break; case 0x8f: /* Sapphire Rapids. */ cpu = "sapphirerapids"; -- cgit v1.1 From 6ba09730375b47c0442b3638d02d75fb3430425c Mon Sep 17 00:00:00 2001 From: liuhongt Date: Fri, 28 Aug 2020 15:01:18 +0800 Subject: Fix: AVX512VP2INTERSECT should imply AVX512DQ. gcc/ChangeLog * common/config/i386/i386-common.c (ix86_handle_option): Set AVX512DQ when AVX512VP2INTERSECT exists. --- gcc/common/config/i386/i386-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index bb14305..5305145 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -906,8 +906,8 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; } else { -- cgit v1.1 From cd2d3822ca0f2f743601cc9d048d51f6d326f6a2 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Tue, 8 Sep 2020 10:10:17 +0100 Subject: MSP430: Use enums to handle -mcpu= values The -mcpu= option accepts only a handful of string values. Using enums instead of strings to handle the accepted values removes the need to have specific processing of the strings in the backend, and simplifies any comparisons which need to be performed on the value. It also allows the default value to have semantic equivalence to a user set value, whilst retaining the ability to differentiate between them. Practically, this allows a user set -mcpu= value to override the the ISA set by -mmcu, whilst the default -mcpu= value can still have an explicit meaning. gcc/ChangeLog: * common/config/msp430/msp430-common.c (msp430_handle_option): Remove OPT_mcpu_ handling. Set target_cpu value to new enum values when parsing certain -mmcu= values. * config/msp430/msp430-opts.h (enum msp430_cpu_types): New. * config/msp430/msp430.c (msp430_option_override): Handle new target_cpu enum values. Set target_cpu using extracted value for given MCU when -mcpu= option is not passed by the user. * config/msp430/msp430.opt: Handle -mcpu= values using enums. gcc/testsuite/ChangeLog: * gcc.target/msp430/mcpu-is-430.c: New test. * gcc.target/msp430/mcpu-is-430x.c: New test. * gcc.target/msp430/mcpu-is-430xv2.c: New test. --- gcc/common/config/msp430/msp430-common.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/msp430/msp430-common.c b/gcc/common/config/msp430/msp430-common.c index 0e261c4..65be319 100644 --- a/gcc/common/config/msp430/msp430-common.c +++ b/gcc/common/config/msp430/msp430-common.c @@ -27,7 +27,7 @@ #include "opts.h" #include "flags.h" -/* Check for generic -mcpu= and -mmcu= names here. If found then we +/* Check for generic -mmcu= names here. If found then we convert to a baseline cpu name. Otherwise we allow the option to be passed on to the backend where it can be checked more fully. */ @@ -39,26 +39,6 @@ msp430_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, { switch (decoded->opt_index) { - case OPT_mcpu_: - if (strcasecmp (decoded->arg, "msp430x") == 0 - || strcasecmp (decoded->arg, "msp430xv2") == 0 - || strcasecmp (decoded->arg, "430x") == 0 - || strcasecmp (decoded->arg, "430xv2") == 0) - { - target_cpu = "msp430x"; - } - else if (strcasecmp (decoded->arg, "msp430") == 0 - || strcasecmp (decoded->arg, "430") == 0) - { - target_cpu = "msp430"; - } - else - { - error ("unrecognized argument of %<-mcpu%>: %s", decoded->arg); - return false; - } - break; - case OPT_mmcu_: /* For backwards compatibility we recognise two generic MCU 430X names. However we want to be able to generate special C @@ -66,13 +46,13 @@ msp430_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, to NULL. */ if (strcasecmp (decoded->arg, "msp430") == 0) { - target_cpu = "msp430"; + target_cpu = MSP430_CPU_MSP430; target_mcu = NULL; } else if (strcasecmp (decoded->arg, "msp430x") == 0 || strcasecmp (decoded->arg, "msp430xv2") == 0) { - target_cpu = "msp430x"; + target_cpu = MSP430_CPU_MSP430X; target_mcu = NULL; } break; -- cgit v1.1 From 786177a3fc9229f964058ae37571f2468ca1dce4 Mon Sep 17 00:00:00 2001 From: Alex Coplan Date: Thu, 10 Sep 2020 17:05:40 +0100 Subject: aarch64: Add support for Armv8-R This adds support for Armv8-R AArch64 to GCC. It adds the -march value armv8-r and sets the ACLE feature macro __ARM_ARCH_PROFILE correctly when -march is set to armv8-r. gcc/ChangeLog: * common/config/aarch64/aarch64-common.c (aarch64_get_extension_string_for_isa_flags): Don't force +crc for Armv8-R. * config/aarch64/aarch64-arches.def: Add entry for Armv8-R. * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): Set __ARM_ARCH_PROFILE correctly for Armv8-R. * config/aarch64/aarch64.h (AARCH64_FL_V8_R): New. (AARCH64_FL_FOR_ARCH8_R): New. (AARCH64_ISA_V8_R): New. * doc/invoke.texi: Add Armv8-R to architecture table. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/armv8-r.c: New test. --- gcc/common/config/aarch64/aarch64-common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c index 51bd319..909006e 100644 --- a/gcc/common/config/aarch64/aarch64-common.c +++ b/gcc/common/config/aarch64/aarch64-common.c @@ -426,8 +426,11 @@ aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags, names. However as a special case if CRC was enabled before, always print it. This is required because some CPUs have an incorrect specification in older assemblers. Even though CRC should be the default for these - cases the -mcpu values won't turn it on. */ - if (isa_flags & AARCH64_ISA_CRC) + cases the -mcpu values won't turn it on. + + Note that assemblers with Armv8-R AArch64 support should not have this + issue, so we don't need this fix when targeting Armv8-R. */ + if ((isa_flags & AARCH64_ISA_CRC) && !AARCH64_ISA_V8_R) isa_flag_bits |= AARCH64_ISA_CRC; /* Pass Two: -- cgit v1.1 From a8c4b66a41fa805757f5943bd41690243365bccd Mon Sep 17 00:00:00 2001 From: liuhongt Date: Wed, 16 Sep 2020 13:56:30 +0800 Subject: If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx. Current status is -mno-avx implies -mno-xsave which should be wrong. gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX_UNSET): Remove OPTION_MASK_ISA_XSAVE_UNSET. (OPTION_MASK_ISA_XSAVE_UNSET): Add OPTION_MASK_ISA_AVX_UNSET. gcc/testsuite/ChangeLog * gcc.target/i386/xsave-avx-1.c: New test. --- gcc/common/config/i386/i386-common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 5305145..6e34095 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -187,12 +187,13 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX_UNSET \ (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ - | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET) + | OPTION_MASK_ISA_AVX2_UNSET ) #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR #define OPTION_MASK_ISA_XSAVE_UNSET \ (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ - | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET) + | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ + | OPTION_MASK_ISA_AVX_UNSET) #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT #define OPTION_MASK_ISA_AVX2_UNSET \ (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) -- cgit v1.1 From 5c609842d13a4c9c6be1a10f7980a74d27daeb85 Mon Sep 17 00:00:00 2001 From: liuhongt Date: Thu, 25 Jul 2019 16:49:36 +0800 Subject: Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16. AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 16 +++++++++++ gcc/common/config/i386/i386-common.c | 50 +++++++++++++++++++++++++++++++++++ gcc/common/config/i386/i386-cpuinfo.h | 3 +++ gcc/common/config/i386/i386-isas.h | 3 +++ 4 files changed, 72 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 12237e2..c96455c 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -509,15 +509,20 @@ get_available_features (struct __processor_model *cpu_model, #define XSTATE_OPMASK 0x20 #define XSTATE_ZMM 0x40 #define XSTATE_HI_ZMM 0x80 +#define XSTATE_TILECFG 0x20000 +#define XSTATE_TILEDATA 0x40000 #define XCR_AVX_ENABLED_MASK \ (XSTATE_SSE | XSTATE_YMM) #define XCR_AVX512F_ENABLED_MASK \ (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM) +#define XCR_AMX_ENABLED_MASK \ + (XSTATE_TILECFG | XSTATE_TILEDATA) /* Check if AVX and AVX512 are usable. */ int avx_usable = 0; int avx512_usable = 0; + int amx_usable = 0; if ((ecx & bit_OSXSAVE)) { /* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and @@ -533,6 +538,8 @@ get_available_features (struct __processor_model *cpu_model, avx512_usable = ((xcrlow & XCR_AVX512F_ENABLED_MASK) == XCR_AVX512F_ENABLED_MASK); } + amx_usable = ((xcrlow & XCR_AMX_ENABLED_MASK) + == XCR_AMX_ENABLED_MASK); } #define set_feature(f) \ @@ -651,6 +658,15 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_PCONFIG); if (edx & bit_IBT) set_feature (FEATURE_IBT); + if (amx_usable) + { + if (edx & bit_AMX_TILE) + set_feature (FEATURE_AMX_TILE); + if (edx & bit_AMX_INT8) + set_feature (FEATURE_AMX_INT8); + if (edx & bit_AMX_BF16) + set_feature (FEATURE_AMX_BF16); + } if (avx512_usable) { if (ebx & bit_AVX512F) diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 6e34095..1014214 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -101,6 +101,9 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -194,6 +197,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ | OPTION_MASK_ISA_AVX_UNSET) +#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT #define OPTION_MASK_ISA_AVX2_UNSET \ (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) @@ -247,6 +251,9 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -931,6 +938,47 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mamx_tile: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET; + } + return true; + + case OPT_mamx_int8: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET; + } + return true; + + case OPT_mamx_bf16: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET; + } + return true; + case OPT_mfma: if (value) { @@ -1265,6 +1313,8 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET; } return true; diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 84ca97e..5b94b1f 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -216,6 +216,9 @@ enum processor_features FEATURE_XSAVEC, FEATURE_XSAVEOPT, FEATURE_XSAVES, + FEATURE_AMX_TILE, + FEATURE_AMX_INT8, + FEATURE_AMX_BF16, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 08c9dbe..3c830ea 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -160,4 +160,7 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("xsaveopt", FEATURE_XSAVEOPT, P_NONE, "-mxsaveopt") ISA_NAMES_TABLE_ENTRY("xsaves", FEATURE_XSAVES, P_NONE, "-mxsaves") + ISA_NAMES_TABLE_ENTRY("amx-tile", FEATURE_AMX_TILE, P_NONE, "-mamx-tile") + ISA_NAMES_TABLE_ENTRY("amx-int8", FEATURE_AMX_INT8, P_NONE, "-mamx-int8") + ISA_NAMES_TABLE_ENTRY("amx-bf16", FEATURE_AMX_BF16, P_NONE, "-mamx-bf16") ISA_NAMES_TABLE_END -- cgit v1.1 From 324bec558e95584e8c1997575ae9d75978af59f1 Mon Sep 17 00:00:00 2001 From: Florian Weimer Date: Thu, 1 Oct 2020 10:08:24 +0200 Subject: PR target/97250: i386: Add support for x86-64-v2, x86-64-v3, x86-64-v4 levels for x86-64 These micro-architecture levels are defined in the x86-64 psABI: https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9 PTA_NO_TUNE is introduced so that the new processor alias table entries do not affect the CPU tuning setting in ix86_tune. The tests depend on the macros added in commit 92e652d8c21bd7e66cbb0f900 ("i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on ISA flags"). gcc/: PR target/97250 * config/i386/i386.h (PTA_NO_TUNE, PTA_X86_64_BASELINE) (PTA_X86_64_V2, PTA_X86_64_V3, PTA_X86_64_V4): New. * common/config/i386/i386-common.c (processor_alias_table): Add "x86-64-v2", "x86-64-v3", "x86-64-v4". * config/i386/i386-options.c (ix86_option_override_internal): Handle new PTA_NO_TUNE processor table entries. * doc/invoke.texi (x86 Options): Document new -march values. gcc/testsuite/: PR target/97250 * gcc.target/i386/x86-64-v2.c: New test. * gcc.target/i386/x86-64-v3.c: New test. * gcc.target/i386/x86-64-v3-haswell.c: New test. * gcc.target/i386/x86-64-v3-skylake.c: New test. * gcc.target/i386/x86-64-v4.c: New test. --- gcc/common/config/i386/i386-common.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 1014214..62a620b 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -1795,9 +1795,13 @@ const pta processor_alias_table[] = PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE}, {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE}, - {"x86-64", PROCESSOR_K8, CPU_K8, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, - 0, P_NONE}, + {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE}, + {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE, + 0, P_NONE}, + {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE, + 0, P_NONE}, + {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE, + 0, P_NONE}, {"eden-x2", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE}, -- cgit v1.1