From 62e56a0d652ce83ae3d220cc4a01de46674188f1 Mon Sep 17 00:00:00 2001 From: Victoria Stepanyan Date: Sun, 6 Dec 2015 17:02:48 +0000 Subject: support for AMD clzero isa. gcc/ChangeLog 2015-12-06 Victoria Stepanyan * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLZERO_SET): New. (ix86_handle_option): Handle clzero. * config.gcc (i[34567]86-*-*): Add clzerointrin.h, (x86_64-*-*): Likewise. * config/i386/clzerointrin.h: New header. * config/i386/cpuid.h (bit_CLZERO): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect CLZERO support. * config/i386/i386.opt (clzero): New. * config/i386/i386-c.c: Define __CLZERO__ if needed. * config/i386/i386.c (ix86_target_string): Define -mclzero option. (PTA_CLZERO): New. (ix86_option_override_internal): Handle new option. (processor_alias_table): Added PTA_CLZERO. (ix86_valid_target_attribute_inner_p): Add OPT_mclzero. (ix86_builtins): Add IX86_BUILTIN_CLZERO, IX86_BUILTIN_CLZERO. (ix86_expand_builtin): Handle IX86_BUILTIN_CLZERO and IX86_BUILTIN_CLZERO built-ins. * config/i386/i386.h (TARGET_CLZERO): New. * config/i386/i386.md (unspecv): Add UNSPEC_CLZERO. (clzero): New pattern. (clzero_): New pattern. * config/i386/x86intrin.h: Include clzerointrin.h. * doc/extend.texi: Document clzero builtins. * doc/invoke.texi: Document -mclzero option. gcc/testsuite/ChangeLog 2015-12-06 Victoria Stepanyan * gcc.target/i386/clzero.c: New. * gcc.target/i386/sse-12.c: Add -mclzero. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r231340 --- gcc/common/config/i386/i386-common.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 49899bd..a9d2208 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -128,6 +128,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_F16C_SET \ (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX +#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -188,6 +189,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX +#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -947,6 +949,20 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mclzero: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLZERO_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLZERO_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; + } + return true; + + /* Comes from final.c -- no real reason to change it. */ #define MAX_CODE_ALIGN 16 -- cgit v1.1