From c7be0832b54669b39dfb56bd91c783dd91aad766 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 16 Mar 2020 17:22:39 +0000 Subject: [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. This patch is part of MVE ACLE intrinsics framework. This patches add support to update (read/write) the APSR (Application Program Status Register) register and FPSCR (Floating-point Status and Control Register) register for MVE. This patch also enables thumb2 mov RTL patterns for MVE. A new feature bit vfp_base is added. This bit is enabled for all VFP, MVE and MVE with floating point extensions. This bit is used to enable the macro TARGET_VFP_BASE. For all the VFP instructions, RTL patterns, status and control registers are guarded by TARGET_HAVE_FLOAT. But this patch modifies that and the common instructions, RTL patterns, status and control registers bewteen MVE and VFP are guarded by TARGET_VFP_BASE macro. The RTL pattern set_fpscr and get_fpscr are updated to use VFPCC_REGNUM because few MVE intrinsics set/get carry bit of FPSCR register. Please refer to Arm reference manual [1] for more details. [1] https://developer.arm.com/docs/ddi0553/latest 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base feature bit is on and -mfpu=auto is passed as compiler option, do not generate error on not finding any matching fpu. Because in this case fpu is not required. * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is enabled for MVE and also for all VFP extensions. (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 is enabled. (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 along with feature bits mve_float. (mve): Modify add options in armv8.1-m.main arch for MVE. (mve.fp): Modify add options in armv8.1-m.main arch for MVE with floating point. * config/arm/arm.c (use_return_insn): Replace the check with TARGET_VFP_BASE. (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE. (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as well. (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE as well. (arm_compute_frame_layout): Likewise. (arm_save_coproc_regs): Likewise. (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM in MVE as well. (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. (arm_expand_epilogue_apcs_frame): Likewise. (arm_expand_epilogue): Likewise. (arm_conditional_register_usage): Likewise. (arm_declare_function_name): Add check to skip printing .fpu directive in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is "softvfp". * config/arm/arm.h (TARGET_VFP_BASE): Define. * config/arm/arm.md (arch): Add "mve" to arch. (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. * config/arm/constraints.md (Uf): Define to allow modification to FPCCR in MVE. * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard to not allow for MVE. * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs enum. (VUNSPEC_GET_FPSCR): Define. * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS instructions which move to general-purpose Register from Floating-point Special register and vice-versa. (thumb2_movhi_fp16): Likewise. (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along with MCR and MRC instructions which set and get Floating-point Status and Control Register (FPSCR). (movdi_vfp): Modify pattern to enable Single-precision scalar float move in MVE. (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar float move patterns in MVE. (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding TARGET_VFP_BASE check. (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. 2020-03-16 Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test. * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. --- gcc/common/config/arm/arm-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 30a2a1d..78a779c 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -1009,7 +1009,8 @@ arm_asm_auto_mfpu (int argc, const char **argv) } } - gcc_assert (i != TARGET_FPU_auto); + gcc_assert (i != TARGET_FPU_auto + || bitmap_bit_p (target_isa, isa_bit_vfp_base)); } auto_fpu = (char *) xmalloc (strlen (fpuname) + sizeof ("-mfpu=")); -- cgit v1.1 From 53161358180fdc2c2c21c8f46bbdd339a1fbb8ae Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Fri, 3 Apr 2020 15:18:35 +0100 Subject: AArch64: Fix options canonicalization for assembler It is currently impossible to use fp16 on any architecture higher than Armv8.3-a due to a bug in options canonization. This bug results in the fp16 flag not being emitted in the assembly when it should have been. This is caused by a complicated architectural requirement at Armv8.4-a. On Armv8.2-a and Armv8.3-a fp16fml is an optional extension and turning it on turns on both fp and fp16. However starting with Armv8.4-a fp16fml is mandatory if fp16 is available, otherwise it's optional. In short this means that to enable fp16fml the smallest option that needs to passed to the assembler is Armv8.4-a+fp16. The fix in this patch takes into account that an option may be on by default in an architecture, but that not all the bits required to use it are on by default in an architecture. In such cases the difference between the two are still emitted to the assembler. gcc/ChangeLog: PR target/94396 * common/config/aarch64/aarch64-common.c (aarch64_get_extension_string_for_isa_flags): Handle default flags. gcc/testsuite/ChangeLog: PR target/94396 * gcc.target/aarch64/options_set_11.c: New test. * gcc.target/aarch64/options_set_12.c: New test. * gcc.target/aarch64/options_set_13.c: New test. * gcc.target/aarch64/options_set_14.c: New test. * gcc.target/aarch64/options_set_15.c: New test. * gcc.target/aarch64/options_set_16.c: New test. * gcc.target/aarch64/options_set_17.c: New test. * gcc.target/aarch64/options_set_18.c: New test. * gcc.target/aarch64/options_set_19.c: New test. * gcc.target/aarch64/options_set_20.c: New test. * gcc.target/aarch64/options_set_21.c: New test. * gcc.target/aarch64/options_set_22.c: New test. * gcc.target/aarch64/options_set_23.c: New test. * gcc.target/aarch64/options_set_24.c: New test. * gcc.target/aarch64/options_set_25.c: New test. * gcc.target/aarch64/options_set_26.c: New test. --- gcc/common/config/aarch64/aarch64-common.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'gcc/common') diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c index 8d24c14..0bddcc8 100644 --- a/gcc/common/config/aarch64/aarch64-common.c +++ b/gcc/common/config/aarch64/aarch64-common.c @@ -391,7 +391,22 @@ aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags, /* We remove all the dependent bits, to prevent them from being turned on twice. This only works because we assume that all there are individual options to set all bits standalone. */ - isa_flag_bits &= ~opt->flags_on; + + /* PR target/94396. + + For flags which would already imply a bit that's on by default (e.g + fp16fml which implies +fp,+fp16) we must emit the flags that are not + on by default. i.e. in Armv8.4-a +fp16fml is default if +fp16. So + if a user passes armv8.4-a+fp16 (or +fp16fml) then we need to emit + +fp16. But if +fp16fml is used in an architecture where it is + completely optional we only have to emit the canonical flag. */ + uint64_t toggle_bits = opt->flags_on & default_arch_flags; + /* Now check to see if the canonical flag is on by default. If it + is not then enabling it will enable all bits in flags_on. */ + if ((opt->flag_canonical & default_arch_flags) == 0) + toggle_bits = opt->flags_on; + + isa_flag_bits &= ~toggle_bits; isa_flag_bits |= opt->flag_canonical; } } -- cgit v1.1