From 3ea47ea1fcab95fd1b80acc724fdbb27fc436985 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 9 Jul 2024 15:50:57 +0800 Subject: RISC-V: Add SiFive extensions, xsfvcp and xsfcease We have already upstreamed these extensions into binutils, and now we need GCC to recognize these extensions and pass them to binutils as well. We also plan to upstream intrinsics in the near future. :) gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add xsfvcp. (riscv_ext_version_table): Add xsfvcp, xsfcease. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt (riscv_sifive_subext): New. (XSFVCP): New. (XSFCEASE): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-1.c: New. * gcc.target/riscv/predef-sf-2.c: New. --- gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'gcc/common') diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 3c4178c..d883efa 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] = {"ssstateen", "zicsr"}, {"sstc", "zicsr"}, + {"xsfvcp", "zve32x"}, + {NULL, NULL} }; @@ -415,6 +417,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1822,6 +1827,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, + {"xsfvcp", &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP}, + {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE}, + {NULL, NULL, 0} }; -- cgit v1.1