From 42b4e87d317377d6dcbb25ee2523da4a0c42478a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 14 Aug 2019 09:28:49 +0000 Subject: [AArch64] Add support for SVE absolute comparisons This patch adds support for floating-point absolute comparisons FACLT and FACLE (aliased as FACGT and FACGE with swapped operands). 2019-08-14 Richard Sandiford gcc/ * config/aarch64/iterators.md (SVE_COND_FP_ABS_CMP): New iterator. * config/aarch64/aarch64-sve.md (*aarch64_pred_fac): New pattern. gcc/testsuite/ * gcc.target/aarch64/sve/vcond_21.c: New test. * gcc.target/aarch64/sve/vcond_21_run.c: Likewise. From-SVN: r274443 --- gcc/ChangeLog | 6 +++ gcc/config/aarch64/aarch64-sve.md | 44 +++++++++++++++++++++- gcc/config/aarch64/iterators.md | 5 +++ gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.target/aarch64/sve/vcond_21.c | 34 +++++++++++++++++ .../gcc.target/aarch64/sve/vcond_21_run.c | 31 +++++++++++++++ 6 files changed, 123 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vcond_21.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vcond_21_run.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73156f1..401b2bc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,10 @@ 2019-08-14 Richard Sandiford + + * config/aarch64/iterators.md (SVE_COND_FP_ABS_CMP): New iterator. + * config/aarch64/aarch64-sve.md (*aarch64_pred_fac): + New pattern. + +2019-08-14 Richard Sandiford Kugan Vivekanandarajah * config/aarch64/aarch64-sve.md (*aarch64_sel_dup): New pattern. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index e12b5d9..b9ef8dd 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -94,7 +94,8 @@ ;; ---- [INT,FP] Compare and select ;; ---- [INT] Comparisons ;; ---- [INT] While tests -;; ---- [FP] Comparisons +;; ---- [FP] Direct comparisons +;; ---- [FP] Absolute comparisons ;; ---- [PRED] Test bits ;; ;; == Reductions @@ -3364,7 +3365,7 @@ ) ;; ------------------------------------------------------------------------- -;; ---- [FP] Comparisons +;; ---- [FP] Direct comparisons ;; ------------------------------------------------------------------------- ;; Includes: ;; - FCMEQ @@ -3474,6 +3475,45 @@ ) ;; ------------------------------------------------------------------------- +;; ---- [FP] Absolute comparisons +;; ------------------------------------------------------------------------- +;; Includes: +;; - FACGE +;; - FACGT +;; - FACLE +;; - FACLT +;; ------------------------------------------------------------------------- + +;; Predicated floating-point absolute comparisons. +(define_insn_and_rewrite "*aarch64_pred_fac" + [(set (match_operand: 0 "register_operand" "=Upa") + (unspec: + [(match_operand: 1 "register_operand" "Upl") + (match_operand:SI 4 "aarch64_sve_ptrue_flag") + (unspec:SVE_F + [(match_operand 5) + (match_operand:SI 6 "aarch64_sve_gp_strictness") + (match_operand:SVE_F 2 "register_operand" "w")] + UNSPEC_COND_FABS) + (unspec:SVE_F + [(match_operand 7) + (match_operand:SI 8 "aarch64_sve_gp_strictness") + (match_operand:SVE_F 3 "register_operand" "w")] + UNSPEC_COND_FABS)] + SVE_COND_FP_ABS_CMP))] + "TARGET_SVE + && aarch64_sve_pred_dominates_p (&operands[5], operands[1]) + && aarch64_sve_pred_dominates_p (&operands[7], operands[1])" + "fac\t%0., %1/z, %2., %3." + "&& (!rtx_equal_p (operands[1], operands[5]) + || !rtx_equal_p (operands[1], operands[7]))" + { + operands[5] = copy_rtx (operands[1]); + operands[7] = copy_rtx (operands[1]); + } +) + +;; ------------------------------------------------------------------------- ;; ---- [PRED] Test bits ;; ------------------------------------------------------------------------- ;; Includes: diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1654ffb..bc43f73 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1709,6 +1709,11 @@ UNSPEC_COND_FCMLT UNSPEC_COND_FCMNE]) +(define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE + UNSPEC_COND_FCMGT + UNSPEC_COND_FCMLE + UNSPEC_COND_FCMLT]) + (define_int_iterator FCADD [UNSPEC_FCADD90 UNSPEC_FCADD270]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index de09124..5f4332b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,9 @@ 2019-08-14 Richard Sandiford + + * gcc.target/aarch64/sve/vcond_21.c: New test. + * gcc.target/aarch64/sve/vcond_21_run.c: Likewise. + +2019-08-14 Richard Sandiford Kugan Vivekanandarajah * g++.target/aarch64/sve/dup_sel_1.C: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_21.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_21.c new file mode 100644 index 0000000..d5df2e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_21.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#define DEF_LOOP(TYPE, ABS, NAME, OP) \ + void \ + test_##TYPE##_##NAME (TYPE *restrict r, \ + TYPE *restrict a, \ + TYPE *restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = ABS (a[i]) OP ABS (b[i]) ? 1.0 : 0.0; \ + } + +#define TEST_TYPE(T, TYPE, ABS) \ + T (TYPE, ABS, lt, <) \ + T (TYPE, ABS, le, <=) \ + T (TYPE, ABS, ge, >=) \ + T (TYPE, ABS, gt, >) + +#define TEST_ALL(T) \ + TEST_TYPE (T, _Float16, __builtin_fabsf16) \ + TEST_TYPE (T, float, __builtin_fabsf) \ + TEST_TYPE (T, double, __builtin_fabs) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tfac[lg]t\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfac[lg]e\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfac[lg]t\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfac[lg]e\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfac[lg]t\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfac[lg]e\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_21_run.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_21_run.c new file mode 100644 index 0000000..15c5513 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_21_run.c @@ -0,0 +1,31 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "vcond_21.c" + +#define N 97 + +#define TEST_LOOP(TYPE, ABS, NAME, OP) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = i % 5 * (i & 1 ? -1 : 1); \ + b[i] = i % 9 * (i & 2 ? -1 : 1); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##NAME (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + { \ + if (r[i] != (ABS (a[i]) OP ABS (b[i]) ? 1.0 : 0.0)) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int __attribute__ ((optimize (1))) +main (int argc, char **argv) +{ + TEST_ALL (TEST_LOOP) + return 0; +} -- cgit v1.1