From 37317a1fc012ba4208a01d337864c579c55d3a3d Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Sun, 22 Jun 2014 19:21:08 +0200 Subject: rs6000: Merge the var_shift yes/no alternatives All instructions that are "var_shift" for some alternative have the shift amount as operands[2]. This patch introduces an attribute "maybe_var_shift". If that is set to "yes", the default value of "var_shift" is set based on the operands[2] value. With that, we can merge the var_shift yes/no cases everywhere. Do so. Also change some more "i" to "n". From-SVN: r211880 --- gcc/ChangeLog | 22 ++ gcc/config/rs6000/rs6000.md | 753 +++++++++++++++++++------------------------- 2 files changed, 354 insertions(+), 421 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d706772..5bc7bfc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,27 @@ 2014-06-22 Segher Boessenkool + * config/rs6000/rs6000.md (maybe_var_shift): New define_attr. + (var_shift): Use it. + (rotl3, *rotlsi3_64, *rotl3_dot, *rotl3_dot2, + *rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6, + *rotlsi3_internal8le, *rotlsi3_internal8be, *rotlsi3_internal9le, + *rotlsi3_internal9be, *rotlsi3_internal10le, *rotlsi3_internal10be, + *rotlsi3_internal11le, *rotlsi3_internal11be, *rotlsi3_internal12le, + *rotlsi3_internal12be, ashl3, *ashlsi3_64, *ashl3_dot, + *ashl3_dot2, lshr3, *lshrsi3_64, *lshr3_dot, + *lshr3_dot2, *ashr3, *ashrsi3_64, *ashr3_dot, + *ashr3_dot2, *rotldi3_internal4, *rotldi3_internal5, + *rotldi3_internal6, *rotldi3_internal7le, *rotldi3_internal7be, + *rotldi3_internal8le, *rotldi3_internal8be, *rotldi3_internal9le, + *rotldi3_internal9be, *rotldi3_internal10le, *rotldi3_internal10be, + *rotldi3_internal11le, *rotldi3_internal11be, *rotldi3_internal12le, + *rotldi3_internal12be, *rotldi3_internal13le, *rotldi3_internal13be, + *rotldi3_internal14le, *rotldi3_internal14be, *rotldi3_internal15le, + *rotldi3_internal15be): Use the new attribute. Merge register and + integer alternatives. + +2014-06-22 Segher Boessenkool + * config/rs6000/rs6000.md (ashrsi3, two anonymous define_insns and define_splits, ashrdi3, *ashrdi3_internal1, *ashrdi3_internal2 and split, *ashrdi3_internal3 and split): Delete, merge into... diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4d0b5ae..8e9039e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -205,9 +205,20 @@ (const_string "yes") (const_string "no"))) +;; Is this instruction using operands[2] as shift amount, and can that be a +;; register? +;; This is used for shift insns. +(define_attr "maybe_var_shift" "no,yes" (const_string "no")) + ;; Is this instruction using a shift amount from a register? ;; This is used for shift insns. -(define_attr "var_shift" "no,yes" (const_string "no")) +(define_attr "var_shift" "no,yes" + (if_then_else (and (eq_attr "type" "shift") + (eq_attr "maybe_var_shift" "yes")) + (if_then_else (match_operand 2 "gpc_reg_operand") + (const_string "yes") + (const_string "no")) + (const_string "no"))) ;; Define floating point instruction sub-types for use with Xfpu.md (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default")) @@ -3861,39 +3872,33 @@ (define_insn "rotl3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - rotl %0,%1,%2 - rotli %0,%1,%2" + "rotl%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - rotlw %0,%1,%2 - rotlwi %0,%1,%h2" + "rotlw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*rotl3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - rotl. %0,%1,%2 - rotli. %0,%1,%2 - # + rotl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -3904,23 +3909,21 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*rotl3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (rotate:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - rotl. %0,%1,%2 - rotli. %0,%1,%2 - # + rotl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -3931,41 +3934,37 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal4" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) - (match_operand:SI 3 "mask_operand" "n,n")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) + (match_operand:SI 3 "mask_operand" "n")))] "" - "@ - rlwnm %0,%1,%2,%m3,%M3 - rlwinm %0,%1,%h2,%m3,%M3" + "rlw%I2nm %0,%1,%h2,%m3,%M3" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:SI 3 "mask_operand" "n,n,n,n")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r,r,r"))] + (clobber (match_scratch:SI 4 "=r,r"))] "" "@ - rlwnm. %4,%1,%2,%m3,%M3 - rlwinm. %4,%1,%h2,%m3,%M3 - # + rlw%I2nm. %4,%1,%h2,%m3,%M3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -3986,24 +3985,22 @@ "") (define_insn "*rotlsi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:SI 3 "mask_operand" "n,n,n,n")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "@ - rlwnm. %0,%1,%2,%m3,%M3 - rlwinm. %0,%1,%h2,%m3,%M3 - # + rlw%I2nm. %0,%1,%h2,%m3,%M3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") @@ -4051,42 +4048,38 @@ (set_attr "type" "shift")]) (define_insn "*rotlsi3_internal8le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xff - rlwinm. %3,%1,%h2,0xff - # + rlw%I2nm. %3,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal8be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xff - rlwinm. %3,%1,%h2,0xff - # + rlw%I2nm. %3,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -4125,44 +4118,40 @@ "") (define_insn "*rotlsi3_internal9le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xff - rlwinm. %0,%1,%h2,0xff - # + rlw%I2nm. %0,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal9be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xff - rlwinm. %0,%1,%h2,0xff - # + rlw%I2nm. %0,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -4199,68 +4188,60 @@ "") (define_insn "*rotlsi3_internal10le" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))] "!BYTES_BIG_ENDIAN" - "@ - rlwnm %0,%1,%2,0xffff - rlwinm %0,%1,%h2,0xffff" + "rlw%I2nm %0,%1,%h2,0xffff" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal10be" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))] "BYTES_BIG_ENDIAN" - "@ - rlwnm %0,%1,%2,0xffff - rlwinm %0,%1,%h2,0xffff" + "rlw%I2nm %0,%1,%h2,0xffff" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal11le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xffff - rlwinm. %3,%1,%h2,0xffff - # + rlw%I2nm. %3,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal11be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xffff - rlwinm. %3,%1,%h2,0xffff - # + rlw%I2nm. %3,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -4299,44 +4280,40 @@ "") (define_insn "*rotlsi3_internal12le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xffff - rlwinm. %0,%1,%h2,0xffff - # + rlw%I2nm. %0,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal12be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xffff - rlwinm. %0,%1,%h2,0xffff - # + rlw%I2nm. %0,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -4374,39 +4351,33 @@ (define_insn "ashl3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sl %0,%1,%2 - sli %0,%1,%2" + "sl%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*ashlsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - slw %0,%1,%2 - slwi %0,%1,%h2" + "slw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*ashl3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sl. %0,%1,%2 - sli. %0,%1,%2 - # + sl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4417,23 +4388,21 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*ashl3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (ashift:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sl. %0,%1,%2 - sli. %0,%1,%2 - # + sl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4444,9 +4413,9 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "rlwinm" @@ -4527,39 +4496,33 @@ (define_insn "lshr3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sr %0,%1,%2 - sri %0,%1,%2" + "sr%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*lshrsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - srw %0,%1,%2 - srwi %0,%1,%h2" + "srw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*lshr3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sr. %0,%1,%2 - sri. %0,%1,%2 - # + sr%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4570,23 +4533,21 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*lshr3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (lshiftrt:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sr. %0,%1,%2 - sri. %0,%1,%2 - # + sr%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4597,9 +4558,9 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "" @@ -5030,39 +4991,33 @@ }) (define_insn "*ashr3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sra %0,%1,%2 - srai %0,%1,%2" + "sra%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*ashrsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI - (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - sraw %0,%1,%2 - srawi %0,%1,%h2" + "sraw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*ashr3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sra. %0,%1,%2 - srai. %0,%1,%2 - # + sra%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -5073,23 +5028,21 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*ashr3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (ashiftrt:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sra. %0,%1,%2 - srai. %0,%1,%2 - # + sra%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -5100,9 +5053,9 @@ (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions @@ -6962,35 +6915,31 @@ }) (define_insn "*rotldi3_internal4" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) - (match_operand:DI 3 "mask64_operand" "n,n")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) + (match_operand:DI 3 "mask64_operand" "n")))] "TARGET_POWERPC64" - "@ - rldc%B3 %0,%1,%2,%S3 - rldic%B3 %0,%1,%H2,%S3" + "rld%I2c%B3 %0,%1,%H2,%S3" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:DI 3 "mask64_operand" "n,n,n,n")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:DI 4 "=r,r,r,r"))] + (clobber (match_scratch:DI 4 "=r,r"))] "TARGET_64BIT" "@ - rldc%B3. %4,%1,%2,%S3 - rldic%B3. %4,%1,%H2,%S3 - # + rld%I2c%B3. %4,%1,%H2,%S3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7011,24 +6960,22 @@ "") (define_insn "*rotldi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:DI 3 "mask64_operand" "n,n,n,n")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_64BIT" "@ - rldc%B3. %0,%1,%2,%S3 - rldic%B3. %0,%1,%H2,%S3 - # + rld%I2c%B3. %0,%1,%H2,%S3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") @@ -7048,68 +6995,60 @@ "") (define_insn "*rotldi3_internal7le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,56 - rldicl %0,%1,%H2,56" + "rld%I2cl %0,%1,%H2,56" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal7be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,56 - rldicl %0,%1,%H2,56" + "rld%I2cl %0,%1,%H2,56" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal8le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,56 - rldicl. %3,%1,%H2,56 - # + rld%I2cl. %3,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal8be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,56 - rldicl. %3,%1,%H2,56 - # + rld%I2cl. %3,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7148,44 +7087,40 @@ "") (define_insn "*rotldi3_internal9le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,56 - rldicl. %0,%1,%H2,56 - # + rld%I2cl. %0,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal9be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,56 - rldicl. %0,%1,%H2,56 - # + rld%I2cl. %0,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -7222,68 +7157,60 @@ "") (define_insn "*rotldi3_internal10le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,48 - rldicl %0,%1,%H2,48" + "rld%I2cl %0,%1,%H2,48" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal10be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,48 - rldicl %0,%1,%H2,48" + "rld%I2cl %0,%1,%H2,48" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal11le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,48 - rldicl. %3,%1,%H2,48 - # + rld%I2cl. %3,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal11be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,48 - rldicl. %3,%1,%H2,48 - # + rld%I2cl. %3,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7322,44 +7249,40 @@ "") (define_insn "*rotldi3_internal12le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,48 - rldicl. %0,%1,%H2,48 - # + rld%I2cl. %0,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal12be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,48 - rldicl. %0,%1,%H2,48 - # + rld%I2cl. %0,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -7396,68 +7319,60 @@ "") (define_insn "*rotldi3_internal13le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,32 - rldicl %0,%1,%H2,32" + "rld%I2cl %0,%1,%H2,32" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal13be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,32 - rldicl %0,%1,%H2,32" + "rld%I2cl %0,%1,%H2,32" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal14le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,32 - rldicl. %3,%1,%H2,32 - # + rld%I2cl. %3,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal14be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,32 - rldicl. %3,%1,%H2,32 - # + rld%I2cl. %3,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7496,44 +7411,40 @@ "") (define_insn "*rotldi3_internal15le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,32 - rldicl. %0,%1,%H2,32 - # + rld%I2cl. %0,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal15be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,32 - rldicl. %0,%1,%H2,32 - # + rld%I2cl. %0,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") -- cgit v1.1