From 077dab3b42f3fa59a1bf227a7a2041adab8ef3f5 Mon Sep 17 00:00:00 2001 From: Hartmut Penner Date: Wed, 15 Jan 2003 10:38:01 +0000 Subject: s390.c (s390_safe_attr_type): New function. * config/s390/s390.c (s390_safe_attr_type): New function. (s390_use_dfa_pipeline_interface): New function, return true for z900. (s390_issue_rate): New function. (s390_agen_dep_p): New function. (addr_generation_dependency_p): Use 's390_safe_attr_type'. (s390_adjust_cost): Return 'cost' if new DFA is used. (s390_adjust_priority): Delete function. * config/s390/s390-protos.h: (s390_agen_dep_p): New prototype. * config/s390/s390.md (atype attribute): Attribute 'atype' default determined by 'op_type'. (type attribute): Added more type attributes. * config/s390/2064.md: New DFA description for z900 pipeline. From-SVN: r61321 --- gcc/ChangeLog | 18 +- gcc/config/s390/2064.md | 131 +++++++ gcc/config/s390/s390-protos.h | 2 + gcc/config/s390/s390.c | 151 ++++---- gcc/config/s390/s390.md | 827 +++++++++++++++++++----------------------- 5 files changed, 607 insertions(+), 522 deletions(-) create mode 100644 gcc/config/s390/2064.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f3184bd..224f08d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,8 +1,20 @@ +2003-01-15 Hartmut Penner + + * config/s390/s390.c (s390_safe_attr_type): New function. + (s390_use_dfa_pipeline_interface): New function, return true for z900. + (s390_issue_rate): New function. + (s390_agen_dep_p): New function. + (addr_generation_dependency_p): Use 's390_safe_attr_type'. + (s390_adjust_cost): Return 'cost' if new DFA is used. + (s390_adjust_priority): Delete function. + * config/s390/s390-protos.h: (s390_agen_dep_p): New prototype. + * config/s390/s390.md (atype attribute): Attribute 'atype' default + determined by 'op_type'. + (type attribute): Added more type attributes. + * config/s390/2064.md: New DFA description for z900 pipeline. + 2003-01-15 Alexandre Oliva - * config/i386/i386.c (ix86_expand_vector_move): Validize constant - forced to memory. Fixes PR bootstrap/9036. - * config/mips/mips.h (CRT_CALL_STATIC_FUNCTION): Define so as to set $gp before the call. diff --git a/gcc/config/s390/2064.md b/gcc/config/s390/2064.md new file mode 100644 index 0000000..a4296c0 --- /dev/null +++ b/gcc/config/s390/2064.md @@ -0,0 +1,131 @@ +;; Scheduling description for z900 (cpu 2064). +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and +;; Ulrich Weigand (uweigand@de.ibm.com). +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; +;; References: +;; The microarchitecture of the IBM eServer z900 processor. +;; E.M. Schwarz et al. +;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. +;; +;; z900 (cpu 2064) pipeline +;; +;; dec +;; --> | <--- +;; LA bypass | agen | +;; | | | +;; --- c1 | Load bypass +;; | | +;; c2---- +;; | +;; e1 +;; | +;; wr + +(define_automaton "z_ipu") +(define_cpu_unit "z_e1" "z_ipu") +(define_cpu_unit "z_wr" "z_ipu") + + +(define_insn_reservation "z_la" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "la")) + "z_e1,z_wr") + +(define_insn_reservation "z_larl" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "larl")) + "z_e1,z_wr") + +(define_insn_reservation "z_load" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "load")) + "z_e1,z_wr") + +(define_insn_reservation "z_store" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "store")) + "z_e1,z_wr") + +(define_insn_reservation "z_call" 5 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "jsr")) + "z_e1*5,z_wr") + +(define_insn_reservation "z_o2" 2 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "o2")) + "z_e1*2,z_wr") + +(define_insn_reservation "z_o3" 3 + (and (eq_attr "cpu" "z900") + (eq_attr "type" "o3")) + "z_e1*3,z_wr") + +; +; Insn still not mentioned are check for +; the usage of the agen unit +; + +(define_insn_reservation "z_int" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "atype" "reg")) + "z_e1,z_wr") + +(define_insn_reservation "z_agen" 1 + (and (eq_attr "cpu" "z900") + (eq_attr "atype" "agen")) + "z_e1,z_wr") + + +;; +;; s390_agen_dep_p returns 1, if a register is set in the +;; first insn and used in the dependend insn to form a address. +;; + +;; +;; If a intruction uses a register to address memory, it needs +;; to be set 5 cycles in advance. +;; + +(define_bypass 5 "z_int,z_agen" + "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") + +;; +;; A load type instruction uses a bypass to feed the result back +;; to the address generation pipeline stage. +;; + +(define_bypass 2 "z_load" + "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") + +;; +;; A load address type instruction uses a bypass to feed the +;; result back to the address generation pipeline stage. +;; + +(define_bypass 1 "z_larl,z_la" + "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") + + + + + diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h index deecef6..6416809 100644 --- a/gcc/config/s390/s390-protos.h +++ b/gcc/config/s390/s390-protos.h @@ -76,6 +76,8 @@ extern void s390_initialize_trampoline PARAMS ((rtx, rtx, rtx)); extern rtx s390_gen_rtx_const_DI PARAMS ((int, int)); extern rtx s390_simplify_dwarf_addr PARAMS ((rtx)); extern void s390_machine_dependent_reorg PARAMS ((rtx)); +extern int s390_agen_dep_p PARAMS ((rtx, rtx)); + #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 25956ec..c80bcc8 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -51,13 +51,17 @@ Boston, MA 02111-1307, USA. */ #include "optabs.h" static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int)); -static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int)); -static int s390_adjust_priority PARAMS ((rtx, int)); static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx, unsigned HOST_WIDE_INT)); static void s390_encode_section_info PARAMS ((tree, int)); static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree)); +static enum attr_type s390_safe_attr_type PARAMS ((rtx)); + +static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int)); +static int s390_issue_rate PARAMS ((void)); +static int s390_use_dfa_pipeline_interface PARAMS ((void)); + #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" @@ -75,12 +79,6 @@ static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, #undef TARGET_ASM_SELECT_RTX_SECTION #define TARGET_ASM_SELECT_RTX_SECTION s390_select_rtx_section -#undef TARGET_SCHED_ADJUST_COST -#define TARGET_SCHED_ADJUST_COST s390_adjust_cost - -#undef TARGET_SCHED_ADJUST_PRIORITY -#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority - #undef TARGET_ENCODE_SECTION_INFO #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info @@ -89,6 +87,14 @@ static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true +#undef TARGET_SCHED_ADJUST_COST +#define TARGET_SCHED_ADJUST_COST s390_adjust_cost +#undef TARGET_SCHED_ISSUE_RATE +#define TARGET_SCHED_ISSUE_RATE s390_issue_rate +#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE +#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE s390_use_dfa_pipeline_interface + + struct gcc_target targetm = TARGET_INITIALIZER; extern int reload_completed; @@ -936,6 +942,17 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = ADDR_REGS, NO_REGS, ADDR_REGS }; +/* Return attribute type of insn. */ + +static enum attr_type +s390_safe_attr_type (insn) + rtx insn; +{ + if (recog_memoized (insn) >= 0) + return get_attr_type (insn); + else + return TYPE_NONE; +} /* Return true if OP a (const_int 0) operand. OP is the current operation. @@ -2892,9 +2909,6 @@ s390_assemble_integer (x, size, aligned_p) return default_assemble_integer (x, size, aligned_p); } - -#define DEBUG_SCHED 0 - /* Returns true if register REGNO is used for forming a memory address in expression X. */ @@ -2946,6 +2960,9 @@ addr_generation_dependency_p (dep_rtx, insn) { rtx target, pat; + if (GET_CODE (dep_rtx) == INSN) + dep_rtx = PATTERN (dep_rtx); + if (GET_CODE (dep_rtx) == SET) { target = SET_DEST (dep_rtx); @@ -2958,7 +2975,7 @@ addr_generation_dependency_p (dep_rtx, insn) { int regno = REGNO (target); - if (get_attr_type (insn) == TYPE_LA) + if (s390_safe_attr_type (insn) == TYPE_LA) { pat = PATTERN (insn); if (GET_CODE (pat) == PARALLEL) @@ -2972,13 +2989,38 @@ addr_generation_dependency_p (dep_rtx, insn) else abort(); } - else if (get_attr_atype (insn) == ATYPE_MEM) + else if (get_attr_atype (insn) == ATYPE_AGEN) return reg_used_in_mem_p (regno, PATTERN (insn)); } } return 0; } +/* Return 1, if dep_insn sets register used in insn in the agen unit. */ + + +int +s390_agen_dep_p(dep_insn, insn) + rtx dep_insn; + rtx insn; +{ + rtx dep_rtx = PATTERN (dep_insn); + int i; + + if (GET_CODE (dep_rtx) == SET + && addr_generation_dependency_p (dep_rtx, insn)) + return 1; + else if (GET_CODE (dep_rtx) == PARALLEL) + { + for (i = 0; i < XVECLEN (dep_rtx, 0); i++) + { + if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) + return 1; + } + } + return 0; +} + /* Return the modified cost of the dependency of instruction INSN on instruction DEP_INSN through the link LINK. COST is the @@ -3012,88 +3054,47 @@ s390_adjust_cost (insn, link, dep_insn, cost) if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) return cost; + /* DFA based scheduling checks address dependency in md file. */ + if (s390_use_dfa_pipeline_interface ()) + return cost; + dep_rtx = PATTERN (dep_insn); - if (GET_CODE (dep_rtx) == SET) - { - if (addr_generation_dependency_p (dep_rtx, insn)) - { - cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; - if (DEBUG_SCHED) - { - fprintf (stderr, "\n\nAddress dependency detected: cost %d\n", - cost); - debug_rtx (dep_insn); - debug_rtx (insn); - } - } - } + if (GET_CODE (dep_rtx) == SET + && addr_generation_dependency_p (dep_rtx, insn)) + cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; else if (GET_CODE (dep_rtx) == PARALLEL) { for (i = 0; i < XVECLEN (dep_rtx, 0); i++) { - if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), - insn)) - { - cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; - if (DEBUG_SCHED) - { - fprintf (stderr, "\n\nAddress dependency detected: cost %d\n" - ,cost); - debug_rtx (dep_insn); - debug_rtx (insn); - } - } + if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) + cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; } } return cost; } +/* The number of instructions that can be issued per cycle. */ -/* A C statement (sans semicolon) to update the integer scheduling priority - INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, - increase the priority to execute INSN later. Do not define this macro if - you do not need to adjust the scheduling priorities of insns. +static int +s390_issue_rate () +{ + return 1; +} - A LA instruction maybe scheduled later, since the pipeline bypasses the - calculated value. */ +/* If the following function returns TRUE, we will use the the DFA + insn scheduler. */ static int -s390_adjust_priority (insn, priority) - rtx insn ATTRIBUTE_UNUSED; - int priority; +s390_use_dfa_pipeline_interface () { - if (! INSN_P (insn)) - return priority; + if (s390_cpu == PROCESSOR_2064_Z900) + return 1; + return 0; - if (GET_CODE (PATTERN (insn)) == USE - || GET_CODE (PATTERN (insn)) == CLOBBER) - return priority; - - switch (get_attr_type (insn)) - { - default: - break; - - case TYPE_LA: - if (priority >= 0 && priority < 0x01000000) - priority <<= 3; - break; - case TYPE_LM: - /* LM in epilogue should never be scheduled. This - is due to literal access done in function body. - The usage of register 13 is not mentioned explicitly, - leading to scheduling 'LM' accross this instructions. - */ - priority = 0x7fffffff; - break; - } - - return priority; } - /* Split all branches that exceed the maximum distance. Returns true if this created a new literal pool entry. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 7490fab..480d152 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3,7 +3,7 @@ ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). ;; This file is part of GNU CC. - + ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) @@ -53,15 +53,41 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3" - (const_string "integer")) +(define_attr "type" "none,integer,load,lr,la,larl,lm,stm, + cs,vs,store,imul,idiv, + branch,jsr,fsimpd,fsimps, + floadd,floads,fstored, fstores, + fmuld,fmuls,fdivd,fdivs, + ftoi,itof,fsqrtd,fsqrts, + other,o2,o3" + (const_string "integer")) -;; Insn are devide in two classes: -;; mem: Insn accessing memory -;; reg: Insn operands all in registers +;; Operand type. Used to default length attribute values -(define_attr "atype" "reg,mem" - (const_string "reg")) +(define_attr "op_type" + "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" + (const_string "RX")) + +;; Insn are devide in two classes: +;; agen: Insn using agen +;; reg: Insn not using agen + +(define_attr "atype" "agen,reg" +(cond [ (eq_attr "op_type" "E") (const_string "reg") + (eq_attr "op_type" "RR") (const_string "reg") + (eq_attr "op_type" "RX") (const_string "agen") + (eq_attr "op_type" "RI") (const_string "reg") + (eq_attr "op_type" "RRE") (const_string "reg") + (eq_attr "op_type" "RS") (const_string "agen") + (eq_attr "op_type" "RSI") (const_string "agen") + (eq_attr "op_type" "S") (const_string "agen") + (eq_attr "op_type" "SI") (const_string "agen") + (eq_attr "op_type" "SS") (const_string "agen") + (eq_attr "op_type" "SSE") (const_string "agen") + (eq_attr "op_type" "RXE") (const_string "agen") + (eq_attr "op_type" "RSE") (const_string "agen") + (eq_attr "op_type" "RIL") (const_string "agen")] + (const_string "reg"))) ;; Generic pipeline function unit. @@ -72,18 +98,42 @@ (eq_attr "type" "integer") 1 1) (define_function_unit "integer" 1 0 + (eq_attr "type" "fsimpd") 1 1) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fsimps") 1 1) + +(define_function_unit "integer" 1 0 (eq_attr "type" "load") 1 1) (define_function_unit "integer" 1 0 + (eq_attr "type" "floadd") 1 1) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "floads") 1 1) + +(define_function_unit "integer" 1 0 (eq_attr "type" "la") 1 1) (define_function_unit "integer" 1 0 + (eq_attr "type" "larl") 1 1) + +(define_function_unit "integer" 1 0 (eq_attr "type" "lr") 1 1) (define_function_unit "integer" 1 0 + (eq_attr "type" "branch") 1 1) + +(define_function_unit "integer" 1 0 (eq_attr "type" "store") 1 1) (define_function_unit "integer" 1 0 + (eq_attr "type" "fstored") 1 1) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fstores") 1 1) + +(define_function_unit "integer" 1 0 (eq_attr "type" "lm") 2 2) (define_function_unit "integer" 1 0 @@ -102,13 +152,31 @@ (eq_attr "type" "imul") 7 7) (define_function_unit "integer" 1 0 - (eq_attr "type" "fmul") 6 6) + (eq_attr "type" "fmuld") 6 6) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fmuls") 6 6) (define_function_unit "integer" 1 0 (eq_attr "type" "idiv") 33 33) (define_function_unit "integer" 1 0 - (eq_attr "type" "fdiv") 33 33) + (eq_attr "type" "fdivd") 33 33) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fdivs") 33 33) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fsqrtd") 30 30) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fsqrts") 30 30) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "ftoi") 2 2) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "itof") 2 2) (define_function_unit "integer" 1 0 (eq_attr "type" "o2") 2 2) @@ -119,11 +187,9 @@ (define_function_unit "integer" 1 0 (eq_attr "type" "other") 5 5) -;; Operand type. Used to default length attribute values +;; Pipeline description for z900 -(define_attr "op_type" - "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" - (const_string "RX")) +(include "2064.md") ;; Length in bytes. @@ -135,7 +201,6 @@ (eq_attr "op_type" "RRE") (const_int 4) (eq_attr "op_type" "RS") (const_int 4) (eq_attr "op_type" "RSI") (const_int 4) - (eq_attr "op_type" "RX") (const_int 4) (eq_attr "op_type" "S") (const_int 4) (eq_attr "op_type" "SI") (const_int 4) (eq_attr "op_type" "SS") (const_int 6) @@ -298,8 +363,7 @@ operands[2] = GEN_INT (block << shift); return \"tm\\t%0,%b2\"; }" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) ; Test-under-Mask instructions @@ -320,8 +384,7 @@ plus_constant (XEXP (operands[0], 0), part)); return \"tm\\t%0,%b1\"; }" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) (define_insn "*tmsi_mem" [(set (reg 33) @@ -339,8 +402,7 @@ plus_constant (XEXP (operands[0], 0), part)); return \"tm\\t%0,%b1\"; }" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) (define_insn "*tmhi_mem" [(set (reg 33) @@ -358,8 +420,7 @@ plus_constant (XEXP (operands[0], 0), part)); return \"tm\\t%0,%b1\"; }" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) (define_insn "*tmqi_mem" [(set (reg 33) @@ -368,8 +429,7 @@ (match_operand:SI 2 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" "tm\\t%0,%b1" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) (define_insn "*tmdi_reg" [(set (reg 33) @@ -470,7 +530,9 @@ (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" "srda\\t%0,0" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) + (define_insn "*tstsi" [(set (reg 33) @@ -482,8 +544,7 @@ "@ ltr\\t%2,%0 icm\\t%2,15,%0" - [(set_attr "op_type" "RR,RS") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RS")]) (define_insn "*tstsi_cconly" [(set (reg 33) @@ -494,8 +555,7 @@ "@ ltr\\t%0,%0 icm\\t%2,15,%0" - [(set_attr "op_type" "RR,RS") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RS")]) (define_insn "*tstsi_cconly2" [(set (reg 33) @@ -515,8 +575,7 @@ "@ icm\\t%2,3,%0 tml\\t%0,65535" - [(set_attr "op_type" "RS,RI") - (set_attr "atype" "mem,reg")]) + [(set_attr "op_type" "RS,RI")]) (define_insn "*tsthiCCT_cconly" [(set (reg 33) @@ -527,8 +586,7 @@ "@ icm\\t%2,3,%0 tml\\t%0,65535" - [(set_attr "op_type" "RS,RI") - (set_attr "atype" "mem,reg")]) + [(set_attr "op_type" "RS,RI")]) (define_insn "*tsthi" [(set (reg 33) @@ -538,8 +596,7 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,3,%0" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*tsthi_cconly" [(set (reg 33) @@ -548,8 +605,7 @@ (clobber (match_scratch:HI 2 "=d"))] "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,3,%0" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*tstqiCCT" [(set (reg 33) @@ -561,8 +617,7 @@ "@ icm\\t%2,1,%0 tml\\t%0,255" - [(set_attr "op_type" "RS,RI") - (set_attr "atype" "mem,reg")]) + [(set_attr "op_type" "RS,RI")]) (define_insn "*tstqiCCT_cconly" [(set (reg 33) @@ -572,8 +627,7 @@ "@ cli\\t%0,0 tml\\t%0,255" - [(set_attr "op_type" "SI,RI") - (set_attr "atype" "mem,reg")]) + [(set_attr "op_type" "SI,RI")]) (define_insn "*tstqi" [(set (reg 33) @@ -583,8 +637,7 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,1,%0" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*tstqi_cconly" [(set (reg 33) @@ -593,9 +646,7 @@ (clobber (match_scratch:QI 2 "=d"))] "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,1,%0" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) - + [(set_attr "op_type" "RS")]) ; Compare (signed) instructions @@ -607,8 +658,7 @@ "@ cgfr\\t%0,%1 cgf\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*cmpdi_ccs" [(set (reg 33) @@ -619,8 +669,7 @@ cgr\\t%0,%1 cghi\\t%0,%c1 cg\\t%0,%1" - [(set_attr "op_type" "RRE,RI,RXE") - (set_attr "atype" "reg,reg,mem")]) + [(set_attr "op_type" "RRE,RI,RXE")]) (define_insn "*cmpsi_ccs_sign" [(set (reg 33) @@ -628,8 +677,7 @@ (match_operand:SI 0 "register_operand" "d")))] "s390_match_ccmode(insn, CCSRmode)" "ch\\t%0,%1" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) (define_insn "*cmpsi_ccs" [(set (reg 33) @@ -640,8 +688,7 @@ cr\\t%0,%1 chi\\t%0,%c1 c\\t%0,%1" - [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem")]) + [(set_attr "op_type" "RR,RI,RX")]) ; Compare (unsigned) instructions @@ -654,8 +701,7 @@ "@ clgfr\\t%0,%1 clgf\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*cmpdi_ccu" [(set (reg 33) @@ -665,8 +711,7 @@ "@ clgr\\t%0,%1 clg\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*cmpsi_ccu" [(set (reg 33) @@ -676,8 +721,7 @@ "@ clr\\t%0,%1 cl\\t%0,%1" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*cmphi_ccu" [(set (reg 33) @@ -685,8 +729,7 @@ (match_operand:HI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clm\\t%0,3,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*cmpqi_ccu" [(set (reg 33) @@ -694,8 +737,7 @@ (match_operand:QI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clm\\t%0,1,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*cli" [(set (reg 33) @@ -703,8 +745,7 @@ (match_operand:QI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, CCUmode)" "cli\\t%0,%b1" - [(set_attr "op_type" "SI") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI")]) (define_insn "*cmpdi_ccu_mem" [(set (reg 33) @@ -712,8 +753,7 @@ (match_operand:DI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*cmpsi_ccu_mem" [(set (reg 33) @@ -721,8 +761,7 @@ (match_operand:SI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*cmphi_ccu_mem" [(set (reg 33) @@ -730,8 +769,7 @@ (match_operand:HI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*cmpqi_ccu_mem" [(set (reg 33) @@ -739,8 +777,7 @@ (match_operand:QI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; DF instructions @@ -751,7 +788,8 @@ (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "ltdbr\\t%0,%0" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimpd")]) (define_insn "*cmpdf_ccs_0_ibm" [(set (reg 33) @@ -759,7 +797,8 @@ (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "ltdr\\t%0,%0" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimpd")]) (define_insn "*cmpdf_ccs" [(set (reg 33) @@ -770,7 +809,7 @@ cdbr\\t%0,%1 cdb\\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd")]) (define_insn "*cmpdf_ccs_ibm" [(set (reg 33) @@ -781,7 +820,7 @@ cdr\\t%0,%1 cd\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd")]) ; SF instructions @@ -792,7 +831,8 @@ (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "ltebr\\t%0,%0" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimps")]) (define_insn "*cmpsf_ccs_0_ibm" [(set (reg 33) @@ -800,7 +840,8 @@ (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lter\\t%0,%0" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimps")]) (define_insn "*cmpsf_ccs" [(set (reg 33) @@ -810,8 +851,8 @@ "@ cebr\\t%0,%1 ceb\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps")]) (define_insn "*cmpsf_ccs" [(set (reg 33) @@ -821,8 +862,8 @@ "@ cer\\t%0,%1 ce\\t%0,%1" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX") + (set_attr "type" "fsimps")]) ;; @@ -843,8 +884,7 @@ # # mvc\\t%O0(16,%R0),%1" - [(set_attr "op_type" "RSE,RSE,NN,NN,SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RSE,RSE,NN,NN,SS")]) (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") @@ -928,8 +968,7 @@ && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') && !FP_REG_P (operands[0])" "lghi\\t%0,%h1" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "*movdi_lli" [(set (match_operand:DI 0 "register_operand" "=d") @@ -950,8 +989,7 @@ default: abort (); } }" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "*movdi_larl" [(set (match_operand:DI 0 "register_operand" "=d") @@ -960,8 +998,7 @@ && !FP_REG_P (operands[0])" "larl\\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "atype" "reg") - (set_attr "type" "la")]) + (set_attr "type" "larl")]) (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q") @@ -976,7 +1013,7 @@ std\\t%1,%0 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS") - (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) + (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")]) (define_insn "*movdi_31" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q") @@ -992,7 +1029,7 @@ std\\t%1,%0 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS") - (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")]) + (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")]) (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") @@ -1138,7 +1175,7 @@ ste\\t%1,%0 mvc\\t%O0(4,%R0),%1" [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") - (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) + (set_attr "type" "lr,load,store,floads,floads,fstores,cs")]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -1165,8 +1202,7 @@ lh\\t%0,%1 sth\\t%1,%0 mvc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "RR,RI,RX,RX,SS") - (set_attr "atype" "reg,reg,mem,mem,mem")]) + [(set_attr "op_type" "RR,RI,RX,RX,SS")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") @@ -1194,8 +1230,7 @@ mvi\\t%0,%b1 mvc\\t%O0(1,%R0),%1" [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS") - (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) - + (set_attr "type" "lr,*,*,store,store,cs")]) (define_insn "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q") @@ -1208,8 +1243,7 @@ stc\\t%1,%0 mvi\\t%0,%b1 mvc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "RR,RI,RX,RX,SI,SS") - (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) + [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") @@ -1230,8 +1264,7 @@ (match_operand:QI 1 "memory_operand" "m"))] "" "ic\\t%0,%1" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) ; ; movstricthi instruction pattern(s). @@ -1243,8 +1276,7 @@ (clobber (reg:CC 33))] "" "icm\\t%0,3,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) ; @@ -1259,7 +1291,7 @@ lr\\t%0,%1 l\\t%0,%1" [(set_attr "op_type" "RR,RS") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "lr,load")]) ; @@ -1292,7 +1324,7 @@ stg\\t%1,%0 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS") - (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) + (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")]) (define_insn "*movdf_31" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q") @@ -1308,7 +1340,7 @@ # mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS") - (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")]) + (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")]) (define_split [(set (match_operand:DF 0 "nonimmediate_operand" "") @@ -1392,7 +1424,7 @@ st\\t%1,%0 mvc\\t%O0(4,%R0),%1" [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") - (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) + (set_attr "type" "floads,floads,fstores,lr,load,store,cs")]) ; ; load_multiple pattern(s). @@ -1474,7 +1506,6 @@ return \"lmg\\t%1,%0,%2\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") (set_attr "type" "lm")]) (define_insn "*load_multiple_si" @@ -1493,7 +1524,6 @@ return \"lm\\t%1,%0,%2\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") (set_attr "type" "lm")]) ; @@ -1578,7 +1608,6 @@ return \"stmg\\t%2,%0,%1\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") (set_attr "type" "stm")]) @@ -1598,7 +1627,6 @@ return \"stm\\t%2,%0,%1\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") (set_attr "type" "stm")]) ;; @@ -1652,7 +1680,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) (define_insn "movstr_short_31" @@ -1679,7 +1707,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) ; Move a block of arbitrary length. @@ -1700,7 +1728,6 @@ "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") - (set_attr "atype" "mem") (set_attr "length" "8")]) (define_insn "movstr_long_31" @@ -1719,7 +1746,6 @@ "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") - (set_attr "atype" "mem") (set_attr "length" "8")]) ; @@ -1770,7 +1796,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) (define_insn "clrstr_short_31" @@ -1798,7 +1824,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) ; Clear a block of arbitrary length. @@ -1815,7 +1841,6 @@ "TARGET_64BIT" "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") - (set_attr "atype" "mem") (set_attr "type" "vs") (set_attr "length" "8")]) @@ -1831,7 +1856,6 @@ "!TARGET_64BIT" "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") - (set_attr "atype" "mem") (set_attr "type" "vs") (set_attr "length" "8")]) @@ -1887,7 +1911,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) (define_insn "cmpstr_short_31" @@ -1915,7 +1939,7 @@ }" [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") - (set_attr "atype" "mem,mem") + (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) ; Compare a block of arbitrary length. @@ -1931,7 +1955,6 @@ "TARGET_64BIT" "clcl\\t%0,%1" [(set_attr "op_type" "RR") - (set_attr "atype" "mem") (set_attr "type" "vs")]) (define_insn "cmpstr_long_31" @@ -1945,7 +1968,6 @@ "!TARGET_64BIT" "clcl\\t%0,%1" [(set_attr "op_type" "RR") - (set_attr "atype" "mem") (set_attr "type" "vs")]) ; Convert condition code to integer in range (-1, 0, 1) @@ -1964,7 +1986,6 @@ }" [(set_attr "op_type" "NN") (set_attr "length" "16") - (set_attr "atype" "reg") (set_attr "type" "other")]) (define_insn "cmpint_di" @@ -1981,7 +2002,6 @@ }" [(set_attr "op_type" "NN") (set_attr "length" "22") - (set_attr "atype" "reg") (set_attr "type" "other")]) @@ -1995,8 +2015,7 @@ (clobber (reg:CC 33))] "" "icm\\t%0,8,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*sethighhisi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2004,8 +2023,7 @@ (clobber (reg:CC 33))] "" "icm\\t%0,12,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn "*sethighqidi_64" [(set (match_operand:DI 0 "register_operand" "=d") @@ -2013,8 +2031,7 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "icmh\\t%0,8,%1" - [(set_attr "op_type" "RSE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RSE")]) (define_insn "*sethighqidi_31" [(set (match_operand:DI 0 "register_operand" "=d") @@ -2022,8 +2039,7 @@ (clobber (reg:CC 33))] "!TARGET_64BIT" "icm\\t%0,8,%1" - [(set_attr "op_type" "RS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RS")]) (define_insn_and_split "*extractqi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2045,7 +2061,7 @@ operands[1] = change_address (operands[1], QImode, 0); }" [(set_attr "type" "o2") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn_and_split "*extracthi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2067,7 +2083,7 @@ operands[1] = change_address (operands[1], HImode, 0); }" [(set_attr "type" "o2") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) ; ; extendsidi2 instruction pattern(s). @@ -2097,8 +2113,7 @@ "@ lgfr\\t%0,%1 lgf\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) ; ; extendhidi2 instruction pattern(s). @@ -2132,8 +2147,7 @@ (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" "lgh\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) ; ; extendqidi2 instruction pattern(s). @@ -2196,8 +2210,7 @@ (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" "lh\\t%0,%1" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) ; ; extendqisi2 instruction pattern(s). @@ -2260,8 +2273,7 @@ "@ llgfr\\t%0,%1 llgf\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) ; ; zero_extendhidi2 instruction pattern(s). @@ -2295,8 +2307,7 @@ (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" "llgh\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) ; ; zero_extendqidi2 instruction pattern(s) @@ -2330,8 +2341,7 @@ (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_64BIT" "llgc\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) ; ; zero_extendhisi2 instruction pattern(s). @@ -2354,8 +2364,7 @@ (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" "llgh\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") @@ -2370,7 +2379,7 @@ (clobber (reg:CC 33))])] "operands[2] = gen_lowpart (HImode, operands[0]);" [(set_attr "type" "o2") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) ; ; zero_extendqisi2 instruction pattern(s). @@ -2393,8 +2402,7 @@ (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_64BIT" "llgc\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") @@ -2406,7 +2414,7 @@ (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);" [(set_attr "type" "o2") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) ; ; zero_extendqihi2 instruction pattern(s). @@ -2429,8 +2437,7 @@ (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_64BIT" "llgc\\t%0,%1" - [(set_attr "op_type" "RXE") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RXE")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") @@ -2442,7 +2449,7 @@ (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);" [(set_attr "type" "o2") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) ; @@ -2495,7 +2502,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cgdbr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other")]) + (set_attr "type" "ftoi")]) ; ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). @@ -2582,7 +2589,8 @@ return \"l\\t%0,%N4\"; }" [(set_attr "op_type" "NN") - (set_attr "type" "other") + (set_attr "type" "ftoi") + (set_attr "atype" "agen") (set_attr "length" "20")]) ; @@ -2636,7 +2644,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cgebr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other")]) + (set_attr "type" "ftoi")]) ; ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). @@ -2699,7 +2707,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cfebr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other")]) + (set_attr "type" "ftoi")]) ; ; floatdidf2 instruction pattern(s). @@ -2725,7 +2733,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cegbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other" )]) + (set_attr "type" "itof" )]) ; ; floatsidf2 instruction pattern(s). @@ -2758,7 +2766,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cdfbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other" )]) + (set_attr "type" "itof" )]) (define_insn "floatsidf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f") @@ -2777,6 +2785,7 @@ }" [(set_attr "op_type" "NN") (set_attr "type" "other" ) + (set_attr "atype" "agen") (set_attr "length" "20")]) ; @@ -2808,7 +2817,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cefbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "other" )]) + (set_attr "type" "itof" )]) ; ; truncdfsf2 instruction pattern(s). @@ -2835,7 +2844,7 @@ lrer\\t%0,%1 le\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "floads,floads")]) ; ; extendsfdf2 instruction pattern(s). @@ -2861,7 +2870,8 @@ "@ ldebr\\t%0,%1 ldeb\\t%0,%1" - [(set_attr "op_type" "RRE,RXE")]) + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "floads,floads")]) (define_insn "extendsfdf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -2871,8 +2881,9 @@ "@ sdr\\t%0,%0\;ler\\t%0,%1 sdr\\t%0,%0\;le\\t%0,%1" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem") + [(set_attr "op_type" "NN,NN") + (set_attr "atype" "reg,agen") + (set_attr "length" "4,6") (set_attr "type" "o2,o2")]) @@ -2899,7 +2910,6 @@ && preferred_la_operand_p (operands[1], 1)" "#" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_split @@ -2919,8 +2929,7 @@ "@ agfr\\t%0,%2 agf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_zero_cc" [(set (reg 33) @@ -2933,8 +2942,7 @@ "@ algfr\\t%0,%2 algf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_zero_cconly" [(set (reg 33) @@ -2946,8 +2954,7 @@ "@ algfr\\t%0,%2 algf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -2958,8 +2965,7 @@ "@ algfr\\t%0,%2 algf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_imm_cc" [(set (reg 33) @@ -2972,8 +2978,7 @@ && s390_match_ccmode (insn, CCAmode) && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" "aghi\\t%0,%h2" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "*adddi3_cc" [(set (reg 33) @@ -2986,8 +2991,7 @@ "@ algr\\t%0,%2 alg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_cconly" [(set (reg 33) @@ -2999,8 +3003,7 @@ "@ algr\\t%0,%2 alg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_cconly2" [(set (reg 33) @@ -3011,8 +3014,7 @@ "@ algr\\t%0,%2 alg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*adddi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d,d") @@ -3024,8 +3026,7 @@ agr\\t%0,%2 aghi\\t%0,%h2 ag\\t%0,%2" - [(set_attr "op_type" "RRE,RI,RXE") - (set_attr "atype" "reg,reg,mem")]) + [(set_attr "op_type" "RRE,RI,RXE")]) (define_insn_and_split "*adddi3_31" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -3076,7 +3077,6 @@ "TARGET_64BIT" "la\\t%0,%a1" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_expand "reload_indi" @@ -3103,7 +3103,6 @@ && preferred_la_operand_p (operands[1], 1)" "#" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_split @@ -3124,8 +3123,7 @@ "s390_match_ccmode (insn, CCAmode) && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" "ahi\\t%0,%h2" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "*addsi3_carry1_cc" [(set (reg 33) @@ -3138,8 +3136,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_carry1_cconly" [(set (reg 33) @@ -3151,8 +3148,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_carry2_cc" [(set (reg 33) @@ -3165,8 +3161,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_carry2_cconly" [(set (reg 33) @@ -3178,8 +3173,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_cc" [(set (reg 33) @@ -3192,8 +3186,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_cconly" [(set (reg 33) @@ -3205,8 +3198,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_cconly2" [(set (reg 33) @@ -3217,8 +3209,7 @@ "@ alr\\t%0,%2 al\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*addsi3_sign" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3227,8 +3218,7 @@ (clobber (reg:CC 33))] "" "ah\\t%0,%2" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) (define_insn "*addsi3_sub" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3237,8 +3227,7 @@ (clobber (reg:CC 33))] "" "ah\\t%0,%2" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d") @@ -3250,8 +3239,7 @@ ar\\t%0,%2 ahi\\t%0,%h2 a\\t%0,%2" - [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem")]) + [(set_attr "op_type" "RR,RI,RX")]) (define_insn "*la_31" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3259,7 +3247,6 @@ "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" "la\\t%0,%a1" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_insn "*la_31_and" @@ -3269,7 +3256,6 @@ "!TARGET_64BIT" "la\\t%0,%a1" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_insn_and_split "*la_31_and_cc" @@ -3284,7 +3270,6 @@ (and:SI (match_dup 1) (const_int 2147483647)))] "" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_insn "force_la_31" @@ -3294,7 +3279,6 @@ "!TARGET_64BIT" "la\\t%0,%a1" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") (set_attr "type" "la")]) (define_expand "reload_insi" @@ -3332,7 +3316,7 @@ adbr\\t%0,%2 adb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd,fsimpd")]) (define_insn "*adddf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -3344,7 +3328,7 @@ adr\\t%0,%2 ad\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd,fsimpd")]) ; ; addsf3 instruction pattern(s). @@ -3369,7 +3353,7 @@ aebr\\t%0,%2 aeb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimps,fsimps")]) (define_insn "*addsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -3381,7 +3365,7 @@ aer\\t%0,%2 ae\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimps,fsimps")]) ;; @@ -3401,8 +3385,7 @@ "@ sgfr\\t%0,%2 sgf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_zero_cc" [(set (reg 33) @@ -3415,8 +3398,7 @@ "@ slgfr\\t%0,%2 slgf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_zero_cconly" [(set (reg 33) @@ -3428,8 +3410,7 @@ "@ slgfr\\t%0,%2 slgf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3440,8 +3421,7 @@ "@ slgfr\\t%0,%2 slgf\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_cc" [(set (reg 33) @@ -3454,8 +3434,7 @@ "@ slgr\\t%0,%2 slg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_cconly" [(set (reg 33) @@ -3467,8 +3446,7 @@ "@ slgr\\t%0,%2 slg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*subdi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3479,8 +3457,7 @@ "@ sgr\\t%0,%2 sg\\t%0,%2" - [(set_attr "op_type" "RRE,RRE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RRE")]) (define_insn_and_split "*subdi3_31" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -3540,8 +3517,7 @@ "@ slr\\t%0,%2 sl\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*subsi3_borrow_cconly" [(set (reg 33) @@ -3553,8 +3529,7 @@ "@ slr\\t%0,%2 sl\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*subsi3_cc" [(set (reg 33) @@ -3567,8 +3542,7 @@ "@ slr\\t%0,%2 sl\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*subsi3_cconly" [(set (reg 33) @@ -3580,8 +3554,7 @@ "@ slr\\t%0,%2 sl\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*subsi3_sign" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3590,8 +3563,7 @@ (clobber (reg:CC 33))] "" "sh\\t%0,%2" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) (define_insn "*subsi3_sub" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3600,8 +3572,7 @@ (clobber (reg:CC 33))] "" "sh\\t%0,%2" - [(set_attr "op_type" "RX") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "RX")]) (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -3612,8 +3583,7 @@ "@ sr\\t%0,%2 s\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) ; @@ -3639,7 +3609,7 @@ sdbr\\t%0,%2 sdb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd,fsimpd")]) (define_insn "*subdf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -3651,7 +3621,7 @@ sdr\\t%0,%2 sd\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimpd,fsimpd")]) ; ; subsf3 instruction pattern(s). @@ -3676,7 +3646,7 @@ sebr\\t%0,%2 seb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimps,fsimps")]) (define_insn "*subsf3_ibm" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -3688,7 +3658,7 @@ ser\\t%0,%2 se\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fsimps,fsimps")]) ;; @@ -3708,7 +3678,6 @@ msgfr\\t%0,%2 msgf\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem") (set_attr "type" "imul")]) @@ -3722,7 +3691,6 @@ mghi\\t%0,%h2 msg\\t%0,%2" [(set_attr "op_type" "RRE,RI,RXE") - (set_attr "atype" "reg,reg,mem") (set_attr "type" "imul")]) ; @@ -3739,7 +3707,6 @@ mhi\\t%0,%h2 ms\\t%0,%2" [(set_attr "op_type" "RRE,RI,RX") - (set_attr "atype" "reg,reg,mem") (set_attr "type" "imul")]) ; @@ -3778,7 +3745,6 @@ mr\\t%0,%2 m\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") (set_attr "type" "imul")]) ; @@ -3804,8 +3770,7 @@ mdbr\\t%0,%2 mdb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmul") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fmuld")]) (define_insn "*muldf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -3817,8 +3782,7 @@ mdr\\t%0,%2 md\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fmul") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fmuld")]) ; ; mulsf3 instruction pattern(s). @@ -3843,8 +3807,7 @@ meebr\\t%0,%2 meeb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmul") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fmuls")]) (define_insn "*mulsf3_ibm" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -3856,8 +3819,7 @@ mer\\t%0,%2 me\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fmul") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fmuls")]) ;; @@ -3923,8 +3885,7 @@ dsgr\\t%0,%2 dsg\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "idiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "idiv")]) (define_insn "divmodtisi3" [(set (match_operand:TI 0 "register_operand" "=d,d") @@ -3942,8 +3903,7 @@ dsgfr\\t%0,%2 dsgf\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "idiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "idiv")]) ; ; udivmoddi4 instruction pattern(s). @@ -4005,8 +3965,7 @@ dlgr\\t%0,%2 dlg\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "idiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "idiv")]) ; ; divmodsi4 instruction pattern(s). @@ -4066,8 +4025,7 @@ dr\\t%0,%2 d\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "idiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "idiv")]) ; ; udivsi3 and umodsi3 instruction pattern(s). @@ -4281,8 +4239,7 @@ ddbr\\t%0,%2 ddb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fdiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fdivd")]) (define_insn "*divdf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -4294,8 +4251,7 @@ ddr\\t%0,%2 dd\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fdiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fdivd")]) ; ; divsf3 instruction pattern(s). @@ -4320,8 +4276,7 @@ debr\\t%0,%2 deb\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fdiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fdivs")]) (define_insn "*divsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -4333,8 +4288,7 @@ der\\t%0,%2 de\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "type" "fdiv") - (set_attr "atype" "reg,mem")]) + (set_attr "type" "fdivs")]) ;; @@ -4356,8 +4310,7 @@ "@ ngr\\t%0,%2 ng\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*anddi3_cconly" [(set (reg 33) @@ -4369,8 +4322,7 @@ "@ ngr\\t%0,%2 ng\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*anddi3_ni" [(set (match_operand:DI 0 "register_operand" "=d") @@ -4392,8 +4344,7 @@ default: abort (); } }" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4404,8 +4355,7 @@ "@ ngr\\t%0,%2 ng\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*anddi3_ss" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4414,8 +4364,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*anddi3_ss_inv" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4424,8 +4373,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; andsi3 instruction pattern(s). @@ -4442,8 +4390,7 @@ "@ nr\\t%0,%2 n\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*andsi3_cconly" [(set (reg 33) @@ -4455,8 +4402,7 @@ "@ nr\\t%0,%2 n\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*andsi3_ni" [(set (match_operand:SI 0 "register_operand" "=d") @@ -4476,8 +4422,7 @@ default: abort (); } }" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -4488,8 +4433,7 @@ "@ nr\\t%0,%2 n\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*andsi3_ss" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -4498,8 +4442,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*andsi3_ss_inv" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -4508,8 +4451,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; andhi3 instruction pattern(s). @@ -4524,8 +4466,7 @@ "@ nr\\t%0,%2 nill\\t%0,%x2" - [(set_attr "op_type" "RR,RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR,RI")]) (define_insn "andhi3" [(set (match_operand:HI 0 "register_operand" "=d") @@ -4534,8 +4475,7 @@ (clobber (reg:CC 33))] "" "nr\\t%0,%2" - [(set_attr "op_type" "RR") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR")]) (define_insn "*andhi3_ss" [(set (match_operand:HI 0 "s_operand" "=Q") @@ -4544,8 +4484,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*andhi3_ss_inv" [(set (match_operand:HI 0 "s_operand" "=Q") @@ -4554,8 +4493,7 @@ (clobber (reg:CC 33))] "" "nc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; andqi3 instruction pattern(s). @@ -4570,8 +4508,7 @@ "@ nr\\t%0,%2 nill\\t%0,%b2" - [(set_attr "op_type" "RR,RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR,RI")]) (define_insn "andqi3" [(set (match_operand:QI 0 "register_operand" "=d") @@ -4580,8 +4517,7 @@ (clobber (reg:CC 33))] "" "nr\\t%0,%2" - [(set_attr "op_type" "RR") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR")]) (define_insn "*andqi3_ss" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -4592,8 +4528,7 @@ "@ ni\\t%0,%b1 nc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI,SS")]) (define_insn "*andqi3_ss_inv" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -4604,8 +4539,7 @@ "@ ni\\t%0,%b1 nc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI,SS")]) ;; @@ -4627,8 +4561,7 @@ "@ ogr\\t%0,%2 og\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*iordi3_cconly" [(set (reg 33) @@ -4640,8 +4573,7 @@ "@ ogr\\t%0,%2 og\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*iordi3_oi" [(set (match_operand:DI 0 "register_operand" "=d") @@ -4663,8 +4595,7 @@ default: abort (); } }" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4675,8 +4606,7 @@ "@ ogr\\t%0,%2 og\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*iordi3_ss" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4685,8 +4615,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*iordi3_ss_inv" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4695,8 +4624,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; iorsi3 instruction pattern(s). @@ -4713,8 +4641,7 @@ "@ or\\t%0,%2 o\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*iorsi3_cconly" [(set (reg 33) @@ -4726,8 +4653,7 @@ "@ or\\t%0,%2 o\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*iorsi3_oi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -4747,8 +4673,7 @@ default: abort (); } }" - [(set_attr "op_type" "RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RI")]) (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -4759,8 +4684,7 @@ "@ or\\t%0,%2 o\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*iorsi3_ss" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -4769,8 +4693,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*iorsi3_ss_inv" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -4779,8 +4702,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; iorhi3 instruction pattern(s). @@ -4795,8 +4717,7 @@ "@ or\\t%0,%2 oill\\t%0,%x2" - [(set_attr "op_type" "RR,RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR,RI")]) (define_insn "iorhi3" [(set (match_operand:HI 0 "register_operand" "=d") @@ -4805,8 +4726,7 @@ (clobber (reg:CC 33))] "" "or\\t%0,%2" - [(set_attr "op_type" "RR") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR")]) (define_insn "*iorhi3_ss" [(set (match_operand:HI 0 "s_operand" "=Q") @@ -4815,8 +4735,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*iorhi3_ss_inv" [(set (match_operand:HI 0 "s_operand" "=Q") @@ -4825,8 +4744,7 @@ (clobber (reg:CC 33))] "" "oc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; iorqi3 instruction pattern(s). @@ -4841,8 +4759,7 @@ "@ or\\t%0,%2 oill\\t%0,%b2" - [(set_attr "op_type" "RR,RI") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR,RI")]) (define_insn "iorqi3" [(set (match_operand:QI 0 "register_operand" "=d") @@ -4851,8 +4768,7 @@ (clobber (reg:CC 33))] "" "or\\t%0,%2" - [(set_attr "op_type" "RR") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR")]) (define_insn "*iorqi3_ss" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -4863,8 +4779,7 @@ "@ oi\\t%0,%b1 oc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "SI,SS")]) (define_insn "*iorqi3_ss_inv" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -4875,8 +4790,7 @@ "@ oi\\t%0,%b1 oc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "SI,SS")]) ;; @@ -4898,8 +4812,7 @@ "@ xgr\\t%0,%2 xg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*xordi3_cconly" [(set (reg 33) @@ -4911,8 +4824,7 @@ "@ xgr\\t%0,%2 xr\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4923,8 +4835,7 @@ "@ xgr\\t%0,%2 xg\\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RRE,RXE")]) (define_insn "*xordi3_ss" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4933,8 +4844,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*xordi3_ss_inv" [(set (match_operand:DI 0 "s_operand" "=Q") @@ -4943,8 +4853,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(8,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; xorsi3 instruction pattern(s). @@ -4961,8 +4870,7 @@ "@ xr\\t%0,%2 x\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*xorsi3_cconly" [(set (reg 33) @@ -4974,8 +4882,7 @@ "@ xr\\t%0,%2 x\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -4986,8 +4893,7 @@ "@ xr\\t%0,%2 x\\t%0,%2" - [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem")]) + [(set_attr "op_type" "RR,RX")]) (define_insn "*xorsi3_ss" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -4996,8 +4902,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*xorsi3_ss_inv" [(set (match_operand:SI 0 "s_operand" "=Q") @@ -5006,8 +4911,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(4,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; xorhi3 instruction pattern(s). @@ -5030,8 +4934,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) (define_insn "*xorhi3_ss_inv" [(set (match_operand:HI 0 "s_operand" "=Q") @@ -5040,8 +4943,7 @@ (clobber (reg:CC 33))] "" "xc\\t%O0(2,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SS")]) ; ; xorqi3 instruction pattern(s). @@ -5054,8 +4956,7 @@ (clobber (reg:CC 33))] "" "xr\\t%0,%2" - [(set_attr "op_type" "RR") - (set_attr "atype" "reg")]) + [(set_attr "op_type" "RR")]) (define_insn "*xorqi3_ss" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -5066,8 +4967,7 @@ "@ xi\\t%0,%b1 xc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI,SS")]) (define_insn "*xorqi3_ss_inv" [(set (match_operand:QI 0 "s_operand" "=Q,Q") @@ -5078,8 +4978,7 @@ "@ xi\\t%0,%b1 xc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "SI,SS") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "SI,SS")]) ;; @@ -5157,7 +5056,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lcdbr\\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimpd")]) (define_insn "*negdf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5165,7 +5065,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lcdr\\t%0,%1" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimpd")]) ; ; negsf2 instruction pattern(s). @@ -5185,7 +5086,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lcebr\\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimps")]) (define_insn "*negsf2" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5193,7 +5095,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lcer\\t%0,%1" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimps")]) ;; @@ -5242,7 +5145,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lpdbr\\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimpd")]) (define_insn "*absdf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5250,7 +5154,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lpdr\\t%0,%1" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimpd")]) ; ; abssf2 instruction pattern(s). @@ -5270,7 +5175,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lpebr\\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimps")]) (define_insn "*abssf2_ibm" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5278,7 +5184,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lper\\t%0,%1" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "type" "fsimps")]) ;; ;;- Square root instructions. @@ -5295,7 +5202,8 @@ "@ sqdbr\\t%0,%1 sqdb\\t%0,%1" - [(set_attr "op_type" "RRE,RSE")]) + [(set_attr "op_type" "RRE,RSE") + (set_attr "type" "fsqrtd")]) ; ; sqrtsf2 instruction pattern(s). @@ -5308,7 +5216,8 @@ "@ sqebr\\t%0,%1 sqeb\\t%0,%1" - [(set_attr "op_type" "RRE,RSE")]) + [(set_attr "op_type" "RRE,RSE") + (set_attr "type" "fsqrts")]) ;; ;;- One complement instructions. @@ -5383,7 +5292,8 @@ "@ rllg\\t%0,%1,%c2 rllg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) ; ; rotlsi3 instruction pattern(s). @@ -5397,7 +5307,8 @@ "@ rll\\t%0,%1,%c2 rll\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) ;; @@ -5423,7 +5334,8 @@ "@ sldl\\t%0,%c2 sldl\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) (define_insn "*ashldi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -5433,7 +5345,8 @@ "@ sllg\\t%0,%1,%2 sllg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) ; ; ashrdi3 instruction pattern(s). @@ -5459,7 +5372,8 @@ "@ srda\\t%0,%c2 srda\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_31" [(set (reg 33) @@ -5471,7 +5385,8 @@ "@ srda\\t%0,%c2 srda\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) (define_insn "*ashrdi3_31" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -5482,8 +5397,9 @@ "@ srda\\t%0,%c2 srda\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) - + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) + (define_insn "*ashrdi3_cc_64" [(set (reg 33) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") @@ -5495,7 +5411,8 @@ "@ srag\\t%0,%1,%c2 srag\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_64" [(set (reg 33) @@ -5507,7 +5424,8 @@ "@ srag\\t%0,%1,%c2 srag\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) (define_insn "*ashrdi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -5518,7 +5436,9 @@ "@ srag\\t%0,%1,%c2 srag\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE")]) + [(set_attr "op_type" "RSE") + (set_attr "atype" "reg")]) + ; ; ashlsi3 instruction pattern(s). @@ -5532,7 +5452,8 @@ "@ sll\\t%0,%c2 sll\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) ; ; ashrsi3 instruction pattern(s). @@ -5549,7 +5470,9 @@ "@ sra\\t%0,%c2 sra\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) + (define_insn "*ashrsi3_cconly" [(set (reg 33) @@ -5561,7 +5484,8 @@ "@ sra\\t%0,%c2 sra\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -5572,7 +5496,8 @@ "@ sra\\t%0,%c2 sra\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) ;; @@ -5598,7 +5523,8 @@ "@ srdl\\t%0,%c2 srdl\\t%0,0(%2)" - [(set_attr "op_type" "RS,RS")]) + [(set_attr "op_type" "RS,RS") + (set_attr "atype" "reg")]) (define_insn "*lshrdi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -5608,7 +5534,8 @@ "@ srlg\\t%0,%1,%c2 srlg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE,RSE")]) + [(set_attr "op_type" "RSE,RSE") + (set_attr "atype" "reg")]) ; ; lshrsi3 instruction pattern(s). @@ -5622,7 +5549,8 @@ "@ srl\\t%0,%c2 srl\\t%0,0(%2)" - [(set_attr "op_type" "RS")]) + [(set_attr "op_type" "RS") + (set_attr "atype" "reg")]) ;; @@ -5813,6 +5741,7 @@ abort (); }" [(set_attr "op_type" "RI") + (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) @@ -5838,7 +5767,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) ;; @@ -5862,6 +5792,7 @@ abort (); }" [(set_attr "op_type" "RI") + (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) @@ -5887,7 +5818,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) ;; ;;- Trap instructions. @@ -5897,7 +5829,8 @@ [(trap_if (const_int 1) (const_int 0))] "" "j\\t.+2" - [(set_attr "op_type" "RX")]) + [(set_attr "op_type" "RX") + (set_attr "type" "branch")]) (define_expand "conditional_trap" [(set (match_dup 2) (match_dup 3)) @@ -5922,7 +5855,8 @@ (const_int 0))] "" "j%C0\\t.+2"; - [(set_attr "op_type" "RX")]) + [(set_attr "op_type" "RI") + (set_attr "type" "branch")]) ;; ;;- Loop instructions. @@ -5971,6 +5905,7 @@ abort (); }" [(set_attr "op_type" "RI") + (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) @@ -6001,7 +5936,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) (define_split [(set (pc) @@ -6049,6 +5985,7 @@ abort (); }" [(set_attr "op_type" "RI") + (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) (const_int 12)))]) @@ -6075,7 +6012,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RRE") (const_string "RXE"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) (define_split [(set (pc) @@ -6122,6 +6060,7 @@ abort (); }" [(set_attr "op_type" "RI") + (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) @@ -6147,7 +6086,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) ; ; casesi instruction pattern(s). @@ -6167,7 +6107,8 @@ [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) - (set_attr "atype" "mem")]) + (set_attr "type" "branch") + (set_attr "atype" "agen")]) (define_expand "casesi" [(match_operand:SI 0 "general_operand" "") @@ -6346,7 +6287,7 @@ "basr\\t%2,%0" [(set_attr "op_type" "RR") (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn "basr_31" [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) @@ -6356,7 +6297,7 @@ "basr\\t%2,%0" [(set_attr "op_type" "RR") (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn "bas_64" [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) @@ -6365,8 +6306,7 @@ "TARGET_64BIT" "bas\\t%2,%a0" [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "type" "jsr")]) (define_insn "bas_31" [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) @@ -6375,8 +6315,7 @@ "!TARGET_64BIT" "bas\\t%2,%a0" [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "type" "jsr")]) ; @@ -6471,7 +6410,8 @@ "TARGET_64BIT" "basr\\t%3,%1" [(set_attr "op_type" "RR") - (set_attr "type" "jsr")]) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) (define_insn "basr_r_31" [(set (match_operand 0 "register_operand" "=df") @@ -6482,7 +6422,7 @@ "basr\\t%3,%1" [(set_attr "op_type" "RR") (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn "bas_r_64" [(set (match_operand 0 "register_operand" "=df") @@ -6492,8 +6432,7 @@ "TARGET_64BIT" "bas\\t%3,%a1" [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "type" "jsr")]) (define_insn "bas_r_31" [(set (match_operand 0 "register_operand" "=df") @@ -6503,8 +6442,7 @@ "!TARGET_64BIT" "bas\\t%3,%a1" [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "type" "jsr")]) ;; @@ -6808,7 +6746,7 @@ "TARGET_64BIT" "larl\\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "la")]) + (set_attr "type" "larl")]) (define_insn "reload_anchor" [(set (match_operand:SI 0 "register_operand" "=a") @@ -6817,6 +6755,7 @@ "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)" [(set_attr "op_type" "NN") (set_attr "type" "la") + (set_attr "atype" "agen") (set_attr "length" "8")]) (define_insn "pool" @@ -6857,7 +6796,7 @@ "br\\t%0" [(set_attr "op_type" "RR") (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn "*return_di" [(return) @@ -6866,7 +6805,7 @@ "br\\t%0" [(set_attr "op_type" "RR") (set_attr "type" "jsr") - (set_attr "atype" "mem")]) + (set_attr "atype" "agen")]) (define_insn "literal_pool_31" [(unspec_volatile [(const_int 0)] 300) @@ -6883,7 +6822,7 @@ return \"\"; }" [(set_attr "op_type" "NN") - (set_attr "type" "la")]) + (set_attr "type" "larl")]) (define_insn "literal_pool_64" [(unspec_volatile [(const_int 0)] 300) @@ -6900,4 +6839,4 @@ return \"\"; }" [(set_attr "op_type" "NN") - (set_attr "type" "la")]) + (set_attr "type" "larl")]) -- cgit v1.1