From 05f0e9eec9f9beeffe024ecd6566b41200d79cff Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Mon, 22 Jul 2024 12:20:43 -0400 Subject: Add -mcpu=power11 support. This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. This patch allows GCC to be configured with the --with-cpu=power11 and --with-tune=power11 options. This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. 2024-07-22 Michael Meissner gcc/ * config.gcc (powerpc*-*-*): Add support for power11. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11. (power11 cpu): Add power11 definition. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. * config/rs6000/power10.md (all reservations): Add power11 support. gcc/testsuite/ * gcc.target/powerpc/power11-1.c: New test. * gcc.target/powerpc/power11-2.c: Likewise. * gcc.target/powerpc/power11-3.c: Likewise. --- gcc/config.gcc | 4 +- gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/aix73.h | 1 + gcc/config/rs6000/driver-rs6000.cc | 2 + gcc/config/rs6000/power10.md | 144 +++++++++++++-------------- gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc | 2 + gcc/config/rs6000/rs6000-cpus.def | 5 + gcc/config/rs6000/rs6000-opts.h | 1 + gcc/config/rs6000/rs6000-string.cc | 1 + gcc/config/rs6000/rs6000-tables.opt | 11 +- gcc/config/rs6000/rs6000.cc | 32 ++++-- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 ++ gcc/doc/invoke.texi | 2 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 19 ++++ gcc/testsuite/gcc.target/powerpc/power11-3.c | 9 ++ 21 files changed, 171 insertions(+), 90 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/power11-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/power11-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/power11-3.c diff --git a/gcc/config.gcc b/gcc/config.gcc index bc45615..7453ade 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) cpu_is_64bit=yes ;; esac @@ -5641,7 +5641,7 @@ case "${target}" in eval "with_$which=405" ;; "" | common | native \ - | power[3456789] | power10 | power5+ | power6x \ + | power[3456789] | power1[01] | power5+ | power6x \ | powerpc | powerpc64 | powerpc64le \ | rs64 \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 24bc301..41037b3 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index c43974f..fe59f83 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index b1572bd..1318b0b 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index 3ebbaa4..f490072 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = { { "power8", "-mpwr8" }, { "power9", "-mpwr9" }, { "power10", "-mpwr10" }, + { "power11", "-mpwr11" }, { "powerpc", "-mppc" }, { "rs64", "-mppc" }, { "603", "-m603" }, @@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = { { "power8", "-mpower8" }, { "power9", "-mpower9" }, { "power10", "-mpower10" }, + { "power11", "-mpower11" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199..2310c46 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM Power10 and Power11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-larx" 4 (and (eq_attr "type" "load_l") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; All load quad forms (define_insn_reservation "power10-lq" 4 (and (eq_attr "type" "load,load_l") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-stcx" 0 (and (eq_attr "type" "store_c") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; All store quad forms (define_insn_reservation "power10-stq" 0 (and (eq_attr "type" "store,store_c") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-sync" 1 (and (eq_attr "type" "sync,isync") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") @@ -248,7 +248,7 @@ (define_insn_reservation "power10-alu" 2 (and (eq_attr "type" "add,exts,integer,logical,isel") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; 4 cycle CR latency (define_bypass 4 "power10-alu" @@ -256,28 +256,28 @@ (define_insn_reservation "power10-fused_alu" 2 (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; paddi (define_insn_reservation "power10-paddi" 2 (and (eq_attr "type" "add") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; Rotate/shift (non-record form) (define_insn_reservation "power10-rot" 2 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; Record form rotate/shift (define_insn_reservation "power10-rot-compare" 3 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-rot-compare" @@ -285,7 +285,7 @@ (define_insn_reservation "power10-alu2" 3 (and (eq_attr "type" "cntlz,popcnt,trap") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-alu2" @@ -293,24 +293,24 @@ (define_insn_reservation "power10-cmp" 2 (and (eq_attr "type" "cmp") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; Treat 'two' and 'three' types as 2 or 3 way cracked (define_insn_reservation "power10-two" 4 (and (eq_attr "type" "two") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-three" 6 (and (eq_attr "type" "three") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_all_power10,EXU_power10") (define_insn_reservation "power10-mul" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul" @@ -319,7 +319,7 @@ (define_insn_reservation "power10-mul-compare" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul-compare" @@ -331,13 +331,13 @@ (define_insn_reservation "power10-div" 12 (and (eq_attr "type" "div") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-div-compare" 12 (and (eq_attr "type" "div") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; 14 cycle CR latency (define_bypass 14 "power10-div-compare" @@ -345,34 +345,34 @@ (define_insn_reservation "power10-crlogical" 2 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcrf" 2 (and (eq_attr "type" "mfcrf") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcr" 3 (and (eq_attr "type" "mfcr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; Should differentiate between 1 cr field and > 1 since target of > 1 cr ; is cracked (define_insn_reservation "power10-mtcr" 3 (and (eq_attr "type" "mtcr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtjmpr" 3 (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfjmpr" 2 (and (eq_attr "type" "mfjmpr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") @@ -380,126 +380,126 @@ (define_insn_reservation "power10-fpsimple" 3 (and (eq_attr "type" "fpsimple") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fp" 5 (and (eq_attr "type" "fp,dmul") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fpcompare" 3 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sdiv" 22 (and (eq_attr "type" "sdiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-ddiv" 27 (and (eq_attr "type" "ddiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sqrt" 26 (and (eq_attr "type" "ssqrt") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dsqrt" 36 (and (eq_attr "type" "dsqrt") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vec-2cyc" 2 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fused-vec" 2 (and (eq_attr "type" "fused_vector") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccmp" 3 (and (eq_attr "type" "veccmp") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecsimple" 2 (and (eq_attr "type" "vecsimple") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecnormal" 5 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qp" 12 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "no") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm-compare" 3 (and (eq_attr "type" "vecperm") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-prefixed-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccomplex" 6 (and (eq_attr "type" "veccomplex") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecfdiv" 24 (and (eq_attr "type" "vecfdiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecdiv" 27 (and (eq_attr "type" "vecdiv") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpdiv" 56 (and (eq_attr "type" "vecdiv") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpmul" 24 (and (eq_attr "type" "qmul") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtvsr" 2 (and (eq_attr "type" "mtvsr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfvsr" 2 (and (eq_attr "type" "mfvsr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") @@ -507,26 +507,26 @@ ; Branch is 2 cycles, grouped with STU for issue (define_insn_reservation "power10-branch" 2 (and (eq_attr "type" "jmpreg,branch") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-branch" 3 (and (eq_attr "type" "fused_mtbc") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Crypto (define_insn_reservation "power10-crypto" 4 (and (eq_attr "type" "crypto") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") ; HTM (define_insn_reservation "power10-htm" 2 (and (eq_attr "type" "htmsimple,htm") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") @@ -535,26 +535,26 @@ (define_insn_reservation "power10-dfp" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dfpq" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_power10") ; MMA (define_insn_reservation "power10-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,EXU_super_power10") (define_insn_reservation "power10-prefixed-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,EXU_super_power10") ; 4 cycle MMA->MMA latency (define_bypass 4 "power10-mma,power10-prefixed-mma" diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h index 364bba4..ed269e3 100644 --- a/gcc/config/rs6000/ppc-auxv.h +++ b/gcc/config/rs6000/ppc-auxv.h @@ -47,9 +47,8 @@ #define PPC_PLATFORM_PPC476 12 #define PPC_PLATFORM_POWER8 13 #define PPC_PLATFORM_POWER9 14 - -/* This is not yet official. */ #define PPC_PLATFORM_POWER10 15 +#define PPC_PLATFORM_POWER11 16 /* AT_HWCAP bits. These must match the values defined in the Linux kernel. */ #define PPC_FEATURE_32 0x80000000 diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 0a24d20..117cf01 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -2442,6 +2442,7 @@ static const struct const char *cpu; unsigned int cpuid; } cpu_is_info[] = { + { "power11", PPC_PLATFORM_POWER11 }, { "power10", PPC_PLATFORM_POWER10 }, { "power9", PPC_PLATFORM_POWER9 }, { "power8", PPC_PLATFORM_POWER8 }, diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 6229c50..68519e1 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -435,6 +435,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); + if ((flags & OPTION_MASK_POWER11) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 6ee678e..84fac8b 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,9 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) +#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_POWER11) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -123,6 +126,7 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ + | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ @@ -250,6 +254,7 @@ RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) +RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | POWER11_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 33fd0ef..88e3578 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -62,6 +62,7 @@ enum processor_type PROCESSOR_POWER8, PROCESSOR_POWER9, PROCESSOR_POWER10, + PROCESSOR_POWER11, PROCESSOR_RS64A, PROCESSOR_MPCCORE, diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index c4c62e8..0f99290 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -964,6 +964,7 @@ expand_compare_loop (rtx operands[]) break; case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (bytes_is_const) max_bytes = 191; else diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 65f4670..a5649fe 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -186,14 +186,17 @@ EnumValue Enum(rs6000_cpu_opt_value) String(power10) Value(52) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(53) +Enum(rs6000_cpu_opt_value) String(power11) Value(53) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(54) +Enum(rs6000_cpu_opt_value) String(powerpc) Value(54) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55) EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56) + +EnumValue +Enum(rs6000_cpu_opt_value) String(rs64) Value(57) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 5ed64b1..eddd2ad 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* SF->DF convert */ }; -/* Instruction costs on POWER10 processors. */ +/* Instruction costs on Power10/Power11 processors. */ static const struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* mulsi */ @@ -4385,7 +4385,8 @@ rs6000_option_override_internal (bool global_init_p) generating power10 instructions. */ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { - if (rs6000_tune == PROCESSOR_POWER10) + if (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4414,6 +4415,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 + && rs6000_tune != PROCESSOR_POWER11 && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4428,6 +4430,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4727,6 +4730,7 @@ rs6000_option_override_internal (bool global_init_p) break; case PROCESSOR_POWER10: + case PROCESSOR_POWER11: rs6000_cost = &power10_cost; break; @@ -5899,6 +5903,8 @@ rs6000_machine_from_flags (void) flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL | OPTION_MASK_ALTIVEC); + if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) + return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -10147,6 +10153,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18228,7 +18235,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18267,6 +18275,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18841,6 +18850,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: + case PROCESSOR_POWER11: return 8; default: return 1; @@ -19556,8 +19566,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10/Power11 dependent reordering. */ + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19581,8 +19593,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10/Power11 dependent reordering. */ + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22799,7 +22813,8 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24470,6 +24485,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, + { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 8ea9ac1..703be90 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -101,6 +101,7 @@ you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ mcpu=power8|mcpu=powerpc64le: -mpower8; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f59be53..637a859 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -350,7 +350,7 @@ ppc750,ppc7400,ppc7450, ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, - power4,power5,power6,power7,power8,power9,power10, + power4,power5,power6,power7,power8,power9,power10,power11, rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index e8ca703..94323bd 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -585,6 +585,12 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save mpower10 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved +;; Users should not use -mpower11, but we need to use a bit to identify when +;; the user changes the default cpu via #pragma GCC target("cpu=power11") +;; and then resets it later. +mpower11 +Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved + mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3f6634c..e0a6412 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31558,7 +31558,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, +@samp{power9}, @samp{power10}, @samp{power11}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, @samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c b/gcc/testsuite/gcc.target/powerpc/power11-1.c new file mode 100644 index 0000000..029a596 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power11 -O2" } */ + +/* Basic check to see if the compiler supports -mcpu=power11 and if it defines + _ARCH_PWR11. */ + +#ifndef _ARCH_PWR11 +#error "-mcpu=power11 is not supported" +#endif + +void foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c b/gcc/testsuite/gcc.target/powerpc/power11-2.c new file mode 100644 index 0000000..e3438e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check if we can set the power11 target via a target attribute. */ + +__attribute__((__target__("cpu=power9"))) +void foo_p9 (void) +{ +} + +__attribute__((__target__("cpu=power10"))) +void foo_p10 (void) +{ +} + +__attribute__((__target__("cpu=power11"))) +void foo_p11 (void) +{ +} diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c new file mode 100644 index 0000000..fa1aedd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Check if we can set the power11 target via a target_clones attribute. */ + +__attribute__((__target_clones__("cpu=power11,cpu=power9,default"))) +void foo (void) +{ +} -- cgit v1.1