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2023-06-20Daily bump.GCC Administrator1-0/+20
2023-06-19amdgcn: implement vector div and mod libfuncsAndrew Stubbs9-47/+1052
Also divmod, but only for scalar modes, for now (because there are no complex int vectors yet). gcc/ChangeLog: * config/gcn/gcn.cc (gcn_expand_divmod_libfunc): New function. (gcn_init_libfuncs): Add div and mod functions for all modes. Add placeholders for divmod functions. (TARGET_EXPAND_DIVMOD_LIBFUNC): Define. libgcc/ChangeLog: * config/gcn/lib2-divmod-di.c: Reimplement like lib2-divmod.c. * config/gcn/lib2-divmod.c: Likewise. * config/gcn/lib2-gcn.h: Add new types and prototypes for all the new vector libfuncs. * config/gcn/t-amdgcn: Add new files. * config/gcn/amdgcn_veclib.h: New file. * config/gcn/lib2-vec_divmod-di.c: New file. * config/gcn/lib2-vec_divmod-hi.c: New file. * config/gcn/lib2-vec_divmod-qi.c: New file. * config/gcn/lib2-vec_divmod.c: New file. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/predcom-2.c: Avoid vectors on amdgcn. * gcc.dg/unroll-8.c: Likewise. * gcc.dg/vect/slp-26.c: Change expected results on amdgdn. * lib/target-supports.exp (check_effective_target_vect_int_mod): Add amdgcn. (check_effective_target_divmod): Likewise. * gcc.target/gcn/simd-math-3-16.c: New test. * gcc.target/gcn/simd-math-3-2.c: New test. * gcc.target/gcn/simd-math-3-32.c: New test. * gcc.target/gcn/simd-math-3-4.c: New test. * gcc.target/gcn/simd-math-3-8.c: New test. * gcc.target/gcn/simd-math-3-char-16.c: New test. * gcc.target/gcn/simd-math-3-char-2.c: New test. * gcc.target/gcn/simd-math-3-char-32.c: New test. * gcc.target/gcn/simd-math-3-char-4.c: New test. * gcc.target/gcn/simd-math-3-char-8.c: New test. * gcc.target/gcn/simd-math-3-char-run-16.c: New test. * gcc.target/gcn/simd-math-3-char-run-2.c: New test. * gcc.target/gcn/simd-math-3-char-run-32.c: New test. * gcc.target/gcn/simd-math-3-char-run-4.c: New test. * gcc.target/gcn/simd-math-3-char-run-8.c: New test. * gcc.target/gcn/simd-math-3-char-run.c: New test. * gcc.target/gcn/simd-math-3-char.c: New test. * gcc.target/gcn/simd-math-3-long-16.c: New test. * gcc.target/gcn/simd-math-3-long-2.c: New test. * gcc.target/gcn/simd-math-3-long-32.c: New test. * gcc.target/gcn/simd-math-3-long-4.c: New test. * gcc.target/gcn/simd-math-3-long-8.c: New test. * gcc.target/gcn/simd-math-3-long-run-16.c: New test. * gcc.target/gcn/simd-math-3-long-run-2.c: New test. * gcc.target/gcn/simd-math-3-long-run-32.c: New test. * gcc.target/gcn/simd-math-3-long-run-4.c: New test. * gcc.target/gcn/simd-math-3-long-run-8.c: New test. * gcc.target/gcn/simd-math-3-long-run.c: New test. * gcc.target/gcn/simd-math-3-long.c: New test. * gcc.target/gcn/simd-math-3-run-16.c: New test. * gcc.target/gcn/simd-math-3-run-2.c: New test. * gcc.target/gcn/simd-math-3-run-32.c: New test. * gcc.target/gcn/simd-math-3-run-4.c: New test. * gcc.target/gcn/simd-math-3-run-8.c: New test. * gcc.target/gcn/simd-math-3-run.c: New test. * gcc.target/gcn/simd-math-3-short-16.c: New test. * gcc.target/gcn/simd-math-3-short-2.c: New test. * gcc.target/gcn/simd-math-3-short-32.c: New test. * gcc.target/gcn/simd-math-3-short-4.c: New test. * gcc.target/gcn/simd-math-3-short-8.c: New test. * gcc.target/gcn/simd-math-3-short-run-16.c: New test. * gcc.target/gcn/simd-math-3-short-run-2.c: New test. * gcc.target/gcn/simd-math-3-short-run-32.c: New test. * gcc.target/gcn/simd-math-3-short-run-4.c: New test. * gcc.target/gcn/simd-math-3-short-run-8.c: New test. * gcc.target/gcn/simd-math-3-short-run.c: New test. * gcc.target/gcn/simd-math-3-short.c: New test. * gcc.target/gcn/simd-math-3.c: New test. * gcc.target/gcn/simd-math-4-char-run.c: New test. * gcc.target/gcn/simd-math-4-char.c: New test. * gcc.target/gcn/simd-math-4-long-run.c: New test. * gcc.target/gcn/simd-math-4-long.c: New test. * gcc.target/gcn/simd-math-4-run.c: New test. * gcc.target/gcn/simd-math-4-short-run.c: New test. * gcc.target/gcn/simd-math-4-short.c: New test. * gcc.target/gcn/simd-math-4.c: New test. * gcc.target/gcn/simd-math-5-16.c: New test. * gcc.target/gcn/simd-math-5-32.c: New test. * gcc.target/gcn/simd-math-5-4.c: New test. * gcc.target/gcn/simd-math-5-8.c: New test. * gcc.target/gcn/simd-math-5-char-16.c: New test. * gcc.target/gcn/simd-math-5-char-32.c: New test. * gcc.target/gcn/simd-math-5-char-4.c: New test. * gcc.target/gcn/simd-math-5-char-8.c: New test. * gcc.target/gcn/simd-math-5-char-run-16.c: New test. * gcc.target/gcn/simd-math-5-char-run-32.c: New test. * gcc.target/gcn/simd-math-5-char-run-4.c: New test. * gcc.target/gcn/simd-math-5-char-run-8.c: New test. * gcc.target/gcn/simd-math-5-char-run.c: New test. * gcc.target/gcn/simd-math-5-char.c: New test. * gcc.target/gcn/simd-math-5-long-16.c: New test. * gcc.target/gcn/simd-math-5-long-32.c: New test. * gcc.target/gcn/simd-math-5-long-4.c: New test. * gcc.target/gcn/simd-math-5-long-8.c: New test. * gcc.target/gcn/simd-math-5-long-run-16.c: New test. * gcc.target/gcn/simd-math-5-long-run-32.c: New test. * gcc.target/gcn/simd-math-5-long-run-4.c: New test. * gcc.target/gcn/simd-math-5-long-run-8.c: New test. * gcc.target/gcn/simd-math-5-long-run.c: New test. * gcc.target/gcn/simd-math-5-long.c: New test. * gcc.target/gcn/simd-math-5-run-16.c: New test. * gcc.target/gcn/simd-math-5-run-32.c: New test. * gcc.target/gcn/simd-math-5-run-4.c: New test. * gcc.target/gcn/simd-math-5-run-8.c: New test. * gcc.target/gcn/simd-math-5-run.c: New test. * gcc.target/gcn/simd-math-5-short-16.c: New test. * gcc.target/gcn/simd-math-5-short-32.c: New test. * gcc.target/gcn/simd-math-5-short-4.c: New test. * gcc.target/gcn/simd-math-5-short-8.c: New test. * gcc.target/gcn/simd-math-5-short-run-16.c: New test. * gcc.target/gcn/simd-math-5-short-run-32.c: New test. * gcc.target/gcn/simd-math-5-short-run-4.c: New test. * gcc.target/gcn/simd-math-5-short-run-8.c: New test. * gcc.target/gcn/simd-math-5-short-run.c: New test. * gcc.target/gcn/simd-math-5-short.c: New test. * gcc.target/gcn/simd-math-5.c: New test.
2023-06-19amdgcn: Delete inactive libfuncsAndrew Stubbs3-126/+0
The HImode libfuncs weren't called and trying to enable them fails because TARGET_PROMOTE_FUNCTION_MODE wants to widen the arguments but the signedness isn't known. libgcc/ChangeLog: * config/gcn/lib2-gcn.h (QItype, UQItype, HItype, UHItype): Delete. (__divhi3, __modhi3, __udivhi3, __umodhi3): Delete. * config/gcn/t-amdgcn: Don't build lib2-divmod-hi.c. * config/gcn/lib2-divmod-hi.c: Removed.
2023-06-08Daily bump.GCC Administrator1-0/+6
2023-06-07libgcc: Fix eh_frame fast path in find_fde_tailFlorian Weimer1-1/+1
The eh_frame value is only used by linear_search_fdes, not the binary search directly in find_fde_tail, so the bug is not immediately apparent with most programs. Fixes commit e724b0480bfa5ec04f39be8c7290330b495c59de ("libgcc: Special-case BFD ld unwind table encodings in find_fde_tail"). libgcc/ PR libgcc/109712 * unwind-dw2-fde-dip.c (find_fde_tail): Correct fast path for parsing eh_frame.
2023-06-06Daily bump.GCC Administrator1-0/+18
2023-06-04libgcc: Use initarray section type for .init_stackKewen Lin3-3/+3
One of my workmates found there is a warning like: libgcc/config/rs6000/morestack.S:402: Warning: ignoring incorrect section type for .init_array.00000 when compiling libgcc/config/rs6000/morestack.S. Since commit r13-6545 touched that file recently, which was suspected to be responsible for this warning, I did some investigation and found this is a warning staying for a long time. For section .init_stack*, it's preferred to use section type SHT_INIT_ARRAY. So this patch is use "@init_array" to replace "@progbits". Although the warning is trivial, Segher suggested me to post this to fix it, in order to avoid any possible misunderstanding/confusion on the warning. As Alan confirmed, this doesn't require a premise check on if the existing binutils supports "@init_array" or not, "because if you want split-stack to work, you must link with gold, any version of binutils that has gold has an assembler that understands @init_array". (Thanks Alan!) libgcc/ChangeLog: * config/i386/morestack.S: Use @init_array rather than @progbits for section type of section .init_array. * config/rs6000/morestack.S: Likewise. * config/s390/morestack.S: Likewise.
2023-06-05MIPS: Add speculation_barrier supportYunQiang Su4-2/+94
speculation_barrier for MIPS needs sync+jr.hb (r2+), so we implement __speculation_barrier in libgcc, like arm32 does. gcc/ChangeLog: * config/mips/mips-protos.h (mips_emit_speculation_barrier): New prototype. * config/mips/mips.cc (speculation_barrier_libfunc): New static variable. (mips_init_libfuncs): Initialize it. (mips_emit_speculation_barrier): New function. * config/mips/mips.md (speculation_barrier): Call mips_emit_speculation_barrier. libgcc/ChangeLog: * config/mips/lib1funcs.S: New file. define __speculation_barrier and include mips16.S. * config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S. define LIB1ASMFUNCS as _speculation_barrier. set version info for __speculation_barrier. * config/mips/libgcc-mips.ver: New file. * config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S included in lib1funcs.S now.
2023-06-04Daily bump.GCC Administrator1-0/+10
2023-06-03fix radix sort on 32bit platforms [PR109670]Thomas Neumann1-5/+3
The radix sort uses two buffers, a1 for input and a2 for output. After every digit the role of the two buffers is swapped. When terminating the sort early the code made sure the output was in a2. However, when we run out of bits, as can happen on 32bit platforms, the sorted result was in a1, as we had just swapped a1 and a2. This patch fixes the problem by unconditionally having a1 as output after every loop iteration. This bug manifested itself only on 32bit platforms and even then only in some circumstances, as it needs frames where a swap is required due to differences in the top-most byte, which is affected by ASLR. The new logic was validated by exhaustive search over 32bit input values. libgcc/ChangeLog: PR libgcc/109670 * unwind-dw2-fde.c: Fix radix sort buffer management.
2023-06-03release the sorted FDE array when deregistering a frame [PR109685]Thomas Neumann1-0/+6
The atomic fastpath bypasses the code that releases the sort array which was lazily allocated during unwinding. We now check after deregistering if there is an array to free. libgcc/ChangeLog: PR libgcc/109685 * unwind-dw2-fde.c: Free sort array in atomic fast path.
2023-05-20Daily bump.GCC Administrator1-0/+13
2023-05-19Darwin, libgcc : Adjust min version supported for the OS.Iain Sandoe6-8/+63
Tools from later versions of the OS deprecate or fail to support earlier OS revisions. Signed-off-by: Iain Sandoe <iain@sandoe.co.uk> libgcc/ChangeLog: * config.host: Arrange to set min Darwin OS versions from the configured host version. * config/darwin10-unwind-find-enc-func.c: Do not use current headers, but declare the nexessary structures locally to the versions in use for Mac OSX 10.6. * config/t-darwin: Amend to handle configured min OS versions. * config/t-darwin-min-1: New. * config/t-darwin-min-5: New. * config/t-darwin-min-8: New.
2023-05-16Daily bump.GCC Administrator1-0/+8
2023-05-15fix assert in non-atomic pathThomas Neumann1-1/+3
The non-atomic path does not have range information, we have to adjust the assert handle that case, too. libgcc/ChangeLog: * unwind-dw2-fde.c: Fix assert in non-atomic path.
2023-05-15fix assert in __deregister_frame_info_basesSören Tempel1-1/+3
The assertion in __deregister_frame_info_bases assumes that for every frame something was inserted into the lookup data structure by __register_frame_info_bases. Unfortunately, this does not necessarily hold true as the btree_insert call in __register_frame_info_bases will not insert anything for empty ranges. Therefore, we need to explicitly account for such empty ranges in the assertion as `ob` will be a null pointer for such ranges, hence causing the assertion to fail. Signed-off-by: Sören Tempel <soeren@soeren-tempel.net> libgcc/ChangeLog: * unwind-dw2-fde.c: Accept empty ranges when deregistering frames.
2023-05-03Daily bump.GCC Administrator1-0/+5
2023-05-02RISC-V: Enforce Libatomic LR/SC SEQ_CSTPatrick O'Neill1-2/+2
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> libgcc/ChangeLog: * config/riscv/atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02Daily bump.GCC Administrator1-0/+5
2023-05-01libgcc pru: Define TARGET_HAS_NO_HW_DIVIDEDimitar Dimitrov1-0/+3
This patch aligns the configuration to the actual PRU capabilities. It also reduces the size of the affected libgcc functions. For a real-world project using integer arithmetics the savings are significant: Before: text data bss dec hex filename 3688 865 544 5097 13e9 hc-sr04-range-sensor.elf With TARGET_HAS_NO_HW_DIVIDE defined: text data bss dec hex filename 2824 865 544 4233 1089 hc-sr04-range-sensor.elf Execution speed also appears to have improved. The moddi3 function is now executed in half the CPU cycles. libgcc/ChangeLog: * config/pru/t-pru (HOST_LIBGCC2_CFLAGS): Add -DTARGET_HAS_NO_HW_DIVIDE. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2023-04-27Daily bump.GCC Administrator1-0/+10
2023-04-27libgcc CRIS: Define TARGET_HAS_NO_HW_DIVIDEHans-Peter Nilsson1-0/+3
With this, execution time for e.g. __moddi3 go from 59 to 40 cycles in the "fast" case or from 290 to 200 cycles in the "slow" case (when the !TARGET_HAS_NO_HW_DIVIDE variant calls division and modulus functions for 32-bit SImode), as exposed by gcc.c-torture/execute/arith-rand-ll.c compiled for -march=v10. Unfortunately, it just puts a performance improvement "dent" of 0.07% in a arith-rand-ll.c-based performance test - where all loops are also reduced to 1/10. The size of every affected libgcc function is reduced to less than half and they are all now leaf functions. * config/cris/t-cris (HOST_LIBGCC2_CFLAGS): Add -DTARGET_HAS_NO_HW_DIVIDE.
2023-04-26RISCV: Inline subword atomic opsPatrick O'Neill1-0/+2
RISC-V has no support for subword atomic operations; code currently generates libatomic library calls. This patch changes the default behavior to inline subword atomic calls (using the same logic as the existing library call). Behavior can be specified using the -minline-atomics and -mno-inline-atomics command line flags. gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm. This will need to stay for backwards compatibility and the -mno-inline-atomics flag. 2023-04-18 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: PR target/104338 * config/riscv/riscv-protos.h: Add helper function stubs. * config/riscv/riscv.cc: Add helper functions for subword masking. * config/riscv/riscv.opt: Add command-line flag. * config/riscv/sync.md: Add masking logic and inline asm for fetch_and_op, fetch_and_nand, CAS, and exchange ops. * doc/invoke.texi: Add blurb regarding command-line flag. libgcc/ChangeLog: PR target/104338 * config/riscv/atomic.c: Add reference to duplicate logic. gcc/testsuite/ChangeLog: PR target/104338 * gcc.target/riscv/inline-atomics-1.c: New test. * gcc.target/riscv/inline-atomics-2.c: New test. * gcc.target/riscv/inline-atomics-3.c: New test. * gcc.target/riscv/inline-atomics-4.c: New test. * gcc.target/riscv/inline-atomics-5.c: New test. * gcc.target/riscv/inline-atomics-6.c: New test. * gcc.target/riscv/inline-atomics-7.c: New test. * gcc.target/riscv/inline-atomics-8.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-04-09Daily bump.GCC Administrator1-0/+6
2023-04-08PR target/109402: v850 (not v850e) variant of __muldi3() moves sp in ↵Tetsuma Hoshino1-2/+0
reversed direction [PR109402] muldi3 will deallocate stack space after the call to __save_r26_r31, then re-allocate the space a short while later. If an interrupt occurs in that window, it can clobber items on the stack. PR target/109402 libgcc/ * config/v850/lib1funcs.S (___muldi3): Remove unnecessary stack manipulations.
2023-04-06Daily bump.GCC Administrator1-0/+9
2023-04-05Add assember CFI directives to millicode division and remainder routines.John David Anglin1-0/+14
The millicode division and remainder routines trap division by zero. The unwinder needs these directives to unwind divide by zero traps. 2023-04-05 John David Anglin <danglin@gcc.gnu.org> libgcc/ChangeLog: PR target/109374 * config/pa/milli64.S (RETURN_COLUMN): Define. ($$divI): Add CFI directives. ($$divU): Likewise. ($$remI): Likewise. ($$remU): Likewise.
2023-03-20Daily bump.GCC Administrator1-0/+5
2023-03-19or1k: Do not clear existing FPU exceptions before updatingStafford Horne1-1/+0
We should always carry the exceptions forward. This bug was found when working on testing glibc math tests, many tests were failing with Overflow and Underflow flags not set. This was traced to here. libgcc/ChangeLog: * config/or1k/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove statement clearing existing exceptions.
2023-03-14Daily bump.GCC Administrator1-0/+7
2023-03-13xtensa: add .note.GNU-stack section on linuxMax Filippov4-0/+24
gcc/ * config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro. libgcc/ * config/xtensa/crti.S: Add .note.GNU-stack section on linux. * config/xtensa/crtn.S: Likewise. * config/xtensa/lib1funcs.S: Likewise. * config/xtensa/lib2funcs.S: Likewise.
2023-03-13Daily bump.GCC Administrator1-0/+11
2023-03-13aarch64: Add bfloat16_t support for aarch64Jakub Jelinek5-3/+109
x86_64/i686 has for a few months working std::bfloat16_t support, __bf16 there is no longer a storage only type, but can be used for arithmetics and is supported in libgcc and libstdc++. The following patch adds similar support for AArch64. Unlike the x86 changes, this one keeps the old __bf16 mangling of u6__bf16 rather than DF16b (so an exception from Itanium ABI), but otherwise __bf16 and decltype (0.0bf16) are the same type and both in C++ act as extended floating-point type. 2023-03-13 Jakub Jelinek <jakub@redhat.com> gcc/ * config/aarch64/aarch64.h (aarch64_bf16_type_node): Remove. (aarch64_bf16_ptr_type_node): Adjust comment. * config/aarch64/aarch64.cc (aarch64_gimplify_va_arg_expr): Use bfloat16_type_node rather than aarch64_bf16_type_node. (aarch64_libgcc_floating_mode_supported_p, aarch64_scalar_mode_supported_p): Also support BFmode. (aarch64_invalid_conversion, aarch64_invalid_unary_op): Remove. (aarch64_invalid_binary_op): Remove BFmode related rejections. (TARGET_INVALID_CONVERSION, TARGET_INVALID_UNARY_OP): Don't redefine. * config/aarch64/aarch64-builtins.cc (aarch64_bf16_type_node): Remove. (aarch64_int_or_fp_type): Use bfloat16_type_node rather than aarch64_bf16_type_node. (aarch64_init_simd_builtin_types): Likewise. (aarch64_init_bf16_types): Likewise. Don't create bfloat16_type_node, which is created in tree.cc already. * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general-c/ternary_bfloat16_opt_n_1.c: Don't expect one __bf16 related error. * gcc.target/aarch64/bfloat16_vector_typecheck_1.c: Adjust or remove dg-error directives for __bf16 being an extended arithmetic type. * gcc.target/aarch64/bfloat16_vector_typecheck_2.c: Likewise. * gcc.target/aarch64/bfloat16_scalar_typecheck.c: Likewise. * g++.target/aarch64/bfloat_cpp_typecheck.C: Don't expect two __bf16 related errors. libgcc/ * config/aarch64/t-softfp (softfp_extensions): Add bfsf. (softfp_truncations): Add tfbf dfbf sfbf hfbf. (softfp_extras): Add floatdibf floatundibf floattibf floatuntibf. * config/aarch64/libgcc-softfp.ver (GCC_13.0.0): Export __extendbfsf2 and __trunc{s,d,t,h}fbf2. * config/aarch64/sfp-machine.h (_FP_NANFRAC_B, _FP_NANSIGN_B): Define. * soft-fp/floatundibf.c: New file. * soft-fp/floatdibf.c: New file. libstdc++-v3/ * config/abi/pre/gnu.ver (CXXABI_1.3.14): Also export __bf16 tinfos if it isn't mangled as DF16b but u6__bf16.
2023-03-11Daily bump.GCC Administrator1-0/+10
2023-03-10libgcc, i386: Add __fix{,uns}bfti and __float{,un}tibf [PR107703]Jakub Jelinek4-1/+96
While DI <-> BF conversions can be handled (and are) through DI <-> XF <-> BF and for narrower integral modes even sometimes through DF or SF, because XFmode has 64-bit mantissa and so all the DImode values are exactly representable in XFmode. That is not the case for TImode, and while e.g. the HF -> TI conversions are IMHO useless in libgcc, because HFmode has -65504.0f16, 65504.0f16 range, all the integers will be already representable in SImode (or even HImode for unsigned) and so I think HF -> DI -> TI conversions are faster and valid, BFmode has roughly the same range as SFmode and so we absolutely need the TI -> BF conversions to avoid double rounding. As for BF -> TI conversions, they can be either also implemented in libgcc, or they can be implemented (as done in this commit) as BF -> SF -> TI conversions with the same code generation used elsewhere, just doing the 16-bit left shift of the bits - I think we don't need to handle sNaNs during the BF -> SF part because SF -> TI (which is already a libcall too) will handle that too. The BF -> SF -> TI path avoids wasting 32: 0000000000015e10 321 FUNC GLOBAL DEFAULT 13 __fixbfti@@GCC_13.0.0 89: 0000000000015f60 299 FUNC GLOBAL DEFAULT 13 __fixunsbfti@@GCC_13.0.0 2023-03-10 Jakub Jelinek <jakub@redhat.com> PR target/107703 * optabs.cc (expand_fix): For conversions from BFmode to integral, use shifts to convert it to SFmode first and then convert SFmode to integral. * soft-fp/floattibf.c: New file. * soft-fp/floatuntibf.c: New file. * config/i386/libgcc-glibc.ver: Export __float{,un}tibf @ GCC_13.0.0. * config/i386/64/t-softfp (softfp_extras): Add floattibf and floatuntibf. (CFLAGS-floattibf.c, CFLAGS-floatunstibf.c): Add -msse2.
2023-03-09Daily bump.GCC Administrator1-0/+6
2023-03-08libgcc, rs6000: Fix bump size for powerpc64 elfv1 ABI [PR108727]Kewen Lin1-2/+2
As PR108727 shows, when cleanup code called by the stack unwinder calls function _Unwind_Resume, it goes via plt stub like: function 00000000.plt_call._Unwind_Resume: => 0x0000000010003580 <+0>: std r2,40(r1) 0x0000000010003584 <+4>: ld r12,-31760(r2) 0x0000000010003588 <+8>: mtctr r12 0x000000001000358c <+12>: ld r2,-31752(r2) 0x0000000010003590 <+16>: cmpldi r2,0 0x0000000010003594 <+20>: bnectr+ 0x0000000010003598 <+24>: b 0x100031a4 <_Unwind_Resume@plt> It wants to save TOC base (r2) to r1 + 40, but we only bump the stack segment by 32 bytes as follows: stdu %r29,-32(%r3) It means the access is out of the stack segment allocated by __generic_morestack, once the touch area isn't writable like this failure shows, it would cause segment fault. So fix the bump size with one reasonable value PARAMS. PR libgcc/108727 libgcc/ChangeLog: * config/rs6000/morestack.S (__morestack): Use PARAMS for new stack bump size.
2023-03-07Daily bump.GCC Administrator1-0/+16
2023-03-06PR target/107299: Fix build issue when long double is IEEE 128-bitMichael Meissner5-11/+52
This patch updates the IEEE 128-bit types used in libgcc. At the moment, we cannot build GCC when the target uses IEEE 128-bit long doubles, such as building the compiler for a native Fedora 36 system. The build dies when it is trying to build the _mulkc3.c and _divkc3 modules. This patch changes libgcc to use long double for the IEEE 128-bit base type if long double is IEEE 128-bit, and it uses _Float128 otherwise. The built-in functions are adjusted to be the correct version based on the IEEE 128-bit base type used. While it is desirable to ultimately have __float128 and _Float128 use the same internal type and mode within GCC, at present if you use the option -mabi=ieeelongdouble, the __float128 type will use the long double type and not the _Float128 type. We get an internal compiler error if we combine the signbitf128 built-in with a long double type. I've gone through several iterations of trying to fix this within GCC, and there are various problems that have come up. I developed this alternative patch that changes libgcc so that it does not tickle the issue. I hope we can fix the compiler at some point, but right now, this is preventing people on Fedora 36 systems from building compilers where the default long double is IEEE 128-bit. 2023-03-06 Michael Meissner <meissner@linux.ibm.com> libgcc/ PR target/107299 * config/rs6000/_divkc3.c (COPYSIGN): Use the correct built-in based on whether long double is IBM or IEEE. (INFINITY): Likewise. (FABS): Likewise. * config/rs6000/_mulkc3.c (COPYSIGN): Likewise. (INFINITY): Likewise. * config/rs6000/quad-float128.h (TF): Remove definition. (TFtype): Define to be long double or _Float128. (TCtype): Define to be _Complex long double or _Complex _Float128. * libgcc2.h (TFtype): Allow machine config files to override this. (TCtype): Likewise. * soft-fp/quad.h (TFtype): Likewise.
2023-02-14Daily bump.GCC Administrator1-0/+5
2023-02-13RISC-V: Handle vlenb correctly in unwindingKito Cheng2-0/+42
gcc/ChangeLog: * config/riscv/riscv.h (RISCV_DWARF_VLENB): New. (DWARF_FRAME_REGISTERS): New. (DWARF_REG_TO_UNWIND_COLUMN): New. libgcc/ChangeLog: * config.host (riscv*-*-*): Add config/riscv/value-unwind.h. * config/riscv/value-unwind.h: New.
2023-02-04Daily bump.GCC Administrator1-0/+5
2023-02-03arm: Fix warning in libgcc/config/arm/pr-support.cChristophe Lyon1-0/+6
I have noticed some warnings when building GCC for arm-eabi: pr-support.c:110:7: warning: variable ‘set_pac_sp’ set but not used [-Wunused-but-set-variable] pr-support.c:109:7: warning: variable ‘set_pac’ set but not used [-Wunused-but-set-variable] This small patch avoids them by defining these two variables undef TARGET_HAVE_PACBTI, like the code which actually uses them. libgcc/ * config/arm/pr-support.c (__gnu_unwind_execute): Use TARGET_HAVE_PACBTI to define set_pac and set_pac_sp.
2023-01-31Daily bump.GCC Administrator1-0/+6
2023-01-30Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurdFlavio Cruz2-1/+17
Tested by building a toolchain and compiling gnumach for x86_64 [1]. This is the basic version without unwind support which I think is only required to implement exceptions. [1] https://github.com/flavioc/cross-hurd/blob/master/bootstrap-kernel.sh. gcc/ChangeLog: * config.gcc: Recognize x86_64-*-gnu* targets and include i386/gnu64.h. * config/i386/gnu64.h: Define configuration for new target including ld.so location. libgcc/ChangeLog: * config.host: Recognize x86_64-*-gnu* targets. * config/i386/gnu-unwind.h: Update to handle __x86_64__ with a TODO for now. Signed-off-by: Flavio Cruz <flaviocruz@gmail.com>
2023-01-24Daily bump.GCC Administrator1-0/+19
2023-01-23arm: Add support for new frame unwinding instruction "0xb5".Srinath Parvathaneni1-2/+13
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When an exception is taken and "0xb5" instruction is encounter during runtime stack-unwinding, we use effective vsp as modifier in pointer authentication. On completion of stack unwinding if "0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf libgcc/ChangeLog: 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/pr-support.c (__gnu_unwind_execute): Decode opcode "0xb5".
2023-01-23[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtimeAndrea Corallo2-0/+60
This patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feature is switched on for the architecture. This means that switching on the target feature via -march or -mcpu is sufficient and -mbranch-protection need not be enabled. This ensures that the unwinder is authenticated only if the PACBTI instructions are available in the non-NOP space as it uses AUTG. Just generating PAC/AUT instructions using -mbranch-protection will not enable authentication on the unwinder. Pre-approved with the requested changes here <https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586555.html>. gcc/ChangeLog: * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce new pseudo register class _UVRSC_PAC. libgcc/ChangeLog: * config/arm/pr-support.c (__gnu_unwind_execute): Decode exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate with AUTG if found. * config/arm/unwind-arm.c (struct pseudo_regs): New. (phase1_vrs): Introduce new field to store pseudo-reg state. (phase2_vrs): Likewise. (_Unwind_VRS_Get): Load pseudo register state from virtual reg set. (_Unwind_VRS_Set): Store pseudo register state to virtual reg set. (_Unwind_VRS_Pop): Load pseudo register value from stack into VRS. Co-Authored-By: Tejas Belagod <tbelagod@arm.com> Co-Authored-By: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2023-01-19Daily bump.GCC Administrator1-0/+11
2023-01-18libgcc: Fix uninitialized RA signing on AArch64 [PR107678]Wilco Dijkstra4-34/+22
A recent change only initializes the regs.how[] during Dwarf unwinding which resulted in an uninitialized offset used in return address signing and random failures during unwinding. The fix is to encode the return address signing state in REG_UNSAVED and a new state REG_UNSAVED_ARCHEXT. libgcc/ PR target/107678 * unwind-dw2.h (REG_UNSAVED_ARCHEXT): Add new enum. * unwind-dw2.c (uw_update_context_1): Add REG_UNSAVED_ARCHEXT case. * unwind-dw2-execute_cfa.h: Use REG_UNSAVED_ARCHEXT/REG_UNSAVED to encode the return address signing state. * config/aarch64/aarch64-unwind.h (aarch64_demangle_return_addr) Check current return address signing state. (aarch64_frob_update_contex): Remove.
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