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2018-09-26crtprec.c (set_precision): Use fnstcw instead of fstcw.Uros Bizjak1-1/+1
* config/i386/crtprec.c (set_precision): Use fnstcw instead of fstcw. From-SVN: r264649
2018-09-21Leverage cacheTextUpdate for __clear_cache on VxWorksOlivier Hainque3-0/+45
2018-09-21 Alexandre Oliva <oliva@adacore.com> libgcc/ * config/vxcache.c: New file. Provide __clear_cache, based on the cacheTextUpdate VxWorks service. * config/t-vxworks (LIB2ADD): Add vxcache.c. (LIB2FUNCS_EXCLUDE): Add _clear_cache. * config/t-vxwoks7: Likewise. gcc/ * config/vxworks.h (CLEAR_INSN_CACHE): #define to 1. From-SVN: r264479
2018-09-21[NDS32] Sync glibc and kernel structure, all use _rt_sigframe.Monk Chiang1-14/+4
libgcc/ * config/nds32/linux-unwind.h (struct _rt_sigframe): Use struct ucontext_t type instead. (nds32_fallback_frame_state): Remove struct _sigframe statement. From-SVN: r264461
2018-09-21[NDS32] Add t-nds32-glibc file.Kito Cheng1-0/+34
libgcc/ * config/nds32/t-nds32-glibc: New file. From-SVN: r264460
2018-09-18Use v2 map syntax in libgcc-unwind.map if Solaris ld supports itRainer Orth1-0/+11
* configure.ac (solaris_ld_v2_maps): New test. * configure: Regenerate. * Makefile.in (solaris_ld_v2_maps): New variable. * config/t-slibgcc-sld (libgcc-unwind.map): Emit v2 mapfile syntax if supported. From-SVN: r264382
2018-08-23PR target/86951 arm - Handle speculation barriers on pre-armv7 CPUsRichard Earnshaw2-1/+45
The AArch32 instruction sets prior to Armv7 do not define the ISB and DSB instructions that are needed to form a speculation barrier. While I do not know of any instances of cores based on those instruction sets being vulnerable to speculative side channel attacks it is possible to run code built for those ISAs on more recent hardware where they would become vulnerable. This patch works around this by using a library call added to libgcc. That code can then take any platform-specific actions necessary to ensure safety. For the moment I've only handled two cases: the library code being built for armv7 or later anyway and running on Linux. On Linux we can handle this by calling the kernel function that will flush a small amount of cache. Such a sequence ends with a ISB+DSB sequence if running on an Armv7 or later CPU. gcc: PR target/86951 * config/arm/arm-protos.h (arm_emit_speculation_barrier): New prototype. * config/arm/arm.c (speculation_barrier_libfunc): New static variable. (arm_init_libfuncs): Initialize it. (arm_emit_speculation_barrier): New function. * config/arm/arm.md (speculation_barrier): Call arm_emit_speculation_barrier for architectures that do not have DSB or ISB. (speculation_barrier_insn): Only match on Armv7 or later. libgcc: PR target/86951 * config/arm/lib1funcs.asm (speculation_barrier): New function. * config/arm/t-arm (LIB1ASMFUNCS): Add it to list of functions to build. From-SVN: r263806
2018-08-22Move Darwin10 unwinder fix to a crt shim.Iain Sandoe3-13/+17
gcc/ * config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Adjust to use the Darwin10-specific unwinder-shim. * config/darwin12.h (LINK_GCC_C_SEQUENCE_SPEC): Remove. * config/rs6000/darwin.h (DARWIN_CRT1_SPEC, DARWIN_DYLIB1_SPEC): New to cater for Darwin10 Rosetta. libgcc/ * config/unwind-dw2-fde-darwin.c (_darwin10_Unwind_FindEnclosingFunction): move from here ... * config/darwin10-unwind-find-enc-func.c: … to here. * config/t-darwin: Build Darwin10 unwinder shim crt. * libgcc/config.host: Add the Darwin10 unwinder shim. From-SVN: r263765
2018-08-17C-SKY port: libgccJojo7-0/+1349
2018-08-17 Jojo <jijie_rong@c-sky.com> Huibin Wang <huibin_wang@c-sky.com> Sandra Loosemore <sandra@codesourcery.com> Chung-Lin Tang <cltang@codesourcery.com> C-SKY port: libgcc libgcc/ * config.host: Add C-SKY support. * config/csky/*: New. Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com> Co-Authored-By: Huibin Wang <huibin_wang@c-sky.com> Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com> From-SVN: r263631
2018-08-12[NDS32] Implement more C ISR extension.Chung-Ju Wu87-241/+883
gcc/ * config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in extra_headers. * common/config/nds32/nds32-common.c (nds32_handle_option): Handle OPT_misr_secure_ case. * config/nds32/nds32-isr.c: Implementation of backward compatibility. * config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New. * config/nds32/nds32.c (nds32_attribute_table): Add critical and secure attribute. * config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL. (nds32_isr_info): New field security_level. (TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro. * config/nds32/nds32.md (return_internal): Consider critical attribute. * config/nds32/nds32.opt (misr-secure): New option. * config/nds32/nds32_init.inc: New file. * config/nds32/nds32_isr.h: New file. libgcc/ * config/nds32/t-nds32-isr: Rearrange object dependency. * config/nds32/initfini.c: Add dwarf2 unwinding support. * config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions and registers usage. * config/nds32/isr-library/excp_isr.S: Ditto. * config/nds32/isr-library/intr_isr.S: Ditto. * config/nds32/isr-library/reset.S: Ditto. * config/nds32/isr-library/restore_all.inc: Ditto. * config/nds32/isr-library/restore_mac_regs.inc: Ditto. * config/nds32/isr-library/restore_partial.inc: Ditto. * config/nds32/isr-library/restore_usr_regs.inc: Ditto. * config/nds32/isr-library/save_all.inc: Ditto. * config/nds32/isr-library/save_mac_regs.inc: Ditto. * config/nds32/isr-library/save_partial.inc: Ditto. * config/nds32/isr-library/save_usr_regs.inc: Ditto. * config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size. From-SVN: r263493
2018-08-11pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.John David Anglin1-39/+27
gcc * config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum. Update comment for atomic instructions. (atomic_storeqi, atomic_storehi, atomic_storesi, atomic_storesf, atomic_loaddf, atomic_loaddf_1, atomic_storedf, atomic_storedf_1): Remove. (atomic_loaddi): Revise fence expansion to only emit fence prior to load for __ATOMIC_SEQ_CST model. (atomic_loaddi_1): Remove float register target. (atomic_storedi): Handle CONST_INT values. (atomic_storedi_1): Remove float register source. Add special case for zero value. (memory_barrier): New expander and insn. libgcc * config/pa/linux-atomic.c: Update comment. (FETCH_AND_OP_2, OP_AND_FETCH_2, FETCH_AND_OP_WORD, OP_AND_FETCH_WORD, COMPARE_AND_SWAP_2, __sync_val_compare_and_swap_4, SYNC_LOCK_TEST_AND_SET_2, __sync_lock_test_and_set_4): Use __ATOMIC_RELAXED for atomic loads. (SYNC_LOCK_RELEASE_1): New define. Use __sync_synchronize() and unordered store to release lock. (__sync_lock_release_8): Likewise. (SYNC_LOCK_RELEASE_2): Remove define. From-SVN: r263488
2018-08-02arm - correctly handle denormal results during softfp subtractionNicolas Pitre2-9/+11
2018-08-02 Nicolas Pitre <nico@fluxnic.net> PR libgcc/86512 * config/arm/ieee754-df.S (adddf3): Don't shortcut denormal handling when exponent goes negative. Update my email address. * config/arm/ieee754-sf.S (addsf3): Likewise. From-SVN: r263267
2018-07-30[ARM] libgcc: Fix comment for code working on architectures >= 4.Christophe Lyon2-2/+2
2018-07-30 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/ieee754-df.S: Fix comment for code working on architectures >= 4. * config/arm/ieee754-sf.S: Likewise. From-SVN: r263066
2018-07-27i386: Remove _Unwind_Frames_IncrementH.J. Lu1-5/+0
CET kernel has been changed to place a restore token on shadow stack for signal handler to enhance security. It is usually transparent to user programs since kernel will pop the restore token when signal handler returns. But when an exception is thrown from a signal handler, now we need to remove _Unwind_Frames_Increment to pop the the restore token from shadow stack. Otherwise, we get FAIL: g++.dg/torture/pr85334.C -O0 execution test FAIL: g++.dg/torture/pr85334.C -O1 execution test FAIL: g++.dg/torture/pr85334.C -O2 execution test FAIL: g++.dg/torture/pr85334.C -O3 -g execution test FAIL: g++.dg/torture/pr85334.C -Os execution test FAIL: g++.dg/torture/pr85334.C -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test PR libgcc/85334 * config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment): Removed. From-SVN: r263030
2018-06-21[ARM] Use __ARM_ARCH and __ARM_FEATURE_LDREX instead of __ARM_ARCH__Christophe Lyon4-77/+27
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> libatomic/ * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX and HAVE_STREXBHD libgcc/ * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use __ARM_ARCH and __ARM_FEATURE_CLZ instead. (HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead. * config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of __ARM_ARCH__. * config/arm/ieee754-sf.S: Likewise. * config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__. From-SVN: r261841
2018-06-21[ARM] libgcc: Remove unsupported code for __ARM_ARCH__ < 4Christophe Lyon2-103/+2
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> libgcc/ * config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no longer supported. * config/arm/ieee754-sf.S: Likewise. From-SVN: r261840
2018-06-18re PR target/85358 (PowerPC: Using -mabi=ieeelongdouble -mcpu=power9 breaks ↵Michael Meissner2-2/+2
__ibm128) [gcc] 2018-06-18 Michael Meissner <meissner@linux.ibm.com> PR target/85358 * config/rs6000/rs6000-modes.def (toplevel): Rework the 128-bit floating point modes, so that IFmode is numerically greater than TFmode, which is greater than KFmode using FRACTIONAL_FLOAT_MODE to declare the ordering. This prevents IFmode from being converted to TFmode when long double is IEEE 128-bit on an ISA 3.0 machine. Include rs6000-modes.h to share the fractional values between genmodes* and the rest of the compiler. (IFmode): Likewise. (KFmode): Likewise. (TFmode): Likewise. * config/rs6000/rs6000-modes.h: New file. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Change the meaning of rs6000_long_double_size so that 126..128 selects an appropriate 128-bit floating point type. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.h (toplevel): Include rs6000-modes.h. (TARGET_LONG_DOUBLE_128): Change the meaning of rs6000_long_double_size so that 126..128 selects an appropriate 128-bit floating point type. (LONG_DOUBLE_TYPE_SIZE): Update comment. * config/rs6000/rs6000.md (trunciftf2): Correct the modes of the source and destination to match the standard usage. (truncifkf2): Likewise. (copysign<mode>3, IEEE iterator): Rework copysign of float128 on ISA 2.07 to use an explicit clobber, instead of passing in a temporary. (copysign<mode>3_soft): Likewise. [libgcc] 2018-06-18 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128 support modules with -mno-gnu-attribute. * config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise. From-SVN: r261712
2018-06-07t-vxworks (LIBGCC_INCLUDES): Add -I$(MULTIBUILDTOP)../../gcc/include.Olivier Hainque2-4/+8
2018-06-07 Olivier Hainque <hainque@adacore.com> * config/t-vxworks (LIBGCC_INCLUDES): Add -I$(MULTIBUILDTOP)../../gcc/include. * config/t-vxworks7: Likewise. Reformat a bit to match the t-vxworks layout. From-SVN: r261273
2018-06-07config.gcc: Support "tremont".Olga Makhotina1-0/+1
2018-06-07 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config.gcc: Support "tremont". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "tremont". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_TREMONT. * config/i386/i386.c (m_TREMONT): Define. (processor_target_table): Add "tremont". (PTA_TREMONT): Define. (ix86_lea_outperforms): Add TARGET_TREMONT. (get_builtin_code_for_version): Handle PROCESSOR_TREMONT. (fold_builtin_cpu): Add M_INTEL_TREMONT, replace M_INTEL_GOLDMONT and M_INTEL_GOLDMONT_PLUS. (fold_builtin_cpu): Add "tremont". (ix86_add_stmt_cost): Add TARGET_TREMONT. (ix86_option_override_internal): Add "tremont". * config/i386/i386.h (processor_costs): Define TARGET_TREMONT. (processor_type): Add PROCESSOR_TREMONT. * config/i386/x86-tune.def: Add m_TREMONT. * doc/invoke.texi: Add tremont as x86 -march=/-mtune= CPU type. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Test arch=tremont. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_TREMONT. From-SVN: r261270
2018-06-02[NDS32] Support Linux target for nds32.Chung-Ju Wu2-0/+438
gcc/ * config.gcc (nds32*): Use nds32-linux.opt and nds32-elf.opt. (nds32le-*-*, nds32be-*-*): Integrate checking process. (nds32*-*-*): Add glibc and uclibc conditions. * common/config/nds32/nds32-common.c (nds32_except_unwind_info): New. (TARGET_EXCEPT_UNWIND_INFO): Define. * config/nds32/elf.h: New file. * config/nds32/linux.h: New file. * config/nds32/nds32-elf.opt: New file. * config/nds32/nds32-linux.opt: New file. * config/nds32/nds32-fp-as-gp.c (pass_nds32_fp_as_gp::gate): Consider TARGET_LINUX_ABI. * config/nds32/nds32.c (nds32_conditional_register_usage): Consider TARGET_LINUX_ABI. (nds32_asm_file_end): Ditto. (nds32_print_operand): Ditto. (nds32_insert_attributes): Ditto. (nds32_init_libfuncs): New function. (TARGET_HAVE_TLS): Define. (TARGET_INIT_LIBFUNCS): Define. * config/nds32/nds32.h (TARGET_DEFAULT_RELAX): Apply different relax spec content. (TARGET_ELF): Apply different mcmodel setting. (LINK_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): The content has been migrated into elf.h and linux.h files. * config/nds32/nds32.md (add_pc): Consider TARGET_LINUX_ABI. * config/nds32/nds32.opt (mvh): Consider TARGET_LINUX_ABI. (mcmodel): The content has been migrated into nds32-elf.opt and nds32-linux.opt files. * config/nds32/t-elf: New file. * config/nds32/t-linux: New file. libgcc/ * config.host (nds32*-linux*): New. * config/nds32/linux-atomic.c: New file. * config/nds32/linux-unwind.h: New file. Co-Authored-By: Kito Cheng <kito.cheng@gmail.com> Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r261116
2018-05-31re PR target/85591 (__builtin_cpu_is() is not detecting bdver2 with Model = ↵Uros Bizjak1-4/+7
0x02) PR target/85591 * config/i386/cpuinfo.c (get_amd_cpu): Return AMDFAM15H_BDVER2 for AMDFAM15H model 0x2. From-SVN: r261036
2018-05-23lb1sf68.S (Laddsf$nf): Fix sign bit handling in path to Lf$finfty.Kalamatee1-2/+2
2018-05-23 Kalamatee <kalamatee@gmail.com> * config/m68k/lb1sf68.S (Laddsf$nf): Fix sign bit handling in path to Lf$finfty. From-SVN: r260626
2018-05-18RISC-V: Add RV32E support.Kito Cheng1-1/+45
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> gcc/ * common/config/riscv/riscv-common.c (riscv_parse_arch_string): Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i. * config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e. * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define __riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI. * config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E. * config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE, compute save_libcall_adjustment properly. (riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E. (riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E. * config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E. (STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE. (GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise. (ABI_SPEC): Handle mabi=ilp32e. * config/riscv/riscv.opt (abi_type): Add ABI_ILP32E. (RVE): Add RVE mask. * doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info. <-march>: Add rv32e as an example. gcc/testsuite/ * gcc.dg/stack-usage-1.c: Add support for rv32e. libgcc/ * config/riscv/save-restore.S: Add support for rv32e. Co-Authored-By: Jim Wilson <jimw@sifive.com> Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r260384
2018-05-18[arm][1/2] Remove support for deprecated -march=armv5 and armv5eKyrylo Tkachov1-2/+2
The -march=armv5 and armv5e options have been deprecated in GCC 7 [1]. This patch removes support for them. It's mostly mechanical stuff. The functionality that was previously gated on arm_arch5 is now gated on arm_arch5t and the functionality that was gated on arm_arch5e is now gated on arm_arch5te. A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and therefore is deleted. References to armv5 and armv5e are deleted/updated throughout the source tree and testsuite. Bootstrapped and tested on arm-none-linux-gnueabihf. Also built a cc1 for arm-wrs-vxworks as a sanity check. * config/arm/arm-cpus.in (armv5, armv5e): Delete features. (armv5t, armv5te): New features. (ARMv5, ARMv5e): Delete fgroups. (ARMv5t, ARMv5te): Adjust for above changes. (ARMv6m): Likewise. (armv5, armv5e): Delete arches. * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of arm_arch5. (*call_reg_arm): Likewise. (*call_value_reg_armv5): Likewise. (*call_value_reg_arm): Likewise. (*call_symbol): Likewise. (*call_value_symbol): Likewise. (*sibcall_insn): Likewise. (*sibcall_value_insn): Likewise. (clzsi2): Likewise. (prefetch): Likewise. (define_split and define_peephole2 dependent on arm_arch5): Likewise. * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of arm_arch5e. (TARGET_ARM_QBIT): Likewise. (TARGET_DSP_MULTIPLY): Likewise. (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E. (arm_arch5, arm_arch5e): Delete. (arm_arch5t, arm_arch5te): Declare. * config/arm/arm.c (arm_arch5, arm_arch5e): Delete. (arm_arch5t): Declare. (arm_option_reconfigure_globals): Update for the above. (arm_options_perform_arch_sanity_checks): Update comment, replace use of arm_arch5 with arm_arch5t. (use_return_insn): Likewise. (arm_emit_call_insn): Likewise. (output_return_instruction): Likewise. (arm_final_prescan_insn): Likewise. (arm_coproc_builtin_available): Likewise. * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and arm_arch5e with arm_arch5t and arm_arch5te. * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete. (arm_arch5t, arm_arch5te): Declare. * config/arm/arm-tables.opt: Regenerate. * config/arm/t-arm-elf: Remove references to armv5, armv5e. * config/arm/t-multilib: Likewise. * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t instead of arm_arch5. (*call_reg_thumb1): Likewise. (*call_value_reg_thumb1_v5): Likewise. (*call_value_reg_thumb1): Likewise. * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now unreachable path. * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e. * gcc.target/arm/pr40887.c: Update comment. * lib/target-supports.exp: Don't generate effective target checks and related helpers for armv5. Update comment. * gcc.target/arm/armv5_thumb_isa.c: Delete. * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective target check and options. * config/arm/libunwind.S: Update comment relating to armv5. From-SVN: r260362
2018-05-17arm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.Jerome Lambourg1-2/+3
2018-05-17 Jerome Lambourg <lambourg@adacore.com> gcc/ * config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove #include <stdint.h>. Replace intptr_t with __INTPTR_TYPE__. libgcc/ * config/arm/cmse.c (cmse_check_address_range): Replace UINTPTR_MAX with __UINTPTR_MAX__ and uintptr_t with __UINTPTR_TYPE__. From-SVN: r260330
2018-05-17config.gcc: Support "goldmont-plus".Olga Makhotina2-0/+5
2018-05-17 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config.gcc: Support "goldmont-plus". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont-plus". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_GOLDMONT_PLUS. * config/i386/i386.c (m_GOLDMONT_PLUS): Define. (processor_target_table): Add "goldmont-plus". (PTA_GOLDMONT_PLUS): Define. (ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS. (get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS. (fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS. (fold_builtin_cpu): Add "goldmont-plus". (ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS. (ix86_option_override_internal): Add "goldmont-plus". * config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS. (processor_type): Add PROCESSOR_GOLDMONT_PLUS. * config/i386/x86-tune.def: Add m_GOLDMONT_PLUS. * doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS. * config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test goldmont-plus. * gcc.target/i386/funcspec-56.inc: Test arch=goldmont-plus. From-SVN: r260307
2018-05-08config.gcc: Support "goldmont".Olga Makhotina2-0/+6
2018-05-08 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config.gcc: Support "goldmont". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_GOLDMONT. * config/i386/i386.c (m_GOLDMONT): Define. (processor_target_table): Add "goldmont". (PTA_GOLDMONT): Define. (ix86_lea_outperforms): Add TARGET_GOLDMONT. (get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT. (fold_builtin_cpu): Add M_INTEL_GOLDMONT. (fold_builtin_cpu): Add "goldmont". (ix86_add_stmt_cost): Add TARGET_GOLDMONT. (ix86_option_override_internal): Add "goldmont". * config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT. (processor_type): Add PROCESSOR_GOLDMONT. * config/i386/i386.md: Add CPU "glm". * config/i386/glm.md: New file. * config/i386/x86-tune.def: Add m_GOLDMONT. * doc/invoke.texi: Add goldmont as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT. * config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test goldmont. * gcc.target/i386/funcspec-56.inc: Tests for arch=goldmont and arch=silvermont. From-SVN: r260042
2018-04-27re PR libgcc/84292 (__sync_add_and_fetch returns the old value instead of ↵Andreas Tobler1-11/+11
the new value) 2018-04-27 Andreas Tobler <andreast@gcc.gnu.org> Maryse Levavasseur <maryse.levavasseur@stormshield.eu> PR libgcc/84292 * config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the op_and_fetch to return the right result. Co-Authored-By: Maryse Levavasseur <maryse.levavasseur@stormshield.eu> From-SVN: r259722
2018-04-27PR85532, crtend.o built without --enable-initfini-array has bad .eh_frameAlan Modra1-1/+1
PR libgcc/85532 * config/rs6000/t-crtstuff (CRTSTUFF_T_CFLAGS): Add -fno-asynchronous-unwind-tables. From-SVN: r259702
2018-04-25[NDS32] Fix incorrect settings in sfp-machine.h and t-nds32-newlib for hard fp.Chung-Ju Wu2-1/+20
libgcc/ * config/nds32/sfp-machine.h: Fix settings for NDS32_ABI_2FP_PLUS. * config/nds32/t-nds32-newlib (HOST_LIBGCC2_CFLAGS): Use -fwrapv. From-SVN: r259645
2018-04-24x86: Update __CET__ checkH.J. Lu1-1/+1
__CET__ has been changed by revision 259522: commit d59cfa9a4064339cf2bd2da828c4c133f13e57f0 Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Fri Apr 20 13:30:13 2018 +0000 Define __CET__ for -fcf-protection and remove -mibt to (__CET__ & 1) != 0: -fcf-protection=branch or -fcf-protection=full (__CET__ & 2) != 0: -fcf-protection=return or -fcf-protection=full We should check (__CET__ & 2) != 0 for shadow stack. libgcc/ * config/i386/linux-unwind.h: Add (__CET__ & 2) != 0 check when including "config/i386/shadow-stack-unwind.h". libitm/ * config/x86/sjlj.S (_ITM_beginTransaction): Add (__CET__ & 2) != 0 check for shadow stack. (GTM_longjmp): Likewise. From-SVN: r259621
2018-04-20re PR target/85456 (PowerPC: Using -mabi=ieeelongdouble calls wrong function ↵Michael Meissner5-3/+82
for __builtin_powi.) [libgcc] 2018-04-20 Michael Meissner <meissner@linux.ibm.com> PR target/85456 * config/rs6000/_powikf2.c: New file. Add support for the __builtin_powil function when long double is IEEE 128-bit floating point. * config/rs6000/float128-ifunc.c (__powikf2_resolve): Add __powikf2 support. (__powikf2): Likewise. * config/rs6000/quad-float128.h (__powikf2_sw): Likewise. (__powikf2_hw): Likewise. (__powikf2): Likewise. * config/rs6000/t-float128 (fp128_ppc_funcs): Likewise. * config/rs6000/t-float128-hw (fp128_hw_func): Likewise. (_powikf2-hw.c): Likewise. [gcc] 2018-04-20 Michael Meissner <meissner@linux.ibm.com> PR target/85456 * config/rs6000/rs6000.c (init_float128_ieee): Add support to call __powikf2 when long double is IEEE 128-bit. [gcc/testsuite] 2018-04-20 Michael Meissner <meissner@linux.ibm.com> PR target/85456 * gcc.target/powerpc/pr85456.c: New test. From-SVN: r259533
2018-04-19libgcc/CET: Skip signal frames when unwinding shadow stackH.J. Lu1-0/+5
When -fcf-protection -mcet is used, I got FAIL: g++.dg/eh/sighandle.C (gdb) bt #0 _Unwind_RaiseException (exc=exc@entry=0x416ed0) at /export/gnu/import/git/sources/gcc/libgcc/unwind.inc:140 #1 0x00007ffff7d9936b in __cxxabiv1::__cxa_throw (obj=<optimized out>, tinfo=0x403dd0 <typeinfo for int@@CXXABI_1.3>, dest=0x0) at /export/gnu/import/git/sources/gcc/libstdc++-v3/libsupc++/eh_throw.cc:90 #2 0x0000000000401255 in sighandler (signo=11, si=0x7fffffffd6f8, uc=0x7fffffffd5c0) at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:9 #3 <signal handler called> <<<< Signal frame which isn't on shadow stack #4 dosegv () at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:14 #5 0x00000000004012e3 in main () at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:30 (gdb) p frames $6 = 5 (gdb) frame count should be 4, not 5. This patch skips signal frames when unwinding shadow stack. gcc/testsuite/ PR libgcc/85334 * g++.dg/torture/pr85334.C: New test. libgcc/ PR libgcc/85334 * unwind-generic.h (_Unwind_Frames_Increment): New. * config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment): Likewise. * unwind.inc (_Unwind_RaiseException_Phase2): Increment frame count with _Unwind_Frames_Increment. (_Unwind_ForcedUnwind_Phase2): Likewise. From-SVN: r259502
2018-04-19libgcc/CET: Add _CET_ENDBR to __stack_split_initializeH.J. Lu1-0/+1
Program received signal SIGSEGV, Segmentation fault. __stack_split_initialize () at /export/gnu/import/git/sources/gcc/libgcc/config/i386/morestack.S:751 751 leaq -16000(%rsp),%rax # We should have at least 16K. Missing separate debuginfos, use: dnf debuginfo-install libgcc-8.0.1-0.21.0.fc28.x86_64 (gdb) disass Dump of assembler code for function __stack_split_initialize: => 0x0000000000402858 <+0>: lea -0x3e80(%rsp),%rax 0x0000000000402860 <+8>: mov %rax,%fs:0x70 0x0000000000402869 <+17>: sub $0x8,%rsp 0x000000000040286d <+21>: mov %rsp,%rdi 0x0000000000402870 <+24>: mov $0x3e80,%esi 0x0000000000402875 <+29>: callq 0x401810 <__generic_morestack_set_initial_sp> 0x000000000040287a <+34>: add $0x8,%rsp 0x000000000040287e <+38>: retq End of assembler dump. (gdb) This patch adds the missing ENDBR to __stack_split_initialize. PR libgcc/85379 * config/i386/morestack.S (__stack_split_initialize): Add _CET_ENDBR. From-SVN: r259497
2018-04-16re PR target/84945 (UBSAN: gcc/config/i386/i386.c:33312:22: runtime error: ↵Jakub Jelinek1-1/+8
shift exponent 32 is too large for 32-bit type 'int') PR target/84945 * config/i386/cpuinfo.c (set_feature): Wrap into do while (0) to avoid -Wdangling-else warnings. Mask shift counts to avoid -Wshift-count-negative and -Wshift-count-overflow false positives. From-SVN: r259398
2018-03-29i386: Enable AVX/AVX512 features only if supported by OSXSAVEH.J. Lu1-44/+90
Enable AVX and AVX512 features only if their states are supported by OSXSAVE. PR target/85100 * config/i386/cpuinfo.c (XCR_XFEATURE_ENABLED_MASK): New. (XSTATE_FP): Likewise. (XSTATE_SSE): Likewise. (XSTATE_YMM): Likewise. (XSTATE_OPMASK): Likewise. (XSTATE_ZMM): Likewise. (XSTATE_HI_ZMM): Likewise. (XCR_AVX_ENABLED_MASK): Likewise. (XCR_AVX512F_ENABLED_MASK): Likewise. (get_available_features): Enable AVX and AVX512 features only if their states are supported by OSXSAVE. From-SVN: r258954
2018-03-22Fix PR85025: libgcc/config/i386/shadow-stack-unwind.h is wrong. Igor Tsimbalist1-1/+1
PR target/85025 * config/i386/shadow-stack-unwind.h (_Unwind_Frames_Extra): Fix a typo, tmp => 255. From-SVN: r258763
2018-03-20re PR target/84945 (UBSAN: gcc/config/i386/i386.c:33312:22: runtime error: ↵Jakub Jelinek2-36/+53
shift exponent 32 is too large for 32-bit type 'int') PR target/84945 * config/i386/i386.c (fold_builtin_cpu): For features above 31 use __cpu_features2 variable instead of __cpu_model.__cpu_features[0]. Use 1U instead of 1. Formatting fixes. * gcc.target/i386/pr84945.c: New test. * config/i386/cpuinfo.h (__cpu_features2): Declare. * config/i386/cpuinfo.c (__cpu_features2): New variable for ifndef SHARED only. (set_feature): Define. (get_available_features): Use set_feature macro. Set __cpu_features2 to the second word of features ifndef SHARED. From-SVN: r258673
2018-03-15Add builtin_cpu for cannonlake and new isa features.Julia Koval2-1/+16
gcc/ * config/i386/i386.c (F_AVX512VBMI2, F_GFNI, F_VPCLMULQDQ, F_AVX512VNNI, F_AVX512BITALG): New. gcc/testsuite/ * gcc.target/i386/builtin_target.c (check_intel_cpu_model): Add cannonlake. (check_features): Add avx512vbmi2, gfni, vpclmulqdq, avx512vnni, avx512bitalg. libgcc/ * config/i386/cpuinfo.c (get_available_features): Add FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, FEATURE_AVX512BITALG. * config/i386/cpuinfo.h (processor_features) Add FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, FEATURE_AVX512BITALG. From-SVN: r258551
2018-03-14Split-up -march=icelake on -march=icelake-server and -march=icelake-clientJulia Koval1-1/+2
Split-up -march=icelake on -march=icelake-server and -march=icelake-client gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (PTA_SKYLAKE): Add SGX. (PTA_ICELAKE): Remove. (PTA_ICELAKE_CLIENT): New. (PTA_ICELAKE_SERVER): New. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type): Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake-client and icelake-server. From-SVN: r258518
2018-03-07fptr.c (_dl_read_access_allowed): New.John David Anglin1-0/+20
* config/pa/fptr.c (_dl_read_access_allowed): New. (__canonicalize_funcptr_for_compare): Use it. From-SVN: r258310
2018-02-28re PR debug/83917 (with -mcall-ms2sysv-xlogues, stepping into x86 tail-call ↵Jakub Jelinek2-22/+7
restore stub gives bad backtrace) PR debug/83917 * configure.ac (AS_HIDDEN_DIRECTIVE): AC_DEFINE_UNQUOTED this to $asm_hidden_op if visibility ("hidden") attribute works. (HAVE_AS_CFI_SECTIONS): New AC_DEFINE. * config/i386/i386-asm.h: Don't include auto-host.h. (PACKAGE_VERSION, PACKAGE_NAME, PACKAGE_STRING, PACKAGE_TARNAME, PACKAGE_URL): Don't undefine. (USE_GAS_CFI_DIRECTIVES): Don't use nor define this macro, instead guard cfi_startproc only on ifdef __GCC_HAVE_DWARF2_CFI_ASM. (FN_HIDDEN): Change guard from #ifdef HAVE_GAS_HIDDEN to #ifdef AS_HIDDEN_DIRECTIVE, use AS_HIDDEN_DIRECTIVE macro in the definition instead of hardcoded .hidden. * config/i386/cygwin.S: Include i386-asm.h first before .cfi_sections directive. Use #ifdef HAVE_AS_CFI_SECTIONS rather than #ifdef HAVE_GAS_CFI_SECTIONS_DIRECTIVE to guard .cfi_sections. (USE_GAS_CFI_DIRECTIVES): Don't define. * configure: Regenerated. * config.in: Likewise. From-SVN: r258057
2018-02-26re PR debug/83917 (with -mcall-ms2sysv-xlogues, stepping into x86 tail-call ↵Jakub Jelinek4-22/+52
restore stub gives bad backtrace) PR debug/83917 * config/i386/i386-asm.h (PACKAGE_VERSION, PACKAGE_NAME, PACKAGE_STRING, PACKAGE_TARNAME, PACKAGE_URL): Undefine between inclusion of auto-target.h and auto-host.h. (USE_GAS_CFI_DIRECTIVES): Define if not defined already based on __GCC_HAVE_DWARF2_CFI_ASM. (cfi_startproc, cfi_endproc, cfi_adjust_cfa_offset, cfi_def_cfa_register, cfi_def_cfa, cfi_register, cfi_offset, cfi_push, cfi_pop): Define. * config/i386/cygwin.S: Don't include auto-host.h here, just define USE_GAS_CFI_DIRECTIVES to 1 or 0 and include i386-asm.h. (cfi_startproc, cfi_endproc, cfi_adjust_cfa_offset, cfi_def_cfa_register, cfi_register, cfi_push, cfi_pop): Remove. * config/i386/resms64fx.h: Add cfi_* directives. * config/i386/resms64x.h: Likewise. From-SVN: r258010
2018-02-20libgcc: xtensa: fix build with -mtext-section-literalsMax Filippov2-0/+2
libgcc/ 2018-02-20 Max Filippov <jcmvbkbc@gmail.com> * config/xtensa/ieee754-df.S (__adddf3_aux): Add .literal_position directive. * config/xtensa/ieee754-sf.S (__addsf3_aux): Likewise. From-SVN: r257862
2018-02-16Additional fix for PR 84239.Igor Tsimbalist1-1/+8
PR target/84239 * libgcc/config/i386/shadow-stack-unwind.h (_Unwind_Frames_Extra): Include cetintrin.h not x86intrin.h. From-SVN: r257730
2018-02-14Reimplement CET intrinsics for rdssp/incssp insn.Igor Tsimbalist1-12/+5
Introduce a couple of new CET intrinsics for reading and updating a shadow stack pointer (_get_ssp and _inc_ssp). They replace the existing _rdssp[d|q] and _incssp[d|q] instrinsics. PR target/84239 * gcc/config/i386/cetintrin.h: Remove _rdssp[d|q] and add _get_ssp intrinsics. Remove argument from __builtin_ia32_rdssp[d|q]. * gcc/config/i386/i386-builtin-types.def: Add UINT_FTYPE_VOID. * gcc/config/i386/i386-builtin.def: Remove argument from __builtin_ia32_rdssp[d|q]. * gcc/config/i386/i386.c: Use UINT_FTYPE_VOID. Use ix86_expand_special_args_builtin for _rdssp[d|q]. * gcc/config/i386/i386.md: Remove argument from rdssp[si|di] insn. Clear register before usage. * doc/extend.texi: Remove argument from __builtin_ia32_rdssp[d|q]. Add documentation for new _get_ssp and _inc_ssp intrinsics. * testsuite/gcc.target/i386/cet-intrin-3.c: Use new _get_ssp and _inc_ssp intrinsics. * testsuite/gcc.target/i386/cet-intrin-4.c: Likewise. * testsuite/gcc.target/i386/cet-rdssp-1.c: Remove argument from __builtin_ia32_rdssp[d|q]. * libgcc/config/i386/shadow-stack-unwind.hi (_Unwind_Frames_Extra): Use new _get_ssp and _inc_ssp intrinsics. From-SVN: r257660
2018-02-02Add -march=icelake.Julia Koval1-0/+1
gcc/ * config.gcc: Add -march=icelake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake. * config/i386/i386.c (processor_costs): Add m_ICELAKE. (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2, PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New. (processor_target_table): Add icelake. (ix86_option_override_internal): Handle new PTAs. (get_builtin_code_for_version): Handle icelake. (M_INTEL_COREI7_ICELAKE): New. (fold_builtin_cpu): Handle icelake. * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New. * doc/invoke.texi: Add -march=icelake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.dg/ext/mv16.C: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE. From-SVN: r257331
2018-01-26[ARC] Add support for reduced register file setClaudiu Zissulescu1-11/+11
gcc/ 2018-01-26 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-arches.def: Option mrf16 valid for all architectures. * config/arc/arc-c.def (__ARC_RF16__): New predefined macro. * config/arc/arc-cpus.def (em_mini): New cpu with rf16 on. * config/arc/arc-options.def (FL_RF16): Add mrf16 option. * config/arc/arc-tables.opt: Regenerate. * config/arc/arc.c (arc_conditional_register_usage): Handle reduced register file case. (arc_file_start): Set must have build attributes. * config/arc/arc.h (MAX_ARC_PARM_REGS): Conditional define using mrf16 option value. * config/arc/arc.opt (mrf16): Add new option. * config/arc/elf.h (ATTRIBUTE_PCS): Define. * config/arc/genmultilib.awk: Handle new mrf16 option. * config/arc/linux.h (ATTRIBUTE_PCS): Define. * config/arc/t-multilib: Regenerate. * doc/invoke.texi (ARC Options): Document mrf16 option. libgcc/ 2018-01-26 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16 option. (__divsi3): Use RF16 safe registers. (__modsi3): Likewise. From-SVN: r257083
2018-01-23libgcc: xtensa: fix NaN return from add/sub/mul/div helpersMax Filippov2-31/+74
libgcc/ 2018-01-23 Max Filippov <jcmvbkbc@gmail.com> * config/xtensa/ieee754-df.S (__addsf3, __subsf3, __mulsf3) (__divsf3): Make NaN return value quiet. * config/xtensa/ieee754-sf.S (__adddf3, __subdf3, __muldf3) (__divdf3): Make NaN return value quiet. From-SVN: r257002
2018-01-22rl78.md: New define_expand "anddi3".Sebastian Perta2-1/+68
2018-01-22 Sebastian Perta <sebastian.perta@renesas.com> * config/rl78/rl78.md: New define_expand "anddi3". 2018-01-22 Sebastian Perta <sebastian.perta@renesas.com> * config/rl78/anddi3.S: New assembly file. * config/rl78/t-rl78: Added anddi3.S to LIB2ADD. From-SVN: r256958
2018-01-22rl78.md: New define_expand "umindi3".Sebastian Perta2-0/+75
2018-01-22 Sebastian Perta <sebastian.perta@renesas.com> * config/rl78/rl78.md: New define_expand "umindi3". 2018-01-22 Sebastian Perta <sebastian.perta@renesas.com> * config/rl78/umindi3.S: New assembly file. * config/rl78/t-rl78: Added umindi3.S to LIB2ADD. From-SVN: r256957
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