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2023-02-03arm: Fix warning in libgcc/config/arm/pr-support.cChristophe Lyon1-0/+6
I have noticed some warnings when building GCC for arm-eabi: pr-support.c:110:7: warning: variable ‘set_pac_sp’ set but not used [-Wunused-but-set-variable] pr-support.c:109:7: warning: variable ‘set_pac’ set but not used [-Wunused-but-set-variable] This small patch avoids them by defining these two variables undef TARGET_HAVE_PACBTI, like the code which actually uses them. libgcc/ * config/arm/pr-support.c (__gnu_unwind_execute): Use TARGET_HAVE_PACBTI to define set_pac and set_pac_sp.
2023-01-23arm: Add support for new frame unwinding instruction "0xb5".Srinath Parvathaneni1-2/+13
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When an exception is taken and "0xb5" instruction is encounter during runtime stack-unwinding, we use effective vsp as modifier in pointer authentication. On completion of stack unwinding if "0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf libgcc/ChangeLog: 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/pr-support.c (__gnu_unwind_execute): Decode opcode "0xb5".
2023-01-23[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtimeAndrea Corallo2-0/+60
This patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feature is switched on for the architecture. This means that switching on the target feature via -march or -mcpu is sufficient and -mbranch-protection need not be enabled. This ensures that the unwinder is authenticated only if the PACBTI instructions are available in the non-NOP space as it uses AUTG. Just generating PAC/AUT instructions using -mbranch-protection will not enable authentication on the unwinder. Pre-approved with the requested changes here <https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586555.html>. gcc/ChangeLog: * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce new pseudo register class _UVRSC_PAC. libgcc/ChangeLog: * config/arm/pr-support.c (__gnu_unwind_execute): Decode exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate with AUTG if found. * config/arm/unwind-arm.c (struct pseudo_regs): New. (phase1_vrs): Introduce new field to store pseudo-reg state. (phase2_vrs): Likewise. (_Unwind_VRS_Get): Load pseudo register state from virtual reg set. (_Unwind_VRS_Set): Store pseudo register state to virtual reg set. (_Unwind_VRS_Pop): Load pseudo register value from stack into VRS. Co-Authored-By: Tejas Belagod <tbelagod@arm.com> Co-Authored-By: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2023-01-16Update copyright years.Jakub Jelinek24-24/+24
2023-01-13arm: unified syntax for libgcc clear_cacheSeija Kijin1-1/+1
The patch to convert all thumb1 code in libgcc to unified syntax omitted changing all swi instructions to the current name: svc. libgcc/ChangeLog: * config/arm/lib1funcs.S (clear_cache): Use SVC to conform to unified syntax.
2022-01-03Update copyright years.Jakub Jelinek24-24/+24
2021-08-24arm: add erratum mitigation to __gnu_cmse_nonsecure_call [PR102035]Richard Earnshaw1-0/+5
Add the recommended erratum mitigation sequence to __gnu_cmse_nonsecure_call for use on Armv8-m.main devices. Since this is in the library code we cannot know in advance whether the core we are running on will be affected by this, so always enable it. libgcc: PR target/102035 * config/arm/cmse_nonsecure_call.S (__gnu_cmse_nonsecure_call): Add vlldm erratum work-around.
2021-06-11arm: Fix the mve multilib for the broken cmse support (pr99939).Srinath Parvathaneni2-5/+4
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken as specified in PR99939 and this patch fixes the issue. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assembly output. * gcc.target/arm/cmse/cmse-20.c: New test. libgcc/ChangeLog: 2021-06-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/99939 * config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE macro. * config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o on passing -mcmse option.
2021-02-24arm: Fix CMSE support detection in libgcc (PR target/99157)Christophe Lyon1-1/+1
As discussed in the PR, the Makefile fragment lacks a double '$' to get the return-code from GCC invocation, resulting is CMSE support missing from multilibs. I checked that the simple patch proposed in the PR fixes the problem. 2021-02-23 Christophe Lyon <christophe.lyon@linaro.org> Hau Hsu <hsuhau617@gmail.com> PR target/99157 libgcc/ * config/arm/t-arm: Fix cmse support detection.
2021-01-04Update copyright years.Jakub Jelinek24-24/+24
2020-09-17libgcc/config/arm/fp16.c: Make _internal functions static inlineChristophe Lyon1-1/+9
This patch makes the *_internal functions 'static inline' to avoid these warnings during the build: /libgcc/config/arm/fp16.c:169:1: warning: no previous prototype for '__gnu_h2f_internal' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:194:1: warning: no previous prototype for '__gnu_f2h_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:200:1: warning: no previous prototype for '__gnu_h2f_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:206:1: warning: no previous prototype for '__gnu_f2h_alternative' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:212:1: warning: no previous prototype for '__gnu_h2f_alternative' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:218:1: warning: no previous prototype for '__gnu_d2h_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:224:1: warning: no previous prototype for '__gnu_d2h_alternative' [-Wmissing-prototypes] 2020-09-11 Torbjörn SVENSSON <torbjorn.svensson@st.com> Christophe Lyon <christophe.lyon@linaro.org> libgcc/ * config/arm/fp16.c (__gnu_h2f_internal): Add 'static inline' qualifier. (__gnu_f2h_ieee, __gnu_h2f_ieee, __gnu_f2h_alternative) (__gnu_h2f_alternative,__gnu_d2h_ieee, __gnu_d2h_alternative): Add missing prototypes.
2020-03-26arm: unified syntax for libgcc when built with -Os [PR94220]Richard Earnshaw1-16/+17
The recent patch to convert all thumb1 code in libgcc to unified syntax ommitted the conditional code that is used only when building the library for minimal size. This patch fixes this case. I've also fixed the COND macro so that a single definition is always used that is for unified syntax. This eliminates a warning that is now being seen from the assembler when compiling the ieee fp support code. PR target/94220 * config/arm/lib1funcs.asm (COND): Use a single definition for unified syntax. (aeabi_uidivmod): Unified syntax when optimizing Thumb for size. (aeabi_idivmod): Likewise. (divsi3_skip_div0_test): Likewise.
2020-03-17[GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE with -mfloat-abi=hardMihail Ionescu1-0/+3
This patch adds a new multilib for armv8.1-m.main+mve with hard float abi. For armv8.1-m.main+mve soft and softfp, the v8-M multilibs will be reused. The following mappings are also updated: "-mfloat-abi=hard -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/hard" "-mfloat-abi=softfp -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/softfp" "-mfloat-abi=soft -march=armv8.1-m.main+mve.fp -> armv8-m.main/nofp" gcc/ChangeLog: 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com> * config/arm/t-rmprofile: create new multilib for armv8.1-m.main+mve hard float and reuse v8-m.main ones for v8.1-m.main+mve . gcc/testsuite/ChangeLog: 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com> * gcc.target/arm/multilib.exp: Add new v8.1-M entry. libgcc/ChangLog: 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com> * config/arm/t-arm: Do not compile cmse_nonsecure_call.S for v8.1-m.
2020-03-03libgcc: arm: convert thumb1 code to unified syntaxRichard Earnshaw3-277/+296
Unified syntax has been the official syntax for thumb1 assembly for over 10 years now. It's time we made preparations for that becoming the default in the assembler. But before we can start doing that we really need to clean up some laggards from the olden days. Libgcc support for thumb1 is one such example. This patch converts all of the legacy (disjoint) syntax that I could find over to unified code. The identification was done by using a trick version of gas that defaulted to unified mode which then faults if legacy syntax is encountered. The code produced was then compared against the old code to check for differences. One such difference does exist, but that is because in unified syntax 'movs rd, rn' is encoded as 'lsls rd, rn, #0', rather than 'adds rd, rn, #0'; but that is a deliberate change that was introduced because the lsls encoding more closely reflects the behaviour of 'movs' in arm state (where only some of the condition flags are modified). * config/arm/bpabi-v6m.S (aeabi_lcmp): Convert thumb1 code to unified syntax. (aeabi_ulcmp, aeabi_ldivmod, aeabi_uldivmod): Likewise. (aeabi_frsub, aeabi_cfcmpeq, aeabi_fcmpeq): Likewise. (aeabi_fcmp, aeabi_drsub, aeabi_cdrcmple): Likewise. (aeabi_cdcmpeq, aeabi_dcmpeq, aeabi_dcmp): Likewise. * config/arm/lib1funcs.S (Lend_fde): Convert thumb1 code to unified syntax. (divsi3, modsi3): Likewise. (clzdi2, ctzsi2): Likewise. * config/arm/libunwind.S (restore_core_regs): Convert thumb1 code to unified syntax. (UNWIND_WRAPPER): Likewise.
2020-02-07arm: Fix up arm installed unwind.h for use in pedantic modes [PR93615]Jakub Jelinek1-9/+5
As the following testcase shows, unwind.h on ARM can't be (starting with GCC 10) compiled with -std=c* modes, only -std=gnu* modes. The problem is it uses asm keyword, which isn't a keyword in those modes (system headers vs. non-system ones don't make a difference here). glibc and other installed headers use __asm or __asm__ keywords instead that work fine in both standard and gnu modes. While there, as it is an installed header, I think it is also wrong to completely ignore any identifier namespace rules. The generic unwind.h defines just _Unwind* namespace identifiers plus _sleb128_t/_uleb128_t (but e.g. unlike libstdc++/glibc headers doesn't uglify operand names), the ARM unwind.h is much worse here. I've just changed the gnu_Unwind_Find_got function at least not be in user identifier namespace, but perhaps it would be good to go further and rename e.g. or e.g. typedef _Unwind_Reason_Code (*personality_routine) (_Unwind_State, _Unwind_Control_Block *, _Unwind_Context *); in unwind-arm-common.h. 2020-02-07 Jakub Jelinek <jakub@redhat.com> PR target/93615 * config/arm/unwind-arm.h (gnu_Unwind_Find_got): Rename to ... (_Unwind_gnu_Find_got): ... this. Use __asm instead of asm. Remove trailing :s in asm. Formatting fixes. (_Unwind_decode_typeinfo_ptr): Adjust caller. * gcc.dg/pr93615.c: New test.
2020-01-16[PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgccMihail Ionescu1-1/+1
This patch is part of a patch series to add support for Armv8.1-M Mainline Security Extensions architecture. Code to detect whether cmse.c can be buit with -mcmse checks the output of host GCC when invoked with -mcmse. However, an error from the compiler does not prevent some minimal output so this always holds true. 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/t-arm: Check return value of gcc rather than lack of output.
2020-01-01Update copyright years.Jakub Jelinek24-24/+24
From-SVN: r279813
2019-11-14Update the arm-*-vxworks* supportJerome Lambourg1-10/+55
2019-11-13 Jerome Lambourg <lambourg@adacore.com> Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc: Collapse the arm-vxworks entries into a single arm-wrs-vxworks7* one, bpabi based. Update the default cpu from arm8 to armv7-a * config/arm/vxworks.h (CC1_SPEC): Simplify, knowing that we always use ARM_UNWIND_INFO. (DWARF2_UNWIND_INFO): Remove redefinition. (ARM_TARGET2_DWARF_FORMAT): Likewise. (VXWORKS_PERSONALITY): Define, to "llvm". (VXWORKS_EXTRA_LIBS_RTP): Define, to "-lllvm". libgcc/ * config.host: Collapse the arm-vxworks entries into a single arm-wrs-vxworks7* one. * config/arm/unwind-arm-vxworks.c: Update comments. Provide __gnu_Unwind_Find_exidx and a weak dummy __cxa_type_match for kernel modules, to be overriden by libstdc++ when we link with it. Rely on externally provided __exidx_start/end. Co-Authored-By: Doug Rupp <rupp@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r278253
2019-09-20Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M ↵Christophe Lyon1-5/+0
architecture This is causing regressions when mixing with user code compiled in ARM mode. 2019-09-20 Christophe Lyon <christophe.lyon@st.com> Revert: 2019-09-10 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only architecture. From-SVN: r276001
2019-09-10[ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architectureChristophe Lyon1-0/+5
Without this, when we are unwinding across a signal frame we can jump to an even address which leads to an exception. This is needed in __gnu_persnality_sigframe_fdpic() when restoring the PC from the signal frame since the PC saved by the kernel has the LSB bit set to zero. 2019-09-10 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> libgcc/ * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only architecture. Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> From-SVN: r275575
2019-09-10[ARM/FDPIC v6 06/24] [ARM] FDPIC: Add support for c++ exceptionsChristophe Lyon2-3/+83
The main difference with existing support is that function addresses are function descriptor addresses instead. This means that all code dealing with function pointers now has to cope with function descriptors instead. For the same reason, Linux kernel helpers can no longer be called by dereferencing their address, so we implement wrappers that directly call the kernel helpers. When restoring a function address, we also have to restore the FDPIC register value (r9). 2019-09-10 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> gcc/ * ginclude/unwind-arm-common.h (unwinder_cache): Add reserved5 field. libgcc/ * config/arm/linux-atomic.c (__kernel_cmpxchg): Add FDPIC support. (__kernel_dmb): Likewise. (__fdpic_cmpxchg): New function. (__fdpic_dmb): New function. * config/arm/unwind-arm.h (FDPIC_REGNUM): New define. (gnu_Unwind_Find_got): New function. (_Unwind_decode_typeinfo_ptr): Add FDPIC support. * unwind-arm-common.inc (UCB_PR_GOT): New. (funcdesc_t): New struct. (get_eit_entry): Add FDPIC support. (unwind_phase2): Likewise. (unwind_phase2_forced): Likewise. (__gnu_Unwind_RaiseException): Likewise. (__gnu_Unwind_Resume): Likewise. (__gnu_Unwind_Backtrace): Likewise. * unwind-pe.h (read_encoded_value_with_base): Likewise. libstdc++/ * libsupc++/eh_personality.cc (get_ttype_entry): Add FDPIC support. Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> From-SVN: r275568
2019-07-31[Arm][CMSE]Add warn_unused_return attribute to cmse functionsJoel Hutton1-0/+1
At present it is possible to call the CMSE functions for checking addresses (such as cmse_check_address_range) and forget to check/use the return value. This patch makes the interfaces more robust against programmer error by marking these functions with the warn_unused_result attribute. With this set, any use of these functions that does not use the result will produce a warning. This produces a warning on default warn levels when the result of the cmse functions is not used. For the following function: void foo() { int *data; cmse_check_address_range((int*)data, 0, 0); } The following warning is emitted: warning: ignoring return value of 'cmse_check_address_range' declared with attribute 'warn_unused_result' [-Wunused-result] 6 | cmse_check_address_range((int*)data, 0, 0); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ gcc/ChangeLog: 2019-07-31 Joel Hutton <Joel.Hutton@arm.com> * config/arm/arm_cmse.h (cmse_nonsecure_caller): Add warn_unused_result attribute. (cmse_check_address_range): Add warn_unused_result attribute. libgcc/ChangeLog: 2019-07-31 Joel Hutton <Joel.Hutton@arm.com> * config/arm/cmse.c (cmse_check_address_range): Add warn_unused_result attribute. 2019-07-31 Joel Hutton <Joel.Hutton@arm.com> * gcc.target/arm/cmse/cmse-17.c: New test. From-SVN: r273924
2019-06-14[NetBSD] Add support for the Arm EABI.Matt Thomas2-0/+26
This is a roll-up of a set of changes needed to support the Arm EABI on NetBSD. 2019-06-14 Matt Thomas <matt@3am-software.com> Matthew Green <mrg@eterna.com.au> Nick Hudson <skrll@netbsd.org> Maya Rashish <coypu@sdf.org> Richard Earnshaw <rearnsha@arm.com> gcc: * config.gcc (arm*-*-netbsdelf*) Add support for EABI configuration. * config.host (arm*-*-netbsd*): Use driver-arm.o on native NetBSD. * config/arm/netbsd-eabi.h: New file. * config/arm/netbsd-elf.h (TARGET_OS_CPP_BUILTINS): Undefine before redefining. (SUBTARGET_EXTRA_ASM_SPEC): Don't pass -matpcs to the assembler. * config/netbsd-elf.h (NETBSD_LINK_LD_ELF_SO_SPEC): New define. (NETBSD_SUBTARGET_EXTRA_SPECS): New define. (SUBTARGET_EXTRA_SPECS): Define to NETBSD_SUBTARGET_EXTRA_SPECS. libatomic: * configure.tgt (arm*): Handle NetBSD in the same way as FreeBSD. libgcc: * config.host (arm*-*-netbsdelf*): Add support for EABI configurations. * config/arm/t-netbsd (LIB1ASMFUNCS): Add some additional assembler functions to build. * config/arm/t-netbsd-eabi: New file. Co-Authored-By: Matthew Green <mrg@eterna.com.au> Co-Authored-By: Maya Rashish <coypu@sdf.org> Co-Authored-By: Nick Hudson <skrll@netbsd.org> Co-Authored-By: Richard Earnshaw <rearnsha@arm.com> From-SVN: r272290
2019-04-23re PR target/89093 (C++ exception handling clobbers d8 VFP register)Ramana Radhakrishnan2-0/+2
PR target/89093 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Diagnose if used with general-regs-only. (arm_conditional_register_usage): Don't add non-general regs if general-regs-only. (arm_valid_target_attribute_rec): Handle general-regs-only. * config/arm/arm.h (TARGET_HARD_FLOAT): Return false if general-regs-only. (TARGET_HARD_FLOAT_SUB): Define. (TARGET_SOFT_FLOAT): Define as negation of TARGET_HARD_FLOAT_SUB. (TARGET_REALLY_IWMMXT): Add && !TARGET_GENERAL_REGS_ONLY. (TARGET_REALLY_IWMMXT2): Likewise. * config/arm/arm.opt: Add -mgeneral-regs-only. * doc/extend.texi: Document ARM general-regs-only target. * doc/invoke.texi: Document ARM -mgeneral-regs-only. libgcc/ * config/arm/pr-support.c: Add #pragma GCC target("general-regs-only"). * config/arm/unwind-arm.c: Likewise. * unwind-c.c (PERSONALITY_FUNCTION): Add general-regs-only target attribute for ARM. libobjc/ * exception.c (PERSONALITY_FUNCTION): Add general-regs-only target attribute for ARM. libphobos/ * libdruntime/gcc/deh.d: Import gcc.attribute. (personality_fn_attributes): New enum. (scanLSDA, CONTINUE_UNWINDING, gdc_personality, __gdc_personality): Add @personality_fn_attributes. libstdc++-v3/ * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): Add general-regs-only target attribute for ARM. Co-Authored-By: Bernd Edlinger <bernd.edlinger@hotmail.de> Co-Authored-By: Jakub Jelinek <jakub@redhat.com> From-SVN: r270504
2019-01-01Update copyright years.Jakub Jelinek24-24/+24
From-SVN: r267494
2018-12-19[ARM] Optimize executable size when using softfloat fmul/dmulThomas Preud'homme4-15/+52
Softfloat single precision and double precision floating-point multiplication routines in libgcc share some code with the floating-point division of their corresponding precision. As the code is structured now, this leads to *all* division code being pulled in an executable in softfloat mode even if only multiplication is performed. This patch create some new LIB1ASMFUNCS macros to also build files with just the multiplication and shared code as weak symbols. By putting these earlier in the static library, they can then be picked up when only multiplication is used and they are overriden by the global definition in the existing file containing both multiplication and division code when division is needed. The patch also removes changes made to the FUNC_START and ARM_FUNC_START macros in r218124 since the intent was to put multiplication and division code into their own section in a later patch to achieve the same size optimization. That approach relied on specific section layout to ensure multiplication and division were not too far from the shared bit of code in order to the branches to be within range. Due to lack of guarantee regarding section layout, in particular with all the possibility of linker scripts, this approach was chosen instead. This patch keeps the two testcases that were posted by Tony Wang on the mailing list to implement this approach and adds a new one. 2018-12-19 Thomas Preud'homme <thomas.preudhomme@linaro.org> libgcc/ * /config/arm/lib1funcs.S (FUNC_START): Remove unused sp_section parameter and corresponding code. (ARM_FUNC_START): Likewise in both definitions. Also update footer comment about condition that need to match with gcc/config/arm/elf.h to also include libgcc/config/arm/t-arm. * config/arm/ieee754-df.S (muldf3): Also build it if L_arm_muldf3 is defined. Weakly define it in this case. * config/arm/ieee754-sf.S (mulsf3): Likewise with L_arm_mulsf3. * config/arm/t-elf (LIB1ASMFUNCS): Build _arm_muldf3.o and _arm_mulsf3.o before muldiv versions if targeting Thumb-1 only. Add comment to keep condition in sync with the one in libgcc/config/arm/lib1funcs.S and gcc/config/arm/elf.h. gcc/ * config/arm/elf.h: Update comment about condition that need to match with libgcc/config/arm/lib1funcs.S to also include libgcc/config/arm/t-arm. * doc/sourcebuild.texi (output-exists, output-exists-not): Rename subsubsection these directives are in to "Check for output files". Move scan-symbol to that section and add to it new scan-symbol-not directive. 2018-12-19 Tony Wang <tony.wang@arm.com> Thomas Preud'homme <thomas.preudhomme@linaro.org> gcc/testsuite/ * lib/lto.exp (lto-execute): Define output_file and testname_with_flags to same value as execname. (scan-symbol): Move and rename to ... * lib/gcc-dg.exp (scan-symbol-common): This. Adapt into a helper function returning true or false if a symbol is present. (scan-symbol): New procedure. (scan-symbol-not): Likewise. * gcc.target/arm/size-optimization-ieee-1.c: New testcase. * gcc.target/arm/size-optimization-ieee-2.c: Likewise. * gcc.target/arm/size-optimization-ieee-3.c: Likewise. From-SVN: r267282
2018-08-23PR target/86951 arm - Handle speculation barriers on pre-armv7 CPUsRichard Earnshaw2-1/+45
The AArch32 instruction sets prior to Armv7 do not define the ISB and DSB instructions that are needed to form a speculation barrier. While I do not know of any instances of cores based on those instruction sets being vulnerable to speculative side channel attacks it is possible to run code built for those ISAs on more recent hardware where they would become vulnerable. This patch works around this by using a library call added to libgcc. That code can then take any platform-specific actions necessary to ensure safety. For the moment I've only handled two cases: the library code being built for armv7 or later anyway and running on Linux. On Linux we can handle this by calling the kernel function that will flush a small amount of cache. Such a sequence ends with a ISB+DSB sequence if running on an Armv7 or later CPU. gcc: PR target/86951 * config/arm/arm-protos.h (arm_emit_speculation_barrier): New prototype. * config/arm/arm.c (speculation_barrier_libfunc): New static variable. (arm_init_libfuncs): Initialize it. (arm_emit_speculation_barrier): New function. * config/arm/arm.md (speculation_barrier): Call arm_emit_speculation_barrier for architectures that do not have DSB or ISB. (speculation_barrier_insn): Only match on Armv7 or later. libgcc: PR target/86951 * config/arm/lib1funcs.asm (speculation_barrier): New function. * config/arm/t-arm (LIB1ASMFUNCS): Add it to list of functions to build. From-SVN: r263806
2018-08-02arm - correctly handle denormal results during softfp subtractionNicolas Pitre2-9/+11
2018-08-02 Nicolas Pitre <nico@fluxnic.net> PR libgcc/86512 * config/arm/ieee754-df.S (adddf3): Don't shortcut denormal handling when exponent goes negative. Update my email address. * config/arm/ieee754-sf.S (addsf3): Likewise. From-SVN: r263267
2018-07-30[ARM] libgcc: Fix comment for code working on architectures >= 4.Christophe Lyon2-2/+2
2018-07-30 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/ieee754-df.S: Fix comment for code working on architectures >= 4. * config/arm/ieee754-sf.S: Likewise. From-SVN: r263066
2018-06-21[ARM] Use __ARM_ARCH and __ARM_FEATURE_LDREX instead of __ARM_ARCH__Christophe Lyon4-77/+27
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> libatomic/ * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX and HAVE_STREXBHD libgcc/ * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use __ARM_ARCH and __ARM_FEATURE_CLZ instead. (HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead. * config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of __ARM_ARCH__. * config/arm/ieee754-sf.S: Likewise. * config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__. From-SVN: r261841
2018-06-21[ARM] libgcc: Remove unsupported code for __ARM_ARCH__ < 4Christophe Lyon2-103/+2
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> libgcc/ * config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no longer supported. * config/arm/ieee754-sf.S: Likewise. From-SVN: r261840
2018-05-18[arm][1/2] Remove support for deprecated -march=armv5 and armv5eKyrylo Tkachov1-2/+2
The -march=armv5 and armv5e options have been deprecated in GCC 7 [1]. This patch removes support for them. It's mostly mechanical stuff. The functionality that was previously gated on arm_arch5 is now gated on arm_arch5t and the functionality that was gated on arm_arch5e is now gated on arm_arch5te. A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and therefore is deleted. References to armv5 and armv5e are deleted/updated throughout the source tree and testsuite. Bootstrapped and tested on arm-none-linux-gnueabihf. Also built a cc1 for arm-wrs-vxworks as a sanity check. * config/arm/arm-cpus.in (armv5, armv5e): Delete features. (armv5t, armv5te): New features. (ARMv5, ARMv5e): Delete fgroups. (ARMv5t, ARMv5te): Adjust for above changes. (ARMv6m): Likewise. (armv5, armv5e): Delete arches. * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of arm_arch5. (*call_reg_arm): Likewise. (*call_value_reg_armv5): Likewise. (*call_value_reg_arm): Likewise. (*call_symbol): Likewise. (*call_value_symbol): Likewise. (*sibcall_insn): Likewise. (*sibcall_value_insn): Likewise. (clzsi2): Likewise. (prefetch): Likewise. (define_split and define_peephole2 dependent on arm_arch5): Likewise. * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of arm_arch5e. (TARGET_ARM_QBIT): Likewise. (TARGET_DSP_MULTIPLY): Likewise. (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E. (arm_arch5, arm_arch5e): Delete. (arm_arch5t, arm_arch5te): Declare. * config/arm/arm.c (arm_arch5, arm_arch5e): Delete. (arm_arch5t): Declare. (arm_option_reconfigure_globals): Update for the above. (arm_options_perform_arch_sanity_checks): Update comment, replace use of arm_arch5 with arm_arch5t. (use_return_insn): Likewise. (arm_emit_call_insn): Likewise. (output_return_instruction): Likewise. (arm_final_prescan_insn): Likewise. (arm_coproc_builtin_available): Likewise. * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and arm_arch5e with arm_arch5t and arm_arch5te. * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete. (arm_arch5t, arm_arch5te): Declare. * config/arm/arm-tables.opt: Regenerate. * config/arm/t-arm-elf: Remove references to armv5, armv5e. * config/arm/t-multilib: Likewise. * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t instead of arm_arch5. (*call_reg_thumb1): Likewise. (*call_value_reg_thumb1_v5): Likewise. (*call_value_reg_thumb1): Likewise. * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now unreachable path. * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e. * gcc.target/arm/pr40887.c: Update comment. * lib/target-supports.exp: Don't generate effective target checks and related helpers for armv5. Update comment. * gcc.target/arm/armv5_thumb_isa.c: Delete. * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective target check and options. * config/arm/libunwind.S: Update comment relating to armv5. From-SVN: r260362
2018-05-17arm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.Jerome Lambourg1-2/+3
2018-05-17 Jerome Lambourg <lambourg@adacore.com> gcc/ * config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove #include <stdint.h>. Replace intptr_t with __INTPTR_TYPE__. libgcc/ * config/arm/cmse.c (cmse_check_address_range): Replace UINTPTR_MAX with __UINTPTR_MAX__ and uintptr_t with __UINTPTR_TYPE__. From-SVN: r260330
2018-04-27re PR libgcc/84292 (__sync_add_and_fetch returns the old value instead of ↵Andreas Tobler1-11/+11
the new value) 2018-04-27 Andreas Tobler <andreast@gcc.gnu.org> Maryse Levavasseur <maryse.levavasseur@stormshield.eu> PR libgcc/84292 * config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the op_and_fetch to return the right result. Co-Authored-By: Maryse Levavasseur <maryse.levavasseur@stormshield.eu> From-SVN: r259722
2018-01-03Update copyright years.Jakub Jelinek24-24/+24
From-SVN: r256169
2017-08-01config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as ↵Jerome Lambourg2-0/+34
arm-wrs-vxworks. 2017-08-01 Jerome Lambourg <lambourg@adacore.com> Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. Update target_cpu_name from arm6 (arch v3) to arm8 (arch v4). * config/arm/vxworks.h (MAYBE_TARGET_BPABI_CPP_BUILTINS): New, helper for TARGET_OS_CPP_BUILTIN. (TARGET_OS_CPP_BUILTIN): Invoke MAYBE_TARGET_BPABI_CPP_BUILTINS(), refine CPU definitions for arm_arch5 and add those for arm_arch6 and arm_arch7. (MAYBE_ASM_ABI_SPEC): New, helper for SUBTARGET_EXTRA_ASM_SPEC, passing required abi options to the assembler for EABI configurations. (EXTRA_CC1_SPEC): New macro, to help prevent the implicit production of .text.hot and .text.unlikely sections for kernel modules when using ARM style exceptions. (CC1_SPEC): Remove obsolete attempt at mimicking Diab toolchain options. Add EXTRA_CC1_SPEC. (VXWORKS_ENDIAN_SPEC): Adjust comment and remove handling of Diab toolchain options. (DWARF2_UNWIND_INFO): Redefine to handle the pre/post VxWorks 7 transition. (ARM_TARGET2_DWARF_FORMAT): Define. * config/arm/t-vxworks: Adjust multilib control to removal of the Diab command line options. libgcc/ * config.host (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. * config/arm/t-vxworks7: New file. Add unwind-arm-vxworks.c to LIB2ADDEH. * config/arm/unwind-arm-vxworks.c: New file. Provide dummy __exidx_start and __exidx_end for downloadable modules. Co-Authored-By: Doug Rupp <rupp@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r250781
2017-07-06Add support for ARMv8-R architectureThomas Preud'homme1-1/+1
2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm-cpus.in (armv8-r): Add new entry. * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R enumerator. * doc/invoke.texi: Mention -march=armv8-r and its extensions. gcc/testsuite/ * lib/target-supports.exp: Generate check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r and check_effective_target_arm_arch_v8r_multilib. libgcc/ * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. From-SVN: r250025
2017-06-16[arm] Explicitly set .fpu in cmse_nonsecure_call.SRichard Earnshaw1-0/+8
This file is missing a .fpu directive and was relying on the compiler driver passing through a -mfpu= command line option. When the FPU is auto, that will not be passed through correctly, so set something suitable within the file itself. libgcc: * config/arm/cmse_nonsecure_call.S: Explicitly set the FPU. From-SVN: r249297
2017-05-17unwind-arm.h: Make _Unwind_GetIP...Andreas Tobler2-0/+29
2017-05-17 Andreas Tobler <andreast@gcc.gnu.org> * config/arm/unwind-arm.h: Make _Unwind_GetIP, _Unwind_GetIPInfo and _Unwind_SetIP available as functions for arm*-*-freebsd*. * config/arm/unwind-arm.c: Implement the above. From-SVN: r248173
2017-05-06Add fuchsia support to libgccJoshua Conner1-1/+1
* config/arm/unwind-arm.h (_Unwind_decode_typeinfo_ptr): Use pc-relative indirect handling for fuchsia. * config/t-slibgcc-fuchsia: New file. * config.host (*-*-fuchsia*, aarch64*-*-fuchsia*, arm*-*-fuchsia*, x86_64-*-fuchsia*): Add definitions. From-SVN: r247710
2017-01-01Update copyright years.Jakub Jelinek23-23/+23
From-SVN: r243994
2016-12-02ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_callAndre Vieira2-0/+133
gcc/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (detect_cmse_nonsecure_call): New. (cmse_nonsecure_call_clear_caller_saved): New. (arm_reorg): Use cmse_nonsecure_call_clear_caller_saved. (arm_function_ok_for_sibcall): Disable sibcalls for cmse_nonsecure_call. * config/arm/arm-protos.h (detect_cmse_nonsecure_call): New. * config/arm/arm.md (call): Handle cmse_nonsecure_entry. (call_value): Likewise. (nonsecure_call_internal): New. (nonsecure_call_value_internal): New. * config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New. (*nonsecure_call_value_reg_thumb1_v5): New. * config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New. (*nonsecure_call_value_reg_thumb2): New. * config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New. libgcc/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/cmse_nonsecure_call.S: New. * config/arm/t-arm: Compile cmse_nonsecure_call.S gcc/testsuite/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir. * gcc.target/arm/cmse/cmse-9.c: Added some extra tests. * gcc.target/arm/cmse/cmse-14.c: New. * gcc.target/arm/cmse/baseline/bitfield-4.c: New. * gcc.target/arm/cmse/baseline/bitfield-5.c: New. * gcc.target/arm/cmse/baseline/bitfield-6.c: New. * gcc.target/arm/cmse/baseline/bitfield-7.c: New. * gcc.target/arm/cmse/baseline/bitfield-8.c: New. * gcc.target/arm/cmse/baseline/bitfield-9.c: New. * gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New. * gcc.target/arm/cmse/baseline/cmse-11.c: New. * gcc.target/arm/cmse/baseline/cmse-13.c: New. * gcc.target/arm/cmse/baseline/cmse-6.c: New. * gcc.target/arm/cmse/baseline/union-1.c: New. * gcc.target/arm/cmse/baseline/union-2.c: New. * gcc.target/arm/cmse/mainline/bitfield-4.c: New. * gcc.target/arm/cmse/mainline/bitfield-5.c: New. * gcc.target/arm/cmse/mainline/bitfield-6.c: New. * gcc.target/arm/cmse/mainline/bitfield-7.c: New. * gcc.target/arm/cmse/mainline/bitfield-8.c: New. * gcc.target/arm/cmse/mainline/bitfield-9.c: New. * gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: New. * gcc.target/arm/cmse/mainline/union-1.c: New. * gcc.target/arm/cmse/mainline/union-2.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-13.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-7.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-8.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-13.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-7.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-8.c: New. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New. Co-Authored-By: Thomas Preud'homme <thomas.preudhomme@arm.com> From-SVN: r243192
2016-12-02Add support for ARMv8-M's Secure Extensions flag and intrinsicsAndre Vieira2-0/+120
gcc/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config.gcc (extra_headers): Added arm_cmse.h. * config/arm/arm-arches.def (ARM_ARCH): (armv8-m): Add FL2_CMSE. (armv8-m.main): Likewise. (armv8-m.main+dsp): Likewise. * config/arm/arm-c.c (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. * config/arm/arm-flags.h: Define FL2_CMSE. * config/arm.c (arm_arch_cmse): New. (arm_option_override): New error for unsupported cmse target. * config/arm/arm.h (arm_arch_cmse): New. * config/arm/arm.opt (mcmse): New. * config/arm/arm_cmse.h: New file. * doc/invoke.texi (ARM Options): Add -mcmse. * doc/sourcebuild.texi (arm_cmse_ok): Add new effective target. * doc/extend.texi: Add ARMv8-M Security Extensions entry. gcc/testsuite/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse.exp: New. * gcc.target/arm/cmse/cmse-1.c: New. * gcc.target/arm/cmse/cmse-12.c: New. * lib/target-supports.exp (check_effective_target_arm_cmse_ok): New. libgcc/ChangeLog: 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/t-arm (HAVE_CMSE): New. * config/arm/cmse.c: New. Co-Authored-By: Thomas Preud'homme <thomas.preudhomme@arm.com> From-SVN: r243187
2016-11-23[Patch 15/17 libgcc ARM] Add double to half conversions.James Greenhalgh1-0/+27
libgcc/ * config/arm/fp16.c (binary64): New. (__gnu_d2h_internal): New. (__gnu_d2h_ieee): New. (__gnu_d2h_alternative): New. Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com> From-SVN: r242782
2016-11-23[Patch 14/17] [libgcc, ARM] Generalise float-to-half conversion function.James Greenhalgh1-18/+72
libgcc/ * config/arm/fp16.c (struct format): New. (binary32): New. (__gnu_float2h_internal): New. Body moved from __gnu_f2h_internal and generalize. (_gnu_f2h_internal): Move body to function __gnu_float2h_internal. Call it with binary32. Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com> From-SVN: r242781
2016-07-21[ARM] Fix PR target/59833Aurelien Jarno1-3/+7
For Aurelien Jarno <aurelien@aurel32.net> On ARM soft-float, the float to double conversion doesn't convert a sNaN to qNaN as the IEEE Std 754 standard mandates: "Under default exception handling, any operation signaling an invalid operation exception and for which a floating-point result is to be delivered shall deliver a quiet NaN." Given the soft float ARM code ignores exceptions and always provides a result, a float to double conversion of a signaling NaN should return a quiet NaN. Fix this in extendsfdf2. gcc/ChangeLog: PR target/59833 * config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN. gcc/testsuite/ChangeLog: * gcc.dg/pr59833.c: New testcase. From-SVN: r238584
2016-07-11lib1funcs.S: Add new wrapper.Hale Wang1-32/+218
2016-07-11 Hale Wang <hale.wang@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/lib1funcs.S: Add new wrapper. Co-Authored-By: Andre Vieira <andre.simoesdiasvieira@arm.com> From-SVN: r238215
2016-07-07arm-arches.def (armv8-m.base): Define new architecture.Thomas Preud'homme1-1/+2
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm-arches.def (armv8-m.base): Define new architecture. (armv8-m.main): Likewise. (armv8-m.main+dsp): Likewise. * config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define. (FL_FOR_ARCH8M_MAIN): Likewise. * config/arm/arm-tables.opt: Regenerate. * config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and armv8-m.main+dsp to BE8_LINK_SPEC. * config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M. (enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN. * config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M Baseline and Mainline. (arm_option_override_internal): Also disable arm_restrict_it when !arm_arch_notm. Update comment for -munaligned-access to also cover ARMv8-M Baseline. (arm_file_start): Increase buffer size for printing architecture name. * doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main and armv8-m.main+dsp. (mno-unaligned-access): Clarify that this is disabled by default for ARMv8-M Baseline architectures as well. gcc/testsuite/ * lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and check_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and ARMv8-M Mainline architectures. libgcc/ * config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M. From-SVN: r238081
2016-07-07lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later and ARMv5t* rather ↵Thomas Preud'homme1-3/+4
than for a fixed list of... 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> libgcc/ * config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later and ARMv5t* rather than for a fixed list of architectures. From-SVN: r238080
2016-07-07elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to decide whether to ↵Thomas Preud'homme4-19/+25
prevent... 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to decide whether to prevent some libgcc routines being included for some multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the link between this condition and the one in libgcc/config/arm/lib1func.S. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use __ARM_ARCH_ISA_ARM to test for Cortex-M devices. libgcc/ * config/arm/bpabi-v6m.S: Clarify what architectures is the implementation suitable for. * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases for all Thumb-1 only targets. (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (EQUIV): Likewise. (ARM_FUNC_ALIAS): Likewise. (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv version. (modsi3): Likewise. (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (clzdi2): Likewise. (ctzsi2): Likewise. (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__ in guard for checking whether it is defined. (final includes): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__ and add comment to indicate the connection between this condition and the one in gcc/config/arm/elf.h. * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. * config/arm/t-softfp: Likewise. From-SVN: r238079
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