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2025-03-03Fortran: reject empty derived type with bind(C) attribute [PR101577]Harald Anlauf3-3/+32
PR fortran/101577 gcc/fortran/ChangeLog: * symbol.cc (verify_bind_c_derived_type): Generate error message for derived type with no components in standard conformance mode, indicating that this is a GNU extension. gcc/testsuite/ChangeLog: * gfortran.dg/empty_derived_type.f90: Adjust dg-options. * gfortran.dg/empty_derived_type_2.f90: New test.
2025-03-03aarch64: Ignore target pragmas while defining intrinsicsAndrew Carlotti6-49/+74
Refactor the switcher classes into two separate classes: - sve_alignment_switcher takes the alignment switching functionality, and is used only for ABI correctness when defining sve structure types. - aarch64_target_switcher takes the rest of the functionality of aarch64_simd_switcher and sve_switcher, and gates simd/sve specific parts upon the specified feature flags. Additionally, aarch64_target_switcher now adds dependencies of the specified flags (which adds +fcma and +bf16 to some intrinsic declarations), and unsets current_target_pragma. This last change fixes an internal bug where we would sometimes add a user specified target pragma (stored in current_target_pragma) on top of an internally specified target architecture while initialising intrinsics with `#pragma GCC aarch64 "arm_*.h"`. As far as I can tell, this has no visible impact at the moment. However, the unintended target feature combinations lead to unwanted behaviour in an under-development patch. This also fixes a missing Makefile dependency, which was due to aarch64-sve-builtins.o incorrectly depending on the undefined $(REG_H). The correct $(REGS_H) dependency is added to the switcher's new source location. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_extension_info): Add field. (aarch64_get_required_features): New. * config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher): Rename to... (aarch64_target_switcher::aarch64_target_switcher): ...this, and extend to handle sve, nosimd and target pragmas. (aarch64_simd_switcher::~aarch64_simd_switcher): Rename to... (aarch64_target_switcher::~aarch64_target_switcher): ...this, and extend to handle sve, nosimd and target pragmas. (handle_arm_acle_h): Use aarch64_target_switcher. (handle_arm_neon_h): Rename switcher and pass explicit flags. (aarch64_general_init_builtins): Ditto. * config/aarch64/aarch64-protos.h (class aarch64_simd_switcher): Rename to... (class aarch64_target_switcher): ...this, and add new members. (aarch64_get_required_features): New prototype. * config/aarch64/aarch64-sve-builtins.cc (sve_switcher::sve_switcher): Delete (sve_switcher::~sve_switcher): Delete (sve_alignment_switcher::sve_alignment_switcher): New (sve_alignment_switcher::~sve_alignment_switcher): New (register_builtin_types): Use alignment switcher (init_builtins): Rename switcher. (handle_arm_neon_sve_bridge_h): Ditto. (handle_arm_sme_h): Ditto. (handle_arm_sve_h): Ditto, and use alignment switcher. * config/aarch64/aarch64-sve-builtins.h (class sve_switcher): Delete. (class sme_switcher): Delete. (class sve_alignment_switcher): New. * config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H). (aarch64-sve-builtins.o): Remove $(REG_H).
2025-03-03arm: remove some redundant zero_extend ops on thumb1Richard Earnshaw2-2/+30
The code in gcc.target/unsigned-extend-1.c really should not need an unsigned extension operations when the optimizers are used. For Arm and thumb2 that is indeed the case, but for thumb1 code it gets more complicated as there are too many instructions for combine to look at. For thumb1 we end up with two redundant zero_extend patterns which are not removed: the first after the subtract instruction and the second of the final boolean result. We can partially fix this (for the second case above) by adding a new split pattern for LEU and GEU patterns which work because the two instructions for the [LG]EU pattern plus the redundant extension instruction are combined into a single insn, which we can then split using the 3->2 method back into the two insns of the [LG]EU sequence. Because we're missing the optimization for all thumb1 cases (not just those architectures with UXTB), I've adjust the testcase to detect all the idioms that we might use for zero-extending a value, namely: UXTB AND ...#255 (in thumb1 this would require a register to hold 255) LSL ... #24; LSR ... #24 but I've also marked this test as XFAIL for thumb1 because we can't yet eliminate the first of the two extend instructions. gcc/ * config/arm/thumb1.md (split patterns for GEU and LEU): New. gcc/testsuite: * gcc.target/arm/unsigned-extend-1.c: Expand check for any insn suggesting a zero-extend. XFAIL for thumb1 code.
2025-03-03Revert "combine: Reverse negative logic in ternary operator"Uros Bizjak1-11/+11
This reverts commit f1c30c6213fb228f1e8b5973d10c868b834a4acd.
2025-03-03combine: Reverse negative logic in ternary operatorUros Bizjak1-11/+11
Reverse negative logic in !a ? b : c to become a ? c : b. No functional changes. gcc/ChangeLog: * combine.cc (distribute_notes): Reverse negative logic in ternary operators.
2025-03-03combine: Discard REG_UNUSED note in i2 when register is also referenced in ↵Uros Bizjak2-7/+58
i3 [PR118739] The combine pass is trying to combine: Trying 16, 22, 21 -> 23: 16: r104:QI=flags:CCNO>0 22: {r120:QI=r104:QI^0x1;clobber flags:CC;} REG_UNUSED flags:CC 21: r119:QI=flags:CCNO<=0 REG_DEAD flags:CCNO 23: {r110:QI=r119:QI|r120:QI;clobber flags:CC;} REG_DEAD r120:QI REG_DEAD r119:QI REG_UNUSED flags:CC and creates the following two insn sequence: modifying insn i2 22: r104:QI=flags:CCNO>0 REG_DEAD flags:CC deferring rescan insn with uid = 22. modifying insn i3 23: r110:QI=flags:CCNO<=0 REG_DEAD flags:CC deferring rescan insn with uid = 23. where the REG_DEAD note in i2 is not correct, because the flags register is still referenced in i3. In try_combine() megafunction, we have this part: --cut here-- /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ if (i3notes) distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL, elim_i2, elim_i1, elim_i0); if (i2notes) distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL, elim_i2, elim_i1, elim_i0); if (i1notes) distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL, elim_i2, local_elim_i1, local_elim_i0); if (i0notes) distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL, elim_i2, elim_i1, local_elim_i0); if (midnotes) distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL, elim_i2, elim_i1, elim_i0); --cut here-- where the compiler distributes REG_UNUSED note from i2: 22: {r120:QI=r104:QI^0x1;clobber flags:CC;} REG_UNUSED flags:CC via distribute_notes() using the following: --cut here-- /* Otherwise, if this register is used by I3, then this register now dies here, so we must put a REG_DEAD note here unless there is one already. */ else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) && ! (REG_P (XEXP (note, 0)) ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) { PUT_REG_NOTE_KIND (note, REG_DEAD); place = i3; } --cut here-- Flags register is used in I3, but there already is a REG_DEAD note in I3. The above condition doesn't trigger and continues in the "else" part where REG_DEAD note is put to I2. The proposed solution corrects the above logic to trigger every time the register is referenced in I3, avoiding the "else" part. PR rtl-optimization/118739 gcc/ChangeLog: * combine.cc (distribute_notes) <case REG_UNUSED>: Correct the logic when the register is used by I3. gcc/testsuite/ChangeLog: * gcc.target/i386/pr118739.c: New test.
2025-03-03ipa-vr: Handle non-conversion unary ops separately from conversions (PR 118785)Martin Jambor2-3/+56
Since we construct arithmetic jump functions even when there is a type conversion in between the operation encoded in the jump function and when it is passed in a call argument, the IPA propagation phase must also perform the operation and conversion in two steps. IPA-VR had actually been doing it even before for binary operations but, as PR 118756 exposes, not in the case on unary operations. This patch adds the necessary step to rectify that. Like in the scalar constant case, we depend on expr_type_first_operand_type_p to determine the type of the result of the arithmetic operation. On top this, the patch special-cases ABSU_EXPR because it looks useful an so that the PR testcase exercises the added code-path. This seems most appropriate for stage 4, long term we should probably stream the types, probably after also encoding them with a string of expr_eval_op rather than what we have today. A check for expr_type_first_operand_type_p was also missing in the handling of binary ops and the intermediate value_range was initialized with a wrong type, so I also fixed this. gcc/ChangeLog: 2025-02-24 Martin Jambor <mjambor@suse.cz> PR ipa/118785 * ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Handle non-conversion unary operations separately before doing any conversions. Check expr_type_first_operand_type_p for non-unary operations too. Fix type of op_res. gcc/testsuite/ChangeLog: 2025-02-24 Martin Jambor <mjambor@suse.cz> PR ipa/118785 * g++.dg/lto/pr118785_0.C: New test.
2025-03-03tree-optimization/119057 - bogus double reduction detectionRichard Biener2-5/+26
We are detecting a cycle as double reduction where the inner loop cycle has extra out-of-loop uses. This clashes at least with assumptions from the SLP discovery code which says the cycle isn't reachable from another SLP instance. It also was not intended to support this case, in fact with GCC 14 we seem to generate wrong code here. PR tree-optimization/119057 * tree-vect-loop.cc (check_reduction_path): Add argument specifying whether we're analyzing the inner loop of a double reduction. Do not allow extra uses outside of the double reduction cycle in this case. (vect_is_simple_reduction): Adjust. * gcc.dg/vect/pr119057.c: New testcase.
2025-03-03ipa/119067 - bogus TYPE_PRECISION check on VECTOR_TYPERichard Biener3-1/+41
odr_types_equivalent_p can end up using TYPE_PRECISION on vector types which is a no-go. The following instead uses TYPE_VECTOR_SUBPARTS for vector types so we also end up comparing the number of vector elements. PR ipa/119067 * ipa-devirt.cc (odr_types_equivalent_p): Check TYPE_VECTOR_SUBPARTS for vectors. * g++.dg/lto/pr119067_0.C: New testcase. * g++.dg/lto/pr119067_1.C: Likewise.
2025-03-03Fortran: Fix regression on double free on elemental function [PR118747]Andre Vehreschild3-10/+41
Fix a regression were adding a temporary variable inserted a copy of the argument to the elemental function. That copy was then later used to free allocated memory, but the freeing was not tracked in the source array correctly. PR fortran/118747 gcc/fortran/ChangeLog: * trans-array.cc (gfc_trans_array_ctor_element): Remove copy to temporary variable. * trans-expr.cc (gfc_conv_procedure_call): Use references to array members instead of copies when freeing after use. Formatting fix. gcc/testsuite/ChangeLog: * gfortran.dg/alloc_comp_auto_array_4.f90: New test.
2025-03-03Daily bump.GCC Administrator5-1/+70
2025-03-02[RISC-V][PR target/118934] Fix ICE in RISC-V long branch supportJeff Law3-5/+5
I'm not sure if I goof'd this or if I merely upstreamed someone else's goof. Either way the long branch code isn't working correctly. We were using 'n' as the output modifier to negate the condition. But 'n' has a special meaning elsewhere, so when presented with a condition rather than what was expected, boom, the compiler ICE'd. Thankfully there's only a few places where we were using %n which I turned into %r. The BZ entry includes a good testcase, it just takes a long time to compile as it's trying to create the out-of-range scenario. I'm not including the testcase due to how long it takes, but I did test it locally to ensure it's working properly now. I'm sure that with a little bit of work I could create at testcase that worked before and fails with the trunk (by taking advantage of the fuzzyness in length computations). So I'm going to consider this a regression. Will push to the trunk after pre-commit testing does its thing. PR target/118934 gcc/ * config/riscv/corev.md (cv_branch): Adjust output template. (branch): Likewise. * config/riscv/riscv.md (branch): Likewise. * config/riscv/riscv.cc (riscv_asm_output_opcode): Handle 'r' rather than 'n'.
2025-03-02PR modula2/119088 ICE when for loop accesses an unknown variable as the iteratorGaius Mulley2-7/+21
This patch fixes an ICE which occurs when a FOR statement attempts to use an undeclared variable as its iterator. gcc/m2/ChangeLog: PR modula2/119088 * gm2-compiler/M2SymInit.mod (ConfigSymInit): Reimplement to defensively check for NulSym type. gcc/testsuite/ChangeLog: PR modula2/119088 * gm2/pim/fail/tinyfor4.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2025-03-02Fortran: Small fixes in intrinsic.texi.Sandra Loosemore1-13/+13
gcc/fortran/ChangeLog * intrinsic.texi: Fix inconsistent capitalization of argument names and other minor copy-editing.
2025-03-02Fortran: Move "Standard" subheading in documentation [PR47928]Sandra Loosemore1-923/+923
As noted in the issue, the version of the standard an intrinsic was introduced in is usually not the second-most-important thing a user needs to know. This patch moves it from near the beginning of each section towards the end, just ahead of "See also". gcc/fortran/ChangeLog PR fortran/47928 * intrinsic.texi: Move the "Standard" subheading farther down.
2025-03-02Fortran: Rename/move "Syntax" subheading in documentation [PR47928]Sandra Loosemore2-1159/+1159
As suggested in the issue, it makes more sense to describe the function call argument syntax before talking about the arguments in the description. gcc/fortran/ChangeLog PR fortran/47928 * gfortran.texi: Move all the "Syntax" subheadings ahead of "Description", and rename to "Synopsis". * intrinsic.texi: Likewise.
2025-03-02Fortran: Whitespace cleanup in documentation [PR47928]Sandra Loosemore1-19/+15
This is a preparatory patch for the main changes requested in the issue. gcc/fortran/ChangeLog PR fortran/47928 * intrinsic.texi: Put a blank line between "@item @emph{}" subheadings, but not more than one.
2025-03-02Fortran: Tidy subheadings in Fortran documentation [PR47928]Sandra Loosemore2-49/+48
This is a preparatory patch for the main documentation changes requested in the issue. gcc/fortran/ChangeLog PR fortran/47928 * gfortran.texi: Consistently use "@emph{Notes}:" instead of other spellings. * intrinsic.texi: Likewise. Also fix an inconsistent capitalization and remove a redundant "Standard" entry.
2025-03-02avr: Fix up avr_print_operand diagnostics [PR118991]Jakub Jelinek1-4/+13
As can be seen in gcc/po/gcc.pot: #: config/avr/avr.cc:2754 #, c-format msgid "bad I/O address 0x" msgstr "" exgettext couldn't retrieve the whole format string in this case, because it uses a macro in the middle. output_operand_lossage is c-format function though, so we can't use %wx to print HOST_WIDE_INT, and HOST_WIDE_INT_PRINT_HEX_PURE is on some hosts %lx, on others %llx and on others %I64x so isn't really translatable that way. As Joseph mentioned in the PR, there is no easy way around this but go through a temporary buffer, which the following patch does. 2025-03-02 Jakub Jelinek <jakub@redhat.com> PR translation/118991 * config/avr/avr.cc (avr_print_operand): Print ival into a temporary buffer and use %s in output_operand_lossage to make the diagnostics translatable.
2025-03-02gimple: sccopy: Prune removed statements from SCCs [PR117919]Filip Kastl2-0/+65
While writing the sccopy pass I didn't realize that 'replace_uses_by ()' can remove portions of the CFG. This happens when replacing arguments of some statement results in the removal of an EH edge. Because of this sccopy can then work with GIMPLE statements that aren't part of the IR anymore. In PR117919 this triggered an assertion within the pass which assumes that statements the pass works with are reachable. This patch tells the pass to notice when a statement isn't in the IR anymore and remove it from it's worklist. PR tree-optimization/117919 gcc/ChangeLog: * gimple-ssa-sccopy.cc (scc_copy_prop::propagate): Prune statements that 'replace_uses_by ()' removed. gcc/testsuite/ChangeLog: * g++.dg/pr117919.C: New test. Signed-off-by: Filip Kastl <fkastl@suse.cz>
2025-03-02Daily bump.GCC Administrator4-1/+50
2025-03-01doc: Simplify description of *-*-freebsd*Gerald Pfeifer1-2/+1
gcc: PR target/69374 * doc/install.texi (Specific, *-*-freebsd*): Simplify description.
2025-03-01ggc: Fix up ggc_internal_cleared_alloc_no_dtor [PR117047]Jakub Jelinek1-1/+1
Apparently I got one of the !HAVE_ATTRIBUTE_ALIAS fallbacks wrong. It compiled with a warning: ../../gcc/ggc-common.cc: In function 'void* ggc_internal_cleared_alloc_no_dtor(size_t, void (*)(void*), size_t, size_t)': ../../gcc/ggc-common.cc:154:44: warning: unused parameter 'size' [-Wunused-parameter] 154 | ggc_internal_cleared_alloc_no_dtor (size_t size, void (*f)(void *), | ~~~~~~~^~~~ and obviously didn't work right (always allocated 0-sized objects). Fixed thusly. 2025-03-01 Jakub Jelinek <jakub@redhat.com> PR jit/117047 * ggc-common.cc (ggc_internal_cleared_alloc_no_dtor): Pass size rather than s as the first argument to ggc_internal_cleared_alloc.
2025-03-01Fortran: fix front-end memleak after failure during parsing of NULLIFYHarald Anlauf2-0/+3
gcc/fortran/ChangeLog: * match.cc (gfc_match_nullify): Free matched expression when cleaning up. * primary.cc (match_variable): Initialize result to NULL.
2025-03-01[PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implicationYuriy Kolerov5-1/+25
zce must imply zcf but this rule was corrupted after refactoring in 9e12010b5e724277ea. This may be observed ater generating an .s file from any source code file with -mriscv-attribute -march=rv32if_zce -mabi=ilp32 -S options. A full march will be presented in arch attribute: rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0 As you see, zcf is not presented here though f_zce pair is passed in -march. According to The RISC-V Instruction Set Manual: Specifying Zce on RV32 with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. PR target/118906 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: fix zce to zcf implication. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-zce-1.c: New test. * gcc.target/riscv/attribute-zce-2.c: New test. * gcc.target/riscv/attribute-zce-3.c: New test. * gcc.target/riscv/attribute-zce-4.c: New test.
2025-03-01[PATCH] H8/300, libgcc: PR target/114222 For HImode call internal ffs() ↵Jan Dubiec1-0/+8
implementation instead of an external one When INT_TYPE_SIZE < BITS_PER_WORD gcc emits a call to an external ffs() implementation instead of a call to "__builtin_ffs()" – see function init_optabs() in <SRCROOT>/gcc/optabs-libfuncs.cc. External ffs() (which is usually the one from newlib) in turn calls __builtin_ffs() what causes infinite recursion and stack overflow. This patch overrides default gcc bahaviour for H8/300H (and newer) and provides a generic ffs() implementation for HImode. PR target/114222 gcc/ChangeLog: * config/h8300/h8300.cc (h8300_init_libfuncs): For HImode override calls to external ffs() (from newlib) with calls to __ffshi2() from libgcc. The implementation of ffs() in newlib calls __builtin_ffs() what causes infinite recursion and finally a stack overflow. libgcc/ChangeLog: * config/h8300/t-h8300: Add __ffshi2(). * config/h8300/ffshi2.c: New file.
2025-03-01input: Fix UB during self-tests [PR119052]Jakub Jelinek1-5/+12
As the comment in check_line says: /* get_buffer is not null terminated, but the sscanf stops after a number. */ the buffer is not null terminated, there is line.length () to determine the size of the line. But unlike what the comment says, sscanf actually still requires null terminated string argument, anything else is UB. E.g. glibc when initializing the temporary FILE stream for the string does if (size == 0) end = strchr (ptr, '\0'); and this strchr/rawmemchr is what shows up in valgrind report on cc1/cc1plus doing self-tests. The function is used only in a test with 1000 lines, each containg its number, so numbers from 1 to 1000 inclusive (each time with '\n' separator, but that isn't included in line.length ()). So the function just uses a temporary buffer which can fit numbers from 1 to 1000 as strings with terminating '\0' and runs sscanf on that (why not strtoul?). Furthermore, the caller allocated number of lines * 15 bytes for the string, but 1000\n is 5 bytes, so I think * 5 is more than enough. 2025-03-01 Jakub Jelinek <jakub@redhat.com> PR other/119052 * input.cc (check_line): Don't call sscanf on non-null terminated buffer, instead copy line.length () bytes from line.get_buffer () to a local buffer, null terminate it and call sscanf on that. Formatting fix. (test_replacement): Just allocate maxline * 5 rather than maxline * 15 bytes for the file. Formatting fix.
2025-03-01Daily bump.GCC Administrator8-1/+271
2025-03-01ggc: Avoid using ATTRIBUTE_MALLOC for allocations that need finalization ↵Jakub Jelinek9-17/+211
[PR117047] As analyzed by Andrew/David/Richi/Sam in the PR, the reason for the libgccjit ICE is that there are GC allocations with finalizers and we still mark ggc_internal_{,cleared_}alloc with ATTRIBUTE_MALLOC, which to the optimizers hints that nothing will actually read the state of the objects when they get out of lifetime. The finalizer actually inspects those though. What actually happens in the testcases is that on tree expr_size = TYPE_SIZE (expr->get_type ()->as_tree ()); we see that expr->get_type () was allocated using something with malloc attribute but it doesn't escape and only the type size from it is queried, so there is no need to store other members of it. Except that it does escape in the GC internals. Normal GC allocations are fine, they don't look at the data in the allocated objects on "free", but the ones with finalizers actually call a function on that object and expect the data to be in there. So that we don't lose ATTRIBUTE_MALLOC for the common case when no finalization is needed, the following patch uses the approach used e.g. for glibc error function which can sometimes be noreturn but at other times just return normally. If possible, it uses __attribute__((alias ("..."))) to add an alias to the function, where one is without ATTRIBUTE_MALLOC and one (with _no_dtor suffix) is with ATTRIBUTE_MALLOC (note, as this is C++ and I didn't want to hardcode particular mangling I used an extern "C" function with 2 aliases to it), and otherwise adds a wrapper (for the ggc-page/ggc-common case with noinline attribute if possible, for ggc-none that doesn't matter because ggc-none doesn't support finalizers). The *_no_dtor aliases/wrappers are then used in inline functions which pass unconditional NULL, 0 as the f/s pair. 2025-03-01 Jakub Jelinek <jakub@redhat.com> PR jit/117047 * acinclude.m4 (gcc_CHECK_ATTRIBUTE_ALIAS): New. * configure.ac: Add gcc_CHECK_ATTRIBUTE_ALIAS. * ggc.h (ggc_internal_alloc): Remove ATTRIBUTE_MALLOC from overload with finalizer pointer. Call ggc_internal_alloc_no_dtor in inline overload without finalizer pointer. (ggc_internal_alloc_no_dtor): Declare. (ggc_internal_cleared_alloc): Remove ATTRIBUTE_MALLOC from overload with finalizer pointer. Call ggc_internal_cleared_alloc_no_dtor in inline overload without finalizer pointer. (ggc_internal_cleared_alloc_no_dtor): Declare. (ggc_alloc): Call ggc_internal_alloc_no_dtor if no finalization is needed. (ggc_alloc_no_dtor): Call ggc_internal_alloc_no_dtor. (ggc_cleared_alloc): Call ggc_internal_cleared_alloc_no_dtor if no finalization is needed. (ggc_vec_alloc): Call ggc_internal_alloc_no_dtor if no finalization is needed. (ggc_cleared_vec_alloc): Call ggc_internal_cleared_alloc_no_dtor if no finalization is needed. * ggc-page.cc (ggc_internal_alloc): If HAVE_ATTRIBUTE_ALIAS, turn overload with finalizer into alias to ggc_internal_alloc_ and rename it to ... (ggc_internal_alloc_): ... this, make it extern "C". (ggc_internal_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS, otherwise new noinline wrapper. * ggc-common.cc (ggc_internal_cleared_alloc): If HAVE_ATTRIBUTE_ALIAS, turn overload with finalizer into alias to ggc_internal_alloc_ and rename it to ... (ggc_internal_cleared_alloc_): ... this, make it extern "C". (ggc_internal_cleared_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS, otherwise new noinline wrapper. * ggc-none.cc (ggc_internal_alloc): If HAVE_ATTRIBUTE_ALIAS, turn overload with finalizer into alias to ggc_internal_alloc_ and rename it to ... (ggc_internal_alloc_): ... this, make it extern "C". (ggc_internal_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS, otherwise new wrapper. (ggc_internal_cleared_alloc): If HAVE_ATTRIBUTE_ALIAS, turn overload with finalizer into alias to ggc_internal_alloc_ and rename it to ... (ggc_internal_cleared_alloc_): ... this, make it extern "C". (ggc_internal_cleared_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS, otherwise new wrapper. * genmatch.cc (ggc_internal_cleared_alloc, ggc_free): Formatting fix. (ggc_internal_cleared_alloc_no_dtor): Define. * config.in: Regenerate. * configure: Regenerate.
2025-03-01openmp: Fix up simd clone mask argument creation on x86 [PR115871]Jakub Jelinek2-1/+11
The following testcase ICEs since r14-5057. The Intel vector ABI says that in the ZMM case the masks is passed in unsigned int or unsigned long long arguments and how many bits in them and how many of those arguments are is determined by the characteristic data type of the function. In the testcase simdlen is 32 and characteristic data type is double, so return as well as first argument is passed in 4 V8DFmode arguments and the mask is supposed to be passed in 4 unsigned int arguments (8 bits in each). Before the r14-5057 change there was sc->args[i].orig_type = parm_type; ... case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_CONSTANT_STEP: case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_VARIABLE_STEP: case SIMD_CLONE_ARG_TYPE_VECTOR: if (INTEGRAL_TYPE_P (parm_type) || POINTER_TYPE_P (parm_type)) veclen = sc->vecsize_int; else veclen = sc->vecsize_float; if (known_eq (veclen, 0U)) veclen = sc->simdlen; else veclen = exact_div (veclen, GET_MODE_BITSIZE (SCALAR_TYPE_MODE (parm_type))); for the argument handling and if (sc->inbranch) { tree base_type = simd_clone_compute_base_data_type (sc->origin, sc); ... if (INTEGRAL_TYPE_P (base_type) || POINTER_TYPE_P (base_type)) veclen = sc->vecsize_int; else veclen = sc->vecsize_float; if (known_eq (veclen, 0U)) veclen = sc->simdlen; else veclen = exact_div (veclen, GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type))); for the mask handling. r14-5057 moved this argument creation later and unified that: case SIMD_CLONE_ARG_TYPE_MASK: case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_CONSTANT_STEP: case SIMD_CLONE_ARG_TYPE_LINEAR_VAL_VARIABLE_STEP: case SIMD_CLONE_ARG_TYPE_VECTOR: if (sc->args[i].arg_type == SIMD_CLONE_ARG_TYPE_MASK && sc->mask_mode != VOIDmode) elem_type = boolean_type_node; else elem_type = TREE_TYPE (sc->args[i].vector_type); if (INTEGRAL_TYPE_P (elem_type) || POINTER_TYPE_P (elem_type)) veclen = sc->vecsize_int; else veclen = sc->vecsize_float; if (known_eq (veclen, 0U)) veclen = sc->simdlen; else veclen = exact_div (veclen, GET_MODE_BITSIZE (SCALAR_TYPE_MODE (elem_type))); This is correct for the argument cases (so linear or vector) (though POINTER_TYPE_P will never appear as TREE_TYPE of a vector), but the boolean_type_node in there is completely bogus, when using AVX512 integer masks as I wrote above we need the characteristic data type, not bool, and bool is strange in that it has bitsize of 8 (or 32 on darwin), while the masks are 1 bit per lane anyway. Fixed thusly. 2025-03-01 Jakub Jelinek <jakub@redhat.com> PR middle-end/115871 * omp-simd-clone.cc (simd_clone_adjust): For SIMD_CLONE_ARG_TYPE_MASK and sc->mask_mode not VOIDmode, set elem_type to the characteristic type rather than boolean_type_node. * gcc.dg/gomp/simd-clones-8.c: New test.
2025-02-28[PATCH] H8/300: PR target/109189 Silence -Wformat warnings on WindowsJan Dubiec1-11/+11
This patch fixes annoying -Wformat warnings when gcc is built on Windows/MinGW64. Instead of %ld it uses HOST_WIDE_INT_PRINT_DEC macro, just like many other targets do. PR target/109189 gcc/ChangeLog: * config/h8300/h8300.cc (h8300_print_operand): Replace %ld format strings with HOST_WIDE_INT_PRINT_DEC macro in order to silence -Wformat warnings when building on Windows/MinGW64.
2025-03-01testsuite: Fix up toplevel-asm-1.c for LoongArchXi Ruoyao1-1/+1
Like RISC-V, on LoongArch we don't really support %cN for SYMBOL_REFs even with -fno-pic. gcc/testsuite/ChangeLog: * c-c++-common/toplevel-asm-1.c: Use %cc3 %cc4 instead of %c3 %c4 on LoongArch.
2025-02-28d: Fix comparing uninitialized memory in dstruct.d [PR116961]Iain Buclaw5-14/+21
Floating-point emulation in the D front-end is done via a type named `struct longdouble`, which in GDC is a small interface around the real_value type. Because the D code cannot include gcc/real.h directly, a big enough buffer is used for the data instead. On x86_64, this buffer is actually bigger than real_value itself, so when a new longdouble object is created with longdouble r; real_from_string3 (&r.rv (), buffer, mode); return r; there is uninitialized padding at the end of `r`. This was never a problem when D was implemented in C++ (until GCC 12) as comparing two longdouble objects with `==' would be forwarded to the relevant operator== overload that extracted the underlying real_value. However when the front-end was translated to D, such conditions were instead rewritten into identity comparisons return exp.toReal() is CTFloat.zero The `is` operator gets lowered as a call to `memcmp() == 0', which is where the read of uninitialized memory occurs, as seen by valgrind. ==26778== Conditional jump or move depends on uninitialised value(s) ==26778== at 0x911F41: dmd.dstruct._isZeroInit(dmd.expression.Expression) (dstruct.d:635) ==26778== by 0x9123BE: StructDeclaration::finalizeSize() (dstruct.d:373) ==26778== by 0x86747C: dmd.aggregate.AggregateDeclaration.determineSize(ref const(dmd.location.Loc)) (aggregate.d:226) [...] To avoid accidentally reading uninitialized data, explicitly initialize all `longdouble` variables with an empty constructor on C++ side of the implementation before initializing underlying real_value type it holds. PR d/116961 gcc/d/ChangeLog: * d-codegen.cc (build_float_cst): Change new_value type from real_t to real_value. * d-ctfloat.cc (CTFloat::fabs): Default initialize the return value. (CTFloat::ldexp): Likewise. (CTFloat::parse): Likewise. * d-longdouble.cc (longdouble::add): Likewise. (longdouble::sub): Likewise. (longdouble::mul): Likewise. (longdouble::div): Likewise. (longdouble::mod): Likewise. (longdouble::neg): Likewise. * d-port.cc (Port::isFloat32LiteralOutOfRange): Likewise. (Port::isFloat64LiteralOutOfRange): Likewise. gcc/testsuite/ChangeLog: * gdc.dg/pr116961.d: New test.
2025-02-28c++: fix rejects-valid and ICE with constexpr NSDMI [PR110822]Marek Polacek3-1/+54
Since r10-7718 the attached tests produce an ICE in verify_address: error: constant not recomputed when 'ADDR_EXPR' changed but before that we wrongly rejected the tests with "is not a constant expression". This patch fixes both problems. Since r10-7718 replace_decl_r can replace {._M_dataplus=&<retval>._M_local_buf, ._M_local_buf=0} with {._M_dataplus=&HelloWorld._M_local_buf, ._M_local_buf=0} The initial &<retval>._M_local_buf was not constant, but since HelloWorld is a static VAR_DECL, the resulting &HelloWorld._M_local_buf should have been marked as TREE_CONSTANT. And since we're taking its address, the whole thing should be TREE_ADDRESSABLE. PR c++/114913 PR c++/110822 gcc/cp/ChangeLog: * constexpr.cc (replace_decl_r): If we've replaced something inside of an ADDR_EXPR, call cxx_mark_addressable and recompute_tree_invariant_for_addr_expr on the resulting ADDR_EXPR. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/constexpr-nsdmi4.C: New test. * g++.dg/cpp0x/constexpr-nsdmi5.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2025-02-28c++: ICE in replace_decl [PR118986]Marek Polacek2-9/+43
Yet another problem that started with r15-6052, compile time evaluation of prvalues. cp_fold_r/TARGET_EXPR sees: TARGET_EXPR <D.2701, <<< Unknown tree: expr_stmt D.2701.__p = TARGET_EXPR <D.2684, <<< Unknown tree: aggr_init_expr 3 f1 D.2684 >>>> >>>> so when we call maybe_constant_init, the object we're initializing is D.2701, and the init is the expr_stmt. We unwrap the EXPR_STMT/INIT_EXPR/TARGET_EXPR in maybe_constant_init_1 and so end up evaluating the f1 call. But f1 returns c2 whereas the type of D.2701 is ._anon_0 -- the closure. So then we crash in replace_decl on: gcc_checking_assert (same_type_ignoring_top_level_qualifiers_p (TREE_TYPE (decl), TREE_TYPE (replacement))); due to the mismatched types. cxx_eval_outermost_constant_expr is already ready for the types to be different, in which case the result isn't constant. But replace_decl is called before that check. I'm leaving the assert in replace_decl on purpose, maybe we'll find another use for it. PR c++/118986 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_call_expression): Check that the types match before calling replace_decl, if not, set *non_constant_p. (maybe_constant_init_1): Don't strip INIT_EXPR if it would change the type of the expression. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/constexpr-prvalue1.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2025-02-28ipa-sra: Avoid clashes with ipa-cp when pulling accesses across calls (PR ↵Martin Jambor2-10/+68
118243) Among other things, IPA-SRA checks whether splitting out a bit of an aggregate or something passed by reference would lead into a clash with an already known IPA-CP constant a way which would cause problems later on. Unfortunately the test is done only in adjust_parameter_descriptions and is missing when accesses are propagated from callees to callers, which leads to miscompilation reported as PR 118243 (where the callee is a function created by ipa-split). The matter is then further complicated by the fact that we consider complex numbers as scalars even though they can be modified piecemeal (IPA-CP can detect and propagate the pieces separately too) which then confuses the parameter manipulation machinery furter. This patch simply adds the missing check to avoid the IPA-SRA transform in these cases too, which should be suitable for backporting to all affected release branches. It is a bit of a shame as in the PR testcase we do propagate both components of the complex number in question and the transformation phase could recover. I have some prototype patches in this direction but that is something for (a) stage 1. gcc/ChangeLog: 2025-02-10 Martin Jambor <mjambor@suse.cz> PR ipa/118243 * ipa-sra.cc (pull_accesses_from_callee): New parameters caller_ipcp_ts and param_idx. Check that scalar pulled accesses would not clash with a known IPA-CP aggregate constant. (param_splitting_across_edge): Pass IPA-CP transformation summary and caller parameter index to pull_accesses_from_callee. gcc/testsuite/ChangeLog: 2025-02-10 Martin Jambor <mjambor@suse.cz> PR ipa/118243 * g++.dg/ipa/pr118243.C: New test.
2025-02-28c++: generic lambda, implicit 'this' capture, xobj memfn [PR119038]Patrick Palka2-4/+14
When a generic lambda calls an overload set containing an iobj member function we speculatively capture 'this'. We need to do the same for an xobj member function. PR c++/119038 gcc/cp/ChangeLog: * lambda.cc (maybe_generic_this_capture): Consider xobj member functions as well, not just iobj. Update function comment. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-lambda15.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2025-02-28c++: Fix cxx_eval_store_expression {REAL,IMAG}PART_EXPR handling [PR119045]Jakub Jelinek2-2/+20
I've added the asserts that probe == target because {REAL,IMAG}PART_EXPR always implies a scalar type and so applying ARRAY_REF/COMPONENT_REF etc. on it further doesn't make sense and the later code relies on it to be the last one in refs array. But as the following testcase shows, we can fail those assertions in case there is a reference or pointer to the __real__ or __imag__ part, in that case we just evaluate the constant expression and so probe won't be the same as target. That case doesn't push anything into the refs array though. The following patch changes those asserts to verify that refs is still empty, which fixes it. 2025-02-28 Jakub Jelinek <jakub@redhat.com> PR c++/119045 * constexpr.cc (cxx_eval_store_expression) <case REALPART_EXPR>: Assert that refs->is_empty () rather than probe == target. (cxx_eval_store_expression) <case IMAGPART_EXPR>: Likewise. * g++.dg/cpp1y/constexpr-complex2.C: New test.
2025-02-28c++: Adjust #embed support for P1967R14Jakub Jelinek6-5/+26
Now that the #embed paper has been voted in, the following patch removes the pedwarn for C++26 on it (and adjusts pedwarn warning for older C++ versions) and predefines __cpp_pp_embed FTM. Also, the patch changes cpp_error to cpp_pedwarning with for C++ -Wc++26-extensions guarding, and for C add -Wc11-c23-compat warning about #embed. I believe we otherwise implement everything in the paper already, except I'm really confused by the [Example: #embed <data.dat> limit(__has_include("a.h")) #if __has_embed(<data.dat> limit(__has_include("a.h"))) // ill-formed: __has_include [cpp.cond] cannot appear here #endif — end example] part. My reading of both C23 and C++ with the P1967R14 paper in is that the first case (#embed with __has_include or __has_embed in its clauses) is what is clearly invalid and so the ill-formed note should be for #embed. And the __has_include/__has_embed in __has_embed is actually questionable. Both C and C++ have something like "The identifiers __has_include, __has_embed, and __has_c_attribute shall not appear in any context not mentioned in this subclause." or "The identifiers __has_include and __has_cpp_attribute shall not appear in any context not mentioned in this subclause." (into which P1967R14 adds __has_embed) in the conditional inclusion subclause. #embed is defined in a different one, so using those in there is invalid (unless "using the rules specified for conditional inclusion" wording e.g. in limit clause overrides that). The reason why I think it is fuzzy for __has_embed is that __has_embed is actually defined in the Conditional inclusion subclause (so that would mean one can use __has_include, __has_embed and __has_*attribute in there) but its clauses are described in a different one. GCC currently accepts #embed __FILE__ limit (__has_include (<stdarg.h>)) #if __has_embed (__FILE__ limit (__has_include (<stdarg.h>))) #endif #embed __FILE__ limit (__has_embed (__FILE__)) #if __has_embed (__FILE__ limit (__has_embed (__FILE__))) #endif Note, it isn't just about limit clause, but also about prefix/suffix/if_empty, except that in those cases the "using the rules specified for conditional inclusion" doesn't apply. In any case, I'd hope that can be dealt with incrementally (and should be handled the same for both C and C++). 2025-02-28 Jakub Jelinek <jakub@redhat.com> libcpp/ * include/cpplib.h (enum cpp_warning_reason): Add CPP_W_CXX26_EXTENSIONS enumerator. * init.cc (lang_defaults): Set embed for GNUCXX26 and CXX26. * directives.cc (do_embed): Adjust pedwarn wording for embed in C++, use cpp_pedwarning instead of cpp_error and add CPP_W_C11_C23_COMPAT warning of cpp_pedwarning hasn't diagnosed anything. gcc/c-family/ * c.opt (Wc++26-extensions): Add CppReason(CPP_W_CXX26_EXTENSIONS). * c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_pp_embed=202502 for C++26. gcc/testsuite/ * g++.dg/cpp/embed-1.C: Adjust for pedwarn wording change and don't expect any error for C++26. * g++.dg/cpp/embed-2.C: Adjust for pedwarn wording change and don't expect any warning for C++26. * g++.dg/cpp26/feat-cxx26.C: Test __cpp_pp_embed value. * gcc.dg/cpp/embed-17.c: New test.
2025-02-28lto/91299 - weak definition inlined with LTORichard Biener3-1/+23
The following fixes a thinko in the handling of interposed weak definitions which confused the interposition check in get_availability by setting DECL_EXTERNAL too early. PR lto/91299 gcc/lto/ * lto-symtab.cc (lto_symtab_merge_symbols): Set DECL_EXTERNAL only after calling get_availability. gcc/testsuite/ * gcc.dg/lto/pr91299_0.c: New testcase. * gcc.dg/lto/pr91299_1.c: Likewise.
2025-02-28ipa/111245 - bogus modref analysis for store in call that might throwRichard Biener2-2/+24
We currently record a kill for *x_4(D) = always_throws (); because we consider the store always executing since the appropriate check for whether the stmt could throw is guarded by !cfun->can_throw_non_call_exceptions. PR ipa/111245 * ipa-modref.cc (modref_access_analysis::analyze_store): Do not guard the check of whether the stmt could throw by cfun->can_throw_non_call_exceptions. * g++.dg/torture/pr111245.C: New testcase.
2025-02-28ifcvt: Fix ICE with (fix:SI (fix:DF (reg:DF))) [PR117712]Jakub Jelinek2-1/+26
As documented in the manual, FIX/UNSIGNED_FIX from floating point mode to integral mode has unspecified rounding and FIX from floating point mode to the same floating point mode is expressing rounding toward zero. So, some targets (arc, arm, csky, m68k, mmix, nds32, pdp11, sparc and visium) use (fix:SI (fix:SF (match_operand:SF 1 "..._operand"))) etc. to express the rounding toward zero during conversion to integer. For some reason other targets don't use that. Anyway, the 2 FIXes (or inner FIX with outer UNSIGNED_FIX) cause problems since the r15-2890 which removed some strict checks in ifcvt.cc on what SET_SRC can be actually conditionalized (I must say I'm still worried about the change, don't know why one can't get e.g. inline asm or something with UNSPEC or some complex backend specific RTLs that force_operand can't handle), force_operand just ICEs on it, it can only handle (through expand_fix) conversions from floating point to integral. The following patch fixes this by detecting this case and just pretend the inner FIX isn't there, i.e. call expand_fix with the inner FIX's operand instead, which works and on targets like arm it will just create the nested FIXes again. 2025-02-28 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/117712 * expr.cc (force_operand): Handle {,UNSIGNED_}FIX with FIX operand using expand_fix on the inner FIX operand. * gcc.dg/pr117712.c: New test.
2025-02-28tree-optimization/87984 - hard register assignments not preservedRichard Biener3-1/+28
The following disables redundant store elimination to hard register variables which isn't valid. PR tree-optimization/87984 * tree-ssa-dom.cc (dom_opt_dom_walker::optimize_stmt): Do not perform redundant store elimination to hard register variables. * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): Likewise. * gcc.target/i386/pr87984.c: New testcase.
2025-02-28middle-end/66279 - gimplification clobbers shared asm constraintsRichard Biener2-0/+24
When the C++ frontend clones a CTOR we do not copy ASM_EXPR constraints fully as walk_tree does not recurse to TREE_PURPOSE of TREE_LIST nodes. At this point doing that seems too dangerous so the following instead avoids gimplification of ASM_EXPRs to clobber the shared constraints and unshares it there, like it also unshares TREE_VALUE when it re-writes a "+" output constraint to separate "=" output and matching input constraint. PR middle-end/66279 * gimplify.cc (gimplify_asm_expr): Copy TREE_PURPOSE before rewriting it for "+" processing. * g++.dg/pr66279.C: New testcase.
2025-02-28testsuite: Remove -m32 from another i386/ testJakub Jelinek1-1/+1
I found another test which uses -m32 in gcc.target/i386/ . Similarly to the previously posted test, the test ought to be tested during i686-linux testing or x86_64-linux test with --target_board=unix\{-m32,-m64\} There is nothing ia32 specific on the test, so I've just dropped the -m32. 2025-02-28 Jakub Jelinek <jakub@redhat.com> * gcc.target/i386/strub-pr118006.c: Remove -m32 from dg-options.
2025-02-28testsuite: Fix up gcc.target/i386/pr118940.c test [PR118940]Jakub Jelinek1-124/+27
The testcase uses -m32 in dg-options, something we try hard not to do, if something should be tested only for -m32, it is { target ia32 } test, if it can be tested for -m64/-mx32 too, just some extra options are needed for ia32, it should have dg-additional-options with ia32 target. Also, the test wasn't reduced, so I've reduced it using cvise and manual tweaks and verified the test still FAILs before r15-7700 and succeeds with current trunk. 2025-02-28 Jakub Jelinek <jakub@redhat.com> PR target/118940 * gcc.target/i386/pr118940.c: Drop -w, -g and -m32 from dg-options, move -march=i386 -mregparm=3 to dg-additional-options for ia32 and -fno-pie to dg-additional-options for pie. Reduce the test.
2025-02-28Fortran: Ensure finalizer is called for unreferenced variable [PR118730]Andre Vehreschild5-3/+44
PR fortran/118730 gcc/fortran/ChangeLog: * resolve.cc: Mark unused derived type variable with finalizers referenced to execute finalizer when leaving scope. gcc/testsuite/ChangeLog: * gfortran.dg/class_array_15.f03: Remove unused variable. * gfortran.dg/coarray_poly_7.f90: Adapt scan-tree-dump expr. * gfortran.dg/coarray_poly_8.f90: Same. * gfortran.dg/finalize_60.f90: New test.
2025-02-28x86: Move TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P to i386.ccH.J. Lu2-6/+6
Move the TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P target hook from i386.h to i386.cc. * config/i386/i386.h (TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P): Moved to ... * config/i386/i386.cc (TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P): Here. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-02-28Daily bump.GCC Administrator5-1/+198
2025-02-28RISC-V: Fix bug for expand_const_vector interleave [PR118931]Pan Li2-7/+48
This patch would like to fix one bug when expanding const vector for the interleave case. For example, we have: base1 = 151 step = 121 For vec_series, we will generate vector in format of v[i] = base + i * step. Then the vec_series will have below result for HImode, and we can find that the result overflow to the highest 8 bits of HImode. v1.b = {151, 255, 7, 0, 119, 0, 231, 0, 87, 1, 199, 1, 55, 2, 167, 2} Aka we expect v1.b should be: v1.b = {151, 0, 7, 0, 119, 0, 231, 0, 87, 0, 199, 0, 55, 0, 167, 0} After that it will perform the IOR with v2 for the base2(aka another series). v2.b = {0, 17, 0, 33, 0, 49, 0, 65, 0, 81, 0, 97, 0, 113, 0, 129} Unfortunately, the base1 + i * step1 in HImode may overflow to the high 8 bits, and the high 8 bits will pollute the v2 and result in incorrect value in const_vector. This patch would like to perform the overflow to smode check before the optimized interleave code generation. If overflow or VLA, it will fall back to the default merge approach. The below test suites are passed for this patch. * The rv64gcv fully regression test. PR target/118931 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Add overflow to smode check and clean up highest bits if overflow. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr118931-run-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>