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2015-07-23I6400 scheduling.Prachi Godbole8-4/+184
gcc/ * config/mips/i6400.md: New file. * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400. (mips64r6): Likewise. (i6400): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add I6400 processor. (mips_issue_rate): Add support for i6400. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h (TUNE_I6400): Define. * config/mips/mips.md: Include i6400.md. (processor): Add i6400. * doc/invoke.texi (-march=@var{arch}): Add i6400. From-SVN: r226090
2015-07-23re PR middle-end/66916 (FAIL: gcc.target/arm/pr43920-2.c object-size text <= 54)Richard Biener2-1/+8
2015-07-23 Richard Biener <rguenther@suse.de> PR middle-end/66916 * match.pd: Guard widen and sign-change comparison simplification with single_use. From-SVN: r226089
2015-07-23re PR middle-end/66945 (ICE in generic_simplify (generic-match.c:24790))Richard Biener4-3/+48
2015-07-23 Richard Biener <rguenther@suse.de> PR tree-optimization/66945 * tree-ssa-propagate.c (substitute_and_fold_dom_walker ::before_dom_children): Force the propagators idea of non-executable edges to materialize, not what the folder chooses. * gcc.dg/torture/pr66945.c: New testcase. From-SVN: r226088
2015-07-23gimple.h (gimple_cond_make_false): Use 0 != 0.Richard Biener2-4/+9
2015-07-23 Richard Biener <rguenther@suse.de> * gimple.h (gimple_cond_make_false): Use 0 != 0. (gimple_cond_make_true): Use 1 != 0. From-SVN: r226087
2015-07-22t-msp430 (MULTILIB_DIRNAMES): Remove trailing slashes.DJ Delorie5-11/+60
* config/msp430/t-msp430 (MULTILIB_DIRNAMES): Remove trailing slashes. * config/msp430/msp430.md (ashlhi3): Optimize shifts of subregs. (ashrhi3): Likewise. (lshrhi3): Likewise. (movhi): Take advantage of zero-extend to load small constants. (movpsi): Likewise. (and<mode>3): Likewise. (zero_extendqihi2): Likewise. (zero_extendqisi2): New. * config/msp430/constraints.md (N,O): New. * config/msp430/msp430.h (WORD_REGISTER_OPERATIONS): Define. From-SVN: r226085
2015-07-23Daily bump.GCC Administrator1-1/+1
From-SVN: r226084
2015-07-22re PR target/66954 (function multiversioning fails for target "aes")Uros Bizjak4-2/+54
libgcc/ChangeLog: PR target/66954 * config/i386/cpuinfo.c (enum processor_features): Add FEATURE_AES. (get_available_features): Handle FEATURE_AES. gcc/ChangeLog: PR target/66954 * config/i386/i386.c (get_builtin_code_for_version): Add P_AES to enum feature_priority and feature_list. (fold_builtin_cpu): Add F_AES to enum processor_features and isa_names_table. gcc/testsuite/ChangeLog: PR target/66954 * g++.dg/ext/mv24.C: New test. From-SVN: r226081
2015-07-22unpack.c: Use dg-additional-options rather than dg-options.Marek Polacek2-1/+6
* gcc.dg/vmx/unpack.c: Use dg-additional-options rather than dg-options. From-SVN: r226078
2015-07-22re PR driver/66737 (ld: warning: -z bndplt ignored)Ilya Enkovich2-1/+11
PR driver/66737 * config/i386/linux-common.h (MPX_SPEC): Use linker option for 64bit target only. From-SVN: r226076
2015-07-22* config/nvptx/nvptx.c: Expand some comments.Bernd Schmidt2-5/+28
From-SVN: r226075
2015-07-22Fix r225926's iso_varying_string ICE regressionMikael Morin4-1/+59
PR fortran/61831 PR fortran/66929 gcc/fortran/ * trans-array.c (gfc_get_proc_ifc_for_expr): Use esym as procedure symbol if available. gcc/testsuite/ * gfortran.dg/generic_30.f90: New. From-SVN: r226074
2015-07-22[Patch ARM/AArch64 obvious] Fix typo: Rename insn_reservation ↵James Greenhalgh2-1/+6
cortex_53_advsimd to cortex_a53_advsimd gcc/ * config/arm/cortex-a53 (cortex_53_advsimd): Rename to... (cortex_a53_advsimd): ...This. From-SVN: r226069
2015-07-22genmatch.c (expr::gen_transform): Clarify error message and display location.Richard Biener2-1/+6
2015-07-22 Richard Biener <rguenther@suse.de> * genmatch.c (expr::gen_transform): Clarify error message and display location. From-SVN: r226068
2015-07-22genmatch.c (struct operand): Add location member.Richard Biener2-72/+76
2015-07-22 Richard Biener <rguenther@suse.de> * genmatch.c (struct operand): Add location member. (predicate, expr, c_expr, capture, if_expr, with_expr): Adjust constructors. (struct simplify): Remove match_location and result_location members. (elsehwere): Adjust. From-SVN: r226067
2015-07-22Add scheduling for M51xx core family.Prachi Godbole8-20/+280
gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=m5100 and -march=m5101 to -mips32r5. (MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float. (MIPS_ISA_NAN2008_SPEC): Map -march=m51* to -mnan=2008 if !-msoft-float. * config/mips/mips.md: Include m5100.md. (processor): Add m5100. * doc/invoke.texi (-march=@var{arch}): Add m5100, m5101. From-SVN: r226066
2015-07-22Add -march=interaptiv.Robert Suchanek5-20/+37
gcc/ * config/mips/mips-cpus.def (interaptiv): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=interaptiv to -mips32r2. (BASE_DRIVER_SELF_SPECS): Likewise but map to -mdsp. * doc/invoke.texi (-march=@var{arch}): Add interaptiv. From-SVN: r226065
2015-07-22[AArch64] PR target/63521 Define REG_ALLOC_ORDERJiong Wang2-0/+31
2015-07-22 Jiong Wang <jiong.wang@arm.com> gcc/ PR target/63521 * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define. (HONOR_REG_ALLOC_ORDER): Define. From-SVN: r226064
2015-07-22re PR tree-optimization/66952 (wrong code at -O2 and -O3 on x86_64-linux-gnu)Richard Biener6-1/+76
2015-07-22 Richard Biener <rguenther@suse.de> PR tree-optimization/66952 * tree-ssa-ifcombine.c (pass_tree_ifcombine::execute): For blocks we end up executing unconditionally reset all SSA info such as range and alignment. * tree-ssanames.h (reset_flow_sensitive_info): Declare. * tree-ssanames.c (reset_flow_sensitive_info): New function. * gcc.dg/torture/pr66952.c: New testcase. From-SVN: r226062
2015-07-22aarch64-simd.md (vec_store_lanesoi_lane<mode>): Fix typo in attribute.Charles Baylis2-1/+6
2015-07-22 Charles Baylis <charles.baylis@linaro.org> * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Fix typo in attribute. From-SVN: r226061
2015-07-22genmatch.c (parser::parse_result): Properly handle match with result ↵Richard Biener2-0/+6
operands and conditions. 2015-07-22 Richard Biener <rguenther@suse.de> * genmatch.c (parser::parse_result): Properly handle match with result operands and conditions. From-SVN: r226060
2015-07-22re PR target/63870 ([Aarch64] [ARM] Errors in use of NEON intrinsics are ↵Charles Baylis138-179/+2621
reported incorrectly) gcc/ChangeLog: 2015-07-22 Charles Baylis <charles.baylis@linaro.org> PR target/63870 * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_struct_load_store_lane_index. (aarch64_types_loadstruct_lane_qualifiers): Use qualifier_struct_load_store_lane_index for lane index argument for last argument. (aarch64_types_storestruct_lane_qualifiers): Ditto. (builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_args): Add new argument describing mode of builtin. Check lane bounds for arguments with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_builtin): Emit error for incorrect lane indices if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX. (aarch64_simd_expand_builtin): Handle arguments with qualifier_struct_load_store_lane_index. Pass machine mode of builtin to aarch64_simd_expand_args. * config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and vst[234]_lane with BUILTIN_VALLDIF. * config/aarch64/aarch64-simd.md: (aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform endianness reversal on lane index. (aarch64_vec_load_lanesci_lane<mode>): Ditto. (aarch64_vec_load_lanesxi_lane<mode>): Ditto. (vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. (vec_store_lanesci_lane<mode>): Ditto. (vec_store_lanesxi_lane<mode>): Ditto. (aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness reversal of lane index. (aarch64_ld3_lane<mode>): Ditto. (aarch64_ld4_lane<mode>): Ditto. (aarch64_st2_lane<mode>): Ditto. (aarch64_st3_lane<mode>): Ditto. (aarch64_st4_lane<mode>): Ditto. * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter to qmode. Add new mode parameter. Update uses. (__LD3_LANE_FUNC): Ditto. (__LD4_LANE_FUNC): Ditto. (__ST2_LANE_FUNC): Ditto. (__ST3_LANE_FUNC): Ditto. (__ST4_LANE_FUNC): Ditto. gcc/testsuite/ChangeLog: 2015-07-22 Charles Baylis <charles.baylis@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New test. From-SVN: r226059
2015-07-22invoke.texi (Language Independent Options): Rename node to Diagnostic ↵Jonathan Wakely2-5/+10
Message Formatting Options. * doc/invoke.texi (Language Independent Options): Rename node to Diagnostic Message Formatting Options. From-SVN: r226058
2015-07-22Daily bump.GCC Administrator1-1/+1
From-SVN: r226057
2015-07-21decl.c (grokdeclarator): For an erroneous template parameter propagate ↵Paolo Carlini4-3/+16
error_mark_node as type. /cp 2015-07-21 Paolo Carlini <paolo.carlini@oracle.com> * decl.c (grokdeclarator): For an erroneous template parameter propagate error_mark_node as type. /testsuite 2015-07-21 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/template/crash81.C: Update. From-SVN: r226054
2015-07-21re PR ipa/66424 (wrong code at -O2 and -O3 on x86_64-linux-gnu in 32-bit mode)Vladimir Makarov4-0/+72
2015-07-21 Vladimir Makarov <vmakarov@redhat.com> PR ipa/66424. * lra-remat.c (operand_to_remat): Prevent using insns with input subregs processed separately by IRA. 2015-07-21 Vladimir Makarov <vmakarov@redhat.com> PR ipa/66424. * gcc.target/i386/pr66424.c: New. From-SVN: r226053
2015-07-21ssa-iterators.h (has_zero_uses, [...]): Implement as straight loops.Andrew MacLeod3-53/+37
2015-07-21 Andrew MacLeod <amacleod@redhat.com> * ssa-iterators.h (has_zero_uses, has_single_use): Implement as straight loops. (single_imm_use): Check for iterator node. (num_imm_uses): Likewise. * tree-ssa-operands.c (has_zero_uses_1): Delete. (single_imm_use_1): Check for iterator node. From-SVN: r226051
2015-07-21configure.ac: Add check for new options in isl-0.15.Mike Frysinger14-9/+103
* configure.ac: Add check for new options in isl-0.15. * config.in, configure: Rebuilt. * graphite-blocking.c: Include <isl/constraint.h> * graphite-interchange.c, graphite-poly.c: Likewise. * graphhite-scop-detection.c, graphite-sese-to-poly.c: Likewise. * graphite.c: Likewise. * graphite-isl-ast-to-gimple.c: Include <isl/constraint.h> and <isl/union_set.h>. * graphite-dependences.c: Include <isl/constraint.h>. (max_number_of_out_dimensions): Returns isl_stat. (extend_schedule_1): Likewise (extend_schedule): Corresponding changes. * graphite-optimize-isl.c: Include <isl/constraint.h> and <isl/union_set.h>. (getSingleMap): Change return type of isl_stat. (optimize_isl): Conditionally use isl_options_set_schedule_serialize_sccs. * graphite-poly.h (isl_stat, isl_stat_ok): Define fallbacks if not HAVE_ISL_OPTIONS_SET_SCHEDULE_SERIALIZE_SCCS. Co-Authored-By: Bernhard Reutner-Fischer <aldot@gcc.gnu.org> From-SVN: r226050
2015-07-21re PR target/66956 ([avr] Using 32*32=64 multiplicatiion (umulsidi3) for ↵Georg-Johann Lay2-2/+10
32=32*32 without MUL.) PR target/66956 * config/avr/avr-dimode.md (<extend_u>mulsidi3_insn) (<extend_u>mulsidi3): Don't use if !AVR_HAVE_MUL. From-SVN: r226046
2015-07-21thumb-bitfld1.c (foo): Add explicit return type.Alex Velenko2-0/+6
2015-07-21 Alex Velenko <Alex.Velenko@arm.com> * gcc.target/arm/thumb-bitfld1.c (foo): Add explicit return type. From-SVN: r226043
2015-07-21re PR tree-optimization/66948 (Performance regression in bit manipulation code)Richard Biener3-8/+28
2015-07-21 Richard Biener <rguenther@suse.de> PR tree-optimization/66948 * genmatch.c (capture_info::walk_match): Also recurse to captures. Properly compute expr state from captures of captures. * match.pd: Add single-use guards to (X & C2) >> C1 into (X >> C1) & (C2 >> C1) transform. From-SVN: r226041
2015-07-21target.c (gomp_offload_image_to_device): Rename to ...Nathan Sidwell2-5/+20
libgomp/ * target.c (gomp_offload_image_to_device): Rename to ... (gomp_load_image_to_device): ... here. (GOMP_offload_register): Adjust call. (gomp_init_device): Likewise. (gomp_unload_image_from_device): New. Broken out of ... (GOMP_offload_unregister): ... here. Call it. (gomp_unload_device): New. * libgomp.h (gomp_unload_device): Declare. * oacc-init.c (acc_shutdown_1): Unload from device before deleting mem maps. gcc/ * config/nvptx/mkoffload.c (process): Add static destructor call. From-SVN: r226039
2015-07-21Fix r225926's broken testcaseMikael Morin2-3/+9
gcc/testsuite/ PR fortran/61831 * gfortran.dg/derived_constructor_comps_6.f90: Fix dg directive. Drop address sanitization. From-SVN: r226038
2015-07-21split-live-ranges-for-shrink-wrap.c (dg-skip-if): Skip -march=armv4t.Alex Velenko2-0/+8
2015-07-21 Alex Velenko <Alex.Velenko@arm.com> gcc/testsuite/ * gcc.target/arm/split-live-ranges-for-shrink-wrap.c (dg-skip-if): Skip -march=armv4t. (dg-additional-options): Set armv5t flag. From-SVN: r226036
2015-07-21Fix ChangeLog of r225926 (PR fortran/61831)Mikael Morin1-1/+1
From-SVN: r226033
2015-07-21unpack-be-order.c: Use -Wno-shift-overflow.Marek Polacek4-2/+10
* gcc.dg/vmx/unpack-be-order.c: Use -Wno-shift-overflow. * gcc.dg/vmx/unpack.c: Likewise. * gcc.target/powerpc/quad-atomic.c: Likewise. From-SVN: r226032
2015-07-21[match.pd] PR middle-end/66915 Restrict A - B -> A + (-B) to non-fixed-point ↵Kyrylo Tkachov2-2/+8
types PR middle-end/66915 * match.pd (A - B -> A + (-B)): Don't allow folding when type if a fixed-point type. From-SVN: r226028
2015-07-21Daily bump.GCC Administrator1-1/+1
From-SVN: r226026
2015-07-20rl78-real.md (andqi3_real): Expand operands for clr1.DJ Delorie2-2/+7
* config/rl78/rl78-real.md (andqi3_real): Expand operands for clr1. (iorqi3_real): Likewise for set1. From-SVN: r226023
2015-07-20i386.c (ix86_md_asm_adjust): Handle DImode dest_mode for !TARGET_64BIT.Uros Bizjak4-2/+25
* config/i386/i386.c (ix86_md_asm_adjust): Handle DImode dest_mode for !TARGET_64BIT. testsuite/ChangeLog: * gcc.target/i386/asm-flag-5.c (f_ll): New. From-SVN: r226017
2015-07-20add missing changelogAditya Kumar1-0/+6
From-SVN: r226015
2015-07-20Refactor graphite-isl-ast-to-gimple.cAditya Kumar1-32/+180
Refactor graphite-isl-ast-to-gimple.c: Refactor so that each function can access 'region'. This will help maintain a parameter rename_map within a region. No functional change intended. This patch will be followed by another set of patches where translate_isl_ast_to_gimple::region is used to keep parameters which need renaming. Since we are planning to remove limit_scops, we now have to maintain a set of parameters which needs renaming. This refactoring helps avoid passing `region' to all the functions in this file. It passes bootstrap and regtest. gcc/ChangeLog: 2015-07-19 Aditya Kumar <hiraditya@msn.com> * graphite-isl-ast-to-gimple.c: Refactor so that each function can access 'region'. This will help maintain a parameter rename_map within a region. From-SVN: r226014
2015-07-20compiler: Create dummy labels for blank labels.Ian Lance Taylor3-6/+26
Fixes golang/go#11591. Reviewed-on: https://go-review.googlesource.com/12043 From-SVN: r226009
2015-07-20compiler: Remove unnecessary check for GCC-specific issue.Ian Lance Taylor2-13/+2
Reviewed-on: https://go-review.googlesource.com/11800 compiler: remove name of unused parameter to avoid warning Reviewed-on: https://go-review.googlesource.com/12367 From-SVN: r226007
2015-07-20* config/rs6000/rs6000.md (*lt0_disi): New.Segher Boessenkool2-0/+15
From-SVN: r226006
2015-07-20re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)Segher Boessenkool7-1478/+930
PR target/66217 * config/rs6000/constraints.md ("S", "T", "t"): Delete. Update "available letters" comment. * config/rs6000/predicates.md (mask_operand, mask_operand_wrap, mask64_operand, mask64_2_operand, any_mask_operand, and64_2_operand, and_2rld_operand): Delete. (and_operand): Adjust. (rotate_mask_operator): New. * config/rs6000/rs6000-protos.h (build_mask64_2_operands, includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p, includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete. (rs6000_is_valid_mask, rs6000_is_valid_and_mask, rs6000_is_valid_shift_mask, rs6000_is_valid_insert_mask, rs6000_insn_for_and_mask, rs6000_insn_for_shift_mask, rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and, rs6000_emit_2insn_and): New. * config/rs6000/rs6000.c (num_insns_constant): Adjust. (build_mask64_2_operands, includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p, includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete. (rs6000_is_valid_mask, rs6000_is_valid_and_mask, rs6000_insn_for_and_mask, rs6000_is_valid_shift_mask, s6000_insn_for_shift_mask, rs6000_is_valid_insert_mask, rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and, rs6000_emit_2insn_and): New. (print_operand) <'b', 'B', 'm', 'M', 's', 'S', 'W'>: Delete. (rs6000_rtx_costs) <CONST_INT>: Delete mask_operand and mask64_operand handling. <NOT>: Don't fall through to next case. <AND>: Handle the various rotate-and-mask cases directly. <IOR>: Always cost as one insn. * config/rs6000/rs6000.md (splitter for bswap:SI): Adjust. (and<mode>3): Adjust expander for the new patterns. (and<mode>3_imm, and<mode>3_imm_dot, and<mode>3_imm_dot2, and<mode>3_imm_mask_dot, and<mode>3_imm_mask_dot2): Adjust condition. (*and<mode>3_imm_dot_shifted): New. (*and<mode>3_mask): Delete, rewrite as ... (and<mode>3_mask): ... New. (*and<mode>3_mask_dot, *and<mode>3_mask_dot): Rewrite. (andsi3_internal0_nomc): Delete. (*andsi3_internal6): Delete. (*and<mode>3_2insn): New. (insv, insvsi_internal, *insvsi_internal1, *insvsi_internal2, *insvsi_internal3, *insvsi_internal4, *insvsi_internal5, *insvsi_internal6, insvdi_internal, *insvdi_internal2, *insvdi_internal3): Delete. (*rotl<mode>3_mask, *rotl<mode>3_mask_dot, *rotl<mode>3_mask_dot2, *rotl<mode>3_insert, *rotl<mode>3_insert_2, *rotl<mode>3_insert_3, *rotl<mode>3_insert_4, two splitters for multi-precision shifts, *ior<mode>_mask): New. (extzv, extzvdi_internal, *extzvdi_internal1, *extzvdi_internal2, *rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2, *ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2, *lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2): Delete. (ashr<mode>3): Delete expander. (*ashr<mode>3): Rename to ... (ashr<mode>3): ... This. (ashrdi3_no_power, *ashrdisi3_noppc64be): Delete. (*rotldi3_internal4, *rotldi3_internal5 and split, *rotldi3_internal6 and split, *ashldi3_internal4, ashldi3_internal5 and split, *ashldi3_internal6 and split, *ashldi3_internal7, ashldi3_internal8 and split, *ashldi3_internal9 and split): Delete. (*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): Delete. (splitter for loading a mask): Adjust. * doc/md.texi (Machine Constraints): Remove q, S, T, t constraints. From-SVN: r226005
2015-07-20genemit.c (print_code, [...]): Remove declarations.Marek Polacek2-8/+6
* genemit.c (print_code, gen_exp, gen_insn, gen_expand, gen_split, output_add_clobbers, output_added_clobbers_hard_reg_p, gen_rtx_scratch): Remove declarations. From-SVN: r226003
2015-07-20[AArch64][testcase] Restrict got_mem_hoist_1.c with small memory modelJiong Wang2-0/+6
From-SVN: r225999
2015-07-20re PR c++/55095 (Wshift-overflow)Marek Polacek27-13/+473
PR c++/55095 * c-common.c (c_fully_fold_internal): Warn about left shift overflows. Use EXPR_LOC_OR_LOC. (maybe_warn_shift_overflow): New function. * c-common.h (maybe_warn_shift_overflow): Declare. * c-opts.c (c_common_post_options): Set warn_shift_overflow. * c.opt (Wshift-overflow): New option. * c-typeck.c (digest_init): Pass OPT_Wpedantic to pedwarn_init. (build_binary_op): Warn about left shift overflows. * typeck.c (cp_build_binary_op): Warn about left shift overflows. * doc/invoke.texi: Document -Wshift-overflow and -Wshift-overflow=. * c-c++-common/Wshift-overflow-1.c: New test. * c-c++-common/Wshift-overflow-2.c: New test. * c-c++-common/Wshift-overflow-3.c: New test. * c-c++-common/Wshift-overflow-4.c: New test. * c-c++-common/Wshift-overflow-5.c: New test. * g++.dg/cpp1y/left-shift-1.C: New test. * gcc.dg/c90-left-shift-2.c: New test. * gcc.dg/c90-left-shift-3.c: New test. * gcc.dg/c99-left-shift-2.c: New test. * gcc.dg/c99-left-shift-3.c: New test. * gcc.dg/pr40501.c: Use -Wno-shift-overflow. * gcc.c-torture/execute/pr40386.c: Likewise. * gcc.dg/vect/pr33373.c: Likewise. * gcc.dg/vect/vect-shift-2-big-array.c: Likewise. * gcc.dg/vect/vect-shift-2.c: Likewise. Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com> From-SVN: r225998
2015-07-20[simplify-rtx][2/2] Simplify - (y ? -x : x) -> (!y ? -x : x)Kyrylo Tkachov4-0/+52
* simplify-rtx.c (simplify_unary_operation_1, NEG case): (neg (x ? (neg y) : y)) -> !x ? (neg y) : y. * gcc.target/aarch64/neg_abs_1.c: New test. From-SVN: r225997
2015-07-20[PATCH][combine][1/2] Try to simplify before substitutingKyrylo Tkachov2-45/+50
* combine.c (combine_simplify_rtx): Move simplification step before various transformations/substitutions. From-SVN: r225996
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