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2016-09-23S/390: Mode attrs "bitoff[_plus]" simplify risbg instructions.Dominik Vogt4-15/+31
Add a new mode attribute to simplify some instruction patterns. gcc/ChangeLog: 2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com> * config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes. ("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10") ("*insv<mode>_zEC12_appendbitsleft") ("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll") ("*r<noxa>sbg_<mode>_srl"): Use new attributes. gcc/testsuite/ChangeLog: 2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com> * gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly output to the simplified instructions. From-SVN: r240409
2016-09-23ipa-cp.c (ipcp_store_vr_results): Avoid static local var zero.Jakub Jelinek6-9/+24
* ipa-cp.c (ipcp_store_vr_results): Avoid static local var zero. * sreal.h (sreal::min, sreal::max): Avoid static local vars, construct values without normalization. * tree-ssa-sccvn.c (vn_reference_lookup_3): Don't initialize static local lhs_ops to vNULL. cp/ * name-lookup.c (store_bindings, store_class_bindings): Don't initialize static local bindings_need_stored to vNULL. From-SVN: r240408
2016-09-23[PATCH 7/17][ARM] Add FP16 data movement instructions.Matthew Wahab7-15/+467
gcc/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> Jiong Wang <jiong.wang@arm.com> * config/arm/arm.c (coproc_secondary_reload_class): Make HFmode available when FP16 instructions are available. (output_move_vfp): Add support for 16-bit data moves. (arm_validize_comparison): Fix some white-space. Support HFmode by conversion to SFmode. * config/arm/arm.md (truncdfhf2): Fix a comment. (extendhfdf2): Likewise. (cstorehf4): New. (movsicc): Fix some white-space. (movhfcc): New. (movsfcc): Fix some white-space. (*cmovhf): New. * config/arm/vfp.md (*arm_movhi_vfp): Disable when VFP FP16 instructions are available. (*thumb2_movhi_vfp): Likewise. (*arm_movhi_fp16): New. (*thumb2_movhi_fp16): New. (*movhf_vfp_fp16): New. (*movhf_vfp_neon): Disable when VFP FP16 instructions are available. (*movhf_vfp): Likewise. (extendhfsf2): Enable when VFP FP16 instructions are available. (truncsfhf2): Enable when VFP FP16 instructions are available. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/arm/armv8_2_fp16-move-1.c: New. * gcc.target/arm/fp16-aapcs-1.c: Update expected output. Co-Authored-By: Jiong Wang <jiong.wang@arm.com> From-SVN: r240407
2016-09-23Fix typos: adress -> addressMartin Liska2-2/+6
* config/s390/vx-builtins.md: Replace 'adress' with 'address'. From-SVN: r240406
2016-09-23gcc-dg.exp (process-message): Support relative line number notation - .+4 or ↵Jakub Jelinek1-0/+18
.-1 etc. * lib/gcc-dg.exp (process-message): Support relative line number notation - .+4 or .-1 etc. * gcc.dg/dg-test-1.c: New test. From-SVN: r240405
2016-09-23[PATCH 6/17][ARM] Add data processing intrinsics for float16_t.Matthew Wahab18-49/+650
gcc/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm.c (arm_evpc_neon_vuzp): Add support for V8HF and V4HF modes. (arm_evpc_neon_vtrn): Likewise. (arm_evpc_neon_vrev): Likewise. (arm_evpc_neon_vext): Likewise. * config/arm/arm_neon.h (vbsl_f16): New. (vbslq_f16): New. (vdup_n_f16): New. (vdupq_n_f16): New. (vdup_lane_f16): New. (vdupq_lane_f16): New. (vext_f16): New. (vextq_f16): New. (vmov_n_f16): New. (vmovq_n_f16): New. (vrev64_f16): New. (vrev64q_f16): New. (vtrn_f16): New. (vtrnq_f16): New. (vuzp_f16): New. (vuzpq_f16): New. (vzip_f16): New. (vzipq_f16): New. * config/arm/arm_neon_buillins.def (vdup_n): New (v8hf, v4hf variants). (vdup_lane): New (v8hf, v4hf variants). (vext): New (v8hf, v4hf variants). (vbsl): New (v8hf, v4hf variants). * config/arm/iterators.md (VDQWH): New. (VH): New. (V_double_vector_mode): Add V8HF and V4HF. Fix white-space. (Scalar_mul_8_16): Fix white-space. (Is_d_reg): Add V4HF and V8HF. * config/arm/neon.md (neon_vdup_lane<mode>_internal): New. (neon_vdup_lane<mode>): New. (neon_vtrn<mode>_internal): Replace VDQW with VDQWH. (*neon_vtrn<mode>_insn): Likewise. (neon_vzip<mode>_internal): Likewise. Also fix white-space. (*neon_vzip<mode>_insn): Likewise (neon_vuzp<mode>_internal): Likewise. (*neon_vuzp<mode>_insn): Likewise * config/arm/vec-common.md (vec_perm_const<mode>): New. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED): New (expected-hfloat-16x4): Make conditional on __fp16 support. (expected-hfloat-16x8): Likewise. (vdup_n_f16): Disable for non-AArch64 targets. * gcc.target/aarch64/advsimd-intrinsics/vbsl.c: Add __fp16 tests, conditional on FP16_SUPPORTED. * gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vext.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Add support for testing __fp16. * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: Add __fp16 tests, conditional on FP16_SUPPORTED. * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise. From-SVN: r240404
2016-09-23[PATCH 5/17][ARM] Enable HI mode moves for floating point values.Matthew Wahab6-3/+161
gcc/ 2016-09-23 Jiong Wang <jiong.wang@arm.com> Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm.c (output_move_vfp): Weaken assert to allow HImode. (arm_hard_regno_mode_ok): Allow HImode values in VFP registers. * config/arm/arm.md (*movhi_bytes): Disable when VFP registers are available. Also fix some white-space. * config/arm/vfp.md (*arm_movhi_vfp): New. (*thumb2_movhi_vfp): New. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/arm/short-vfp-1.c: New. From-SVN: r240403
2016-09-23[PATCH 4/17][ARM] Define feature macros for FP16.Matthew Wahab4-0/+60
2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm-c.c (arm_cpu_builtins): Define "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" and "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC". testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/arm/attr-fp16-arith-1.c: New. From-SVN: r240402
2016-09-23[PATCH 3/17][Testsuite] Add ARM support for ARMv8.2-A with FP16 arithmetic ↵Matthew Wahab4-0/+207
instructions. gcc/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * doc/sourcebuild.texi (ARM-specific attributes): Add anchor for arm_v8_1a_neon_ok. Add entries for arm_v8_2a_fp16_scalar_ok, arm_v8_2a_fp16_scalar_hw, arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_neon_hw. (Add options): Add entries for arm_v8_1a_neon, arm_v8_2a_scalar, arm_v8_2a_neon. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * lib/target-supports.exp (add_options_for_arm_v8_2a_fp16_scalar): New. (add_options_for_arm_v8_2a_fp16_neon): New. (check_effective_target_arm_arch_v8_2a_ok): Auto-generate. (add_options_for_arm_arch_v8_2a): Auto-generate. (check_effective_target_arm_arch_v8_2a_multilib): Auto-generate. (check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache): New. (check_effective_target_arm_v8_2a_fp16_scalar_ok): New. (check_effective_target_arm_v8_2a_fp16_neon_ok_nocache): New. (check_effective_target_arm_v8_2a_fp16_neon_ok): New. (check_effective_target_arm_v8_2a_fp16_scalar_hw): New. (check_effective_target_arm_v8_2a_fp16_neon_hw): New. From-SVN: r240401
2016-09-23[PATCH 2/17][Testsuite] Add a selector for ARM FP16 alternative format support.Matthew Wahab24-0/+121
2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * doc/sourcebuild.texi (ARM-specific attributes): Add entries for arm_fp16_alternative_ok and arm_fp16_none_ok. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * g++.dg/ext/arm-fp16/arm-fp16-ops-3.C: Use arm_fp16_alternative_ok. * g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise. * gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise. * gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c: Likewise. * gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c: Likewise. * gcc.target/arm/fp16-compile-alt-1.c: Likewise. * gcc.target/arm/fp16-compile-alt-10.c: Likewise. * gcc.target/arm/fp16-compile-alt-11.c: Likewise. * gcc.target/arm/fp16-compile-alt-12.c: Likewise. * gcc.target/arm/fp16-compile-alt-2.c: Likewise. * gcc.target/arm/fp16-compile-alt-3.c: Likewise. * gcc.target/arm/fp16-compile-alt-4.c: Likewise. * gcc.target/arm/fp16-compile-alt-5.c: Likewise. * gcc.target/arm/fp16-compile-alt-6.c: Likewise. * gcc.target/arm/fp16-compile-alt-7.c: Likewise. * gcc.target/arm/fp16-compile-alt-8.c: Likewise. * gcc.target/arm/fp16-compile-alt-9.c: Likewise. * gcc.target/arm/fp16-compile-none-1.c: Use arm_fp16_none_ok. * gcc.target/arm/fp16-compile-none-2.c: Likewise. * gcc.target/arm/fp16-rounding-alt-1.c: Use arm_fp16_alternative_ok. * lib/target-supports.exp (check_effective_target_arm_fp16_alternative_ok_nocache): New. (check_effective_target_arm_fp16_alternative_ok): New. (check_effective_target_arm_fp16_none_ok_nocache): New. (check_effective_target_arm_fp16_none_ok): New. From-SVN: r240400
2016-09-23Fix typo in IPA ICFMartin Liska4-2/+12
* ipa-icf.c (sem_variable::merge): Replace adress with address. * gcc.dg/ipa/pr77653.c: Replace adress with address. From-SVN: r240399
2016-09-23[PATCH 1/17][ARM] Add ARMv8.2-A command line option and profile.Matthew Wahab9-7/+95
2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm-arches.def ("armv8.1-a"): Add FL_CRC32. ("armv8.2-a"): New. ("armv8.2-a+fp16"): New. * config/arm/arm-protos.h (FL2_ARCH8_2): New. (FL2_FP16INST): New. (FL2_FOR_ARCH8_2A): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.c (arm_arch8_2): New. (arm_fp16_inst): New. (arm_option_override): Set arm_arch8_2 and arm_fp16_inst. Check for incompatible fp16-format settings. * config/arm/arm.h (TARGET_VFP_FP16INST): New. (TARGET_NEON_FP16INST): New. (arm_arch8_2): Declare. (arm_fp16_inst): Declare. * config/arm/bpabi.h (BE8_LINK_SPEC): Add entries for march=armv8.2-a and march=armv8.2-a+fp16. * config/arm/t-aprofile (Arch Matches): Add entries for armv8.2-a and armv8.2-a+fp16. * doc/invoke.texi (ARM Options): Add "-march=armv8.1-a", "-march=armv8.2-a" and "-march=armv8.2-a+fp16". From-SVN: r240398
2016-09-23Remove fused-madd from documentationMartin Liska2-5/+5
* doc/extend.texi: Remove fused-madd from i386 target options. From-SVN: r240395
2016-09-23Support movbe as a i386 target optimization nodeMartin Liska4-0/+30
* gcc.target/i386/movbe-4.c: New test. * config/i386/i386.c (ix86_valid_target_attribute_inner_p): Handle movbe. From-SVN: r240394
2016-09-23Support crc32 as a i386 target optimization nodeMartin Liska4-0/+35
* config/i386/i386.c (ix86_valid_target_attribute_inner_p): Handle crc32. * gcc.target/i386/crc32-5.c: New test. From-SVN: r240393
2016-09-23re PR target/71652 (ICE in in ix86_target_macros_internal, at ↵Martin Liska6-23/+102
config/i386/i386-c.c:187) Fix PR target/71652 PR target/71652 * config/i386/i386.c (ix86_option_override_internal): Change signature and return false when there's an error related to arch string. (release_options_strings): New function. (ix86_valid_target_attribute_tree): Call the function. * gcc.target/i386/pr71652.c: New test. * gcc.target/i386/pr71652-2.c: New test. * gcc.target/i386/pr71652-3.c: New test. From-SVN: r240392
2016-09-23gcc-dg.exp (process-message): Support relative line number notation - .+4 or ↵Jakub Jelinek2-0/+13
.-1 etc. * lib/gcc-dg.exp (process-message): Support relative line number notation - .+4 or .-1 etc. * gcc.dg/dg-test-1.c: New test. From-SVN: r240391
2016-09-23* hsa-gen.c (hsa_op_immed::hsa_op_immed Use CONSTRUCTOR_NELTS (...)Jakub Jelinek15-19/+44
instead of vec_safe_length (CONSTRUCTOR_ELTS (...)). (gen_hsa_ctor_assignment): Likewise. * print-tree.c (print_node): Likewise. * tree-dump.c (dequeue_and_dump): Likewise. * tree-sra.c (sra_modify_constructor_assign): Likewise. * expr.c (store_constructor): Likewise. * fold-const.c (operand_equal_p): Likewise. * tree-pretty-print.c (dump_generic_node): Likewise. * hsa-brig.c (hsa_op_immed::emit_to_buffer): Likewise. * ipa-icf-gimple.c (func_checker::compare_operand): Likewise. cp/ * typeck2.c (process_init_constructor_record): Use CONSTRUCTOR_NELTS (...) instead of vec_safe_length (CONSTRUCTOR_ELTS (...)). * decl.c (reshape_init_r): Likewise. (check_initializer): Likewise. ada/ * gcc-interface/decl.c (gnat_to_gnu_entity): Use CONSTRUCTOR_NELTS (...) instead of vec_safe_length (CONSTRUCTOR_ELTS (...)). From-SVN: r240390
2016-09-23hooks.h (hook_uint_uintp_false): Declare.Richard Biener2-0/+5
2016-09-23 Richard Biener <rguenther@suse.de> * hooks.h (hook_uint_uintp_false): Declare. From-SVN: r240389
2016-09-23Provide right LDD offset bound in avr_address_costSenthil Kumar Selvaraj2-2/+11
This patch fixes cost computation in avr_address_cost - instead of the hardcoded 61, it uses the already existing MAX_LD_OFFSET(mode) macro. This showed up when investigating a code size regression in the ivopts pass. That pass computes address_cost with and without an offset to decide on the right induction variable candidate(s). The legitimate address target hook returns false for offsets more than 63, so the pass calls the TARGET_ADDRESS_COST hook with 62 as the offset. The avr_address_cost hook returns 18 as the cost, and the ivopts pass concludes that the cost of address with *any* offset is 18, which is not true - the higher cost is incurred only with offsets bigger than MAX_LD_OFFSET. This in turn results in a suboptimal choice of induction variables in the ivopts pass. The patch changes the hardcoded 61 to use the mode specific MAX_LD_OFFSET instead. Regression testing with just that fix showed one additional compilation timeout. That turned out to be the same as https://lists.nongnu.org/archive/html/avr-gcc-list/2014-03/msg00010.html - the middle end takes too much time to decide on the best strategy to multiply DImode values on a 64 bit host. This already causes timeouts for a few builtin-arith-overflow-* tests (see https://gcc.gnu.org/ml/gcc-testresults/2016-09/msg02018.html), so it isn't really related to this fix. Just providing a cost estimate for DImode mul fixes the timeout though, so the patch does that by scaling SImode costs by 2 for DImode muls. With both changes in, there are no regressions, and the builtin-arith-overflow-* tests now PASS and don't timeout. gcc/ChangeLog 2016-09-22 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> * config/avr/avr.c (avr_rtx_costs_1): Handle DImode MULT. (avr_address_cost): Replace 61 with MAX_LD_OFFSET(mode). From-SVN: r240388
2016-09-23Daily bump.GCC Administrator1-1/+1
From-SVN: r240386
2016-09-22PR target/77676 - powerpc64 and powerpc64le stage2 bootstrap failMartin Sebor8-35/+138
gcc/testsuite/ChangeLog: PR target/77676 * gcc.dg/tree-ssa/builtin-sprintf-1.c: Define and use wint_t. * gcc.dg/tree-ssa/builtin-sprintf-2.c: Fix typo. * gcc.dg/tree-ssa/builtin-sprintf-3.c: New test. * gcc.dg/tree-ssa/builtin-sprintf-warn-5.c: New test. gcc/ChangeLog: PR target/77676 * gimple-ssa-sprintf.c (target_int_min, target_int_max): Use HOST_BITS_PER_WIDE_INT, make a static local variable auto. (target_int_min): Correct computation. (format_integer): Use long long as the argument for the ll length modifier. (format_floating): Use target_int_max(). (get_string_length): Same. (format_string): Avoid setting the bounded flag for strings of unknown length. (try_substitute_return_value): Avoid setting range info when the result isn't bounded. * varasm.c (assemble_name): Increase buffer size. From-SVN: r240383
2016-09-22compiler: compile runtime.getcaller{pc,sp} into builtin functionsIan Lance Taylor7-26/+108
The runtime functions runtime.getcallerpc and runtime.getcallersp are intended to be efficient ways to get the return and frame address of the caller (that is, the caller of runtime.getcallerpc). In the C code that is implemented by simply using C macros: This patch essentially implements those macros in the Go code. It would be nice if we could just use //extern for this, but it doesn't work because the runtime code passes the right argument. Of course we could change the runtime code, but these are common enough that I'd prefer to avoid the difference from the gc version of the runtime code. This patch corrects the existing declaration of __builtin_return_address to use uint32, rather than uint, for the parameter type. The builtin functions take the C type "unsigned int", which for the targets we use corresponds to the Go type uint32. Not that it should matter, really. Reviewed-on: https://go-review.googlesource.com/29653 From-SVN: r240382
2016-09-22ifcvt-1.c: Compile also for 64-bit i?86-*-* target.Uros Bizjak9-11/+26
* gcc.dg/ifcvt-1.c: Compile also for 64-bit i?86-*-* target. * gcc.dg/ifcvt-2.c: Ditto. * gcc.dg/zero_bits_compound-1.c: Ditto. * gcc.dg/zero_bits_compound-1.c: Ditto. * gcc.dg/pr40550.c: Simplify target selectors. Use dg-additional-options. * gcc.dg/pr47893.c: Ditto. * gcc.dg/pr68435.c: Compile also for i?86-*-* target. Add -march=i686 additional options for 32-bit x86 targets. * gcc.dg/pr70955.c: Move to ... * gcc.target/i386/pr70955.c: ... here. Simplify target selector. From-SVN: r240381
2016-09-22re PR c++/61019 (ICE: incomplete type of class template as ↵Paolo Carlini2-0/+15
pseudo-destructor-name) 2016-09-22 Paolo Carlini <paolo.carlini@oracle.com> PR c++/61019 * g++.dg/cpp0x/pr61019.C: New. From-SVN: r240380
2016-09-22[ARM] Add support for -mpure-code optionAndre Vieira13-30/+257
gcc/ChangeLog: 2016-09-22 Andre Vieira <andre.simoesdiasvieira@arm.com> Terry Guo <terry.guo@arm.com> * target.def (elf_flags_numeric): New target hook. * targhooks.h (default_asm_elf_flags_numeric): New. * varasm.c (default_asm_elf_flags_numeric): New. (default_elf_asm_named_section): Use new target hook. * config/arm/arm.opt (mpure-code): New. * config/arm/arm.h (SECTION_ARM_PURECODE): New. * config/arm/arm.c (arm_asm_init_sections): Add section attribute to default text section if -mpure-code. (arm_option_check_internal): Diagnose use of option with non supported targets and/or options. (arm_asm_elf_flags_numeric): New. (arm_function_section): New. (arm_elf_section_type_flags): New. * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable for -mpure-code. * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New. * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise. gcc/testsuite/ChangeLog: 2016-09-22 Andre Vieira <andre.simoesdiasvieira@arm.com> Terry Guo <terry.guo@arm.com> * gcc.target/arm/pure-code/ffunction-sections.c: New. * gcc.target/arm/pure-code/no-literal-pool.c: New. * gcc.target/arm/pure-code/pure-code.exp: New. Co-Authored-By: Terry Guo <terry.guo@arm.com> From-SVN: r240379
2016-09-22gofrontend: add missing break in Builtin_call_expression::do_flattenIan Lance Taylor2-1/+2
Reviewed-on: https://go-review.googlesource.com/29593 From-SVN: r240378
2016-09-22const-2b.c: Also compile for x86_64-*-*.Uros Bizjak2-2/+6
* gcc.dg/debug/dwarf2/const-2b.c: Also compile for x86_64-*-*. Remove SSE effective target requirement. From-SVN: r240377
2016-09-22re PR c++/71979 (ICE with on C++ code with incorrect type in overloaded base ↵Paolo Carlini4-2/+29
class '=' operator: in build_base_path, at cp/class.c:304) /cp 2016-09-22 Paolo Carlini <paolo.carlini@oracle.com> PR c++/71979 * class.c (build_base_path): Allow for lookup_base returning NULL_TREE. /testsuite 2016-09-22 Paolo Carlini <paolo.carlini@oracle.com> PR c++/71979 * g++.dg/cpp0x/pr71979.C: New. From-SVN: r240373
2016-09-22Revert accidental commit.Jan Hubicka1-1/+0
From-SVN: r240369
2016-09-22* regcprop.c (copyprop_hardreg_forward_1): Remove noop moves.Jan Hubicka2-1/+27
From-SVN: r240365
2016-09-22make next_cc0_user take rtx_insn *Trevor Saunders3-4/+7
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * emit-rtl.c (next_cc0_user): Make argument type rtx_insn *. * rtl.h: Adjust prototype. From-SVN: r240362
2016-09-22make next/prev active_insn and active_insn_p take rtx_insn *Trevor Saunders9-41/+75
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * emit-rtl.c (next_active_insn): Change argument type to rtx_insn *. (prev_active_insn): Likewise. (active_insn_p): Likewise. * rtl.h: Adjust prototypes. * cfgcleanup.c (merge_blocks_move_successor_nojumps): Adjust. * config/arc/arc.md: Likewise. * config/pa/pa.c (branch_to_delay_slot_p): Likewise. (branch_needs_nop_p): Likewise. (use_skip_p): Likewise. * config/sh/sh.c (gen_block_redirect): Likewise. (split_branches): Likewise. * reorg.c (optimize_skip): Likewise. (fill_simple_delay_slots): Likewise. (fill_slots_from_thread): Likewise. (relax_delay_slots): Likewise. * resource.c (mark_target_live_regs): Likewise. From-SVN: r240361
2016-09-22make next/prev nonnote_nondebug_insn take rtx_insn *Trevor Saunders6-17/+25
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config/cris/cris.c (cris_asm_output_case_end): Change argument type to rtx_insn *. * emit-rtl.c (next_nonnote_nondebug_insn): Likewise. (prev_nonnote_nondebug_insn): Likewise. * config/cris/cris-protos.h: Adjust prototype. * rtl.h: Likewise. * jump.c (rtx_renumbered_equal_p): Adjust. From-SVN: r240360
2016-09-22make prev_real_insn take rtx_insn *Trevor Saunders5-6/+12
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * emit-rtl.c (prev_real_insn): Change argument type to rtx_insn *. * rtl.h: Adjust prototype. * config/sh/sh.md: Adjust. * dwarf2out.c (add_var_loc_to_decl): Likewise. From-SVN: r240359
2016-09-22make next/prev nondebug_insn take rtx_insn *Trevor Saunders5-10/+15
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * emit-rtl.c (next_nondebug_insn): Change argument type to rtx_insn *. (prev_nondebug_insn): Likewise. * loop-doloop.c (doloop_condition_get): Likewise. * rtl.h: Adjust prototype. * cfgloop.h: Likewise. From-SVN: r240358
2016-09-22make next/prev _nonnote_insn take rtx_insn *Trevor Saunders8-35/+54
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * emit-rtl.c (next_nonnote_insn): Change argument type to rtx_insn *. (prev_nonnote_insn): Likewise. * jump.c (reversed_comparison_code_parts): Likewise. (reversed_comparison): Likewise. * rtl.h: Adjust prototypes. * config/arc/arc.md: Adjust. * cse.c (find_comparison_args): Likewise. * reorg.c (redundant_insn): Change return type to rtx_insn *. (fix_reg_dead_note): Change argument type to rtx_insn *. (delete_prior_computation): Likewise. (delete_computation): Likewise. (fill_slots_from_thread): Adjust. (relax_delay_slots): Likewise. * simplify-rtx.c (simplify_unary_operation_1): Likewise. (simplify_relational_operation_1): Likewise. (simplify_ternary_operation): Likewise. From-SVN: r240357
2016-09-22use rtx_insn * moreTrevor Saunders19-37/+66
gcc/ChangeLog: 2016-09-22 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config/arc/arc-protos.h (arc_label_align): Change type of variables from rtx to rtx_insn *. * config/arc/arc.c (arc_label_align): Likewise. * config/arm/arm.c (any_sibcall_could_use_r3): Likewise. * config/bfin/bfin.c (workaround_speculation): Likewise. * config/c6x/c6x.c (find_next_cycle_insn): Likewise. (find_last_same_clock): Likewise. (reorg_split_calls): Likewise. * config/cris/cris-protos.h (cris_cc0_user_requires_cmp): Likewise. * config/cris/cris.c (cris_cc0_user_requires_cmp): Likewise. * config/h8300/h8300-protos.h (same_cmp_preceding_p): Likewise. (same_cmp_following_p): Likewise. * config/h8300/h8300.c (same_cmp_preceding_p): Likewise. (same_cmp_following_p): Likwise. * config/m32r/m32r.c (m32r_expand_epilogue): Likewise. * config/nds32/nds32-protos.h (nds32_target_alignment): Likewise. * config/nds32/nds32.c (nds32_target_alignment): Likewise. * config/rl78/rl78.c (rl78_alloc_physical_registers_op2): * Likewise. (rl78_alloc_physical_registers_cmp): Likewise. (rl78_alloc_physical_registers_umul): Likewise. (rl78_calculate_death_notes): Likewise. * config/s390/s390-protos.h (s390_label_align): Likewise. * config/s390/s390.c (s390_label_align): Likewise. * config/sh/sh.c (barrier_align): Likewise. * config/sparc/sparc-protos.h (emit_cbcond_nop): Likewise. * config/sparc/sparc.c (sparc_asm_function_epilogue): Likewise. (emit_cbcond_nop): Likewise. From-SVN: r240356
2016-09-22pr77550.C: Use __SIZE_TYPE__.Bernd Edlinger2-2/+6
2016-09-22 Bernd Edlinger <bernd.edlinger@hotmail.de> * g++.dg/pr77550.C: Use __SIZE_TYPE__. From-SVN: r240355
2016-09-22re PR ipa/77653 (wrong code at -Os and above on x86_64-linux-gnu (in both ↵Martin Liska4-5/+37
32-bit and 64-bit modes)) Fix PR ipa/77653 PR ipa/77653 * gcc.dg/ipa/pr77653.c: New test. PR ipa/77653 * ipa-icf.c (sem_variable::merge): Yield merge operation if alias address matters, not necessarily address of original. From-SVN: r240354
2016-09-22re PR tree-optimization/77697 (suspicious code in tree-ssa-forwprop.c)Richard Biener2-3/+10
2016-09-22 Richard Biener <rguenther@suse.de> PR middle-end/77697 * gimple-fold.c (fold_array_ctor_reference): Turn asserts into fold fails. From-SVN: r240353
2016-09-22re PR tree-optimization/77677 (ICE at -O1 and above in both 32-bit and ↵Richard Biener2-0/+14
64-bit modes on x86_64-linux-gnu (internal compiler error: in set_value_range, at tree-vrp.c:361)) 2016-09-22 Richard Biener <rguenther@suse.de> PR middle-end/77677 * gimple-match-head.c (gimple_resimplify1): Drop TREE_OVERFLOW from constant folding results. (gimple_resimplify2): Likewise. (gimple_resimplify3): Likewise. From-SVN: r240352
2016-09-22re PR fortran/77678 (ICE in fold_read_from_constant_string, at ↵Richard Biener2-1/+8
fold-const.c:13706) 2016-09-22 Richard Biener <rguenther@suse.de> PR middle-end/77678 * expr.c (expand_expr_real_1): Guard array access against negative offset. From-SVN: r240351
2016-09-22Use GMP_RNDN for portability to MPFR 2.4.2Rainer Orth2-2/+8
* gimple-ssa-sprintf.c (format_floating_max): Use GMP_RNDN instead of MPFR_RNDN. (format_floating): Likewise. From-SVN: r240350
2016-09-22re PR fortran/48298 ([F03] User-Defined Derived-Type IO (DTIO))Paul Thomas2-4/+7
2016-09-22 Paul Thomas <pault@gcc.gnu.org> PR fortran/48298 * gfortran.h : Place the pseudo operators INTRINSIC_FORMATTED and INTRINSIC_UNFORMATTED after the sentinel in enum gfc_intrinsic_op so that they do not appear as place holders in module_write. * interface.c (dtio_op): Comment on the special nature of the pseudo operators INTRINSIC FORMATTED and INTRINSIC_UNFORMATTED. From-SVN: r240349
2016-09-22re PR tree-optimization/77665 (ICE in expand_GOMP_SIMD_VF, at internal-fn.c:172)Jakub Jelinek4-5/+43
PR fortran/77665 * tree-inline.c (remap_gimple_stmt): Set has_simduid_loops for all IFN_GOMP_SIMD_* internal fns, not just for IFN_GOMP_SIMD_ORDERED_*. * gfortran.dg/gomp/pr77665.f90: New test. From-SVN: r240348
2016-09-22class.c (push_super_field): Set DECL_CONTEXT.Richard Biener2-0/+6
2016-09-22 Richard Biener <rguenther@suse.de> java/ * class.c (push_super_field): Set DECL_CONTEXT. From-SVN: r240346
2016-09-22interface.c (check_dtio_interface1): Introduce errors for alternate returns ↵Paul Thomas5-4/+209
and incorrect numbers of arguments. 2016-09-22 Paul Thomas <pault@gcc.gnu.org> * interface.c (check_dtio_interface1): Introduce errors for alternate returns and incorrect numbers of arguments. (gfc_find_specific_dtio_proc): Return cleanly if the derived type either doesn't exist or has no namespace. 2016-09-22 Paul Thomas <pault@gcc.gnu.org> * gfortran.dg/dtio_11.f90: Correct for changed error messages. * gfortran.dg/dtio_13.f90: New test. From-SVN: r240342
2016-09-22re PR fortran/66107 (ICE on missing parameter value for initialisation ↵Louis Krupp4-1/+29
(segfault)) 2016-09-21 Louis Krupp <louis.krupp@zoho.com> PR fortran/66107 * gfortran.dg/pr66107.f90: New test. 2016-09-21 Louis Krupp <louis.krupp@zoho.com> PR fortran/66107 * decl.c (add_init_expr_to_sym): Catch variable character length in parameter array. From-SVN: r240341
2016-09-22Daily bump.GCC Administrator1-1/+1
From-SVN: r240339
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