aboutsummaryrefslogtreecommitdiff
path: root/gcc
AgeCommit message (Collapse)AuthorFilesLines
2024-07-23RISC-V: Implement the .SAT_TRUNC for scalarPan Li13-0/+259
This patch would like to implement the simple .SAT_TRUNC pattern in the riscv backend. Aka: Form 1: #define DEF_SAT_U_TRUC_FMT_1(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \ { \ bool overflow = x > (WT)(NT)(-1); \ return ((NT)x) | (NT)-overflow; \ } DEF_SAT_U_TRUC_FMT_1(uint32_t, uint64_t) Before this patch: __attribute__((noinline)) uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x) { _Bool overflow; unsigned char _1; unsigned char _2; unsigned char _3; uint8_t _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY overflow_5 = x_4(D) > 255; _1 = (unsigned char) x_4(D); _2 = (unsigned char) overflow_5; _3 = -_2; _6 = _1 | _3; return _6; ;; succ: EXIT } After this patch: __attribute__((noinline)) uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x) { uint8_t _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY _6 = .SAT_TRUNC (x_4(D)); [tail call] return _6; ;; succ: EXIT } The below tests suites are passed for this patch 1. The rv64gcv fully regression test. 2. The rv64gcv build with glibc gcc/ChangeLog: * config/riscv/iterators.md (ANYI_DOUBLE_TRUNC): Add new iterator for int double truncation. (ANYI_DOUBLE_TRUNCATED): Add new attr for int double truncation. (anyi_double_truncated): Ditto but for lowercase. * config/riscv/riscv-protos.h (riscv_expand_ustrunc): Add new func decl for expanding ustrunc * config/riscv/riscv.cc (riscv_expand_ustrunc): Add new func impl to expand ustrunc. * config/riscv/riscv.md (ustrunc<mode><anyi_double_truncated>2): Impl the new pattern ustrunc<m><n>2 for int. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macro. * gcc.target/riscv/sat_arith_data.h: New test. * gcc.target/riscv/sat_u_trunc-1.c: New test. * gcc.target/riscv/sat_u_trunc-2.c: New test. * gcc.target/riscv/sat_u_trunc-3.c: New test. * gcc.target/riscv/sat_u_trunc-run-1.c: New test. * gcc.target/riscv/sat_u_trunc-run-2.c: New test. * gcc.target/riscv/sat_u_trunc-run-3.c: New test. * gcc.target/riscv/scalar_sat_unary.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-23Daily bump.GCC Administrator5-1/+399
2024-07-22Fix handling of ICF_NOVOPS in ipa-modrefJan Hubicka1-15/+21
As shown in somewhat convoluted testcase, ipa-modref is mistreating ECF_NOVOPS as "having no side effects". This come from time when modref cared only about memory accesses and thus it was possible to shortcut on it. This patch removes (hopefully) all those bad shortcuts. Bootstrapped/regtested x86_64-linux, comitted. gcc/ChangeLog: PR ipa/109985 * ipa-modref.cc (modref_summary::useful_p): Fix handling of ECF_NOVOPS. (modref_access_analysis::process_fnspec): Likevise. (modref_access_analysis::analyze_call): Likevise. (propagate_unknown_call): Likevise. (modref_propagate_in_scc): Likevise. (modref_propagate_flags_in_scc): Likewise. (ipa_merge_modref_summary_after_inlining): Likewise.
2024-07-22c++: Some cp-tree.def comment fixesJakub Jelinek1-12/+11
While reading the fold expression and concept tree comments, I found various spots referring to non-existent macros etc. The following patch attempts to sync that with what is actually implemented. 2024-07-22 Jakub Jelinek <jakub@redhat.com> * cp-tree.def (UNARY_LEFT_FOLD_EXPR): Use FOLD_EXPR_MODIFY_P instead of FOLD_EXPR_MOD_P or FOLDEXPR_MOD_P in the comment. Comment formatting fixes. (ATOMIC_CONSTEXPR): Use CONSTR_INFO instead of ATOMIC_CONSTR_INFO and ATOMIC_CONSTR_MAP instead of ATOMIC_CONSTR_PARMS in the comment. Comment formatting fixes. (CONJ_CONSTR): Remove comment about third operand. Use CONSTR_INFO instead of CONJ_CONSTR_INFO and DISJ_CONSTR_INFO. (CHECK_CONSTR): Use CHECK_CONSTR_ARGS instead of CHECK_CONSTR_ARGUMENTS.
2024-07-22Fix modref's iteraction with store mergingJan Hubicka2-0/+32
Hi, this patch fixes wrong code in case store-merging introduces load of function parameter that was previously write-only (which happens for bitfields). Without this, the whole store-merged area is consdered to be killed. PR ipa/111613 gcc/ChangeLog: * ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ and EAF_NO_INDIRECT_READ from past flags. gcc/testsuite/ChangeLog: * gcc.c-torture/pr111613.c: New test.
2024-07-22Add -mcpu=power11 support.Michael Meissner21-90/+171
This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. This patch allows GCC to be configured with the --with-cpu=power11 and --with-tune=power11 options. This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. 2024-07-22 Michael Meissner <meissner@linux.ibm.com> gcc/ * config.gcc (powerpc*-*-*): Add support for power11. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11. (power11 cpu): Add power11 definition. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. * config/rs6000/power10.md (all reservations): Add power11 support. gcc/testsuite/ * gcc.target/powerpc/power11-1.c: New test. * gcc.target/powerpc/power11-2.c: Likewise. * gcc.target/powerpc/power11-3.c: Likewise.
2024-07-22[4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destinationJeff Law1-3/+10
If we encounter something during SET handling that we can not handle, the safe thing to do is to ignore the destination and continue the loop. We've actually been trying to do slightly better with SUBREG destinations by iterating into SUBREG_REG. It turns out that wasn't working as expected. The problem is once we "continue" we lose the state that we were inside the SET and thus we ended up ignoring the destination completely rather than tracking the SUBREG_REG object. This could be fixed by restarting SET processing, but I just don't see this as all that important to handle. So rather than leave the code as-is, not working per design, I'm twiddling it to use the common 'skip subrtxs and continue' idiom used elsewhere. This is a prerequisite for another patch in this series. Specifically I have a patch that explicitly tracks if we skipped a destination rather than trying to imply it from the state of LIVE_TMP. So this is probably NFC right now, but that's a short-lived NFC. Bootstrapped and regression tested on x86 and also run as part of a larger kit on the crosses in my tester. PR rtl-optimization/115877 gcc/ * ext-dce.cc (ext_dce_process_sets): More correctly handle SUBREG destinations.
2024-07-22Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced to ↵Jan Hubicka2-2/+39
function call parameters modref_eaf_analysis::analyze_ssa_name misinterprets EAF flags. If dereferenced parameter is passed (to map_iterator in the testcase) it can be returned indirectly which in turn makes it to escape into the next function call. PR ipa/115033 gcc/ChangeLog: * ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix checking of EAF flags when analysing values dereferenced as function parameters. gcc/testsuite/ChangeLog: * gcc.c-torture/execute/pr115033.c: New test.
2024-07-22Fix accounting of offsets in unadjusted_ptr_and_unit_offsetJan Hubicka2-2/+25
unadjusted_ptr_and_unit_offset accidentally throws away the offset computed by get_addr_base_and_unit_offset. Instead of passing extra_offset it passes offset. PR ipa/114207 gcc/ChangeLog: * ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of offsets in ADDR_EXPR. gcc/testsuite/ChangeLog: * gcc.c-torture/execute/pr114207.c: New test.
2024-07-22Compare loop bounds in ipa-icfJan Hubicka2-0/+32
Hi, this testcase shows another poblem with missing comparators for metadata in ICF. With value ranges available to loop optimizations during early opts we can estimate number of iterations based on guarding condition that can be split away by the fnsplit pass. This patch disables ICF when number of iteraitons does not match. Bootstrapped/regtesed x86_64-linux, will commit it shortly gcc/ChangeLog: PR ipa/115277 * ipa-icf-gimple.cc (func_checker::compare_loops): compare loop bounds. gcc/testsuite/ChangeLog: * gcc.c-torture/compile/pr115277.c: New test.
2024-07-22rtl-ssa: Avoid using a stale splay tree root [PR116009]Richard Sandiford2-1/+25
In the fix for PR115928, I'd failed to notice that "root" was used later in the function, so needed to be updated. gcc/ PR rtl-optimization/116009 * rtl-ssa/accesses.cc (function_info::add_def): Set the root local variable after removing the old clobber group. gcc/testsuite/ PR rtl-optimization/116009 * gcc.c-torture/compile/pr116009.c: New test.
2024-07-22rtl-ssa: Add debug routines for def_splay_treeRichard Sandiford2-0/+18
This patch adds debug routines for def_splay_tree, which I found useful while debugging PR116009. gcc/ * rtl-ssa/accesses.h (rtl_ssa::pp_def_splay_tree): Declare. (dump, debug): Add overloads for def_splay_tree. * rtl-ssa/accesses.cc (rtl_ssa::pp_def_splay_tree): New function. (dump, debug): Add overloads for def_splay_tree.
2024-07-22aarch64: Tighten aarch64_simd_mem_operand_p [PR115969]Richard Sandiford2-2/+11
aarch64_simd_mem_operand_p checked for a memory with a POST_INC or REG address, but it didn't check what kind of register was being used. This meant that it allowed DImode FPRs as well as GPRs. I wondered about rewriting it to use aarch64_classify_address, but this one-line fix seemed simpler. The structure then mirrors the existing early exit in aarch64_classify_address itself: /* On LE, for AdvSIMD, don't support anything other than POST_INC or REG addressing. */ if (advsimd_struct_p && TARGET_SIMD && !BYTES_BIG_ENDIAN && (code != POST_INC && code != REG)) return false; gcc/ PR target/115969 * config/aarch64/aarch64.cc (aarch64_simd_mem_operand_p): Require the operand to be a legitimate memory_operand. gcc/testsuite/ PR target/115969 * gcc.target/aarch64/pr115969.c: New test.
2024-07-22[NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as ↵Jeff Law1-7/+57
live in ext-dce Another patch to refine liveness computations. This should be NFC and is designed to help debugging. In simplest terms the patch avoids setting bit groups outside the size of a pseudo as live. Consider a HImode pseudo, bits 16..63 for such a pseudo don't really have meaning, yet we often set bit groups related to bits 16.63 on in the liveness bitmaps. This makes debugging harder than it needs to be by simply having larger bitmaps to verify when walking through the code in a debugger. This has been bootstrapped and regression tested on x86_64. It's also been tested on the crosses in my tester without regressions. Pushing to the trunk, PR rtl-optimization/115877 gcc/ * ext-dce.cc (group_limit): New function. (mark_reg_live): Likewise. (ext_dce_process_sets): Use new functions. (ext_dce_process_uses): Likewise. (ext_dce_init): Likewise.
2024-07-22Fix hash of WIDEN_*_EXPRRichard Biener1-1/+1
We're hashing operand 2 to the temporary hash. * fold-const.cc (operand_compare::hash_operand): Fix hash of WIDEN_*_EXPR.
2024-07-22constify inchashRichard Biener1-3/+3
The following constifies parts of inchash. * inchash.h (inchash::end): Make const. (inchash::merge): Take const reference hash argument. (inchash::add_commutative): Likewise.
2024-07-22Fix Rejects allocatable coarray passed as a dummy argument [88624]Andre Vehreschild3-10/+48
Coarray parameters of procedures/functions need to be dereffed, because they are references to the descriptor but the routine expected the descriptor directly. PR fortran/88624 gcc/fortran/ChangeLog: * trans-expr.cc (gfc_conv_procedure_call): Treat pointers/references (e.g. from parameters) correctly by derefing them. gcc/testsuite/ChangeLog: * gfortran.dg/coarray/dummy_1.f90: Add calling function trough function. * gfortran.dg/pr88624.f90: New test.
2024-07-22AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE ↵Tamar Christina5-0/+112
[PR115531]. This implements the new target hook indicating that for AArch64 when possible we prefer masked operations for any type vs doing LOAD + SELECT or SELECT + STORE. Thanks, Tamar gcc/ChangeLog: PR tree-optimization/115531 * config/aarch64/aarch64.cc (aarch64_conditional_operation_is_expensive): New. (TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE): New. gcc/testsuite/ChangeLog: PR tree-optimization/115531 * gcc.dg/vect/vect-conditional_store_1.c: New test. * gcc.dg/vect/vect-conditional_store_2.c: New test. * gcc.dg/vect/vect-conditional_store_3.c: New test. * gcc.dg/vect/vect-conditional_store_4.c: New test.
2024-07-22middle-end: Implement conditonal store vectorizer pattern [PR115531]Tamar Christina6-0/+189
This adds a conditional store optimization for the vectorizer as a pattern. The vectorizer already supports modifying memory accesses because of the pattern based gather/scatter recognition. Doing it in the vectorizer allows us to still keep the ability to vectorize such loops for architectures that don't have MASK_STORE support, whereas doing this in ifcvt makes us commit to MASK_STORE. Concretely for this loop: void foo1 (char *restrict a, int *restrict b, int *restrict c, int n, int stride) { if (stride <= 1) return; for (int i = 0; i < n; i++) { int res = c[i]; int t = b[i+stride]; if (a[i] != 0) res = t; c[i] = res; } } today we generate: .L3: ld1b z29.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x2, x5, lsl 2] ld1w z30.s, p7/z, [x1, x5, lsl 2] cmpne p15.b, p6/z, z29.b, #0 sel z30.s, p15, z30.s, z31.s st1w z30.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 which in gimple is: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect_t_20.12_74 = .MASK_LOAD (vectp.10_72, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; vect_res_11.17_80 = VEC_COND_EXPR <mask__34.16_79, vect_t_20.12_74, vect_res_18.9_68>; .MASK_STORE (vectp_c.18_81, 32B, loop_mask_67, vect_res_11.17_80); A MASK_STORE is already conditional, so there's no need to perform the load of the old values and the VEC_COND_EXPR. This patch makes it so we generate: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; .MASK_STORE (vectp_c.18_81, 32B, mask__34.16_79, vect_res_18.9_68); which generates: .L3: ld1b z30.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x1, x5, lsl 2] cmpne p7.b, p7/z, z30.b, #0 st1w z31.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 gcc/ChangeLog: PR tree-optimization/115531 * tree-vect-patterns.cc (vect_cond_store_pattern_same_ref): New. (vect_recog_cond_store_pattern): New. (vect_vect_recog_func_ptrs): Use it. * target.def (conditional_operation_is_expensive): New. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Document it. * targhooks.cc (default_conditional_operation_is_expensive): New. * targhooks.h (default_conditional_operation_is_expensive): New.
2024-07-21testsuite: powerpc: fix dg-do run typoSam James1-1/+1
'dg-run' is not a valid dejagnu directive, 'dg-do run' is needed here for the test to be executed. PR target/108699 gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr108699.c: Fix 'dg-run' typo. Signed-off-by: Sam James <sam@gentoo.org>
2024-07-22RISC-V: Rearrange the test helper files for vector .SAT_*Pan Li184-262/+262
Rearrange the test help header files, as well as align the name conventions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvv_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust the include file names. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Move to... * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: ...here. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-22Daily bump.GCC Administrator5-1/+45
2024-07-21Fortran: Fix regression caused by r14-10477 [PR59104]Paul Thomas4-1/+36
2024-07-21 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/59104 * gfortran.h : Add decl_order to gfc_symbol. * symbol.cc : Add static next_decl_order.. (gfc_set_sym_referenced): Set symbol decl_order. * trans-decl.cc : Include dependency.h. (decl_order): Replace symbol declared_at.lb->location with decl_order. gcc/testsuite/ PR fortran/59104 * gfortran.dg/dependent_decls_3.f90: New test.
2024-07-21[PR rtl-optimization/115877][2/n] Improve liveness computation for constant ↵Jeff Law1-0/+1
initialization While debugging pr115877, I noticed we were failing to remove the destination register from LIVENOW bitmap when it was set to a constant value. ie (set (dest) (const_int)). This was a trivial oversight in safe_for_live_propagation. I don't have an example of this affecting code generation, but it certainly could. More importantly, by making LIVENOW more accurate it's easier to debug when LIVENOW differs from expectations. As with the prior patch this has been tested as part of a larger patchset with the crosses as well as individually on x86_64. Pushing to the trunk, PR rtl-optimization/115877 gcc/ * ext-dce.cc (safe_for_live_propagation): Handle RTX_CONST_OBJ.
2024-07-21[PR rtl-optimization/115877] Fix livein computation for ext-dceJeff Law1-0/+2
So I'm not yet sure how I'm going to break everything down, but this is easy enough to break out as 1/N of ext-dce fixes/improvements. When handling uses in an insn, we first determine what bits are set in the destination which is represented in DST_MASK. Then we use that to refine what bits are live in the source operands. In the source operand handling section we *modify* DST_MASK if the source operand is a SUBREG (ugh!). So if the first operand is a SUBREG, then we can incorrectly compute which bit groups are live in the second operand, especially if it is a SUBREG as well. This was seen when testing a larger set of patches on the rl78 port (builtin-arith-overflow-p-7 & pr71631 execution failures), so no new test for this bugfix. Run through my tester (in conjunction with other ext-dce changes) on the various cross targets. Run individually through a bootstrap and regression test cycle on x86_64 as well. Pushing to the trunk. PR rtl-optimization/115877 gcc/ * ext-dce.cc (ext_dce_process_uses): Restore the value of DST_MASK for reach operand.
2024-07-21gcc: stop adding -fno-common for checking buildsSam James4-16/+5
Originally added in r0-44646-g204250d2fcd084 and r0-44627-gfd350d241fecf6 whic moved -fno-common from all builds to just checking builds. Since r10-4867-g6271dd984d7f92, GCC defaults to -fno-common. There's no need to pass it specially for checking builds. We could keep it for older bootstrap compilers with checking but I don't see much value in that, it was already just a bonus before. gcc/ChangeLog: * Makefile.in (NOCOMMON_FLAG): Delete. (GCC_WARN_CFLAGS): Drop NOCOMMON_FLAG. (GCC_WARN_CXXFLAGS): Drop NOCOMMON_FLAG. * configure.ac: Ditto. * configure: Regenerate. gcc/d/ChangeLog: * Make-lang.in (WARN_DFLAGS): Drop NOCOMMON_FLAG.
2024-07-21SH: Fix outage caused by recently added 2nd combine pass after reg allocOleg Endo1-1/+9
I've also confirmed on the CSiBE set that the secondary combine pass is actually beneficial on SH. It does result in some code size reductions. gcc/CHangeLog: * config/sh/sh.md (mov_neg_si_t): Allow insn and split after register allocation. (*treg_noop_move): New insn.
2024-07-21Daily bump.GCC Administrator6-1/+179
2024-07-20Require bitint575 for pr116003.cAndrew MacLeod1-1/+1
Require a bitint target large enough. gcc/testsuite/ * gcc.dg/pr116003.c: Require bitint575 target.
2024-07-20Revert "Add documentation for musttail attribute"Andi Kleen1-23/+2
This reverts commit 56f824cc206ff00d466aaeb11211d8005c4668bc.
2024-07-20Revert "Add tests for C/C++ musttail attributes"Andi Kleen14-324/+0
This reverts commit 37c4703ce84722b9c24db3e8e6d57ab6d3a7b5eb.
2024-07-20Revert "C: Implement musttail attribute for returns"Andi Kleen3-64/+16
This reverts commit 7db47f7b915c5f5d645fa536547e26b92290afe3.
2024-07-20Revert "C++: Support clang compatible [[musttail]] (PR83324)"Andi Kleen6-63/+4
This reverts commit 59dd1d7ab21ad9a7ebf641ec9aeea609c003ad2f.
2024-07-20Output CodeView function informationMark Harmstone1-3/+288
Translate DW_TAG_subprogram DIEs into CodeView LF_FUNC_ID types and S_GPROC32_ID / S_LPROC32_ID symbols. ld will then transform these into S_GPROC32 / S_LPROC32 symbols, which map addresses to unmangled function names. gcc/ * dwarf2codeview.cc (enum cv_sym_type): Add new values. (struct codeview_symbol): Add function to union. (struct codeview_custom_type): Add lf_func_id to union. (write_function): New function. (write_codeview_symbols): Call write_function. (write_lf_func_id): New function. (write_custom_types): Call write_lf_func_id. (add_function): New function. (codeview_debug_early_finish): Call add_function.
2024-07-20Add bitint to options for testcaseAndrew MacLeod1-1/+1
Testcase should only be for bitint targets gcc/testsuite/ * gcc.dg/pr116003.c : Add target bitint.
2024-07-20doc: Remove documentation of two obsolete spec stringsAndré Maroneze1-3/+0
gcc: * doc/invoke.texi (Spec Files): Remove documentation of obsolete spec strings "predefines" and "signed_char".
2024-07-20Avoid undefined behaviour in build_option_suggestionsSiddhesh Poyarekar1-1/+1
The inner loop in build_option_suggestions uses OPTION to take the address of OPTB and use it across iterations, which is undefined behaviour since OPTB is defined within the loop. Pull it outside the loop to make this defined. gcc/ChangeLog: * opt-suggestions.cc (option_proposer::build_option_suggestions): Pull OPTB definition out of the innermost loop.
2024-07-19Add documentation for musttail attributeAndi Kleen1-2/+23
gcc/ChangeLog: PR c/83324 * doc/extend.texi: Document [[musttail]]
2024-07-19Add tests for C/C++ musttail attributesAndi Kleen14-0/+324
Some adopted from the existing C musttail plugin tests. Also extends the ability to query the sibcall capabilities of the target. gcc/testsuite/ChangeLog: * lib/target-supports.exp: (check_effective_target_struct_tail_call): New function. * c-c++-common/musttail1.c: New test. * c-c++-common/musttail12.c: New test. * c-c++-common/musttail13.c: New test. * c-c++-common/musttail2.c: New test. * c-c++-common/musttail3.c: New test. * c-c++-common/musttail4.c: New test. * c-c++-common/musttail5.c: New test. * c-c++-common/musttail7.c: New test. * c-c++-common/musttail8.c: New test. * g++.dg/musttail10.C: New test. * g++.dg/musttail11.C: New test. * g++.dg/musttail6.C: New test. * g++.dg/musttail9.C: New test.
2024-07-19C: Implement musttail attribute for returnsAndi Kleen3-16/+64
Implement a C23 clang compatible musttail attribute similar to the earlier C++ implementation in the C parser. gcc/c/ChangeLog: PR c/83324 * c-parser.cc (struct attr_state): Define with musttail_p. (c_parser_statement_after_labels): Handle [[musttail]]. (c_parser_std_attribute): Dito. (c_parser_handle_musttail): Dito. (c_parser_compound_statement_nostart): Dito. (c_parser_all_labels): Dito. (c_parser_statement): Dito. * c-tree.h (c_finish_return): Add musttail_p flag. * c-typeck.cc (c_finish_return): Handle musttail_p flag.
2024-07-19C++: Support clang compatible [[musttail]] (PR83324)Andi Kleen6-4/+63
This patch implements a clang compatible [[musttail]] attribute for returns. musttail is useful as an alternative to computed goto for interpreters. With computed goto the interpreter function usually ends up very big which causes problems with register allocation and other per function optimizations not scaling. With musttail the interpreter can be instead written as a sequence of smaller functions that call each other. To avoid unbounded stack growth this requires forcing a sibling call, which this attribute does. It guarantees an error if the call cannot be tail called which allows the programmer to fix it instead of risking a stack overflow. Unlike computed goto it is also type-safe. It turns out that David Malcolm had already implemented middle/backend support for a musttail attribute back in 2016, but it wasn't exposed to any frontend other than a special plugin. This patch adds a [[gnu::musttail]] attribute for C++ that can be added to return statements. The return statement must be a direct call (it does not follow dependencies), which is similar to what clang implements. It then uses the existing must tail infrastructure. For compatibility it also detects clang::musttail Passes bootstrap and full test gcc/c-family/ChangeLog: * c-attribs.cc (set_musttail_on_return): New function. * c-common.h (set_musttail_on_return): Declare new function. gcc/cp/ChangeLog: PR c/83324 * cp-tree.h (AGGR_INIT_EXPR_MUST_TAIL): Add. * parser.cc (cp_parser_statement): Handle musttail. (cp_parser_jump_statement): Dito. * pt.cc (tsubst_expr): Copy CALL_EXPR_MUST_TAIL_CALL. * semantics.cc (simplify_aggr_init_expr): Handle musttail.
2024-07-19Add a musttail generic attribute to the c-attribs tableAndi Kleen2-0/+16
The actual handling is directly in the parser since the generic mechanism doesn't support statement attributes, but this gives basic error checking/detection on the attribute. gcc/c-family/ChangeLog: PR c/83324 * c-attribs.cc (handle_musttail_attribute): Add. * c-common.h (handle_musttail_attribute): Add.
2024-07-20LoongArch: Organize the code related to split move and merge the same functions.Lulu Cheng3-169/+58
gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_split_128bit_move): Delete. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move): Delete. (loongarch_split_256bit_move_p): Delete. (loongarch_split_vector_move): Add a function declaration. * config/loongarch/loongarch.cc (loongarch_vector_costs::finish_cost): Adjust the code formatting. (loongarch_split_vector_move_p): Merge loongarch_split_128bit_move_p and loongarch_split_256bit_move_p. (loongarch_split_move_p): Merge code. (loongarch_split_move): Likewise. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move_p): Delete. (loongarch_split_128bit_move): Delete. (loongarch_split_vector_move): Merge loongarch_split_128bit_move and loongarch_split_256bit_move. (loongarch_split_256bit_move): Delete. (loongarch_global_init): Remove the extra semicolon at the end of the function. * config/loongarch/loongarch.md (*movdf_softfloat): Added a new condition TARGET_64BIT.
2024-07-20Daily bump.GCC Administrator5-1/+138
2024-07-19Check for SSA_NAME not in the IL yet.Andrew MacLeod2-1/+26
Check for an SSA_NAME not in the CFG before trying to create an equivalence record in the defintion block. PR tree-optimization/116003 gcc/ * value-relation.cc (equiv_oracle::register_initial_def): Check if SSA_NAME is in the IL before registering. gcc/testsuite/ * gcc.dg/pr116003.c: New.
2024-07-19Rewrite usage comment at the top of 'gcc/passes.def'Thomas Schwinge1-8/+5
Since Subversion r201359 (Git commit a167b052dfe9a8509bb23c374ffaeee953df0917) "Introduce gen-pass-instances.awk and pass-instances.def", the usage comment at the top of 'gcc/passes.def' no longer is accurate (even if that latter file does continue to use the 'NEXT_PASS' form without 'NUM') -- and, worse, the 'NEXT_PASS' etc. in that usage comment are processed by the 'gcc/gen-pass-instances.awk' script: --- source-gcc/gcc/passes.def 2024-06-24 18:55:15.132561641 +0200 +++ build-gcc/gcc/pass-instances.def 2024-06-24 18:55:27.768562714 +0200 [...] @@ -20,546 +22,578 @@ /* Macros that should be defined when using this file: INSERT_PASSES_AFTER (PASS) PUSH_INSERT_PASSES_WITHIN (PASS) POP_INSERT_PASSES () - NEXT_PASS (PASS) + NEXT_PASS (PASS, 1) TERMINATE_PASS_LIST (PASS) */ [...] (That is, this is 'NEXT_PASS' for the first instance of pass 'PASS'.) That's benign so far, but with another thing that I'll be extending, I'd then run into an error while the script handles this comment block. ;-\ gcc/ * passes.def: Rewrite usage comment at the top.
2024-07-19Treat boolean vector elements as 0/-1 [PR115406]Richard Sandiford3-3/+23
Previously we built vector boolean constants using 1 for true elements and 0 for false elements. This matches the predicates produced by SVE's PTRUE instruction, but leads to a miscompilation on AVX, where all bits of a boolean element should be set. One option for RTL would be to make this target-configurable. But that isn't really possible at the tree level, where vectors should work in a more target-independent way. (There is currently no way to create a "generic" packed boolean vector, but never say never :)) And, if we were going to pick a generic behaviour, it would make sense to use 0/-1 rather than 0/1, for consistency with integer vectors. Both behaviours should work with SVE on read, since SVE ignores the upper bits in each predicate element. And the choice shouldn't make much difference for RTL, since all SVE predicate modes are expressed as vectors of BI, rather than of multi-bit booleans. I suspect there might be some fallout from this change on SVE. But I think we should at least give it a go, and see whether any fallout provides a strong counterargument against the approach. gcc/ PR middle-end/115406 * fold-const.cc (native_encode_vector_part): For vector booleans, check whether an element is nonzero and, if so, set all of the correspending bits in the target image. * simplify-rtx.cc (native_encode_rtx): Likewise. gcc/testsuite/ PR middle-end/115406 * gcc.dg/torture/pr115406.c: New test.
2024-07-19arm: Update fp16-aapcs-[24].c after insn_propagation patchRichard Sandiford2-6/+10
These tests used to generate: bl swap ldr r2, [sp, #4] mov r0, r2 @ __fp16 but g:9d20529d94b23275885f380d155fe8671ab5353a means that we can load directly into r0: bl swap ldrh r0, [sp, #4] @ __fp16 This patch updates the tests to "defend" this change. While there, the scans include: mov\tr1, r[03]} But if the spill of r2 occurs first, there's no real reason why r2 couldn't be used as the temporary, instead r3. The patch tries to update the scans while preserving the spirit of the originals. gcc/testsuite/ * gcc.target/arm/fp16-aapcs-2.c: Expect the return value to be loaded directly from the stack. Test that the swap generates two moves out of r0/r1 and two moves in. * gcc.target/arm/fp16-aapcs-4.c: Likewise.
2024-07-19c++: xobj fn call without obj [PR115783]Patrick Palka2-1/+49
The code path for rejecting an object-less call to a non-static member function should also consider xobj member functions (so that we correctly reject the below calls with a "cannot call member function without object" diagnostic). PR c++/115783 gcc/cp/ChangeLog: * call.cc (build_new_method_call): Generalize METHOD_TYPE check to DECL_OBJECT_MEMBER_FUNCTION_P. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-diagnostics11.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2024-07-19AVR: Support new built-in function __builtin_avr_mask1.Georg-Johann Lay5-0/+336
gcc/ * config/avr/builtins.def (MASK1): New DEF_BUILTIN. * config/avr/avr.cc (avr_rtx_costs_1): Handle rtx costs for expressions like __builtin_avr_mask1. (avr_init_builtins) <uintQI_ftype_uintQI_uintQI>: New tree type. (avr_expand_builtin) [AVR_BUILTIN_MASK1]: Diagnose unexpected forms. (avr_fold_builtin) [AVR_BUILTIN_MASK1]: Handle case. * config/avr/avr.md (gen_mask1): New expand helper. (mask1_0x01_split, mask1_0x80_split, mask1_0xfe_split): New insn-and-split. (*mask1_0x01, *mask1_0x80, *mask1_0xfe): New insns. * doc/extend.texi (AVR Built-in Functions) <__builtin_avr_mask1>: Document new built-in function. gcc/testsuite/ * gcc.target/avr/torture/builtin-mask1.c: New test.
generated by cgit v1.1 at 2025-09-20 19:54:08 +0000