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The messages modified in this patch do not have a clear intended
parent. This causes a lot of issues when grouping continuation
messages together with their parent. This can be confusing as it
is not obvious what was the parent message that caused this
problem or in worst case scenarios the message not being printed
alltogether.
These modified messages do not seem to be related to any concrete
error message and thus should be treated as independent messages.
gcc/ada/
* sem_ch12.adb (Abandon_Instantiation): Remove continuation
characters from the error message.
* sem_ch13.adb (Check_False_Aspect_For_Derived_Type): Remove
continuation characters from the error message.
* sem_ch6.adb (Assert_False): Avoid creating a continuation
message without a parent. If no primary message is created then
the message is considered as primary.
gcc/testsuite/ChangeLog:
* gnat.dg/interface6.adb: Adjust test.
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Currently unless pretty printing is enabled we avoid parsing
the message strings for continuation messages. This leads
to inconsistent state for the Error_Msg_Object-s that are
being created.
gcc/ada/
* erroutc.adb (Prescan_Message): Avoid not parsing all of the
message attributes.
* erroutc.ads: Update the documentation.
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Avoid cases where the main message is an error and the
continuation is a warning.
gcc/ada/
* freeze.adb: Remove warning insertion characters from a
continuation message.
* sem_util.adb: Remove warning insertion characters from a
continuation message.
* sem_warn.adb: Use same warning character as the main message.
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Separate the line fitting algorithm from the general line
printing algorithm.
gcc/ada/
* erroutc.ads: Add new method Output_Text_Within
* erroutc.adb: Move the line fitting code to a new method called
Output_Text_Within
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To check validity of data values, we must strip privacy from their
types.
gcc/ada/
* checks.adb (Expr_Known_Valid): Use Validated_View, which strips
type derivation and privacy.
* exp_ch3.adb (Simple_Init_Private_Type): Kill checks inside
unchecked conversions, just like in Simple_Init_Scalar_Type.
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gcc/ada/
* styleg.adb (Check_Line_Max_Length): Add the actual line length
to the diagnostic message.
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The compiler was flagging type-mismatch errors on iterated component
associations in array aggregates of form "for C in <iterator_name>",
improperly requiring the type of the iterator to be the array index
type. The parser can't distinguish whether the association is one
involving an actual discrete choice vs. an iterator specification,
and creates an N_Iterated_Component_Association with a Defining_Identifer
and Discrete_Choices, and the analysis phase has to disambiguate this,
determining whether to create an N_Iterator_Specification node for
the association. A related change is to revise the similar code for
iterated associations of container aggregates, to allow forms of
iterator objects other than just function calls.
gcc/ada/
* sem_aggr.adb (Resolve_Array_Aggregate): Add loop over associations to locate
N_Iterated_Component_Associations that do not have an Iterator_Specification,
and if their Discrete_Choices list consists of a single choice, analyze it and
if it's the name of an iterator object, then create an Iterator_Specification
and associate it with the iterated component association.
(Resolve_Iterated_Association): Replace test for function call with test of
Is_Object_Reference, to handle other forms of iterator objects in container
aggregates.
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gcc/ada/
* usage.adb (Usage): Document switch -gnatw_j
* doc/gnat_rm/gnat_language_extensions.rst: Add documentation.
* gnat_rm.texi: Regenerate.
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This patch moves the documentation for conditional when constructs out of the
curated set (e.g. into -gnatX0).
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: Move conditional when
constructs out of the curated set.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
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This patch fixes a regression introduced by g:708ee71808ea61758e73.
x86_64 allows addresses of the form:
(zero_extend:DI (subreg:SI (symbol_ref:DI "foo") 0))
Before the previous patch, a lax SUBREG check meant that we would
treat the subreg as a base and reload it into a base register.
But that wasn't what the target was expecting. Instead we should
treat "foo" as a constant displacement, to match:
leal foo, <dest>
After the patch, we recognised that "foo" isn't a base register,
but ICEd on it rather than handling it as a displacement.
With or without the recent patches, if the address had instead been:
(zero_extend:DI
(subreg:SI (plus:DI (reg:DI R) (symbol_ref:DI "foo") 0)))
then we would have treated "foo" as the displacement and R as the base
or index, as expected. The problem was that the code that does this was
rejecting all subregs of objects, rather than just subregs of variable
objects.
gcc/
PR middle-end/116516
* rtlanal.cc (strip_address_mutations): Allow subregs around
constant displacements.
gcc/testsuite/
PR middle-end/116516
* gcc.c-torture/compile/pr116516.c: New test.
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smallest_int_mode_for_size now returns an optional mode rather
than aborting on failure. This patch adjusts a couple of callers
so that they fail gracefully when no mode exists.
There should be no behavioural change, since anything that triggers
the new return paths would previously have aborted. I just think
this is how the code would have been written if the option had been
available earlier.
gcc/
* dse.cc (find_shift_sequence): Allow smallest_int_mode_for_size
to failure.
* optabs.cc (expand_twoval_binop_libfunc): Likewise.
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This patch adds new CC modes CCN and CCZN for operations that
set SREG.N, resp. SREG.Z and SREG.N. Add peephole2 patterns
to generate new compute + branch insns that make use
of the Z and N flags. Most of these patterns need their own
asm output routines that don't do all the micro-optimizations
that the ordinary outputs may perform, as the latter have no
requirement to set CC in a usable way.
We don't use cmpelim because it cannot provide scratch regs
(which peephole2 can), and some of the patterns require a
scratch reg, whereas the same operations that don't set REG_CC
don't require a scratch. See the comments in avr.md for details.
The existing add.for.cc* patterns are simplified as they no
more cover QImode, which is handled in a separate QImode case.
Apart from that, it adds 3 patterns for subtractions and one
pattern for shift left, all for multi-byte cases (HI, PSI, SI).
The add.for.cc* patterns now use CC[Z]Nmode, instead of the
formerly abuse of CCmode.
PR target/115830
gcc/
* config/avr/avr-modes.def (CCN, CCZN): New CC_MODEs.
* config/avr/avr-protos.h (avr_cond_branch): New from
ret_cond_branch.
(avr_out_plus_set_N, avr_op8_ZN_operator, avr_cmp0_code)
(avr_out_op8_set_ZN, avr_len_op8_set_ZN): New protos.
(ccn_reg_rtx, cczn_reg_rtx): New declarations.
* config/avr/avr.cc (avr_cond_branch): New from ret_cond_branch.
(avr_cond_string): Add bool cc_overflow_unusable argument.
(avr_print_operand) ['L']: Like 'j' but overflow unusable.
['K']: Like 'k' but overflow unusable.
(avr_out_plus_set_ZN): Remove handling of QImode.
(avr_out_plus_set_N, avr_op8_ZN_operator, avr_cmp0_code)
(avr_out_op8_set_ZN, avr_len_op8_set_ZN): New functions.
(avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_N]: Hande case.
(avr_class_max_nregs): All MODE_CCs occupy one hard reg.
(avr_hard_regno_nregs): Same.
(avr_hard_regno_mode_ok) [REG_CC]: Allow all MODE_CC.
(pass_manager.h, context.h, tree-pass.h): Include them.
(ccn_reg_rtx, cczn_reg_rtx): New GTY variables.
(avr_init_expanders): Initialize them.
(avr_option_override): Run peephole2 a second time.
* config/avr/avr.md (adjust_len) [add_set_N]: New attr value.
(ALLCC, HI_SI): New mode iterators.
(CCname): New mode attribute.
(eqnegtle, cmp_signed, op8_ZN): New code iterators.
(swap, SWAP): New code attributes.
(branch): Handle CCNmode and CCZNmode. Assimilate...
(difficult_branch): ...this insn.
(p1m1): Remove.
(gen_add_for_<code>_<mode>): Adjust to CCNmode and CCZNmode. Use
HISI as mode iterator. Extend peephole2s that produce them.
(*add.for.eqne.<mode>): Extend to *add.for.cc[z]n.<mode>.
(*ashift.for.ccn.<mode>): New insn and peephole2 to make them.
(*sub.for.cczn.<mode>, *sub-extend<mode>.for.cczn.<mode>):
New insns and peephole2s to make them.
(*op8.for.cczn.<code>): New insn and peephole2 to make them.
* config/avr/predicates.md (const_1_to_3_operand)
(abs1_abs2_operand, signed_comparison_operator)
(op8_ZN_operator): New predicates.
gcc/testsuite/
* gcc.target/avr/pr115830-add.c: New test.
* gcc.target/avr/pr115830-add-c.c: New test.
* gcc.target/avr/pr115830-add-i.c: New test.
* gcc.target/avr/pr115830-and.c: New test.
* gcc.target/avr/pr115830-asl.c: New test.
* gcc.target/avr/pr115830-asr.c: New test.
* gcc.target/avr/pr115830-ior.c: New test.
* gcc.target/avr/pr115830-lsr.c: New test.
* gcc.target/avr/pr115830-asl32.c: New test.
* gcc.target/avr/pr115830-sub.c: New test.
* gcc.target/avr/pr115830-sub-ext.c: New test.
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In some scenarios, it is possible for the CFG cleanup to cause one of
the labels mentioned in CO_YIELD, which coro-early-expand-ifns intends
to remove, to become part of some statement. As a result, when that
label is removed, the statement it became part of becomes invalid,
crashing the compiler.
There doesn't appear to be a reason to remove the labels (anymore, at
least), so let's not do that.
PR c++/105104
gcc/ChangeLog:
* coroutine-passes.cc (execute_early_expand_coro_ifns): Don't
remove any labels.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/torture/pr105104.C: New test.
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gcc/
* config.gcc (extra_objs) [target=avr]: Add avr-passes.o.
* config/avr/t-avr (avr-passes.o): New rule to make it.
* config/avr/avr.cc (#define INCLUDE_VECTOR): Remove.
(cfganal.h, cfgrtl.h, context.h, tree-pass.h, print-rtl.h): Don't
include them.
(avr_strict_signed_p, avr_strict_unsigned_p, avr_2comparisons_rhs)
(make_avr_pass_recompute_notes, make_avr_pass_casesi)
(make_avr_pass_ifelse, make_avr_pass_pre_proep, avr_split_tiny_move)
(emit_move_ccc, emit_move_ccc_after, reg_seen_between_p)
(avr_maybe_adjust_cfa, avr_redundant_compare_regs)
(avr_parallel_insn_from_insns, avr_is_casesi_sequence)
(avr_optimize_casesi, avr_redundant_compare, make_avr_pass_fuse_add)
(avr_optimize_2ifelse, avr_rest_of_handle_ifelse)
(avr_casei_sequence_check_operands)
Move functions...
(avr_pass_data_fuse_add, avr_pass_data_ifelse)
(avr_pass_data_casesi, avr_pass_data_recompute_notes)
(avr_pass_data_pre_proep): Move objects...
(avr_pass_fuse_add, avr_pass_pre_proep, avr_pass_recompute_notes)
(avr_pass_ifelse, avr_pass_casesi, AVR_LdSt_Props): Move classes...
* config/avr/avr-passes.cc: ... to this new C++ module.
(struct Ranges): Move to...
* config/avr/ranges.h: ...this new file.
* config/avr/avr-protos.h: Adjust comments.
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When adding RTL variants of the scan-ltrans-tree* functions in:
r15-3254-g3f51f0dc88ec21c1ec79df694200f10ef85915f4
I messed up the name of the underlying scan function to invoke. The
code currently attempts to invoke functions named
scan{,-not,-dem,-dem-not} but should instead be invoking
scan-dump{,-not,-dem,-dem-not}. This patch fixes that.
gcc/testsuite/ChangeLog:
PR testsuite/116522
* lib/scanltranstree.exp: Fix name of underlying scan function
used for scan-ltrans-{tree,rtl}-dump{,-not,-dem,-dem-not}.
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When the source mode is potentially larger than one vector (e.g. an
LMUL2 mode for VLEN=128) we don't know which vector the subreg actually
refers to. For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI))
could actually be the a full (high) vector register of a two-register
group (at VLEN=128) or the higher part of a single register (at VLEN>128).
As the subreg is statically ambiguous we prevent such situations in
can_change_mode_class.
The culprit in PR116086 is
_12 = BIT_FIELD_REF <vect_cst__42, 128, 128>;
which can be expanded with a vector-vector extract (from V4DI to V2DI).
This patch adds a VLS-mode vector-vector extract that handles "halving"
cases like this one by sliding down the source vector, thus making sure
the correct part is used.
PR target/116086
gcc/ChangeLog:
* config/riscv/autovec.md (vec_extract<mode><v_half>): Add
vector-vector extract for VLS modes.
* config/riscv/riscv.cc (riscv_can_change_mode_class): Forbid
VLS modes larger than one vector.
* config/riscv/vector-iterators.md: Add vector-vector extract
iterators.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add effective target checks for
zvl256b and zvl512b.
* gcc.target/riscv/rvv/autovec/pr116086-2-run.c: New test.
* gcc.target/riscv/rvv/autovec/pr116086-2.c: New test.
* gcc.target/riscv/rvv/autovec/pr116086.c: New test.
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This patch provides more accurate costs/gains for (wide) immediate
constants in STV, suitably adjusting the costs/gains when the highpart
and lowpart words are the same.
2024-08-28 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-features.cc (timode_immed_const_gain): New
function to determine the gain/cost on a CONST_WIDE_INT.
(timode_scalar_chain::compute_convert_gain): Fix whitespace.
<case CONST_WIDE_INT>: Provide more accurate estimates using
timode_immed_const_gain.
<case AND>: Handle CONSTANT_SCALAR_INT_P (src).
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If recording the definition of a struct member function, write an
LF_MFUNC_ID type rather than an LF_FUNC_ID. This links directly to the
struct type, rather than to an LF_STRING_ID with its name.
gcc/
* dwarf2codeview.cc (enum cv_leaf_type): Add LF_MFUNC_ID.
(write_lf_mfunc_id): New function.
(add_lf_func_id): New function.
(add_lf_mfunc_id): New function.
(add_function): Call add_lf_func_id or add_lf_mfunc_id.
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CodeView has two ways of recording struct member functions.
Non-overloaded functions have an LF_ONEMETHOD sub-type in the field
list, which records the name and the function type (LF_MFUNCTION).
Overloaded functions have an LF_METHOD instead, which points to an
LF_METHODLIST, which is an array of links to various LF_MFUNCTION types.
gcc/
* dwarf2codeview.cc (enum cv_leaf_type): Add LF_MFUNCTION,
LF_METHODLIST, LF_METHOD, and LF_ONEMETHOD.
(struct codeview_subtype): Add lf_onemethod and lf_method to union.
(struct lf_methodlist_entry): New type.
(struct codeview_custom_type): Add lf_mfunc_id, lf_mfunction, and
lf_methodlist to union.
(struct codeview_method): New type.
(struct method_hasher): New type.
(get_type_num_subroutine_type): Add forward declaration.
(write_lf_fieldlist): Handle LF_ONEMETHOD and LF_METHOD.
(write_lf_mfunction): New function.
(write_lf_methodlist): New function.
(write_custom_types): Handle LF_MFUNCTION and LF_METHODLIST.
(add_struct_function): New function.
(get_mfunction_type): New function.
(is_templated_func): New function.
(get_type_num_struct): Handle DW_TAG_subprogram child DIEs.
(get_type_num_subroutine_type): Add containing_class_type, this_type,
and this_adjustment params, and handle creating LF_MFUNCTION types as
well as LF_PROCEDURE.
(get_type_num): New params for get_type_num_subroutine_type.
(add_function): New params for get_type_num_subroutine_type.
* dwarf2codeview.h (CV_METHOD_VANILLA, CV_METHOD_VIRTUAL): Define.
(CV_METHOD_STATIC, CV_METHOD_FRIEND, CV_METHOD_INTRO): Likewise.
(CV_METHOD_PUREVIRT, CV_METHOD_PUREINTRO): Likewise.
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Record LF_STMEMBER field list subtypes to represent static data members
in structs.
gcc/
* dwarf2codeview.cc (enum cv_leaf_type): Add LF_STMEMBER.
(struct codeview_subtype): Add lf_static_member to union.
(write_lf_fieldlist): Handle LF_STMEMBER.
(add_struct_member): New function.
(add_struct_static_member): New function.
(get_accessibility): New function.
(get_type_num_struct): Split out into add_struct_member and
get_accessibility, and handle static members.
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If a function is in a namespace, create an LF_STRING_ID type for the
name of its parent, and record this in the LF_FUNC_ID type we create
for the function.
gcc/
* dwarf2codeview.cc (enum cf_leaf_type): Add LF_STRING_ID.
(struct codeview_custom_type): Add lf_string_id to union.
(struct string_id_hasher): New type.
(string_id_htab): New global variable.
(write_lf_string_id): New function.
(write_custom_types): Call write_lf_string_id.
(codeview_debug_finish): Free string_id_htab.
(add_string_id): New function.
(get_scope_string_id): New function.
(add_function): Call get_scope_string_id and set scope.
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Run all CodeView names through a new function get_name, which chains
together a DIE's DW_AT_name with that of its parent to create a
C++-style name.
gcc/
* dwarf2codeview.cc (get_name): New function.
(add_enum_forward_def): Call get_name.
(get_type_num_enumeration_type): Call get_name.
(add_struct_forward_def): Call get_name.
(get_type_num_struct): Call get_name.
(add_variable): Call get_name.
(add function): Call get_name.
* dwarf2out.cc (get_die_parent): Rename to dw_get_die_parent and make
non-static.
(generate_type_signature): Handle renamed get_die_parent.
* dwarf2out.h (dw_get_die_parent): Add declaration.
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Here maybe_init_list_as_array gets elttype=field, init={NON_LVALUE_EXPR <2>}
and it tries to convert the init's element type (int) to field
using implicit_conversion, which works, so overall maybe_init_list_as_array
is successful.
But it constifies init_elttype so we end up with "const int". Later,
when we actually perform the conversion and invoke field::field(T&&),
we end up with this error:
error: binding reference of type 'int&&' to 'const int' discards qualifiers
So I think maybe_init_list_as_array should try to perform the conversion,
like it does below with fc.
PR c++/116476
gcc/cp/ChangeLog:
* call.cc (maybe_init_list_as_array): Try convert_like and see if it
worked.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-opt2.C: New test.
Reviewed-by: Jason Merrill <jason@redhat.com>
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This patch removes the warnings generated by -Wodr from the library
interface between modula-2 and C.
gcc/m2/ChangeLog:
PR modula2/116181
* Make-lang.in (MC_SRC_FLAGS): New macro.
(m2/mc-boot/$(SRC_PREFIX)%.o): Use MC_SRC_FLAGS.
(m2/mc-boot-ch/$(SRC_PREFIX)%.o): Ditto.
(m2/gm2-libs-boot/M2RTS.o): Ditto.
(m2/gm2-libs-boot/%.o): Ditto.
(GM2-LIBS-BOOT-H): New macro.
(m2/gm2-libs-boot/RTcodummy.o): Use MC_SRC_FLAGS.
Remove gm2-libs-host.h from the dependancy.
(m2/gm2-libs-boot/wrapc.o): Use MC_SRC_FLAGS.
Add dependancy GM2-LIBS-BOOT-H.
(m2/gm2-libs-boot/UnixArgs.o): Ditto.
(m2/gm2-libs-boot/choosetemp.o): Ditto.
(m2/gm2-libs-boot/errno.o): Ditto.
(m2/gm2-libs-boot/dtoa.o): Ditto.
(m2/gm2-libs-boot/ldtoa.o): Ditto.
(m2/gm2-libs-boot/termios.o): Ditto.
(m2/gm2-libs-boot/SysExceptions.o): Ditto.
(m2/gm2-compiler-boot/M2GCCDeclare.o): Add gm2-libs-ch to the
search path.
(m2/gm2-compiler-boot/M2Error.o): Ditto.
(m2/gm2-compiler-boot/%.o): Ditto.
(m2/pge-boot/%.o): Ditto.
* gm2-gcc/m2color.cc (m2color_colorize_start): Replace parameter
type char to void and recast to char * when calling colorize_start.
* gm2-gcc/m2color.h (m2color_colorize_start): Replace parameter
type char to void.
* gm2-gcc/m2type.h: Remove #if 0 block.
* gm2-libs-ch/SysExceptions.c (DECL_PROC_T): Provide alternative
defines for MC an gm2.
(PROC_FUNC): Ditto.
(EXTERN): Force undefine and redefine.
(SysExceptions_InitExceptionHandlers): Rewrite function
declaration using defined macros.
(_M2_SysExceptions_init): Use EXTERN.
(_M2_SysExceptions_finish): Replace with ...
(_M2_SysExceptions_fini): ... this and add parameters.
* gm2-libs-ch/UnixArgs.cc (gm2-libs-host.h): Include.
(GUnixArgs.h): Include.
(GM2RTS.h): Include.
(UnixArgs_GetArgV): Change return type to void *.
(UnixArgs_GetEnvV): Ditto.
* gm2-libs-ch/m2rts.h (M2RTS_RegisterModule_Cstr): Add new
conditional macro.
(M2RTS_RequestDependant): Remove.
(M2RTS_RegisterModule): Ditto.
(M2RTS_Terminate): Ditto.
(M2RTS_DeconstructModules): Ditto.
(M2RTS_Halt): Ditto.
(_M2_M2RTS_init): Ditto.
(M2RTS_ConstructModules): Ditto.
* gm2-libs-ch/termios.c (_termios_C): Define.
(EXTERN): Add conditional definition.
(doSetUnset): New function.
(_M2_termios_init): Add correct parameters.
(_M2_termios_finish): Ditto.
(_M2_termios_fini): Ditto.
* mc-boot-ch/GSysExceptions.c (DECL_PROC_T): New define.
(PROC_FUNC): Ditto.
(EXTERN): Force undef.
(SysExceptions_InitExceptionHandlers): Rewrite.
* mc-boot-ch/Glibc.c (libc_open): Rename parameter
oflag to flags.
* mc-boot-ch/Gtermios.cc (_termios_C): New define.
(KillTermios): Change parameter type from
struct termios * to termios_TERMIOS.
(tcsnow): Rewrite.
(tcsnow): Rewrite.
(tcsdrain): Rewrite.
(tcsflush): Rewrite.
(cfgetospeed): Rewrite.
(cfgetispeed): Rewrite.
(cfsetospeed): Rewrite.
(cfsetispeed): Rewrite.
(cfsetspeed): Rewrite.
(cfsetspeed): Rewrite.
(tcgetattr): Rewrite.
(tcsetattr): Rewrite.
(cfmakeraw): Rewrite.
(tcsendbreak): Rewrite.
(tcdrain): Rewrite.
(tcflushi): Rewrite.
(tcflusho): Rewrite.
(tcflushio): Rewrite.
(tcflowoni): Rewrite.
(tcflowoffi): Rewrite.
(tcflowono): Rewrite.
(tcflowoffo): Rewrite.
(GetFlag): Rewrite.
(SetFlag): Rewrite.
(GetChar): Rewrite.
(SetChar): Rewrite.
(InitTermios): Rewrite.
* pge-boot/GM2RTS.cc: Regenerate.
* pge-boot/GSysExceptions.cc: Ditto.
* pge-boot/Gtermios.cc: Ditto.
* pge-boot/m2rts.h: Rewrite.
* mc-boot-ch/GSYSTEM.h: New file.
* mc-boot-ch/GSysExceptions.h: New file.
* mc-boot-ch/Gtermios.h: New file.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
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While working on PR 114224, I found it would be useful to dump the
different costs of the expansion to make easier to understand why one
was chosen over the other.
Changes since v1:
* v2: make the dump a single line
Bootstrapped and tested on x86_64-linux-gnu.
Build and tested for aarch64-linux-gnu.
gcc/ChangeLog:
* internal-fn.cc (expand_POPCOUNT): Dump the costs for
the two choices.
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gcc/ChangeLog:
* doc/contrib.texi (Contributors): Add Dhruv Matani.
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Mini-pass avr-ifelse realizes optimizations that replace two cbranch
insns with one comparison and two branches. This patch adds the
following improvements:
- The right operand of the comparisons may also be REGs.
Formerly only CONST_INT was handled.
- The RTX code of the first comparison in no more restricted
to (effectively) EQ.
- When the second cbranch is located in the fallthrough path
of the first cbranch, then difficult (expensive) comparisons
can always be avoided. This may require to swap the branch
targets. (When the second cbranch is located after the target
label of the first one, then getting rid of difficult branches
would require to reorder blocks.)
- The code has been cleaned up: avr_rest_of_handle_ifelse() now
just scans the insn stream for optimization candidates. The code
that actually performs the transformation has been outsourced to
the new function avr_optimize_2ifelse().
- The code to find a better representation for reg-const_int comparisons
has been split into two parts: First try to find codes such that the
right-hand sides of the comparisons are the same (avr_2comparisons_rhs).
When this succeeds then one comparison can serve two branches, and
that function tries to get rid of difficult branches. This is always
possible when the second cbranch is located in the fallthrough path
of the first one.
Some final notes on why we don't use compare-elim: 1) The two cbranch
insns may come with different scratch operands depending on the chosen
constraint alternatives. There are cases where the outgoing comparison
requires a scratch but only one incoming cbranch has one. 2) Avoiding
difficult branches can be achieved by rewiring basic blocks.
compare-elim doesn't do that; it doesn't even know the costs of the
branch codes. 3) avr_2comparisons_rhs() may de-canonicalize a
comparison to achieve its goal. compare-elim doesn't know how to do
that. 4) There are more reasons, see for example the commit message
and discussion for PR115830.
avr_2comparisons_rhs tries to decompose the interval as given by some
[u]intN_t into three intervals using the new Ranges struct that
implemens set operations on finite unions of intervals.
Sadly, value-range.h is not well suited for that, and writing a
wrapper around it that avoids all corner case ICEs would be more
laborious than struct Ranges.
gcc/
* config/avr/avr.cc (INCLUDE_VECTOR): Define it.
(cfganal.h): Include it.
(Ranges): New struct.
(avr_2comparisons_rhs, avr_redundant_compare_regs)
(avr_strict_signed_p, avr_strict_unsigned_p): New static functions.
(avr_redundant_compare): Overhaul: Allow more cases.
(avr_optimize_2ifelse): New static function, outsourced from...
(avr_rest_of_handle_ifelse): ...this method.
gcc/testsuite/
* gcc.target/avr/torture/ifelse-c.h: New file.
* gcc.target/avr/torture/ifelse-d.h: New file.
* gcc.target/avr/torture/ifelse-q.h: New file.
* gcc.target/avr/torture/ifelse-r.h: New file.
* gcc.target/avr/torture/ifelse-c-i8.c: New test.
* gcc.target/avr/torture/ifelse-d-i8.c: New test.
* gcc.target/avr/torture/ifelse-q-i8.c: New test.
* gcc.target/avr/torture/ifelse-r-i8.c: New test.
* gcc.target/avr/torture/ifelse-c-i16.c: New test.
* gcc.target/avr/torture/ifelse-d-i16.c: New test.
* gcc.target/avr/torture/ifelse-q-i16.c: New test.
* gcc.target/avr/torture/ifelse-r-i16.c: New test.
* gcc.target/avr/torture/ifelse-c-u16.c: New test.
* gcc.target/avr/torture/ifelse-d-u16.c: New test.
* gcc.target/avr/torture/ifelse-q-u16.c: New test.
* gcc.target/avr/torture/ifelse-r-u16.c: New test.
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* ka.po: New file.
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Here we crash on a cp_gimplify_expr/TARGET_EXPR assert:
gcc_checking_assert (!TARGET_EXPR_ELIDING_P (*expr_p)
|| !TREE_ADDRESSABLE (TREE_TYPE (*expr_p)));
We cannot elide the TARGET_EXPR because we're taking its address.
It is set as eliding in massage_init_elt. I've tried to not set
TARGET_EXPR_ELIDING_P when the context is not direct-initialization.
That didn't work: even when it's not direct-initialization now, it
can become one later, for instance, after split_nonconstant_init.
One problem is that replace_placeholders_for_class_temp_r will replace
placeholders in non-eliding TARGET_EXPRs with the slot, but if we then
elide the TARGET_EXPR, we end up with a "stray" VAR_DECL and crash.
(Only some TARGET_EXPRs are handled by replace_decl.)
I thought I'd have to go back to
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651163.html> but
then I realized that this problem occurrs only with ()-init but not
{}-init. With {}-init, there is no problem, because we are clearing
TARGET_EXPR_ELIDING_P in process_init_constructor_record:
/* We can't actually elide the temporary when initializing a
potentially-overlapping field from a function that returns by
value. */
if (ce->index
&& TREE_CODE (next) == TARGET_EXPR
&& unsafe_copy_elision_p (ce->index, next))
TARGET_EXPR_ELIDING_P (next) = false;
But that does not happen for ()-init because we have no ce->index.
()-init doesn't allow brace elision so we don't really reshape them.
But I can just move the clearing a few lines down and then it handles
both ()-init and {}-init.
PR c++/116424
gcc/cp/ChangeLog:
* typeck2.cc (process_init_constructor_record): Move the clearing of
TARGET_EXPR_ELIDING_P down.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/paren-init38.C: New test.
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generic_vector_cost is not currently used by any SVE target
by default; it has to be specifically selected by -mtune=generic.
Its SVE costing has historically been somewhat idealised, since
it predated any actual SVE cores. This seems like a useful
tradition to continue, at least for testing purposes.
The ideal case is that gathers and scatters do not induce a specific
one-off overhead. This patch therefore sets the gather/scatter init
costs to zero.
This patch is necessary to switch -mtune=generic over to the
"new" vector costs.
gcc/
* config/aarch64/tuning_models/generic.h (generic_sve_vector_cost):
Set gather_load_x32_init_cost and gather_load_x64_init_cost to 0.
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The SVE gather and scatter costs are classified based on whether
they do 4 loads per 128 bits (x32) or 2 loads per 128 bits (x64).
The number after the "x" refers to the number of bits in each
"container".
However, the test for which to use was based on the element size
rather than the container size. This meant that we'd use the
overly conservative x32 costs for VNx2SI gathers. VNx2SI gathers
are really .D gathers in which the upper half of each extension
result is ignored.
This patch is necessary to switch -mtune=generic over to the
"new" vector costs.
gcc/
* config/aarch64/aarch64.cc (aarch64_detect_vector_stmt_subtype)
(aarch64_vector_costs::add_stmt_cost): Use the x64 cost rather
than x32 cost for all VNx2 modes.
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g:8d6c6fbc5271dde433998c09407b30e2cf195420 improved the code
generated for functions like:
void test_s8 (int8x8x2_t *ptr) { *ptr = (int8x8x2_t) {}; }
Previously we would load zero from the constant pool, whereas
now we just use "stp xzr, xzr". This patch adds a test for
this improvement.
gcc/testsuite/
* gcc.target/aarch64/struct_zero.c: New test.
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The documentation of ASM_INPUT_P implied that the flag has no
effect on ASM_EXPRs that have operands (and which therefore must be
extended asms). In fact we require ASM_INPUT_P to be false for all
extended asms.
gcc/
* tree.h (ASM_INPUT_P): Fix documentation.
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transform [PR116355]
The gen_pow2p function generates (a & -a) == a as a fallback for
POPCOUNT (a) == 1. Not only is the bitmagic not equivalent to
POPCOUNT (a) == 1 but it also introduces UB (consider signed
a = INT_MIN).
This patch rewrites gen_pow2p to always use __builtin_popcount instead.
This means that what the end result GIMPLE code is gets decided by an
already existing machinery in a later pass. That is a cleaner solution
I think. This existing machinery also uses a ^ (a - 1) > a - 1 which is
the correct bitmagic.
While rewriting gen_pow2p I had to add logic for converting the
operand's type to a type that __builtin_popcount accepts. I naturally
also added this logic to gen_log2. Thanks to this, exponential index
transform gains the capability to handle all operand types with
precision at most that of long long int.
gcc/ChangeLog:
PR tree-optimization/116355
* tree-switch-conversion.cc (can_log2): Add capability to
suggest converting the operand to a different type.
(gen_log2): Add capability to generate a conversion in case the
operand is of a type incompatible with the logarithm operation.
(can_pow2p): New function.
(gen_pow2p): Rewrite to use __builtin_popcount instead of
manually inserting an internal fn call or bitmagic. Also add
capability to generate a conversion.
(switch_conversion::is_exp_index_transform_viable): Call
can_pow2p. Store types suggested by can_log2 and gen_log2.
(switch_conversion::exp_index_transform): Params of gen_pow2p
and gen_log2 changed so update their calls.
* tree-switch-conversion.h: Add m_exp_index_transform_log2_type
and m_exp_index_transform_pow2p_type to switch_conversion class
to track type conversions needed to generate the "is power of 2"
and logarithm operations.
gcc/testsuite/ChangeLog:
PR tree-optimization/116355
* gcc.target/i386/switch-exp-transform-1.c: Don't test for
presence of POPCOUNT internal fn after switch conversion. Test
for it after __builtin_popcount has had a chance to get
expanded.
* gcc.target/i386/switch-exp-transform-3.c: Also test char and
short.
Signed-off-by: Filip Kastl <fkastl@suse.cz>
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This extends the scan-ltrans-tree* helpers to create RTL variants. This
is needed to check the behaviour of an RTL pass under LTO.
gcc/ChangeLog:
PR libstdc++/116140
* doc/sourcebuild.texi: Document ltrans-rtl value of kind for
scan-<kind>-dump*.
gcc/testsuite/ChangeLog:
PR libstdc++/116140
* lib/scanltranstree.exp (scan-ltrans-rtl-dump): New.
(scan-ltrans-rtl-dump-not): New.
(scan-ltrans-rtl-dump-dem): New.
(scan-ltrans-rtl-dump-dem-not): New.
(scan-ltrans-rtl-dump-times): New.
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I found it helpful to be able to print a whole SLP instance from gdb.
* tree-vect-slp.cc (debug): Add overload for slp_instance.
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The following fixes a leak of the discovered single-lane store
SLP nodes from which we only use their children. This uncovers
a latent reference counting issue in the interleaving build where
we fail to increment their reference count.
* tree-vect-slp.cc (vect_build_slp_store_interleaving):
Fix reference counting.
(vect_build_slp_instance): Release rhs_nodes.
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This splits out SLP store interleaving into a separate function.
* tree-vect-slp.cc (vect_build_slp_store_interleaving): Split
out from ...
(vect_build_slp_instance): Here.
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The pedwarns for each of these features should be silenced by
the appropriate -Wno-c++??-extensions.
The handle_pragma_diagnostic_impl change is necessary so that we handle
-Wc++23-extensions early so it's available to interpret_float while lexing.
gcc/c-family/ChangeLog:
* c-pragma.cc (handle_pragma_diagnostic_impl): Also handle
-Wc++23-extensions early.
* c-lex.cc (interpret_float): Use -Wc++23-extensions for extended
floating point literal pedwarn.
gcc/cp/ChangeLog:
* parser.cc (cp_parser_simple_type_specifier): Use
-Wc++20-extensions for auto parameter pedwarn.
* pt.cc (do_decl_instantiation, do_type_instantiation): Use
-Wc++11-extensions for 'extern template'.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/extern_template-7.C: New test.
* g++.dg/cpp23/ext-floating19.C: New test.
* g++.dg/cpp2a/abbrev-fn1.C: New test.
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|
Move the run test of pr116278 to dg/torture and leave the risc-v the
asm check under risc-v part.
PR target/116278
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr116278-run-1.c: Take compile instead of run.
* gcc.target/riscv/pr116278-run-2.c: Ditto.
* gcc.dg/torture/pr116278-run-1.c: New test.
* gcc.dg/torture/pr116278-run-2.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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The .SAT_ADD has 2 operand, when one of the operand may be INTEGER_CST.
For example _1 = .SAT_ADD (_2, 9) comes from below sample code.
Form 3:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
T ret; \
for (i = 0; i < limit; i++) \
{ \
out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
} \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9)
It will fail to vectorize as the vectorizable_call will check the
operands is type_compatiable but the imm will be (const_int 9) with
the SImode, which is different from _2 (DImode). Aka:
uint64_t _1;
uint64_t _2;
_1 = .SAT_ADD (_2, 9);
This patch would like to reconcile the imm operand to the operand type
mode of _2 by fold_convert to make the vectorizable_call happy.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
gcc/ChangeLog:
* tree-vect-patterns.cc (vect_recog_sat_add_pattern): Add fold
convert for const_int to the type of operand 0.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-4.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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We add pattern for vector rotate, but seems like we forgot adding
mode_idx which used in AVL propgation (riscv-avlprop.cc).
gcc/ChangeLog:
* config/riscv/vector.md (mode_idx): Add vrol and vror.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/rotr.c: New.
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This patch would like to support the form 1 of the scalar signed
integer .SAT_ADD. Aka below example:
Form 1:
#define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_add_##T##_fmt_1 (T x, T y) \
{ \
T sum = (UT)x + (UT)y; \
return (x ^ y) < 0 \
? sum \
: (sum ^ x) >= 0 \
? sum \
: x < 0 ? MIN : MAX; \
}
DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
We can tell the difference before and after this patch if backend
implemented the ssadd<m>3 pattern similar as below.
Before this patch:
4 │ __attribute__((noinline))
5 │ int64_t sat_s_add_int64_t_fmt_1 (int64_t x, int64_t y)
6 │ {
7 │ int64_t sum;
8 │ long unsigned int x.0_1;
9 │ long unsigned int y.1_2;
10 │ long unsigned int _3;
11 │ long int _4;
12 │ long int _5;
13 │ int64_t _6;
14 │ _Bool _11;
15 │ long int _12;
16 │ long int _13;
17 │ long int _14;
18 │ long int _16;
19 │ long int _17;
20 │
21 │ ;; basic block 2, loop depth 0
22 │ ;; pred: ENTRY
23 │ x.0_1 = (long unsigned int) x_7(D);
24 │ y.1_2 = (long unsigned int) y_8(D);
25 │ _3 = x.0_1 + y.1_2;
26 │ sum_9 = (int64_t) _3;
27 │ _4 = x_7(D) ^ y_8(D);
28 │ _5 = x_7(D) ^ sum_9;
29 │ _17 = ~_4;
30 │ _16 = _5 & _17;
31 │ if (_16 < 0)
32 │ goto <bb 3>; [41.00%]
33 │ else
34 │ goto <bb 4>; [59.00%]
35 │ ;; succ: 3
36 │ ;; 4
37 │
38 │ ;; basic block 3, loop depth 0
39 │ ;; pred: 2
40 │ _11 = x_7(D) < 0;
41 │ _12 = (long int) _11;
42 │ _13 = -_12;
43 │ _14 = _13 ^ 9223372036854775807;
44 │ ;; succ: 4
45 │
46 │ ;; basic block 4, loop depth 0
47 │ ;; pred: 2
48 │ ;; 3
49 │ # _6 = PHI <sum_9(2), _14(3)>
50 │ return _6;
51 │ ;; succ: EXIT
52 │
53 │ }
After this patch:
4 │ __attribute__((noinline))
5 │ int64_t sat_s_add_int64_t_fmt_1 (int64_t x, int64_t y)
6 │ {
7 │ int64_t _4;
8 │
9 │ ;; basic block 2, loop depth 0
10 │ ;; pred: ENTRY
11 │ _4 = .SAT_ADD (x_5(D), y_6(D)); [tail call]
12 │ return _4;
13 │ ;; succ: EXIT
14 │
15 │ }
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add the matching for signed .SAT_ADD.
* tree-ssa-math-opts.cc (gimple_signed_integer_sat_add): Add new
matching func decl.
(match_unsigned_saturation_add): Try signed .SAT_ADD and rename
to ...
(match_saturation_add): ... here.
(math_opts_dom_walker::after_dom_children): Update the above renamed
func from caller.
Signed-off-by: Pan Li <pan2.li@intel.com>
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gcc/testsuite:
PR testsuite/116271
* gcc.dg/vect/tsvc/vect-tsvc-s176.c [TRUNCATE_TEST]: Make sure
that m stays the same as the loop bound of the middle loop.
* gcc.dg/vect/tsvc/tsvc.h (get_expected_result) <s176> [TRUNCATE_TEST]:
Adjust expected value.
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|
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_SUB_IMM_FMT_4(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_4 (T x) \
{ \
return x > (T)IMM ? x - (T)IMM : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 23)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-16.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
{ \
return (T)IMM > y ? (T)IMM - y : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 23)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-10.c: New test.
* gcc.target/riscv/sat_u_sub_imm-10_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-10_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-12.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-10.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-11.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-12.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
|
|
SPARC does not support vectorizing conditions, which this test relies
on. Use vect_condition as effective target.
Committed as obvious.
PR testsuite/116500
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-switch-ifcvt-1.c: Use vect_condition to
check if vectorizing conditions is supported for target.
|
|
* zh_CN.po: Update.
|
