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To implement -fomit-leaf-frame-pointer, there are 2 places where we need
to check whether we have to use a frame chain (since register allocation
may allocate LR in a leaf function that omits the frame pointer, but if
LR is spilled we must emit a frame chain). To simplify this do not force
frame_pointer_needed via aarch64_frame_pointer_required, but enable the
frame chain in aarch64_layout_frame. Now aarch64_frame_pointer_required
can be removed and aarch64_can_eliminate is simplified.
gcc/
* config/aarch64/aarch64.c (aarch64_frame_pointer_required)
Remove.
(aarch64_layout_frame): Initialise emit_frame_chain.
(aarch64_can_eliminate): Remove omit leaf frame pointer code.
(TARGET_FRAME_POINTER_REQUIRED): Remove define.
testsuite/
* gcc.target/aarch64/dwarf-cfa-reg.c: Update.
From-SVN: r254533
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this routine to handle multiple levels of derivations.
gcc/ada/
2017-11-08 Javier Miranda <miranda@adacore.com>
* sem_disp.adb (Is_Inherited_Public_Operation): Extend the
functionality of this routine to handle multiple levels of derivations.
2017-11-08 Hristian Kirtchev <kirtchev@adacore.com>
* einfo.adb: Elist36 is now used as Nested_Scenarios.
(Nested_Scenarios): New routine.
(Set_Nested_Scenarios): New routine.
(Write_Field36_Name): New routine.
* einfo.ads: Add new attribute Nested_Scenarios along with occurrences
in entities.
(Nested_Scenarios): New routine along with pragma Inline.
(Set_Nested_Scenarios): New routine along with pragma Inline.
* sem_elab.adb (Find_And_Process_Nested_Scenarios): New routine.
(Process_Nested_Scenarios): New routine.
(Traverse_Body): When a subprogram body is traversed for the first
time, find, save, and process all suitable scenarios found within.
Subsequent traversals of the same subprogram body utilize the saved
scenarios.
2017-11-08 Piotr Trojanek <trojanek@adacore.com>
* lib-xref-spark_specific.adb (Add_SPARK_Scope): Remove detection of
protected operations.
(Add_SPARK_Xrefs): Simplify detection of empty entities.
* get_spark_xrefs.ads, get_spark_xrefs.adb, put_spark_xrefs.ads,
put_spark_xrefs.adb, spark_xrefs_test.adb: Remove code for writing,
reading and testing SPARK cross-references stored in the ALI files.
* lib-xref.ads (Output_SPARK_Xrefs): Remove.
* lib-writ.adb (Write_ALI): Do not write SPARK cross-references to the
ALI file.
* spark_xrefs.ads, spark_xrefs.adb (pspark): Remove, together
with description of the SPARK xrefs ALI format.
* gcc-interface/Make-lang.in (GNAT_ADA_OBJS): Remove get_spark_refs.o
and put_spark_refs.o.
2017-11-08 Hristian Kirtchev <kirtchev@adacore.com>
* exp_ch4.adb (Apply_Accessibility_Check): Do not finalize the object
when the associated access type is subject to pragma
No_Heap_Finalization.
* exp_intr.adb (Expand_Unc_Deallocation): Use the available view of the
designated type in case it comes from a limited withed unit.
gcc/testsuite/
2017-11-08 Javier Miranda <miranda@adacore.com>
* gnat.dg/overriding_ops2.adb, gnat.dg/overriding_ops2.ads,
gnat.dg/overriding_ops2_pkg.ads, gnat.dg/overriding_ops2_pkg-high.ads:
New testcase.
From-SVN: r254532
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SPARK-related flags.
2017-11-08 Hristian Kirtchev <kirtchev@adacore.com>
* exp_ch3.adb (Expand_N_Object_Declaration): Save and restore relevant
SPARK-related flags. Add ??? comment.
* exp_util.adb (Insert_Actions): Add an entry for node
N_Variable_Reference_Marker.
* sem.adb (Analyze): Add an entry for node N_Variable_Reference_Marker.
* sem_ch8.adb (Find_Direct_Name): Add constant Is_Assignment_LHS. Build
and record a variable reference marker for the current name.
(Find_Expanded_Name): Add constant Is_Assignment_LHS. Build and record
a variable reference marker for the current name.
* sem_elab.adb (Build_Variable_Reference_Marker): New routine.
(Extract_Variable_Reference_Attributes): Reimplemented.
(Info_Scenario): Add output for variable references and remove output
for variable reads.
(Info_Variable_Read): Removed.
(Info_Variable_Reference): New routine.
(Is_Suitable_Scenario): Variable references are now suitable scenarios
while variable reads are not.
(Output_Active_Scenarios): Add output for variable references and
remove output for variable reads.
(Output_Variable_Read): Removed.
(Output_Variable_Reference): New routine.
(Process_Variable_Read): Removed.
(Process_Variable_Reference): New routine.
(Process_Variable_Reference_Read): New routine.
* sem_elab.ads (Build_Variable_Reference_Marker): New routine.
* sem_res.adb (Resolve_Actuals): Build and record a variable reference
marker for the current actual.
* sem_spark.adb (Check_Node): Add an entry for node
N_Variable_Reference_Marker.
* sem_util.adb (Within_Subprogram_Call): Moved to the library level.
* sem_util.ads (Within_Subprogram_Call): Moved to the library level.
* sinfo.adb (Is_Read): New routine.
(Is_Write): New routine.
(Target): Updated to handle variable reference markers.
(Set_Is_Read): New routine.
(Set_Is_Write): New routine.
(Set_Target): Updated to handle variable reference markers.
* sinfo.ads: Add new attributes Is_Read and Is_Write along with
occurrences in nodes. Update attribute Target. Add new node
kind N_Variable_Reference_Marker.
(Is_Read): New routine along with pragma Inline.
(Is_Write): New routine along with pragma Inline.
(Set_Is_Read): New routine along with pragma Inline.
(Set_Is_Write): New routine along with pragma Inline.
* sprint.adb (Sprint_Node_Actual): Add an entry for node
N_Variable_Reference_Marker.
From-SVN: r254531
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* c-c++-common/torture/aarch64-vect-lane-2.c (search_line_fast):
Change type to void.
From-SVN: r254530
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2017-11-08 Arnaud Charlet <charlet@adacore.com>
* sem_util.adb (Subprogram_Name): Append suffix for overloaded
subprograms.
From-SVN: r254529
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2017-11-08 Yannick Moy <moy@adacore.com>
* sem_ch8.adb (Use_One_Type, Update_Use_Clause_Chain): Do not report
about unused use-type or use-package clauses inside inlined bodies.
2017-11-08 Hristian Kirtchev <kirtchev@adacore.com>
* sem_elab.adb (Ensure_Prior_Elaboration): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not guarantee the
prior elaboration of a unit when the need came from a partial
finalization context.
(In_Initialization_Context): Relocated to Process_Call.
(Is_Partial_Finalization_Proc): New routine.
(Process_Access): Add new parameter In_Partial_Fin along with a comment
on its usage.
(Process_Activation_Call): Add new parameter In_Partial_Fin along with
a comment on its usage.
(Process_Activation_Conditional_ABE_Impl): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not emit any ABE
diagnostics when the activation occurs in a partial finalization
context.
(Process_Activation_Guaranteed_ABE_Impl): Add new parameter
In_Partial_Fin along with a comment on its usage.
(Process_Call): Add new parameter In_Partial_Fin along with a comment
on its usage. A call is within a partial finalization context when it
targets a finalizer or primitive [Deep_]Finalize, and the call appears
in initialization actions. Pass this information down to the recursive
steps of the Processing phase.
(Process_Call_Ada): Add new parameter In_Partial_Fin along with a
comment on its usage. Remove the guard which suppresses the generation
of implicit Elaborate[_All] pragmas. This is now done in
Ensure_Prior_Elaboration.
(Process_Call_Conditional_ABE): Add new parameter In_Partial_Fin along
with a comment on its usage. Do not emit any ABE diagnostics when the
call occurs in a partial finalization context.
(Process_Call_SPARK): Add new parameter In_Partial_Fin along with a
comment on its usage.
(Process_Instantiation): Add new parameter In_Partial_Fin along with a
comment on its usage.
(Process_Instantiation_Ada): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Process_Instantiation_Conditional_ABE): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not emit any ABE
diagnostics when the instantiation occurs in a partial finalization
context.
(Process_Instantiation_SPARK): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Process_Scenario): Add new parameter In_Partial_Fin along with a
comment on its usage.
(Process_Single_Activation): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Traverse_Body): Add new parameter In_Partial_Fin along with a comment
on its usage.
2017-11-08 Arnaud Charlet <charlet@adacore.com>
* sem_ch13.adb: Add optional parameter to Error_Msg.
2017-11-08 Jerome Lambourg <lambourg@adacore.com>
* fname.adb (Is_Internal_File_Name): Do not check the 8+3 naming schema
for the Interfaces.* hierarchy as longer unit names are now allowed.
2017-11-08 Arnaud Charlet <charlet@adacore.com>
* sem_util.adb (Subprogram_Name): Emit sloc for the enclosing
subprogram as well. Support more cases of entities.
(Append_Entity_Name): Add some defensive code.
From-SVN: r254528
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Earlier GFortran used to redefine boolean_type_node, which in the rest
of the compiler means the C/C++ _Bool/bool type, to the Fortran
default logical type. When this redefinition was removed, a few
issues surfaced. Namely,
1) PR 82869, where we created a boolean tmp variable, and passed it to
the runtime library as a Fortran logical variable of a different size.
2) Fortran specifies that logical operations should be done with the
default logical kind, not in any other kind.
3) Using 8-bit variables have some issues, such as
- on x86, partial register stalls and length prefix changes.
- s390 has a compare with immediate and jump instruction which
works with 32-bit but not 8-bit quantities.
This patch addresses these issues by introducing a type
logical_type_node which is a Fortran LOGICAL variable of default
kind. It is then used in places were the Fortran standard mandates, as
well as for compiler generated temporary variables.
For x86-64, using the Polyhedron benchmark suite, no performance or
code size difference worth mentioning was observed.
Regtested on x86_64-pc-linux-gnu.
gcc/fortran/ChangeLog:
2017-11-08 Janne Blomqvist <jb@gcc.gnu.org>
PR 82869
* convert.c (truthvalue_conversion): Use logical_type_node.
* trans-array.c (gfc_trans_allocate_array_storage): Likewise.
(gfc_trans_create_temp_array): Likewise.
(gfc_trans_array_ctor_element): Likewise.
(gfc_trans_array_constructor_value): Likewise.
(trans_array_constructor): Likewise.
(trans_array_bound_check): Likewise.
(gfc_conv_array_ref): Likewise.
(gfc_trans_scalarized_loop_end): Likewise.
(gfc_conv_array_extent_dim): Likewise.
(gfc_array_init_size): Likewise.
(gfc_array_allocate): Likewise.
(gfc_trans_array_bounds): Likewise.
(gfc_trans_dummy_array_bias): Likewise.
(gfc_conv_array_parameter): Likewise.
(duplicate_allocatable): Likewise.
(duplicate_allocatable_coarray): Likewise.
(structure_alloc_comps): Likewise
(get_std_lbound): Likewise
(gfc_alloc_allocatable_for_assignment): Likewise
* trans-decl.c (add_argument_checking): Likewise
(gfc_generate_function_code): Likewise
* trans-expr.c (gfc_copy_class_to_class): Likewise
(gfc_trans_class_array_init_assign): Likewise
(gfc_trans_class_init_assign): Likewise
(gfc_conv_expr_present): Likewise
(gfc_conv_substring): Likewise
(gfc_conv_cst_int_power): Likewise
(gfc_conv_expr_op): Likewise
(gfc_conv_procedure_call): Likewise
(fill_with_spaces): Likewise
(gfc_trans_string_copy): Likewise
(gfc_trans_alloc_subarray_assign): Likewise
(gfc_trans_pointer_assignment): Likewise
(gfc_trans_scalar_assign): Likewise
(fcncall_realloc_result): Likewise
(alloc_scalar_allocatable_for_assignment): Likewise
(trans_class_assignment): Likewise
(gfc_trans_assignment_1): Likewise
* trans-intrinsic.c (build_fixbound_expr): Likewise
(gfc_conv_intrinsic_aint): Likewise
(gfc_trans_same_strlen_check): Likewise
(conv_caf_send): Likewise
(trans_this_image): Likewise
(conv_intrinsic_image_status): Likewise
(trans_image_index): Likewise
(gfc_conv_intrinsic_bound): Likewise
(conv_intrinsic_cobound): Likewise
(gfc_conv_intrinsic_mod): Likewise
(gfc_conv_intrinsic_dshift): Likewise
(gfc_conv_intrinsic_dim): Likewise
(gfc_conv_intrinsic_sign): Likewise
(gfc_conv_intrinsic_ctime): Likewise
(gfc_conv_intrinsic_fdate): Likewise
(gfc_conv_intrinsic_ttynam): Likewise
(gfc_conv_intrinsic_minmax): Likewise
(gfc_conv_intrinsic_minmax_char): Likewise
(gfc_conv_intrinsic_anyall): Likewise
(gfc_conv_intrinsic_arith): Likewise
(gfc_conv_intrinsic_minmaxloc): Likewise
(gfc_conv_intrinsic_minmaxval): Likewise
(gfc_conv_intrinsic_btest): Likewise
(gfc_conv_intrinsic_bitcomp): Likewise
(gfc_conv_intrinsic_shift): Likewise
(gfc_conv_intrinsic_ishft): Likewise
(gfc_conv_intrinsic_ishftc): Likewise
(gfc_conv_intrinsic_leadz): Likewise
(gfc_conv_intrinsic_trailz): Likewise
(gfc_conv_intrinsic_mask): Likewise
(gfc_conv_intrinsic_spacing): Likewise
(gfc_conv_intrinsic_rrspacing): Likewise
(gfc_conv_intrinsic_size): Likewise
(gfc_conv_intrinsic_sizeof): Likewise
(gfc_conv_intrinsic_transfer): Likewise
(gfc_conv_allocated): Likewise
(gfc_conv_associated): Likewise
(gfc_conv_same_type_as): Likewise
(gfc_conv_intrinsic_trim): Likewise
(gfc_conv_intrinsic_repeat): Likewise
(conv_isocbinding_function): Likewise
(conv_intrinsic_ieee_is_normal): Likewise
(conv_intrinsic_ieee_is_negative): Likewise
(conv_intrinsic_ieee_copy_sign): Likewise
(conv_intrinsic_move_alloc): Likewise
* trans-io.c (set_parameter_value_chk): Likewise
(set_parameter_value_inquire): Likewise
(set_string): Likewise
* trans-openmp.c (gfc_walk_alloc_comps): Likewise
(gfc_omp_clause_default_ctor): Likewise
(gfc_omp_clause_copy_ctor): Likewise
(gfc_omp_clause_assign_op): Likewise
(gfc_omp_clause_dtor): Likewise
(gfc_omp_finish_clause): Likewise
(gfc_trans_omp_clauses): Likewise
(gfc_trans_omp_do): Likewise
* trans-stmt.c (gfc_trans_goto): Likewise
(gfc_trans_sync): Likewise
(gfc_trans_arithmetic_if): Likewise
(gfc_trans_simple_do): Likewise
(gfc_trans_do): Likewise
(gfc_trans_forall_loop): Likewise
(gfc_trans_where_2): Likewise
(gfc_trans_allocate): Likewise
(gfc_trans_deallocate): Likewise
* trans-types.c (gfc_init_types): Initialize logical_type_node and
its true/false trees.
(gfc_get_array_descr_info): Use logical_type_node.
* trans-types.h (logical_type_node): New tree.
(logical_true_node): Likewise.
(logical_false_node): Likewise.
* trans.c (gfc_trans_runtime_check): Use logical_type_node.
(gfc_call_malloc): Likewise
(gfc_allocate_using_malloc): Likewise
(gfc_allocate_allocatable): Likewise
(gfc_add_comp_finalizer_call): Likewise
(gfc_add_finalizer_call): Likewise
(gfc_deallocate_with_status): Likewise
(gfc_deallocate_scalar_with_status): Likewise
(gfc_call_realloc): Likewise
gcc/testsuite/ChangeLog:
2017-11-08 Janne Blomqvist <jb@gcc.gnu.org>
PR 82869
* gfortran.dg/logical_temp_io.f90: New test.
* gfortran.dg/logical_temp_io_kind8.f90: New test.
From-SVN: r254526
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2017-11-08 Martin Liska <mliska@suse.cz>
* gcc.dg/tree-ssa/vrp101.c: Update expected pattern as
frequencies are not longer printed in dump output.
From-SVN: r254525
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2017-11-08 Martin Liska <mliska@suse.cz>
* gimplify.c (expand_FALLTHROUGH_r): Simplify usage
of gimple_call_internal_p.
From-SVN: r254524
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From-SVN: r254523
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* g++.old-deja/g++.brendan/asm-extn1.C: Accept all sparc* targets.
(main): Add return type.
From-SVN: r254522
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2017-11-07 Tom de Vries <tom@codesourcery.com>
* config/mips/mips.h (ASM_OUTPUT_LABELREF): Wrap in "do {} while (0)".
From-SVN: r254521
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2017-11-07 Tom de Vries <tom@codesourcery.com>
* config/mips/mips.h (ASM_OUTPUT_CASE_END): Remove semicolon after
"do {} while (0)".
From-SVN: r254520
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2017-11-08 Martin Liska <mliska@suse.cz>
PR sanitizer/82792
* gimplify.c (expand_FALLTHROUGH_r): Skip IFN_ASAN_MARK.
2017-11-08 Martin Liska <mliska@suse.cz>
PR sanitizer/82792
* g++.dg/asan/pr82792.C: New test.
From-SVN: r254519
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From-SVN: r254516
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From-SVN: r254513
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https://gcc.gnu.org/ml/gcc-patches/2017-11/msg00498.html
2017-11-07 Boris Kolpackov <boris@codesynthesis.com>
* Make-lang.in (CP_PLUGIN_HEADERS): Add operators.def since included
in cp-tree.h.
From-SVN: r254512
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PR c++/82835
* cp-gimplify.c (cxx_omp_clause_apply_fn): For methods pass i - 1 to
convert_default_arg instead of i.
* testsuite/libgomp.c++/pr82835.C: New test.
From-SVN: r254511
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PR target/82855
* config/i386/i386.md (SWI1248_AVX512BWDQ2_64): New mode iterator.
(*cmp<mode>_ccz_1): New insn with $k alternative.
* gcc.target/i386/avx512dq-pr82855.c: New test.
From-SVN: r254510
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PR target/82855
* config/i386/i386.c (ix86_swap_binary_operands_p): Treat
RTX_COMM_COMPARE as commutative as well.
(ix86_binary_operator_ok): Formatting fix.
* config/i386/sse.md (*mul<mode>3<mask_name><round_name>,
*<code><mode>3<mask_name><round_saeonly_name>,
*<code><mode>3<mask_name>, *<code>tf3, *mul<mode>3<mask_name>,
*<s>mul<mode>3_highpart<mask_name>,
*vec_widen_umult_even_v16si<mask_name>,
*vec_widen_umult_even_v8si<mask_name>,
*vec_widen_umult_even_v4si<mask_name>,
*vec_widen_smult_even_v16si<mask_name>,
*vec_widen_smult_even_v8si<mask_name>, *sse4_1_mulv2siv2di3<mask_name>,
*avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
*avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
*sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
*sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
<avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
*sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
*<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
!(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
ix86_binary_operator_ok. Formatting fixes.
(*<plusminus_insn><mode>3<mask_name><round_name>,
*<plusminus_insn><mode>3, *<plusminus_insn><mode>3_m): Formatting
fixes.
From-SVN: r254509
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We currently generate (sometimes pretty long) sequences of integer
insns to implement the various cstore patterns. If the CPU has a fast
isel, we can use that at the same latency as of just two integer insns
(you also get a load immediate of 1, and sometimes one of 0 as well,
but those are not in the critical path: they don't depend on any other
instruction).
There are a few patterns that already are implemented with just two
instructions; so don't use isel in that case (I still need to check
all lt/gt/ltu/gtu/le/leu/ge/geu patterns with all SI/DI combinations,
one or two might be better without isel).
This introduces a new GPR2 mode iterator, for those patterns that use
two independent integer modes.
* config/rs6000/rs6000.md (GPR2): New mode_iterator.
("cstore<mode>4"): Don't always expand with rs6000_emit_int_cmove for
eq and ne if TARGET_ISEL.
(cmp): New code_iterator.
(UNS, UNSU_, UNSIK): New code_attrs.
(<code><GPR:mode><GPR2:mode>2_isel): New define_insn_and_split.
("eq<mode>3"): New define_expand, rename the define_insn_and_split
to...
("eq<mode>3"): ... this.
("ne<mode>3"): New define_expand, rename the define_insn_and_split
to...
("ne<mode>3"): ... this.
From-SVN: r254508
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gcc/
PR target/82812
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag.
(ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags.
* config/i386/i386-c.c (ix86_target_macros_internal): Ditto.
* config/i386/i386.opt: Ditto.
* config/i386/i386.c (ix86_target_string): Ditto.
(ix86_option_override_internal): Ditto.
(ix86_init_mpx_builtins): Move MPX to args2.
(ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineinvqb_v64qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v32qi,
__builtin_ia32_vgf2p8affineinvqb_v32qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array.
From-SVN: r254507
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PR target/80425
* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
(zero-extendsidi peephole2): Remove peephole.
testsuite/ChangeLog:
PR target/80425
* gcc.target/i386/pr80425-3.c: New test.
From-SVN: r254505
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Nested functions are named "outerfunc.$nestedN", where N is a
number. nested_function_num extracts that number. The name is
first passed to unpack_hidden_name, which handles the "." and
should result "$nestedN". Don't expect the "." again.
This fixes assertion failure when escape analysis is enabled
and -fgo-debug-escape is on. The failure looks
go1: internal compiler error: in nested_function_num, at go/gofrontend/names.cc:241
0x7bd7d3 Gogo::nested_function_num(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)
Reviewed-on: https://go-review.googlesource.com/76213
From-SVN: r254504
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PR c/53037
* stor-layout.c: Include attribs.h.
(handle_warn_if_not_align): Replace test on TYPE_USER_ALIGN with
explicit lookup of "aligned" attribute.
From-SVN: r254503
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From-SVN: r254502
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Without this we aren't getting proper memcpy inlining on RISC-V systems,
which is particularly disastrous for Dhrystone performance on RV32IM
systems.
gcc/ChangeLog
2017-11-07 Andrew Waterman <andrew@sifive.com>
* config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New
prototype.
(riscv_expand_block_move): Likewise.
gcc/config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
implementation.
(RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER): New define.
(RISCV_MAX_MOVE_BYTES_STRAIGHT): New define.
gcc/config/riscv/riscv.c (riscv_block_move_straight): New
function.
(riscv_adjust_block_mem): Likewise.
(riscv_block_move_loop): Likewise.
(riscv_expand_block_move): Likewise.
gcc/config/riscv/riscv.md (movmemsi): New pattern.
From-SVN: r254501
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Use no suffix at all in the musl dynamic linker name for hard
float ABI. Use -sf and -sp suffixes in musl dynamic linker name
for soft float and single precision ABIs. The following table
outlines the musl interpreter names for the RISC-V ABI names.
musl interpreter | RISC-V ABI
----------------------- | -------------
ld-musl-riscv32.so.1 | riscv32-ilp32d
ld-musl-riscv64.so.1 | riscv64-lp64d
ld-musl-riscv32-sf.so.1 | riscv32-ilp32
ld-musl-riscv64-sf.so.1 | riscv64-lp64
ld-musl-riscv32-sp.so.1 | riscv32-ilp32f
ld-musl-riscv64-sp.so.1 | riscv64-lp64f
gcc/ChangeLog
2017-11-06 Michael Clark <michaeljclark@mac.com>
* config/riscv/linux.h (MUSL_ABI_SUFFIX): New define.
(MUSL_DYNAMIC_LINKER): Likewise.
From-SVN: r254500
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Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs. This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc). But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.
This patch makes the expanders use aarch64_reg_or_imm instead.
2017-11-07 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
nonmmory_operand.
From-SVN: r254499
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2017-11-07 Richard Biener <rguenther@suse.de>
* match.pd: Fix build.
From-SVN: r254498
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Canonicalize x / (- y) into (-x) / y.
This moves negates out of the RHS of a division in order to
allow further simplifications and potentially more reciprocal CSEs.
2017-11-07 Wilco Dijkstra <wdijkstr@arm.com>
Jackson Woodruff <jackson.woodruff@arm.com>
gcc/
PR tree-optimization/71026
* match.pd: Canonicalize negate in division.
testsuite/
PR 71026/tree-optimization/71026
* gcc.dg/div_neg: New test.
From-SVN: r254497
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Currently the code A << (B - C) is not simplified.
However at least a more specific case of 1U << (C -x) where
C = precision(type) - 1 can be simplified to (1 << C) >> x.
This is done by adding a new simplification rule in match.pd.
2017-11-07 Sudakshina Das <sudi.das@arm.com>
gcc/
PR middle-end/80131
* match.pd: Simplify 1 << (C - x) where C = precision (x) - 1.
testsuite/
PR middle-end/80131
* testsuite/gcc.dg/pr80131-1.c: New Test.
From-SVN: r254496
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2017-11-07 Marc Glisse <marc.glisse@inria.fr>
gcc/
* match.pd ((a&~b)|(a^b),(a&~b)^~a,(a|b)&~(a^b),a|~(a^b),
(a|b)|(a&^b),(a&b)|~(a^b),~(~a&b),~X^Y): New transformations.
gcc/testsuite/
* gcc.dg/tree-ssa/bitops-1.c: New file.
From-SVN: r254495
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gcc/ChangeLog:
2017-11-07 Marc Glisse <marc.glisse@inria.fr>
* fold-const.c (negate_expr_p) [PLUS_EXPR, MINUS_EXPR]: Handle
non-scalar integral types.
* match.pd (negate_expr_p): Handle MINUS_EXPR.
(-(A-B), -(~A)): New transformations.
gcc/testsuite/ChangeLog:
2017-11-07 Marc Glisse <marc.glisse@inria.fr>
* gcc.dg/tree-ssa/negminus.c: New test.
From-SVN: r254494
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SUBTARGET_OVERRIDE_OPTIONS
2017-11-07 Tom de Vries <tom@codesourcery.com>
* config/powerpcspe/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove
semicolon after "do {} while (0)".
* config/powerpcspe/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
From-SVN: r254493
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2017-11-07 Tom de Vries <tom@codesourcery.com>
* config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove semicolon
after "do {} while (0)".
* config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
From-SVN: r254492
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2017-11-07 Tom de Vries <tom@codesourcery.com>
PR other/82784
* config/arm/arm.c (HANDLE_NARROW_SHIFT_ARITH): Remove semicolon after
"while {} do (0)".
(arm_rtx_costs_internal): Add missing semicolon after
HANDLE_NARROW_SHIFT_ARITH call.
From-SVN: r254490
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* typeck2.c (build_m_component_ref): Also accept in lower stds with
a pedwarn.
From-SVN: r254487
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We want to actually use isel, so we shouldn't disable it. It is
already not set by default on CPUs that don't have it, or where we
do not want to use it.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
disable isel if it was not set explicitly.
From-SVN: r254485
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FT32 makes use of multiple address spaces. When trying to inspect
objects in GDB, GDB was treating them as a straight "const". The cause
seems to be in GCC DWARF2 output.
This output is handled in gcc/gcc/dwarf2out.c, where modified_type_die()
checks that TYPE has qualifiers CV_QUALS. However while TYPE has
ADDR_SPACE qualifiers, the modified_type_die() explicitly discards the
ADDR_SPACE qualifiers.
This patch retains the ADDR_SPACE qualifiers as modified_type_die()
outputs the DWARF type tree. This allows the types to match, and correct
type information for the object is emitted.
[gcc]
2017-11-06 James Bowman <james.bowman@ftdichip.com>
* gcc/dwarf2out.c (modified_type_die): Retain ADDR_SPACE
qualifiers.
(add_type_attribute) likewise.
From-SVN: r254484
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From-SVN: r254483
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When there is no need to make a copy of ix86_frame, we can use reference
of struct ix86_frame to avoid copy.
Tested on x86-64.
* config/i386/i386.c (ix86_can_use_return_insn_p): Use reference
of struct ix86_frame.
(ix86_initial_elimination_offset): Likewise.
(ix86_expand_split_stack_prologue): Likewise.
From-SVN: r254480
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* gcc.target/i386/stack-check-12.c: Revert to initial version. Then..
Add -fomit-frame-pointer.
From-SVN: r254479
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2017-11-06 Marc Glisse <marc.glisse@inria.fr>
* tree-vrp.h (enum value_range_type): Update stale comment.
From-SVN: r254478
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Currently the runtime is hard-coded to non-escape in various places.
Don't run escape analysis for runtime.
Reviewed-on: https://go-review.googlesource.com/76210
From-SVN: r254476
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"make check" runs make recursively to check each package. Pass
the flags through. So it is possible to run "make check" with
different settings easily.
Reviewed-on: https://go-review.googlesource.com/76029
From-SVN: r254475
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This patch passes the number of units to aarch64_expand_vec_perm
and aarch64_expand_vec_perm_const, which avoids a to_constant ()
once GET_MODE_NUNITS is variable.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Take the number of units too.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Likewise.
* config/aarch64/aarch64-simd.md (vec_perm_const<mode>)
(vec_perm<mode>): Update accordingly.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254469
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This patch passes the number of units to aarch64_simd_vect_par_cnst_half,
which avoids a to_constant () once GET_MODE_NUNITS is variable.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half):
Take the number of units too.
* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise.
(aarch64_simd_check_vect_par_cnst_half): Update call accordingly,
but check for a vector mode before rather than after the call.
* config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>)
(move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>)
(vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>)
(vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>)
(vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>)
(aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3)
(widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>)
(aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>)
(aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>)
(aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>)
(aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>)
(aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>)
(aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>)
(aarch64_sqdmull2_n<mode>): Update accordingly.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254468
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This patch passes the number of units to aarch64_reverse_mask,
which avoids a to_constant () once GET_MODE_NUNITS is variable.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take
the number of units too.
* config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise.
* config/aarch64/aarch64-simd.md (vec_load_lanesoi<mode>)
(vec_store_lanesoi<mode>, vec_load_lanesci<mode>)
(vec_store_lanesci<mode>, vec_load_lanesxi<mode>)
(vec_store_lanesxi<mode>): Update accordingly.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254467
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Later patches turn the number of vector units into a poly_int.
We deliberately don't support applying GEN_INT to those (except
in target code that doesn't distinguish between poly_ints and normal
constants); gen_int_mode needs to be used instead.
This patch therefore replaces instances of:
GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])))
with uses of a new endian_lane_rtx function.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_endian_lane_rtx): Declare.
* config/aarch64/aarch64.c (aarch64_endian_lane_rtx): New function.
* config/aarch64/aarch64.h (ENDIAN_LANE_N): Take the number
of units rather than the mode.
* config/aarch64/iterators.md (nunits): New mode attribute.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
Use aarch64_endian_lane_rtx instead of GEN_INT (ENDIAN_LANE_N ...).
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
(aarch64_dup_lane_<vswap_width_name><mode>, *aarch64_mul3_elt<mode>)
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_64v2df, *aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>, *aarch64_mls_elt<mode>)
(*aarch64_mls_elt_<vswap_width_name><mode>, *aarch64_fma4_elt<mode>)
(*aarch64_fma4_elt_<vswap_width_name><mode>):: Likewise.
(*aarch64_fma4_elt_to_64v2df, *aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fnma4_elt_to_64v2df, reduc_plus_scal_<mode>): Likewise.
(reduc_plus_scal_v4sf, reduc_<maxmin_uns>_scal_<mode>): Likewise.
(reduc_<maxmin_uns>_scal_<mode>): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>, *aarch64_mulx_elt_<vswap_width_name><mode>)
(*aarch64_mulx_elt<mode>, *aarch64_vgetfmulx<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>, aarch64_sq<r>dmulh_laneq<mode>)
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
(aarch64_vec_store_lanesoi_lane<mode>): Likewise.
(aarch64_vec_load_lanesci_lane<mode>): Likewise.
(aarch64_vec_store_lanesci_lane<mode>): Likewise.
(aarch64_vec_load_lanesxi_lane<mode>): Likewise.
(aarch64_vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_simd_vec_set<mode>): Update use of ENDIAN_LANE_N.
(aarch64_simd_vec_setv2di): Likewise.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254466
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