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2019-08-11d: Fix ICE: gimplification failed (gimplify.c at 13436)Iain Buclaw4-1/+33
The expression that caused the ICE ++(a += 1.0); The D front-end rewrites and applies implicit type conversions so the expression gets simplified as (int)((double) a += 1.0) += 1 The codegen pass would subsequently generate the following invalid code (int)(double) a = (int)((double) a + 1.0) + 1 The LHS expression `(int)(double) a', represented as a FIX_TRUNC_EXPR being what trips as it is not a valid lvalue for assignment. While LHS casts are stripped away, convert_expr adds a double cast because it converts the expression to its original type before converting it to its target type. There is no valid reason why this is done, so it has been removed. gcc/d/ChangeLog: PR d/90601 * d-convert.cc (convert_expr): Don't convert an expression to its original front-end type before converting to its target type. gcc/testsuite/ChangeLog: PR d/90601 * gdc.dg/pr90601.d: New test. From-SVN: r274263
2019-08-11Correct a single misfire in previous ChangeLog cleanup.Hans-Peter Nilsson1-1/+1
From-SVN: r274262
2019-08-11Daily bump.GCC Administrator1-1/+1
From-SVN: r274261
2019-08-10decl.c (match_old_style_init): Use a clearer error message.Steven G. Kargl15-70/+185
2019-08-10 Steven G. Kargl <kargl@gcc.gnu.org> * decl.c (match_old_style_init): Use a clearer error message. * expr.c (gfc_check_assign): Update BOZ checking to provide a stricter adherence to the Fortran standard. Use gfc_invalid_boz () to relax errors into warnings. * gfortran.h (gfc_isym_id): Add new ids GFC_ISYM_DFLOAT, GFC_ISYM_FLOAT, GFC_ISYM_REALPART, and GFC_ISYM_SNGL * intrinsic.c (add_functions): Use new ids to split REAL generic into REAL, FLOAT, DFLOAT, SNGL, and REALPART generics. (gfc_intrinsic_func_interface): Allow new intrinsics in an initialization expression * resolve.c (resolve_operator): Deal with BOZ as operands. Use gfc_invalid_boz to allow for errors or warnings via the -fallow-invalid-boz option. A BOZ cannot be an operand to an unary operator. Both operands of a binary operator cannot be BOZ. For binary operators, convert a BOZ operand into the type and kind of the other operand for REAL or INTEGER operand. * trans-intrinsic.c: Use new ids to cause conversions to happen. 2019-08-10 Steven G. Kargl <kargl@gcc.gnu.org> * gfortran.dg/boz_8.f90: Adjust error messages. * gfortran.dg/nan_4.f90: Ditto. * gfortran.dg/boz_1.f90: Add -fallow-invalid-boz to dg-options, and test for warnings. * gfortran.dg/boz_3.f90: Ditto. * gfortran.dg/boz_4.f90: Ditto. * gfortran.dg/dec_structure_6.f90: Ditto. * gfortran.dg/ibits.f90: Ditto. From-SVN: r274257
2019-08-10d: Fix internal compiler error: in add_expr, at tree.c:7794Iain Buclaw4-3/+34
gcc/d/ChangeLog: PR d/91238 * d-codegen.cc (build_address): If taking the address of a CALL_EXPR, wrap it in a TARGET_EXPR. gcc/testsuite/ChangeLog: PR d/91238 * gdc.dg/pr91238.d: New test. From-SVN: r274253
2019-08-10tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DEVICE_TYPE.Jakub Jelinek16-13/+306
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DEVICE_TYPE. (enum omp_clause_device_type_kind): New enum. (struct tree_omp_clause): Add subcode.device_type_kind. * tree.h (OMP_CLAUSE_DEVICE_TYPE_KIND): Define. * tree.c (omp_clause_num_ops, omp_clause_code_name): Add entries for device_type clause. (walk_tree_1): Handle OMP_CLAUSE_DEVICE_TYPE. * tree-pretty-print.c (dump_omp_clause): Likewise. c-family/ * c-pragma.h (enum pragma_omp_clause): Add PRAGMA_OMP_CLAUSE_DEVICE_TYPE. c/ * c-parser.c (c_parser_omp_clause_name): Parse device_type. (c_parser_omp_clause_device_type): New function. (c_parser_omp_all_clauses): Handle PRAGMA_OMP_CLAUSE_DEVICE_TYPE. (OMP_DECLARE_TARGET_CLAUSE_MASK): Add PRAGMA_OMP_CLAUSE_DEVICE_TYPE. (c_parser_omp_declare_target): Handle device_type clauses. Remove diagnostics for declare target with clauses nested in clause-less declare target declaration-definition-seq. * c-typeck.c (c_finish_omp_clauses): Handle OMP_CLAUSE_DEVICE_TYPE. cp/ * parser.c (cp_parser_omp_clause_name): Parse device_type. (cp_parser_omp_clause_device_type): New function. (cp_parser_omp_all_clauses): Handle PRAGMA_OMP_CLAUSE_DEVICE_TYPE. (OMP_DECLARE_TARGET_CLAUSE_MASK): Add PRAGMA_OMP_CLAUSE_DEVICE_TYPE. (cp_parser_omp_declare_target): Handle device_type clauses. Remove diagnostics for declare target with clauses nested in clause-less declare target declaration-definition-seq. * semantics.c (finish_omp_clauses): Handle OMP_CLAUSE_DEVICE_TYPE. testsuite/ * c-c++-common/gomp/declare-target-2.c: Don't expect error for declare target with clauses in between declare target without clauses and end declare target. * c-c++-common/gomp/declare-target-4.c: New test. From-SVN: r274252
2019-08-10re PR target/91408 (ICE in extract_insn, at recog.c:2310 since r273981)Jakub Jelinek4-2/+42
PR target/91408 * config/i386/mmx.md (usadv8qi): Use register_operand instead of vector_operand. * gcc.target/i386/pr91408.c: New test. From-SVN: r274251
2019-08-10Assorted ChangeLog cleanups.Jakub Jelinek15-642/+661
From-SVN: r274250
2019-08-10Fix ODR violation in d/runtime.ccIain Buclaw2-4/+12
gcc/d/ChangeLog: PR d/90893 * runtime.cc (enum libcall_type): Rename to... (enum d_libcall_type): ...this. (get_libcall_type): Use d_libcall_type. (build_libcall_decl): Likewise. From-SVN: r274249
2019-08-10Daily bump.GCC Administrator1-1/+1
From-SVN: r274248
2019-08-09* uk.po: Update.Joseph Myers2-48/+52
From-SVN: r274241
2019-08-09reload1.c (finish_spills): Do not check ira_conflicts_p when handling ↵Vladimir Makarov2-6/+6
spilled pseudos. * reload1.c (finish_spills): Do not check ira_conflicts_p when handling spilled pseudos. From-SVN: r274240
2019-08-09rs6000: vec-rotate-*.c fixesSegher Boessenkool5-2/+13
This fixes two minor problems with the new testcases. The first is that almost all other tests, including all vec* tests, for powerpc use names with dashes, not underscores. The more important one is the the vec-rotate-1.c and vec-rotate-3.c tests need the -maltivec flag. gcc/testsuite/ * gcc.target/powerpc/vec_rotate-1.c: Rename to ... * gcc.target/powerpc/vec-rotate-1.c: ... this. Add -maltivec option. * gcc.target/powerpc/vec_rotate-2.c: Rename to ... * gcc.target/powerpc/vec-rotate-2.c: ... this. * gcc.target/powerpc/vec_rotate-3.c: Rename to ... * gcc.target/powerpc/vec-rotate-3.c: ... this. Add -maltivec option. * gcc.target/powerpc/vec_rotate-4.c: Rename to ... * gcc.target/powerpc/vec-rotate-4.c: ... this. From-SVN: r274239
2019-08-09[aarch64] PR target/91386 Use copy_rtx to avoid modifying original insns in ↵Richard Earnshaw2-9/+17
peep2 pattern PR target/91386 is a situation where a peephole2 pattern substitution is discarded late because the selected instructions contain frame-related notes that we cannot redistribute (because the pattern has more than one insn in the output). Unfortunately, the original insns were being modified during the generation, so after the undo we are left with corrupt RTL. We avoid this by ensuring that the modifications are always made on a copy, so that the original insns are never changed. PR target/91386 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Use copy_rtx to preserve the contents of the original insns. From-SVN: r274238
2019-08-09[arm] Recognize thumb2 16-bit variants of the add and compare instructionsRichard Earnshaw2-8/+27
The addsi3_compare_op[12] patterns currently only have constraints to pick the 32-bit variants of the instructions. Although the assembler may sometimes opportunistically match a 16-bit t2 instruction, there's no real control over that within the compiler. Consequently we might emit a 32-bit adds instruction with a 16-bit subs instruction would serve equally well. We do, of course still have to be careful about the small number of boundary cases by controlling the order quite carefully. This patch adds the constraints and templates to match the t2 16-bit variants of these instructions. Now, for example, we can generate subs r0, r0, #1 // 16-bit instruction instead of adds r0, r0, #1 // 32-bit instruction. *confit/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants. (addsi3_compare_op2): Likewise. From-SVN: r274237
2019-08-09[PATCH][GCC][AARCH64] Add effective-target check to b key execution testsSam Tebbs4-0/+20
gcc/testsuite 2019-08-09 Sam Tebbs<sam.tebbs@arm.com> * lib/target-supports.exp (check_effective_target_arm_v8_4a_bkey_directive): New proc. * g++.target/aarch64/return_address_sign_b_exception.C, return_address_sign_ab_exception.C: Add dg-require-effective-target checks. From-SVN: r274236
2019-08-09Strengthen alias_ptr_types_compatible_p in LTO mode.Martin Liska2-2/+15
2019-08-09 Martin Liska <mliska@suse.cz> * alias.c (alias_ptr_types_compatible_p): Strengten type comparison in LTO mode. From-SVN: r274235
2019-08-09Reject tail calls that read from an escaped RESULT_DECL (PR90313)Richard Sandiford4-0/+73
In this PR we have two return paths from a function "map". The common code sets <result> to the value returned by one path, while the other path does: <retval> = map (&<retval>, ...); We treated this call as tail recursion, losing the copy semantics on the value returned by the recursive call. We'd correctly reject the same thing for variables: local = map (&local, ...); The problem is that RESULT_DECLs didn't get the same treatment. 2019-08-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR middle-end/90313 * tree-tailcall.c (find_tail_calls): Reject calls that might read from an escaped RESULT_DECL. gcc/testsuite/ PR middle-end/90313 * g++.dg/torture/pr90313.cc: New test. From-SVN: r274234
2019-08-09Add -flto=auto option value.Martin Liska6-13/+25
2019-08-09 Martin Liska <mliska@suse.cz> * doc/invoke.texi: Document the option value. * lto-wrapper.c (run_gcc): Set auto_parallel only with -flto=auto. 2019-08-09 Martin Liska <mliska@suse.cz> * g++.dg/lto/devirt-19_0.C: Add -flto=auto. From-SVN: r274232
2019-08-09Provide proper error message for -flto=abcd.Martin Liska4-0/+20
2019-08-09 Martin Liska <mliska@suse.cz> * opts.c (common_handle_option): Error for an invalid argument to -flto=. 2019-08-09 Martin Liska <mliska@suse.cz> * gcc.dg/spellcheck-options-21.c: New test. From-SVN: r274231
2019-08-09Implement -fopt-info support for IPA ICF.Martin Liska33-124/+185
2019-08-09 Martin Liska <mliska@suse.cz> * ipa-icf.c (sem_function::merge): Define AUTO_DUMP_SCOPE and use dump_printf to report optimization. (sem_variable::merge): Likwise. (sem_item_optimizer::merge_classes): Use dump_printf to report ICF hits. 2019-08-09 Martin Liska <mliska@suse.cz> * g++.dg/ipa/ipa-icf-2.C: Add -optimized to -fdump-ipa-icf. * g++.dg/ipa/ipa-icf-3.C: Likewise. * g++.dg/ipa/ipa-icf-4.C: Likewise. * g++.dg/ipa/ipa-icf-6.C: Likewise. * gcc.dg/ipa/ipa-icf-1.c: Likewise. * gcc.dg/ipa/ipa-icf-10.c: Likewise. * gcc.dg/ipa/ipa-icf-11.c: Likewise. * gcc.dg/ipa/ipa-icf-12.c: Likewise. * gcc.dg/ipa/ipa-icf-13.c: Likewise. * gcc.dg/ipa/ipa-icf-16.c: Likewise. * gcc.dg/ipa/ipa-icf-18.c: Likewise. * gcc.dg/ipa/ipa-icf-2.c: Likewise. * gcc.dg/ipa/ipa-icf-20.c: Likewise. * gcc.dg/ipa/ipa-icf-21.c: Likewise. * gcc.dg/ipa/ipa-icf-23.c: Likewise. * gcc.dg/ipa/ipa-icf-25.c: Likewise. * gcc.dg/ipa/ipa-icf-26.c: Likewise. * gcc.dg/ipa/ipa-icf-27.c: Likewise. * gcc.dg/ipa/ipa-icf-3.c: Likewise. * gcc.dg/ipa/ipa-icf-35.c: Likewise. * gcc.dg/ipa/ipa-icf-36.c: Likewise. * gcc.dg/ipa/ipa-icf-37.c: Likewise. * gcc.dg/ipa/ipa-icf-38.c: Likewise. * gcc.dg/ipa/ipa-icf-39.c: Likewise. * gcc.dg/ipa/ipa-icf-5.c: Likewise. * gcc.dg/ipa/ipa-icf-7.c: Likewise. * gcc.dg/ipa/ipa-icf-8.c: Likewise. * gcc.dg/ipa/ipa-icf-merge-1.c: Likewise. * gcc.dg/ipa/pr64307.c: Likewise. * gcc.dg/ipa/pr90555.c: Likewise. From-SVN: r274230
2019-08-09Port value profiling to -fopt-info infrastructure.Martin Liska16-67/+91
2019-08-09 Martin Liska <mliska@suse.cz> * value-prof.c (gimple_divmod_fixed_value_transform): Use dump_printf_loc. (gimple_mod_pow2_value_transform): Likewise. (gimple_mod_subtract_transform): Likewise. (init_node_map): Likewise. (gimple_ic_transform): Likewise. (gimple_stringops_transform): Likewise. 2019-08-09 Martin Liska <mliska@suse.cz> * g++.dg/tree-prof/indir-call-prof.C: Add -optimize to -fdump-ipa-profile. * g++.dg/tree-prof/morefunc.C: Likewise. * g++.dg/tree-prof/reorder.C: Likewise. * gcc.dg/tree-prof/ic-misattribution-1.c: Likewise. * gcc.dg/tree-prof/indir-call-prof.c: Likewise. * gcc.dg/tree-prof/stringop-1.c: Likewise. * gcc.dg/tree-prof/stringop-2.c: Likewise. * gcc.dg/tree-prof/val-prof-1.c: Likewise. * gcc.dg/tree-prof/val-prof-2.c: Likewise. * gcc.dg/tree-prof/val-prof-3.c: Likewise. * gcc.dg/tree-prof/val-prof-4.c: Likewise. * gcc.dg/tree-prof/val-prof-5.c: Likewise. * gcc.dg/tree-prof/val-prof-7.c: Likewise. From-SVN: r274229
2019-08-09c-parser.c (check_no_duplicate_clause): Simplify using omp_find_clause.Jakub Jelinek7-21/+305
c/ * c-parser.c (check_no_duplicate_clause): Simplify using omp_find_clause. (c_parser_omp_clause_if): Fix up printing of target {enter,exit} data directive name modifiers. (c_parser_omp_clause_proc_bind): Check for duplicate proc_bind clause. cp/ * parser.c (check_no_duplicate_clause): Simplify using omp_find_clause. (cp_parser_omp_clause_if): Fix up printing of target {enter,exit} data directive name modifiers. testsuite/ * c-c++-common/gomp/if-4.c: New test. * c-c++-common/gomp/clause-dups-1.c: New test. From-SVN: r274227
2019-08-09re PR c/91401 (schedule + dist_schedule clauses rejected on distribute ↵Jakub Jelinek7-3/+53
parallel for) PR c/91401 c/ * c-parser.c (c_parser_omp_clause_dist_schedule): Fix up typos in the check_no_duplicate_clause call. Comment it out, instead emit a warning for duplicate dist_schedule clauses. cp/ * parser.c (cp_parser_omp_clause_dist_schedule): Comment out the check_no_duplicate_clause call, instead emit a warning for duplicate dist_schedule clauses. testsuite/ * c-c++-common/gomp/pr91401-1.c: New test. * c-c++-common/gomp/pr91401-2.c: New test. From-SVN: r274226
2019-08-09use rand instead of randomAlexandre Oliva6-29/+17
rand is in ISO C, whereas random is only in POSIX, so it makes sense to use the more portable function everywhere instead of falling back from one to the other on systems that miss the less portable one. for gcc/testsuite/ChangeLog * gcc.target/i386/sse2-mul-1.c: Use rand. Drop fallback. * gcc.target/i386/sse4_1-blendps-2.c: Likewise. * gcc.target/i386/sse4_1-blendps.c: Likewise. * gcc.target/i386/xop-vshift-1.c: Likewise. * gcc.target/powerpc/direct-move.h: Likewise. From-SVN: r274225
2019-08-09Daily bump.GCC Administrator1-1/+1
From-SVN: r274224
2019-08-08decl.c (grokdeclarator): Use id_loc and EXPR_LOCATION in a few error messages.Paolo Carlini9-20/+39
/cp 2019-08-08 Paolo Carlini <paolo.carlini@oracle.com> * decl.c (grokdeclarator): Use id_loc and EXPR_LOCATION in a few error messages. /testsuite 2019-08-08 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/cpp0x/enum20.C: Test location(s) too. * g++.dg/other/friend3.C: Likewise. * g++.dg/parse/dtor5.C: Likewise. * g++.dg/parse/friend7.C: Likewise. * g++.dg/template/error22.C: Likewise. * g++.old-deja/g++.brendan/err-msg5.C: Likewise. From-SVN: r274220
2019-08-08* doc/extend.texi: Add const qualifier to ld intrinsics.Mihailo Stojanovic2-4/+8
From-SVN: r274219
2019-08-08rs6000: Rename DFP iterator and attr to DDTD and qSegher Boessenkool2-67/+70
This is more in line with the other iterators we have, and a bit easier to read and write. * config/rs6000/dfp.md (D64_D128): Rename to ... (DDTD): ... this, throughout. (dfp_suffix): Rename to ... (q): ... this, throughout. From-SVN: r274218
2019-08-08rs6000: Use iterators in more DFP patternsSegher Boessenkool2-99/+58
I noticed some patterns in dfp.md could use the D64_D128 iterator but don't yet. This converts all remaining simple cases. * config/rs6000/dfp.md (D64_D128): Move earlier in the file. (dfp_suffix): Ditto. (adddd3, addtd3): Merge to ... (add<mode>3 for D64_D128): ... this. (subdd3, subtd3): Merge to ... (sub<mode>3 for D64_D128): ... this. (muldd3, multd3): Merge to ... (mul<mode>3 for D64_D128): ... this. (divdd3, divtd3): Merge to ... (div<mode>3 for D64_D128): ... this. (*cmpdd_internal1, *cmptd_internal1): Merge to ... (*cmp<mode>_internal1 for D64_D128): ... this. (ftruncdd2, ftrunctd2): Merge to ... (ftrunc<mode>2 for D64_D128): ... this. (fixdddi2, fixtddi2): Merge to ... (fix<mode>di2 for D64_D128): ... this. From-SVN: r274217
2019-08-08RISC-V: Fix C ABI for flattened struct with 0-length bitfield.Jim Wilson5-16/+113
gcc/ PR target/91229 * config/riscv/riscv.c (riscv_flatten_aggregate_field): New arg ignore_zero_width_bit_field_p. Skip zero size bitfields when true. Pass into recursive call. (riscv_flatten_aggregate_argument): New arg. Pass to riscv_flatten_aggregate_field. (riscv_pass_aggregate_in_fpr_pair_p): New local warned. Call riscv_flatten_aggregate_argument twice, with false and true as last arg. Process result twice. Compare results and warn if different. (riscv_pass_aggregate_in_fpr_and_gpr_p): Likewise. gcc/testsuite/ * gcc.target/riscv/flattened-struct-abi-1.c: New test. * gcc.target/riscv/flattened-struct-abi-2.c: New test. From-SVN: r274215
2019-08-08re PR c++/79520 (Spurious caching for constexpr arguments)Marek Polacek2-0/+16
PR c++/79520 * g++.dg/cpp1y/constexpr-79520.C: New test. From-SVN: r274214
2019-08-08[C] Fix bogus nested enum error messageRichard Sandiford5-1/+42
For: enum a { A }; enum a { B }; we emit a bogus error about nested definitions before the real error: foo.c:2:6: error: nested redefinition of ‘enum a’ 2 | enum a { B }; | ^ foo.c:2:6: error: redeclaration of ‘enum a’ foo.c:1:6: note: originally defined here 1 | enum a { A }; | ^ This is because we weren't clearing C_TYPE_BEING_DEFINED once the definition was over. I think it's OK to clear C_TYPE_BEING_DEFINED even for a definition that actually is nested (and so whose outer definition is still open), since we'll already have given an error by then. It means that second and subsequent attempts to define a nested enum will usually get the redeclaration error instead of the nested error, but that seems just as accurate (nested_first and nested_second in the test). The only exception is if the first nested enum was also invalid by being empty, but then the enum as a whole has already produced two errors (nested_empty in the test). 2019-08-08 Richard Sandiford <richard.sandiford@arm.com> gcc/c/ * c-decl.c (finish_enum): Clear C_TYPE_BEING_DEFINED. gcc/testsuite/ * gcc.dg/pr79983.c (enum E): Don't allow an error about nested definitions. * gcc.dg/enum-redef-1.c: New test. From-SVN: r274213
2019-08-08PR c++/87519 - bogus warning with -Wsign-conversion.Marek Polacek4-2/+27
* typeck.c (cp_build_binary_op): Use same_type_p instead of comparing the types directly. * g++.dg/warn/Wsign-conversion-5.C: New test. From-SVN: r274211
2019-08-08constexpr.c (inline_asm_in_constexpr_error): New.Marek Polacek4-11/+37
* constexpr.c (inline_asm_in_constexpr_error): New. (cxx_eval_constant_expression) <case ASM_EXPR>: Call it. (potential_constant_expression_1) <case ASM_EXPR>: Likewise. * g++.dg/cpp2a/inline-asm3.C: New test. From-SVN: r274210
2019-08-08Fix file descriptor existence of MinGW.Martin Liska3-4/+10
2019-08-08 Martin Liska <mliska@suse.cz> PR bootstrap/91352 * gcc.c (driver::detect_jobserver): Use is_valid_fd. * lto-wrapper.c (jobserver_active_p): Likewise. 2019-08-08 Martin Liska <mliska@suse.cz> PR bootstrap/91352 * libiberty.h (is_valid_fd): New function. 2019-08-08 Martin Liska <mliska@suse.cz> PR bootstrap/91352 * lrealpath.c (is_valid_fd): New function. From-SVN: r274208
2019-08-08When cloning set operator new/delete to false.Martin Liska2-0/+10
2019-08-08 Martin Liska <mliska@suse.cz> * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop IS_OPERATOR_NEW and IS_OPERATOR_DELETE. (create_version_clone_with_body): Likewise. From-SVN: r274207
2019-08-08gimplify.c (omp_add_variable): Use GOVD_PRIVATE | GOVD_EXPLICIT for VLA ↵Jakub Jelinek7-18/+86
helper variables on target data even if... * gimplify.c (omp_add_variable): Use GOVD_PRIVATE | GOVD_EXPLICIT for VLA helper variables on target data even if not GOVD_FIRSTPRIVATE. (gimplify_scan_omp_clauses): For OMP_CLAUSE_USE_DEVICE_* use just GOVD_EXPLICIT flags. (gimplify_omp_workshare): For OMP_TARGET_DATA move all OMP_CLAUSE_USE_DEVICE_* clauses to the end of clauses chain. * omp-low.c (scan_sharing_clauses): For OMP_CLAUSE_USE_DEVICE_* call install_var_field with mask 11 instead of 3. (lower_omp_target): For OMP_CLAUSE_USE_DEVICE_* use pass (splay_tree_key) &DECL_UID (var) to build_sender_ref instead of var. gcc/c/ * c-typeck.c (c_finish_omp_clauses): For C_ORT_OMP OMP_CLAUSE_USE_DEVICE_* clauses use oacc_reduction_head bitmap instead of generic_head to track duplicates. gcc/cp/ * semantics.c (finish_omp_clauses): For C_ORT_OMP OMP_CLAUSE_USE_DEVICE_* clauses use oacc_reduction_head bitmap instead of generic_head to track duplicates. libgomp/ * target.c (gomp_map_vars_internal): For GOMP_MAP_USE_DEVICE_PTR perform the lookup in the first loop only if !not_found_cnt, otherwise perform lookups for it in the second loop guarded with if (not_found_cnt || has_firstprivate). * testsuite/libgomp.c/target-37.c: New test. * testsuite/libgomp.c++/target-22.C: New test. From-SVN: r274206
2019-08-08Daily bump.GCC Administrator1-1/+1
From-SVN: r274205
2019-08-07re PR fortran/91359 (logical function X returns .TRUE. - Warning: spaghetti ↵Steven G. Kargl3-5/+11
code) 2019-08-07 Steven G. Kargl <kargl@gcc.gnu.org> PR fortran/91359 * pr91359_2.f: Fix missing hyphen in dg-do * pr91359_1.f: Ditto. Remove RESULT variable to test actual fix! From-SVN: r274201
2019-08-07re PR c++/67533 (internal compiler error: in build_call_a, at cp/call.c:372)Marek Polacek2-0/+12
PR c++/67533 * g++.dg/tls/thread_local-ice5.C: New test. From-SVN: r274200
2019-08-07[AArch64] Fix INSR for zero floatsRichard Sandiford5-4/+30
We used INSR to handle zero integers but not zero floats. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/constraints.md (Z): Handle floating-point zeros too. * config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/init_13.c: New test. From-SVN: r274193
2019-08-07[AArch64] Prefer FPRs over GPRs for INSRRichard Sandiford4-8/+23
INSR of GPRs involves a cross-file move while INSR of FPRs doesn't. We should therefore disparage the GPR version relative to the FPR version. The patch also adds MOVPRFX handling, but this is only tested properly by the ACLE. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add MOVPRFX alternatives. Make the GPR alternatives more expensive than the FPR ones. gcc/testsuite/ * gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into a temporary FPR. From-SVN: r274192
2019-08-07[AArch64] Prefer FPRs over GPRs for CLASTBRichard Sandiford4-2/+37
This patch makes the SVE CLASTB GPR alternative more expensive than the FPR alternative in order to avoid unnecessary cross-file moves. It also fixes the prefix used to print the FPR; <vw> only handles 32-bit and 64-bit elements. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (fold_extract_last_<mode>): Disparage the GPR alternative relative to the FPR one. Fix handling of 8-bit and 16-bit FPR values. gcc/testsuite/ * gcc.target/aarch64/sve/clastb_8.c: New test. From-SVN: r274191
2019-08-07[AArch64] Merge SVE reduction patternsRichard Sandiford3-61/+75
The reorg showed that we had an unnecessary separation between the bitwise and max/min reductions for integers, and the addition and max/min reductions for fp. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (BITWISEV): Delete. (SVE_INT_REDUCTION, SVE_FP_REDUCTION): New int iterators. (optab): Handle UNSPEC_UMAXV, UNSPEC_UMINV, UNSPEC_SMAXV, UNSPEC_SMINV, UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, UNSPEC_FMINNMV, UNSPEC_FMINV. (bit_reduc_op): Delete. (sve_int_op): New int attribute. (sve_fp_op): Handle UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, UNSPEC_FMINNMV, UNSPEC_FMINV. * config/aarch64/aarch64-sve.md (reduc_<MAXMINV:maxmin_uns>_scal_<SVE_I:mode>) (*reduc_<MAXMINV:maxmin_uns>_scal_<SVE_I:mode>) (reduc_<BITWISEV:optab>_scal_<SVE_I:mode>) (*reduc_<BITWISEV:optab>_scal_<SVE_I:mode>): Merge into... (reduc_<SVE_INT_REDUCTION:optab>_scal_<SVE_I:mode>) (*reduc_<SVE_INT_REDUCTION:optab>_scal_<SVE_I:mode>): ...these new patterns. (reduc_plus_scal_<SVE_F:mode>, *reduc_plus_scal_<SVE_I:mode>) (reduc_<FMAXMINV:optab>_scal_<SVE_F:mode>) (*reduc_<FMAXMINV:optab>_scal_<SVE_F:mode>): Merge into... (reduc_<SVE_FP_REDUCTION:optab>_scal_<SVE_F:mode>) (*reduc_<SVE_FP_REDUCTION:optab>_scal_<SVE_F:mode>): ...these new patterns. From-SVN: r274190
2019-08-07[AArch64] Merge SVE ternary FP operationsRichard Sandiford2-176/+51
This patch combines the four individual fused multiply-add optabs into one pattern and uses unspecs instead of rtx codes. This is part of a series of patches that change the SVE FP patterns so that they can describe cases in which the predicate isn't all-true. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (fma<mode>4, *fma<mode>4) (fnma<mode>4, *fnma<mode>4, fnms<mode>4, *fnms<mode>4) (fms<mode>4, *fms<mode>4): Replace with... (<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4) (*<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4): ...these new patterns. Use unspecs instead of rtx codes. (cond_<optab><mode>, *cond_<optab><mode>_2, *cond_<optab><mode>_4) (*cond_<optab><mode>_any): Add the predicate to SVE_COND_FP_TERNARY. From-SVN: r274189
2019-08-07[AArch64] Merge SVE FMAXNM/FMINNM patternsRichard Sandiford3-36/+37
This patch makes us use the same define_insn for both the smax/smin and fmax/fmin optabs. It also continues the process started by the earlier FP unary patch of moving predicated FP patterns from rtx codes to unspecs. There's no need to handle the FMAX and FMIN instructions until the ACLE patch, since we only use FMAXNM and FMINNM at present. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SVE_COND_FP_MAXMIN_PUBLIC): New int iterator. (maxmin_uns_op): Handle UNSPEC_COND_FMAXNM and UNSPEC_COND_FMINNM. * config/aarch64/aarch64-sve.md (<FMAXMIN:su><FMAXMIN:maxmin><SVE_F:mode>3): Rename to... (<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): ...this and use a single unspec for the rhs. (*<su><maxmin><mode>3): Delete. (<maxmin_uns><SVE_F:mode>3): Use a single unspec for the rhs. From-SVN: r274188
2019-08-07[AArch64] Merge SVE FP unary patternsRichard Sandiford3-60/+78
This patch merges the SVE FP rounding patterns with the other SVE FP unary patterns. At the moment, we only generate unary FP operations for full vectors, so we can use (sqrt:VNx4SF ...) etc. in the rtl pattern. With the ACLE, it's also possible to generate predicated operations on partial vectors without specifying a value for inactive lanes. (sqrt:VNx4SF ...) would then have different faulting behaviour from the instruction that the pattern generates. This patch therefore uses unspecs to represent the operations instead. Later patches make this change for other patterns. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (UNSPEC_COND_FABS, UNSPEC_COND_FNEG) (UNSPEC_COND_FRINTA, UNSPEC_COND_FRINTI, UNSPEC_COND_FRINTM) (UNSPEC_COND_FRINTN, UNSPEC_COND_FRINTP, UNSPEC_COND_FRINTX) (UNSPEC_COND_FRINTZ, UNSPEC_COND_FSQRT): New unspecs. (optab, sve_fp_op): Handle them. (SVE_FP_UNARY): Delete. (optab): Remove sqrt entry. (sve_fp_op): Remove neg, abs and sqrt entries. (SVE_COND_FP_UNARY): New int iterator. * config/aarch64/aarch64-sve.md (<frint_pattern><mode>2) (*<frint_pattern><mode>2): Delete. (<SVE_FP_UNARY:optab><SVE_F:mode>2): Replace with... (<SVE_COND_FP_UNARY:optab><SVE_F:mode>2): ...this. (*<SVE_FP_UNARY:optab><SVE_F:mode>2): Replace with... (*<SVE_COND_FP_UNARY:optab><SVE_F:mode>2): ...this. From-SVN: r274187
2019-08-07[AArch64] Remove redundant SVE FADDA patternRichard Sandiford2-15/+4
*pred_fold_left_plus_<mode> could no longer match anything, since UNSPEC_FADDA now takes three operands. Predicated FADDAs should now go through mask_fold_left_plus_<mode> instead. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete. From-SVN: r274186
2019-08-07[AArch64] Make SVE UNSPEC_COND_*s match the insn mnemonicRichard Sandiford3-51/+87
This patch makes the UNSPEC_COND* names match the instruction mnemonics, rather than having the previous mixture in which some used instructions while others used operator names. 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (UNSPEC_COND_ADD): Rename to... (UNSPEC_COND_FADD): ...this. (UNSPEC_COND_SUB): Rename to... (UNSPEC_COND_FSUB): ...this. (UNSPEC_COND_MUL): Rename to... (UNSPEC_COND_FMUL): ...this. (UNSPEC_COND_DIV): Rename to... (UNSPEC_COND_FDIV): ...this. (UNSPEC_COND_MAX): Rename to... (UNSPEC_COND_FMAXNM): ...this. (UNSPEC_COND_MIN): Rename to... (UNSPEC_COND_FMINNM): ...this. (UNSPEC_COND_LT): Rename to... (UNSPEC_COND_FCMLT): ...this. (UNSPEC_COND_LE): Rename to... (UNSPEC_COND_FCMLE): ...this. (UNSPEC_COND_EQ): Rename to... (UNSPEC_COND_FCMEQ): ...this. (UNSPEC_COND_NE): Rename to... (UNSPEC_COND_FCMNE): ...this. (UNSPEC_COND_GE): Rename to... (UNSPEC_COND_FCMGE): ...this. (UNSPEC_COND_GT): Rename to... (UNSPEC_COND_FCMGT): ...this. (SVE_COND_FP_BINARY, SVE_COND_FP_CMP, optab, cmp_op, sve_fp_op) (sve_fp_op_rev): Update accordingly. * config/aarch64/aarch64.c (aarch64_unspec_cond_code): Likewise. From-SVN: r274185
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