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2023-11-09RISC-V/testsuite: Fix several zvfh tests.Robin Dapp34-108/+310
This fixes some zvfh test oversights as well as adds zfh to the target requirements. It's not strictly necessary to have zfh but it greatly simplifies test handling when we can just calculate the reference value instead of working around it. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Adjust. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Ditto. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: New test.
2023-11-09i386: Improve stack protector patterns and peephole2s even moreUros Bizjak1-9/+66
Improve stack protector patterns and peephole2s even more: a. Use unrelated register clears with integer mode size <= word mode size to clear stack protector scratch register. b. Use unrelated register initializations in front of stack protector sequence to clear stack protector scratch register. c. Use unrelated register initializations using LEA instructions to clear stack protector scratch register. These stack protector improvements reuse 6914 unrelated register initializations to substitute the clear of stack protector scratch register in 12034 instances of stack protector sequence in recent linux defconfig build. gcc/ChangeLog: * config/i386/i386.md (@stack_protect_set_1_<PTR:mode>_<W:mode>): Use W mode iterator instead of SWI48. Output MOV instead of XOR for TARGET_USE_MOV0. (stack_protect_set_1 peephole2): Use integer modes with mode size <= word mode size for operand 3. (stack_protect_set_1 peephole2 #2): New peephole2 pattern to substitute stack protector scratch register clear with unrelated register initialization, originally in front of stack protector sequence. (*stack_protect_set_3_<PTR:mode>_<SWI48:mode>): New insn pattern. (stack_protect_set_1 peephole2): New peephole2 pattern to substitute stack protector scratch register clear with unrelated register initialization involving LEA instruction.
2023-11-09[IRA]: Fixing conflict calculation from region landing pads.Vladimir N. Makarov1-16/+28
The following patch fixes conflict calculation from exception landing pads. The previous patch processed only one newly created landing pad. Besides it was wrong, it also resulted in large memory consumption by IRA. gcc/ChangeLog: PR rtl-optimization/110215 * ira-lives.cc: (add_conflict_from_region_landing_pads): New function. (process_bb_node_lives): Use it.
2023-11-09i386 PIE: accept @GOTOFF in load/store multi base addressAlexandre Oliva1-14/+75
Looking at the code generated for sse2-{load,store}-multi.c with PIE, I realized we could use UNSPEC_GOTOFF as a base address, and that this would enable the test to use the vector insns expected by the tests even with PIC, so I extended the base + offset logic used by the SSE2 multi-load/store peepholes to accept reg + symbolic base + offset too, so that the test generated the expected insns even with PIE. for gcc/ChangeLog * config/i386/i386.cc (symbolic_base_address_p, base_address_p): New, factored out from... (extract_base_offset_in_addr): ... here and extended to recognize REG+GOTOFF, as in gcc.target/i386/sse2-load-multi.c and sse2-store-multi.c with PIE enabled by default.
2023-11-09testsuite: xfail scev-[35].c on ia32Alexandre Oliva2-2/+2
These gimplefe tests never got the desired optimization on ia32, but they only started visibly failing when the representation of MEMs in dumps changed from printing 'symbol: a' to '&a'. The transformation is not considered profitable on ia32, that's why it doesn't take place. Maybe that's a bug in itself, but it's not a regression, and not something to be noisy about. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/scev-3.c: xfail on ia32. * gcc.dg/tree-ssa/scev-5.c: Likewise.
2023-11-09AArch64: Add SVE implementation for cond_copysign.Tamar Christina2-0/+87
This adds an implementation for masked copysign along with an optimized pattern for masked copysign (x, -1). gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64-sve.md (cond_copysign<mode>): New. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/sve/fneg-abs_5.c: New test.
2023-11-09AArch64: Handle copysign (x, -1) expansion efficientlyTamar Christina3-10/+57
copysign (x, -1) is effectively fneg (abs (x)) which on AArch64 can be most efficiently done by doing an OR of the signbit. The middle-end will optimize fneg (abs (x)) now to copysign as the canonical form and so this optimizes the expansion. If the target has an inclusive-OR that takes an immediate, then the transformed instruction is both shorter and faster. For those that don't, the immediate has to be separately constructed, but this still ends up being faster as the immediate construction is not on the critical path. Note that this is part of another patch series, the additional testcases are mutually dependent on the match.pd patch. As such the tests are added there insteadof here. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64.md (copysign<GPF:mode>3): Handle copysign (x, -1). * config/aarch64/aarch64-simd.md (copysign<mode>3): Likewise. * config/aarch64/aarch64-sve.md (copysign<mode>3): Likewise.
2023-11-09AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD ↵Tamar Christina6-21/+22
inefficient [PR109154] SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR by immediate and would require a reload then use an unpredicated SVE ORR instead. This has both speed and size improvements. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64.md (<optab><mode>3): Add SVE split case. * config/aarch64/aarch64-simd.md (ior<mode>3<vczle><vczbe>): Likewise. * config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/sve/fneg-abs_1.c: Updated. * gcc.target/aarch64/sve/fneg-abs_2.c: Updated. * gcc.target/aarch64/sve/fneg-abs_4.c: Updated.
2023-11-09AArch64: Add movi for 0 moves for scalar types [PR109154]Tamar Christina5-3/+7
Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates should be created with a movi of 0. At the moment we generate an `fmov .., xzr` which is slower and requires a GP -> FP transfer. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64.md (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Add new w -> Z case. * config/aarch64/iterators.md (Vbtype): Add QI and HI. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/fneg-abs_2.c: Updated. * gcc.target/aarch64/fneg-abs_4.c: Updated. * gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.
2023-11-09AArch64: Add special patterns for creating DI scalar and vector constant 1 ↵Tamar Christina9-33/+119
<< 63 [PR109154] This adds a way to generate special sequences for creation of constants for which we don't have single instructions sequences which would have normally lead to a GP -> FP transfer or a literal load. The patch starts out by adding support for creating 1 << 63 using fneg (mov 0). gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p, aarch64_maybe_generate_simd_constant): New. * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VQMOV:mode>, *aarch64_simd_mov<VDMOV:mode>): Add new coden for special constants. * config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int): Take optional mode. (aarch64_simd_special_constant_p, aarch64_maybe_generate_simd_constant): New. * config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for special constants. * config/aarch64/constraints.md (Dx): new. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/fneg-abs_1.c: Updated. * gcc.target/aarch64/fneg-abs_2.c: Updated. * gcc.target/aarch64/fneg-abs_4.c: Updated. * gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.
2023-11-09ifcvt: Add support for conditional copysignTamar Christina3-3/+6
This adds a masked variant of copysign. Nothing very exciting just the general machinery to define and use a new masked IFN. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Note: This patch is part of a testseries and tests for it are added in the AArch64 patch that adds supports for the optab. gcc/ChangeLog: PR tree-optimization/109154 * internal-fn.def (COPYSIGN): New. * match.pd (UNCOND_BINARY, COND_BINARY): Map IFN_COPYSIGN to IFN_COND_COPYSIGN. * optabs.def (cond_copysign_optab, cond_len_copysign_optab): New.
2023-11-09middle-end: optimize fneg (fabs (x)) to copysign (x, -1) [PR109154]Tamar Christina15-12/+303
This patch transforms fneg (fabs (x)) into copysign (x, -1) which is more canonical and allows a target to expand this sequence efficiently. Such sequences are common in scientific code working with gradients. There is an existing canonicalization of copysign (x, -1) to fneg (fabs (x)) which I remove since this is a less efficient form. The testsuite is also updated in light of this. gcc/ChangeLog: PR tree-optimization/109154 * match.pd: Add new neg+abs rule, remove inverse copysign rule. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.dg/fold-copysign-1.c: Updated. * gcc.dg/pr55152-2.c: Updated. * gcc.dg/tree-ssa/abs-4.c: Updated. * gcc.dg/tree-ssa/backprop-6.c: Updated. * gcc.dg/tree-ssa/copy-sign-2.c: Updated. * gcc.dg/tree-ssa/mult-abs-2.c: Updated. * gcc.target/aarch64/fneg-abs_1.c: New test. * gcc.target/aarch64/fneg-abs_2.c: New test. * gcc.target/aarch64/fneg-abs_3.c: New test. * gcc.target/aarch64/fneg-abs_4.c: New test. * gcc.target/aarch64/sve/fneg-abs_1.c: New test. * gcc.target/aarch64/sve/fneg-abs_2.c: New test. * gcc.target/aarch64/sve/fneg-abs_3.c: New test. * gcc.target/aarch64/sve/fneg-abs_4.c: New test.
2023-11-09middle-end: expand copysign handling from lockstep to nested itersTamar Christina1-24/+24
various optimizations in match.pd only happened on COPYSIGN in lock step which means they exclude IFN_COPYSIGN. COPYSIGN however is restricted to only the C99 builtins and so doesn't work for vectors. The patch expands these optimizations to work as nested iters. This is needed for the second patch which will add the testcase. gcc/ChangeLog: PR tree-optimization/109154 * match.pd: expand existing copysign optimizations.
2023-11-09Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)Simon Wright2-3/+34
The description of the second Value function (returning Duration) (ARM 9.6.1(87) doesn't place any limitation on the Elapsed_Time parameter's value, beyond "Constraint_Error is raised if the string is not formatted as described for Image, or the function cannot interpret the given string as a Duration value". It would seem reasonable that Value and Image should be consistent, in that any string produced by Image should be accepted by Value. Since Image must produce a two-digit representation of the Hours, there's an implication that its Elapsed_Time parameter should be less than 100.0 hours (the ARM merely says that in that case the result is implementation-defined). The current implementation of Value raises Constraint_Error if the Elapsed_Time parameter is greater than or equal to 24 hours. This patch removes the restriction, so that the Elapsed_Time parameter must only be less than 100.0 hours. 2023-10-15 Simon Wright <simon@pushface.org> PR ada/111813 gcc/ada/ * libgnat/a-calfor.adb (Value (2)): Allow values of parameter Elapsed_Time greater than or equal to 24 hours, by doing the hour calculations in Natural rather than Hour_Number (0 .. 23). Calculate the result directly rather than by using Seconds_Of (whose Hour parameter is of type Hour_Number). If an exception occurs of type Constraint_Error, re-raise it rather than raising a new CE. gcc/testsuite/ * gnat.dg/calendar_format_value.adb: New test.
2023-11-09Do not prepend target triple to -fuse-ld=lld,mold.Tatsuyuki Ishi1-5/+8
lld and mold are platform-agnostic and not prefixed with target triple. Prepending the target triple makes it less likely to find the intended linker executable. A potential breaking change is that we no longer try to search for triple-prefixed lld/mold binaries anymore. However, since there doesn't seem to be support to build LLVM or mold with triple-prefixed executable names, it seems better to just not bother with that case. PR driver/111605 * collect2.cc (main): Do not prepend target triple to -fuse-ld=lld,mold.
2023-11-09Refactor x86 decl based scatter vectorization, prepare SLPRichard Biener2-360/+332
The following refactors the x86 decl based scatter vectorization similar to what I did to the gather path. This prepares scatters for SLP as well, mainly single-lane since there are multiple missing bits to support multi-lane scatters. Tested extensively on the SLP-only branch which has the ability to force SLP even for single lanes. PR tree-optimization/111133 * tree-vect-stmts.cc (vect_build_scatter_store_calls): Remove and refactor to ... (vect_build_one_scatter_store_call): ... this new function. (vectorizable_store): Use vect_check_scalar_mask to record the SLP node for the mask operand. Code generate scatters with builtin decls from the main scatter vectorization path and prepare that for SLP. * tree-vect-slp.cc (vect_get_operand_map): Do not look at the VDEF to decide between scatter or gather since that doesn't work for patterns. Use the LHS being an SSA_NAME or not instead.
2023-11-09RISC-V: Refine frm emit after bb end in succ edgesPan Li1-4/+17
This patch would like to fine the frm insn emit when we meet abnormal edge in the loop. Conceptually, we only need to emit once when abnormal instead of every iteration in the loop. This patch would like to fix this defect and only perform insert_insn_end_basic_block when at least one succ edge is abnormal. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_frm_emit_after_bb_end): Only perform once emit when at least one succ edge is abnormal. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-11-09RISC-V: Add PR112450 test to avoid regressionJuzhe-Zhong1-0/+19
ICE has been fixed by Richard:https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112450. Add test to avoid future regression. Committed. PR target/112450 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112450.c: New test.
2023-11-09tree-optimization/112450 - avoid AVX512 style masking for BImode masksRichard Biener1-1/+4
The following avoids running into the AVX512 style masking code for RVV which would theoretically be able to handle it if I were not relying on integer mode maskness in vect_get_loop_mask. While that's easy to fix (patch in PR), the preference is to not have AVX512 style masking for RVV, thus the following. * tree-vect-loop.cc (vect_verify_full_masking_avx512): Check we have integer mode masks as required by vect_get_loop_mask.
2023-11-09tree-optimization/112444 - avoid bougs PHI value-numberingRichard Biener2-2/+79
With .DEFERRED_INIT ssa_undefined_value_p () can return true for values we did not visit (because they proved unreachable) but are not .VN_TOP. Avoid using those as value which, because they are not visited, are assumed to be defined outside of the region. PR tree-optimization/112444 * tree-ssa-sccvn.cc (visit_phi): Avoid using not visited defs as undefined vals. * gcc.dg/torture/pr112444.c: New testcase.
2023-11-09MIPS: Use -mnan value for -mabs if not specifiedYunQiang Su3-0/+22
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's use this behaivor by default in GCC, aka gcc -mnan=2008 -c fabs.c will imply `-mabs=2008`. And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable like previous. gcc/ChangeLog * config/mips/mips.cc(mips_option_override): Set mips_abs to 2008, if mips_abs is default and mips_nan is 2008. gcc/testsuite/ * gcc.target/mips/fabs-nan2008.c: New test. * gcc.target/mips/fabsf-nan2008.c: New test.
2023-11-09i386: Fix C99 compatibility issues in the x86-64 AVX ABI test suiteFlorian Weimer9-11/+15
gcc/testsuite/ * gcc.target/x86_64/abi/avx/avx-check.h (main): Call __builtin_printf instead of printf. * gcc.target/x86_64/abi/avx/test_passing_m256.c (fun_check_passing_m256_8_values): Add missing void return type. * gcc.target/x86_64/abi/avx512f/avx512f-check.h (main): Call __builtin_printf instead of printf. * gcc.target/x86_64/abi/avx512f/test_passing_m512.c (fun_check_passing_m512_8_values): Add missing void return type. * gcc.target/x86_64/abi/bf16/bf16-check.h (main): Call __builtin_printf instead of printf. * gcc.target/x86_64/abi/bf16/m256bf16/bf16-ymm-check.h (main): Likewise. * gcc.target/x86_64/abi/bf16/m256bf16/test_passing_m256.c (fun_check_passing_m256bf16_8_values): Add missing void return type. * gcc.target/x86_64/abi/bf16/m512bf16/bf16-zmm-check.h (main): Call __builtin_printf instead of printf. * gcc.target/x86_64/abi/bf16/m512bf16/test_passing_m512.c (fun_check_passing_m512bf16_8_values): Add missign void return type.
2023-11-09c: Add -Wreturn-mismatch warning, split from -Wreturn-typeFlorian Weimer11-27/+277
The existing -Wreturn-type option covers both constraint violations (which are mandatory to diagnose) and warnings that have known false positives. The new -Wreturn-mismatch warning is only about the constraint violations (missing or extra return expressions), and should eventually be turned into a permerror. The -std=gnu89 test cases show that by default, we do not warn for return; in a function not returning void. This matches previous practice for -Wreturn-type. gcc/c-family/ * c.opt (Wreturn-mismatch): New. gcc/c/ * c-typeck.cc (c_finish_return): Use pedwarn with OPT_Wreturn_mismatch for missing/extra return expressions. gcc/ * doc/invoke.texi (Warning Options): Document -Wreturn-mismatch. Update -Wreturn-type documentation. gcc/testsuite/ * gcc.dg/Wreturn-mismatch-1.c: New. * gcc.dg/Wreturn-mismatch-2.c: New. * gcc.dg/Wreturn-mismatch-3.c: New. * gcc.dg/Wreturn-mismatch-4.c: New. * gcc.dg/Wreturn-mismatch-5.c: New. * gcc.dg/Wreturn-mismatch-6.c: New. * gcc.dg/noncompile/pr55976-1.c: Change -Werror=return-type to -Werror=return-mismatch. * gcc.dg/noncompile/pr55976-2.c: Change -Wreturn-type to -Wreturn-mismatch.
2023-11-09gcc.dg/Wmissing-parameter-type*: Test the intended warningFlorian Weimer2-4/+4
gcc/testsuite/ChangeLog: * gcc.dg/Wmissing-parameter-type.c: Build with -std=gnu89 to trigger the -Wmissing-parameter-type warning and not the default -Wimplicit warning. Also match against -Wmissing-parameter-type. * gcc.dg/Wmissing-parameter-type-Wextra.c: Likewise.
2023-11-09s390: Revise vector reverse elementsStefan Schulze Frielinghaus12-147/+527
Replace UNSPEC_VEC_ELTSWAP with a vec_select implementation. Furthermore, for a vector reverse elements operation between registers of mode V8HI perform three rotates instead of a vperm operation since the latter involves loading the permutation vector from the literal pool. Prior z15, instead of larl + vl + vl + vperm prefer vl + vpdi (+ verllg (+ verllf)) for a load operation. Likewise, prior z15, instead of larl + vl + vperm + vst prefer vpdi (+ verllg (+ verllf)) + vst for a store operation. gcc/ChangeLog: * config/s390/s390.md: Remove UNSPEC_VEC_ELTSWAP. * config/s390/vector.md (eltswapv16qi): New expander. (*eltswapv16qi): New insn and splitter. (eltswapv8hi): New insn and splitter. (eltswap<mode>): New insn and splitter for modes V_HW_4 as well as V_HW_2. * config/s390/vx-builtins.md (eltswap<mode>): Remove. (*eltswapv16qi): Remove. (*eltswap<mode>): Remove. (*eltswap<mode>_emu): Remove. gcc/testsuite/ChangeLog: * gcc.target/s390/zvector/vec-reve-load-halfword-z14.c: Remove vperm and substitude by vpdi et al. * gcc.target/s390/zvector/vec-reve-load-halfword.c: Likewise. * gcc.target/s390/vector/reverse-elements-1.c: New test. * gcc.target/s390/vector/reverse-elements-2.c: New test. * gcc.target/s390/vector/reverse-elements-3.c: New test. * gcc.target/s390/vector/reverse-elements-4.c: New test. * gcc.target/s390/vector/reverse-elements-5.c: New test. * gcc.target/s390/vector/reverse-elements-6.c: New test. * gcc.target/s390/vector/reverse-elements-7.c: New test.
2023-11-09s390: Add expand_perm_reverse_elementsStefan Schulze Frielinghaus1-72/+16
Replace expand_perm_with_rot, expand_perm_with_vster, and expand_perm_with_vstbrq with a general implementation expand_perm_reverse_elements. gcc/ChangeLog: * config/s390/s390.cc (expand_perm_with_rot): Remove. (expand_perm_reverse_elements): New. (expand_perm_with_vster): Remove. (expand_perm_with_vstbrq): Remove. (vectorize_vec_perm_const_1): Replace removed functions with new one.
2023-11-09s390: Recognize further vpdi and vmr{l,h} patternStefan Schulze Frielinghaus1-28/+90
Deal with cases where vpdi and vmr{l,h} are still applicable if the operands of those instructions are swapped. For example, currently for V2DI foo (V2DI x) { return (V2DI) {x[1], x[0]}; } the assembler sequence vlgvg %r1,%v24,1 vzero %v0 vlvgg %v0,%r1,0 vmrhg %v24,%v0,%v24 is emitted. With this patch a single vpdi is emitted. Extensive tests are included in a subsequent patch of this series where more cases are covered. gcc/ChangeLog: * config/s390/s390.cc (expand_perm_with_merge): Deal with cases where vmr{l,h} are still applicable if the operands are swapped. (expand_perm_with_vpdi): Likewise for vpdi.
2023-11-09s390: Reduce number of patterns where the condition is false anywayStefan Schulze Frielinghaus2-51/+46
For patterns which make use of two modes, do not build the cross product and then exclude illegal combinations via conditions but rather do not create those in the first place. Here we are following the idea of the attribute TOINTVEC/tointvec and introduce TOINT/toint. gcc/ChangeLog: * config/s390/s390.md (VX_CONV_INT): Remove iterator. (gf): Add float mappings. (TOINT, toint): New attribute. (*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13): Remove. (*fixuns_trunc<mode><toint>2_z13): Add. (*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13): Remove. (*fix_trunc<mode><toint>2_bfp_z13): Add. (*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13): Remove. (*floatuns<toint><mode>2_z13): Add. * config/s390/vector.md (VX_VEC_CONV_INT): Remove iterator. (float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove. (float<tointvec><mode>2): Add. (floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove. (floatuns<tointvec><mode>2): Add. (fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2): Remove. (fix_trunc<mode><tointvec>2): Add. (fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2): Remove. (fixuns_trunc<VX_VEC_CONV_BFP:mode><tointvec>2): Add.
2023-11-09libgcc: Add {unsigned ,}__int128 <-> _Decimal{32,64,128} conversion support ↵Jakub Jelinek4-0/+535
[PR65833] The following patch adds the missing {unsigned ,}__int128 <-> _Decimal{32,64,128} conversion support into libgcc.a on top of the _BitInt support (doing it without that would be larger amount of code and I hope all the targets which support __int128 will eventually support _BitInt, after all it is a required part of C23) and because it is in libgcc.a only, it doesn't hurt that much if it is added for some architectures only in GCC 15. Initially I thought about doing this on the compiler side, but doing it on the library side seems to be easier and more -Os friendly. The tests currently require bitint effective target, that can be removed when all the int128 targets support bitint. 2023-11-09 Jakub Jelinek <jakub@redhat.com> PR libgcc/65833 libgcc/ * config/t-softfp (softfp_bid_list): Add {U,}TItype <-> _Decimal{32,64,128} conversions. * soft-fp/floattisd.c: New file. * soft-fp/floattidd.c: New file. * soft-fp/floattitd.c: New file. * soft-fp/floatuntisd.c: New file. * soft-fp/floatuntidd.c: New file. * soft-fp/floatuntitd.c: New file. * soft-fp/fixsdti.c: New file. * soft-fp/fixddti.c: New file. * soft-fp/fixtdti.c: New file. * soft-fp/fixunssdti.c: New file. * soft-fp/fixunsddti.c: New file. * soft-fp/fixunstdti.c: New file. gcc/testsuite/ * gcc.dg/dfp/int128-1.c: New test. * gcc.dg/dfp/int128-2.c: New test. * gcc.dg/dfp/int128-3.c: New test. * gcc.dg/dfp/int128-4.c: New test.
2023-11-09attribs: Fix ICE with -Wno-attributes= [PR112339]Jakub Jelinek2-3/+15
The following testcase ICEs, because with -Wno-attributes=foo::no_sanitize (but generally any other non-gnu namespace and some gnu well known attribute name within that other namespace) the FEs don't really parse attribute arguments of such attribute, but lookup_attribute_spec is non-NULL with NULL handler and such attributes are added to DECL_ATTRIBUTES or TYPE_ATTRIBUTES and then when e.g. middle-end does lookup_attribute on a particular attribute and expects the attribute to mean something and/or have a particular verified arguments, it can crash when seeing the foreign attribute in there instead. The following patch fixes that by never adding ignored attributes to DECL_ATTRIBUTES/TYPE_ATTRIBUTES, previously that was the case just for attributes in ignored namespace (where lookup_attribute_space returned NULL). We don't really know anything about those attributes, so shouldn't pretend we know something about them, especially when the arguments are error_mark_node or NULL instead of something that would have been parsed. And it would be really weird if we normally ignore say [[clang::unused]] attribute, but when people use -Wno-attributes=clang::unused we actually treated it as gnu::unused. All the user asked for is suppress warnings about that attribute being unknown. The first hunk is just playing safe, I'm worried people could -Wno-attributes=gnu:: and get various crashes with known GNU attributes not being actually parsed and recorded (or worse e.g. when we tweak standard attributes into GNU attributes and we wouldn't add those). The -Wno-attributes= documentation says that it suppresses warning about unknown attributes, so I think -Wno-attributes=gnu:: should prevent warning about say [[gnu::foobarbaz]] attribute, but not about [[gnu::unused]] because the latter is a known attribute. The routine would return true for any scoped attribute in the ignored namespace, with the change it ignores only unknown attributes in ignored namespace, known ones in there will be ignored only if they have max_length of -2 (e.g.. with -Wno-attributes=gnu:: -Wno-attributes=gnu::foobarbaz). 2023-11-09 Jakub Jelinek <jakub@redhat.com> PR c/112339 * attribs.cc (attribute_ignored_p): Only return true for attr_namespace_ignored_p if as is NULL. (decl_attributes): Never add ignored attributes. * c-c++-common/ubsan/Wno-attributes-1.c: New test.
2023-11-09RISC-V: Fix the illegal operands for the XTheadMemidx extension.Jin Ma2-2/+32
The pattern "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip" and "*zero_extendhi<GPR:mode>2_bitmanip" in bitmanip.md are similar to the pattern "*th_memidx_bb_extendqi<SUPERQI:mode>2" and "*th_memidx_bb_zero_extendhi<GPR:mode>2" in thead.md, which will cause the wrong instruction to be generated and report the following error in binutils: Assembler messages: Error: illegal operands `lb a5,(a0),1,0' In fact, the correct instruction is "th.lbia a5,(a0),1,0". gcc/ChangeLog: * config/riscv/bitmanip.md: Avoid the conflict between zbb and xtheadmemidx in patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmemidx-uindex-zbb.c: New test.
2023-11-09Fix SIMD clone SLP a bit moreRichard Biener1-5/+4
The following fixes an omission, mangling the non-SLP and SLP simd-clone info. * tree-vect-stmts.cc (vectorizable_simd_clone_call): Record to the correct simd_clone_info.
2023-11-09RISC-V: Fix dynamic LMUL cost model ICEJuzhe-Zhong4-3/+69
When trying to use dynamic LMUL to compile benchmark. Notice there is a bunch ICEs. This patch fixes those ICEs and append tests. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Fix ICE. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: New test.
2023-11-09testsuite: adjust gomp test for x86 -m32Alexandre Oliva1-7/+7
declare-target-3.C expects .quad for entries in offload_var_table, but the entries are pointer-wide, so 32-bit targets use .long instead. Accept both. for gcc/testsuite/ChangeLog * g++.dg/gomp/declare-target-3.C: Adjust for 32-bit targets.
2023-11-09testsuite: force PIC/PIE off for pr58245-1.CAlexandre Oliva1-0/+4
This test expects a single mention of stack_chk_fail, as part of a call sequence, but when e.g. PIE is enabled by default, we output .hidden stack_chk_fail_local, which makes for a count mismatch. Disable PIC/PIE so as to not depend on the configurable default. for gcc/testsuite/ChangeLog * g++.dg/pr58245-1.C: Disable PIC/PIE.
2023-11-09skip debug stmts when assigning locus discriminatorsAlexandre Oliva1-0/+16
c-c++-common/goacc/kernels-loop-g.c has been failing (compare-debug) on i686-linux-gnu since r13-3172, because the implementation enabled debug stmts to cause discriminators to be assigned differently, and the discriminators are printed in the .gkd dumps that -fcompare-debug compares. This patch prevents debug stmts from affecting the discriminators in nondebug stmts, but enables debug stmts to get discriminators just as nondebug stmts would if their line numbers match. I suppose we could arrange for discriminators to be omitted from the -fcompare-debug dumps, but keeping discriminators in sync is probably good to avoid other potential sources of divergence between debug and nondebug. for gcc/ChangeLog * tree-cfg.cc (assign_discriminators): Handle debug stmts.
2023-11-09RISC-V: Fix dynamic tests [NFC]Juzhe-Zhong37-40/+42
This patch just adapt dynamic LMUL tests for following preparing patches. Committed. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr111848.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/rvv-costmodel-vect.exp: Run all tests.
2023-11-09Daily bump.GCC Administrator4-1/+652
2023-11-08i386: Apply LRA reload workaround to insns with high registers [PR82524]Uros Bizjak12-243/+673
LRA is not able to reload zero_extracted in-out operand with matched input operand in the same way as strict_low_part in-out operand. The patch applies the strict_low_part workaround, where we allow LRA to generate an instruction with non-matched input operand, which is split post reload to the instruction that inserts non-matched input operand to an in-out operand and the instruction that uses matched operand, also to zero_extracted in-out operand case. The generated code from the pr82524.c testcase improves from: movl %esi, %ecx movl %edi, %eax movsbl %ch, %esi addl %esi, %edx movb %dl, %ah to: movl %edi, %eax movl %esi, %ecx movb %ch, %ah addb %dl, %ah The compiler is now also able to handle non-commutative operations: movl %edi, %eax movl %esi, %ecx movb %ch, %ah subb %dl, %ah and unary operations: movl %edi, %eax movl %esi, %edx movb %dh, %ah negb %ah The patch also robustifies split condition of the splitters to ensure that only alternatives with unmatched operands are split. PR target/82524 gcc/ChangeLog: * config/i386/i386.md (*add<mode>_1_slp): Split insn only for unmatched operand 0. (*sub<mode>_1_slp): Ditto. (*<any_logic:code><mode>_1_slp): Merge pattern from "*and<mode>_1_slp" and "*<any_logic:code><mode>_1_slp" using any_logic code iterator. Split insn only for unmatched operand 0. (*neg<mode>1_slp): Split insn only for unmatched operand 0. (*one_cmpl<mode>_1_slp): Ditto. (*ashl<mode>3_1_slp): Ditto. (*<any_shiftrt:insn><mode>_1_slp): Ditto. (*<any_rotate:insn><mode>_1_slp): Ditto. (*addqi_ext<mode>_1): Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*<plusminus:insn>qi_ext<mode>_2): Merge pattern from "*addqi_ext<mode>_2" and "*subqi_ext<mode>_2" using plusminus code iterator. Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*subqi_ext<mode>_1): Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*<any_logic:code>qi_ext<mode>_0): Merge pattern from "*andqi_ext<mode>_0" and and "*<any_logic:code>qi_ext<mode>_0" using any_logic code iterator. (*<any_logic:code>qi_ext<mode>_1): Merge pattern from "*andqi_ext<mode>_1" and "*<any_logic:code>qi_ext<mode>_1" using any_logic code iterator. Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*<any_logic:code>qi_ext<mode>_1_cc): Merge pattern from "*andqi_ext<mode>_1_cc" and "*xorqi_ext<mode>_1_cc" using any_logic code iterator. Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*<any_logic:code>qi_ext<mode>_2): Merge pattern from "*andqi_ext<mode>_2" and "*<any_or:code>qi_ext<mode>_2" using any_logic code iterator. Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*<any_logic:code>qi_ext<mode>_3): Redefine as define_insn_and_split. Add alternative 1 and split insn after reload for unmatched operand 0. (*negqi_ext<mode>_1): Rename from "*negqi_ext<mode>_2". Add alternative 1 and split insn after reload for unmatched operand 0. (*one_cmplqi_ext<mode>_1): Ditto. (*ashlqi_ext<mode>_1): Ditto. (*<any_shiftrt:insn>qi_ext<mode>_1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr78904-1.c (test_sub): New test. * gcc.target/i386/pr78904-1a.c (test_sub): Ditto. * gcc.target/i386/pr78904-1b.c (test_sub): Ditto. * gcc.target/i386/pr78904-2.c (test_sub): Ditto. * gcc.target/i386/pr78904-2a.c (test_sub): Ditto. * gcc.target/i386/pr78904-2b.c (test_sub): Ditto. * gcc.target/i386/pr78952-4.c (test_sub): Ditto. * gcc.target/i386/pr82524.c: New test. * gcc.target/i386/pr82524-1.c: New test. * gcc.target/i386/pr82524-2.c: New test. * gcc.target/i386/pr82524-3.c: New test.
2023-11-08Fix SLP of emulated gathersRichard Biener1-1/+1
The following fixes an error in the SLP of emulated gathers, discovered by x86 specific tests when enabling single-lane SLP. * tree-vect-stmts.cc (vectorizable_load): Adjust offset vector gathering for SLP of emulated gathers.
2023-11-08TLC to vect_check_store_rhs and vect_slp_child_index_for_operandRichard Biener3-28/+31
This prepares us for the SLP of scatters. We have to tell vect_slp_child_index_for_operand whether we are dealing with a scatter/gather stmt so this adds an argument similar to the one we have for vect_get_operand_map. This also refactors vect_check_store_rhs to get the actual rhs and the associated SLP node instead of leaving that to the caller. * tree-vectorizer.h (vect_slp_child_index_for_operand): Add gatherscatter_p argument. * tree-vect-slp.cc (vect_slp_child_index_for_operand): Likewise. Pass it on. * tree-vect-stmts.cc (vect_check_store_rhs): Turn the rhs argument into an output, also output the SLP node associated with it. (vectorizable_simd_clone_call): Adjust. (vectorizable_store): Likewise. (vectorizable_load): Likewise.
2023-11-08Fix SLP of masked loadsRichard Biener1-7/+4
The following adjusts things to use the correct mask operand for the SLP of masked loads and gathers. Test coverage is from runtime fails of i386 specific AVX512 tests when enabling single-lane SLP. * tree-vect-stmts.cc (vectorizable_load): Use the correct vectorized mask operand.
2023-11-08RISC-V: Removed unnecessary sign-extend for vsetvlLehua Ding2-0/+72
Hi, This patch try to combine bellow two insns and then further remove unnecessary sign_extend operations. This optimization is borrowed from LLVM (https://godbolt.org/z/4f6v56xej): (set (reg:DI 134 [ _1 ]) (unspec:DI [ (const_int 19 [0x13]) (const_int 8 [0x8]) (const_int 5 [0x5]) (const_int 2 [0x2]) repeated x2 ] UNSPEC_VSETVL)) (set (reg/v:DI 135 [ <retval> ]) (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0))) The reason we can remove signe_extend is because currently the vl value returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and bits 17 to 63 (including 31) are always 0, so there is no change after sign_extend. Note that for HI and QI modes we cannot do this. Of course, if the range returned by vsetvl later expands to 32 bits, then this combine pattern needs to be removed. But that could be a long time from now. gcc/ChangeLog: * config/riscv/vector.md (*vsetvldi_no_side_effects_si_extend): New combine pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: New test.
2023-11-08Improve C99 compatibility of gcc.dg/setjmp-7.c testFlorian Weimer1-0/+1
gcc/testsuite/ChangeLog: * gcc.dg/setjmp-7.c (_setjmp): Declare.
2023-11-08RISC-V: Fix VSETVL VL check condition bugJuzhe-Zhong2-1/+12
When fixing the induction variable vectorization bug, notice there is a ICE bug in VSETVL PASS: 0x178015b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../../../../gcc/gcc/rtl.cc:770 0x1079cdd rhs_regno(rtx_def const*) ../../../../gcc/gcc/rtl.h:1934 0x1dab360 vsetvl_info::parse_insn(rtl_ssa::insn_info*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:1070 0x1daa272 vsetvl_info::vsetvl_info(rtl_ssa::insn_info*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:746 0x1da5d98 pre_vsetvl::fuse_local_vsetvl_info() ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2708 0x1da94d9 pass_vsetvl::lazy_vsetvl() ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3444 0x1da977c pass_vsetvl::execute(function*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3504 Committed as it is obvious. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: Fix ICE. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vl-use-ice.c: New test.
2023-11-08libgfortran: Remove empty array descriptor first dimension overwrite [PR112371]Mikael Morin1-0/+588
Remove the forced overwrite of the first dimension of the result array descriptor to set it to zero extent, in the function templates for transformational functions doing an array reduction along a dimension. This overwrite, which happened before early returning in case the result array was empty, was wrong because an array may have a non-zero extent in the first dimension and still be empty if it has a zero extent in a higher dimension. Overwriting the dimension was resulting in wrong array result upper bound for the first dimension in that case. The offending piece of code was present in several places, and this removes them all. More precisely, there is only one case to fix for logical reduction functions, and there are three cases for other reduction functions, corresponding to non-masked reduction, reduction with array mask, and reduction with scalar mask. The impacted m4 files are ifunction_logical.m4 for logical reduction functions, ifunction.m4 for regular functions and types, ifunction-s.m4 for character minloc and maxloc, ifunction-s2.m4 for character minval and maxval, and ifindloc1.m4 for findloc. PR fortran/112371 libgfortran/ChangeLog: * m4/ifunction.m4 (START_ARRAY_FUNCTION, START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Remove overwrite of the first dimension of the array descriptor. * m4/ifunction-s.m4 (START_ARRAY_FUNCTION, START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Ditto. * m4/ifunction-s2.m4 (START_ARRAY_FUNCTION, START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Ditto. * m4/ifunction_logical.m4 (START_ARRAY_FUNCTION): Ditto. * m4/ifindloc1.m4: Ditto. * generated/all_l1.c: Regenerate. * generated/all_l16.c: Regenerate. * generated/all_l2.c: Regenerate. * generated/all_l4.c: Regenerate. * generated/all_l8.c: Regenerate. * generated/any_l1.c: Regenerate. * generated/any_l16.c: Regenerate. * generated/any_l2.c: Regenerate. * generated/any_l4.c: Regenerate. * generated/any_l8.c: Regenerate. * generated/count_16_l.c: Regenerate. * generated/count_1_l.c: Regenerate. * generated/count_2_l.c: Regenerate. * generated/count_4_l.c: Regenerate. * generated/count_8_l.c: Regenerate. * generated/findloc1_c10.c: Regenerate. * generated/findloc1_c16.c: Regenerate. * generated/findloc1_c17.c: Regenerate. * generated/findloc1_c4.c: Regenerate. * generated/findloc1_c8.c: Regenerate. * generated/findloc1_i1.c: Regenerate. * generated/findloc1_i16.c: Regenerate. * generated/findloc1_i2.c: Regenerate. * generated/findloc1_i4.c: Regenerate. * generated/findloc1_i8.c: Regenerate. * generated/findloc1_r10.c: Regenerate. * generated/findloc1_r16.c: Regenerate. * generated/findloc1_r17.c: Regenerate. * generated/findloc1_r4.c: Regenerate. * generated/findloc1_r8.c: Regenerate. * generated/findloc1_s1.c: Regenerate. * generated/findloc1_s4.c: Regenerate. * generated/iall_i1.c: Regenerate. * generated/iall_i16.c: Regenerate. * generated/iall_i2.c: Regenerate. * generated/iall_i4.c: Regenerate. * generated/iall_i8.c: Regenerate. * generated/iany_i1.c: Regenerate. * generated/iany_i16.c: Regenerate. * generated/iany_i2.c: Regenerate. * generated/iany_i4.c: Regenerate. * generated/iany_i8.c: Regenerate. * generated/iparity_i1.c: Regenerate. * generated/iparity_i16.c: Regenerate. * generated/iparity_i2.c: Regenerate. * generated/iparity_i4.c: Regenerate. * generated/iparity_i8.c: Regenerate. * generated/maxloc1_16_i1.c: Regenerate. * generated/maxloc1_16_i16.c: Regenerate. * generated/maxloc1_16_i2.c: Regenerate. * generated/maxloc1_16_i4.c: Regenerate. * generated/maxloc1_16_i8.c: Regenerate. * generated/maxloc1_16_r10.c: Regenerate. * generated/maxloc1_16_r16.c: Regenerate. * generated/maxloc1_16_r17.c: Regenerate. * generated/maxloc1_16_r4.c: Regenerate. * generated/maxloc1_16_r8.c: Regenerate. * generated/maxloc1_16_s1.c: Regenerate. * generated/maxloc1_16_s4.c: Regenerate. * generated/maxloc1_4_i1.c: Regenerate. * generated/maxloc1_4_i16.c: Regenerate. * generated/maxloc1_4_i2.c: Regenerate. * generated/maxloc1_4_i4.c: Regenerate. * generated/maxloc1_4_i8.c: Regenerate. * generated/maxloc1_4_r10.c: Regenerate. * generated/maxloc1_4_r16.c: Regenerate. * generated/maxloc1_4_r17.c: Regenerate. * generated/maxloc1_4_r4.c: Regenerate. * generated/maxloc1_4_r8.c: Regenerate. * generated/maxloc1_4_s1.c: Regenerate. * generated/maxloc1_4_s4.c: Regenerate. * generated/maxloc1_8_i1.c: Regenerate. * generated/maxloc1_8_i16.c: Regenerate. * generated/maxloc1_8_i2.c: Regenerate. * generated/maxloc1_8_i4.c: Regenerate. * generated/maxloc1_8_i8.c: Regenerate. * generated/maxloc1_8_r10.c: Regenerate. * generated/maxloc1_8_r16.c: Regenerate. * generated/maxloc1_8_r17.c: Regenerate. * generated/maxloc1_8_r4.c: Regenerate. * generated/maxloc1_8_r8.c: Regenerate. * generated/maxloc1_8_s1.c: Regenerate. * generated/maxloc1_8_s4.c: Regenerate. * generated/maxval1_s1.c: Regenerate. * generated/maxval1_s4.c: Regenerate. * generated/maxval_i1.c: Regenerate. * generated/maxval_i16.c: Regenerate. * generated/maxval_i2.c: Regenerate. * generated/maxval_i4.c: Regenerate. * generated/maxval_i8.c: Regenerate. * generated/maxval_r10.c: Regenerate. * generated/maxval_r16.c: Regenerate. * generated/maxval_r17.c: Regenerate. * generated/maxval_r4.c: Regenerate. * generated/maxval_r8.c: Regenerate. * generated/minloc1_16_i1.c: Regenerate. * generated/minloc1_16_i16.c: Regenerate. * generated/minloc1_16_i2.c: Regenerate. * generated/minloc1_16_i4.c: Regenerate. * generated/minloc1_16_i8.c: Regenerate. * generated/minloc1_16_r10.c: Regenerate. * generated/minloc1_16_r16.c: Regenerate. * generated/minloc1_16_r17.c: Regenerate. * generated/minloc1_16_r4.c: Regenerate. * generated/minloc1_16_r8.c: Regenerate. * generated/minloc1_16_s1.c: Regenerate. * generated/minloc1_16_s4.c: Regenerate. * generated/minloc1_4_i1.c: Regenerate. * generated/minloc1_4_i16.c: Regenerate. * generated/minloc1_4_i2.c: Regenerate. * generated/minloc1_4_i4.c: Regenerate. * generated/minloc1_4_i8.c: Regenerate. * generated/minloc1_4_r10.c: Regenerate. * generated/minloc1_4_r16.c: Regenerate. * generated/minloc1_4_r17.c: Regenerate. * generated/minloc1_4_r4.c: Regenerate. * generated/minloc1_4_r8.c: Regenerate. * generated/minloc1_4_s1.c: Regenerate. * generated/minloc1_4_s4.c: Regenerate. * generated/minloc1_8_i1.c: Regenerate. * generated/minloc1_8_i16.c: Regenerate. * generated/minloc1_8_i2.c: Regenerate. * generated/minloc1_8_i4.c: Regenerate. * generated/minloc1_8_i8.c: Regenerate. * generated/minloc1_8_r10.c: Regenerate. * generated/minloc1_8_r16.c: Regenerate. * generated/minloc1_8_r17.c: Regenerate. * generated/minloc1_8_r4.c: Regenerate. * generated/minloc1_8_r8.c: Regenerate. * generated/minloc1_8_s1.c: Regenerate. * generated/minloc1_8_s4.c: Regenerate. * generated/minval1_s1.c: Regenerate. * generated/minval1_s4.c: Regenerate. * generated/minval_i1.c: Regenerate. * generated/minval_i16.c: Regenerate. * generated/minval_i2.c: Regenerate. * generated/minval_i4.c: Regenerate. * generated/minval_i8.c: Regenerate. * generated/minval_r10.c: Regenerate. * generated/minval_r16.c: Regenerate. * generated/minval_r17.c: Regenerate. * generated/minval_r4.c: Regenerate. * generated/minval_r8.c: Regenerate. * generated/norm2_r10.c: Regenerate. * generated/norm2_r16.c: Regenerate. * generated/norm2_r17.c: Regenerate. * generated/norm2_r4.c: Regenerate. * generated/norm2_r8.c: Regenerate. * generated/parity_l1.c: Regenerate. * generated/parity_l16.c: Regenerate. * generated/parity_l2.c: Regenerate. * generated/parity_l4.c: Regenerate. * generated/parity_l8.c: Regenerate. * generated/product_c10.c: Regenerate. * generated/product_c16.c: Regenerate. * generated/product_c17.c: Regenerate. * generated/product_c4.c: Regenerate. * generated/product_c8.c: Regenerate. * generated/product_i1.c: Regenerate. * generated/product_i16.c: Regenerate. * generated/product_i2.c: Regenerate. * generated/product_i4.c: Regenerate. * generated/product_i8.c: Regenerate. * generated/product_r10.c: Regenerate. * generated/product_r16.c: Regenerate. * generated/product_r17.c: Regenerate. * generated/product_r4.c: Regenerate. * generated/product_r8.c: Regenerate. * generated/sum_c10.c: Regenerate. * generated/sum_c16.c: Regenerate. * generated/sum_c17.c: Regenerate. * generated/sum_c4.c: Regenerate. * generated/sum_c8.c: Regenerate. * generated/sum_i1.c: Regenerate. * generated/sum_i16.c: Regenerate. * generated/sum_i2.c: Regenerate. * generated/sum_i4.c: Regenerate. * generated/sum_i8.c: Regenerate. * generated/sum_r10.c: Regenerate. * generated/sum_r16.c: Regenerate. * generated/sum_r17.c: Regenerate. * generated/sum_r4.c: Regenerate. * generated/sum_r8.c: Regenerate. gcc/testsuite/ChangeLog: * gfortran.dg/bound_11.f90: New test.
2023-11-08libgfortran: Remove early return if extent is zero [PR112371]Mikael Morin1-0/+207
Remove the early return present in function templates for transformational functions doing a (masked) reduction of an array along a dimension. This early return, which triggered if the extent in the reduction dimension was zero, was wrong because even if the reduction operation degenerates to a constant value in that case, one has to loop anyway along the other dimensions to initialize every element of the resulting array with that constant value. The case of negative extent (not sure whether it may happen in practice) which was also early returning, is handled by clamping to zero. The offending piece of code was present in several places, and this removes them all. Namely, the impacted m4 files are ifunction.m4 for regular functions and types, ifunction-s.m4 for character minloc and maxloc, and ifunction-s2.m4 for character minval and maxval. PR fortran/112371 libgfortran/ChangeLog: * m4/ifunction.m4 (START_MASKED_ARRAY_FUNCTION): Remove early return if extent is zero or less, and clamp negative value to zero. * m4/ifunction-s.m4 (START_MASKED_ARRAY_FUNCTION): Ditto. * m4/ifunction-s2.m4 (START_MASKED_ARRAY_FUNCTION): Ditto. * generated/iall_i1.c: Regenerate. * generated/iall_i16.c: Regenerate. * generated/iall_i2.c: Regenerate. * generated/iall_i4.c: Regenerate. * generated/iall_i8.c: Regenerate. * generated/iany_i1.c: Regenerate. * generated/iany_i16.c: Regenerate. * generated/iany_i2.c: Regenerate. * generated/iany_i4.c: Regenerate. * generated/iany_i8.c: Regenerate. * generated/iparity_i1.c: Regenerate. * generated/iparity_i16.c: Regenerate. * generated/iparity_i2.c: Regenerate. * generated/iparity_i4.c: Regenerate. * generated/iparity_i8.c: Regenerate. * generated/maxloc1_16_i1.c: Regenerate. * generated/maxloc1_16_i16.c: Regenerate. * generated/maxloc1_16_i2.c: Regenerate. * generated/maxloc1_16_i4.c: Regenerate. * generated/maxloc1_16_i8.c: Regenerate. * generated/maxloc1_16_r10.c: Regenerate. * generated/maxloc1_16_r16.c: Regenerate. * generated/maxloc1_16_r17.c: Regenerate. * generated/maxloc1_16_r4.c: Regenerate. * generated/maxloc1_16_r8.c: Regenerate. * generated/maxloc1_16_s1.c: Regenerate. * generated/maxloc1_16_s4.c: Regenerate. * generated/maxloc1_4_i1.c: Regenerate. * generated/maxloc1_4_i16.c: Regenerate. * generated/maxloc1_4_i2.c: Regenerate. * generated/maxloc1_4_i4.c: Regenerate. * generated/maxloc1_4_i8.c: Regenerate. * generated/maxloc1_4_r10.c: Regenerate. * generated/maxloc1_4_r16.c: Regenerate. * generated/maxloc1_4_r17.c: Regenerate. * generated/maxloc1_4_r4.c: Regenerate. * generated/maxloc1_4_r8.c: Regenerate. * generated/maxloc1_4_s1.c: Regenerate. * generated/maxloc1_4_s4.c: Regenerate. * generated/maxloc1_8_i1.c: Regenerate. * generated/maxloc1_8_i16.c: Regenerate. * generated/maxloc1_8_i2.c: Regenerate. * generated/maxloc1_8_i4.c: Regenerate. * generated/maxloc1_8_i8.c: Regenerate. * generated/maxloc1_8_r10.c: Regenerate. * generated/maxloc1_8_r16.c: Regenerate. * generated/maxloc1_8_r17.c: Regenerate. * generated/maxloc1_8_r4.c: Regenerate. * generated/maxloc1_8_r8.c: Regenerate. * generated/maxloc1_8_s1.c: Regenerate. * generated/maxloc1_8_s4.c: Regenerate. * generated/maxval1_s1.c: Regenerate. * generated/maxval1_s4.c: Regenerate. * generated/maxval_i1.c: Regenerate. * generated/maxval_i16.c: Regenerate. * generated/maxval_i2.c: Regenerate. * generated/maxval_i4.c: Regenerate. * generated/maxval_i8.c: Regenerate. * generated/maxval_r10.c: Regenerate. * generated/maxval_r16.c: Regenerate. * generated/maxval_r17.c: Regenerate. * generated/maxval_r4.c: Regenerate. * generated/maxval_r8.c: Regenerate. * generated/minloc1_16_i1.c: Regenerate. * generated/minloc1_16_i16.c: Regenerate. * generated/minloc1_16_i2.c: Regenerate. * generated/minloc1_16_i4.c: Regenerate. * generated/minloc1_16_i8.c: Regenerate. * generated/minloc1_16_r10.c: Regenerate. * generated/minloc1_16_r16.c: Regenerate. * generated/minloc1_16_r17.c: Regenerate. * generated/minloc1_16_r4.c: Regenerate. * generated/minloc1_16_r8.c: Regenerate. * generated/minloc1_16_s1.c: Regenerate. * generated/minloc1_16_s4.c: Regenerate. * generated/minloc1_4_i1.c: Regenerate. * generated/minloc1_4_i16.c: Regenerate. * generated/minloc1_4_i2.c: Regenerate. * generated/minloc1_4_i4.c: Regenerate. * generated/minloc1_4_i8.c: Regenerate. * generated/minloc1_4_r10.c: Regenerate. * generated/minloc1_4_r16.c: Regenerate. * generated/minloc1_4_r17.c: Regenerate. * generated/minloc1_4_r4.c: Regenerate. * generated/minloc1_4_r8.c: Regenerate. * generated/minloc1_4_s1.c: Regenerate. * generated/minloc1_4_s4.c: Regenerate. * generated/minloc1_8_i1.c: Regenerate. * generated/minloc1_8_i16.c: Regenerate. * generated/minloc1_8_i2.c: Regenerate. * generated/minloc1_8_i4.c: Regenerate. * generated/minloc1_8_i8.c: Regenerate. * generated/minloc1_8_r10.c: Regenerate. * generated/minloc1_8_r16.c: Regenerate. * generated/minloc1_8_r17.c: Regenerate. * generated/minloc1_8_r4.c: Regenerate. * generated/minloc1_8_r8.c: Regenerate. * generated/minloc1_8_s1.c: Regenerate. * generated/minloc1_8_s4.c: Regenerate. * generated/minval1_s1.c: Regenerate. * generated/minval1_s4.c: Regenerate. * generated/minval_i1.c: Regenerate. * generated/minval_i16.c: Regenerate. * generated/minval_i2.c: Regenerate. * generated/minval_i4.c: Regenerate. * generated/minval_i8.c: Regenerate. * generated/minval_r10.c: Regenerate. * generated/minval_r16.c: Regenerate. * generated/minval_r17.c: Regenerate. * generated/minval_r4.c: Regenerate. * generated/minval_r8.c: Regenerate. * generated/product_c10.c: Regenerate. * generated/product_c16.c: Regenerate. * generated/product_c17.c: Regenerate. * generated/product_c4.c: Regenerate. * generated/product_c8.c: Regenerate. * generated/product_i1.c: Regenerate. * generated/product_i16.c: Regenerate. * generated/product_i2.c: Regenerate. * generated/product_i4.c: Regenerate. * generated/product_i8.c: Regenerate. * generated/product_r10.c: Regenerate. * generated/product_r16.c: Regenerate. * generated/product_r17.c: Regenerate. * generated/product_r4.c: Regenerate. * generated/product_r8.c: Regenerate. * generated/sum_c10.c: Regenerate. * generated/sum_c16.c: Regenerate. * generated/sum_c17.c: Regenerate. * generated/sum_c4.c: Regenerate. * generated/sum_c8.c: Regenerate. * generated/sum_i1.c: Regenerate. * generated/sum_i16.c: Regenerate. * generated/sum_i2.c: Regenerate. * generated/sum_i4.c: Regenerate. * generated/sum_i8.c: Regenerate. * generated/sum_r10.c: Regenerate. * generated/sum_r16.c: Regenerate. * generated/sum_r17.c: Regenerate. * generated/sum_r4.c: Regenerate. * generated/sum_r8.c: Regenerate. gcc/testsuite/ChangeLog: * gfortran.dg/bound_10.f90: New test.
2023-11-08libgfortran: Don't skip allocation if size is zero [PR112412]Mikael Morin1-0/+195
In the function template of transformational functions doing a reduction of an array along one dimension, if the passed in result array was unallocated and the calculated allocation size was zero (this is the case of empty result arrays), an early return used to skip the allocation. This change moves the allocation before the early return, so that empty result arrays are not seen as unallocated. This is possible because zero size is explicitly supported by the allocation function. The offending code is present in several places, and this updates them all. More precisely, there is one place in the template for logical reductions, and there are two places in the templates corresponding to masked reductions with respectively array mask and scalar mask. Templates for unmasked reductions, which already allocate before returning, are not affected, but unmasked reductions are checked nevertheless in the testcase. The affected m4 files are ifunction.m4 for regular functions and types, ifunction-s.m4 for character minloc and maxloc, ifunction-s2.m4 for character minval and maxval, and ifunction_logical for logical reductions. PR fortran/112412 libgfortran/ChangeLog: * m4/ifunction.m4 (START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Don't skip allocation if the allocation size is zero. * m4/ifunction-s.m4 (START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Ditto. * m4/ifunction-s2.m4 (START_MASKED_ARRAY_FUNCTION, SCALAR_ARRAY_FUNCTION): Ditto. * m4/ifunction_logical.m4 (START_ARRAY_FUNCTION): Ditto. * generated/all_l1.c: Regenerate. * generated/all_l16.c: Regenerate. * generated/all_l2.c: Regenerate. * generated/all_l4.c: Regenerate. * generated/all_l8.c: Regenerate. * generated/any_l1.c: Regenerate. * generated/any_l16.c: Regenerate. * generated/any_l2.c: Regenerate. * generated/any_l4.c: Regenerate. * generated/any_l8.c: Regenerate. * generated/count_16_l.c: Regenerate. * generated/count_1_l.c: Regenerate. * generated/count_2_l.c: Regenerate. * generated/count_4_l.c: Regenerate. * generated/count_8_l.c: Regenerate. * generated/iall_i1.c: Regenerate. * generated/iall_i16.c: Regenerate. * generated/iall_i2.c: Regenerate. * generated/iall_i4.c: Regenerate. * generated/iall_i8.c: Regenerate. * generated/iany_i1.c: Regenerate. * generated/iany_i16.c: Regenerate. * generated/iany_i2.c: Regenerate. * generated/iany_i4.c: Regenerate. * generated/iany_i8.c: Regenerate. * generated/iparity_i1.c: Regenerate. * generated/iparity_i16.c: Regenerate. * generated/iparity_i2.c: Regenerate. * generated/iparity_i4.c: Regenerate. * generated/iparity_i8.c: Regenerate. * generated/maxloc1_16_i1.c: Regenerate. * generated/maxloc1_16_i16.c: Regenerate. * generated/maxloc1_16_i2.c: Regenerate. * generated/maxloc1_16_i4.c: Regenerate. * generated/maxloc1_16_i8.c: Regenerate. * generated/maxloc1_16_r10.c: Regenerate. * generated/maxloc1_16_r16.c: Regenerate. * generated/maxloc1_16_r17.c: Regenerate. * generated/maxloc1_16_r4.c: Regenerate. * generated/maxloc1_16_r8.c: Regenerate. * generated/maxloc1_16_s1.c: Regenerate. * generated/maxloc1_16_s4.c: Regenerate. * generated/maxloc1_4_i1.c: Regenerate. * generated/maxloc1_4_i16.c: Regenerate. * generated/maxloc1_4_i2.c: Regenerate. * generated/maxloc1_4_i4.c: Regenerate. * generated/maxloc1_4_i8.c: Regenerate. * generated/maxloc1_4_r10.c: Regenerate. * generated/maxloc1_4_r16.c: Regenerate. * generated/maxloc1_4_r17.c: Regenerate. * generated/maxloc1_4_r4.c: Regenerate. * generated/maxloc1_4_r8.c: Regenerate. * generated/maxloc1_4_s1.c: Regenerate. * generated/maxloc1_4_s4.c: Regenerate. * generated/maxloc1_8_i1.c: Regenerate. * generated/maxloc1_8_i16.c: Regenerate. * generated/maxloc1_8_i2.c: Regenerate. * generated/maxloc1_8_i4.c: Regenerate. * generated/maxloc1_8_i8.c: Regenerate. * generated/maxloc1_8_r10.c: Regenerate. * generated/maxloc1_8_r16.c: Regenerate. * generated/maxloc1_8_r17.c: Regenerate. * generated/maxloc1_8_r4.c: Regenerate. * generated/maxloc1_8_r8.c: Regenerate. * generated/maxloc1_8_s1.c: Regenerate. * generated/maxloc1_8_s4.c: Regenerate. * generated/maxval1_s1.c: Regenerate. * generated/maxval1_s4.c: Regenerate. * generated/maxval_i1.c: Regenerate. * generated/maxval_i16.c: Regenerate. * generated/maxval_i2.c: Regenerate. * generated/maxval_i4.c: Regenerate. * generated/maxval_i8.c: Regenerate. * generated/maxval_r10.c: Regenerate. * generated/maxval_r16.c: Regenerate. * generated/maxval_r17.c: Regenerate. * generated/maxval_r4.c: Regenerate. * generated/maxval_r8.c: Regenerate. * generated/minloc1_16_i1.c: Regenerate. * generated/minloc1_16_i16.c: Regenerate. * generated/minloc1_16_i2.c: Regenerate. * generated/minloc1_16_i4.c: Regenerate. * generated/minloc1_16_i8.c: Regenerate. * generated/minloc1_16_r10.c: Regenerate. * generated/minloc1_16_r16.c: Regenerate. * generated/minloc1_16_r17.c: Regenerate. * generated/minloc1_16_r4.c: Regenerate. * generated/minloc1_16_r8.c: Regenerate. * generated/minloc1_16_s1.c: Regenerate. * generated/minloc1_16_s4.c: Regenerate. * generated/minloc1_4_i1.c: Regenerate. * generated/minloc1_4_i16.c: Regenerate. * generated/minloc1_4_i2.c: Regenerate. * generated/minloc1_4_i4.c: Regenerate. * generated/minloc1_4_i8.c: Regenerate. * generated/minloc1_4_r10.c: Regenerate. * generated/minloc1_4_r16.c: Regenerate. * generated/minloc1_4_r17.c: Regenerate. * generated/minloc1_4_r4.c: Regenerate. * generated/minloc1_4_r8.c: Regenerate. * generated/minloc1_4_s1.c: Regenerate. * generated/minloc1_4_s4.c: Regenerate. * generated/minloc1_8_i1.c: Regenerate. * generated/minloc1_8_i16.c: Regenerate. * generated/minloc1_8_i2.c: Regenerate. * generated/minloc1_8_i4.c: Regenerate. * generated/minloc1_8_i8.c: Regenerate. * generated/minloc1_8_r10.c: Regenerate. * generated/minloc1_8_r16.c: Regenerate. * generated/minloc1_8_r17.c: Regenerate. * generated/minloc1_8_r4.c: Regenerate. * generated/minloc1_8_r8.c: Regenerate. * generated/minloc1_8_s1.c: Regenerate. * generated/minloc1_8_s4.c: Regenerate. * generated/minval1_s1.c: Regenerate. * generated/minval1_s4.c: Regenerate. * generated/minval_i1.c: Regenerate. * generated/minval_i16.c: Regenerate. * generated/minval_i2.c: Regenerate. * generated/minval_i4.c: Regenerate. * generated/minval_i8.c: Regenerate. * generated/minval_r10.c: Regenerate. * generated/minval_r16.c: Regenerate. * generated/minval_r17.c: Regenerate. * generated/minval_r4.c: Regenerate. * generated/minval_r8.c: Regenerate. * generated/product_c10.c: Regenerate. * generated/product_c16.c: Regenerate. * generated/product_c17.c: Regenerate. * generated/product_c4.c: Regenerate. * generated/product_c8.c: Regenerate. * generated/product_i1.c: Regenerate. * generated/product_i16.c: Regenerate. * generated/product_i2.c: Regenerate. * generated/product_i4.c: Regenerate. * generated/product_i8.c: Regenerate. * generated/product_r10.c: Regenerate. * generated/product_r16.c: Regenerate. * generated/product_r17.c: Regenerate. * generated/product_r4.c: Regenerate. * generated/product_r8.c: Regenerate. * generated/sum_c10.c: Regenerate. * generated/sum_c16.c: Regenerate. * generated/sum_c17.c: Regenerate. * generated/sum_c4.c: Regenerate. * generated/sum_c8.c: Regenerate. * generated/sum_i1.c: Regenerate. * generated/sum_i16.c: Regenerate. * generated/sum_i2.c: Regenerate. * generated/sum_i4.c: Regenerate. * generated/sum_i8.c: Regenerate. * generated/sum_r10.c: Regenerate. * generated/sum_r16.c: Regenerate. * generated/sum_r17.c: Regenerate. * generated/sum_r4.c: Regenerate. * generated/sum_r8.c: Regenerate. gcc/testsuite/ChangeLog: * gfortran.dg/allocated_4.f90: New test.
2023-11-08RISC-V: Eliminate unused parameter warning.xuli1-1/+1
The parameter orig_fndecl is not used, use anonymous parameters instead. ../.././gcc/gcc/config/riscv/riscv-c.cc: In function ‘bool riscv_check_builtin_call(location_t, vec<unsigned int>, tree, tree, unsigned int, tree_node**)’: ../.././gcc/gcc/config/riscv/riscv-c.cc:207:11: warning: unused parameter ‘orig_fndecl’ [-Wunused-parameter] tree orig_fndecl, unsigned int nargs, tree *args) ^~~~~~~~~~~ gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_check_builtin_call): Eliminate warning.
2023-11-08[i386] APX: Fix ICE due to movti postreload splitter [PR112394]Hongyu Wang3-4/+31
When APX EGPR enabled, the TImode move pattern *movti_internal allows move between gpr and sse reg using constraint pair ("r","Yd"). Then a post-reload splitter transform such move to vec_extractv2di, while under -msse4.1 -mno-avx EGPR is not allowed for its enabled alternative, which caused ICE that insn does not match the constraint. To prevent such ICE, we need to adjust the constraint correspond to "Yd". Add a new constraint "jc" to disable EGPR under -mno-avx. gcc/ChangeLog: PR target/112394 * config/i386/constraints.md (jc): New constraint that prohibits EGPR on -mno-avx. * config/i386/i386.md (*movdi_internal): Change r constraint corresponds to Yd. (*movti_internal): Likewise. gcc/testsuite/ChangeLog: PR target/112394 * gcc.target/i386/pr112394.c: New test.
generated by cgit v1.1 at 2025-09-20 02:12:50 +0000