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1. Use addu16i.d for TARGET_64BIT and suitable immediates.
2. Split one addition with immediate into two addu16i.d or addi.{d/w}
instructions if possible. This can avoid using a temp register w/o
increase the count of instructions.
Inspired by https://reviews.llvm.org/D143710 and
https://reviews.llvm.org/D147222.
Bootstrapped and regtested on loongarch64-linux-gnu. Ok for GCC 14?
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_addu16i_imm12_operand_p): New function prototype.
(loongarch_split_plus_constant): Likewise.
* config/loongarch/loongarch.cc
(loongarch_addu16i_imm12_operand_p): New function.
(loongarch_split_plus_constant): Likewise.
* config/loongarch/loongarch.h (ADDU16I_OPERAND): New macro.
(DUAL_IMM12_OPERAND): Likewise.
(DUAL_ADDU16I_OPERAND): Likewise.
* config/loongarch/constraints.md (La, Lb, Lc, Ld, Le): New
constraint.
* config/loongarch/predicates.md (const_dual_imm12_operand): New
predicate.
(const_addu16i_operand): Likewise.
(const_addu16i_imm12_di_operand): Likewise.
(const_addu16i_imm12_si_operand): Likewise.
(plus_di_operand): Likewise.
(plus_si_operand): Likewise.
(plus_si_extend_operand): Likewise.
* config/loongarch/loongarch.md (add<mode>3): Convert to
define_insn_and_split. Use plus_<mode>_operand predicate
instead of arith_operand. Add alternatives for La, Lb, Lc, Ld,
and Le constraints.
(*addsi3_extended): Convert to define_insn_and_split. Use
plus_si_extend_operand instead of arith_operand. Add
alternatives for La and Le alternatives.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/add-const.c: New test.
* gcc.target/loongarch/stack-check-cfa-1.c: Adjust for stack
frame size change.
* gcc.target/loongarch/stack-check-cfa-2.c: Likewise.
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This is for upcoming work in this area.
gcc/ChangeLog:
* value-range.h (Value_Range::Value_Range): New.
(Value_Range::contains_p): New.
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The discriminator in vrange cannot change after construction,
similarly the number of allocated ranges in an irange. It's best to
make them constant to avoid invalid changes.
gcc/ChangeLog:
* value-range.h (class vrange): Make m_discriminator const.
(class irange): Make m_max_ranges const. Adjust constructors
accordingly.
(class unsupported_range): Construct vrange appropriately.
(class frange): Same.
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under the architecture and use the default definition instead.
In some cases, setting this macro as the default can reduce the number of conditional
branch instructions.
gcc/ChangeLog:
* config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove the macro
definition.
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set instructions.
gcc/ChangeLog:
* doc/extend.texi: Add section for LoongArch Base Built-in functions.
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gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_first_stack_step): Make codes more
readable.
(riscv_expand_epilogue): Likewise.
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Here when level lowering the bound ttp TT<typename T::type> via the
substitution T=C, we're neglecting to canonicalize (and thereby strip
of simple typedefs) the substituted template arguments {A<int>} before
determining the new canonical type via hash table lookup. This leads to
a hash mismatch ICE for the two equivalent types TT<int> and TT<A<int>>
since iterative_hash_template_arg assumes type arguments are already
canonicalized.
We can fix this by canonicalizing or coercing the substituted arguments
directly, but seeing as creation and ordinary substitution of bound ttps
both go through lookup_template_class, which in turn performs the desired
coercion/canonicalization, it seems preferable to make this code path go
through lookup_template_class as well.
PR c++/109531
gcc/cp/ChangeLog:
* pt.cc (tsubst) <case BOUND_TEMPLATE_TEMPLATE_PARM>:
In the level-lowering case just use lookup_template_class
to rebuild the bound ttp.
gcc/testsuite/ChangeLog:
* g++.dg/template/canon-type-20.C: New test.
* g++.dg/template/ttp36.C: New test.
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The stack that save-restore reserves is not well accumulated in stack allocation and deallocation.
This patch allows less instructions to be used in stack allocation and deallocation if save-restore enabled.
before patch:
bar:
call t0,__riscv_save_4
addi sp,sp,-64
...
li t0,-12288
addi t0,t0,-1968 # optimized out after patch
add sp,sp,t0 # prologue
...
li t0,12288 # epilogue
addi t0,t0,2000 # optimized out after patch
add sp,sp,t0
...
addi sp,sp,32
tail __riscv_restore_4
after patch:
bar:
call t0,__riscv_save_4
addi sp,sp,-2032
...
li t0,-12288
add sp,sp,t0 # prologue
...
li t0,12288 # epilogue
add sp,sp,t0
...
addi sp,sp,2032
tail __riscv_restore_4
gcc/
* config/riscv/riscv.cc (riscv_expand_prologue): Consider save-restore in
stack allocation.
(riscv_expand_epilogue): Consider save-restore in stack deallocation.
gcc/testsuite
* gcc.target/riscv/stack_save_restore.c: New test.
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gate_hoist_loads is defined before its usage so there is
no reason for the declaration (prototype) to be there.
Committed as obvious after a bootstrap/test on x86_64-linux-gnu with no regressions.
gcc/ChangeLog:
* tree-ssa-phiopt.cc (gate_hoist_loads): Remove
prototype.
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A warning pass should not be exporting global ranges it finds along
the way, because that will alter the behavior of future passes.
The reason the present behavior was there was because of some long ago
forgotten regression in another pass. This regression is no longer
there, and if there's ever any fallout from cleaning this up, we can
address it in the pass that is missing some information.
gcc/ChangeLog:
* gimple-ssa-warn-alloca.cc (pass_walloca::execute): Do not export
global ranges.
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These functions are NOPs on the soft-float ABIs. Since we're already
forcing the ISA, let's just force the ABI too.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadfmv-fmv.c: Force the ilp32d ABI.
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The RVV test harness currently sets the ISA according to the target
tuple, but doesn't also set the ABI. This just sets the ABI to match
the ISA, though we should really also be respecting the user's specific
ISA to test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp (gcc_mabi): New variable.
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The test case that was added is rv64i-specific, as there's better ways
to generate this code on rv32i (where the long/int cast is a NOP) and on
rv64i_zba (where we have word shifts). This renames the original test
case and adds two more for those targets.
gcc/testsuite/ChangeLog:
PR target/106602
* gcc.target/riscv/pr106602.c: Moved to...
* gcc.target/riscv/pr106602-rv64i.c: ...here.
* gcc.target/riscv/pr106602-rv32i.c: New test.
* gcc.target/riscv/pr106602-rv64i_zba.c: New test.
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gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_first_stack_step): Add a new function
parameter remaining_size.
(riscv_compute_frame_info): Adapt new riscv_first_stack_step interface.
(riscv_expand_prologue): Likewise.
(riscv_expand_epilogue): Likewise.
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gcc/ChangeLog:
* config/riscv/bitmanip.md (rotrsi3_sext): Support generating
roriw for constant counts.
* rtl.h (reverse_rotate_by_imm_p): Add function declartion
* simplify-rtx.cc (reverse_rotate_by_imm_p): New function.
(simplify_context::simplify_binary_operation_1): Use it.
* expmed.cc (expand_shift_1): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-04.c: New test.
* gcc.target/riscv/zbb-rol-ror-05.c: New test.
* gcc.target/riscv/zbb-rol-ror-06.c: New test.
* gcc.target/riscv/zbb-rol-ror-07.c: New test.
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gcc/ada/ChangeLog:
* gnatvsn.ads: Bump Library_Version to 14.
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2023-04-17 Jakub Jelinek <jakub@redhat.com>
* BASE-VER: Set to 14.0.0.
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109318)
It turns out that since addition of the code that can identify globals
which are only read from, the code that keeps track of the references
can decrement their count for the same calls, once during IPA-CP and
then again during inlining. Fixed by adding a special flag to the
pass-through variant and simply wiping out the reference to the
refdesc structure from the constant ones.
Moreover, during debugging of the issue I have discovered that the
code removing references could remove a reference associated with the
same statement but of a wrong type. In all cases it wanted to remove
an IPA_REF_ADDR reference so removing a lesser one instead should do
no harm in practice, but we should try to be consistent and so this
patch extends symtab_node::find_reference so that it searches for a
reference of a given type only.
gcc/ChangeLog:
2023-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/107769
PR ipa/109318
* cgraph.h (symtab_node::find_reference): Add parameter use_type.
* ipa-prop.h (ipa_pass_through_data): New flag refdesc_decremented.
(ipa_zap_jf_refdesc): New function.
(ipa_get_jf_pass_through_refdesc_decremented): Likewise.
(ipa_set_jf_pass_through_refdesc_decremented): Likewise.
* ipa-cp.cc (ipcp_discover_new_direct_edges): Provide a value for
the new parameter of find_reference.
(adjust_references_in_caller): Likewise. Make sure the constant jump
function is not used to decrement a refdec counter again. Only
decrement refdesc counters when the pass_through jump function allows
it. Added a detailed dump when decrementing refdesc counters.
* ipa-prop.cc (ipa_print_node_jump_functions_for_edge): Dump new flag.
(ipa_set_jf_simple_pass_through): Initialize the new flag.
(ipa_set_jf_unary_pass_through): Likewise.
(ipa_set_jf_arith_pass_through): Likewise.
(remove_described_reference): Provide a value for the new parameter of
find_reference.
(update_jump_functions_after_inlining): Zap refdesc of new jfunc if
the previous pass_through had a flag mandating that we do so.
(propagate_controlled_uses): Likewise. Only decrement refdesc
counters when the pass_through jump function allows it.
(ipa_edge_args_sum_t::duplicate): Provide a value for the new
parameter of find_reference.
(ipa_write_jump_function): Assert the new flag does not have to be
streamed.
* symtab.cc (symtab_node::find_reference): Add parameter use_type, use
it in searching.
gcc/testsuite/ChangeLog:
2023-04-06 Martin Jambor <mjambor@suse.cz>
PR ipa/107769
PR ipa/109318
* gcc.dg/ipa/pr109318.c: New test.
* gcc.dg/lto/pr107769_0.c: Likewise.
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AmpereOne (-mcpu=ampere1) breaks LDP instructions into two uops.
Given the chance that this causes instructions to slip into the next
decoding cycle and the additional overheads when handling
cacheline-crossing LDP instructions, we disable the generation of LDP
isntructions through the tuning structure from instruction combining
(such as in peephole2).
Given the code-density benefits in builtins and prologue/epilogue
expansion, we allow LDPs there.
This commit:
* adds a new tuning option AARCH64_EXTRA_TUNE_NO_LDP_COMBINE
* allows -moverride=tune=... to override this
These changes are benchmark-driven, yielding the following changes
(with a net-overall improvement):
503.bwaves_r. -0.88%
507.cactuBSSN_r 0.35%
508.namd_r 3.09%
510.parest_r -2.99%
511.povray_r 5.54%
519.lbm_r 15.83%
521.wrf_r 0.56%
526.blender_r 2.47%
527.cam4_r 0.70%
538.imagick_r 0.00%
544.nab_r -0.33%
549.fotonik3d_r. -0.42%
554.roms_r 0.00%
-------------------------
= total 1.79%
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-Authored-By: Di Zhao <di.zhao@amperecomputing.com>
gcc/ChangeLog:
* config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION):
Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE.
* config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
Check for the above tuning option when processing loads.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ampere1-no_ldp_combine.c: New test.
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With
make check-gcc check-g++ -j32 -k RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mavx,-m32/-mavx512f,-m32/-march=cascadelake,-m64,-m64/-mavx,-m64/-mavx512f,-m64/-march=cascadelake\}
+vect.exp=vect-simd-clone*'
the vect-simd-clone-1[678]f.c tests fail with -m32/-mavx512f and -m32/-march=cascadelake,
in that case there are zero matches rather than the 4 expected for ia32.
-m64/-mavx512f and -m64/-march=cascadelake works fine though (2 expected
matches).
So, the following patch just adds -mno-avx512f for x86 non-lp64.
2023-04-17 Jakub Jelinek <jakub@redhat.com>
* gcc.dg/vect/vect-simd-clone-16f.c: Add -mno-avx512f for non-lp64 x86.
* gcc.dg/vect/vect-simd-clone-17f.c: Likewise.
* gcc.dg/vect/vect-simd-clone-18f.c: Likewise.
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VRP queues edges to process late for updating global ranges for
__builtin_unreachable. But this interferes with edge removal
from substitute_and_fold. The following deals with this by
looking up the edge with source/dest block indices which do not
become stale.
PR tree-optimization/109524
* tree-vrp.cc (remove_unreachable::m_list): Change to a
vector of pairs of block indices.
(remove_unreachable::maybe_register_block): Adjust.
(remove_unreachable::remove_and_update_globals): Likewise.
Deal with removed blocks.
* g++.dg/pr109524.C: New testcase.
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Hi,
As PR108809 mentioned, vec_xl_len_r and vec_xst_len_r are tested
in gcc.target/powerpc/builtins-5-p9-runnable.c.
The vector operand of these two bifs are different from the view
of v16_int8 between BE and LE, even it is same from the view of
128bits(uint128/V1TI).
The test case gcc.target/powerpc/builtins-5-p9-runnable.c was
written for LE environment, this patch updates it for BE.
Tested on ppc64 BE and LE.
Is this ok for trunk?
BR,
Jeff (Jiufu)
gcc/testsuite/ChangeLog:
PR testsuite/108809
* gcc.target/powerpc/builtins-5-p9-runnable.c: Update for BE.
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gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-2.c: Adjust include way
for riscv_vector.h
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: Add missing
-mabi.
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There are sorts of shortcut codegen for the RVV mask insn. For
example.
vmxor vd, va, va => vmclr vd.
We would like to add more optimization like this but first of all
we must add the tests for the existing shortcut optimization, to
ensure we don't break existing optimization from underlying shortcut
optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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Recently the conditional move expander's predicates were loosened for the
benefit of the THEAD processors. In particular one operand that was
previously "register_operand" is now "reg_or_0_operand". That's fine for
THEAD, but breaks for SFB which requires a register for that operand.
This results in an ICE when compiling the testcase an SFB target such as
the sifive s76.
This change adjusts the expansion code slightly to copy the value into
a register for SFB.
Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
configured to enable SFB by default.
PR target/109508
gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): For
TARGET_SFB_ALU, force the true arm into a register.
gcc/testsuite
* gcc.target/riscv/pr109508.c: New test.
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PR target/54816 is now fixed on mainline. This adds a test case to
check that it doesn't regress in future. Tested with a cross compiler
to avr-elf. Committed as obvious.
2023-04-16 Roger Sayle <roger@nextmovesoftware.com>
gcc/testsuite/ChangeLog
PR target/54816
* gcc.target/avr/pr54816.c: New test case.
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gcc/ada/
PR bootstrap/109510
* gcc-interface/decl.cc (gnat_to_gnu_entity) <types>: Do not reset
align to zero in any case. Set TYPE_USER_ALIGN on the type only if
it is an aggregate type, or else a type whose default alignment is
specifically capped on selected platforms.
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2023-04-15 John David Anglin <danglin@gcc.gnu.org>
gcc/ChangeLog:
PR target/104989
* config/pa/pa-protos.h (pa_function_arg_size): Update prototype.
* config/pa/pa.cc (pa_function_arg): Return NULL_RTX if argument
size is zero.
(pa_arg_partial_bytes): Don't call pa_function_arg_size twice.
(pa_function_arg_size): Change return type to int. Return zero
for arguments larger than 1 GB. Update comments.
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We were assuming that the result of evaluation of TARGET_EXPR_INITIAL would
always be the new value of the temporary, but that's not necessarily true
when the initializer is complex (i.e. target_expr_needs_replace). In that
case evaluating the initializer initializes the temporary as a side-effect.
PR c++/109357
gcc/cp/ChangeLog:
* constexpr.cc (cxx_eval_constant_expression) [TARGET_EXPR]:
Check for complex initializer.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/constexpr-dtor15.C: New test.
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The following patch is just a dumb improvement, gets rid of 2 unnecessary
instructions on both the PR's original testcase and on the two reduced ones,
both on -mcpu=neoverse-v1 and -mavx512f.
The thing is, if we have args_len (args_len >= 2) unique PHI arguments,
we need only args_len - 1 COND_EXPRs to expand the PHI, because first
COND_EXPR can merge 2 unique arguments and all the following ones merge
another unique argument with the previously merged arguments,
while the code for mysterious reasons was always emitting args_len
COND_EXPRs, where the first COND_EXPR merged the first and second unique
arguments, the second COND_EXPR merged the second unique argument with
result of merging the first and second unique arguments and the rest was
already expectable, nth COND_EXPR for n > 2 merged the nth unique argument
with result of merging the previous unique arguments.
Now, in my understanding, the bb_predicate for bb's predecessor need to
form a disjunct set which together creates the successor's bb_predicate,
so I don't see why we'd need to check all the bb_predicates, if we check
all but one then when all those other ones are false the last bb_predicate
is necessarily true. Given that the code attempts to sort argument with
most occurrences (so likely most complex combined predicate) last, I chose
not to test that last argument's predicate.
So e.g. on the testcase from comment 47 in the PR:
void
foo (int *f, int d, int e)
{
for (int i = 0; i < 1024; i++)
{
int a = f[i];
int t;
if (a < 0)
t = 1;
else if (a < e)
t = 1 - a * d;
else
t = 0;
f[i] = t;
}
}
we used to emit:
_7 = a_10 < 0;
_21 = a_10 >= 0;
_22 = a_10 < e_11(D);
_23 = _21 & _22;
_26 = a_10 >= e_11(D);
_27 = _21 & _26;
_ifc__42 = _7 ? 1 : t_13;
_ifc__43 = _23 ? t_13 : _ifc__42;
t_6 = _27 ? 0 : _ifc__43;
while the following patch changes it to:
_7 = a_10 < 0;
_21 = a_10 >= 0;
_22 = a_10 < e_11(D);
_23 = _21 & _22;
_ifc__42 = _23 ? t_13 : 0;
t_6 = _7 ? 1 : _ifc__42;
which I believe should be sufficient for a PHI <1, t_13, 0>.
I've gathered some statistics and on x86_64-linux and i686-linux
bootstraps/regtests, this code triggers:
92 4 4
112 2 4
141 3 4
4046 3 3
(where 2nd number is args_len and 3rd argument EDGE_COUNT (bb->preds)
and first argument count of those from sort | uniq -c | sort -n).
In all these cases the patch should squeze one extra COND_EXPR and
its associated predicate (the latter only if it wasn't used elsewhere).
Incrementally, I think we should try to perform some analysis on which
predicates depend on inverses of other predicates and if possible try
to sort the arguments better and omit testing unnecessary predicates.
So essentially for the above testcase deconstruct it back to:
_7 = a_10 < 0;
_22 = a_10 < e_11(D);
_ifc__42 = _22 ? t_13 : 0;
t_6 = _7 ? 1 : _ifc__42;
which is like what this patch produces, but with the & a_10 >= 0 part
removed, because the last predicate is a_10 < 0 and so testing a_10 >= 0
on what appears on the false branch doesn't make sense.
But I'm afraid that will take more work than is doable in stage4 right now.
2023-04-15 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109154
* tree-if-conv.cc (predicate_scalar_phi): For complex PHIs, emit just
args_len - 1 COND_EXPRs rather than args_len. Formatting fix.
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When long double is 64-bit wide, as on vxworks, the rs6000 backend
defines neither the __ibm128 type nor the __SIZEOF_IBM128__ macro, but
pr99708.c expected both to be always defined. Adjust the test to
match the implementation.
Co-Authored-By: Kewen Lin <linkw@linux.ibm.com>
for gcc/testsuite/ChangeLog
PR target/99708
* gcc.target/powerpc/pr99708.c: Accept lack of
__SIZEOF_IBM128__ when long double is 64-bit wide.
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Here we hit the MEM_REF case, with its arg an ADDR_EXPR, but had no handling
for that and wrongly assumed it would be a reference to a local variable.
This patch overhauls the logic for deciding whether the target is something
to warn about so that we only warn if we specifically recognize the target
as non-local. None of the existing tests regress as a result.
PR c++/109514
gcc/ChangeLog:
* gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores):
Overhaul lhs_ref.ref analysis.
gcc/testsuite/ChangeLog:
* g++.dg/warn/Wdangling-pointer-6.C: New test.
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gcc/fortran/ChangeLog:
PR fortran/109511
* simplify.cc (gfc_simplify_set_exponent): Fix implementation of
compile-time simplification of intrinsic SET_EXPONENT for argument
X < 1 and for I < 0.
gcc/testsuite/ChangeLog:
PR fortran/109511
* gfortran.dg/set_exponent_1.f90: New test.
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The Aarch64 back-end now asserts that the main variant of scalar types
has TYPE_USER_ALIGN cleared, and that's not the case for scalar types
declared with a confirming alignment clause in Ada.
gcc/ada/
PR bootstrap/109510
* gcc-interface/decl.cc (gnat_to_gnu_entity) <types>: Reset align
to zero if its value is equal to TYPE_ALIGN and the type is scalar.
Set TYPE_USER_ALIGN on the type only if align is positive.
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The following reverts the s/avx_runtime/avx/ changes I've done,
they were wrong.
* gcc.dg/vect/vect-simd-clone-16e.c: Revert back to
checking avx_runtime in dump scanning.
* gcc.dg/vect/vect-simd-clone-17e.c: Likewise.
* gcc.dg/vect/vect-simd-clone-18e.c: Likewise.
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2023-04-14 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/104272
* gfortran.h : Add expr3_not_explicit bit field to gfc_code.
* resolve.cc (resolve_allocate_expr): Set bit field when the
default initializer is applied to expr3.
* trans-stmt.cc (gfc_trans_allocate): If expr3_not_explicit is
set, do not deallocate expr3.
gcc/testsuite/
PR fortran/104272
* gfortran.dg/class_result_8.f90 : Number of builtin_frees down
from 6 to 5 without memory leaks.
* gfortran.dg/finalize_52.f90: New test
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The following fixes a check that should have rejected vectorizing
a conversion between a mask and non-mask type. Those should be
done via pattern statements.
PR tree-optimization/109502
* tree-vect-stmts.cc (vectorizable_assignment): Fix
check for conversion between mask and non-mask types.
* gcc.dg/vect/pr109502.c: New testcase.
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This replaces i686*-*-* && { ! lp64 } with the appropriate
{ i?86-*-* x86_64-*-* } && { ! lp64 } for the testcases and
also amends the e variants checking last variant for avx.
I've used avx in the dump scanning, not avx_runtime, since
the dumps get produced when one would not execute but only
compile them. The f varaints lack AVX checking, I didn't
rectify this with this patch.
* gcc.dg/vect/vect-simd-clone-16e.c: Fix x86 lp64 checking
and add missing avx guard.
* gcc.dg/vect/vect-simd-clone-17e.c: Likewise.
* gcc.dg/vect/vect-simd-clone-18e.c: Likewise.
* gcc.dg/vect/vect-simd-clone-16f.c: Fix x86 lp64 checking.
* gcc.dg/vect/vect-simd-clone-17f.c: Likewise.
* gcc.dg/vect/vect-simd-clone-18f.c: Likewise.
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The following testcase is miscompiled on riscv since the addition
of *mvconst_internal define_insn_and_split.
We have:
(insn 36 35 39 2 (set (mem/c:SI (plus:SI (reg/f:SI 65 frame)
(const_int -64 [0xffffffffffffffc0])) [2 S4 A128])
(reg:SI 166)) "pr109040.c":9:11 178 {*movsi_internal}
(expr_list:REG_DEAD (reg:SI 166)
(nil)))
(insn 39 36 40 2 (set (reg:SI 171)
(zero_extend:SI (mem/c:HI (plus:SI (reg/f:SI 65 frame)
(const_int -64 [0xffffffffffffffc0])) [0 S2 A128]))) "pr109040.c":9:11 111 {*zero_extendhisi2}
(nil))
and RTL DSE's replace_read since r0-86337-g18b526e806ab6455 handles
even different modes like in the above case, and so it optimizes it into:
(insn 47 35 39 2 (set (reg:HI 175)
(subreg:HI (reg:SI 166) 0)) "pr109040.c":9:11 179 {*movhi_internal}
(expr_list:REG_DEAD (reg:SI 166)
(nil)))
(insn 39 47 40 2 (set (reg:SI 171)
(zero_extend:SI (reg:HI 175))) "pr109040.c":9:11 111 {*zero_extendhisi2}
(expr_list:REG_DEAD (reg:HI 175)
(nil)))
Pseudo 166 is result of AND with 0x8084c constant (forced into a register).
Combine attempts to combine the AND with the insn 47 above created by DSE,
and turns it because of WORD_REGISTER_OPERATIONS and its assumption that all
the subword operations are actually done on word mode into:
(set (subreg:SI (reg:HI 175) 0)
(and:SI (reg:SI 167 [ m ])
(reg:SI 168)))
and later on the ZERO_EXTEND is thrown away.
We then see
(and:SI (subreg:SI (reg:HI 175) 0) (const_int 0x84c))
and optimize that into
(subreg:SI (and:HI (reg:HI 175) (const_int 0x84c)) 0)
which is still fine, in WORD_REGISTER_OPERATIONS the AND in HImode
will set all upper bits up to BITS_PER_WORD to zeros.
But later on simplify_binary_operation_1 or simplify_and_const_int_1
sees that because nonzero_bits ((reg:HI 175), HImode) == 0x84c, we can
optimize the AND into (reg:HI 175). That isn't correct, because while
the low 16 bits of that REG are known to have all bits but 0x84c cleared,
we don't know that all the upper 16 bits are all clear as well.
So, for WORD_REGISTER_OPERATIONS for integral modes smaller than word mode,
we need to check all bits from word_mode in nonzero_bits for the optimizations.
2023-04-14 Jeff Law <jlaw@ventanamicro.com>
Jakub Jelinek <jakub@redhat.com>
PR target/108947
PR target/109040
* combine.cc (simplify_and_const_int_1): Compute nonzero_bits in
word_mode rather than mode if WORD_REGISTER_OPERATIONS and mode is
smaller than word_mode.
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case AND>: Likewise.
* gcc.dg/pr108947.c: New test.
* gcc.c-torture/execute/pr109040.c: New test.
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On Thu, Apr 13, 2023 at 06:35:07AM -0600, Jeff Law wrote:
> Bootstrap was successful with v3, but there's hundreds of testsuite failures
> due to the simplify-rtx hunk. compile/20070520-1.c for example when
> compiled with: -O3 -funroll-loops -march=rv64gc -mabi=lp64d
>
> Thursdays are my hell day. It's unlikely I'd be able to look at this at all
> today.
So, seems to me this is because loop-iv.cc asks for invalid RTL to be
simplified, it calls simplify_gen_binary (AND, SImode,
(subreg:SI (plus:DI (reg:DI 289 [ ivtmp_312 ])
(const_int 4294967295 [0xffffffff])) 0),
(const_int 4294967295 [0xffffffff]))
but 0xffffffff is not valid SImode CONST_INT, and unlike previously
we no longer on WORD_REGISTER_OPERATIONS targets which have DImode
word_mode optimize that into the op0, so the invalid constant is emitted
into the IL and checking fails.
The following patch fixes that (and we optimize that & -1 away even earlier
with that).
2023-04-14 Jakub Jelinek <jakub@redhat.com>
* loop-iv.cc (iv_number_of_iterations): Use gen_int_mode instead
of GEN_INT.
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The case file-CWE-1341-example.c checkes [CWE-1341](`double-fclose`).
While on some systems, besides [CWE-1341], a message of [CWE-415] is
also reported. On those systems, attribute `malloc` may be attached on
fopen:
```
# 258 "/usr/include/stdio.h" 3 4
extern FILE *fopen (const char *__restrict __filename,
const char *__restrict __modes)
__attribute__ ((__malloc__)) __attribute__ ((__malloc__ (fclose, 1))) ;
or say: __attribute_malloc__ __attr_dealloc_fclose __wur;
```
See (PR analyzer/108722) for future fix in the analyzer.
This workaround patch adds -Wno-analyzer-double-free to this case.
gcc/testsuite/ChangeLog:
PR analyzer/108722
* gcc.dg/analyzer/file-CWE-1341-example.c: Update.
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gcc/fortran/ChangeLog:
PR fortran/109492
* trans-expr.cc (gfc_conv_power_op): Use absu_hwi and
unsigned HOST_WIDE_INT for portability.
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r13-6098-g46711ff8e60d64 made make_typename_type no longer ignore
non-types during the lookup, unless the TYPENAME_TYPE in question was
followed by the :: scope resolution operator. But there is another
exception to this rule: we need to ignore non-types during the lookup
also if the TYPENAME_TYPE was named with a tag other than 'typename',
such as 'struct' or 'enum', since in that case we're dealing with an
elaborated-type-specifier and so [basic.lookup.elab] applies. This
patch implements this additional exception.
PR c++/109420
gcc/cp/ChangeLog:
* decl.cc (make_typename_type): Also ignore non-types during the
lookup if tag_type corresponds to an elaborated-type-specifier.
* pt.cc (tsubst) <case TYPENAME_TYPE>: Pass class_type or
enum_type as tag_type to make_typename_type accordingly instead
of always passing typename_type.
gcc/testsuite/ChangeLog:
* g++.dg/template/typename27.C: New test.
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An incomplete type argument to several traits is specified to be undefined
behavior in the library; since it's a compile-time property, we diagnose
it. But apparently some code was relying on the previous behavior of not
diagnosing. So let's make it a permerror.
The assert in cxx_incomplete_type_diagnostic didn't like that, and I don't
see the point of having the assert, so let's just remove it.
PR c++/109277
gcc/cp/ChangeLog:
* semantics.cc (check_trait_type): Handle incomplete type directly.
* typeck2.cc (cxx_incomplete_type_diagnostic): Remove assert.
gcc/testsuite/ChangeLog:
* g++.dg/ext/is_convertible5.C: New test.
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Like other diagnostic functions that might be silenced by options, it should
return whether or not it actually emitted a diagnostic.
gcc/cp/ChangeLog:
* typeck2.cc (cxx_incomplete_type_diagnostic): Return bool.
* cp-tree.h (cxx_incomplete_type_diagnostic): Adjust.
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