| Age | Commit message (Collapse) | Author | Files | Lines |
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This patch adds the unary_n shape description.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_n): New.
* config/arm/arm-mve-builtins-shapes.h (unary_n): New.
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Factorize vdup builtins so that they use parameterized names.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY)
(MVE_FP_N_VDUPQ_ONLY): New.
(mve_insn): Add vdupq.
* config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vdupq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vdupq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vdupq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
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Implement vrev16q, vrev32q, vrev64q using the new MVE builtins
framework.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q):
New.
* config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm_mve.h (vrev16q): Remove.
(vrev32q): Remove.
(vrev64q): Remove.
(vrev64q_m): Remove.
(vrev16q_m): Remove.
(vrev32q_m): Remove.
(vrev16q_x): Remove.
(vrev32q_x): Remove.
(vrev64q_x): Remove.
(vrev64q_f16): Remove.
(vrev64q_f32): Remove.
(vrev32q_f16): Remove.
(vrev16q_s8): Remove.
(vrev32q_s8): Remove.
(vrev32q_s16): Remove.
(vrev64q_s8): Remove.
(vrev64q_s16): Remove.
(vrev64q_s32): Remove.
(vrev64q_u8): Remove.
(vrev64q_u16): Remove.
(vrev64q_u32): Remove.
(vrev32q_u8): Remove.
(vrev32q_u16): Remove.
(vrev16q_u8): Remove.
(vrev64q_m_u8): Remove.
(vrev64q_m_s8): Remove.
(vrev64q_m_u16): Remove.
(vrev64q_m_s16): Remove.
(vrev64q_m_u32): Remove.
(vrev64q_m_s32): Remove.
(vrev16q_m_s8): Remove.
(vrev32q_m_f16): Remove.
(vrev16q_m_u8): Remove.
(vrev32q_m_s8): Remove.
(vrev64q_m_f16): Remove.
(vrev32q_m_u8): Remove.
(vrev32q_m_s16): Remove.
(vrev64q_m_f32): Remove.
(vrev32q_m_u16): Remove.
(vrev16q_x_s8): Remove.
(vrev16q_x_u8): Remove.
(vrev32q_x_s8): Remove.
(vrev32q_x_s16): Remove.
(vrev32q_x_u8): Remove.
(vrev32q_x_u16): Remove.
(vrev64q_x_s8): Remove.
(vrev64q_x_s16): Remove.
(vrev64q_x_s32): Remove.
(vrev64q_x_u8): Remove.
(vrev64q_x_u16): Remove.
(vrev64q_x_u32): Remove.
(vrev32q_x_f16): Remove.
(vrev64q_x_f16): Remove.
(vrev64q_x_f32): Remove.
(__arm_vrev16q_s8): Remove.
(__arm_vrev32q_s8): Remove.
(__arm_vrev32q_s16): Remove.
(__arm_vrev64q_s8): Remove.
(__arm_vrev64q_s16): Remove.
(__arm_vrev64q_s32): Remove.
(__arm_vrev64q_u8): Remove.
(__arm_vrev64q_u16): Remove.
(__arm_vrev64q_u32): Remove.
(__arm_vrev32q_u8): Remove.
(__arm_vrev32q_u16): Remove.
(__arm_vrev16q_u8): Remove.
(__arm_vrev64q_m_u8): Remove.
(__arm_vrev64q_m_s8): Remove.
(__arm_vrev64q_m_u16): Remove.
(__arm_vrev64q_m_s16): Remove.
(__arm_vrev64q_m_u32): Remove.
(__arm_vrev64q_m_s32): Remove.
(__arm_vrev16q_m_s8): Remove.
(__arm_vrev16q_m_u8): Remove.
(__arm_vrev32q_m_s8): Remove.
(__arm_vrev32q_m_u8): Remove.
(__arm_vrev32q_m_s16): Remove.
(__arm_vrev32q_m_u16): Remove.
(__arm_vrev16q_x_s8): Remove.
(__arm_vrev16q_x_u8): Remove.
(__arm_vrev32q_x_s8): Remove.
(__arm_vrev32q_x_s16): Remove.
(__arm_vrev32q_x_u8): Remove.
(__arm_vrev32q_x_u16): Remove.
(__arm_vrev64q_x_s8): Remove.
(__arm_vrev64q_x_s16): Remove.
(__arm_vrev64q_x_s32): Remove.
(__arm_vrev64q_x_u8): Remove.
(__arm_vrev64q_x_u16): Remove.
(__arm_vrev64q_x_u32): Remove.
(__arm_vrev64q_f16): Remove.
(__arm_vrev64q_f32): Remove.
(__arm_vrev32q_f16): Remove.
(__arm_vrev32q_m_f16): Remove.
(__arm_vrev64q_m_f16): Remove.
(__arm_vrev64q_m_f32): Remove.
(__arm_vrev32q_x_f16): Remove.
(__arm_vrev64q_x_f16): Remove.
(__arm_vrev64q_x_f32): Remove.
(__arm_vrev16q): Remove.
(__arm_vrev32q): Remove.
(__arm_vrev64q): Remove.
(__arm_vrev64q_m): Remove.
(__arm_vrev16q_m): Remove.
(__arm_vrev32q_m): Remove.
(__arm_vrev16q_x): Remove.
(__arm_vrev32q_x): Remove.
(__arm_vrev64q_x): Remove.
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Factorize vrev16q vrev32q vrev64q so that they use generic builtin
names.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
(MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
(MVE_FP_M_VREV32Q_ONLY): New iterators.
(mve_insn): Add vrev16q, vrev32q, vrev64q.
* config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this
(mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
(mve_vrev64q_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vrev32q_<supf><mode>): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev16q_<supf>v16qi): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev64q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev32q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev16q_m_<supf>v16qi): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
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Implement vcmp using the new MVE builtins framework.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-functions.h (class
unspec_based_mve_function_exact_insn_vcmp): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vcmp.
* config/arm/arm_mve.h (vcmpneq): Remove.
(vcmphiq): Remove.
(vcmpeqq): Remove.
(vcmpcsq): Remove.
(vcmpltq): Remove.
(vcmpleq): Remove.
(vcmpgtq): Remove.
(vcmpgeq): Remove.
(vcmpneq_m): Remove.
(vcmphiq_m): Remove.
(vcmpeqq_m): Remove.
(vcmpcsq_m): Remove.
(vcmpcsq_m_n): Remove.
(vcmpltq_m): Remove.
(vcmpleq_m): Remove.
(vcmpgtq_m): Remove.
(vcmpgeq_m): Remove.
(vcmpneq_s8): Remove.
(vcmpneq_s16): Remove.
(vcmpneq_s32): Remove.
(vcmpneq_u8): Remove.
(vcmpneq_u16): Remove.
(vcmpneq_u32): Remove.
(vcmpneq_n_u8): Remove.
(vcmphiq_u8): Remove.
(vcmphiq_n_u8): Remove.
(vcmpeqq_u8): Remove.
(vcmpeqq_n_u8): Remove.
(vcmpcsq_u8): Remove.
(vcmpcsq_n_u8): Remove.
(vcmpneq_n_s8): Remove.
(vcmpltq_s8): Remove.
(vcmpltq_n_s8): Remove.
(vcmpleq_s8): Remove.
(vcmpleq_n_s8): Remove.
(vcmpgtq_s8): Remove.
(vcmpgtq_n_s8): Remove.
(vcmpgeq_s8): Remove.
(vcmpgeq_n_s8): Remove.
(vcmpeqq_s8): Remove.
(vcmpeqq_n_s8): Remove.
(vcmpneq_n_u16): Remove.
(vcmphiq_u16): Remove.
(vcmphiq_n_u16): Remove.
(vcmpeqq_u16): Remove.
(vcmpeqq_n_u16): Remove.
(vcmpcsq_u16): Remove.
(vcmpcsq_n_u16): Remove.
(vcmpneq_n_s16): Remove.
(vcmpltq_s16): Remove.
(vcmpltq_n_s16): Remove.
(vcmpleq_s16): Remove.
(vcmpleq_n_s16): Remove.
(vcmpgtq_s16): Remove.
(vcmpgtq_n_s16): Remove.
(vcmpgeq_s16): Remove.
(vcmpgeq_n_s16): Remove.
(vcmpeqq_s16): Remove.
(vcmpeqq_n_s16): Remove.
(vcmpneq_n_u32): Remove.
(vcmphiq_u32): Remove.
(vcmphiq_n_u32): Remove.
(vcmpeqq_u32): Remove.
(vcmpeqq_n_u32): Remove.
(vcmpcsq_u32): Remove.
(vcmpcsq_n_u32): Remove.
(vcmpneq_n_s32): Remove.
(vcmpltq_s32): Remove.
(vcmpltq_n_s32): Remove.
(vcmpleq_s32): Remove.
(vcmpleq_n_s32): Remove.
(vcmpgtq_s32): Remove.
(vcmpgtq_n_s32): Remove.
(vcmpgeq_s32): Remove.
(vcmpgeq_n_s32): Remove.
(vcmpeqq_s32): Remove.
(vcmpeqq_n_s32): Remove.
(vcmpneq_n_f16): Remove.
(vcmpneq_f16): Remove.
(vcmpltq_n_f16): Remove.
(vcmpltq_f16): Remove.
(vcmpleq_n_f16): Remove.
(vcmpleq_f16): Remove.
(vcmpgtq_n_f16): Remove.
(vcmpgtq_f16): Remove.
(vcmpgeq_n_f16): Remove.
(vcmpgeq_f16): Remove.
(vcmpeqq_n_f16): Remove.
(vcmpeqq_f16): Remove.
(vcmpneq_n_f32): Remove.
(vcmpneq_f32): Remove.
(vcmpltq_n_f32): Remove.
(vcmpltq_f32): Remove.
(vcmpleq_n_f32): Remove.
(vcmpleq_f32): Remove.
(vcmpgtq_n_f32): Remove.
(vcmpgtq_f32): Remove.
(vcmpgeq_n_f32): Remove.
(vcmpgeq_f32): Remove.
(vcmpeqq_n_f32): Remove.
(vcmpeqq_f32): Remove.
(vcmpeqq_m_f16): Remove.
(vcmpeqq_m_f32): Remove.
(vcmpneq_m_u8): Remove.
(vcmpneq_m_n_u8): Remove.
(vcmphiq_m_u8): Remove.
(vcmphiq_m_n_u8): Remove.
(vcmpeqq_m_u8): Remove.
(vcmpeqq_m_n_u8): Remove.
(vcmpcsq_m_u8): Remove.
(vcmpcsq_m_n_u8): Remove.
(vcmpneq_m_s8): Remove.
(vcmpneq_m_n_s8): Remove.
(vcmpltq_m_s8): Remove.
(vcmpltq_m_n_s8): Remove.
(vcmpleq_m_s8): Remove.
(vcmpleq_m_n_s8): Remove.
(vcmpgtq_m_s8): Remove.
(vcmpgtq_m_n_s8): Remove.
(vcmpgeq_m_s8): Remove.
(vcmpgeq_m_n_s8): Remove.
(vcmpeqq_m_s8): Remove.
(vcmpeqq_m_n_s8): Remove.
(vcmpneq_m_u16): Remove.
(vcmpneq_m_n_u16): Remove.
(vcmphiq_m_u16): Remove.
(vcmphiq_m_n_u16): Remove.
(vcmpeqq_m_u16): Remove.
(vcmpeqq_m_n_u16): Remove.
(vcmpcsq_m_u16): Remove.
(vcmpcsq_m_n_u16): Remove.
(vcmpneq_m_s16): Remove.
(vcmpneq_m_n_s16): Remove.
(vcmpltq_m_s16): Remove.
(vcmpltq_m_n_s16): Remove.
(vcmpleq_m_s16): Remove.
(vcmpleq_m_n_s16): Remove.
(vcmpgtq_m_s16): Remove.
(vcmpgtq_m_n_s16): Remove.
(vcmpgeq_m_s16): Remove.
(vcmpgeq_m_n_s16): Remove.
(vcmpeqq_m_s16): Remove.
(vcmpeqq_m_n_s16): Remove.
(vcmpneq_m_u32): Remove.
(vcmpneq_m_n_u32): Remove.
(vcmphiq_m_u32): Remove.
(vcmphiq_m_n_u32): Remove.
(vcmpeqq_m_u32): Remove.
(vcmpeqq_m_n_u32): Remove.
(vcmpcsq_m_u32): Remove.
(vcmpcsq_m_n_u32): Remove.
(vcmpneq_m_s32): Remove.
(vcmpneq_m_n_s32): Remove.
(vcmpltq_m_s32): Remove.
(vcmpltq_m_n_s32): Remove.
(vcmpleq_m_s32): Remove.
(vcmpleq_m_n_s32): Remove.
(vcmpgtq_m_s32): Remove.
(vcmpgtq_m_n_s32): Remove.
(vcmpgeq_m_s32): Remove.
(vcmpgeq_m_n_s32): Remove.
(vcmpeqq_m_s32): Remove.
(vcmpeqq_m_n_s32): Remove.
(vcmpeqq_m_n_f16): Remove.
(vcmpgeq_m_f16): Remove.
(vcmpgeq_m_n_f16): Remove.
(vcmpgtq_m_f16): Remove.
(vcmpgtq_m_n_f16): Remove.
(vcmpleq_m_f16): Remove.
(vcmpleq_m_n_f16): Remove.
(vcmpltq_m_f16): Remove.
(vcmpltq_m_n_f16): Remove.
(vcmpneq_m_f16): Remove.
(vcmpneq_m_n_f16): Remove.
(vcmpeqq_m_n_f32): Remove.
(vcmpgeq_m_f32): Remove.
(vcmpgeq_m_n_f32): Remove.
(vcmpgtq_m_f32): Remove.
(vcmpgtq_m_n_f32): Remove.
(vcmpleq_m_f32): Remove.
(vcmpleq_m_n_f32): Remove.
(vcmpltq_m_f32): Remove.
(vcmpltq_m_n_f32): Remove.
(vcmpneq_m_f32): Remove.
(vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq_s8): Remove.
(__arm_vcmpneq_s16): Remove.
(__arm_vcmpneq_s32): Remove.
(__arm_vcmpneq_u8): Remove.
(__arm_vcmpneq_u16): Remove.
(__arm_vcmpneq_u32): Remove.
(__arm_vcmpneq_n_u8): Remove.
(__arm_vcmphiq_u8): Remove.
(__arm_vcmphiq_n_u8): Remove.
(__arm_vcmpeqq_u8): Remove.
(__arm_vcmpeqq_n_u8): Remove.
(__arm_vcmpcsq_u8): Remove.
(__arm_vcmpcsq_n_u8): Remove.
(__arm_vcmpneq_n_s8): Remove.
(__arm_vcmpltq_s8): Remove.
(__arm_vcmpltq_n_s8): Remove.
(__arm_vcmpleq_s8): Remove.
(__arm_vcmpleq_n_s8): Remove.
(__arm_vcmpgtq_s8): Remove.
(__arm_vcmpgtq_n_s8): Remove.
(__arm_vcmpgeq_s8): Remove.
(__arm_vcmpgeq_n_s8): Remove.
(__arm_vcmpeqq_s8): Remove.
(__arm_vcmpeqq_n_s8): Remove.
(__arm_vcmpneq_n_u16): Remove.
(__arm_vcmphiq_u16): Remove.
(__arm_vcmphiq_n_u16): Remove.
(__arm_vcmpeqq_u16): Remove.
(__arm_vcmpeqq_n_u16): Remove.
(__arm_vcmpcsq_u16): Remove.
(__arm_vcmpcsq_n_u16): Remove.
(__arm_vcmpneq_n_s16): Remove.
(__arm_vcmpltq_s16): Remove.
(__arm_vcmpltq_n_s16): Remove.
(__arm_vcmpleq_s16): Remove.
(__arm_vcmpleq_n_s16): Remove.
(__arm_vcmpgtq_s16): Remove.
(__arm_vcmpgtq_n_s16): Remove.
(__arm_vcmpgeq_s16): Remove.
(__arm_vcmpgeq_n_s16): Remove.
(__arm_vcmpeqq_s16): Remove.
(__arm_vcmpeqq_n_s16): Remove.
(__arm_vcmpneq_n_u32): Remove.
(__arm_vcmphiq_u32): Remove.
(__arm_vcmphiq_n_u32): Remove.
(__arm_vcmpeqq_u32): Remove.
(__arm_vcmpeqq_n_u32): Remove.
(__arm_vcmpcsq_u32): Remove.
(__arm_vcmpcsq_n_u32): Remove.
(__arm_vcmpneq_n_s32): Remove.
(__arm_vcmpltq_s32): Remove.
(__arm_vcmpltq_n_s32): Remove.
(__arm_vcmpleq_s32): Remove.
(__arm_vcmpleq_n_s32): Remove.
(__arm_vcmpgtq_s32): Remove.
(__arm_vcmpgtq_n_s32): Remove.
(__arm_vcmpgeq_s32): Remove.
(__arm_vcmpgeq_n_s32): Remove.
(__arm_vcmpeqq_s32): Remove.
(__arm_vcmpeqq_n_s32): Remove.
(__arm_vcmpneq_m_u8): Remove.
(__arm_vcmpneq_m_n_u8): Remove.
(__arm_vcmphiq_m_u8): Remove.
(__arm_vcmphiq_m_n_u8): Remove.
(__arm_vcmpeqq_m_u8): Remove.
(__arm_vcmpeqq_m_n_u8): Remove.
(__arm_vcmpcsq_m_u8): Remove.
(__arm_vcmpcsq_m_n_u8): Remove.
(__arm_vcmpneq_m_s8): Remove.
(__arm_vcmpneq_m_n_s8): Remove.
(__arm_vcmpltq_m_s8): Remove.
(__arm_vcmpltq_m_n_s8): Remove.
(__arm_vcmpleq_m_s8): Remove.
(__arm_vcmpleq_m_n_s8): Remove.
(__arm_vcmpgtq_m_s8): Remove.
(__arm_vcmpgtq_m_n_s8): Remove.
(__arm_vcmpgeq_m_s8): Remove.
(__arm_vcmpgeq_m_n_s8): Remove.
(__arm_vcmpeqq_m_s8): Remove.
(__arm_vcmpeqq_m_n_s8): Remove.
(__arm_vcmpneq_m_u16): Remove.
(__arm_vcmpneq_m_n_u16): Remove.
(__arm_vcmphiq_m_u16): Remove.
(__arm_vcmphiq_m_n_u16): Remove.
(__arm_vcmpeqq_m_u16): Remove.
(__arm_vcmpeqq_m_n_u16): Remove.
(__arm_vcmpcsq_m_u16): Remove.
(__arm_vcmpcsq_m_n_u16): Remove.
(__arm_vcmpneq_m_s16): Remove.
(__arm_vcmpneq_m_n_s16): Remove.
(__arm_vcmpltq_m_s16): Remove.
(__arm_vcmpltq_m_n_s16): Remove.
(__arm_vcmpleq_m_s16): Remove.
(__arm_vcmpleq_m_n_s16): Remove.
(__arm_vcmpgtq_m_s16): Remove.
(__arm_vcmpgtq_m_n_s16): Remove.
(__arm_vcmpgeq_m_s16): Remove.
(__arm_vcmpgeq_m_n_s16): Remove.
(__arm_vcmpeqq_m_s16): Remove.
(__arm_vcmpeqq_m_n_s16): Remove.
(__arm_vcmpneq_m_u32): Remove.
(__arm_vcmpneq_m_n_u32): Remove.
(__arm_vcmphiq_m_u32): Remove.
(__arm_vcmphiq_m_n_u32): Remove.
(__arm_vcmpeqq_m_u32): Remove.
(__arm_vcmpeqq_m_n_u32): Remove.
(__arm_vcmpcsq_m_u32): Remove.
(__arm_vcmpcsq_m_n_u32): Remove.
(__arm_vcmpneq_m_s32): Remove.
(__arm_vcmpneq_m_n_s32): Remove.
(__arm_vcmpltq_m_s32): Remove.
(__arm_vcmpltq_m_n_s32): Remove.
(__arm_vcmpleq_m_s32): Remove.
(__arm_vcmpleq_m_n_s32): Remove.
(__arm_vcmpgtq_m_s32): Remove.
(__arm_vcmpgtq_m_n_s32): Remove.
(__arm_vcmpgeq_m_s32): Remove.
(__arm_vcmpgeq_m_n_s32): Remove.
(__arm_vcmpeqq_m_s32): Remove.
(__arm_vcmpeqq_m_n_s32): Remove.
(__arm_vcmpneq_n_f16): Remove.
(__arm_vcmpneq_f16): Remove.
(__arm_vcmpltq_n_f16): Remove.
(__arm_vcmpltq_f16): Remove.
(__arm_vcmpleq_n_f16): Remove.
(__arm_vcmpleq_f16): Remove.
(__arm_vcmpgtq_n_f16): Remove.
(__arm_vcmpgtq_f16): Remove.
(__arm_vcmpgeq_n_f16): Remove.
(__arm_vcmpgeq_f16): Remove.
(__arm_vcmpeqq_n_f16): Remove.
(__arm_vcmpeqq_f16): Remove.
(__arm_vcmpneq_n_f32): Remove.
(__arm_vcmpneq_f32): Remove.
(__arm_vcmpltq_n_f32): Remove.
(__arm_vcmpltq_f32): Remove.
(__arm_vcmpleq_n_f32): Remove.
(__arm_vcmpleq_f32): Remove.
(__arm_vcmpgtq_n_f32): Remove.
(__arm_vcmpgtq_f32): Remove.
(__arm_vcmpgeq_n_f32): Remove.
(__arm_vcmpgeq_f32): Remove.
(__arm_vcmpeqq_n_f32): Remove.
(__arm_vcmpeqq_f32): Remove.
(__arm_vcmpeqq_m_f16): Remove.
(__arm_vcmpeqq_m_f32): Remove.
(__arm_vcmpeqq_m_n_f16): Remove.
(__arm_vcmpgeq_m_f16): Remove.
(__arm_vcmpgeq_m_n_f16): Remove.
(__arm_vcmpgtq_m_f16): Remove.
(__arm_vcmpgtq_m_n_f16): Remove.
(__arm_vcmpleq_m_f16): Remove.
(__arm_vcmpleq_m_n_f16): Remove.
(__arm_vcmpltq_m_f16): Remove.
(__arm_vcmpltq_m_n_f16): Remove.
(__arm_vcmpneq_m_f16): Remove.
(__arm_vcmpneq_m_n_f16): Remove.
(__arm_vcmpeqq_m_n_f32): Remove.
(__arm_vcmpgeq_m_f32): Remove.
(__arm_vcmpgeq_m_n_f32): Remove.
(__arm_vcmpgtq_m_f32): Remove.
(__arm_vcmpgtq_m_n_f32): Remove.
(__arm_vcmpleq_m_f32): Remove.
(__arm_vcmpleq_m_n_f32): Remove.
(__arm_vcmpltq_m_f32): Remove.
(__arm_vcmpltq_m_n_f32): Remove.
(__arm_vcmpneq_m_f32): Remove.
(__arm_vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq): Remove.
(__arm_vcmphiq): Remove.
(__arm_vcmpeqq): Remove.
(__arm_vcmpcsq): Remove.
(__arm_vcmpltq): Remove.
(__arm_vcmpleq): Remove.
(__arm_vcmpgtq): Remove.
(__arm_vcmpgeq): Remove.
(__arm_vcmpneq_m): Remove.
(__arm_vcmphiq_m): Remove.
(__arm_vcmpeqq_m): Remove.
(__arm_vcmpcsq_m): Remove.
(__arm_vcmpltq_m): Remove.
(__arm_vcmpleq_m): Remove.
(__arm_vcmpgtq_m): Remove.
(__arm_vcmpgeq_m): Remove.
|
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This patch adds the cmp shape description.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-shapes.cc (cmp): New.
* config/arm/arm-mve-builtins-shapes.h (cmp): New.
|
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Factorize vcmp so that they use the same pattern.
2022-10-25 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N)
(MVE_CMP_M_N_F, mve_cmp_op1): New.
(isu): Add VCMP*
(supf): Likewise.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ...
(@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this.
(mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>)
(mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>)
(mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this.
(mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>)
(mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>)
(mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>)
(mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into
...
(@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this.
(mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>)
(mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>)
(mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>)
(mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge
into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this.
(mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>)
(mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>)
(mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
|
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'torture-init'
Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1
"Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'"
made 'torture-init' non-idempotent re 'LTO_TORTURE_OPTIONS', in order to catch
certain classes of errors. Now, most of all '*.exp' files have 'torture-init'
followed by 'set-torture-options' before 'gcc-dg-runtest' etc., and therefore
don't run into the latter's
"Some callers set torture options themselves; don't override those." code.
Some '*.exp' files however do 'torture-init' but not 'set-torture-options', and
therefore we can't any longer conditionalize the implicit 'torture-init' by
'![torture-options-exist]'.
gcc/testsuite/
* lib/torture-options.exp (torture-init-done): Add.
* lib/gcc-dg.exp (gcc-dg-runtest): Use it to conditionalize
implicit 'torture-init'.
* lib/gfortran-dg.exp (gfortran-dg-runtest): Likewise.
* lib/obj-c++-dg.exp (obj-c++-dg-runtest): Likewise.
* lib/objc-dg.exp (objc-dg-runtest): Likewise.
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'LTO_TORTURE_OPTIONS' usage
Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1
"Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'"
made it a requirement that 'LTO_TORTURE_OPTIONS' usage be within
'torture-init'/'torture-finish', and missed a few cases that didn't have that.
gcc/testsuite/
* gcc.target/arm/acle/acle.exp: Add missing
'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS'
usage.
* gcc.target/arm/cmse/cmse.exp: Likewise.
* gcc.target/arm/pure-code/pure-code.exp: Likewise.
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This patch teaches match.pd to simplify popcount(X&Y)+popcount(X|Y) as
popcount(X)+popcount(Y), and the related simplifications that
popcount(X)+popcount(Y)-popcount(X&Y) is popcount(X|Y). As surprising
as it might seem, this idiom is common in cheminformatics codes
(for Tanimoto coefficient calculations).
2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* match.pd <popcount optimizations>: Simplify popcount(X|Y) +
popcount(X&Y) as popcount(X)+popcount(Y). Likewise, simplify
popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and
vice versa.
gcc/testsuite/ChangeLog
* gcc.dg/fold-popcount-8.c: New test case.
* gcc.dg/fold-popcount-9.c: Likewise.
* gcc.dg/fold-popcount-10.c: Likewise.
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This is the latest iteration of my patch from August 2020
https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552391.html
incorperating feedback and suggestions from reviewers.
This patch to match.pd optimizes away bit permutation operations,
specifically bswap and rotate, in calls to popcount and parity.
2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* match.pd <popcount optimizations>: Simplify popcount(bswap(x))
as popcount(x). Simplify popcount(rotate(x,y)) as popcount(x).
<parity optimizations>: Simplify parity(bswap(x)) as parity(x).
Simplify parity(rotate(x,y)) as parity(x).
gcc/testsuite/ChangeLog
* gcc.dg/fold-parity-6.c: New test.
* gcc.dg/fold-parity-7.c: Likewise.
* gcc.dg/fold-popcount-6.c: Likewise.
* gcc.dg/fold-popcount-7.c: Likewise.
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This patch is the prerequiste patch for more RVV auto-vectorization
support.
Since when we enable a very simple binary operations, we will end
up with such following ICE:
during RTL pass: expand
add_run-1.c: In function 'main':
add_run-1.c:28:1: internal compiler error: Segmentation fault
0x1618ea3 crash_signal
../../../riscv-gcc/gcc/toplev.cc:314
0xe76cd9 single_set(rtx_insn const*)
../../../riscv-gcc/gcc/rtl.h:3602
0x1080f8a emit_move_insn(rtx_def*, rtx_def*)
../../../riscv-gcc/gcc/expr.cc:4342
0x170c458 insert_value_copy_on_edge
../../../riscv-gcc/gcc/tree-outof-ssa.cc:352
0x170d58e eliminate_phi
../../../riscv-gcc/gcc/tree-outof-ssa.cc:785
0x170df17 expand_phi_nodes(ssaexpand*)
../../../riscv-gcc/gcc/tree-outof-ssa.cc:1024
0xef27e2 execute
../../../riscv-gcc/gcc/cfgexpand.cc:6818
This is because LoopVectorizer assume target is able to handle
series const vector when we enable binary operations.
Then it will be easily causing ICE like that.
gcc/ChangeLog:
* config/riscv/autovec.md (@vec_series<mode>): New pattern
* config/riscv/riscv-protos.h (expand_vec_series): New function.
* config/riscv/riscv-v.cc (emit_binop): Ditto.
(emit_index_op): Ditto.
(expand_vec_series): Ditto.
(expand_const_vector): Add series vector handling.
* config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/series-1.c: New test.
* gcc.target/riscv/rvv/autovec/series_run-1.c: New test.
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|
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This PR points out that std::is_convertible has given the wrong answer
in
static_assert (!std::is_convertible_v <int () const, int (*) ()>, "");
since r13-2822 implemented __is_{,nothrow_}convertible.
std::is_convertible uses the imaginary
To test() { return std::declval<From>(); }
to do its job. Here, From is 'int () const'. std::declval is defined as:
template<class T>
typename std::add_rvalue_reference<T>::type declval() noexcept;
std::add_rvalue_reference is defined as "If T is a function type that
has no cv- or ref- qualifier or an object type, provides a member typedef
type which is T&&, otherwise type is T."
In our case, T is cv-qualified, so the result is T, so we end up with
int () const declval() noexcept;
which is invalid. In other words, this is pretty much like:
using T = int () const;
T fn1(); // bad, fn returning a fn
T& fn2(); // bad, cannot declare reference to qualified function type
T* fn3(); // bad, cannot declare pointer to qualified function type
using U = int ();
U fn4(); // bad, fn returning a fn
U& fn5(); // OK
U* fn6(); // OK
I think is_convertible_helper needs to simulate std::declval better.
To that end, I'm introducing build_trait_object, to be used where
a declval is needed.
PR c++/109680
gcc/cp/ChangeLog:
* method.cc (build_trait_object): New.
(assignable_expr): Use it.
(ref_xes_from_temporary): Likewise.
(is_convertible_helper): Likewise. Check FUNC_OR_METHOD_TYPE_P.
gcc/testsuite/ChangeLog:
* g++.dg/ext/is_convertible6.C: New test.
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This cleans up the use of [(clobber (const_int 0))] in the i386 backend.
2023-05-10 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred
[(const_int 0)] idiom, instead of [(clobber (const_int 0))].
(*concat<mode><dwi>3_2): Likewise.
(*concat<mode><dwi>3_3): Likewise.
(*concat<mode><dwi>3_4): Likewise.
(*concat<mode><dwi>3_5): Likewise.
(*concat<mode><dwi>3_6): Likewise.
(*concat<mode><dwi>3_7): Likewise.
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While looking at PR109247 I made this change to improve diagnostics. I
don't think I'm going ahead with that patch, but this still seems like a
worthy cleanup.
gcc/cp/ChangeLog:
* call.cc (convert_like_internal): Share ck_ref_bind handling
between all bad conversions.
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Add missing insn pattern for v2qi -> v2si vector extend and named
expanders to activate generation of vector extends to 8-byte and 4-byte
vectors.
gcc/ChangeLog:
PR target/92658
* config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern.
(<insn>v4qiv4hi2): New expander.
(<insn>v2hiv2si2): Ditto.
(<insn>v2qiv2si2): Ditto.
(<insn>v2qiv2hi2): Ditto.
gcc/testsuite/ChangeLog:
PR target/92658
* gcc.target/i386/pr92658-sse4-4b.c: New test.
* gcc.target/i386/pr92658-sse4-8b.c: New test.
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gcc/fortran/ChangeLog:
* dump-parse-tree.cc (gfc_debug_expr): Remove forward declaration.
(debug): Add DEBUG_FUNCTION.
(show_code_node): Remove erroneous whitespace.
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gcc/fortran/ChangeLog:
PR fortran/109624
* dump-parse-tree.cc (debug): New function for gfc_namespace.
(gfc_debug_code): Delete forward declaration.
(show_attr): Make sure to print balanced braces.
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While working on improving min/max detection, this
code (which is reduced from worse_state in ipa-pure-const.cc)
was being miscompiled. Since there was no testcase in the
testsuite yet for this, this patch adds one.
Committed as obvious after testing the testcase via:
make check-gcc RUNTESTFLAGS="execute.exp=20230510-1.c"
gcc/testsuite/ChangeLog:
* gcc.c-torture/execute/20230510-1.c: New test.
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DR 2543 clarifies that constinit variables should follow the language, and
diagnose non-constant initializers (according to [expr.const]) even if they
can actually initialize the variables statically.
DR 2543
gcc/cp/ChangeLog:
* constexpr.cc (cxx_eval_outermost_constant_expr): Preserve
TARGET_EXPR flags.
(potential_constant_expression_1): Check TARGET_EXPR_ELIDING_P.
* typeck2.cc (store_init_value): Diagnose constinit sooner.
gcc/testsuite/ChangeLog:
* g++.dg/DRs/dr2543.C: New test.
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The restriction on the "permitted result of a constant expression" to not
refer to an immediate function applies regardless of context. The previous
code tried to only check in cases where we wouldn't get the check in
cp_fold_r, but with the next patch I would need to add another case and it
shouldn't be a problem to always check.
We also shouldn't talk about immediate evaluation when we aren't dealing
with one.
gcc/cp/ChangeLog:
* constexpr.cc (cxx_eval_outermost_constant_expr): Always check
for address of immediate fn.
(maybe_constant_init_1): Evaluate PTRMEM_CST.
gcc/testsuite/ChangeLog:
* g++.dg/DRs/dr2478.C: Handle -fimplicit-constexpr.
* g++.dg/cpp23/consteval-if12.C: Adjust diagnostics.
* g++.dg/cpp2a/consteval20.C: Likewise.
* g++.dg/cpp2a/consteval24.C: Likewise.
* g++.dg/cpp2a/srcloc20.C: Likewise.
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The following forces the g++.dg/torture/pr106922.C testcase to use
the C++11 libstdc++ ABI and checks whether that worked.
gcc/testsuite/
* g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
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So this is the 2nd patch on the way to LRA for the H8.
LRA is more sensitive to getting define_constraint vs define_memory_constraint
vs define_special_memory_constraint correct. than reload.
The H8 port has the "Q" constraint, which is used to indicate memory addresses
that can be used under certain circumstances in various ALU operations. So it
should be a memory constraint. Ideally it'd would be a simple memory
constraint, but it's used in contexts where MEMs are valid only for certain
parts in the H8 family. So it really needs to be a special_memory_constraint.
The "Zz" constraint accepts memory, but the forms are limited and can not be
reloaded into a register. It seems to be working, but I wouldn't be totally
surprised if this got stressed in the right way if it broke.
Anyway, this patch fixes "Q" and "Zz" to be special memory constraints.
Regression tested with gdbsim and pushed to the trunk.
gcc
* config/h8300/constraints.md (Q): Make this a special memory
constraint.
(Zz): Similarly.
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The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE
which doesn't really match the passed in arguments (FUNCTION_TYPE has
5 arguments, call has 6). Now, I think that is a Fortran FE bug that
should be fixed there, but I think with function pointers one can
create something similar (of course invalid) in C/C++ too,so IMHO IPA
should be also more careful.
The ipa_get_callee_param_type function can return NULL if something goes
wrong and it does e.g. if asked for 7th argument type on a function
with just 5 arguments and similar. But, if a function isn't varargs,
when asked for 6th argument type on a function with just 5 arguments
it actually returns void_type_node because the argument list is in that
case terminated with void_list_node.
The following patch makes sure we don't treat void_list_node as something
holding another argument.
2023-05-10 Jakub Jelinek <jakub@redhat.com>
PR fortran/109788
* ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t)
if t is void_list_node.
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This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe.
This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required
still triggers.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete.
(aarch64_sqmovun<mode>_insn_be): Delete.
(aarch64_sqmovun<mode><vczle><vczbe>): New define_insn.
(aarch64_sqmovun<mode>): Delete expander.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/pr99195_4.c: Add tests for sqmovun.
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vec-concat-zero
Another straightforward patch annotating patterns for the zip1, zip2, uzp1, uzp2, rev* instructions, plus tests.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>):
Rename to...
(aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This.
(aarch64_rev<REVERSE:rev_op><mode>): Rename to...
(aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add tests for zip and rev
intrinsics.
|
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vec-concat-zero
Moving onto the saturating instructions, this one goes through the simple add/sub ones.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>):
Rename to...
(aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This.
(aarch64_<sur>qadd<mode>): Rename to...
(aarch64_<sur>qadd<mode><vczle><vczbe>): ... This.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add testing for qadd, qsub.
* gcc.target/aarch64/simd/pr99195_6.c: New test.
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This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns for the QSHRN instructions in favour
of annotating a single one with <vczle><vczbe>. This allows simplification of the expander too.
Tests are added to ensure that we still optimise away the concat-with-zero use case.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/pr99195_5.c: New test.
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This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN instructions.
Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN cases,
as well as the intrinsic expanders that select between the two.
Tests are also added. Thankfully the diffstat comes out negative \O/.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete.
(aarch64_xtn<mode>_insn_be): Likewise.
(trunc<mode><Vnarrowq>2): Rename to...
(trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
(aarch64_xtn<mode>): Move under the above. Just emit the truncate RTL.
(aarch64_<su>qmovn<mode>): Likewise.
(aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
(aarch64_<su>qmovn<mode>_insn_le): Delete.
(aarch64_<su>qmovn<mode>_insn_be): Likewise.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.
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The following testcase shows we silently accept (and ignore) attributes without
arguments used as pack expansions. This is because we call
make_pack_expansion and that starts with
if (!arg || arg == error_mark_node)
return arg;
Now, an attribute without arguments like [[noreturn...]] is IMHO always
invalid, in this case for 2 reasons; one is that as it has no arguments,
no pack can be present and second is that the standard says that
attributes need to specially permit uses of parameter pack and doesn't
explicitly permit it for any of the standard attributes (except for alignas?
which has different syntax).
If an attribute has some arguments but doesn't contain packs in those
arguments, make_pack_expansion will already diagnose it.
The patch also changes cp_parser_std_attribute, such that for attributes unknown
to the compiler (or perhaps registered just for -Wno-attributes=) we differentiate
between the attribute having no arguments (in that case we want to diagnose them
when followed by ellipsis even if they are unknown, as they can't contain a pack
in that case) and the case where they do have arguments but we've just skipped over
those arguments because we don't know how to parse them (except that they are
a balanced token sequence) - in that case we really don't know if they contain
packs or not.
2023-05-10 Jakub Jelinek <jakub@redhat.com>
PR c++/109756
* parser.cc (cp_parser_std_attribute): For unknown attributes with
arguments set TREE_VALUE (attribute) to error_mark_node after skipping
the balanced tokens.
(cp_parser_std_attribute_list): If ... is used after attribute without
arguments, diagnose it and return error_mark_node. If
TREE_VALUE (attribute) is error_mark_node, don't call
make_pack_expansion nor return early error_mark_node.
* g++.dg/cpp0x/gen-attrs-78.C: New test.
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REG_P(operand[1]) in -O0.
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
return maxVal;
}
Before this patch:
bug.c:15:1: internal compiler error: Segmentation fault
15 | }
| ^
0x145d723 crash_signal
../.././riscv-gcc/gcc/toplev.cc:314
0x22929dd const_csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:44
0x2292a21 csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:46
0x23dfbb0 recog_356
../.././riscv-gcc/gcc/config/riscv/iterators.md:72
0x23efecd recog(rtx_def*, rtx_insn*, int*)
../.././riscv-gcc/gcc/config/riscv/iterators.md:89
0xdddc15 recog_memoized(rtx_insn*)
../.././riscv-gcc/gcc/recog.h:273
After this patch:
vsetivli zero,0,e16,m1,ta,ma
vmv.x.s a5,v1
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
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TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.
They let movmisalign<mode> to handle scalable vector of SVE.
For RVV, we should follow the same implementation of ARM SVE.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
incorrect codes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.
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This patch is fix dead loop in vsetvl intrinsic avl checking.
vsetvli->get_def () has vsetvli->get_def () has vsetvli.....
Then it will keep looping in the vsetvli avl checking which is a dead loop.
PR target/109773
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function.
(source_equal_p): Fix dead loop in vsetvl avl checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr109773-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109773-2.c: New test.
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While I was writting a match.pd patch, I can across GCC was being miscompiled
but no testcase was failing. So this adds that testcase.
Committed after testing on x86_64 with
make check-gcc RUNTESTFLAGS="execute.exp=20230509-1.c"
gcc/testsuite/ChangeLog:
* gcc.c-torture/execute/20230509-1.c: New test.
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Typo spotted while doing CCmode improvements, as a missed
optimization. It's almost visible from the patch context;
there's not much done in terms of "mode-adjustment" when
replacing (reg:CC CRIS_CC0_REGNUM) with a copy!
This bug affects functions in the newlib printf-formatting
functions (nothing else in libgcc or newlib libc), with the
performance impact on coremark scores being less than 1e-6
(3/5078992 cycles, 6/48543 bytes).
* config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode
of modeadjusted_dccr.
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* hr.po: Update.
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After diagnosing and recovering from unstable satisfaction, it's
possible to evaluate an atom for the first time noisily rather than
quietly. The satisfaction cache tries to handle this situation
gracefully, but apparently not gracefully enough: we inserted an empty
slot into the cache, and left it empty, which later makes
hash_table::check_complete_insertion unhappy. This patch fixes this by
removing the empty slot in this case.
PR c++/109752
gcc/cp/ChangeLog:
* constraint.cc (satisfaction_cache::satisfaction_cache): In the
unexpected case of evaluating an atom for the first time noisily,
remove the cache slot that we inserted.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/concepts-pr109752.C: New test.
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When late processing a noexcept-spec from a nested class after completion
of the outer class (since it's a complete-class context), we pass the wrong
class context to noexcept_override_late_checks -- the outer class type
instead of the nested class type -- which leads to bogus errors in the
below test.
This patch fixes this by making noexcept_override_late_checks obtain the
class context directly via DECL_CONTEXT instead of via an additional
parameter.
PR c++/109761
gcc/cp/ChangeLog:
* parser.cc (cp_parser_class_specifier): Don't pass a class
context to noexcept_override_late_checks.
(noexcept_override_late_checks): Remove 'type' parameter
and use DECL_CONTEXT of 'fndecl' instead.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/noexcept78.C: New test.
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Implement vmaxaq and vminaq using the new MVE builtins framework.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxaq and
vminaq.
* config/arm/arm_mve.h (vminaq): Remove.
(vmaxaq): Remove.
(vminaq_m): Remove.
(vmaxaq_m): Remove.
(vminaq_s8): Remove.
(vmaxaq_s8): Remove.
(vminaq_s16): Remove.
(vmaxaq_s16): Remove.
(vminaq_s32): Remove.
(vmaxaq_s32): Remove.
(vminaq_m_s8): Remove.
(vmaxaq_m_s8): Remove.
(vminaq_m_s16): Remove.
(vmaxaq_m_s16): Remove.
(vminaq_m_s32): Remove.
(vmaxaq_m_s32): Remove.
(__arm_vminaq_s8): Remove.
(__arm_vmaxaq_s8): Remove.
(__arm_vminaq_s16): Remove.
(__arm_vmaxaq_s16): Remove.
(__arm_vminaq_s32): Remove.
(__arm_vmaxaq_s32): Remove.
(__arm_vminaq_m_s8): Remove.
(__arm_vmaxaq_m_s8): Remove.
(__arm_vminaq_m_s16): Remove.
(__arm_vmaxaq_m_s16): Remove.
(__arm_vminaq_m_s32): Remove.
(__arm_vmaxaq_m_s32): Remove.
(__arm_vminaq): Remove.
(__arm_vmaxaq): Remove.
(__arm_vminaq_m): Remove.
(__arm_vmaxaq_m): Remove.
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Factorize vmaxaq vminaq so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
New.
(mve_insn): Add vmaxa, vmina.
(supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
* config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
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This patch adds the binary_maxamina shape description.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New.
* config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
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Implement vmaxnmaq and vminnmaq using the new MVE builtins framework.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxnmaq and
vminnmaq.
* config/arm/arm_mve.h (vminnmaq): Remove.
(vmaxnmaq): Remove.
(vmaxnmaq_m): Remove.
(vminnmaq_m): Remove.
(vminnmaq_f16): Remove.
(vmaxnmaq_f16): Remove.
(vminnmaq_f32): Remove.
(vmaxnmaq_f32): Remove.
(vmaxnmaq_m_f16): Remove.
(vminnmaq_m_f16): Remove.
(vmaxnmaq_m_f32): Remove.
(vminnmaq_m_f32): Remove.
(__arm_vminnmaq_f16): Remove.
(__arm_vmaxnmaq_f16): Remove.
(__arm_vminnmaq_f32): Remove.
(__arm_vmaxnmaq_f32): Remove.
(__arm_vmaxnmaq_m_f16): Remove.
(__arm_vminnmaq_m_f16): Remove.
(__arm_vmaxnmaq_m_f32): Remove.
(__arm_vminnmaq_m_f32): Remove.
(__arm_vminnmaq): Remove.
(__arm_vmaxnmaq): Remove.
(__arm_vmaxnmaq_m): Remove.
(__arm_vminnmaq_m): Remove.
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Factorize vmaxnmaq and vminnmaq so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ)
(MVE_VMAXNMA_VMINNMAQ_M): New.
(mve_insn): Add vmaxnma, vminnma.
* config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>):
Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
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Implement vmaxnmavq vmaxnmvq vminnmavq vminnmvq using the new MVE
builtins framework.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New.
(vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq)
(vminnmavq, vminnmvq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq)
(vminnmavq, vminnmvq): New.
* config/arm/arm_mve.h (vminnmvq): Remove.
(vminnmavq): Remove.
(vmaxnmvq): Remove.
(vmaxnmavq): Remove.
(vmaxnmavq_p): Remove.
(vmaxnmvq_p): Remove.
(vminnmavq_p): Remove.
(vminnmvq_p): Remove.
(vminnmvq_f16): Remove.
(vminnmavq_f16): Remove.
(vmaxnmvq_f16): Remove.
(vmaxnmavq_f16): Remove.
(vminnmvq_f32): Remove.
(vminnmavq_f32): Remove.
(vmaxnmvq_f32): Remove.
(vmaxnmavq_f32): Remove.
(vmaxnmavq_p_f16): Remove.
(vmaxnmvq_p_f16): Remove.
(vminnmavq_p_f16): Remove.
(vminnmvq_p_f16): Remove.
(vmaxnmavq_p_f32): Remove.
(vmaxnmvq_p_f32): Remove.
(vminnmavq_p_f32): Remove.
(vminnmvq_p_f32): Remove.
(__arm_vminnmvq_f16): Remove.
(__arm_vminnmavq_f16): Remove.
(__arm_vmaxnmvq_f16): Remove.
(__arm_vmaxnmavq_f16): Remove.
(__arm_vminnmvq_f32): Remove.
(__arm_vminnmavq_f32): Remove.
(__arm_vmaxnmvq_f32): Remove.
(__arm_vmaxnmavq_f32): Remove.
(__arm_vmaxnmavq_p_f16): Remove.
(__arm_vmaxnmvq_p_f16): Remove.
(__arm_vminnmavq_p_f16): Remove.
(__arm_vminnmvq_p_f16): Remove.
(__arm_vmaxnmavq_p_f32): Remove.
(__arm_vmaxnmvq_p_f32): Remove.
(__arm_vminnmavq_p_f32): Remove.
(__arm_vminnmvq_p_f32): Remove.
(__arm_vminnmvq): Remove.
(__arm_vminnmavq): Remove.
(__arm_vmaxnmvq): Remove.
(__arm_vmaxnmavq): Remove.
(__arm_vmaxnmavq_p): Remove.
(__arm_vmaxnmvq_p): Remove.
(__arm_vminnmavq_p): Remove.
(__arm_vminnmvq_p): Remove.
(__arm_vmaxnmavq_m): Remove.
(__arm_vmaxnmvq_m): Remove.
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We can call code_for_mve_q_p_f only once this function exists, which
is the case after we factorized vmaxnmavq, vmaxnmvq, vminnmavq and
vminnmvq in a previous patch.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
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Factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq so that they use the
same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ)
(MVE_VMAXNMxV_MINNMxVQ_P): New.
(mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv.
* config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>)
(mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>)
(mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ...
(@mve_<mve_insn>q_p_f<mode>): ... this.
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|
Implement vmaxnmq and vminnmq using the new MVE builtins framework.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New.
* config/arm/arm_mve.h (vminnmq): Remove.
(vmaxnmq): Remove.
(vmaxnmq_m): Remove.
(vminnmq_m): Remove.
(vminnmq_x): Remove.
(vmaxnmq_x): Remove.
(vminnmq_f16): Remove.
(vmaxnmq_f16): Remove.
(vminnmq_f32): Remove.
(vmaxnmq_f32): Remove.
(vmaxnmq_m_f32): Remove.
(vmaxnmq_m_f16): Remove.
(vminnmq_m_f32): Remove.
(vminnmq_m_f16): Remove.
(vminnmq_x_f16): Remove.
(vminnmq_x_f32): Remove.
(vmaxnmq_x_f16): Remove.
(vmaxnmq_x_f32): Remove.
(__arm_vminnmq_f16): Remove.
(__arm_vmaxnmq_f16): Remove.
(__arm_vminnmq_f32): Remove.
(__arm_vmaxnmq_f32): Remove.
(__arm_vmaxnmq_m_f32): Remove.
(__arm_vmaxnmq_m_f16): Remove.
(__arm_vminnmq_m_f32): Remove.
(__arm_vminnmq_m_f16): Remove.
(__arm_vminnmq_x_f16): Remove.
(__arm_vminnmq_x_f32): Remove.
(__arm_vmaxnmq_x_f16): Remove.
(__arm_vmaxnmq_x_f32): Remove.
(__arm_vminnmq): Remove.
(__arm_vmaxnmq): Remove.
(__arm_vmaxnmq_m): Remove.
(__arm_vminnmq_m): Remove.
(__arm_vminnmq_x): Remove.
(__arm_vmaxnmq_x): Remove.
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Factorize vmaxnmq and vminnmq so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MAX_MIN_F): New.
(MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F.
(mve_insn): Add vmaxnm, vminnm.
(max_min_f_str): New.
* config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>):
Merge into ...
(@mve_<max_min_f_str>q_f<mode>): ... this.
(mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
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