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2023-03-16tree-optimization/109123 - run -Wuse-afer-free only earlyRichard Biener4-19/+60
The following switches the -Wuse-after-free diagnostics from emitted during the late access warning passes to the early access warning passes to make sure we run before passes performing code motion run which are the source of a lot of false positives on use-after-free not involving memory operations. The patch also fixes an issue in c-c++-common/Wuse-after-free-6.c and causes the name of the unused pointer to appear in the diagnostic for extra cases in gcc.dg/Wuse-after-free-2.c PR tree-optimization/109123 * gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer): Do not emit -Wuse-after-free late. (pass_waccess::check_call): Always check call pointer uses. * gcc.dg/Wuse-after-free-pr109123.c: New testcase. * gcc.dg/Wuse-after-free-2.c: Amend expected diagnostic with the name of the pointer. * c-c++-common/Wuse-after-free-6.c: Un-XFAIL case.
2023-03-16Avoid random stmt order result in pass_waccess::use_after_inval_pRichard Biener3-49/+37
use_after_inval_p uses stmt UIDs to speed up repeated dominance checks within a basic-block but it fails to assign UIDs to PHIs which means compares with PHIs in the same block get a random result. The following factors renumber_gimple_stmt_uids to expose a new renumber_gimple_stmt_uids_in_block we can share. But since we rely on processing even earlier PHIs to follow pointer adjustments (we look at those even if earlier) the patch also moves PHI handling out of the use_after_inval_p guard. This then also fixes PR109141. PR tree-optimization/109141 * tree-dfa.h (renumber_gimple_stmt_uids_in_block): New. * tree-dfa.cc (renumber_gimple_stmt_uids_in_block): Split out from ... (renumber_gimple_stmt_uids): ... here and (renumber_gimple_stmt_uids_in_blocks): ... here. * gimple-ssa-warn-access.cc (pass_waccess::use_after_inval_p): Use renumber_gimple_stmt_uids_in_block to also assign UIDs to PHIs. (pass_waccess::check_pointer_uses): Process all PHIs.
2023-03-16Move target independent documentation files into subdirGaius Mulley8-10/+1590
Move target independent documentation files into a subdir m2 so that the maintainer-scripts/update_web_docs_git can build gm2.texi from the source tree (and without any build dir). gcc/m2/ChangeLog: * Make-lang.in: Rename target-independent to target-independent/m2. * target-independent/readme.txt: Update. * target-independent/m2/gm2-ebnf.texi: New file. * target-independent/m2/gpl_v3_without_node.texi: New file. * target-independent/Builtins.texi: Rename ... * target-independent/m2/Builtins.texi: ... to this. * target-independent/SYSTEM-iso.texi: Rename ... * target-independent/m2/SYSTEM-iso.texi: ... to this. * target-independent/SYSTEM-pim.texi: Rename ... * target-independent/m2/SYSTEM-pim.texi: ... to this. * target-independent/gm2-libs.texi: Rename ... * target-independent/m2/gm2-libs.texi: ... to this. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-03-16Daily bump.GCC Administrator6-1/+386
2023-03-15c++: co_await and initializer_list [PR103871]Jason Merrill2-0/+23
When flatten_await_stmt processes the backing array for an initializer_list, we call cp_build_modify_expr to initialize the promoted variable from the TARGET_EXPR; that needs to be accepted. PR c++/103871 PR c++/98056 gcc/cp/ChangeLog: * typeck.cc (cp_build_modify_expr): Allow array initialization of DECL_ARTIFICIAL variable. gcc/testsuite/ChangeLog: * g++.dg/coroutines/co-await-initlist1.C: New test.
2023-03-15diagnostics: attempt to capture crash info in SARIF output [PR109097]David Malcolm10-18/+458
As noted in PR analyzer/109097, if an internal compiler error occurs when -fdiagnostics-format=sarif-file is specified, we currently fail to write out a .sarif file, and the output to stderr doesn't contain "internal compiler error" or "Internal compiler error"; just the backtrace if we're lucky, and the "Please submit a full bug report" messages. This is a nuisance e.g. for my integration testing of -fanalyzer, where I'm gathering the results of builds via the .sarif output: if it crashes on a particular source file, then no output is generated, and it's effectively silent about the crash. This patch fixes things by adding a callback to diagnostic_context so that the SARIF output code can make one final attempt to write its output if an ICE occurs. It also special-cases the output, so that an ICE is treated as an "error"-level "notification" relating to the operation of the tool (SARIF v2.1.0 section 3.58), rather than a "result" about the code being analyzed by the tool. The patch adds test coverage for this via a plugin that can inject: * calls to internal_compiler_error, and * writes through a NULL pointer and verifying that a .sarif file is written out capturing the crash (and also that an ICE occurs via dg-ice, which seems to treat the ICE as an XFAIL, which is reasonable). I've added support for this to my integration-testing scripts: testing shows that with this patch we capture analyzer crashes in .sarif files (specifically, the analyzer crash on qemu: PR analyzer/109094), and I've updated my scripts to work with and report such output. I manually verified that the resulting .sarif files validate against the schema. gcc/ChangeLog: PR analyzer/109097 * diagnostic-format-sarif.cc (class sarif_invocation): New. (class sarif_ice_notification): New. (sarif_builder::m_invocation_obj): New field. (sarif_invocation::add_notification_for_ice): New. (sarif_invocation::prepare_to_flush): New. (sarif_ice_notification::sarif_ice_notification): New. (sarif_builder::sarif_builder): Add m_invocation_obj. (sarif_builder::end_diagnostic): Special-case DK_ICE and DK_ICE_NOBT. (sarif_builder::flush_to_file): Call prepare_to_flush on m_invocation_obj. Pass the latter to make_top_level_object. (sarif_builder::make_result_object): Move creation of "locations" array to... (sarif_builder::make_locations_arr): ...this new function. (sarif_builder::make_top_level_object): Add "invocation_obj" param and pass it to make_run_object. (sarif_builder::make_run_object): Add "invocation_obj" param and use it. (sarif_ice_handler): New callback. (diagnostic_output_format_init_sarif): Wire up sarif_ice_handler. * diagnostic.cc (diagnostic_initialize): Initialize new field "ice_handler_cb". (diagnostic_action_after_output): If it is set, make one attempt to call ice_handler_cb. * diagnostic.h (diagnostic_context::ice_handler_cb): New field. gcc/testsuite/ChangeLog: PR analyzer/109097 * c-c++-common/diagnostic-format-sarif-file-1.c: Verify that we have an invocation object marked as succeeding, with no notifications. * gcc.dg/plugin/crash-test-ice-sarif.c: New test. * gcc.dg/plugin/crash-test-ice-stderr.c: New test. * gcc.dg/plugin/crash-test-write-though-null-sarif.c: New test. * gcc.dg/plugin/crash-test-write-though-null-stderr.c: New test. * gcc.dg/plugin/crash_test_plugin.c: New plugin. * gcc.dg/plugin/plugin.exp (plugin_test_list): Add the new plugin and test cases. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-03-15PR 109125 13 regression SIGBUS in m2pim_ldtoa_ldtoaGaius Mulley2-4/+4
This patch fixes more bool int parameter mismatches found in dtoa and ldtoa. gcc/m2/ChangeLog: PR modula2/109125 * gm2-libs-ch/dtoa.cc (dtoa_strtod): Replace int with bool. * gm2-libs-ch/ldtoa.cc (ldtoa_strtold): Replace int with bool. libgm2/ChangeLog: PR modula2/109125 * libm2pim/dtoa.cc (TRUE): Remove. (FALSE): Remove. Replace int with bool. * libm2pim/ldtoa.cc (TRUE): Remove. (FALSE): Remove. Replace int with bool. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-03-15i386: Fix blend vector permutation for 8-byte modesUros Bizjak7-18/+53
8-byte modes should be processed only for TARGET_MMX_WITH_SSE. Handle V2SFmode and fix V2HImode handling. The resulting BLEND instructions are always faster than MOVSS/MOVSD, so prioritize them w.r.t MOVSS/MOVSD for TARGET_SSE4_1. gcc/ChangeLog: * config/i386/i386-expand.cc (expand_vec_perm_blend): Handle 8-byte modes only with TARGET_MMX_WITH_SSE. Handle V2SFmode and fix V2HImode handling. (expand_vec_perm_1): Try to emit BLEND instruction before MOVSS/MOVSD. * config/i386/mmx.md (*mmx_blendps): New insn pattern. gcc/testsuite/ChangeLog: * gcc.target/i386/merge-1.c (dg-options): Use -mno-sse4. * gcc.target/i386/sse2-mmx-21.c (dg-options): Ditto. * gcc.target/i386/sse-movss-4.c (dg-options): Use -mno-sse4. Simplify scan-assembler-not strings. * gcc.target/i386/sse2-movsd-3.c (dg-options): Ditto. * gcc.target/i386/sse2-mmx-movss-1.c: New test.
2023-03-15Fortran: rank checking with explicit-/assumed-size arrays and CLASS [PR58331]Harald Anlauf2-7/+76
gcc/fortran/ChangeLog: PR fortran/58331 * interface.cc (compare_parameter): Adjust check of array dummy arguments to handle the case of CLASS variables. gcc/testsuite/ChangeLog: PR fortran/58331 * gfortran.dg/class_dummy_10.f90: New test. Co-authored-by: Tobias Burnus <tobias@codesourcery.com>
2023-03-15c++: ICE with constexpr lambda [PR107280]Marek Polacek2-1/+17
We crash here since r10-3661, the store_init_value hunk in particular. Before, we called cp_fully_fold_init, so e.g. {.str=VIEW_CONVERT_EXPR<char[8]>("")} was folded into {.str=""} but now we don't fold and keep the VCE around, and it causes trouble in cxx_eval_store_expression: in the !refs->is_empty () loop we descend on .str's initializer but since it's wrapped in a VCE, we skip the STRING_CST check and then crash on the CONSTRUCTOR_NO_CLEARING. PR c++/107280 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_store_expression): Strip location wrappers. gcc/testsuite/ChangeLog: * g++.dg/cpp1z/constexpr-lambda28.C: New test.
2023-03-15OpenMP: Add omp_in_explicit_task to omp_runtime_api_callTobias Burnus1-0/+1
gcc/ * omp-low.cc (omp_runtime_api_call): Add omp_in_explicit_task.
2023-03-15Avoid duplicate diagnostic in g++.dg/warn/Wuse-after-free3.CRichard Biener2-2/+5
We are diagnosing operator delete (this_3(D)); A::f (this_3(D)); *this_3(D) ={v} CLOBBER; where the CLOBBER appears at the end of the DTOR for C++11 and later. The following avoids this by simply never diagnosing clobbers as use-after-free. * gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses): Do not diagnose clobbers. * g++.dg/warn/Wuse-after-free3.C: Remove expected duplicate diagnostic.
2023-03-15c++: injected class name as default ttp arg [PR58538]Jason Merrill2-3/+8
This function needs to handle this case like convert_template_argument. PR c++/58538 gcc/cp/ChangeLog: * semantics.cc (check_template_template_default_arg): Check maybe_get_template_decl_from_type_decl. gcc/testsuite/ChangeLog: * g++.dg/template/ttp7.C: Remove expected error.
2023-03-15c++: passing one ttp to another [PR108179]Jason Merrill2-16/+25
I kept trying to improve our choice of how many levels of outer_args to add, when really the problem was that outer_args are for PARM and for this reverse deduction we should be adding the outer arguments for ARG. I spent quite a while trying to get DECL_CONTEXT set consistently on template template parameters that have gone through reduce_template_parm_level before I realized I could just use current_scope(). PR c++/108179 PR c++/104107 PR c++/95036 gcc/cp/ChangeLog: * pt.cc (coerce_template_template_parms): Use args from DECL_CONTEXT (arg_tmpl) instead of outer_args. gcc/testsuite/ChangeLog: * g++.dg/template/ttp35.C: New test.
2023-03-15c++: coerce_template_template_parms interface tweakJason Merrill1-27/+15
This should have no semantic effect, but is a prerequisite for the PR108179 fix to follow. PR c++/108179 gcc/cp/ChangeLog: * pt.cc (coerce_template_template_parms): Take the arg and parm templates directly. (coerce_template_template_parm): Adjust. (template_template_parm_bindings_ok_p): Adjust. (convert_template_argument): Adjust.
2023-03-15tree-optimization/109139 - fix .DEFERRED_INIT removalRichard Biener2-1/+14
The following make sure to strip MEMs when looking for unused decls on the LHS of .DEFERRED_INIT. PR tree-optimization/109139 * tree-ssa-live.cc (remove_unused_locals): Look at the base address for unused decls on the LHS of .DEFERRED_INIT. * gcc.dg/torture/pr109139.c: New testcase.
2023-03-15builtins: Move the character difference into result instead of reassigning ↵Xi Ruoyao1-2/+10
result [PR109086] expand_simple_binop() is allowed to allocate a new pseudo-register and return it, instead of forcing the result into the provided pseudo-register. This can cause a problem when we expand the unrolled loop for __builtin_strcmp: the compiler always generates code for all n iterations of the loop, so "result" will be an alias of the pseudo-register allocated and used in the last iteration; but at runtime the loop can break early, causing this pseudo-register uninitialized. Emit a move instruction in the iteration to force the difference into one register which has been allocated before the loop, to avoid this issue. gcc/ChangeLog: PR other/109086 * builtins.cc (inline_string_cmp): Force the character difference into "result" pseudo-register, instead of reassign the pseudo-register.
2023-03-15riscv: thead: Add support for the XTheadMemPair ISA extensionChristoph Müllner10-29/+824
The XTheadMemPair ISA extension allows to pair two loads or stores: * th.ldd (2x LD) * th.lwd (2x LW) * th.lwud (2x LWU) * th.sdd (2x SD) * th.swd (2x SW) The displacement of these instructions is quite limited: * Displacement := imm2 << shamt * imm2 is a 2-bit unsigned value {0..3} * shamt is 4 for th.ldd/th.sdd and 3 otherwise But even with this small displacement we can identify many candidates. The merge of the two loads/stores is realized in form of peephole2 passes that support instruction reordering. The CFA expansion (save/restore registers on/from stack) is not processed by the peephole2 pass and, therefore, needs special-treatment. Many ideas of this patch are inspired by similar/equal approaches in other backends. gcc/ChangeLog: * config.gcc: Add thead.o to RISC-V extra_objs. * config/riscv/peephole.md: Add mempair peephole passes. * config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New prototype. (th_mempair_operands_p): Likewise. (th_mempair_order_operands): Likewise. (th_mempair_prepare_save_restore_operands): Likewise. (th_mempair_save_restore_regs): Likewise. (th_mempair_output_move): Likewise. * config/riscv/riscv.cc (riscv_save_reg): Move code. (riscv_restore_reg): Move code. (riscv_for_each_saved_reg): Add code to emit mempair insns. * config/riscv/t-riscv: Add thead.cc. * config/riscv/thead.md (*th_mempair_load_<GPR:mode>2): New insn. (*th_mempair_store_<GPR:mode>2): Likewise. (*th_mempair_load_extendsidi2): Likewise. (*th_mempair_load_zero_extendsidi2): Likewise. * config/riscv/thead.cc: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmempair-1.c: New test. * gcc.target/riscv/xtheadmempair-2.c: New test. * gcc.target/riscv/xtheadmempair-3.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: thead: Add support for the XTheadFmv ISA extensionChristoph Müllner5-6/+95
The XTheadFmv ISA extension provides instructions to move data between 32-bit GP registers and 64-bit FP registers. Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> gcc/ChangeLog: * config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS) New constraint "th_f_fmv". (TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint "th_r_fmv". * config/riscv/riscv.cc (riscv_split_doubleword_move): Add split code for XTheadFmv. (riscv_secondary_memory_needed): XTheadFmv does not need secondary memory. * config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to movdf_hardfloat_rv32. * config/riscv/thead.md (th_fmv_hw_w_x): New INSN. (th_fmv_x_w): New INSN. (th_fmv_x_hw): New INSN. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmv-fmv.c: New test.
2023-03-15riscv: thead: Add support for the XTheadMac ISA extensionChristoph Müllner3-0/+182
The XTheadMac ISA extension provides multiply-accumulate/subtract instructions: * mula/mulaw/mulah * muls/mulsw/mulsh To benefit from middle-end passes, we expand the following named patterns in riscv.md (as they are not T-Head-specific): * maddhisi4 * msubhisi4 Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> gcc/ChangeLog: * config/riscv/riscv.md (maddhisi4): New expand. (msubhisi4): New expand. * config/riscv/thead.md (*th_mula<mode>): New pattern. (*th_mulawsi): New pattern. (*th_mulawsi2): New pattern. (*th_maddhisi4): New pattern. (*th_sextw_maddhisi4): New pattern. (*th_muls<mode>): New pattern. (*th_mulswsi): New pattern. (*th_mulswsi2): New pattern. (*th_msubhisi4): New pattern. (*th_sextw_msubhisi4): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmac-mula-muls.c: New test.
2023-03-15riscv: thead: Add support for the XTheadCondMov ISA extensionsChristoph Müllner13-24/+440
This patch adds support for XTheadCondMov ISA extension. The extension brings a one-sided conditional move (no else-assignment). Given that GCC has a great if-conversion pass, we don't need to do much, besides properly expanding mov<mode>cc accordingly and adjust the cost model. gcc/ChangeLog: * config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator. * config/riscv/riscv-protos.h (riscv_expand_conditional_move): Add prototype. * config/riscv/riscv.cc (riscv_rtx_costs): Add costs for XTheadCondMov. (riscv_expand_conditional_move): New function. (riscv_expand_conditional_move_onesided): New function. * config/riscv/riscv.md: Add support for XTheadCondMov. * config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add support for XTheadCondMov. (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: thead: Add support for the XTheadBb ISA extensionChristoph Müllner10-6/+288
This patch adds support for the XTheadBb ISA extension. Thus, there is a functional overlap of the new instructions with existing Bitmanip instruction, which allows a good amount of code sharing. However, the vendor extensions are cleanly separated from the standard extensions (e.g. by using INSN expand pattern that will re-emit RTL that matches the patterns of either Bitmanip or XThead INSNs). gcc/ChangeLog: * config/riscv/bitmanip.md (clzdi2): New expand. (clzsi2): New expand. (ctz<mode>2): New expand. (popcount<mode>2): New expand. (<bitmanip_optab>si2): Rename INSN. (*<bitmanip_optab>si2): Hide INSN name. (<bitmanip_optab>di2): Rename INSN. (*<bitmanip_optab>di2): Hide INSN name. (rotrsi3): Remove INSN. (rotr<mode>3): Add expand. (*rotrsi3): New INSN. (rotrdi3): Rename INSN. (*rotrdi3): Hide INSN name. (rotrsi3_sext): Rename INSN. (*rotrsi3_sext): Hide INSN name. (bswap<mode>2): Remove INSN. (bswapdi2): Add expand. (bswapsi2): Add expand. (*bswap<mode>2): Hide INSN name. * config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign extraction. * config/riscv/riscv.md (extv<mode>): New expand. (extzv<mode>): New expand. * config/riscv/thead.md (*th_srri<mode>3): New INSN. (*th_ext<mode>): New INSN. (*th_extu<mode>): New INSN. (*th_clz<mode>2): New INSN. (*th_rev<mode>2): New INSN. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-ext.c: New test. * gcc.target/riscv/xtheadbb-extu-2.c: New test. * gcc.target/riscv/xtheadbb-extu.c: New test. * gcc.target/riscv/xtheadbb-ff1.c: New test. * gcc.target/riscv/xtheadbb-rev.c: New test. * gcc.target/riscv/xtheadbb-srri.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: thead: Add support for the XTheadBs ISA extensionChristoph Müllner3-2/+26
This patch adds support for the XTheadBs ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. The cost model adjustment reuses the xbs:bext cost. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost. * config/riscv/thead.md (*th_tst<mode>3): New INSN. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbs-tst.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: thead: Add support for the XTheadBa ISA extensionChristoph Müllner3-0/+87
This patch adds support for the XTheadBa ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. gcc/ChangeLog: * config/riscv/riscv.md: Include thead.md * config/riscv/thead.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba-addsl.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: riscv-cores.def: Add T-Head XuanTie C906Christoph Müllner2-0/+32
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the core of the Allwinner D1). Note, that the tuning struct for the C906 is already part of GCC (it is also name "thead-c906"). gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-thead-c906.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15riscv: Add basic XThead* vendor extension supportChristoph Müllner15-0/+222
This patch add basic support for the following XThead* ISA extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadInt * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The extensions are just recognized by the compiler and feature test macros are generated (which this patch also brings tests for). gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add xthead* extensions. * config/riscv/riscv-opts.h (MASK_XTHEADBA): New. (MASK_XTHEADBB): New. (MASK_XTHEADBS): New. (MASK_XTHEADCMO): New. (MASK_XTHEADCONDMOV): New. (MASK_XTHEADFMEMIDX): New. (MASK_XTHEADFMV): New. (MASK_XTHEADINT): New. (MASK_XTHEADMAC): New. (MASK_XTHEADMEMIDX): New. (MASK_XTHEADMEMPAIR): New. (MASK_XTHEADSYNC): New. (TARGET_XTHEADBA): New. (TARGET_XTHEADBB): New. (TARGET_XTHEADBS): New. (TARGET_XTHEADCMO): New. (TARGET_XTHEADCONDMOV): New. (TARGET_XTHEADFMEMIDX): New. (TARGET_XTHEADFMV): New. (TARGET_XTHEADINT): New. (TARGET_XTHEADMAC): New. (TARGET_XTHEADMEMIDX): New. (TARGET_XTHEADMEMPAIR): new. (TARGET_XTHEADSYNC): New. * config/riscv/riscv.opt: Add riscv_xthead_subext. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba.c: New test. * gcc.target/riscv/xtheadbb.c: New test. * gcc.target/riscv/xtheadbs.c: New test. * gcc.target/riscv/xtheadcmo.c: New test. * gcc.target/riscv/xtheadcondmov.c: New test. * gcc.target/riscv/xtheadfmemidx.c: New test. * gcc.target/riscv/xtheadfmv.c: New test. * gcc.target/riscv/xtheadint.c: New test. * gcc.target/riscv/xtheadmac.c: New test. * gcc.target/riscv/xtheadmemidx.c: New test. * gcc.target/riscv/xtheadmempair.c: New test. * gcc.target/riscv/xtheadsync.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-15i386:Add missing OPTION_MASK_ISA_AVX512VL in i386-builtin.def for VAES builtinsHu, Lin12-4/+18
gcc/ChangeLog: PR target/109117 * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi, __builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi, __builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL. gcc/testsuite/ChangeLog: PR target/109117 * gcc.target/i386/pr109117-1.c: New test.
2023-03-15Daily bump.GCC Administrator6-1/+194
2023-03-15gcc/testsuite/gcc.dg: Fix pic test case for PE targetsJonathan Yong3-3/+15
gcc/testsuite/ChangeLog: * gcc.dg/pic-2.c: Fix expected __PIC__ value. * gcc.dg/pic-3.c: Ditto. * gcc.dg/pic-4.c: Ditto. Signed-off-by: Jonathan Yong <10walls@gmail.com>
2023-03-14c++: redeclaring member of constrained class template [PR96830]Patrick Palka3-0/+101
An out-of-line definition of a member of a constrained class template needs to repeat the template's constraints, but it turns out we don't verify anywhere that the two sets of constraints match. This patch adds such a check to push_template_decl, nearby a similar consistency check for the template parameter list lengths. PR c++/96830 gcc/cp/ChangeLog: * pt.cc (push_inline_template_parms_recursive): Set TEMPLATE_PARMS_CONSTRAINTS. (push_template_decl): For an out-of-line declaration, verify constraints for each enclosing template scope match those of the original template declaratation. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-class5.C: New test. * g++.dg/cpp2a/concepts-class5a.C: New test.
2023-03-14c++: constrained template friend class matching [PR96830]Patrick Palka2-2/+32
When instantiating a constrained template friend naming an already declared class template, tsubst_friend_class erroneously passes to redeclare_class_template the existing template's constraints instead of those of the friend declaration, which causes the constraint comparison check therein to trivially succeed and we fail to diagnose legitimate constraint mismatches. PR c++/96830 gcc/cp/ChangeLog: * pt.cc (redeclare_class_template): Add missing "of" in constraint mismatch diagnostic. (tsubst_friend_class): For an already declared class template, substitute and pass the friend declaration's constraints to redeclare_class_template instead of passing the existing template's constraints. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-friend14.C: New test.
2023-03-14c++: variable tmpl partial specialization [PR108468]Jason Merrill2-0/+14
Generally we expect TPARMS_PRIMARY_TEMPLATE to be set, but sometimes it isn't for partial instantiations. This ought to be improved, but it's trivial to work around it in this case. PR c++/108468 gcc/cp/ChangeLog: * pt.cc (unify_pack_expansion): Check that TPARMS_PRIMARY_TEMPLATE is non-null. gcc/testsuite/ChangeLog: * g++.dg/cpp1y/var-templ78.C: New test.
2023-03-14PR 109125 Modula2 SIGBUS in m2pim_ldtoa_ldtoaGaius Mulley3-380/+382
13 regression failures seen on sparc SIGBUS in m2pim_ldtoa_ldtoa. This patch fixes int bool parameter mismatches between the definition modules and their C/C++ implementations. gcc/m2/ChangeLog: PR modula2/109125 * gm2-libs-ch/cgetopt.c (cgetopt_SetOption): Replace int for bool. * gm2-libs-ch/termios.c (doSetUnset): Replace int for bool. * gm2-libs/Builtins.mod (isfinitef): Correct typo in return statement. libgm2/ChangeLog: PR modula2/109125 * libm2iso/ErrnoCategory.cc (FALSE): Remove. (TRUE): Remove. * libm2iso/wrapsock.c (TRUE): Remove. (FALSE): Remove. * libm2iso/wraptime.cc (TRUE): Remove. (FALSE): Remove. * libm2pim/cgetopt.cc: Replace int for bool for every BOOLEAN parameter in the definition module. * libm2pim/dtoa.cc: Ditto. * libm2pim/ldtoa.cc: Ditto. * libm2pim/termios.cc: Ditto. (doSetUnset): Replace int for bool. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-03-14c++: -Wreturn-type with if (true) throw [PR107310]Jason Merrill3-2/+24
I removed this folding in GCC 12 because it was interfering with an experiment of richi's, but that never went in and the change causes regressions, so let's put it back. This reverts commit r12-5638-ga3e75c1491cd2d. PR c++/107310 gcc/cp/ChangeLog: * cp-gimplify.cc (genericize_if_stmt): Restore folding of constant conditions. gcc/testsuite/ChangeLog: * c-c++-common/Wimplicit-fallthrough-39.c: Adjust warning. * g++.dg/warn/Wreturn-6.C: New test.
2023-03-14i386: Fix up split_double_concat [PR109109]Jakub Jelinek3-3/+328
In my PR107627 change I've missed one important case, which causes miscompilation of f4 and f6 in the following tests. Combine matches there *concatsidi3_3 define_insn_and_split (as with all other f* functions in those tests), and RA ends up with: (insn 11 10 17 2 (set (reg:DI 0 ax [89]) (ior:DI (ashift:DI (zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI 0 ax [94]) (const_int 4 [0x4])) (symbol_ref:SI ("arr") [flags 0x2] <var_decl 0x7f4e7fe4ccf0 arr>)) [1 arr[ax_6(D)]+0 S4 A32])) (const_int 32 [0x20])) (zero_extend:DI (reg:SI 1 dx [95])))) "pr109109-6.c":24:49 681 {*concatsidi3_3} (nil)) split_double_concat turned that into: movl arr(,%eax,4), %edx movl %edx, %eax which is incorrect, because the first instruction overrides the input %edx value that should be put into output %eax; the two insns can't be swapped because the MEM's address uses %eax. The following patch fixes that case to emit movl arr(,%eax,4), %eax xchgl %edx, %eax instead. 2023-03-14 Jakub Jelinek <jakub@redhat.com> PR target/109109 * config/i386/i386-expand.cc (split_double_concat): Fix splitting when lo is equal to dhi and hi is a MEM which uses dlo register. * gcc.target/i386/pr109109-1.c: New test. * gcc.target/i386/pr109109-2.c: New test.
2023-03-14d: Fix undefined reference to lambda defined in private enum [PR109108]Iain Buclaw3-28/+34
Previously lambdas were connected to the module they were defined in. Now they are emitted into every referencing compilation unit, and are given one-only linkage. PR d/109108 gcc/d/ChangeLog: * decl.cc (function_defined_in_root_p): Remove. (get_symbol_decl): Set DECL_LAMBDA_FUNCTION_P on function literals. (start_function): Unconditionally unset DECL_EXTERNAL (set_linkage_for_decl): Give lambda functions one-only linkage. gcc/testsuite/ChangeLog: * gdc.dg/torture/imports/pr109108.d: New test. * gdc.dg/torture/pr109108.d: New test.
2023-03-14ipa-cp: Improve updating behavior when profile counts have gone badMartin Jambor1-7/+22
Looking into the behavior of profile count updating in PR 107925, I noticed that an option not considered possible was actually happening, and - with the guesswork in place to distribute unexplained counts - it simply can happen. Currently it is handled by dropping the counts to local estimated zero, whereas it is probably better to leave the count as they are but drop the category to GUESSED_GLOBAL0 - which is what profile_count::combine_with_ipa_count in a similar case (or so I hope :-) gcc/ChangeLog: 2023-02-20 Martin Jambor <mjambor@suse.cz> PR ipa/107925 * ipa-cp.cc (update_profiling_info): Drop counts of orig_node to global0 instead of zeroing when it does not have as many counts as it should.
2023-03-14ipa-cp: Fix various issues in update_specialized_profile (PR 107925)Martin Jambor1-4/+6
The patch below fixes various issues in function update_specialized_profile. The main is removal of the assert which is bogus in the case of recursive cloning. The division of unexplained counts is guesswork, which then leads to updates of counts of recursive edges, which then can be redirected to the new clone and their count subtracted from the count and there simply may not be enough left in the count of the original node - especially when we clone a lot because of using --param ipa-cp-eval-threshold=1. The other issue was omission to drop the count of the original node to ipa count. And when calculating the remainder, we should use lenient_count_portion_handling to account for partial train runs. Finally, the patch adds dumping of the original count which I think is useful. gcc/ChangeLog: 2023-02-17 Martin Jambor <mjambor@suse.cz> PR ipa/107925 * ipa-cp.cc (update_specialized_profile): Drop orig_node_count to ipa count, remove assert, lenient_count_portion_handling, dump also orig_node_count.
2023-03-14i386: Use movss to implement V2SImode VEC_PERM.Uros Bizjak2-10/+8
Perform V2SI vector permutation in the same way as existing V2SF for TARGET_MMX_WITH_SSE targets. The testcase: typedef unsigned int v2si __attribute__((vector_size(8))); v2si foo(v2si x, v2si y) { return (v2si){y[0], x[1]}; } is currently compiled to (-O2): foo: movdqa %xmm0, %xmm2 movdqa %xmm1, %xmm0 pshufd $0xe5, %xmm2, %xmm2 punpckldq %xmm2, %xmm0 ret and with the patched compiler: foo: movss %xmm1, %xmm0 ret The functionality is already tested in gcc.target/i386/vperm-v2si.c gcc/ChangeLog: * config/i386/i386-expand.cc (expand_vec_perm_movs): Handle V2SImode for TARGET_MMX_WITH_SSE. * config/i386/mmx.md (*mmx_movss_<mode>): Rename from *mmx_movss using V2FI mode iterator to handle both V2SI and V2SF modes.
2023-03-14testsuite: Fix up g++.dg/cpp2a/concepts-lambda3.C [PR108972]Jakub Jelinek1-2/+3
On Fri, Mar 10, 2023 at 01:49:38PM -0500, Jason Merrill via Gcc-patches wrote: > gcc/testsuite/ChangeLog: > > * g++.dg/cpp2a/concepts-lambda3.C: Run at lower std levels, > but expect errors. I'm seeing +UNRESOLVED: g++.dg/cpp2a/concepts-lambda3.C -std=c++11 compilation failed to produce executable +UNRESOLVED: g++.dg/cpp2a/concepts-lambda3.C -std=c++14 compilation failed to produce executable +UNRESOLVED: g++.dg/cpp2a/concepts-lambda3.C -std=c++17 compilation failed to produce executable +UNRESOLVED: g++.dg/cpp2a/concepts-lambda3.C -std=c++98 compilation failed to produce executable with this change, and if I test with GXX_TESTSUITE_STDS=98,11,14,17,20,2b make check-g++ -k RUNTESTFLAGS="--target_board=unix\{-m32,-m64,-m64/-fconcepts\} dg.exp=concepts-lambda3.C" I see even FAILs for the -fconcepts case, so apparently even -std=c++17 -fconcepts isn't enough to make it compile without errors. The following patch will expect errors for all of c++17_down and will make the test dg-do compile for that case too, such that the UNRESOLVED stuff is gone. 2023-03-14 Jakub Jelinek <jakub@redhat.com> PR c++/108972 PR testsuite/109129 * g++.dg/cpp2a/concepts-lambda3.C: Use dg-do run only for c++20, for c++17_down dg-do compile. Expect dg-excess-errors for c++17_down rather than ! concepts.
2023-03-14c++: Treat unnamed bitfields as padding for ↵Jakub Jelinek2-2/+12
__has_unique_object_representations [PR109096] As reported in the PR, for __has_unique_object_representations we were treating unnamed bitfields as named ones, which is wrong, they are actually padding. THe following patch fixes that. 2023-03-14 Jakub Jelinek <jakub@redhat.com> PR c++/109096 * tree.cc (record_has_unique_obj_representations): Ignore unnamed bitfields. * g++.dg/cpp1z/has-unique-obj-representations3.C: New test.
2023-03-14RISC-V: Avoid calloc() poisoning on muslSam James2-1/+5
This fixes errors like: ``` In file included from /usr/include/pthread.h:30, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/riscv64-gentoo-linux-musl/bits/gthr-default.h:35, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/riscv64-gentoo-linux-musl/bits/gthr.h:148, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/ext/atomicity.h:35, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/bits/ios_base.h:39, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/ios:42, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/istream:38, from /usr/lib/gcc/riscv64-gentoo-linux-musl/12/include/g++-v12/sstream:38, from /var/tmp/portage/sys-devel/gcc-13.0.1_pre20230305/work/gcc-13-20230305/gcc/config/riscv/genrvv-type-indexer.cc:22: /usr/include/sched.h:84:7: error: attempt to use poisoned "calloc" 84 | void *calloc(size_t, size_t); | ^ /usr/include/sched.h:124:36: error: attempt to use poisoned "calloc" 124 | #define CPU_ALLOC(n) ((cpu_set_t *)calloc(1,CPU_ALLOC_SIZE(n))) | ^ make[3]: *** [Makefile:2855: build/genrvv-type-indexer.o] Error 1 ``` See also 3b21c21f3f5726823e19728fdd1571a14aae0fb3 and 49d508065bdd36fb1a9b6aad9666b1edb5e06474, which was fixed in PR106102. gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc: Avoid calloc() poisoning on musl by including <sstream> earlier. * system.h: Add INCLUDE_SSTREAM. Signed-off-by: Sam James <sam@gentoo.org>
2023-03-14Remove variables only used with .DEFERRED_INITRichard Biener2-1/+36
In PR109087 it was noticed that we rely on DSE to remove .DEFERRED_INIT when it is the only remaining use of a variable. Since DSE is imperfect and even if it were not would be limited by the amount of statements to walk the following enhances the unused var removal pass to handle .DEFERRED_INIT like CLOBBERs, thus we do not keep local variables just because they are deferred initialized. * tree-ssa-live.cc (remove_unused_locals): Do not treat the .DEFERRED_INIT of a variable as use, instead remove that if it is the only use. * gcc.dg/auto-init-unused-1.c: New testcase.
2023-03-14Add testcase for ifcvt fixEric Botcazou1-0/+69
gcc/testsuite/ PR tree-optimization/109005 * gnat.dg/specs/opt6.ads: New test.
2023-03-14Revert latest change to emit_group_storeEric Botcazou1-10/+7
This pessimizes on targets with insv instructions. gcc/ PR rtl-optimization/107762 * expr.cc (emit_group_store): Revert latest change.
2023-03-14testsuite: move mla_1 test to aarch64 only [PR109118]Tamar Christina1-3/+2
I previously made the test generic, but there's no list of targets that support integer MLA, and so it's not really feasible for me to make this generic. As such I've moved it to be AArch64 only. gcc/testsuite/ChangeLog: PR testsuite/109118 * gcc.dg/mla_1.c: Moved to... * gcc.target/aarch64/sve/mla_3.c: ...here.
2023-03-14ifcvt: Lower bitfields only if suitable for scalar register [PR 109005]Andre Vieira1-3/+3
This patch fixes the condition check for eligilibity of lowering bitfields, where before we would check for non-BLKmode types, in the hope of excluding unsuitable aggregate types, we now check directly the representative is not an aggregate type, i.e. suitable for a scalar register. gcc/ChangeLog: PR tree-optimization/109005 * tree-if-conv.cc (get_bitfield_rep): Replace BLKmode check with aggregate type check.
2023-03-14tree-vect-patterns: Fix up ICE in upper_bound [PR109115]Jakub Jelinek2-1/+21
As mentioned in the PR, range_of_expr returns false if the type of the expression isn't suitable for corresponding range type, but doesn't if the range is undefined for other reasons. Still, lower/upper_bound is defined only for ranges which actually have at least one pair of subranges, VR_UNDEFINED range doesn't have it. 2023-03-14 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/109115 * tree-vect-patterns.cc (vect_recog_divmod_pattern): Don't use r.upper_bound () on r.undefined_p () range. * gcc.dg/pr109115.c: New test.
2023-03-14Fix overactive sanity check in profile_count::to_sreal_scaleJan Hubicka1-23/+11
As discussed in the PR log, profile_count::to_cgraph_frequency was originally intended to work across function boundary and has some extra logic and sanity check for that. It is used only within single function and with current API it can not really work well globally, so this patch synchronizes its implementation with probability_in which does similar job but to determine relative probability. gcc/ChangeLog: 2023-03-14 Jan Hubicka <hubicka@ucw.cz> PR tree-optimization/106896 * profile-count.cc (profile_count::to_sreal_scale): Synchronize implementatoin with probability_in; avoid some asserts.
2023-03-14New testcaseRichard Biener1-0/+109
This is a reduced testcase for an issue I ran into when trying to improve PTA compile-time further, there wasn't any C family runfail in the testsuite for this. * g++.dg/torture/20230313.C: New testcase.
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