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2023-11-21ada: Avoid Style_Checks pragmas affecting other unitsViljar Indus1-0/+17
gcc/ada/ * par.adb: Restore Style_Checks after parsing each unit.
2023-11-21ada: Fix type for SPARK expansion on deep delta aggregatesYannick Moy1-1/+1
gcc/ada/ * exp_spark.adb (Expand_SPARK_Delta_Or_Aggregate): Fix type.
2023-11-21ada: Further cleanup in finalization machineryEric Botcazou1-4/+1
The bodies of generic units are instantiated separately by GNAT at the end of the processing of the compilation unit. This requires the deferral of the generation of cleanups and finalization actions in enclosing scopes, except for instantiations in generic units where they are not generated. The criterion used to detect this latter case is Inside_A_Generic, but this global variable is not properly updated during the instantiation of generic bodies, leading to problems with nested instantiations, so it is changed to Expander_Active instead. As a matter of fact, the exact same idiom is used a few lines above to clear the Needs_Body variable. gcc/ada/ * sem_ch12.adb (Analyze_Package_Instantiation): Test Expander_Active to detect generic contexts for the generation of cleanup actions.
2023-11-21ada: Fix string indexing within GNAT.Calendar.Time_IO.ValueJustin Squirek1-2/+2
The patch fixes an issue in the compiler whereby calls to GNAT.Calendar.Time_IO.Value where the actual for formal String Date with indexing starting at any value besides one would result in a spurious runtime exception. gcc/ada/ * libgnat/g-catiio.adb (Value): Modify conditionals to use 'Last instead of 'Length
2023-11-21ada: Small improvement to Null_Status functionEric Botcazou1-1/+1
The function is used to optimize away access checks. gcc/ada/ * sem_util.adb (Null_Status): Deal with unchecked type conversions.
2023-11-21ada: Further cleanup in finalization machineryEric Botcazou3-46/+2
This removes the specific treatment of transient scopes in initialization procedures, which is obsolete. gcc/ada/ * exp_aggr.adb (Convert_To_Assignments): Do not treat initialization procedures specially when it comes to creating a transient scope. * exp_ch7.adb (Build_Finalizer.Process_Declarations): Likewise. * exp_util.adb (Requires_Cleanup_Actions): Likewise.
2023-11-21ada: Use CLOCK_MONOTONIC on VxWorksDoug Rupp1-1/+2
The monotonic clock keeps track of the time that has elapsed since system startup; that is, the value returned by clock_gettime() is the amount of time (in seconds and nanoseconds) that has passed since the system booted. The monotonic clock cannot be reset. As a result, time interval measurements made relative to the monotonic clock are not subject to errors resulting from the clock time being unexpectedly adjusted between the interval start and end. gcc/ada/ * s-oscons-tmplt.c: #define CLOCK_RT_Ada "CLOCK_MONOTONIC" for __vxworks
2023-11-21ada: Deep delta aggregates cleanup.Steve Baird1-1/+1
Cleanup after the introduction of deep delta aggregates. Eliminate a new gnatcheck message. gcc/ada/ * sem_aggr.adb: Replace "not Present (...)" call with "No (...)" call.
2023-11-21ada: Small cleanup in finalization machineryEric Botcazou5-45/+8
This removes an obsolete flag and adjusts a couple of obsolete comments. gcc/ada/ * gen_il-fields.ads (Opt_Field_Enum): Remove Is_Finalization_Wrapper * gen_il-gen-gen_nodes.adb (N_Block_Statement): Likewise. * sinfo.ads (Is_Finalization_Wrapper): Delete. * exp_ch7.adb (Build_Finalizer.Process_Declarations): Adjust comment and remove obsolete code testing the Is_Finalization_Wrapper flag. * exp_util.adb (Requires_Cleanup_Actions): Likewise.
2023-11-21ada: Runtime recompilation instructions improvements.Doug Rupp1-6/+7
Revise instructions to work on both cross and native targets hosted on Linux gcc/ada/ * libgnat/libada.gpr: Revise section 1
2023-11-21ada: Deep delta aggregatesSteve Baird6-66/+522
Add support for "deep" delta aggregates, a GNAT-defined language extension conditionally enabled via the -gnatX0 switch. In a deep delta aggregate, a delta choice may specify a subcomponent (as opposed to just a component). gcc/ada/ * par.adb: Add new Boolean variable Inside_Delta_Aggregate. * par-ch4.adb (P_Simple_Expression): Add support for a deep delta aggregate choice. We turn a sequence of selectors into a peculiar tree. We build a component (Indexed or Selected) whose prefix is another such component, etc. The leftmost prefix at the bottom of the tree has a "name" which is the first selector, without any further prefix. For something like "with delta (1)(2) => 3" where the type of the aggregate is an array of arrays of integers, we'll build an N_Indexed_Component whose prefix is an integer literal 1. This is consistent with the trees built for "regular" (Ada-defined) delta aggregates. * sem_aggr.adb (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice): New queries. (Resolve_Deep_Delta_Assoc): new procedure. (Resolve_Delta_Array_Aggregate): call Resolve_Deep_Delta_Assoc in deep case. (Resolve_Delta_Record_Aggregate): call Resolve_Deep_Delta_Assoc in deep case. (Get_Component_Type): new function replaces old Get_Component function. * sem_aggr.ads (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice): New queries. * exp_aggr.adb (Expand_Delta_Array_Aggregate): add nested function Make_Array_Delta_Assignment_LHS; call it instead of Make_Indexed_Component. (Expand_Delta_Record_Aggregate): add nested function Make_Record_Delta_Assignment_LHS; call it instead of Make_Selected_Component. * exp_spark.adb (Expand_SPARK_Delta_Or_Update): Insert range checks for indexes in deep delta aggregates.
2023-11-21ada: Fix Ada.Text_IO.Delete with "encoding=8bits" formRonan Desplanques6-10/+24
Before this patch, on Windows, file with non-ASCII Latin1 names could be created with Ada.Text_IO.Create by passing "encoding=8bits" through the Form parameter and a Latin1-encoded string through the Name parameter, but calling Ada.Text_IO.Delete on them raised an illegitimate exception. This patch fixes this by making the wrappers of the unlink system function aware of the encoding value passed through the Form parameter. It also removes an unnecessary curly-brace block. gcc/ada/ * adaint.c (__gnat_unlink): Add new parameter and fix text conversion on Windows. Remove unnecessary curly braces. * adaint.h (__gnat_unlink): Add new parameter. * libgnat/i-cstrea.ads (unlink): Adapt to __gnat_unlink signature change. * libgnat/i-cstrea.adb (unlink): New Subprogram definition. * libgnat/s-crtl.ads (unlink): Adapt to __gnat_unlink signature change. * libgnat/s-fileio.adb (Delete): Pass encoding argument to unlink.
2023-11-21ada: Fix spurious error on call with default parameter in generic packageEric Botcazou2-5/+16
This occurs when the default value is a function call returning a private type, and is caused by a bad interaction between two internal mechanisms. gcc/ada/ * sem_ch12.adb (Save_Global_References.Set_Global_Type): Beef up comment about the setting of the full view. * sem_res.adb (Resolve_Actuals.Insert_Default): Add another bypass for the case of a generic context.
2023-11-21ada: Fix misplaced index directive in documentationMarc Poulhiès2-14/+25
The index directive must be located before the indexed element, at least for the generated texinfo to be correct. See: https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html#directive-index This was reported along with changes done in https://inbox.sourceware.org/gcc-patches/20230223102714.3606058-3-arsen@aarsen.me/ gcc/ada/ * doc/gnat_ugn/the_gnat_compilation_model.rst: Move index directives. * gnat_ugn.texi: Regenerate.
2023-11-21ada: Fix SCOs generation for aspect specificationsPierre-Marie de Rodat1-0/+7
The recent overhaul for the representation of aspect specifications in the tree broke SCOs generation: decisions that appeared in aspects were processed twice, leading to the emission of erroneous obligations. Tweak SCOs generation to skip aspect specifications the second time to go back to the previous behavior. gcc/ada/ * par_sco.adb (Process_Decisions)<Process_Node>: Skip aspect specifications.
2023-11-21ada: Always use -gnatg in run-time GPR filesRonan Desplanques1-1/+1
This patch makes it so -gnatg is always passed to the compiler when rebuilding the run-time library with the dedicated GPR files. Before this patch, if a user rebuilt the run-time with -XADAFLAGS=XXX where XXX didn't include "-gnatg", the build would immediately fail. This case occurs when following the instructions in libada.gpr, which use '-XADAFLAGS="-gnatn"'. gcc/ada/ * libgnat/libgnat_common.gpr: Unconditionally pass -gnatg.
2023-11-21ada: Trivial typo fix in commentMarc Poulhiès1-1/+1
gcc/ada/ * exp_util.ads: Typo fix.
2023-11-21gcov: Formatting fixesJakub Jelinek1-7/+7
I've noticed the r14-5579 commit introduced some formatting issues, this patch fixes what I saw. 2023-11-21 Jakub Jelinek <jakub@redhat.com> gcc/ * tree-profile.cc (gen_counter_update, tree_profiling): Formatting fixes. libgcc/ * libgcov.h (GCOV_SUPPORTS_ATOMIC): Formatting fixes.
2023-11-21testsuite: Fix up pr111309-2.c on arm [PR111309]Jakub Jelinek1-2/+2
ARM defaults to -fshort-enums and the following testcase FAILs there in 2 lines. The difference is that in C++, E0 has enum E type, which normally has unsigned int underlying type, so it isn't int nor something that promotes to int, which is why we diagnose it (in C it is promoted to int). But with -fshort-enums, the underlying type is unsigned char in that case, which promotes to int just fine. The following patch adjusts the expectations, such that we don't expect it on arm or when people manually test with -fshort-enums. 2023-11-21 Jakub Jelinek <jakub@redhat.com> PR c/111309 * c-c++-common/pr111309-2.c (foo): Don't expect errors for C++ with -fshort-enums if second argument is E0.
2023-11-21builtins: Fix fold_builtin_query clzg/ctzg side-effects handling [PR112639]Jakub Jelinek2-0/+36
As the testcase shows, I've missed one spot where initially the code thinks it could use 2 argument IFN_CLZ/IFN_CTZ form, but then verifies it can't because it doesn't have the right target value and turns it into the arg0 ? arg1 : .C[LT]Z (arg0) form. That form evaluates the argument twice though and so needs save_expr, which I've missed to call in that case. In other cases where it is known from the beginning that it will be needed (e.g. the __builtin_clzg case on types smaller than unsigned int where we'll need to add an addend to the clz value) or the unsigned __int128 expansion called save_expr before. 2023-11-21 Jakub Jelinek <jakub@redhat.com> PR middle-end/112639 * builtins.cc (fold_builtin_bit_query): If arg0 has side-effects, arg1 is specified but cleared, call save_expr on arg0. * gcc.dg/torture/pr112639.c: New test.
2023-11-21[APX PPX] Support Intel APX PPXHongyu Wang11-36/+107
PPX stands for Push-Pop Acceleration. PUSH/PUSH2 and its corresponding POP can be marked with a 1-bit hint to indicate that the POP reads the value written by the PUSH from the stack. The processor tracks these marked instructions internally and fast-forwards register data between matching PUSH and POP instructions, without going through memory or through the training loop of the Fast Store Forwarding Predictor (FSFP). This feature can also be adopted to PUSH2/POP2. For GCC, we emit explicit suffix 'p' (paired) to indicate the push/pop pair are marked with PPX hint. To separate form original push/pop, we add an UNSPEC on top of those PUSH/POP patterns. In the first implementation we only emit them under prologue/epilogue when saving/restoring callee-saved registers to make sure push/pop are paired. So an extra flag was added to check if PPX insns can be emitted for those register save/restore interfaces. The PPX hint is purely a performance hint. If the 'p' suffix is not emitted for paired push/pop, the PPX optimization will be disabled, while program sematic will not be affected at all. gcc/ChangeLog: * config/i386/i386-expand.h (gen_push): Add default bool parameter. (gen_pop): Likewise. * config/i386/i386-opts.h (enum apx_features): Add apx_ppx, add it to apx_all. * config/i386/i386.cc (ix86_emit_restore_reg_using_pop): Add ppx_p parameter for function declaration. (gen_push2): Add ppx_p parameter, emit push2p if ppx_p is true. (gen_push): Likewise. (ix86_emit_restore_reg_using_pop2): Likewise for pop2p. (ix86_emit_save_regs): Emit pushp/push2p under TARGET_APX_PPX. (ix86_emit_restore_reg_using_pop): Add ppx_p, emit popp insn and adjust cfi when ppx_p is ture. (ix86_emit_restore_reg_using_pop2): Add ppx_p and parse to its callee. (ix86_emit_restore_regs_using_pop2): Likewise. (ix86_expand_epilogue): Parse TARGET_APX_PPX to ix86_emit_restore_reg_using_pop. * config/i386/i386.h (TARGET_APX_PPX): New. * config/i386/i386.md (UNSPEC_APX_PPX): New unspec. (pushp_di): New define_insn. (popp_di): Likewise. (push2p_di): Likewise. (pop2p_di): Likewise. * config/i386/i386.opt: Add apx_ppx enum. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-interrupt-1.c: Adjust option to restrict them under certain subfeatures. * gcc.target/i386/apx-push2pop2-1.c: Likewise. * gcc.target/i386/apx-push2pop2_force_drap-1.c: Likewise. * gcc.target/i386/apx-push2pop2_interrupt-1.c: Likewise. * gcc.target/i386/apx-ppx-1.c: New test.
2023-11-21middle-end/112622 - adjust arm testcasesRichard Biener4-16/+16
The error message improved, adjust arm specific testcases. * gcc.target/arm/bfloat16_vector_typecheck_1.c: Adjust. * gcc.target/arm/bfloat16_vector_typecheck_2.c: Likewise. * gcc.target/aarch64/bfloat16_vector_typecheck_1.c: Likewise. * gcc.target/aarch64/bfloat16_vector_typecheck_2.c: Likewise.
2023-11-21tree-optimization/111970 - fix issue with SLP of emulated gather/scatterRichard Biener1-2/+4
There's a missed index adjustment for the SLP vector number when computing the index/data vectors for emulated gather/scatter with SLP. The following fixes this. PR tree-optimization/111970 * tree-vect-stmts.cc (vectorizable_load): Fix offset calculation for SLP gather load. (vectorizable_store): Likewise for SLP scatter store.
2023-11-21LoongArch: Fix libgcc build failure when libc is not availableXi Ruoyao1-1/+9
To use int64_t we included <stdint.h> in loongarch-def.h. Unfortunately, loongarch-def.h is also used by libgcc etc., causing a build failure when building a "stage1" cross compiler at which the target libc is not built yet. As int64_t is used for a C-compatible replacement of HOST_WIDE_INT, it's not directly or indirectly referred by the target libraries. So guard everything requiring stdint.h with #if then they'll not block target libraries. gcc/ChangeLog: * config/loongarch/loongarch-def.h (stdint.h): Guard with #if to exclude it for target libraries. (loongarch_isa_base_features): Likewise. (loongarch_isa): Likewise. (loongarch_abi): Likewise. (loongarch_target): Likewise. (loongarch_cpu_default_isa): Likewise.
2023-11-21RISC-V: Fix reduc_run-9.c test value check bugJuzhe-Zhong1-3/+2
The current test value check is incorrect which is exposed on -march=rv64gcv_zvl256b Confirm on X86 also abort: [jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$./a.out ------33.000000,4078.000000,45001776.000000,63369904.000000--- Aborted (core dumped) Adapt the value check according to X86 result. Pushed as it is obvious. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c: Fix bug.
2023-11-21Support reduc_{and,ior,xor}_scal_m for V4HI/V8QI/V4QImodeliuhongt3-2/+70
gcc/ChangeLog: PR target/112325 * config/i386/i386-expand.cc (emit_reduc_half): Hanlde V8QImode. * config/i386/mmx.md (reduc_<code>_scal_<mode>): New expander. (reduc_<code>_scal_v4qi): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112325-mmx-1.c: New test.
2023-11-21Daily bump.GCC Administrator4-1/+613
2023-11-20Trivial typo fix in variadicMarc Poulhiès3-10/+10
Fix all occurences of varadic, except for Rust (will be part of another change). gcc/ChangeLog: * config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic. * config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name. (nvptx_declare_function_name): Likewise. (nvptx_call_args): Likewise. (nvptx_expand_call): Likewise. gcc/cp/ChangeLog: * lambda.cc (compare_lambda_sig): Fix typo in variadic. libcpp/ChangeLog: * macro.cc (parse_params): Fix typo in variadic. (create_iso_definition): Likewise. Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
2023-11-20gcov: Use unshare_expr() in gen_counter_update()Sebastian Huber1-1/+1
This fixes issues like this: gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c: In function 'main': gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: error: incorrect sharing of tree nodes __gcov0.main[0] # .MEM_12 = VDEF <.MEM_9> __gcov0.main[0] = PROF_edge_counter_4; during IPA pass: profile gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: internal compiler error: verify_gimple failed Unshare the counter expression in the second gimple_build_assign() in gen_counter_update(). This is similar to the original gimple_gen_edge_profiler() for "ref": void gimple_gen_edge_profiler (int edgeno, edge e) { tree one; one = build_int_cst (gcov_type_node, 1); if (flag_profile_update == PROFILE_UPDATE_ATOMIC) [...] else { tree ref = tree_coverage_counter_ref (GCOV_COUNTER_ARCS, edgeno); tree gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node, NULL, "PROF_edge_counter"); gassign *stmt1 = gimple_build_assign (gcov_type_tmp_var, ref); gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node, NULL, "PROF_edge_counter"); gassign *stmt2 = gimple_build_assign (gcov_type_tmp_var, PLUS_EXPR, gimple_assign_lhs (stmt1), one); gassign *stmt3 = gimple_build_assign (unshare_expr (ref), gimple_assign_lhs (stmt2)); gsi_insert_on_edge (e, stmt1); gsi_insert_on_edge (e, stmt2); gsi_insert_on_edge (e, stmt3); } } However, the orignal gimple_gen_time_profiler() did not use unshare_expr() for the counter expression (tree_time_profiler_counter): void gimple_gen_time_profiler (unsigned tag) { [...] /* Emit: counters[0] = ++__gcov_time_profiler_counter. */ if (flag_profile_update == PROFILE_UPDATE_ATOMIC) [...] else { tree tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile"); gassign *assign = gimple_build_assign (tmp, tree_time_profiler_counter); gsi_insert_before (&gsi, assign, GSI_NEW_STMT); tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile"); assign = gimple_build_assign (tmp, PLUS_EXPR, gimple_assign_lhs (assign), one); gsi_insert_after (&gsi, assign, GSI_NEW_STMT); assign = gimple_build_assign (original_ref, tmp); gsi_insert_after (&gsi, assign, GSI_NEW_STMT); assign = gimple_build_assign (tree_time_profiler_counter, tmp); gsi_insert_after (&gsi, assign, GSI_NEW_STMT); } } gcc/ChangeLog: * tree-profile.cc (gen_counter_update): Use unshare_expr() for the counter expression in the second gimple_build_assign().
2023-11-20inter-procedural value range propagationJan Hubicka38-32/+283
implement very basic propapgation of return value ranges from VRP pass. This helps std::vector's push_back since we work out value range of allocated block. This propagates only within single translation unit. I hoped we will also do the propagation at WPA stage, but that needs more work on ipa-cp side. I also added code auto-detecting return_nonnull and corresponding -Wsuggest-attribute. gcc/ChangeLog: * cgraph.cc (add_detected_attribute_1): New function. (cgraph_node::add_detected_attribute): Likewise. * cgraph.h (cgraph_node::add_detected_attribute): Declare. * common.opt: Add -Wsuggest-attribute=returns_nonnull. * doc/invoke.texi: Document new flag. * gimple-range-fold.cc (fold_using_range::range_of_call): Use known reutrn value ranges. * ipa-prop.cc (struct ipa_return_value_summary): New type. (class ipa_return_value_sum_t): New type. (ipa_return_value_sum): New summary. (ipa_record_return_value_range): New function. (ipa_return_value_range): New function. * ipa-prop.h (ipa_return_value_range): Declare. (ipa_record_return_value_range): Declare. * ipa-pure-const.cc (warn_function_returns_nonnull): New funcion. * ipa-utils.h (warn_function_returns_nonnull): Declare. * symbol-summary.h: Fix comment. * tree-vrp.cc (execute_ranger_vrp): Record return values. gcc/testsuite/ChangeLog: * g++.dg/ipa/devirt-2.C: Add noipa attribute to prevent ipa-vrp. * g++.dg/ipa/devirt-7.C: Disable ipa-vrp. * g++.dg/ipa/ipa-icf-2.C: Disable ipa-vrp. * g++.dg/ipa/ipa-icf-3.C: Disable ipa-vrp. * g++.dg/ipa/ivinline-1.C: Disable ipa-vrp. * g++.dg/ipa/ivinline-3.C: Disable ipa-vrp. * g++.dg/ipa/ivinline-5.C: Disable ipa-vrp. * g++.dg/ipa/ivinline-8.C: Disable ipa-vrp. * g++.dg/ipa/nothrow-1.C: Disable ipa-vrp. * g++.dg/ipa/pure-const-1.C: Disable ipa-vrp. * g++.dg/ipa/pure-const-2.C: Disable ipa-vrp. * g++.dg/lto/inline-crossmodule-1_0.C: Disable ipa-vrp. * gcc.c-torture/compile/pr106433.c: Add noipa attribute to prevent ipa-vrp. * gcc.c-torture/execute/frame-address.c: Likewise. * gcc.dg/vla-1.c: Add noipa attribute to prevent ipa-vrp. * gcc.dg/ipa/fopt-info-inline-1.c: Disable ipa-vrp. * gcc.dg/ipa/ipa-icf-25.c: Disable ipa-vrp. * gcc.dg/ipa/ipa-icf-38.c: Disable ipa-vrp. * gcc.dg/ipa/pure-const-1.c: Disable ipa-vrp. * gcc.dg/ipa/remref-0.c: Add noipa attribute to prevent ipa-vrp. * gcc.dg/tree-prof/time-profiler-1.c: Disable ipa-vrp. * gcc.dg/tree-prof/time-profiler-2.c: Disable ipa-vrp. * gcc.dg/tree-ssa/pr110269.c: Disable ipa-vrp. * gcc.dg/tree-ssa/pr20701.c: Disable ipa-vrp. * gcc.dg/tree-ssa/vrp05.c: Disable ipa-vrp. * gcc.dg/tree-ssa/return-value-range-1.c: New test.
2023-11-20tree-optimization/112618 - unused .MASK_CALLRichard Biener2-1/+36
We have to make sure to remove unused .MASK_CALL internal function calls after vectorization. PR tree-optimization/112618 * tree-vect-loop.cc (vect_transform_loop_stmt): For not relevant and unused .MASK_CALL make sure we remove the scalar stmt. * gcc.dg/pr112618.c: New testcase.
2023-11-20tree-optimization/112281 - loop distribution and zero dependence distancesRichard Biener3-4/+50
The following fixes an omission in dependence testing for loop distribution. When the overall dependence distance is not zero but the dependence direction in the innermost common loop is = there is a conflict between the partitions and we have to merge them. PR tree-optimization/112281 * tree-loop-distribution.cc (loop_distribution::pg_add_dependence_edges): For = in the innermost common loop record a partition conflict. * gcc.dg/torture/pr112281-1.c: New testcase. * gcc.dg/torture/pr112281-2.c: Likewise.
2023-11-20middle-end/112622 - convert and vector-to-floatRichard Biener5-11/+20
The following avoids ICEing when trying to convert a vector to a scalar float. PR middle-end/112622 * convert.cc (convert_to_real_1): Use element_precision where a vector type might appear. Provide specific diagnostic for unexpected vector argument. * gcc.dg/pr112622.c: New testcase. * gcc.dg/simd-2.c: Adjust. * gcc.target/i386/vect-bfloat16-typecheck_1.c: Likewise. * gcc.target/i386/vect-bfloat16-typecheck_2.c: Likewise.
2023-11-20RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32Juzhe-Zhong3-29/+17
This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax ICE: bug.c:10:1: error: unrecognizable insn: 10 | } | ^ (insn 10 9 11 2 (set (reg:V4SI 140) (unspec:V4SI [ (unspec:V4BI [ (const_vector:V4BI [ (const_int 1 [0x1]) repeated x4 ]) (const_int 4 [0x4]) (const_int 2 [0x2]) repeated x3 (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (unspec:V4SI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF) (subreg:V4SI (reg:V2DI 138 [ v ]) 0) (subreg:SI (reg/v:DI 136 [ b ]) 0) ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1 (nil)) The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI which is totally same as V4SI on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax. The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use get_vector_mode to get right mode. PR target/112597 gcc/ChangeLog: * config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE. * config/riscv/vector.md: Fix slide1 intermediate mode bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.
2023-11-20RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.Robin Dapp131-129/+2008
We currently allow 64-bit indices/offsets for vector indexed loads and stores even on rv32 but we should not. This patch adjusts the iterators as well as the insn conditions to reflect the RVV spec. It also fixes an oversight in the VLS modes of the demote iterator that was found while testing the patch. gcc/ChangeLog: * config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p): Add check for XLEN == 32. * config/riscv/vector-iterators.md: Change VLS part of the demote iterator to 2x elements modes * config/riscv/vector.md: Adjust iterators and insn conditions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c: New test.
2023-11-20arm: [MVE intrinsics] rework vldq1 vst1qChristophe Lyon5-287/+69
Implement vld1q, vst1q using the new MVE builtins framework. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q) (vst1_impl, vst1q): New. * config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New. * config/arm/arm-mve-builtins-base.h (vld1q, vst1q): New. * config/arm/arm_mve.h (vld1q): Delete. (vst1q): Delete. (vld1q_s8): Delete. (vld1q_s32): Delete. (vld1q_s16): Delete. (vld1q_u8): Delete. (vld1q_u32): Delete. (vld1q_u16): Delete. (vld1q_f32): Delete. (vld1q_f16): Delete. (vst1q_f32): Delete. (vst1q_f16): Delete. (vst1q_s8): Delete. (vst1q_s32): Delete. (vst1q_s16): Delete. (vst1q_u8): Delete. (vst1q_u32): Delete. (vst1q_u16): Delete. (__arm_vld1q_s8): Delete. (__arm_vld1q_s32): Delete. (__arm_vld1q_s16): Delete. (__arm_vld1q_u8): Delete. (__arm_vld1q_u32): Delete. (__arm_vld1q_u16): Delete. (__arm_vst1q_s8): Delete. (__arm_vst1q_s32): Delete. (__arm_vst1q_s16): Delete. (__arm_vst1q_u8): Delete. (__arm_vst1q_u32): Delete. (__arm_vst1q_u16): Delete. (__arm_vld1q_f32): Delete. (__arm_vld1q_f16): Delete. (__arm_vst1q_f32): Delete. (__arm_vst1q_f16): Delete. (__arm_vld1q): Delete. (__arm_vst1q): Delete. * config/arm/mve.md (mve_vld1q_f<mode>): Rename into ... (@mve_vld1q_f<mode>): ... this. (mve_vld1q_<supf><mode>): Rename into ... (@mve_vld1q_<supf><mode>) ... this. (mve_vst1q_f<mode>): Rename into ... (@mve_vst1q_f<mode>): ... this. (mve_vst1q_<supf><mode>): Rename into ... (@mve_vst1q_<supf><mode>) ... this.
2023-11-20arm: [MVE intrinsics] fix vst1 testsChristophe Lyon8-16/+16
vst1q intrinsics return void, so we should not do 'return vst1q_f16 (base, value);' This was OK so far, but will trigger an error/warning with the new implementation of these intrinsics. This patch just removes the 'return' keyword. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/mve/intrinsics/vst1q_f16.c: Remove 'return'. * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
2023-11-20arm: [MVE intrinsics] add load and store shapesChristophe Lyon2-0/+69
This patch adds the load and store shapes descriptions. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (load, store): New. * config/arm/arm-mve-builtins-shapes.h (load, store): New.
2023-11-20arm: [MVE intrinsics] Add support for contiguous loads and storesChristophe Lyon3-1/+199
This patch adds base support for load/store intrinsics to the framework, starting with loads and stores for contiguous memory elements, without extension nor truncation. Compared to the aarch64/SVE implementation, there's no support for gather/scatter loads/stores yet. This will be added later as needed. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-functions.h (multi_vector_function) (full_width_access): New classes. * config/arm/arm-mve-builtins.cc (find_type_suffix_for_scalar_type, infer_pointer_type) (require_pointer_type, get_contiguous_base, add_mem_operand) (add_fixed_operand, use_contiguous_load_insn) (use_contiguous_store_insn): New. * config/arm/arm-mve-builtins.h (memory_vector_mode) (infer_pointer_type, require_pointer_type, get_contiguous_base) (add_mem_operand) (add_fixed_operand, use_contiguous_load_insn) (use_contiguous_store_insn): New.
2023-11-20arm: [MVE intrinsics] Add support for void and load/store pointers as ↵Christophe Lyon2-0/+42
argument types. This patch adds support for '_', 'al' and 'as' for void, load pointer and store pointer argument/return value types in intrinsic signatures. It also adds a mew memory_scalar_type() helper to function_instance, which is used by 'al' and 'as'. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (build_const_pointer): New. (parse_type): Add support for '_', 'al' and 'as'. * config/arm/arm-mve-builtins.h (function_instance): Add memory_scalar_type. (function_base): Likewise.
2023-11-20arm: Fix arm_simd_types and MVE scalar_typesChristophe Lyon2-22/+22
So far we define arm_simd_types and scalar_types using type definitions like intSI_type_node, etc... This is causing problems with later patches which re-implement load/store MVE intrinsics, leading to error messages such as: error: passing argument 1 of 'vst1q_s32' from incompatible pointer type note: expected 'int *' but argument is of type 'int32_t *' {aka 'long int *'} This patch uses get_typenode_from_name (INT32_TYPE) instead, which defines the types as appropriate for the target/C library. 2023-11-16 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Fix initialization of arm_simd_types[].eltype. * config/arm/arm-mve-builtins.def (DEF_MVE_TYPE): Fix scalar types.
2023-11-20RISC-V Regression: Remove scalable compile optionJuzhe-Zhong1-1/+0
Since we already set scalable vectorization by default, this flag is redundant. Also, we are start to full coverage testing with different compile option. E.g --param=riscv-autovec-preference=fixed-vlmax. To avoid compile option confusion. Remove it. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Remove scalable compile option.
2023-11-20c, c++: Add new value for vector types for __builtin_classify_typeJakub Jelinek4-6/+19
While filing a clang request to return 18 on _BitInts for __builtin_classify_type instead of -1 they return currently, I've noticed that we return -1 for vector types. Initially I wanted to change behavior just for __builtin_classify_type (type) form, as that is new in GCC 14 and we've returned for 20+ years -1 for __builtin_classify_type on vector expressions, but I was convinved otherwise, so this changes the behavior even for that and now returns 19. 2023-11-20 Jakub Jelinek <jakub@redhat.com> gcc/ * typeclass.h (enum type_class): Add vector_type_class. * builtins.cc (type_to_class): Return vector_type_class for VECTOR_TYPE. * doc/extend.texi (__builtin_classify_type): Mention bit-precise integer types and vector types. gcc/testsuite/ * c-c++-common/builtin-classify-type-1.c (main): Add tests for vector types.
2023-11-20vect: Add bool pattern handling for COND_OPs.Robin Dapp2-8/+39
In order to handle masks properly for conditional operations this patch teaches vect_recog_mask_conversion_pattern to also handle conditional operations. Now we convert e.g. _mask = *_6; _ifc123 = COND_OP (_mask, ...); into _mask = *_6; patt200 = (<signed-boolean:1>) _mask; patt201 = COND_OP (patt200, ...); This way the mask will be properly recognized as boolean mask and the correct vector mask will be generated. gcc/ChangeLog: PR middle-end/112406 * tree-vect-patterns.cc (vect_recog_mask_conversion_pattern): Convert masks for conditional operations as well. gcc/testsuite/ChangeLog: * gfortran.dg/pr112406.f90: New test.
2023-11-20tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) ↵Jakub Jelinek4-2/+88
optimization for direct optab [PR90693] On Fri, Nov 17, 2023 at 03:01:04PM +0100, Jakub Jelinek wrote: > As a follow-up, I'm considering changing in this routine the popcount > call to IFN_POPCOUNT with 2 arguments and during expansion test costs. Here is the follow-up which does the rtx costs testing. 2023-11-20 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/90693 * tree-ssa-math-opts.cc (match_single_bit_test): Mark POPCOUNT with result only used in equality comparison against 1 with direct optab support as .POPCOUNT call with 2 arguments. * internal-fn.h (expand_POPCOUNT): Declare. * internal-fn.def (DEF_INTERNAL_INT_EXT_FN): New macro, document it, undefine at the end. (POPCOUNT): Use it instead of DEF_INTERNAL_INT_FN. * internal-fn.cc (DEF_INTERNAL_INT_EXT_FN): Define to nothing before inclusion to define expanders. (expand_POPCOUNT): New function.
2023-11-20tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) ↵Jakub Jelinek2-1/+104
optimization [PR90693] Per the earlier discussions on this PR, the following patch folds popcount (x) == 1 (and != 1) into (x ^ (x - 1)) > x - 1 (or <=) if the corresponding popcount optab isn't implemented (I think any double-word popcount or call will be necessarily slower than the above cheap 3 op check and even for -Os larger or same size). I've noticed e.g. C++ aligned new starts with std::has_single_bit which does popcount (x) == 1. As a follow-up, I'm considering changing in this routine the popcount call to IFN_POPCOUNT with 2 arguments and during expansion test costs. 2023-11-20 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/90693 * tree-ssa-math-opts.cc (match_single_bit_test): New function. (math_opts_dom_walker::after_dom_children): Call it for EQ_EXPR and NE_EXPR assignments and GIMPLE_CONDs. * gcc.target/i386/pr90693.c: New test.
2023-11-20internal-fn: Always undefine DEF_INTERNAL* macros at the end of internal-fn.defJakub Jelinek2-16/+6
I have noticed we are inconsistent, some DEF_INTERNAL* macros (most of them) were undefined at the end of internal-fn.def (but in some cases uselessly undefined again after inclusion), while others were not (and sometimes undefined after the inclusion). I've changed it to always undefine at the end of internal-fn.def. 2023-11-20 Jakub Jelinek <jakub@redhat.com> * internal-fn.def: Document missing DEF_INTERNAL* macros and make sure they are all undefined at the end. * internal-fn.cc (lookup_hilo_internal_fn, lookup_evenodd_internal_fn, widening_fn_p, get_len_internal_fn): Don't undef DEF_INTERNAL_*FN macros after inclusion of internal-fn.def.
2023-11-20testsuite: arm: fix arm_movt cut&pastoAlexandre Oliva1-1/+1
I got spurious fails of tests that required arm_thumb1_movt_ok on a target cpu that did not support movt. Looking into it, I found the arm_movt property to have been cut&pasted into other procs that checked for different properties. They shouldn't share the same test results cache entry, so I'm changing their prop names. Or rather its prop name, because the other occurrence was already fixed recently. for gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_arm_thumb1_cbz_ok): Fix prop name cut&pasto.
2023-11-20testsuite: analyzer: expect alignment warning with -fshort-enumsAlexandre Oliva2-2/+2
On targets that have -fshort-enums enabled by default, the type casts in the pr108251 analyzer tests warn that the byte-aligned enums may not be sufficiently aligned to be a struct connection *. The function can't know better, the warning is reasonable, the code doesn't expected enums to be shorter and less aligned than the struct. Rather than use -fno-short-enums, I decided to embrace the warning on targets that have short_enums enabled by default. However, C++ doesn't issue the warning, because even with -fshort-enums, enumeration types are not TYPE_PACKED, and the expression is not sufficiently simplified by the C++ front-end for check_and_warn_address_or_pointer_of_packed_member to identify the insufficiently aligned pointer. So don't expect the warning there. for gcc/testsuite/ChangeLog * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early-O2.c: Expect "unaligned pointer value" warning on short_enums targets, but not in c++. * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c: Likewise.
2023-11-20testsuite: scev: expect fail on ilp32Alexandre Oliva3-3/+6
I've recently patched scev-3.c and scev-5.c because it only passed by accident on ia32. It also fails on some (but not all) arm-eabi variants. It seems hard to characterize the conditions in which the optimization is supposed to pass, but expecting them to fail on ilp32 targets, though probably a little excessive and possibly noisy, is not quite as alarming as getting a fail in test reports, so I propose changing the xfail marker from ia32 to ilp32. I'm also proposing to add a similar marker to scev-4.c. Though it doesn't appear to be failing for me, I've got reports that suggest it still does for others, and it certainly did for us as well. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/scev-3.c: xfail on all ilp32 targets, though some of these do pass. * gcc.dg/tree-ssa/scev-4.c: Likewise. * gcc.dg/tree-ssa/scev-5.c: Likewise.
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